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radv: Move some helper functions to the radv_shader.h header file.
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
32 #include "nir/nir.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36 #include <llvm-c/Transforms/Scalar.h>
37 #include <llvm-c/Transforms/Utils.h>
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct radv_shader_context {
50 struct ac_llvm_context ac;
51 const struct nir_shader *shader;
52 struct ac_shader_abi abi;
53 const struct radv_shader_args *args;
54
55 gl_shader_stage stage;
56
57 unsigned max_workgroup_size;
58 LLVMContextRef context;
59 LLVMValueRef main_function;
60
61 LLVMValueRef descriptor_sets[MAX_SETS];
62
63 LLVMValueRef ring_offsets;
64
65 LLVMValueRef rel_auto_id;
66
67 LLVMValueRef gs_wave_id;
68 LLVMValueRef gs_vtx_offset[6];
69
70 LLVMValueRef esgs_ring;
71 LLVMValueRef gsvs_ring[4];
72 LLVMValueRef hs_ring_tess_offchip;
73 LLVMValueRef hs_ring_tess_factor;
74
75 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
76
77 uint64_t output_mask;
78
79 LLVMValueRef gs_next_vertex[4];
80 LLVMValueRef gs_curprim_verts[4];
81 LLVMValueRef gs_generated_prims[4];
82 LLVMValueRef gs_ngg_emit;
83 LLVMValueRef gs_ngg_scratch;
84
85 uint32_t tcs_num_inputs;
86 uint32_t tcs_num_patches;
87
88 LLVMValueRef vertexptr; /* GFX10 only */
89 };
90
91 struct radv_shader_output_values {
92 LLVMValueRef values[4];
93 unsigned slot_name;
94 unsigned slot_index;
95 unsigned usage_mask;
96 };
97
98 static inline struct radv_shader_context *
99 radv_shader_context_from_abi(struct ac_shader_abi *abi)
100 {
101 struct radv_shader_context *ctx = NULL;
102 return container_of(abi, ctx, abi);
103 }
104
105 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
106 {
107 switch (ctx->stage) {
108 case MESA_SHADER_TESS_CTRL:
109 return ac_unpack_param(&ctx->ac,
110 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
111 0, 8);
112 case MESA_SHADER_TESS_EVAL:
113 return ac_get_arg(&ctx->ac, ctx->args->tes_rel_patch_id);
114 break;
115 default:
116 unreachable("Illegal stage");
117 }
118 }
119
120 /* Tessellation shaders pass outputs to the next shader using LDS.
121 *
122 * LS outputs = TCS inputs
123 * TCS outputs = TES inputs
124 *
125 * The LDS layout is:
126 * - TCS inputs for patch 0
127 * - TCS inputs for patch 1
128 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
129 * - ...
130 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
131 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
132 * - TCS outputs for patch 1
133 * - Per-patch TCS outputs for patch 1
134 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
135 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
136 * - ...
137 *
138 * All three shaders VS(LS), TCS, TES share the same LDS space.
139 */
140 static LLVMValueRef
141 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
142 {
143 assert(ctx->stage == MESA_SHADER_TESS_CTRL);
144 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
145 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
146
147 input_patch_size /= 4;
148 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
149 }
150
151 static LLVMValueRef
152 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
153 {
154 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
155 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
156 uint32_t output_vertex_size = num_tcs_outputs * 16;
157 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
158 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
159 output_patch_size /= 4;
160 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
161 }
162
163 static LLVMValueRef
164 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
165 {
166 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
167 uint32_t output_vertex_size = num_tcs_outputs * 16;
168 output_vertex_size /= 4;
169 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
170 }
171
172 static LLVMValueRef
173 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
174 {
175 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
176 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
177 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
178 uint32_t output_patch0_offset = input_patch_size;
179 unsigned num_patches = ctx->tcs_num_patches;
180
181 output_patch0_offset *= num_patches;
182 output_patch0_offset /= 4;
183 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
184 }
185
186 static LLVMValueRef
187 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
188 {
189 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
190 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
191 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
192 uint32_t output_patch0_offset = input_patch_size;
193
194 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
195 uint32_t output_vertex_size = num_tcs_outputs * 16;
196 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
197 unsigned num_patches = ctx->tcs_num_patches;
198
199 output_patch0_offset *= num_patches;
200 output_patch0_offset += pervertex_output_patch_size;
201 output_patch0_offset /= 4;
202 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
203 }
204
205 static LLVMValueRef
206 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
207 {
208 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
209 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
210
211 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
212 }
213
214 static LLVMValueRef
215 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
216 {
217 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
218 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
219 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
220
221 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
222 patch0_offset);
223 }
224
225 static LLVMValueRef
226 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
227 {
228 LLVMValueRef patch0_patch_data_offset =
229 get_tcs_out_patch0_patch_data_offset(ctx);
230 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
231 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
232
233 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
234 patch0_patch_data_offset);
235 }
236
237 static LLVMValueRef
238 create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module,
239 LLVMBuilderRef builder,
240 const struct ac_shader_args *args,
241 enum ac_llvm_calling_convention convention,
242 unsigned max_workgroup_size,
243 const struct radv_nir_compiler_options *options)
244 {
245 LLVMValueRef main_function =
246 ac_build_main(args, ctx, convention, "main", ctx->voidt, module);
247
248 if (options->address32_hi) {
249 ac_llvm_add_target_dep_function_attr(main_function,
250 "amdgpu-32bit-address-high-bits",
251 options->address32_hi);
252 }
253
254 ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
255
256 return main_function;
257 }
258
259 static void
260 load_descriptor_sets(struct radv_shader_context *ctx)
261 {
262 uint32_t mask = ctx->args->shader_info->desc_set_used_mask;
263 if (ctx->args->shader_info->need_indirect_descriptor_sets) {
264 LLVMValueRef desc_sets =
265 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[0]);
266 while (mask) {
267 int i = u_bit_scan(&mask);
268
269 ctx->descriptor_sets[i] =
270 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
271 LLVMConstInt(ctx->ac.i32, i, false));
272
273 }
274 } else {
275 while (mask) {
276 int i = u_bit_scan(&mask);
277
278 ctx->descriptor_sets[i] =
279 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[i]);
280 }
281 }
282 }
283
284 static enum ac_llvm_calling_convention
285 get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage)
286 {
287 switch (stage) {
288 case MESA_SHADER_VERTEX:
289 case MESA_SHADER_TESS_EVAL:
290 return AC_LLVM_AMDGPU_VS;
291 break;
292 case MESA_SHADER_GEOMETRY:
293 return AC_LLVM_AMDGPU_GS;
294 break;
295 case MESA_SHADER_TESS_CTRL:
296 return AC_LLVM_AMDGPU_HS;
297 break;
298 case MESA_SHADER_FRAGMENT:
299 return AC_LLVM_AMDGPU_PS;
300 break;
301 case MESA_SHADER_COMPUTE:
302 return AC_LLVM_AMDGPU_CS;
303 break;
304 default:
305 unreachable("Unhandle shader type");
306 }
307 }
308
309 /* Returns whether the stage is a stage that can be directly before the GS */
310 static bool is_pre_gs_stage(gl_shader_stage stage)
311 {
312 return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
313 }
314
315 static void create_function(struct radv_shader_context *ctx,
316 gl_shader_stage stage,
317 bool has_previous_stage)
318 {
319 if (ctx->ac.chip_class >= GFX10) {
320 if (is_pre_gs_stage(stage) && ctx->args->options->key.vs_common_out.as_ngg) {
321 /* On GFX10, VS is merged into GS for NGG. */
322 stage = MESA_SHADER_GEOMETRY;
323 has_previous_stage = true;
324 }
325 }
326
327 ctx->main_function = create_llvm_function(
328 &ctx->ac, ctx->ac.module, ctx->ac.builder, &ctx->args->ac,
329 get_llvm_calling_convention(ctx->main_function, stage),
330 ctx->max_workgroup_size,
331 ctx->args->options);
332
333 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
334 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
335 NULL, 0, AC_FUNC_ATTR_READNONE);
336 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
337 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
338
339 load_descriptor_sets(ctx);
340
341 if (stage == MESA_SHADER_TESS_CTRL ||
342 (stage == MESA_SHADER_VERTEX && ctx->args->options->key.vs_common_out.as_ls) ||
343 /* GFX9 has the ESGS ring buffer in LDS. */
344 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
345 ac_declare_lds_as_pointer(&ctx->ac);
346 }
347
348 }
349
350
351 static LLVMValueRef
352 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
353 unsigned desc_set, unsigned binding)
354 {
355 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
356 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
357 struct radv_pipeline_layout *pipeline_layout = ctx->args->options->layout;
358 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
359 unsigned base_offset = layout->binding[binding].offset;
360 LLVMValueRef offset, stride;
361
362 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
363 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
364 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
365 layout->binding[binding].dynamic_offset_offset;
366 desc_ptr = ac_get_arg(&ctx->ac, ctx->args->ac.push_constants);
367 base_offset = pipeline_layout->push_constant_size + 16 * idx;
368 stride = LLVMConstInt(ctx->ac.i32, 16, false);
369 } else
370 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
371
372 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
373
374 if (layout->binding[binding].type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
375 offset = ac_build_imad(&ctx->ac, index, stride, offset);
376 }
377
378 desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
379 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
380 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
381
382 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
383 uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
384 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
385 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
386 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
387
388 if (ctx->ac.chip_class >= GFX10) {
389 desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
390 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
391 S_008F0C_RESOURCE_LEVEL(1);
392 } else {
393 desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
394 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
395 }
396
397 LLVMValueRef desc_components[4] = {
398 LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
399 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->args->options->address32_hi), false),
400 /* High limit to support variable sizes. */
401 LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
402 LLVMConstInt(ctx->ac.i32, desc_type, false),
403 };
404
405 return ac_build_gather_values(&ctx->ac, desc_components, 4);
406 }
407
408 return desc_ptr;
409 }
410
411
412 /* The offchip buffer layout for TCS->TES is
413 *
414 * - attribute 0 of patch 0 vertex 0
415 * - attribute 0 of patch 0 vertex 1
416 * - attribute 0 of patch 0 vertex 2
417 * ...
418 * - attribute 0 of patch 1 vertex 0
419 * - attribute 0 of patch 1 vertex 1
420 * ...
421 * - attribute 1 of patch 0 vertex 0
422 * - attribute 1 of patch 0 vertex 1
423 * ...
424 * - per patch attribute 0 of patch 0
425 * - per patch attribute 0 of patch 1
426 * ...
427 *
428 * Note that every attribute has 4 components.
429 */
430 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
431 {
432 uint32_t num_patches = ctx->tcs_num_patches;
433 uint32_t num_tcs_outputs;
434 if (ctx->stage == MESA_SHADER_TESS_CTRL)
435 num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
436 else
437 num_tcs_outputs = ctx->args->options->key.tes.tcs_num_outputs;
438
439 uint32_t output_vertex_size = num_tcs_outputs * 16;
440 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
441
442 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
443 }
444
445 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
446 LLVMValueRef vertex_index)
447 {
448 LLVMValueRef param_stride;
449 if (vertex_index)
450 param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
451 else
452 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
453 return param_stride;
454 }
455
456 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
457 LLVMValueRef vertex_index,
458 LLVMValueRef param_index)
459 {
460 LLVMValueRef base_addr;
461 LLVMValueRef param_stride, constant16;
462 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
463 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
464 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
465 param_stride = calc_param_stride(ctx, vertex_index);
466 if (vertex_index) {
467 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
468 vertices_per_patch, vertex_index);
469 } else {
470 base_addr = rel_patch_id;
471 }
472
473 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
474 LLVMBuildMul(ctx->ac.builder, param_index,
475 param_stride, ""), "");
476
477 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
478
479 if (!vertex_index) {
480 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
481
482 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
483 patch_data_offset, "");
484 }
485 return base_addr;
486 }
487
488 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
489 unsigned param,
490 unsigned const_index,
491 bool is_compact,
492 LLVMValueRef vertex_index,
493 LLVMValueRef indir_index)
494 {
495 LLVMValueRef param_index;
496
497 if (indir_index)
498 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
499 indir_index, "");
500 else {
501 if (const_index && !is_compact)
502 param += const_index;
503 param_index = LLVMConstInt(ctx->ac.i32, param, false);
504 }
505 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
506 }
507
508 static LLVMValueRef
509 get_dw_address(struct radv_shader_context *ctx,
510 LLVMValueRef dw_addr,
511 unsigned param,
512 unsigned const_index,
513 bool compact_const_index,
514 LLVMValueRef vertex_index,
515 LLVMValueRef stride,
516 LLVMValueRef indir_index)
517
518 {
519
520 if (vertex_index) {
521 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
522 LLVMBuildMul(ctx->ac.builder,
523 vertex_index,
524 stride, ""), "");
525 }
526
527 if (indir_index)
528 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
529 LLVMBuildMul(ctx->ac.builder, indir_index,
530 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
531 else if (const_index && !compact_const_index)
532 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
533 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
534
535 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
536 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
537
538 if (const_index && compact_const_index)
539 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
540 LLVMConstInt(ctx->ac.i32, const_index, false), "");
541 return dw_addr;
542 }
543
544 static LLVMValueRef
545 load_tcs_varyings(struct ac_shader_abi *abi,
546 LLVMTypeRef type,
547 LLVMValueRef vertex_index,
548 LLVMValueRef indir_index,
549 unsigned const_index,
550 unsigned location,
551 unsigned driver_location,
552 unsigned component,
553 unsigned num_components,
554 bool is_patch,
555 bool is_compact,
556 bool load_input)
557 {
558 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
559 LLVMValueRef dw_addr, stride;
560 LLVMValueRef value[4], result;
561 unsigned param = shader_io_get_unique_index(location);
562
563 if (load_input) {
564 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
565 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
566 dw_addr = get_tcs_in_current_patch_offset(ctx);
567 } else {
568 if (!is_patch) {
569 stride = get_tcs_out_vertex_stride(ctx);
570 dw_addr = get_tcs_out_current_patch_offset(ctx);
571 } else {
572 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
573 stride = NULL;
574 }
575 }
576
577 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
578 indir_index);
579
580 for (unsigned i = 0; i < num_components + component; i++) {
581 value[i] = ac_lds_load(&ctx->ac, dw_addr);
582 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
583 ctx->ac.i32_1, "");
584 }
585 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
586 return result;
587 }
588
589 static void
590 store_tcs_output(struct ac_shader_abi *abi,
591 const nir_variable *var,
592 LLVMValueRef vertex_index,
593 LLVMValueRef param_index,
594 unsigned const_index,
595 LLVMValueRef src,
596 unsigned writemask)
597 {
598 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
599 const unsigned location = var->data.location;
600 unsigned component = var->data.location_frac;
601 const bool is_patch = var->data.patch;
602 const bool is_compact = var->data.compact;
603 LLVMValueRef dw_addr;
604 LLVMValueRef stride = NULL;
605 LLVMValueRef buf_addr = NULL;
606 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
607 unsigned param;
608 bool store_lds = true;
609
610 if (is_patch) {
611 if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
612 store_lds = false;
613 } else {
614 if (!(ctx->shader->info.outputs_read & (1ULL << location)))
615 store_lds = false;
616 }
617
618 param = shader_io_get_unique_index(location);
619 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
620 const_index += component;
621 component = 0;
622
623 if (const_index >= 4) {
624 const_index -= 4;
625 param++;
626 }
627 }
628
629 if (!is_patch) {
630 stride = get_tcs_out_vertex_stride(ctx);
631 dw_addr = get_tcs_out_current_patch_offset(ctx);
632 } else {
633 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
634 }
635
636 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
637 param_index);
638 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
639 vertex_index, param_index);
640
641 bool is_tess_factor = false;
642 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
643 location == VARYING_SLOT_TESS_LEVEL_OUTER)
644 is_tess_factor = true;
645
646 unsigned base = is_compact ? const_index : 0;
647 for (unsigned chan = 0; chan < 8; chan++) {
648 if (!(writemask & (1 << chan)))
649 continue;
650 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
651 value = ac_to_integer(&ctx->ac, value);
652 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
653
654 if (store_lds || is_tess_factor) {
655 LLVMValueRef dw_addr_chan =
656 LLVMBuildAdd(ctx->ac.builder, dw_addr,
657 LLVMConstInt(ctx->ac.i32, chan, false), "");
658 ac_lds_store(&ctx->ac, dw_addr_chan, value);
659 }
660
661 if (!is_tess_factor && writemask != 0xF)
662 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
663 buf_addr, oc_lds,
664 4 * (base + chan), ac_glc);
665 }
666
667 if (writemask == 0xF) {
668 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
669 buf_addr, oc_lds,
670 (base * 4), ac_glc);
671 }
672 }
673
674 static LLVMValueRef
675 load_tes_input(struct ac_shader_abi *abi,
676 LLVMTypeRef type,
677 LLVMValueRef vertex_index,
678 LLVMValueRef param_index,
679 unsigned const_index,
680 unsigned location,
681 unsigned driver_location,
682 unsigned component,
683 unsigned num_components,
684 bool is_patch,
685 bool is_compact,
686 bool load_input)
687 {
688 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
689 LLVMValueRef buf_addr;
690 LLVMValueRef result;
691 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
692 unsigned param = shader_io_get_unique_index(location);
693
694 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
695 const_index += component;
696 component = 0;
697 if (const_index >= 4) {
698 const_index -= 4;
699 param++;
700 }
701 }
702
703 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
704 is_compact, vertex_index, param_index);
705
706 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
707 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
708
709 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
710 buf_addr, oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
711 result = ac_trim_vector(&ctx->ac, result, num_components);
712 return result;
713 }
714
715 static LLVMValueRef
716 radv_emit_fetch_64bit(struct radv_shader_context *ctx,
717 LLVMTypeRef type, LLVMValueRef a, LLVMValueRef b)
718 {
719 LLVMValueRef values[2] = {
720 ac_to_integer(&ctx->ac, a),
721 ac_to_integer(&ctx->ac, b),
722 };
723 LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
724 return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
725 }
726
727 static LLVMValueRef
728 load_gs_input(struct ac_shader_abi *abi,
729 unsigned location,
730 unsigned driver_location,
731 unsigned component,
732 unsigned num_components,
733 unsigned vertex_index,
734 unsigned const_index,
735 LLVMTypeRef type)
736 {
737 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
738 LLVMValueRef vtx_offset;
739 unsigned param, vtx_offset_param;
740 LLVMValueRef value[4], result;
741
742 vtx_offset_param = vertex_index;
743 assert(vtx_offset_param < 6);
744 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
745 LLVMConstInt(ctx->ac.i32, 4, false), "");
746
747 param = shader_io_get_unique_index(location);
748
749 for (unsigned i = component; i < num_components + component; i++) {
750 if (ctx->ac.chip_class >= GFX9) {
751 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
752 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
753 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
754 value[i] = ac_lds_load(&ctx->ac, dw_addr);
755
756 if (ac_get_type_size(type) == 8) {
757 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
758 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index + 1, 0), "");
759 LLVMValueRef tmp = ac_lds_load(&ctx->ac, dw_addr);
760
761 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
762 }
763 } else {
764 LLVMValueRef soffset =
765 LLVMConstInt(ctx->ac.i32,
766 (param * 4 + i + const_index) * 256,
767 false);
768
769 value[i] = ac_build_buffer_load(&ctx->ac,
770 ctx->esgs_ring, 1,
771 ctx->ac.i32_0,
772 vtx_offset, soffset,
773 0, ac_glc, true, false);
774
775 if (ac_get_type_size(type) == 8) {
776 soffset = LLVMConstInt(ctx->ac.i32,
777 (param * 4 + i + const_index + 1) * 256,
778 false);
779
780 LLVMValueRef tmp =
781 ac_build_buffer_load(&ctx->ac,
782 ctx->esgs_ring, 1,
783 ctx->ac.i32_0,
784 vtx_offset, soffset,
785 0, ac_glc, true, false);
786
787 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
788 }
789 }
790
791 if (ac_get_type_size(type) == 2) {
792 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
793 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
794 }
795 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
796 }
797 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
798 result = ac_to_integer(&ctx->ac, result);
799 return result;
800 }
801
802 static uint32_t
803 radv_get_sample_pos_offset(uint32_t num_samples)
804 {
805 uint32_t sample_pos_offset = 0;
806
807 switch (num_samples) {
808 case 2:
809 sample_pos_offset = 1;
810 break;
811 case 4:
812 sample_pos_offset = 3;
813 break;
814 case 8:
815 sample_pos_offset = 7;
816 break;
817 default:
818 break;
819 }
820 return sample_pos_offset;
821 }
822
823 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
824 LLVMValueRef sample_id)
825 {
826 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
827
828 LLVMValueRef result;
829 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false);
830 LLVMValueRef ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ring_offsets, &index, 1, "");
831
832 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
833 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
834
835 uint32_t sample_pos_offset =
836 radv_get_sample_pos_offset(ctx->args->options->key.fs.num_samples);
837
838 sample_id =
839 LLVMBuildAdd(ctx->ac.builder, sample_id,
840 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
841 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
842
843 return result;
844 }
845
846
847 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
848 {
849 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
850 uint8_t log2_ps_iter_samples;
851
852 if (ctx->args->shader_info->ps.force_persample) {
853 log2_ps_iter_samples =
854 util_logbase2(ctx->args->options->key.fs.num_samples);
855 } else {
856 log2_ps_iter_samples = ctx->args->options->key.fs.log2_ps_iter_samples;
857 }
858
859 /* The bit pattern matches that used by fixed function fragment
860 * processing. */
861 static const uint16_t ps_iter_masks[] = {
862 0xffff, /* not used */
863 0x5555,
864 0x1111,
865 0x0101,
866 0x0001,
867 };
868 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
869
870 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
871
872 LLVMValueRef result, sample_id;
873 sample_id = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.ancillary), 8, 4);
874 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
875 result = LLVMBuildAnd(ctx->ac.builder, sample_id,
876 ac_get_arg(&ctx->ac, ctx->args->ac.sample_coverage), "");
877 return result;
878 }
879
880
881 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
882 unsigned stream,
883 LLVMValueRef *addrs);
884
885 static void
886 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
887 {
888 LLVMValueRef gs_next_vertex;
889 LLVMValueRef can_emit;
890 unsigned offset = 0;
891 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
892
893 if (ctx->args->options->key.vs_common_out.as_ngg) {
894 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
895 return;
896 }
897
898 /* Write vertex attribute values to GSVS ring */
899 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
900 ctx->gs_next_vertex[stream],
901 "");
902
903 /* If this thread has already emitted the declared maximum number of
904 * vertices, don't emit any more: excessive vertex emissions are not
905 * supposed to have any effect.
906 */
907 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
908 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
909
910 bool use_kill = !ctx->args->shader_info->gs.writes_memory;
911 if (use_kill)
912 ac_build_kill_if_false(&ctx->ac, can_emit);
913 else
914 ac_build_ifcc(&ctx->ac, can_emit, 6505);
915
916 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
917 unsigned output_usage_mask =
918 ctx->args->shader_info->gs.output_usage_mask[i];
919 uint8_t output_stream =
920 ctx->args->shader_info->gs.output_streams[i];
921 LLVMValueRef *out_ptr = &addrs[i * 4];
922 int length = util_last_bit(output_usage_mask);
923
924 if (!(ctx->output_mask & (1ull << i)) ||
925 output_stream != stream)
926 continue;
927
928 for (unsigned j = 0; j < length; j++) {
929 if (!(output_usage_mask & (1 << j)))
930 continue;
931
932 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
933 out_ptr[j], "");
934 LLVMValueRef voffset =
935 LLVMConstInt(ctx->ac.i32, offset *
936 ctx->shader->info.gs.vertices_out, false);
937
938 offset++;
939
940 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
941 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
942
943 out_val = ac_to_integer(&ctx->ac, out_val);
944 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
945
946 ac_build_buffer_store_dword(&ctx->ac,
947 ctx->gsvs_ring[stream],
948 out_val, 1,
949 voffset,
950 ac_get_arg(&ctx->ac,
951 ctx->args->gs2vs_offset),
952 0, ac_glc | ac_slc | ac_swizzled);
953 }
954 }
955
956 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
957 ctx->ac.i32_1, "");
958 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
959
960 ac_build_sendmsg(&ctx->ac,
961 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
962 ctx->gs_wave_id);
963
964 if (!use_kill)
965 ac_build_endif(&ctx->ac, 6505);
966 }
967
968 static void
969 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
970 {
971 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
972
973 if (ctx->args->options->key.vs_common_out.as_ngg) {
974 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
975 return;
976 }
977
978 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
979 }
980
981 static LLVMValueRef
982 load_tess_coord(struct ac_shader_abi *abi)
983 {
984 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
985
986 LLVMValueRef coord[4] = {
987 ac_get_arg(&ctx->ac, ctx->args->tes_u),
988 ac_get_arg(&ctx->ac, ctx->args->tes_v),
989 ctx->ac.f32_0,
990 ctx->ac.f32_0,
991 };
992
993 if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
994 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
995 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
996
997 return ac_build_gather_values(&ctx->ac, coord, 3);
998 }
999
1000 static LLVMValueRef
1001 load_patch_vertices_in(struct ac_shader_abi *abi)
1002 {
1003 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1004 return LLVMConstInt(ctx->ac.i32, ctx->args->options->key.tcs.input_vertices, false);
1005 }
1006
1007
1008 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1009 {
1010 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1011 return ac_get_arg(&ctx->ac, ctx->args->ac.base_vertex);
1012 }
1013
1014 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1015 LLVMValueRef buffer_ptr, bool write)
1016 {
1017 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1018 LLVMValueRef result;
1019
1020 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1021
1022 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1023 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1024
1025 return result;
1026 }
1027
1028 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1029 {
1030 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1031 LLVMValueRef result;
1032
1033 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr)) != LLVMPointerTypeKind) {
1034 /* Do not load the descriptor for inlined uniform blocks. */
1035 return buffer_ptr;
1036 }
1037
1038 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1039
1040 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1041 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1042
1043 return result;
1044 }
1045
1046 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1047 unsigned descriptor_set,
1048 unsigned base_index,
1049 unsigned constant_index,
1050 LLVMValueRef index,
1051 enum ac_descriptor_type desc_type,
1052 bool image, bool write,
1053 bool bindless)
1054 {
1055 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1056 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1057 struct radv_descriptor_set_layout *layout = ctx->args->options->layout->set[descriptor_set].layout;
1058 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1059 unsigned offset = binding->offset;
1060 unsigned stride = binding->size;
1061 unsigned type_size;
1062 LLVMBuilderRef builder = ctx->ac.builder;
1063 LLVMTypeRef type;
1064
1065 assert(base_index < layout->binding_count);
1066
1067 switch (desc_type) {
1068 case AC_DESC_IMAGE:
1069 type = ctx->ac.v8i32;
1070 type_size = 32;
1071 break;
1072 case AC_DESC_FMASK:
1073 type = ctx->ac.v8i32;
1074 offset += 32;
1075 type_size = 32;
1076 break;
1077 case AC_DESC_SAMPLER:
1078 type = ctx->ac.v4i32;
1079 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
1080 offset += radv_combined_image_descriptor_sampler_offset(binding);
1081 }
1082
1083 type_size = 16;
1084 break;
1085 case AC_DESC_BUFFER:
1086 type = ctx->ac.v4i32;
1087 type_size = 16;
1088 break;
1089 case AC_DESC_PLANE_0:
1090 case AC_DESC_PLANE_1:
1091 case AC_DESC_PLANE_2:
1092 type = ctx->ac.v8i32;
1093 type_size = 32;
1094 offset += 32 * (desc_type - AC_DESC_PLANE_0);
1095 break;
1096 default:
1097 unreachable("invalid desc_type\n");
1098 }
1099
1100 offset += constant_index * stride;
1101
1102 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1103 (!index || binding->immutable_samplers_equal)) {
1104 if (binding->immutable_samplers_equal)
1105 constant_index = 0;
1106
1107 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1108
1109 LLVMValueRef constants[] = {
1110 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1111 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1112 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1113 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1114 };
1115 return ac_build_gather_values(&ctx->ac, constants, 4);
1116 }
1117
1118 assert(stride % type_size == 0);
1119
1120 LLVMValueRef adjusted_index = index;
1121 if (!adjusted_index)
1122 adjusted_index = ctx->ac.i32_0;
1123
1124 adjusted_index = LLVMBuildMul(builder, adjusted_index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1125
1126 LLVMValueRef val_offset = LLVMConstInt(ctx->ac.i32, offset, 0);
1127 list = LLVMBuildGEP(builder, list, &val_offset, 1, "");
1128 list = LLVMBuildPointerCast(builder, list,
1129 ac_array_in_const32_addr_space(type), "");
1130
1131 LLVMValueRef descriptor = ac_build_load_to_sgpr(&ctx->ac, list, adjusted_index);
1132
1133 /* 3 plane formats always have same size and format for plane 1 & 2, so
1134 * use the tail from plane 1 so that we can store only the first 16 bytes
1135 * of the last plane. */
1136 if (desc_type == AC_DESC_PLANE_2) {
1137 LLVMValueRef descriptor2 = radv_get_sampler_desc(abi, descriptor_set, base_index, constant_index, index, AC_DESC_PLANE_1,image, write, bindless);
1138
1139 LLVMValueRef components[8];
1140 for (unsigned i = 0; i < 4; ++i)
1141 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor, i);
1142
1143 for (unsigned i = 4; i < 8; ++i)
1144 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor2, i);
1145 descriptor = ac_build_gather_values(&ctx->ac, components, 8);
1146 }
1147
1148 return descriptor;
1149 }
1150
1151 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1152 * so we may need to fix it up. */
1153 static LLVMValueRef
1154 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1155 unsigned adjustment,
1156 LLVMValueRef alpha)
1157 {
1158 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1159 return alpha;
1160
1161 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1162
1163 alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
1164
1165 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1166 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1167 else
1168 alpha = ac_to_integer(&ctx->ac, alpha);
1169
1170 /* For the integer-like cases, do a natural sign extension.
1171 *
1172 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1173 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1174 * exponent.
1175 */
1176 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1177 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1178 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1179 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1180
1181 /* Convert back to the right type. */
1182 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1183 LLVMValueRef clamp;
1184 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1185 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1186 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1187 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1188 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1189 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1190 }
1191
1192 return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
1193 }
1194
1195 static LLVMValueRef
1196 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
1197 LLVMValueRef value,
1198 unsigned num_channels,
1199 bool is_float)
1200 {
1201 LLVMValueRef zero = is_float ? ctx->ac.f32_0 : ctx->ac.i32_0;
1202 LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
1203 LLVMValueRef chan[4];
1204
1205 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
1206 unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
1207
1208 if (num_channels == 4 && num_channels == vec_size)
1209 return value;
1210
1211 num_channels = MIN2(num_channels, vec_size);
1212
1213 for (unsigned i = 0; i < num_channels; i++)
1214 chan[i] = ac_llvm_extract_elem(&ctx->ac, value, i);
1215 } else {
1216 assert(num_channels == 1);
1217 chan[0] = value;
1218 }
1219
1220 for (unsigned i = num_channels; i < 4; i++) {
1221 chan[i] = i == 3 ? one : zero;
1222 chan[i] = ac_to_integer(&ctx->ac, chan[i]);
1223 }
1224
1225 return ac_build_gather_values(&ctx->ac, chan, 4);
1226 }
1227
1228 static void
1229 handle_vs_input_decl(struct radv_shader_context *ctx,
1230 struct nir_variable *variable)
1231 {
1232 LLVMValueRef t_list_ptr = ac_get_arg(&ctx->ac, ctx->args->vertex_buffers);
1233 LLVMValueRef t_offset;
1234 LLVMValueRef t_list;
1235 LLVMValueRef input;
1236 LLVMValueRef buffer_index;
1237 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1238 uint8_t input_usage_mask =
1239 ctx->args->shader_info->vs.input_usage_mask[variable->data.location];
1240 unsigned num_input_channels = util_last_bit(input_usage_mask);
1241
1242 variable->data.driver_location = variable->data.location * 4;
1243
1244 enum glsl_base_type type = glsl_get_base_type(variable->type);
1245 for (unsigned i = 0; i < attrib_count; ++i) {
1246 LLVMValueRef output[4];
1247 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1248 unsigned attrib_format = ctx->args->options->key.vs.vertex_attribute_formats[attrib_index];
1249 unsigned data_format = attrib_format & 0x0f;
1250 unsigned num_format = (attrib_format >> 4) & 0x07;
1251 bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
1252 num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
1253
1254 if (ctx->args->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1255 uint32_t divisor = ctx->args->options->key.vs.instance_rate_divisors[attrib_index];
1256
1257 if (divisor) {
1258 buffer_index = ctx->abi.instance_id;
1259
1260 if (divisor != 1) {
1261 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1262 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1263 }
1264 } else {
1265 buffer_index = ctx->ac.i32_0;
1266 }
1267
1268 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1269 ac_get_arg(&ctx->ac,
1270 ctx->args->ac.start_instance),\
1271 buffer_index, "");
1272 } else {
1273 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1274 ctx->abi.vertex_id,
1275 ac_get_arg(&ctx->ac,
1276 ctx->args->ac.base_vertex), "");
1277 }
1278
1279 const struct ac_data_format_info *vtx_info = ac_get_data_format_info(data_format);
1280
1281 /* Adjust the number of channels to load based on the vertex
1282 * attribute format.
1283 */
1284 unsigned num_channels = MIN2(num_input_channels, vtx_info->num_channels);
1285 unsigned attrib_binding = ctx->args->options->key.vs.vertex_attribute_bindings[attrib_index];
1286 unsigned attrib_offset = ctx->args->options->key.vs.vertex_attribute_offsets[attrib_index];
1287 unsigned attrib_stride = ctx->args->options->key.vs.vertex_attribute_strides[attrib_index];
1288
1289 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1290 /* Always load, at least, 3 channels for formats that
1291 * need to be shuffled because X<->Z.
1292 */
1293 num_channels = MAX2(num_channels, 3);
1294 }
1295
1296 t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false);
1297 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1298
1299 /* Perform per-channel vertex fetch operations if unaligned
1300 * access are detected. Only GFX6 and GFX10 are affected.
1301 */
1302 bool unaligned_vertex_fetches = false;
1303 if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class == GFX10) &&
1304 vtx_info->chan_format != data_format &&
1305 ((attrib_offset % vtx_info->element_size) ||
1306 (attrib_stride % vtx_info->element_size)))
1307 unaligned_vertex_fetches = true;
1308
1309 if (unaligned_vertex_fetches) {
1310 unsigned chan_format = vtx_info->chan_format;
1311 LLVMValueRef values[4];
1312
1313 assert(ctx->ac.chip_class == GFX6 ||
1314 ctx->ac.chip_class == GFX10);
1315
1316 for (unsigned chan = 0; chan < num_channels; chan++) {
1317 unsigned chan_offset = attrib_offset + chan * vtx_info->chan_byte_size;
1318 LLVMValueRef chan_index = buffer_index;
1319
1320 if (attrib_stride != 0 && chan_offset > attrib_stride) {
1321 LLVMValueRef buffer_offset =
1322 LLVMConstInt(ctx->ac.i32,
1323 chan_offset / attrib_stride, false);
1324
1325 chan_index = LLVMBuildAdd(ctx->ac.builder,
1326 buffer_index,
1327 buffer_offset, "");
1328
1329 chan_offset = chan_offset % attrib_stride;
1330 }
1331
1332 values[chan] = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1333 chan_index,
1334 LLVMConstInt(ctx->ac.i32, chan_offset, false),
1335 ctx->ac.i32_0, ctx->ac.i32_0, 1,
1336 chan_format, num_format, 0, true);
1337 }
1338
1339 input = ac_build_gather_values(&ctx->ac, values, num_channels);
1340 } else {
1341 if (attrib_stride != 0 && attrib_offset > attrib_stride) {
1342 LLVMValueRef buffer_offset =
1343 LLVMConstInt(ctx->ac.i32,
1344 attrib_offset / attrib_stride, false);
1345
1346 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1347 buffer_index,
1348 buffer_offset, "");
1349
1350 attrib_offset = attrib_offset % attrib_stride;
1351 }
1352
1353 input = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1354 buffer_index,
1355 LLVMConstInt(ctx->ac.i32, attrib_offset, false),
1356 ctx->ac.i32_0, ctx->ac.i32_0,
1357 num_channels,
1358 data_format, num_format, 0, true);
1359 }
1360
1361 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1362 LLVMValueRef c[4];
1363 c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
1364 c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
1365 c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
1366 c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
1367
1368 input = ac_build_gather_values(&ctx->ac, c, 4);
1369 }
1370
1371 input = radv_fixup_vertex_input_fetches(ctx, input, num_channels,
1372 is_float);
1373
1374 for (unsigned chan = 0; chan < 4; chan++) {
1375 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1376 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1377 if (type == GLSL_TYPE_FLOAT16) {
1378 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
1379 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
1380 }
1381 }
1382
1383 unsigned alpha_adjust = (ctx->args->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
1384 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
1385
1386 for (unsigned chan = 0; chan < 4; chan++) {
1387 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
1388 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
1389 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
1390
1391 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
1392 }
1393 }
1394 }
1395
1396 static void
1397 handle_vs_inputs(struct radv_shader_context *ctx,
1398 struct nir_shader *nir) {
1399 nir_foreach_variable(variable, &nir->inputs)
1400 handle_vs_input_decl(ctx, variable);
1401 }
1402
1403 static void
1404 prepare_interp_optimize(struct radv_shader_context *ctx,
1405 struct nir_shader *nir)
1406 {
1407 bool uses_center = false;
1408 bool uses_centroid = false;
1409 nir_foreach_variable(variable, &nir->inputs) {
1410 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1411 variable->data.sample)
1412 continue;
1413
1414 if (variable->data.centroid)
1415 uses_centroid = true;
1416 else
1417 uses_center = true;
1418 }
1419
1420 ctx->abi.persp_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.persp_centroid);
1421 ctx->abi.linear_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.linear_centroid);
1422
1423 if (uses_center && uses_centroid) {
1424 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT,
1425 ac_get_arg(&ctx->ac, ctx->args->ac.prim_mask),
1426 ctx->ac.i32_0, "");
1427 ctx->abi.persp_centroid =
1428 LLVMBuildSelect(ctx->ac.builder, sel,
1429 ac_get_arg(&ctx->ac, ctx->args->ac.persp_center),
1430 ctx->abi.persp_centroid, "");
1431 ctx->abi.linear_centroid =
1432 LLVMBuildSelect(ctx->ac.builder, sel,
1433 ac_get_arg(&ctx->ac, ctx->args->ac.linear_center),
1434 ctx->abi.linear_centroid, "");
1435 }
1436 }
1437
1438 static void
1439 scan_shader_output_decl(struct radv_shader_context *ctx,
1440 struct nir_variable *variable,
1441 struct nir_shader *shader,
1442 gl_shader_stage stage)
1443 {
1444 int idx = variable->data.location + variable->data.index;
1445 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1446 uint64_t mask_attribs;
1447
1448 variable->data.driver_location = idx * 4;
1449
1450 /* tess ctrl has it's own load/store paths for outputs */
1451 if (stage == MESA_SHADER_TESS_CTRL)
1452 return;
1453
1454 if (variable->data.compact) {
1455 unsigned component_count = variable->data.location_frac +
1456 glsl_get_length(variable->type);
1457 attrib_count = (component_count + 3) / 4;
1458 }
1459
1460 mask_attribs = ((1ull << attrib_count) - 1) << idx;
1461
1462 ctx->output_mask |= mask_attribs;
1463 }
1464
1465
1466 /* Initialize arguments for the shader export intrinsic */
1467 static void
1468 si_llvm_init_export_args(struct radv_shader_context *ctx,
1469 LLVMValueRef *values,
1470 unsigned enabled_channels,
1471 unsigned target,
1472 struct ac_export_args *args)
1473 {
1474 /* Specify the channels that are enabled. */
1475 args->enabled_channels = enabled_channels;
1476
1477 /* Specify whether the EXEC mask represents the valid mask */
1478 args->valid_mask = 0;
1479
1480 /* Specify whether this is the last export */
1481 args->done = 0;
1482
1483 /* Specify the target we are exporting */
1484 args->target = target;
1485
1486 args->compr = false;
1487 args->out[0] = LLVMGetUndef(ctx->ac.f32);
1488 args->out[1] = LLVMGetUndef(ctx->ac.f32);
1489 args->out[2] = LLVMGetUndef(ctx->ac.f32);
1490 args->out[3] = LLVMGetUndef(ctx->ac.f32);
1491
1492 if (!values)
1493 return;
1494
1495 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
1496 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1497 unsigned index = target - V_008DFC_SQ_EXP_MRT;
1498 unsigned col_format = (ctx->args->options->key.fs.col_format >> (4 * index)) & 0xf;
1499 bool is_int8 = (ctx->args->options->key.fs.is_int8 >> index) & 1;
1500 bool is_int10 = (ctx->args->options->key.fs.is_int10 >> index) & 1;
1501 unsigned chan;
1502
1503 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
1504 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
1505 unsigned bits, bool hi) = NULL;
1506
1507 switch(col_format) {
1508 case V_028714_SPI_SHADER_ZERO:
1509 args->enabled_channels = 0; /* writemask */
1510 args->target = V_008DFC_SQ_EXP_NULL;
1511 break;
1512
1513 case V_028714_SPI_SHADER_32_R:
1514 args->enabled_channels = 1;
1515 args->out[0] = values[0];
1516 break;
1517
1518 case V_028714_SPI_SHADER_32_GR:
1519 args->enabled_channels = 0x3;
1520 args->out[0] = values[0];
1521 args->out[1] = values[1];
1522 break;
1523
1524 case V_028714_SPI_SHADER_32_AR:
1525 if (ctx->ac.chip_class >= GFX10) {
1526 args->enabled_channels = 0x3;
1527 args->out[0] = values[0];
1528 args->out[1] = values[3];
1529 } else {
1530 args->enabled_channels = 0x9;
1531 args->out[0] = values[0];
1532 args->out[3] = values[3];
1533 }
1534 break;
1535
1536 case V_028714_SPI_SHADER_FP16_ABGR:
1537 args->enabled_channels = 0x5;
1538 packf = ac_build_cvt_pkrtz_f16;
1539 if (is_16bit) {
1540 for (unsigned chan = 0; chan < 4; chan++)
1541 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
1542 values[chan],
1543 ctx->ac.f32, "");
1544 }
1545 break;
1546
1547 case V_028714_SPI_SHADER_UNORM16_ABGR:
1548 args->enabled_channels = 0x5;
1549 packf = ac_build_cvt_pknorm_u16;
1550 break;
1551
1552 case V_028714_SPI_SHADER_SNORM16_ABGR:
1553 args->enabled_channels = 0x5;
1554 packf = ac_build_cvt_pknorm_i16;
1555 break;
1556
1557 case V_028714_SPI_SHADER_UINT16_ABGR:
1558 args->enabled_channels = 0x5;
1559 packi = ac_build_cvt_pk_u16;
1560 if (is_16bit) {
1561 for (unsigned chan = 0; chan < 4; chan++)
1562 values[chan] = LLVMBuildZExt(ctx->ac.builder,
1563 ac_to_integer(&ctx->ac, values[chan]),
1564 ctx->ac.i32, "");
1565 }
1566 break;
1567
1568 case V_028714_SPI_SHADER_SINT16_ABGR:
1569 args->enabled_channels = 0x5;
1570 packi = ac_build_cvt_pk_i16;
1571 if (is_16bit) {
1572 for (unsigned chan = 0; chan < 4; chan++)
1573 values[chan] = LLVMBuildSExt(ctx->ac.builder,
1574 ac_to_integer(&ctx->ac, values[chan]),
1575 ctx->ac.i32, "");
1576 }
1577 break;
1578
1579 default:
1580 case V_028714_SPI_SHADER_32_ABGR:
1581 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1582 break;
1583 }
1584
1585 /* Pack f16 or norm_i16/u16. */
1586 if (packf) {
1587 for (chan = 0; chan < 2; chan++) {
1588 LLVMValueRef pack_args[2] = {
1589 values[2 * chan],
1590 values[2 * chan + 1]
1591 };
1592 LLVMValueRef packed;
1593
1594 packed = packf(&ctx->ac, pack_args);
1595 args->out[chan] = ac_to_float(&ctx->ac, packed);
1596 }
1597 args->compr = 1; /* COMPR flag */
1598 }
1599
1600 /* Pack i16/u16. */
1601 if (packi) {
1602 for (chan = 0; chan < 2; chan++) {
1603 LLVMValueRef pack_args[2] = {
1604 ac_to_integer(&ctx->ac, values[2 * chan]),
1605 ac_to_integer(&ctx->ac, values[2 * chan + 1])
1606 };
1607 LLVMValueRef packed;
1608
1609 packed = packi(&ctx->ac, pack_args,
1610 is_int8 ? 8 : is_int10 ? 10 : 16,
1611 chan == 1);
1612 args->out[chan] = ac_to_float(&ctx->ac, packed);
1613 }
1614 args->compr = 1; /* COMPR flag */
1615 }
1616 return;
1617 }
1618
1619 if (is_16bit) {
1620 for (unsigned chan = 0; chan < 4; chan++) {
1621 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
1622 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
1623 }
1624 } else
1625 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1626
1627 for (unsigned i = 0; i < 4; ++i)
1628 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
1629 }
1630
1631 static void
1632 radv_export_param(struct radv_shader_context *ctx, unsigned index,
1633 LLVMValueRef *values, unsigned enabled_channels)
1634 {
1635 struct ac_export_args args;
1636
1637 si_llvm_init_export_args(ctx, values, enabled_channels,
1638 V_008DFC_SQ_EXP_PARAM + index, &args);
1639 ac_build_export(&ctx->ac, &args);
1640 }
1641
1642 static LLVMValueRef
1643 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
1644 {
1645 LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
1646 return LLVMBuildLoad(ctx->ac.builder, output, "");
1647 }
1648
1649 static void
1650 radv_emit_stream_output(struct radv_shader_context *ctx,
1651 LLVMValueRef const *so_buffers,
1652 LLVMValueRef const *so_write_offsets,
1653 const struct radv_stream_output *output,
1654 struct radv_shader_output_values *shader_out)
1655 {
1656 unsigned num_comps = util_bitcount(output->component_mask);
1657 unsigned buf = output->buffer;
1658 unsigned offset = output->offset;
1659 unsigned start;
1660 LLVMValueRef out[4];
1661
1662 assert(num_comps && num_comps <= 4);
1663 if (!num_comps || num_comps > 4)
1664 return;
1665
1666 /* Get the first component. */
1667 start = ffs(output->component_mask) - 1;
1668
1669 /* Load the output as int. */
1670 for (int i = 0; i < num_comps; i++) {
1671 out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
1672 }
1673
1674 /* Pack the output. */
1675 LLVMValueRef vdata = NULL;
1676
1677 switch (num_comps) {
1678 case 1: /* as i32 */
1679 vdata = out[0];
1680 break;
1681 case 2: /* as v2i32 */
1682 case 3: /* as v4i32 (aligned to 4) */
1683 out[3] = LLVMGetUndef(ctx->ac.i32);
1684 /* fall through */
1685 case 4: /* as v4i32 */
1686 vdata = ac_build_gather_values(&ctx->ac, out,
1687 !ac_has_vec3_support(ctx->ac.chip_class, false) ?
1688 util_next_power_of_two(num_comps) :
1689 num_comps);
1690 break;
1691 }
1692
1693 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
1694 vdata, num_comps, so_write_offsets[buf],
1695 ctx->ac.i32_0, offset,
1696 ac_glc | ac_slc);
1697 }
1698
1699 static void
1700 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
1701 {
1702 int i;
1703
1704 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1705 assert(ctx->args->streamout_config.used);
1706 LLVMValueRef so_vtx_count =
1707 ac_build_bfe(&ctx->ac,
1708 ac_get_arg(&ctx->ac, ctx->args->streamout_config),
1709 LLVMConstInt(ctx->ac.i32, 16, false),
1710 LLVMConstInt(ctx->ac.i32, 7, false), false);
1711
1712 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
1713
1714 /* can_emit = tid < so_vtx_count; */
1715 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
1716 tid, so_vtx_count, "");
1717
1718 /* Emit the streamout code conditionally. This actually avoids
1719 * out-of-bounds buffer access. The hw tells us via the SGPR
1720 * (so_vtx_count) which threads are allowed to emit streamout data.
1721 */
1722 ac_build_ifcc(&ctx->ac, can_emit, 6501);
1723 {
1724 /* The buffer offset is computed as follows:
1725 * ByteOffset = streamout_offset[buffer_id]*4 +
1726 * (streamout_write_index + thread_id)*stride[buffer_id] +
1727 * attrib_offset
1728 */
1729 LLVMValueRef so_write_index =
1730 ac_get_arg(&ctx->ac, ctx->args->streamout_write_idx);
1731
1732 /* Compute (streamout_write_index + thread_id). */
1733 so_write_index =
1734 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
1735
1736 /* Load the descriptor and compute the write offset for each
1737 * enabled buffer.
1738 */
1739 LLVMValueRef so_write_offset[4] = {};
1740 LLVMValueRef so_buffers[4] = {};
1741 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
1742
1743 for (i = 0; i < 4; i++) {
1744 uint16_t stride = ctx->args->shader_info->so.strides[i];
1745
1746 if (!stride)
1747 continue;
1748
1749 LLVMValueRef offset =
1750 LLVMConstInt(ctx->ac.i32, i, false);
1751
1752 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
1753 buf_ptr, offset);
1754
1755 LLVMValueRef so_offset =
1756 ac_get_arg(&ctx->ac, ctx->args->streamout_offset[i]);
1757
1758 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
1759 LLVMConstInt(ctx->ac.i32, 4, false), "");
1760
1761 so_write_offset[i] =
1762 ac_build_imad(&ctx->ac, so_write_index,
1763 LLVMConstInt(ctx->ac.i32,
1764 stride * 4, false),
1765 so_offset);
1766 }
1767
1768 /* Write streamout data. */
1769 for (i = 0; i < ctx->args->shader_info->so.num_outputs; i++) {
1770 struct radv_shader_output_values shader_out = {};
1771 struct radv_stream_output *output =
1772 &ctx->args->shader_info->so.outputs[i];
1773
1774 if (stream != output->stream)
1775 continue;
1776
1777 for (int j = 0; j < 4; j++) {
1778 shader_out.values[j] =
1779 radv_load_output(ctx, output->location, j);
1780 }
1781
1782 radv_emit_stream_output(ctx, so_buffers,so_write_offset,
1783 output, &shader_out);
1784 }
1785 }
1786 ac_build_endif(&ctx->ac, 6501);
1787 }
1788
1789 static void
1790 radv_build_param_exports(struct radv_shader_context *ctx,
1791 struct radv_shader_output_values *outputs,
1792 unsigned noutput,
1793 struct radv_vs_output_info *outinfo,
1794 bool export_clip_dists)
1795 {
1796 unsigned param_count = 0;
1797
1798 for (unsigned i = 0; i < noutput; i++) {
1799 unsigned slot_name = outputs[i].slot_name;
1800 unsigned usage_mask = outputs[i].usage_mask;
1801
1802 if (slot_name != VARYING_SLOT_LAYER &&
1803 slot_name != VARYING_SLOT_PRIMITIVE_ID &&
1804 slot_name != VARYING_SLOT_CLIP_DIST0 &&
1805 slot_name != VARYING_SLOT_CLIP_DIST1 &&
1806 slot_name < VARYING_SLOT_VAR0)
1807 continue;
1808
1809 if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
1810 slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
1811 continue;
1812
1813 radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
1814
1815 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
1816 outinfo->vs_output_param_offset[slot_name] = param_count++;
1817 }
1818
1819 outinfo->param_exports = param_count;
1820 }
1821
1822 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1823 * (position and parameter data only).
1824 */
1825 static void
1826 radv_llvm_export_vs(struct radv_shader_context *ctx,
1827 struct radv_shader_output_values *outputs,
1828 unsigned noutput,
1829 struct radv_vs_output_info *outinfo,
1830 bool export_clip_dists)
1831 {
1832 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
1833 struct ac_export_args pos_args[4] = {};
1834 unsigned pos_idx, index;
1835 int i;
1836
1837 /* Build position exports */
1838 for (i = 0; i < noutput; i++) {
1839 switch (outputs[i].slot_name) {
1840 case VARYING_SLOT_POS:
1841 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1842 V_008DFC_SQ_EXP_POS, &pos_args[0]);
1843 break;
1844 case VARYING_SLOT_PSIZ:
1845 psize_value = outputs[i].values[0];
1846 break;
1847 case VARYING_SLOT_LAYER:
1848 layer_value = outputs[i].values[0];
1849 break;
1850 case VARYING_SLOT_VIEWPORT:
1851 viewport_value = outputs[i].values[0];
1852 break;
1853 case VARYING_SLOT_CLIP_DIST0:
1854 case VARYING_SLOT_CLIP_DIST1:
1855 index = 2 + outputs[i].slot_index;
1856 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1857 V_008DFC_SQ_EXP_POS + index,
1858 &pos_args[index]);
1859 break;
1860 default:
1861 break;
1862 }
1863 }
1864
1865 /* We need to add the position output manually if it's missing. */
1866 if (!pos_args[0].out[0]) {
1867 pos_args[0].enabled_channels = 0xf; /* writemask */
1868 pos_args[0].valid_mask = 0; /* EXEC mask */
1869 pos_args[0].done = 0; /* last export? */
1870 pos_args[0].target = V_008DFC_SQ_EXP_POS;
1871 pos_args[0].compr = 0; /* COMPR flag */
1872 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
1873 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
1874 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
1875 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
1876 }
1877
1878 if (outinfo->writes_pointsize ||
1879 outinfo->writes_layer ||
1880 outinfo->writes_viewport_index) {
1881 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
1882 (outinfo->writes_layer == true ? 4 : 0));
1883 pos_args[1].valid_mask = 0;
1884 pos_args[1].done = 0;
1885 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
1886 pos_args[1].compr = 0;
1887 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
1888 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
1889 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
1890 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
1891
1892 if (outinfo->writes_pointsize == true)
1893 pos_args[1].out[0] = psize_value;
1894 if (outinfo->writes_layer == true)
1895 pos_args[1].out[2] = layer_value;
1896 if (outinfo->writes_viewport_index == true) {
1897 if (ctx->args->options->chip_class >= GFX9) {
1898 /* GFX9 has the layer in out.z[10:0] and the viewport
1899 * index in out.z[19:16].
1900 */
1901 LLVMValueRef v = viewport_value;
1902 v = ac_to_integer(&ctx->ac, v);
1903 v = LLVMBuildShl(ctx->ac.builder, v,
1904 LLVMConstInt(ctx->ac.i32, 16, false),
1905 "");
1906 v = LLVMBuildOr(ctx->ac.builder, v,
1907 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
1908
1909 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
1910 pos_args[1].enabled_channels |= 1 << 2;
1911 } else {
1912 pos_args[1].out[3] = viewport_value;
1913 pos_args[1].enabled_channels |= 1 << 3;
1914 }
1915 }
1916 }
1917
1918 for (i = 0; i < 4; i++) {
1919 if (pos_args[i].out[0])
1920 outinfo->pos_exports++;
1921 }
1922
1923 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
1924 * Setting valid_mask=1 prevents it and has no other effect.
1925 */
1926 if (ctx->ac.family == CHIP_NAVI10 ||
1927 ctx->ac.family == CHIP_NAVI12 ||
1928 ctx->ac.family == CHIP_NAVI14)
1929 pos_args[0].valid_mask = 1;
1930
1931 pos_idx = 0;
1932 for (i = 0; i < 4; i++) {
1933 if (!pos_args[i].out[0])
1934 continue;
1935
1936 /* Specify the target we are exporting */
1937 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
1938
1939 if (pos_idx == outinfo->pos_exports)
1940 /* Specify that this is the last export */
1941 pos_args[i].done = 1;
1942
1943 ac_build_export(&ctx->ac, &pos_args[i]);
1944 }
1945
1946 /* Build parameter exports */
1947 radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
1948 }
1949
1950 static void
1951 handle_vs_outputs_post(struct radv_shader_context *ctx,
1952 bool export_prim_id,
1953 bool export_clip_dists,
1954 struct radv_vs_output_info *outinfo)
1955 {
1956 struct radv_shader_output_values *outputs;
1957 unsigned noutput = 0;
1958
1959 if (ctx->args->options->key.has_multiview_view_index) {
1960 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
1961 if(!*tmp_out) {
1962 for(unsigned i = 0; i < 4; ++i)
1963 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
1964 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
1965 }
1966
1967 LLVMValueRef view_index = ac_get_arg(&ctx->ac, ctx->args->ac.view_index);
1968 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, view_index), *tmp_out);
1969 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
1970 }
1971
1972 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
1973 sizeof(outinfo->vs_output_param_offset));
1974 outinfo->pos_exports = 0;
1975
1976 if (!ctx->args->options->use_ngg_streamout &&
1977 ctx->args->shader_info->so.num_outputs &&
1978 !ctx->args->is_gs_copy_shader) {
1979 /* The GS copy shader emission already emits streamout. */
1980 radv_emit_streamout(ctx, 0);
1981 }
1982
1983 /* Allocate a temporary array for the output values. */
1984 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
1985 outputs = malloc(num_outputs * sizeof(outputs[0]));
1986
1987 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1988 if (!(ctx->output_mask & (1ull << i)))
1989 continue;
1990
1991 outputs[noutput].slot_name = i;
1992 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
1993
1994 if (ctx->stage == MESA_SHADER_VERTEX &&
1995 !ctx->args->is_gs_copy_shader) {
1996 outputs[noutput].usage_mask =
1997 ctx->args->shader_info->vs.output_usage_mask[i];
1998 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
1999 outputs[noutput].usage_mask =
2000 ctx->args->shader_info->tes.output_usage_mask[i];
2001 } else {
2002 assert(ctx->args->is_gs_copy_shader);
2003 outputs[noutput].usage_mask =
2004 ctx->args->shader_info->gs.output_usage_mask[i];
2005 }
2006
2007 for (unsigned j = 0; j < 4; j++) {
2008 outputs[noutput].values[j] =
2009 ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2010 }
2011
2012 noutput++;
2013 }
2014
2015 /* Export PrimitiveID. */
2016 if (export_prim_id) {
2017 outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
2018 outputs[noutput].slot_index = 0;
2019 outputs[noutput].usage_mask = 0x1;
2020 outputs[noutput].values[0] =
2021 ac_get_arg(&ctx->ac, ctx->args->vs_prim_id);
2022 for (unsigned j = 1; j < 4; j++)
2023 outputs[noutput].values[j] = ctx->ac.f32_0;
2024 noutput++;
2025 }
2026
2027 radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
2028
2029 free(outputs);
2030 }
2031
2032 static void
2033 handle_es_outputs_post(struct radv_shader_context *ctx,
2034 struct radv_es_output_info *outinfo)
2035 {
2036 int j;
2037 LLVMValueRef lds_base = NULL;
2038
2039 if (ctx->ac.chip_class >= GFX9) {
2040 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2041 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2042 LLVMValueRef wave_idx =
2043 ac_unpack_param(&ctx->ac,
2044 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2045 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2046 LLVMBuildMul(ctx->ac.builder, wave_idx,
2047 LLVMConstInt(ctx->ac.i32,
2048 ctx->ac.wave_size, false), ""), "");
2049 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2050 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2051 }
2052
2053 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2054 LLVMValueRef dw_addr = NULL;
2055 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2056 unsigned output_usage_mask;
2057 int param_index;
2058
2059 if (!(ctx->output_mask & (1ull << i)))
2060 continue;
2061
2062 if (ctx->stage == MESA_SHADER_VERTEX) {
2063 output_usage_mask =
2064 ctx->args->shader_info->vs.output_usage_mask[i];
2065 } else {
2066 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2067 output_usage_mask =
2068 ctx->args->shader_info->tes.output_usage_mask[i];
2069 }
2070
2071 param_index = shader_io_get_unique_index(i);
2072
2073 if (lds_base) {
2074 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2075 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2076 "");
2077 }
2078
2079 for (j = 0; j < 4; j++) {
2080 if (!(output_usage_mask & (1 << j)))
2081 continue;
2082
2083 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2084 out_val = ac_to_integer(&ctx->ac, out_val);
2085 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2086
2087 if (ctx->ac.chip_class >= GFX9) {
2088 LLVMValueRef dw_addr_offset =
2089 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2090 LLVMConstInt(ctx->ac.i32,
2091 j, false), "");
2092
2093 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2094 } else {
2095 ac_build_buffer_store_dword(&ctx->ac,
2096 ctx->esgs_ring,
2097 out_val, 1,
2098 NULL,
2099 ac_get_arg(&ctx->ac, ctx->args->es2gs_offset),
2100 (4 * param_index + j) * 4,
2101 ac_glc | ac_slc | ac_swizzled);
2102 }
2103 }
2104 }
2105 }
2106
2107 static void
2108 handle_ls_outputs_post(struct radv_shader_context *ctx)
2109 {
2110 LLVMValueRef vertex_id = ctx->rel_auto_id;
2111 uint32_t num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
2112 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2113 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2114 vertex_dw_stride, "");
2115
2116 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2117 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2118
2119 if (!(ctx->output_mask & (1ull << i)))
2120 continue;
2121
2122 int param = shader_io_get_unique_index(i);
2123 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2124 LLVMConstInt(ctx->ac.i32, param * 4, false),
2125 "");
2126 for (unsigned j = 0; j < 4; j++) {
2127 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2128 value = ac_to_integer(&ctx->ac, value);
2129 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2130 ac_lds_store(&ctx->ac, dw_addr, value);
2131 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2132 }
2133 }
2134 }
2135
2136 static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
2137 {
2138 return ac_unpack_param(&ctx->ac,
2139 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2140 }
2141
2142 static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
2143 {
2144 return ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 28, 4);
2145 }
2146
2147 static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
2148 {
2149 LLVMBuilderRef builder = ctx->ac.builder;
2150 LLVMValueRef tmp;
2151 tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
2152 LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
2153 return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
2154 }
2155
2156 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
2157 {
2158 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2159 LLVMConstInt(ctx->ac.i32, 12, false),
2160 LLVMConstInt(ctx->ac.i32, 9, false),
2161 false);
2162 }
2163
2164 static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
2165 {
2166 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2167 LLVMConstInt(ctx->ac.i32, 22, false),
2168 LLVMConstInt(ctx->ac.i32, 9, false),
2169 false);
2170 }
2171
2172 static LLVMValueRef ngg_get_ordered_id(struct radv_shader_context *ctx)
2173 {
2174 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2175 ctx->ac.i32_0,
2176 LLVMConstInt(ctx->ac.i32, 12, false),
2177 false);
2178 }
2179
2180 static LLVMValueRef
2181 ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
2182 {
2183 unsigned num_outputs = util_bitcount64(ctx->output_mask);
2184
2185 if (ctx->args->options->key.has_multiview_view_index)
2186 num_outputs++;
2187
2188 LLVMTypeRef elements[2] = {
2189 LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
2190 LLVMArrayType(ctx->ac.i8, 4),
2191 };
2192 LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
2193 type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
2194 return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
2195 }
2196
2197 /**
2198 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2199 * is in emit order; that is:
2200 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2201 * - during vertex emit, i.e. while the API GS shader invocation is running,
2202 * N = threadidx * gs_max_out_vertices + emitidx
2203 *
2204 * Goals of the LDS memory layout:
2205 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2206 * in uniform control flow
2207 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2208 * culling
2209 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2210 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2211 * 5. Avoid wasting memory.
2212 *
2213 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2214 * layout, elimination of bank conflicts requires that each vertex occupy an
2215 * odd number of dwords. We use the additional dword to store the output stream
2216 * index as well as a flag to indicate whether this vertex ends a primitive
2217 * for rasterization.
2218 *
2219 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2220 *
2221 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2222 * Indices are swizzled in groups of 32, which ensures point 1 without
2223 * disturbing point 2.
2224 *
2225 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2226 */
2227 static LLVMValueRef
2228 ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
2229 {
2230 LLVMBuilderRef builder = ctx->ac.builder;
2231 LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
2232
2233 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2234 unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
2235 if (write_stride_2exp) {
2236 LLVMValueRef row =
2237 LLVMBuildLShr(builder, vertexidx,
2238 LLVMConstInt(ctx->ac.i32, 5, false), "");
2239 LLVMValueRef swizzle =
2240 LLVMBuildAnd(builder, row,
2241 LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
2242 false), "");
2243 vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
2244 }
2245
2246 return ac_build_gep0(&ctx->ac, storage, vertexidx);
2247 }
2248
2249 static LLVMValueRef
2250 ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
2251 LLVMValueRef emitidx)
2252 {
2253 LLVMBuilderRef builder = ctx->ac.builder;
2254 LLVMValueRef tmp;
2255
2256 tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
2257 tmp = LLVMBuildMul(builder, tmp, gsthread, "");
2258 const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
2259 return ngg_gs_vertex_ptr(ctx, vertexidx);
2260 }
2261
2262 static LLVMValueRef
2263 ngg_gs_get_emit_output_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2264 unsigned out_idx)
2265 {
2266 LLVMValueRef gep_idx[3] = {
2267 ctx->ac.i32_0, /* implied C-style array */
2268 ctx->ac.i32_0, /* first struct entry */
2269 LLVMConstInt(ctx->ac.i32, out_idx, false),
2270 };
2271 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2272 }
2273
2274 static LLVMValueRef
2275 ngg_gs_get_emit_primflag_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2276 unsigned stream)
2277 {
2278 LLVMValueRef gep_idx[3] = {
2279 ctx->ac.i32_0, /* implied C-style array */
2280 ctx->ac.i32_1, /* second struct entry */
2281 LLVMConstInt(ctx->ac.i32, stream, false),
2282 };
2283 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2284 }
2285
2286 static struct radv_stream_output *
2287 radv_get_stream_output_by_loc(struct radv_streamout_info *so, unsigned location)
2288 {
2289 for (unsigned i = 0; i < so->num_outputs; ++i) {
2290 if (so->outputs[i].location == location)
2291 return &so->outputs[i];
2292 }
2293
2294 return NULL;
2295 }
2296
2297 static void build_streamout_vertex(struct radv_shader_context *ctx,
2298 LLVMValueRef *so_buffer, LLVMValueRef *wg_offset_dw,
2299 unsigned stream, LLVMValueRef offset_vtx,
2300 LLVMValueRef vertexptr)
2301 {
2302 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2303 LLVMBuilderRef builder = ctx->ac.builder;
2304 LLVMValueRef offset[4] = {};
2305 LLVMValueRef tmp;
2306
2307 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2308 if (!wg_offset_dw[buffer])
2309 continue;
2310
2311 tmp = LLVMBuildMul(builder, offset_vtx,
2312 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false), "");
2313 tmp = LLVMBuildAdd(builder, wg_offset_dw[buffer], tmp, "");
2314 offset[buffer] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
2315 }
2316
2317 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2318 struct radv_shader_output_values outputs[AC_LLVM_MAX_OUTPUTS];
2319 unsigned noutput = 0;
2320 unsigned out_idx = 0;
2321
2322 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2323 unsigned output_usage_mask =
2324 ctx->args->shader_info->gs.output_usage_mask[i];
2325 uint8_t output_stream =
2326 output_stream = ctx->args->shader_info->gs.output_streams[i];
2327
2328 if (!(ctx->output_mask & (1ull << i)) ||
2329 output_stream != stream)
2330 continue;
2331
2332 outputs[noutput].slot_name = i;
2333 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2334 outputs[noutput].usage_mask = output_usage_mask;
2335
2336 int length = util_last_bit(output_usage_mask);
2337
2338 for (unsigned j = 0; j < length; j++, out_idx++) {
2339 if (!(output_usage_mask & (1 << j)))
2340 continue;
2341
2342 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2343 LLVMConstInt(ctx->ac.i32, out_idx, false));
2344 outputs[noutput].values[j] = LLVMBuildLoad(builder, tmp, "");
2345 }
2346
2347 for (unsigned j = length; j < 4; j++)
2348 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
2349
2350 noutput++;
2351 }
2352
2353 for (unsigned i = 0; i < noutput; i++) {
2354 struct radv_stream_output *output =
2355 radv_get_stream_output_by_loc(so, outputs[i].slot_name);
2356
2357 if (!output ||
2358 output->stream != stream)
2359 continue;
2360
2361 struct radv_shader_output_values out = {};
2362
2363 for (unsigned j = 0; j < 4; j++) {
2364 out.values[j] = outputs[i].values[j];
2365 }
2366
2367 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2368 }
2369 } else {
2370 for (unsigned i = 0; i < so->num_outputs; ++i) {
2371 struct radv_stream_output *output =
2372 &ctx->args->shader_info->so.outputs[i];
2373
2374 if (stream != output->stream)
2375 continue;
2376
2377 struct radv_shader_output_values out = {};
2378
2379 for (unsigned comp = 0; comp < 4; comp++) {
2380 if (!(output->component_mask & (1 << comp)))
2381 continue;
2382
2383 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2384 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2385 out.values[comp] = LLVMBuildLoad(builder, tmp, "");
2386 }
2387
2388 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2389 }
2390 }
2391 }
2392
2393 struct ngg_streamout {
2394 LLVMValueRef num_vertices;
2395
2396 /* per-thread data */
2397 LLVMValueRef prim_enable[4]; /* i1 per stream */
2398 LLVMValueRef vertices[3]; /* [N x i32] addrspace(LDS)* */
2399
2400 /* Output */
2401 LLVMValueRef emit[4]; /* per-stream emitted primitives (only valid for used streams) */
2402 };
2403
2404 /**
2405 * Build streamout logic.
2406 *
2407 * Implies a barrier.
2408 *
2409 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2410 *
2411 * Clobbers gs_ngg_scratch[8:].
2412 */
2413 static void build_streamout(struct radv_shader_context *ctx,
2414 struct ngg_streamout *nggso)
2415 {
2416 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2417 LLVMBuilderRef builder = ctx->ac.builder;
2418 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
2419 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2420 LLVMValueRef cond, tmp, tmp2;
2421 LLVMValueRef i32_2 = LLVMConstInt(ctx->ac.i32, 2, false);
2422 LLVMValueRef i32_4 = LLVMConstInt(ctx->ac.i32, 4, false);
2423 LLVMValueRef i32_8 = LLVMConstInt(ctx->ac.i32, 8, false);
2424 LLVMValueRef so_buffer[4] = {};
2425 unsigned max_num_vertices = 1 + (nggso->vertices[1] ? 1 : 0) +
2426 (nggso->vertices[2] ? 1 : 0);
2427 LLVMValueRef prim_stride_dw[4] = {};
2428 LLVMValueRef prim_stride_dw_vgpr = LLVMGetUndef(ctx->ac.i32);
2429 int stream_for_buffer[4] = { -1, -1, -1, -1 };
2430 unsigned bufmask_for_stream[4] = {};
2431 bool isgs = ctx->stage == MESA_SHADER_GEOMETRY;
2432 unsigned scratch_emit_base = isgs ? 4 : 0;
2433 LLVMValueRef scratch_emit_basev = isgs ? i32_4 : ctx->ac.i32_0;
2434 unsigned scratch_offset_base = isgs ? 8 : 4;
2435 LLVMValueRef scratch_offset_basev = isgs ? i32_8 : i32_4;
2436
2437 ac_llvm_add_target_dep_function_attr(ctx->main_function,
2438 "amdgpu-gds-size", 256);
2439
2440 /* Determine the mapping of streamout buffers to vertex streams. */
2441 for (unsigned i = 0; i < so->num_outputs; ++i) {
2442 unsigned buf = so->outputs[i].buffer;
2443 unsigned stream = so->outputs[i].stream;
2444 assert(stream_for_buffer[buf] < 0 || stream_for_buffer[buf] == stream);
2445 stream_for_buffer[buf] = stream;
2446 bufmask_for_stream[stream] |= 1 << buf;
2447 }
2448
2449 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2450 if (stream_for_buffer[buffer] == -1)
2451 continue;
2452
2453 assert(so->strides[buffer]);
2454
2455 LLVMValueRef stride_for_buffer =
2456 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false);
2457 prim_stride_dw[buffer] =
2458 LLVMBuildMul(builder, stride_for_buffer,
2459 nggso->num_vertices, "");
2460 prim_stride_dw_vgpr = ac_build_writelane(
2461 &ctx->ac, prim_stride_dw_vgpr, prim_stride_dw[buffer],
2462 LLVMConstInt(ctx->ac.i32, buffer, false));
2463
2464 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, buffer, false);
2465 so_buffer[buffer] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr,
2466 offset);
2467 }
2468
2469 cond = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
2470 ac_build_ifcc(&ctx->ac, cond, 5200);
2471 {
2472 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
2473 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
2474
2475 /* Advance the streamout offsets in GDS. */
2476 LLVMValueRef offsets_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2477 LLVMValueRef generated_by_stream_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2478
2479 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2480 ac_build_ifcc(&ctx->ac, cond, 5210);
2481 {
2482 /* Fetch the number of generated primitives and store
2483 * it in GDS for later use.
2484 */
2485 if (isgs) {
2486 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid);
2487 tmp = LLVMBuildLoad(builder, tmp, "");
2488 } else {
2489 tmp = ac_build_writelane(&ctx->ac, ctx->ac.i32_0,
2490 ngg_get_prim_cnt(ctx), ctx->ac.i32_0);
2491 }
2492 LLVMBuildStore(builder, tmp, generated_by_stream_vgpr);
2493
2494 unsigned swizzle[4];
2495 int unused_stream = -1;
2496 for (unsigned stream = 0; stream < 4; ++stream) {
2497 if (!ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2498 unused_stream = stream;
2499 break;
2500 }
2501 }
2502 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2503 if (stream_for_buffer[buffer] >= 0) {
2504 swizzle[buffer] = stream_for_buffer[buffer];
2505 } else {
2506 assert(unused_stream >= 0);
2507 swizzle[buffer] = unused_stream;
2508 }
2509 }
2510
2511 tmp = ac_build_quad_swizzle(&ctx->ac, tmp,
2512 swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2513 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2514
2515 LLVMValueRef args[] = {
2516 LLVMBuildIntToPtr(builder, ngg_get_ordered_id(ctx), gdsptr, ""),
2517 tmp,
2518 ctx->ac.i32_0, // ordering
2519 ctx->ac.i32_0, // scope
2520 ctx->ac.i1false, // isVolatile
2521 LLVMConstInt(ctx->ac.i32, 4 << 24, false), // OA index
2522 ctx->ac.i1true, // wave release
2523 ctx->ac.i1true, // wave done
2524 };
2525
2526 tmp = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.ordered.add",
2527 ctx->ac.i32, args, ARRAY_SIZE(args), 0);
2528
2529 /* Keep offsets in a VGPR for quick retrieval via readlane by
2530 * the first wave for bounds checking, and also store in LDS
2531 * for retrieval by all waves later. */
2532 LLVMBuildStore(builder, tmp, offsets_vgpr);
2533
2534 tmp2 = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2535 scratch_offset_basev, "");
2536 tmp2 = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp2);
2537 LLVMBuildStore(builder, tmp, tmp2);
2538 }
2539 ac_build_endif(&ctx->ac, 5210);
2540
2541 /* Determine the max emit per buffer. This is done via the SALU, in part
2542 * because LLVM can't generate divide-by-multiply if we try to do this
2543 * via VALU with one lane per buffer.
2544 */
2545 LLVMValueRef max_emit[4] = {};
2546 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2547 if (stream_for_buffer[buffer] == -1)
2548 continue;
2549
2550 /* Compute the streamout buffer size in DWORD. */
2551 LLVMValueRef bufsize_dw =
2552 LLVMBuildLShr(builder,
2553 LLVMBuildExtractElement(builder, so_buffer[buffer], i32_2, ""),
2554 i32_2, "");
2555
2556 /* Load the streamout buffer offset from GDS. */
2557 tmp = LLVMBuildLoad(builder, offsets_vgpr, "");
2558 LLVMValueRef offset_dw =
2559 ac_build_readlane(&ctx->ac, tmp,
2560 LLVMConstInt(ctx->ac.i32, buffer, false));
2561
2562 /* Compute the remaining size to emit. */
2563 LLVMValueRef remaining_dw =
2564 LLVMBuildSub(builder, bufsize_dw, offset_dw, "");
2565 tmp = LLVMBuildUDiv(builder, remaining_dw,
2566 prim_stride_dw[buffer], "");
2567
2568 cond = LLVMBuildICmp(builder, LLVMIntULT,
2569 bufsize_dw, offset_dw, "");
2570 max_emit[buffer] = LLVMBuildSelect(builder, cond,
2571 ctx->ac.i32_0, tmp, "");
2572 }
2573
2574 /* Determine the number of emitted primitives per stream and fixup the
2575 * GDS counter if necessary.
2576 *
2577 * This is complicated by the fact that a single stream can emit to
2578 * multiple buffers (but luckily not vice versa).
2579 */
2580 LLVMValueRef emit_vgpr = ctx->ac.i32_0;
2581
2582 for (unsigned stream = 0; stream < 4; ++stream) {
2583 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2584 continue;
2585
2586 /* Load the number of generated primitives from GDS and
2587 * determine that number for the given stream.
2588 */
2589 tmp = LLVMBuildLoad(builder, generated_by_stream_vgpr, "");
2590 LLVMValueRef generated =
2591 ac_build_readlane(&ctx->ac, tmp,
2592 LLVMConstInt(ctx->ac.i32, stream, false));
2593
2594
2595 /* Compute the number of emitted primitives. */
2596 LLVMValueRef emit = generated;
2597 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2598 if (stream_for_buffer[buffer] == stream)
2599 emit = ac_build_umin(&ctx->ac, emit, max_emit[buffer]);
2600 }
2601
2602 /* Store the number of emitted primitives for that
2603 * stream.
2604 */
2605 emit_vgpr = ac_build_writelane(&ctx->ac, emit_vgpr, emit,
2606 LLVMConstInt(ctx->ac.i32, stream, false));
2607
2608 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2609 cond = LLVMBuildICmp(builder, LLVMIntULT, emit, generated, "");
2610 ac_build_ifcc(&ctx->ac, cond, 5221); /* scalar branch */
2611 tmp = LLVMBuildLShr(builder,
2612 LLVMConstInt(ctx->ac.i32, bufmask_for_stream[stream], false),
2613 ac_get_thread_id(&ctx->ac), "");
2614 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2615 ac_build_ifcc(&ctx->ac, tmp, 5222);
2616 {
2617 tmp = LLVMBuildSub(builder, generated, emit, "");
2618 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2619 tmp2 = LLVMBuildGEP(builder, gdsbase, &tid, 1, "");
2620 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpSub, tmp2, tmp,
2621 LLVMAtomicOrderingMonotonic, false);
2622 }
2623 ac_build_endif(&ctx->ac, 5222);
2624 ac_build_endif(&ctx->ac, 5221);
2625 }
2626
2627 /* Store the number of emitted primitives to LDS for later use. */
2628 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2629 ac_build_ifcc(&ctx->ac, cond, 5225);
2630 {
2631 tmp = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2632 scratch_emit_basev, "");
2633 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp);
2634 LLVMBuildStore(builder, emit_vgpr, tmp);
2635 }
2636 ac_build_endif(&ctx->ac, 5225);
2637 }
2638 ac_build_endif(&ctx->ac, 5200);
2639
2640 /* Determine the workgroup-relative per-thread / primitive offset into
2641 * the streamout buffers */
2642 struct ac_wg_scan primemit_scan[4] = {};
2643
2644 if (isgs) {
2645 for (unsigned stream = 0; stream < 4; ++stream) {
2646 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2647 continue;
2648
2649 primemit_scan[stream].enable_exclusive = true;
2650 primemit_scan[stream].op = nir_op_iadd;
2651 primemit_scan[stream].src = nggso->prim_enable[stream];
2652 primemit_scan[stream].scratch =
2653 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
2654 LLVMConstInt(ctx->ac.i32, 12 + 8 * stream, false));
2655 primemit_scan[stream].waveidx = get_wave_id_in_tg(ctx);
2656 primemit_scan[stream].numwaves = get_tgsize(ctx);
2657 primemit_scan[stream].maxwaves = 8;
2658 ac_build_wg_scan_top(&ctx->ac, &primemit_scan[stream]);
2659 }
2660 }
2661
2662 ac_build_s_barrier(&ctx->ac);
2663
2664 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2665 LLVMValueRef wgoffset_dw[4] = {};
2666
2667 {
2668 LLVMValueRef scratch_vgpr;
2669
2670 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ac_get_thread_id(&ctx->ac));
2671 scratch_vgpr = LLVMBuildLoad(builder, tmp, "");
2672
2673 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2674 if (stream_for_buffer[buffer] >= 0) {
2675 wgoffset_dw[buffer] = ac_build_readlane(
2676 &ctx->ac, scratch_vgpr,
2677 LLVMConstInt(ctx->ac.i32, scratch_offset_base + buffer, false));
2678 }
2679 }
2680
2681 for (unsigned stream = 0; stream < 4; ++stream) {
2682 if (ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2683 nggso->emit[stream] = ac_build_readlane(
2684 &ctx->ac, scratch_vgpr,
2685 LLVMConstInt(ctx->ac.i32, scratch_emit_base + stream, false));
2686 }
2687 }
2688 }
2689
2690 /* Write out primitive data */
2691 for (unsigned stream = 0; stream < 4; ++stream) {
2692 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2693 continue;
2694
2695 if (isgs) {
2696 ac_build_wg_scan_bottom(&ctx->ac, &primemit_scan[stream]);
2697 } else {
2698 primemit_scan[stream].result_exclusive = tid;
2699 }
2700
2701 cond = LLVMBuildICmp(builder, LLVMIntULT,
2702 primemit_scan[stream].result_exclusive,
2703 nggso->emit[stream], "");
2704 cond = LLVMBuildAnd(builder, cond, nggso->prim_enable[stream], "");
2705 ac_build_ifcc(&ctx->ac, cond, 5240);
2706 {
2707 LLVMValueRef offset_vtx =
2708 LLVMBuildMul(builder, primemit_scan[stream].result_exclusive,
2709 nggso->num_vertices, "");
2710
2711 for (unsigned i = 0; i < max_num_vertices; ++i) {
2712 cond = LLVMBuildICmp(builder, LLVMIntULT,
2713 LLVMConstInt(ctx->ac.i32, i, false),
2714 nggso->num_vertices, "");
2715 ac_build_ifcc(&ctx->ac, cond, 5241);
2716 build_streamout_vertex(ctx, so_buffer, wgoffset_dw,
2717 stream, offset_vtx, nggso->vertices[i]);
2718 ac_build_endif(&ctx->ac, 5241);
2719 offset_vtx = LLVMBuildAdd(builder, offset_vtx, ctx->ac.i32_1, "");
2720 }
2721 }
2722 ac_build_endif(&ctx->ac, 5240);
2723 }
2724 }
2725
2726 static unsigned ngg_nogs_vertex_size(struct radv_shader_context *ctx)
2727 {
2728 unsigned lds_vertex_size = 0;
2729
2730 if (ctx->args->shader_info->so.num_outputs)
2731 lds_vertex_size = 4 * ctx->args->shader_info->so.num_outputs + 1;
2732
2733 return lds_vertex_size;
2734 }
2735
2736 /**
2737 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2738 * for the vertex outputs.
2739 */
2740 static LLVMValueRef ngg_nogs_vertex_ptr(struct radv_shader_context *ctx,
2741 LLVMValueRef vtxid)
2742 {
2743 /* The extra dword is used to avoid LDS bank conflicts. */
2744 unsigned vertex_size = ngg_nogs_vertex_size(ctx);
2745 LLVMTypeRef ai32 = LLVMArrayType(ctx->ac.i32, vertex_size);
2746 LLVMTypeRef pai32 = LLVMPointerType(ai32, AC_ADDR_SPACE_LDS);
2747 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, ctx->esgs_ring, pai32, "");
2748 return LLVMBuildGEP(ctx->ac.builder, tmp, &vtxid, 1, "");
2749 }
2750
2751 static void
2752 handle_ngg_outputs_post_1(struct radv_shader_context *ctx)
2753 {
2754 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2755 LLVMBuilderRef builder = ctx->ac.builder;
2756 LLVMValueRef vertex_ptr = NULL;
2757 LLVMValueRef tmp, tmp2;
2758
2759 assert((ctx->stage == MESA_SHADER_VERTEX ||
2760 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2761
2762 if (!ctx->args->shader_info->so.num_outputs)
2763 return;
2764
2765 vertex_ptr = ngg_nogs_vertex_ptr(ctx, get_thread_id_in_tg(ctx));
2766
2767 for (unsigned i = 0; i < so->num_outputs; ++i) {
2768 struct radv_stream_output *output =
2769 &ctx->args->shader_info->so.outputs[i];
2770
2771 unsigned loc = output->location;
2772
2773 for (unsigned comp = 0; comp < 4; comp++) {
2774 if (!(output->component_mask & (1 << comp)))
2775 continue;
2776
2777 tmp = ac_build_gep0(&ctx->ac, vertex_ptr,
2778 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2779 tmp2 = LLVMBuildLoad(builder,
2780 ctx->abi.outputs[4 * loc + comp], "");
2781 tmp2 = ac_to_integer(&ctx->ac, tmp2);
2782 LLVMBuildStore(builder, tmp2, tmp);
2783 }
2784 }
2785 }
2786
2787 static void
2788 handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
2789 {
2790 LLVMBuilderRef builder = ctx->ac.builder;
2791 LLVMValueRef tmp;
2792
2793 assert((ctx->stage == MESA_SHADER_VERTEX ||
2794 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2795
2796 LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac,
2797 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
2798 LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac,
2799 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 0, 8);
2800 LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
2801 ac_get_thread_id(&ctx->ac), prims_in_wave, "");
2802 LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
2803 ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
2804 LLVMValueRef vtxindex[] = {
2805 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 0, 16),
2806 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 16, 16),
2807 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[2]), 0, 16),
2808 };
2809
2810 /* Determine the number of vertices per primitive. */
2811 unsigned num_vertices;
2812 LLVMValueRef num_vertices_val;
2813
2814 if (ctx->stage == MESA_SHADER_VERTEX) {
2815 LLVMValueRef outprim_val =
2816 LLVMConstInt(ctx->ac.i32,
2817 ctx->args->options->key.vs.outprim, false);
2818 num_vertices_val = LLVMBuildAdd(builder, outprim_val,
2819 ctx->ac.i32_1, "");
2820 num_vertices = 3; /* TODO: optimize for points & lines */
2821 } else {
2822 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2823
2824 if (ctx->shader->info.tess.point_mode)
2825 num_vertices = 1;
2826 else if (ctx->shader->info.tess.primitive_mode == GL_ISOLINES)
2827 num_vertices = 2;
2828 else
2829 num_vertices = 3;
2830
2831 num_vertices_val = LLVMConstInt(ctx->ac.i32, num_vertices, false);
2832 }
2833
2834 /* Streamout */
2835 if (ctx->args->shader_info->so.num_outputs) {
2836 struct ngg_streamout nggso = {};
2837
2838 nggso.num_vertices = num_vertices_val;
2839 nggso.prim_enable[0] = is_gs_thread;
2840
2841 for (unsigned i = 0; i < num_vertices; ++i)
2842 nggso.vertices[i] = ngg_nogs_vertex_ptr(ctx, vtxindex[i]);
2843
2844 build_streamout(ctx, &nggso);
2845 }
2846
2847 /* Copy Primitive IDs from GS threads to the LDS address corresponding
2848 * to the ES thread of the provoking vertex.
2849 */
2850 if (ctx->stage == MESA_SHADER_VERTEX &&
2851 ctx->args->options->key.vs_common_out.export_prim_id) {
2852 if (ctx->args->shader_info->so.num_outputs)
2853 ac_build_s_barrier(&ctx->ac);
2854
2855 ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
2856 /* Extract the PROVOKING_VTX_INDEX field. */
2857 LLVMValueRef provoking_vtx_in_prim =
2858 LLVMConstInt(ctx->ac.i32, 0, false);
2859
2860 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
2861 LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
2862 LLVMValueRef provoking_vtx_index =
2863 LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
2864
2865 LLVMBuildStore(builder, ac_get_arg(&ctx->ac, ctx->args->ac.gs_prim_id),
2866 ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
2867 ac_build_endif(&ctx->ac, 5400);
2868 }
2869
2870 /* TODO: primitive culling */
2871
2872 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
2873 ngg_get_vtx_cnt(ctx), ngg_get_prim_cnt(ctx));
2874
2875 /* TODO: streamout queries */
2876 /* Export primitive data to the index buffer.
2877 *
2878 * For the first version, we will always build up all three indices
2879 * independent of the primitive type. The additional garbage data
2880 * shouldn't hurt.
2881 *
2882 * TODO: culling depends on the primitive type, so can have some
2883 * interaction here.
2884 */
2885 ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
2886 {
2887 struct ac_ngg_prim prim = {};
2888
2889 if (ctx->args->options->key.vs_common_out.as_ngg_passthrough) {
2890 prim.passthrough = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]);
2891 } else {
2892 prim.num_vertices = num_vertices;
2893 prim.isnull = ctx->ac.i1false;
2894 memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
2895
2896 for (unsigned i = 0; i < num_vertices; ++i) {
2897 tmp = LLVMBuildLShr(builder,
2898 ac_get_arg(&ctx->ac, ctx->args->ac.gs_invocation_id),
2899 LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
2900 prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2901 }
2902 }
2903
2904 ac_build_export_prim(&ctx->ac, &prim);
2905 }
2906 ac_build_endif(&ctx->ac, 6001);
2907
2908 /* Export per-vertex data (positions and parameters). */
2909 ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
2910 {
2911 struct radv_vs_output_info *outinfo =
2912 ctx->stage == MESA_SHADER_TESS_EVAL ?
2913 &ctx->args->shader_info->tes.outinfo : &ctx->args->shader_info->vs.outinfo;
2914
2915 /* Exporting the primitive ID is handled below. */
2916 /* TODO: use the new VS export path */
2917 handle_vs_outputs_post(ctx, false,
2918 ctx->args->options->key.vs_common_out.export_clip_dists,
2919 outinfo);
2920
2921 if (ctx->args->options->key.vs_common_out.export_prim_id) {
2922 unsigned param_count = outinfo->param_exports;
2923 LLVMValueRef values[4];
2924
2925 if (ctx->stage == MESA_SHADER_VERTEX) {
2926 /* Wait for GS stores to finish. */
2927 ac_build_s_barrier(&ctx->ac);
2928
2929 tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
2930 get_thread_id_in_tg(ctx));
2931 values[0] = LLVMBuildLoad(builder, tmp, "");
2932 } else {
2933 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2934 values[0] = ac_get_arg(&ctx->ac, ctx->args->ac.tes_patch_id);
2935 }
2936
2937 values[0] = ac_to_float(&ctx->ac, values[0]);
2938 for (unsigned j = 1; j < 4; j++)
2939 values[j] = ctx->ac.f32_0;
2940
2941 radv_export_param(ctx, param_count, values, 0x1);
2942
2943 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2944 outinfo->param_exports = param_count;
2945 }
2946 }
2947 ac_build_endif(&ctx->ac, 6002);
2948 }
2949
2950 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
2951 {
2952 /* Zero out the part of LDS scratch that is used to accumulate the
2953 * per-stream generated primitive count.
2954 */
2955 LLVMBuilderRef builder = ctx->ac.builder;
2956 LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
2957 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2958 LLVMBasicBlockRef merge_block;
2959 LLVMValueRef cond;
2960
2961 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
2962 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
2963 merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
2964
2965 cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
2966 LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
2967 LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
2968
2969 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
2970 LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
2971
2972 LLVMBuildBr(ctx->ac.builder, merge_block);
2973 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
2974
2975 ac_build_s_barrier(&ctx->ac);
2976 }
2977
2978 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
2979 {
2980 LLVMBuilderRef builder = ctx->ac.builder;
2981 LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
2982 LLVMValueRef tmp;
2983
2984 /* Zero out remaining (non-emitted) primitive flags.
2985 *
2986 * Note: Alternatively, we could pass the relevant gs_next_vertex to
2987 * the emit threads via LDS. This is likely worse in the expected
2988 * typical case where each GS thread emits the full set of
2989 * vertices.
2990 */
2991 for (unsigned stream = 0; stream < 4; ++stream) {
2992 unsigned num_components;
2993
2994 num_components =
2995 ctx->args->shader_info->gs.num_stream_output_components[stream];
2996 if (!num_components)
2997 continue;
2998
2999 const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
3000
3001 ac_build_bgnloop(&ctx->ac, 5100);
3002
3003 const LLVMValueRef vertexidx =
3004 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3005 tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
3006 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3007 ac_build_ifcc(&ctx->ac, tmp, 5101);
3008 ac_build_break(&ctx->ac);
3009 ac_build_endif(&ctx->ac, 5101);
3010
3011 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3012 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3013
3014 tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
3015 LLVMBuildStore(builder, i8_0,
3016 ngg_gs_get_emit_primflag_ptr(ctx, tmp, stream));
3017
3018 ac_build_endloop(&ctx->ac, 5100);
3019 }
3020
3021 /* Accumulate generated primitives counts across the entire threadgroup. */
3022 for (unsigned stream = 0; stream < 4; ++stream) {
3023 unsigned num_components;
3024
3025 num_components =
3026 ctx->args->shader_info->gs.num_stream_output_components[stream];
3027 if (!num_components)
3028 continue;
3029
3030 LLVMValueRef numprims =
3031 LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3032 numprims = ac_build_reduce(&ctx->ac, numprims, nir_op_iadd, ctx->ac.wave_size);
3033
3034 tmp = LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(&ctx->ac), ctx->ac.i32_0, "");
3035 ac_build_ifcc(&ctx->ac, tmp, 5105);
3036 {
3037 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
3038 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
3039 LLVMConstInt(ctx->ac.i32, stream, false)),
3040 numprims, LLVMAtomicOrderingMonotonic, false);
3041 }
3042 ac_build_endif(&ctx->ac, 5105);
3043 }
3044 }
3045
3046 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
3047 {
3048 const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
3049 LLVMBuilderRef builder = ctx->ac.builder;
3050 LLVMValueRef tmp, tmp2;
3051
3052 ac_build_s_barrier(&ctx->ac);
3053
3054 const LLVMValueRef tid = get_thread_id_in_tg(ctx);
3055 LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
3056
3057 /* Streamout */
3058 if (ctx->args->shader_info->so.num_outputs) {
3059 struct ngg_streamout nggso = {};
3060
3061 nggso.num_vertices = LLVMConstInt(ctx->ac.i32, verts_per_prim, false);
3062
3063 LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tid);
3064 for (unsigned stream = 0; stream < 4; ++stream) {
3065 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
3066 continue;
3067
3068 tmp = LLVMBuildLoad(builder,
3069 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream), "");
3070 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3071 tmp2 = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3072 nggso.prim_enable[stream] = LLVMBuildAnd(builder, tmp, tmp2, "");
3073 }
3074
3075 for (unsigned i = 0; i < verts_per_prim; ++i) {
3076 tmp = LLVMBuildSub(builder, tid,
3077 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3078 tmp = ngg_gs_vertex_ptr(ctx, tmp);
3079 nggso.vertices[i] = ac_build_gep0(&ctx->ac, tmp, ctx->ac.i32_0);
3080 }
3081
3082 build_streamout(ctx, &nggso);
3083 }
3084
3085 /* Write shader query data. */
3086 tmp = ac_get_arg(&ctx->ac, ctx->args->ngg_gs_state);
3087 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3088 ac_build_ifcc(&ctx->ac, tmp, 5109);
3089 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid,
3090 LLVMConstInt(ctx->ac.i32, 4, false), "");
3091 ac_build_ifcc(&ctx->ac, tmp, 5110);
3092 {
3093 tmp = LLVMBuildLoad(builder, ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid), "");
3094
3095 ac_llvm_add_target_dep_function_attr(ctx->main_function,
3096 "amdgpu-gds-size", 256);
3097
3098 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
3099 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
3100
3101 const char *sync_scope = LLVM_VERSION_MAJOR >= 9 ? "workgroup-one-as" : "workgroup";
3102
3103 /* Use a plain GDS atomic to accumulate the number of generated
3104 * primitives.
3105 */
3106 ac_build_atomic_rmw(&ctx->ac, LLVMAtomicRMWBinOpAdd, gdsbase,
3107 tmp, sync_scope);
3108 }
3109 ac_build_endif(&ctx->ac, 5110);
3110 ac_build_endif(&ctx->ac, 5109);
3111
3112 /* TODO: culling */
3113
3114 /* Determine vertex liveness. */
3115 LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
3116
3117 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3118 ac_build_ifcc(&ctx->ac, tmp, 5120);
3119 {
3120 for (unsigned i = 0; i < verts_per_prim; ++i) {
3121 const LLVMValueRef primidx =
3122 LLVMBuildAdd(builder, tid,
3123 LLVMConstInt(ctx->ac.i32, i, false), "");
3124
3125 if (i > 0) {
3126 tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
3127 ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
3128 }
3129
3130 /* Load primitive liveness */
3131 tmp = ngg_gs_vertex_ptr(ctx, primidx);
3132 tmp = LLVMBuildLoad(builder,
3133 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3134 const LLVMValueRef primlive =
3135 LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3136
3137 tmp = LLVMBuildLoad(builder, vertliveptr, "");
3138 tmp = LLVMBuildOr(builder, tmp, primlive, ""),
3139 LLVMBuildStore(builder, tmp, vertliveptr);
3140
3141 if (i > 0)
3142 ac_build_endif(&ctx->ac, 5121 + i);
3143 }
3144 }
3145 ac_build_endif(&ctx->ac, 5120);
3146
3147 /* Inclusive scan addition across the current wave. */
3148 LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
3149 struct ac_wg_scan vertlive_scan = {};
3150 vertlive_scan.op = nir_op_iadd;
3151 vertlive_scan.enable_reduce = true;
3152 vertlive_scan.enable_exclusive = true;
3153 vertlive_scan.src = vertlive;
3154 vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
3155 vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
3156 vertlive_scan.numwaves = get_tgsize(ctx);
3157 vertlive_scan.maxwaves = 8;
3158
3159 ac_build_wg_scan(&ctx->ac, &vertlive_scan);
3160
3161 /* Skip all exports (including index exports) when possible. At least on
3162 * early gfx10 revisions this is also to avoid hangs.
3163 */
3164 LLVMValueRef have_exports =
3165 LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
3166 num_emit_threads =
3167 LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
3168
3169 /* Allocate export space. Send this message as early as possible, to
3170 * hide the latency of the SQ <-> SPI roundtrip.
3171 *
3172 * Note: We could consider compacting primitives for export as well.
3173 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3174 * prim data per clock and skips null primitives at no additional
3175 * cost. So compacting primitives can only be beneficial when
3176 * there are 4 or more contiguous null primitives in the export
3177 * (in the common case of single-dword prim exports).
3178 */
3179 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
3180 vertlive_scan.result_reduce, num_emit_threads);
3181
3182 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3183 * of the primitive liveness flags, relying on the fact that each
3184 * threadgroup can have at most 256 threads. */
3185 ac_build_ifcc(&ctx->ac, vertlive, 5130);
3186 {
3187 tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
3188 tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
3189 LLVMBuildStore(builder, tmp2,
3190 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1));
3191 }
3192 ac_build_endif(&ctx->ac, 5130);
3193
3194 ac_build_s_barrier(&ctx->ac);
3195
3196 /* Export primitive data */
3197 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3198 ac_build_ifcc(&ctx->ac, tmp, 5140);
3199 {
3200 LLVMValueRef flags;
3201 struct ac_ngg_prim prim = {};
3202 prim.num_vertices = verts_per_prim;
3203
3204 tmp = ngg_gs_vertex_ptr(ctx, tid);
3205 flags = LLVMBuildLoad(builder,
3206 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3207 prim.isnull = LLVMBuildNot(builder, LLVMBuildTrunc(builder, flags, ctx->ac.i1, ""), "");
3208
3209 for (unsigned i = 0; i < verts_per_prim; ++i) {
3210 prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
3211 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3212 prim.edgeflag[i] = ctx->ac.i1false;
3213 }
3214
3215 /* Geometry shaders output triangle strips, but NGG expects
3216 * triangles. We need to change the vertex order for odd
3217 * triangles to get correct front/back facing by swapping 2
3218 * vertex indices, but we also have to keep the provoking
3219 * vertex in the same place.
3220 */
3221 if (verts_per_prim == 3) {
3222 LLVMValueRef is_odd = LLVMBuildLShr(builder, flags, ctx->ac.i8_1, "");
3223 is_odd = LLVMBuildTrunc(builder, is_odd, ctx->ac.i1, "");
3224
3225 struct ac_ngg_prim in = prim;
3226 prim.index[0] = in.index[0];
3227 prim.index[1] = LLVMBuildSelect(builder, is_odd,
3228 in.index[2], in.index[1], "");
3229 prim.index[2] = LLVMBuildSelect(builder, is_odd,
3230 in.index[1], in.index[2], "");
3231 }
3232
3233 ac_build_export_prim(&ctx->ac, &prim);
3234 }
3235 ac_build_endif(&ctx->ac, 5140);
3236
3237 /* Export position and parameter data */
3238 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
3239 ac_build_ifcc(&ctx->ac, tmp, 5145);
3240 {
3241 struct radv_vs_output_info *outinfo = &ctx->args->shader_info->vs.outinfo;
3242 bool export_view_index = ctx->args->options->key.has_multiview_view_index;
3243 struct radv_shader_output_values *outputs;
3244 unsigned noutput = 0;
3245
3246 /* Allocate a temporary array for the output values. */
3247 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
3248 outputs = calloc(num_outputs, sizeof(outputs[0]));
3249
3250 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
3251 sizeof(outinfo->vs_output_param_offset));
3252 outinfo->pos_exports = 0;
3253
3254 tmp = ngg_gs_vertex_ptr(ctx, tid);
3255 tmp = LLVMBuildLoad(builder,
3256 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1), "");
3257 tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
3258 const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
3259
3260 unsigned out_idx = 0;
3261 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3262 unsigned output_usage_mask =
3263 ctx->args->shader_info->gs.output_usage_mask[i];
3264 int length = util_last_bit(output_usage_mask);
3265
3266 if (!(ctx->output_mask & (1ull << i)))
3267 continue;
3268
3269 outputs[noutput].slot_name = i;
3270 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
3271 outputs[noutput].usage_mask = output_usage_mask;
3272
3273 for (unsigned j = 0; j < length; j++, out_idx++) {
3274 if (!(output_usage_mask & (1 << j)))
3275 continue;
3276
3277 tmp = ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx);
3278 tmp = LLVMBuildLoad(builder, tmp, "");
3279
3280 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3281 if (ac_get_type_size(type) == 2) {
3282 tmp = ac_to_integer(&ctx->ac, tmp);
3283 tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
3284 }
3285
3286 outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
3287 }
3288
3289 for (unsigned j = length; j < 4; j++)
3290 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
3291
3292 noutput++;
3293 }
3294
3295 /* Export ViewIndex. */
3296 if (export_view_index) {
3297 outputs[noutput].slot_name = VARYING_SLOT_LAYER;
3298 outputs[noutput].slot_index = 0;
3299 outputs[noutput].usage_mask = 0x1;
3300 outputs[noutput].values[0] =
3301 ac_to_float(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.view_index));
3302 for (unsigned j = 1; j < 4; j++)
3303 outputs[noutput].values[j] = ctx->ac.f32_0;
3304 noutput++;
3305 }
3306
3307 radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
3308 ctx->args->options->key.vs_common_out.export_clip_dists);
3309 FREE(outputs);
3310 }
3311 ac_build_endif(&ctx->ac, 5145);
3312 }
3313
3314 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
3315 unsigned stream,
3316 LLVMValueRef *addrs)
3317 {
3318 LLVMBuilderRef builder = ctx->ac.builder;
3319 LLVMValueRef tmp;
3320 const LLVMValueRef vertexidx =
3321 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3322
3323 /* If this thread has already emitted the declared maximum number of
3324 * vertices, skip the write: excessive vertex emissions are not
3325 * supposed to have any effect.
3326 */
3327 const LLVMValueRef can_emit =
3328 LLVMBuildICmp(builder, LLVMIntULT, vertexidx,
3329 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3330 ac_build_ifcc(&ctx->ac, can_emit, 9001);
3331
3332 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3333 tmp = LLVMBuildSelect(builder, can_emit, tmp, vertexidx, "");
3334 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3335
3336 const LLVMValueRef vertexptr =
3337 ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
3338 unsigned out_idx = 0;
3339 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3340 unsigned output_usage_mask =
3341 ctx->args->shader_info->gs.output_usage_mask[i];
3342 uint8_t output_stream =
3343 ctx->args->shader_info->gs.output_streams[i];
3344 LLVMValueRef *out_ptr = &addrs[i * 4];
3345 int length = util_last_bit(output_usage_mask);
3346
3347 if (!(ctx->output_mask & (1ull << i)) ||
3348 output_stream != stream)
3349 continue;
3350
3351 for (unsigned j = 0; j < length; j++, out_idx++) {
3352 if (!(output_usage_mask & (1 << j)))
3353 continue;
3354
3355 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
3356 out_ptr[j], "");
3357 out_val = ac_to_integer(&ctx->ac, out_val);
3358 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
3359
3360 LLVMBuildStore(builder, out_val,
3361 ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx));
3362 }
3363 }
3364 assert(out_idx * 4 <= ctx->args->shader_info->gs.gsvs_vertex_size);
3365
3366 /* Determine and store whether this vertex completed a primitive. */
3367 const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
3368
3369 tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
3370 const LLVMValueRef iscompleteprim =
3371 LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
3372
3373 /* Since the geometry shader emits triangle strips, we need to
3374 * track which primitive is odd and swap vertex indices to get
3375 * the correct vertex order.
3376 */
3377 LLVMValueRef is_odd = ctx->ac.i1false;
3378 if (stream == 0 &&
3379 si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) == 3) {
3380 tmp = LLVMBuildAnd(builder, curverts, ctx->ac.i32_1, "");
3381 is_odd = LLVMBuildICmp(builder, LLVMIntEQ, tmp, ctx->ac.i32_1, "");
3382 }
3383
3384 tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
3385 LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
3386
3387 /* The per-vertex primitive flag encoding:
3388 * bit 0: whether this vertex finishes a primitive
3389 * bit 1: whether the primitive is odd (if we are emitting triangle strips)
3390 */
3391 tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
3392 tmp = LLVMBuildOr(builder, tmp,
3393 LLVMBuildShl(builder,
3394 LLVMBuildZExt(builder, is_odd, ctx->ac.i8, ""),
3395 ctx->ac.i8_1, ""), "");
3396 LLVMBuildStore(builder, tmp,
3397 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream));
3398
3399 tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3400 tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
3401 LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
3402
3403 ac_build_endif(&ctx->ac, 9001);
3404 }
3405
3406 static void
3407 write_tess_factors(struct radv_shader_context *ctx)
3408 {
3409 unsigned stride, outer_comps, inner_comps;
3410 LLVMValueRef tcs_rel_ids = ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids);
3411 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 8, 5);
3412 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 0, 8);
3413 unsigned tess_inner_index = 0, tess_outer_index;
3414 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
3415 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3416 int i;
3417 ac_emit_barrier(&ctx->ac, ctx->stage);
3418
3419 switch (ctx->args->options->key.tcs.primitive_mode) {
3420 case GL_ISOLINES:
3421 stride = 2;
3422 outer_comps = 2;
3423 inner_comps = 0;
3424 break;
3425 case GL_TRIANGLES:
3426 stride = 4;
3427 outer_comps = 3;
3428 inner_comps = 1;
3429 break;
3430 case GL_QUADS:
3431 stride = 6;
3432 outer_comps = 4;
3433 inner_comps = 2;
3434 break;
3435 default:
3436 return;
3437 }
3438
3439 ac_build_ifcc(&ctx->ac,
3440 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3441 invocation_id, ctx->ac.i32_0, ""), 6503);
3442
3443 lds_base = get_tcs_out_current_patch_data_offset(ctx);
3444
3445 if (inner_comps) {
3446 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3447 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3448 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3449 }
3450
3451 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3452 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3453 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3454
3455 for (i = 0; i < 4; i++) {
3456 inner[i] = LLVMGetUndef(ctx->ac.i32);
3457 outer[i] = LLVMGetUndef(ctx->ac.i32);
3458 }
3459
3460 // LINES reversal
3461 if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
3462 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3463 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3464 ctx->ac.i32_1, "");
3465 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3466 } else {
3467 for (i = 0; i < outer_comps; i++) {
3468 outer[i] = out[i] =
3469 ac_lds_load(&ctx->ac, lds_outer);
3470 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3471 ctx->ac.i32_1, "");
3472 }
3473 for (i = 0; i < inner_comps; i++) {
3474 inner[i] = out[outer_comps+i] =
3475 ac_lds_load(&ctx->ac, lds_inner);
3476 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3477 ctx->ac.i32_1, "");
3478 }
3479 }
3480
3481 /* Convert the outputs to vectors for stores. */
3482 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3483 vec1 = NULL;
3484
3485 if (stride > 4)
3486 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3487
3488
3489 buffer = ctx->hs_ring_tess_factor;
3490 tf_base = ac_get_arg(&ctx->ac, ctx->args->tess_factor_offset);
3491 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3492 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3493 unsigned tf_offset = 0;
3494
3495 if (ctx->ac.chip_class <= GFX8) {
3496 ac_build_ifcc(&ctx->ac,
3497 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3498 rel_patch_id, ctx->ac.i32_0, ""), 6504);
3499
3500 /* Store the dynamic HS control word. */
3501 ac_build_buffer_store_dword(&ctx->ac, buffer,
3502 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3503 1, ctx->ac.i32_0, tf_base,
3504 0, ac_glc);
3505 tf_offset += 4;
3506
3507 ac_build_endif(&ctx->ac, 6504);
3508 }
3509
3510 /* Store the tessellation factors. */
3511 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3512 MIN2(stride, 4), byteoffset, tf_base,
3513 tf_offset, ac_glc);
3514 if (vec1)
3515 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3516 stride - 4, byteoffset, tf_base,
3517 16 + tf_offset, ac_glc);
3518
3519 //store to offchip for TES to read - only if TES reads them
3520 if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
3521 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3522 LLVMValueRef tf_inner_offset;
3523 unsigned param_outer, param_inner;
3524
3525 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3526 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3527 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3528
3529 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3530 util_next_power_of_two(outer_comps));
3531
3532 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3533 outer_comps, tf_outer_offset,
3534 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3535 0, ac_glc);
3536 if (inner_comps) {
3537 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3538 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3539 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3540
3541 inner_vec = inner_comps == 1 ? inner[0] :
3542 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3543 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3544 inner_comps, tf_inner_offset,
3545 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3546 0, ac_glc);
3547 }
3548 }
3549
3550 ac_build_endif(&ctx->ac, 6503);
3551 }
3552
3553 static void
3554 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3555 {
3556 write_tess_factors(ctx);
3557 }
3558
3559 static bool
3560 si_export_mrt_color(struct radv_shader_context *ctx,
3561 LLVMValueRef *color, unsigned index,
3562 struct ac_export_args *args)
3563 {
3564 /* Export */
3565 si_llvm_init_export_args(ctx, color, 0xf,
3566 V_008DFC_SQ_EXP_MRT + index, args);
3567 if (!args->enabled_channels)
3568 return false; /* unnecessary NULL export */
3569
3570 return true;
3571 }
3572
3573 static void
3574 radv_export_mrt_z(struct radv_shader_context *ctx,
3575 LLVMValueRef depth, LLVMValueRef stencil,
3576 LLVMValueRef samplemask)
3577 {
3578 struct ac_export_args args;
3579
3580 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3581
3582 ac_build_export(&ctx->ac, &args);
3583 }
3584
3585 static void
3586 handle_fs_outputs_post(struct radv_shader_context *ctx)
3587 {
3588 unsigned index = 0;
3589 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3590 struct ac_export_args color_args[8];
3591
3592 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3593 LLVMValueRef values[4];
3594
3595 if (!(ctx->output_mask & (1ull << i)))
3596 continue;
3597
3598 if (i < FRAG_RESULT_DATA0)
3599 continue;
3600
3601 for (unsigned j = 0; j < 4; j++)
3602 values[j] = ac_to_float(&ctx->ac,
3603 radv_load_output(ctx, i, j));
3604
3605 bool ret = si_export_mrt_color(ctx, values,
3606 i - FRAG_RESULT_DATA0,
3607 &color_args[index]);
3608 if (ret)
3609 index++;
3610 }
3611
3612 /* Process depth, stencil, samplemask. */
3613 if (ctx->args->shader_info->ps.writes_z) {
3614 depth = ac_to_float(&ctx->ac,
3615 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3616 }
3617 if (ctx->args->shader_info->ps.writes_stencil) {
3618 stencil = ac_to_float(&ctx->ac,
3619 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3620 }
3621 if (ctx->args->shader_info->ps.writes_sample_mask) {
3622 samplemask = ac_to_float(&ctx->ac,
3623 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3624 }
3625
3626 /* Set the DONE bit on last non-null color export only if Z isn't
3627 * exported.
3628 */
3629 if (index > 0 &&
3630 !ctx->args->shader_info->ps.writes_z &&
3631 !ctx->args->shader_info->ps.writes_stencil &&
3632 !ctx->args->shader_info->ps.writes_sample_mask) {
3633 unsigned last = index - 1;
3634
3635 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3636 color_args[last].done = 1; /* DONE bit */
3637 }
3638
3639 /* Export PS outputs. */
3640 for (unsigned i = 0; i < index; i++)
3641 ac_build_export(&ctx->ac, &color_args[i]);
3642
3643 if (depth || stencil || samplemask)
3644 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3645 else if (!index)
3646 ac_build_export_null(&ctx->ac);
3647 }
3648
3649 static void
3650 emit_gs_epilogue(struct radv_shader_context *ctx)
3651 {
3652 if (ctx->args->options->key.vs_common_out.as_ngg) {
3653 gfx10_ngg_gs_emit_epilogue_1(ctx);
3654 return;
3655 }
3656
3657 if (ctx->ac.chip_class >= GFX10)
3658 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3659
3660 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3661 }
3662
3663 static void
3664 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3665 LLVMValueRef *addrs)
3666 {
3667 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3668
3669 switch (ctx->stage) {
3670 case MESA_SHADER_VERTEX:
3671 if (ctx->args->options->key.vs_common_out.as_ls)
3672 handle_ls_outputs_post(ctx);
3673 else if (ctx->args->options->key.vs_common_out.as_es)
3674 handle_es_outputs_post(ctx, &ctx->args->shader_info->vs.es_info);
3675 else if (ctx->args->options->key.vs_common_out.as_ngg)
3676 handle_ngg_outputs_post_1(ctx);
3677 else
3678 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3679 ctx->args->options->key.vs_common_out.export_clip_dists,
3680 &ctx->args->shader_info->vs.outinfo);
3681 break;
3682 case MESA_SHADER_FRAGMENT:
3683 handle_fs_outputs_post(ctx);
3684 break;
3685 case MESA_SHADER_GEOMETRY:
3686 emit_gs_epilogue(ctx);
3687 break;
3688 case MESA_SHADER_TESS_CTRL:
3689 handle_tcs_outputs_post(ctx);
3690 break;
3691 case MESA_SHADER_TESS_EVAL:
3692 if (ctx->args->options->key.vs_common_out.as_es)
3693 handle_es_outputs_post(ctx, &ctx->args->shader_info->tes.es_info);
3694 else if (ctx->args->options->key.vs_common_out.as_ngg)
3695 handle_ngg_outputs_post_1(ctx);
3696 else
3697 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3698 ctx->args->options->key.vs_common_out.export_clip_dists,
3699 &ctx->args->shader_info->tes.outinfo);
3700 break;
3701 default:
3702 break;
3703 }
3704 }
3705
3706 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3707 LLVMPassManagerRef passmgr,
3708 const struct radv_nir_compiler_options *options)
3709 {
3710 LLVMRunPassManager(passmgr, ctx->ac.module);
3711 LLVMDisposeBuilder(ctx->ac.builder);
3712
3713 ac_llvm_context_dispose(&ctx->ac);
3714 }
3715
3716 static void
3717 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3718 {
3719 struct radv_vs_output_info *outinfo;
3720
3721 switch (ctx->stage) {
3722 case MESA_SHADER_FRAGMENT:
3723 case MESA_SHADER_COMPUTE:
3724 case MESA_SHADER_TESS_CTRL:
3725 case MESA_SHADER_GEOMETRY:
3726 return;
3727 case MESA_SHADER_VERTEX:
3728 if (ctx->args->options->key.vs_common_out.as_ls ||
3729 ctx->args->options->key.vs_common_out.as_es)
3730 return;
3731 outinfo = &ctx->args->shader_info->vs.outinfo;
3732 break;
3733 case MESA_SHADER_TESS_EVAL:
3734 if (ctx->args->options->key.vs_common_out.as_es)
3735 return;
3736 outinfo = &ctx->args->shader_info->tes.outinfo;
3737 break;
3738 default:
3739 unreachable("Unhandled shader type");
3740 }
3741
3742 ac_optimize_vs_outputs(&ctx->ac,
3743 ctx->main_function,
3744 outinfo->vs_output_param_offset,
3745 VARYING_SLOT_MAX,
3746 &outinfo->param_exports);
3747 }
3748
3749 static void
3750 ac_setup_rings(struct radv_shader_context *ctx)
3751 {
3752 if (ctx->args->options->chip_class <= GFX8 &&
3753 (ctx->stage == MESA_SHADER_GEOMETRY ||
3754 ctx->args->options->key.vs_common_out.as_es || ctx->args->options->key.vs_common_out.as_es)) {
3755 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3756 : RING_ESGS_VS;
3757 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3758
3759 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3760 ctx->ring_offsets,
3761 offset);
3762 }
3763
3764 if (ctx->args->is_gs_copy_shader) {
3765 ctx->gsvs_ring[0] =
3766 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3767 LLVMConstInt(ctx->ac.i32,
3768 RING_GSVS_VS, false));
3769 }
3770
3771 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3772 /* The conceptual layout of the GSVS ring is
3773 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3774 * but the real memory layout is swizzled across
3775 * threads:
3776 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3777 * t16v0c0 ..
3778 * Override the buffer descriptor accordingly.
3779 */
3780 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3781 uint64_t stream_offset = 0;
3782 unsigned num_records = ctx->ac.wave_size;
3783 LLVMValueRef base_ring;
3784
3785 base_ring =
3786 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3787 LLVMConstInt(ctx->ac.i32,
3788 RING_GSVS_GS, false));
3789
3790 for (unsigned stream = 0; stream < 4; stream++) {
3791 unsigned num_components, stride;
3792 LLVMValueRef ring, tmp;
3793
3794 num_components =
3795 ctx->args->shader_info->gs.num_stream_output_components[stream];
3796
3797 if (!num_components)
3798 continue;
3799
3800 stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
3801
3802 /* Limit on the stride field for <= GFX7. */
3803 assert(stride < (1 << 14));
3804
3805 ring = LLVMBuildBitCast(ctx->ac.builder,
3806 base_ring, v2i64, "");
3807 tmp = LLVMBuildExtractElement(ctx->ac.builder,
3808 ring, ctx->ac.i32_0, "");
3809 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
3810 LLVMConstInt(ctx->ac.i64,
3811 stream_offset, 0), "");
3812 ring = LLVMBuildInsertElement(ctx->ac.builder,
3813 ring, tmp, ctx->ac.i32_0, "");
3814
3815 stream_offset += stride * ctx->ac.wave_size;
3816
3817 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
3818 ctx->ac.v4i32, "");
3819
3820 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3821 ctx->ac.i32_1, "");
3822 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3823 LLVMConstInt(ctx->ac.i32,
3824 S_008F04_STRIDE(stride), false), "");
3825 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3826 ctx->ac.i32_1, "");
3827
3828 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3829 LLVMConstInt(ctx->ac.i32,
3830 num_records, false),
3831 LLVMConstInt(ctx->ac.i32, 2, false), "");
3832
3833 ctx->gsvs_ring[stream] = ring;
3834 }
3835 }
3836
3837 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3838 ctx->stage == MESA_SHADER_TESS_EVAL) {
3839 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3840 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3841 }
3842 }
3843
3844 unsigned
3845 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
3846 gl_shader_stage stage,
3847 const struct nir_shader *nir)
3848 {
3849 const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
3850 unsigned sizes[3];
3851 for (unsigned i = 0; i < 3; i++)
3852 sizes[i] = nir ? nir->info.cs.local_size[i] : backup_sizes[i];
3853 return radv_get_max_workgroup_size(chip_class, stage, sizes);
3854 }
3855
3856 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3857 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3858 {
3859 LLVMValueRef count =
3860 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
3861 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3862 ctx->ac.i32_0, "");
3863 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3864 ac_get_arg(&ctx->ac, ctx->args->rel_auto_id),
3865 ctx->abi.instance_id, "");
3866 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3867 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
3868 ctx->rel_auto_id,
3869 "");
3870 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3871 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_patch_id),
3872 ctx->abi.vertex_id, "");
3873 }
3874
3875 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx, bool merged)
3876 {
3877 if (merged) {
3878 for(int i = 5; i >= 0; --i) {
3879 ctx->gs_vtx_offset[i] =
3880 ac_unpack_param(&ctx->ac,
3881 ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i & ~1]),
3882 (i & 1) * 16, 16);
3883 }
3884
3885 ctx->gs_wave_id = ac_unpack_param(&ctx->ac,
3886 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info),
3887 16, 8);
3888 } else {
3889 for (int i = 0; i < 6; i++)
3890 ctx->gs_vtx_offset[i] = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i]);
3891 ctx->gs_wave_id = ac_get_arg(&ctx->ac, ctx->args->gs_wave_id);
3892 }
3893 }
3894
3895 /* Ensure that the esgs ring is declared.
3896 *
3897 * We declare it with 64KB alignment as a hint that the
3898 * pointer value will always be 0.
3899 */
3900 static void declare_esgs_ring(struct radv_shader_context *ctx)
3901 {
3902 if (ctx->esgs_ring)
3903 return;
3904
3905 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
3906
3907 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
3908 ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
3909 "esgs_ring",
3910 AC_ADDR_SPACE_LDS);
3911 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
3912 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
3913 }
3914
3915 static
3916 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
3917 struct nir_shader *const *shaders,
3918 int shader_count,
3919 const struct radv_shader_args *args)
3920 {
3921 struct radv_shader_context ctx = {0};
3922 ctx.args = args;
3923
3924 enum ac_float_mode float_mode = AC_FLOAT_MODE_DEFAULT;
3925
3926 if (args->shader_info->float_controls_mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32) {
3927 float_mode = AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO;
3928 }
3929
3930 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
3931 args->options->family, float_mode,
3932 args->shader_info->wave_size, 64);
3933 ctx.context = ctx.ac.context;
3934
3935 ctx.max_workgroup_size = 0;
3936 for (int i = 0; i < shader_count; ++i) {
3937 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3938 radv_nir_get_max_workgroup_size(args->options->chip_class,
3939 shaders[i]->info.stage,
3940 shaders[i]));
3941 }
3942
3943 if (ctx.ac.chip_class >= GFX10) {
3944 if (is_pre_gs_stage(shaders[0]->info.stage) &&
3945 args->options->key.vs_common_out.as_ngg) {
3946 ctx.max_workgroup_size = 128;
3947 }
3948 }
3949
3950 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2);
3951
3952 ctx.abi.inputs = &ctx.inputs[0];
3953 ctx.abi.emit_outputs = handle_shader_outputs_post;
3954 ctx.abi.emit_vertex = visit_emit_vertex;
3955 ctx.abi.load_ubo = radv_load_ubo;
3956 ctx.abi.load_ssbo = radv_load_ssbo;
3957 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3958 ctx.abi.load_resource = radv_load_resource;
3959 ctx.abi.clamp_shadow_reference = false;
3960 ctx.abi.robust_buffer_access = args->options->robust_buffer_access;
3961
3962 bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && args->options->key.vs_common_out.as_ngg;
3963 if (shader_count >= 2 || is_ngg)
3964 ac_init_exec_full_mask(&ctx.ac);
3965
3966 if (args->ac.vertex_id.used)
3967 ctx.abi.vertex_id = ac_get_arg(&ctx.ac, args->ac.vertex_id);
3968 if (args->rel_auto_id.used)
3969 ctx.rel_auto_id = ac_get_arg(&ctx.ac, args->rel_auto_id);
3970 if (args->ac.instance_id.used)
3971 ctx.abi.instance_id = ac_get_arg(&ctx.ac, args->ac.instance_id);
3972
3973 if (args->options->has_ls_vgpr_init_bug &&
3974 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3975 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3976
3977 if (is_ngg) {
3978 /* Declare scratch space base for streamout and vertex
3979 * compaction. Whether space is actually allocated is
3980 * determined during linking / PM4 creation.
3981 *
3982 * Add an extra dword per vertex to ensure an odd stride, which
3983 * avoids bank conflicts for SoA accesses.
3984 */
3985 if (!args->options->key.vs_common_out.as_ngg_passthrough)
3986 declare_esgs_ring(&ctx);
3987
3988 /* This is really only needed when streamout and / or vertex
3989 * compaction is enabled.
3990 */
3991 if (args->shader_info->so.num_outputs) {
3992 LLVMTypeRef asi32 = LLVMArrayType(ctx.ac.i32, 8);
3993 ctx.gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx.ac.module,
3994 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
3995 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(asi32));
3996 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
3997 }
3998 }
3999
4000 for(int i = 0; i < shader_count; ++i) {
4001 ctx.stage = shaders[i]->info.stage;
4002 ctx.shader = shaders[i];
4003 ctx.output_mask = 0;
4004
4005 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
4006 for (int i = 0; i < 4; i++) {
4007 ctx.gs_next_vertex[i] =
4008 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4009 }
4010 if (args->options->key.vs_common_out.as_ngg) {
4011 for (unsigned i = 0; i < 4; ++i) {
4012 ctx.gs_curprim_verts[i] =
4013 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4014 ctx.gs_generated_prims[i] =
4015 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4016 }
4017
4018 unsigned scratch_size = 8;
4019 if (args->shader_info->so.num_outputs)
4020 scratch_size = 44;
4021
4022 LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, scratch_size);
4023 ctx.gs_ngg_scratch =
4024 LLVMAddGlobalInAddressSpace(ctx.ac.module,
4025 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4026 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
4027 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4028
4029 ctx.gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4030 LLVMArrayType(ctx.ac.i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
4031 LLVMSetLinkage(ctx.gs_ngg_emit, LLVMExternalLinkage);
4032 LLVMSetAlignment(ctx.gs_ngg_emit, 4);
4033 }
4034
4035 ctx.abi.load_inputs = load_gs_input;
4036 ctx.abi.emit_primitive = visit_end_primitive;
4037 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4038 ctx.abi.load_tess_varyings = load_tcs_varyings;
4039 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4040 ctx.abi.store_tcs_outputs = store_tcs_output;
4041 if (shader_count == 1)
4042 ctx.tcs_num_inputs = args->options->key.tcs.num_inputs;
4043 else
4044 ctx.tcs_num_inputs = util_last_bit64(args->shader_info->vs.ls_outputs_written);
4045 ctx.tcs_num_patches =
4046 get_tcs_num_patches(
4047 ctx.args->options->key.tcs.input_vertices,
4048 ctx.shader->info.tess.tcs_vertices_out,
4049 ctx.tcs_num_inputs,
4050 ctx.args->shader_info->tcs.outputs_written,
4051 ctx.args->shader_info->tcs.patch_outputs_written,
4052 ctx.args->options->tess_offchip_block_dw_size,
4053 ctx.args->options->chip_class,
4054 ctx.args->options->family);
4055 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
4056 ctx.abi.load_tess_varyings = load_tes_input;
4057 ctx.abi.load_tess_coord = load_tess_coord;
4058 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4059 ctx.tcs_num_patches = args->options->key.tes.num_patches;
4060 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
4061 ctx.abi.load_base_vertex = radv_load_base_vertex;
4062 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
4063 ctx.abi.load_sample_position = load_sample_position;
4064 ctx.abi.load_sample_mask_in = load_sample_mask_in;
4065 }
4066
4067 if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
4068 args->options->key.vs_common_out.as_ngg &&
4069 args->options->key.vs_common_out.export_prim_id) {
4070 declare_esgs_ring(&ctx);
4071 }
4072
4073 bool nested_barrier = false;
4074
4075 if (i) {
4076 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4077 args->options->key.vs_common_out.as_ngg) {
4078 gfx10_ngg_gs_emit_prologue(&ctx);
4079 nested_barrier = false;
4080 } else {
4081 nested_barrier = true;
4082 }
4083 }
4084
4085 if (nested_barrier) {
4086 /* Execute a barrier before the second shader in
4087 * a merged shader.
4088 *
4089 * Execute the barrier inside the conditional block,
4090 * so that empty waves can jump directly to s_endpgm,
4091 * which will also signal the barrier.
4092 *
4093 * This is possible in gfx9, because an empty wave
4094 * for the second shader does not participate in
4095 * the epilogue. With NGG, empty waves may still
4096 * be required to export data (e.g. GS output vertices),
4097 * so we cannot let them exit early.
4098 *
4099 * If the shader is TCS and the TCS epilog is present
4100 * and contains a barrier, it will wait there and then
4101 * reach s_endpgm.
4102 */
4103 ac_emit_barrier(&ctx.ac, ctx.stage);
4104 }
4105
4106 nir_foreach_variable(variable, &shaders[i]->outputs)
4107 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
4108
4109 ac_setup_rings(&ctx);
4110
4111 LLVMBasicBlockRef merge_block = NULL;
4112 if (shader_count >= 2 || is_ngg) {
4113 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
4114 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4115 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4116
4117 LLVMValueRef count =
4118 ac_unpack_param(&ctx.ac,
4119 ac_get_arg(&ctx.ac, args->merged_wave_info),
4120 8 * i, 8);
4121 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
4122 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
4123 thread_id, count, "");
4124 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
4125
4126 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
4127 }
4128
4129 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
4130 prepare_interp_optimize(&ctx, shaders[i]);
4131 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
4132 handle_vs_inputs(&ctx, shaders[i]);
4133 else if(shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
4134 prepare_gs_input_vgprs(&ctx, shader_count >= 2);
4135
4136 ac_nir_translate(&ctx.ac, &ctx.abi, &args->ac, shaders[i]);
4137
4138 if (shader_count >= 2 || is_ngg) {
4139 LLVMBuildBr(ctx.ac.builder, merge_block);
4140 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
4141 }
4142
4143 /* This needs to be outside the if wrapping the shader body, as sometimes
4144 * the HW generates waves with 0 es/vs threads. */
4145 if (is_pre_gs_stage(shaders[i]->info.stage) &&
4146 args->options->key.vs_common_out.as_ngg &&
4147 i == shader_count - 1) {
4148 handle_ngg_outputs_post_2(&ctx);
4149 } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4150 args->options->key.vs_common_out.as_ngg) {
4151 gfx10_ngg_gs_emit_epilogue_2(&ctx);
4152 }
4153
4154 if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4155 args->shader_info->tcs.num_patches = ctx.tcs_num_patches;
4156 args->shader_info->tcs.lds_size =
4157 calculate_tess_lds_size(
4158 ctx.args->options->key.tcs.input_vertices,
4159 ctx.shader->info.tess.tcs_vertices_out,
4160 ctx.tcs_num_inputs,
4161 ctx.tcs_num_patches,
4162 ctx.args->shader_info->tcs.outputs_written,
4163 ctx.args->shader_info->tcs.patch_outputs_written);
4164 }
4165 }
4166
4167 LLVMBuildRetVoid(ctx.ac.builder);
4168
4169 if (args->options->dump_preoptir) {
4170 fprintf(stderr, "%s LLVM IR:\n\n",
4171 radv_get_shader_name(args->shader_info,
4172 shaders[shader_count - 1]->info.stage));
4173 ac_dump_module(ctx.ac.module);
4174 fprintf(stderr, "\n");
4175 }
4176
4177 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4178
4179 if (shader_count == 1)
4180 ac_nir_eliminate_const_vs_outputs(&ctx);
4181
4182 if (args->options->dump_shader) {
4183 args->shader_info->private_mem_vgprs =
4184 ac_count_scratch_private_memory(ctx.main_function);
4185 }
4186
4187 return ctx.ac.module;
4188 }
4189
4190 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4191 {
4192 unsigned *retval = (unsigned *)context;
4193 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4194 char *description = LLVMGetDiagInfoDescription(di);
4195
4196 if (severity == LLVMDSError) {
4197 *retval = 1;
4198 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4199 description);
4200 }
4201
4202 LLVMDisposeMessage(description);
4203 }
4204
4205 static unsigned radv_llvm_compile(LLVMModuleRef M,
4206 char **pelf_buffer, size_t *pelf_size,
4207 struct ac_llvm_compiler *ac_llvm)
4208 {
4209 unsigned retval = 0;
4210 LLVMContextRef llvm_ctx;
4211
4212 /* Setup Diagnostic Handler*/
4213 llvm_ctx = LLVMGetModuleContext(M);
4214
4215 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4216 &retval);
4217
4218 /* Compile IR*/
4219 if (!radv_compile_to_elf(ac_llvm, M, pelf_buffer, pelf_size))
4220 retval = 1;
4221 return retval;
4222 }
4223
4224 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
4225 LLVMModuleRef llvm_module,
4226 struct radv_shader_binary **rbinary,
4227 gl_shader_stage stage,
4228 const char *name,
4229 const struct radv_nir_compiler_options *options)
4230 {
4231 char *elf_buffer = NULL;
4232 size_t elf_size = 0;
4233 char *llvm_ir_string = NULL;
4234
4235 if (options->dump_shader) {
4236 fprintf(stderr, "%s LLVM IR:\n\n", name);
4237 ac_dump_module(llvm_module);
4238 fprintf(stderr, "\n");
4239 }
4240
4241 if (options->record_ir) {
4242 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
4243 llvm_ir_string = strdup(llvm_ir);
4244 LLVMDisposeMessage(llvm_ir);
4245 }
4246
4247 int v = radv_llvm_compile(llvm_module, &elf_buffer, &elf_size, ac_llvm);
4248 if (v) {
4249 fprintf(stderr, "compile failed\n");
4250 }
4251
4252 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4253 LLVMDisposeModule(llvm_module);
4254 LLVMContextDispose(ctx);
4255
4256 size_t llvm_ir_size = llvm_ir_string ? strlen(llvm_ir_string) : 0;
4257 size_t alloc_size = sizeof(struct radv_shader_binary_rtld) + elf_size + llvm_ir_size + 1;
4258 struct radv_shader_binary_rtld *rbin = calloc(1, alloc_size);
4259 memcpy(rbin->data, elf_buffer, elf_size);
4260 if (llvm_ir_string)
4261 memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
4262
4263 rbin->base.type = RADV_BINARY_TYPE_RTLD;
4264 rbin->base.stage = stage;
4265 rbin->base.total_size = alloc_size;
4266 rbin->elf_size = elf_size;
4267 rbin->llvm_ir_size = llvm_ir_size;
4268 *rbinary = &rbin->base;
4269
4270 free(llvm_ir_string);
4271 free(elf_buffer);
4272 }
4273
4274 void
4275 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
4276 struct radv_shader_binary **rbinary,
4277 const struct radv_shader_args *args,
4278 struct nir_shader *const *nir,
4279 int nir_count)
4280 {
4281
4282 LLVMModuleRef llvm_module;
4283
4284 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, args);
4285
4286 ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
4287 nir[nir_count - 1]->info.stage,
4288 radv_get_shader_name(args->shader_info,
4289 nir[nir_count - 1]->info.stage),
4290 args->options);
4291
4292 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4293 if (args->options->chip_class >= GFX9) {
4294 if (nir_count == 2 &&
4295 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
4296 args->shader_info->gs.es_type = nir[0]->info.stage;
4297 }
4298 }
4299 }
4300
4301 static void
4302 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
4303 {
4304 LLVMValueRef vtx_offset =
4305 LLVMBuildMul(ctx->ac.builder, ac_get_arg(&ctx->ac, ctx->args->ac.vertex_id),
4306 LLVMConstInt(ctx->ac.i32, 4, false), "");
4307 LLVMValueRef stream_id;
4308
4309 /* Fetch the vertex stream ID. */
4310 if (!ctx->args->options->use_ngg_streamout &&
4311 ctx->args->shader_info->so.num_outputs) {
4312 stream_id =
4313 ac_unpack_param(&ctx->ac,
4314 ac_get_arg(&ctx->ac,
4315 ctx->args->streamout_config),
4316 24, 2);
4317 } else {
4318 stream_id = ctx->ac.i32_0;
4319 }
4320
4321 LLVMBasicBlockRef end_bb;
4322 LLVMValueRef switch_inst;
4323
4324 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
4325 ctx->main_function, "end");
4326 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
4327
4328 for (unsigned stream = 0; stream < 4; stream++) {
4329 unsigned num_components =
4330 ctx->args->shader_info->gs.num_stream_output_components[stream];
4331 LLVMBasicBlockRef bb;
4332 unsigned offset;
4333
4334 if (stream > 0 && !num_components)
4335 continue;
4336
4337 if (stream > 0 && !ctx->args->shader_info->so.num_outputs)
4338 continue;
4339
4340 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
4341 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
4342 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
4343
4344 offset = 0;
4345 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4346 unsigned output_usage_mask =
4347 ctx->args->shader_info->gs.output_usage_mask[i];
4348 unsigned output_stream =
4349 ctx->args->shader_info->gs.output_streams[i];
4350 int length = util_last_bit(output_usage_mask);
4351
4352 if (!(ctx->output_mask & (1ull << i)) ||
4353 output_stream != stream)
4354 continue;
4355
4356 for (unsigned j = 0; j < length; j++) {
4357 LLVMValueRef value, soffset;
4358
4359 if (!(output_usage_mask & (1 << j)))
4360 continue;
4361
4362 soffset = LLVMConstInt(ctx->ac.i32,
4363 offset *
4364 ctx->shader->info.gs.vertices_out * 16 * 4, false);
4365
4366 offset++;
4367
4368 value = ac_build_buffer_load(&ctx->ac,
4369 ctx->gsvs_ring[0],
4370 1, ctx->ac.i32_0,
4371 vtx_offset, soffset,
4372 0, ac_glc | ac_slc, true, false);
4373
4374 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4375 if (ac_get_type_size(type) == 2) {
4376 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
4377 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
4378 }
4379
4380 LLVMBuildStore(ctx->ac.builder,
4381 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4382 }
4383 }
4384
4385 if (!ctx->args->options->use_ngg_streamout &&
4386 ctx->args->shader_info->so.num_outputs)
4387 radv_emit_streamout(ctx, stream);
4388
4389 if (stream == 0) {
4390 handle_vs_outputs_post(ctx, false, true,
4391 &ctx->args->shader_info->vs.outinfo);
4392 }
4393
4394 LLVMBuildBr(ctx->ac.builder, end_bb);
4395 }
4396
4397 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
4398 }
4399
4400 void
4401 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
4402 struct nir_shader *geom_shader,
4403 struct radv_shader_binary **rbinary,
4404 const struct radv_shader_args *args)
4405 {
4406 struct radv_shader_context ctx = {0};
4407 ctx.args = args;
4408
4409 assert(args->is_gs_copy_shader);
4410
4411 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
4412 args->options->family, AC_FLOAT_MODE_DEFAULT, 64, 64);
4413 ctx.context = ctx.ac.context;
4414
4415 ctx.stage = MESA_SHADER_VERTEX;
4416 ctx.shader = geom_shader;
4417
4418 create_function(&ctx, MESA_SHADER_VERTEX, false);
4419
4420 ac_setup_rings(&ctx);
4421
4422 nir_foreach_variable(variable, &geom_shader->outputs) {
4423 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
4424 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
4425 variable, MESA_SHADER_VERTEX);
4426 }
4427
4428 ac_gs_copy_shader_emit(&ctx);
4429
4430 LLVMBuildRetVoid(ctx.ac.builder);
4431
4432 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4433
4434 ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
4435 MESA_SHADER_VERTEX, "GS Copy Shader", args->options);
4436 (*rbinary)->is_gs_copy_shader = true;
4437
4438 }