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aco: rework lower_to_cssa()
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
32 #include "nir/nir.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36 #include <llvm-c/Transforms/Scalar.h>
37 #include <llvm-c/Transforms/Utils.h>
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct radv_shader_context {
50 struct ac_llvm_context ac;
51 const struct nir_shader *shader;
52 struct ac_shader_abi abi;
53 const struct radv_shader_args *args;
54
55 gl_shader_stage stage;
56
57 unsigned max_workgroup_size;
58 LLVMContextRef context;
59 LLVMValueRef main_function;
60
61 LLVMValueRef descriptor_sets[MAX_SETS];
62
63 LLVMValueRef ring_offsets;
64
65 LLVMValueRef rel_auto_id;
66
67 LLVMValueRef gs_wave_id;
68 LLVMValueRef gs_vtx_offset[6];
69
70 LLVMValueRef esgs_ring;
71 LLVMValueRef gsvs_ring[4];
72 LLVMValueRef hs_ring_tess_offchip;
73 LLVMValueRef hs_ring_tess_factor;
74
75 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
76
77 uint64_t output_mask;
78
79 LLVMValueRef gs_next_vertex[4];
80 LLVMValueRef gs_curprim_verts[4];
81 LLVMValueRef gs_generated_prims[4];
82 LLVMValueRef gs_ngg_emit;
83 LLVMValueRef gs_ngg_scratch;
84
85 uint32_t tcs_num_inputs;
86 uint32_t tcs_num_patches;
87
88 LLVMValueRef vertexptr; /* GFX10 only */
89 };
90
91 struct radv_shader_output_values {
92 LLVMValueRef values[4];
93 unsigned slot_name;
94 unsigned slot_index;
95 unsigned usage_mask;
96 };
97
98 static inline struct radv_shader_context *
99 radv_shader_context_from_abi(struct ac_shader_abi *abi)
100 {
101 struct radv_shader_context *ctx = NULL;
102 return container_of(abi, ctx, abi);
103 }
104
105 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
106 {
107 switch (ctx->stage) {
108 case MESA_SHADER_TESS_CTRL:
109 return ac_unpack_param(&ctx->ac,
110 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
111 0, 8);
112 case MESA_SHADER_TESS_EVAL:
113 return ac_get_arg(&ctx->ac, ctx->args->tes_rel_patch_id);
114 break;
115 default:
116 unreachable("Illegal stage");
117 }
118 }
119
120 static unsigned
121 get_tcs_num_patches(struct radv_shader_context *ctx)
122 {
123 unsigned num_tcs_input_cp = ctx->args->options->key.tcs.input_vertices;
124 unsigned num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
125 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
126 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
127 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
128 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
129 uint32_t output_vertex_size = num_tcs_outputs * 16;
130 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
131 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
132 unsigned num_patches;
133 unsigned hardware_lds_size;
134
135 /* Ensure that we only need one wave per SIMD so we don't need to check
136 * resource usage. Also ensures that the number of tcs in and out
137 * vertices per threadgroup are at most 256.
138 */
139 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
140 /* Make sure that the data fits in LDS. This assumes the shaders only
141 * use LDS for the inputs and outputs.
142 */
143 hardware_lds_size = 32768;
144
145 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
146 * threadgroup, even though there is more than 32 KiB LDS.
147 *
148 * Test: dEQP-VK.tessellation.shader_input_output.barrier
149 */
150 if (ctx->args->options->chip_class >= GFX7 && ctx->args->options->family != CHIP_STONEY)
151 hardware_lds_size = 65536;
152
153 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
154 /* Make sure the output data fits in the offchip buffer */
155 num_patches = MIN2(num_patches, (ctx->args->options->tess_offchip_block_dw_size * 4) / output_patch_size);
156 /* Not necessary for correctness, but improves performance. The
157 * specific value is taken from the proprietary driver.
158 */
159 num_patches = MIN2(num_patches, 40);
160
161 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
162 if (ctx->args->options->chip_class == GFX6) {
163 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
164 num_patches = MIN2(num_patches, one_wave);
165 }
166 return num_patches;
167 }
168
169 static unsigned
170 calculate_tess_lds_size(struct radv_shader_context *ctx)
171 {
172 unsigned num_tcs_input_cp = ctx->args->options->key.tcs.input_vertices;
173 unsigned num_tcs_output_cp;
174 unsigned num_tcs_outputs, num_tcs_patch_outputs;
175 unsigned input_vertex_size, output_vertex_size;
176 unsigned input_patch_size, output_patch_size;
177 unsigned pervertex_output_patch_size;
178 unsigned output_patch0_offset;
179 unsigned num_patches;
180 unsigned lds_size;
181
182 num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
183 num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
184 num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
185
186 input_vertex_size = ctx->tcs_num_inputs * 16;
187 output_vertex_size = num_tcs_outputs * 16;
188
189 input_patch_size = num_tcs_input_cp * input_vertex_size;
190
191 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
192 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
193
194 num_patches = ctx->tcs_num_patches;
195 output_patch0_offset = input_patch_size * num_patches;
196
197 lds_size = output_patch0_offset + output_patch_size * num_patches;
198 return lds_size;
199 }
200
201 /* Tessellation shaders pass outputs to the next shader using LDS.
202 *
203 * LS outputs = TCS inputs
204 * TCS outputs = TES inputs
205 *
206 * The LDS layout is:
207 * - TCS inputs for patch 0
208 * - TCS inputs for patch 1
209 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
210 * - ...
211 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
212 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
213 * - TCS outputs for patch 1
214 * - Per-patch TCS outputs for patch 1
215 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
216 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
217 * - ...
218 *
219 * All three shaders VS(LS), TCS, TES share the same LDS space.
220 */
221 static LLVMValueRef
222 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
223 {
224 assert(ctx->stage == MESA_SHADER_TESS_CTRL);
225 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
226 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
227
228 input_patch_size /= 4;
229 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
230 }
231
232 static LLVMValueRef
233 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
234 {
235 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
236 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
237 uint32_t output_vertex_size = num_tcs_outputs * 16;
238 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
239 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
240 output_patch_size /= 4;
241 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
242 }
243
244 static LLVMValueRef
245 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
246 {
247 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
248 uint32_t output_vertex_size = num_tcs_outputs * 16;
249 output_vertex_size /= 4;
250 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
251 }
252
253 static LLVMValueRef
254 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
255 {
256 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
257 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
258 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
259 uint32_t output_patch0_offset = input_patch_size;
260 unsigned num_patches = ctx->tcs_num_patches;
261
262 output_patch0_offset *= num_patches;
263 output_patch0_offset /= 4;
264 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
265 }
266
267 static LLVMValueRef
268 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
269 {
270 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
271 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
272 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
273 uint32_t output_patch0_offset = input_patch_size;
274
275 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
276 uint32_t output_vertex_size = num_tcs_outputs * 16;
277 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
278 unsigned num_patches = ctx->tcs_num_patches;
279
280 output_patch0_offset *= num_patches;
281 output_patch0_offset += pervertex_output_patch_size;
282 output_patch0_offset /= 4;
283 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
284 }
285
286 static LLVMValueRef
287 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
288 {
289 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
290 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
291
292 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
293 }
294
295 static LLVMValueRef
296 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
297 {
298 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
299 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
300 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
301
302 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
303 patch0_offset);
304 }
305
306 static LLVMValueRef
307 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
308 {
309 LLVMValueRef patch0_patch_data_offset =
310 get_tcs_out_patch0_patch_data_offset(ctx);
311 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
312 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
313
314 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
315 patch0_patch_data_offset);
316 }
317
318 static LLVMValueRef
319 create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module,
320 LLVMBuilderRef builder,
321 const struct ac_shader_args *args,
322 enum ac_llvm_calling_convention convention,
323 unsigned max_workgroup_size,
324 const struct radv_nir_compiler_options *options)
325 {
326 LLVMValueRef main_function =
327 ac_build_main(args, ctx, convention, "main", ctx->voidt, module);
328
329 if (options->address32_hi) {
330 ac_llvm_add_target_dep_function_attr(main_function,
331 "amdgpu-32bit-address-high-bits",
332 options->address32_hi);
333 }
334
335 ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
336
337 return main_function;
338 }
339
340 static void
341 load_descriptor_sets(struct radv_shader_context *ctx)
342 {
343 uint32_t mask = ctx->args->shader_info->desc_set_used_mask;
344 if (ctx->args->shader_info->need_indirect_descriptor_sets) {
345 LLVMValueRef desc_sets =
346 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[0]);
347 while (mask) {
348 int i = u_bit_scan(&mask);
349
350 ctx->descriptor_sets[i] =
351 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
352 LLVMConstInt(ctx->ac.i32, i, false));
353
354 }
355 } else {
356 while (mask) {
357 int i = u_bit_scan(&mask);
358
359 ctx->descriptor_sets[i] =
360 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[i]);
361 }
362 }
363 }
364
365 static enum ac_llvm_calling_convention
366 get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage)
367 {
368 switch (stage) {
369 case MESA_SHADER_VERTEX:
370 case MESA_SHADER_TESS_EVAL:
371 return AC_LLVM_AMDGPU_VS;
372 break;
373 case MESA_SHADER_GEOMETRY:
374 return AC_LLVM_AMDGPU_GS;
375 break;
376 case MESA_SHADER_TESS_CTRL:
377 return AC_LLVM_AMDGPU_HS;
378 break;
379 case MESA_SHADER_FRAGMENT:
380 return AC_LLVM_AMDGPU_PS;
381 break;
382 case MESA_SHADER_COMPUTE:
383 return AC_LLVM_AMDGPU_CS;
384 break;
385 default:
386 unreachable("Unhandle shader type");
387 }
388 }
389
390 /* Returns whether the stage is a stage that can be directly before the GS */
391 static bool is_pre_gs_stage(gl_shader_stage stage)
392 {
393 return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
394 }
395
396 static void create_function(struct radv_shader_context *ctx,
397 gl_shader_stage stage,
398 bool has_previous_stage)
399 {
400 if (ctx->ac.chip_class >= GFX10) {
401 if (is_pre_gs_stage(stage) && ctx->args->options->key.vs_common_out.as_ngg) {
402 /* On GFX10, VS is merged into GS for NGG. */
403 stage = MESA_SHADER_GEOMETRY;
404 has_previous_stage = true;
405 }
406 }
407
408 ctx->main_function = create_llvm_function(
409 &ctx->ac, ctx->ac.module, ctx->ac.builder, &ctx->args->ac,
410 get_llvm_calling_convention(ctx->main_function, stage),
411 ctx->max_workgroup_size,
412 ctx->args->options);
413
414 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
415 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
416 NULL, 0, AC_FUNC_ATTR_READNONE);
417 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
418 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
419
420 load_descriptor_sets(ctx);
421
422 if (stage == MESA_SHADER_TESS_CTRL ||
423 (stage == MESA_SHADER_VERTEX && ctx->args->options->key.vs_common_out.as_ls) ||
424 /* GFX9 has the ESGS ring buffer in LDS. */
425 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
426 ac_declare_lds_as_pointer(&ctx->ac);
427 }
428
429 }
430
431
432 static LLVMValueRef
433 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
434 unsigned desc_set, unsigned binding)
435 {
436 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
437 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
438 struct radv_pipeline_layout *pipeline_layout = ctx->args->options->layout;
439 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
440 unsigned base_offset = layout->binding[binding].offset;
441 LLVMValueRef offset, stride;
442
443 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
444 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
445 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
446 layout->binding[binding].dynamic_offset_offset;
447 desc_ptr = ac_get_arg(&ctx->ac, ctx->args->ac.push_constants);
448 base_offset = pipeline_layout->push_constant_size + 16 * idx;
449 stride = LLVMConstInt(ctx->ac.i32, 16, false);
450 } else
451 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
452
453 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
454
455 if (layout->binding[binding].type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
456 offset = ac_build_imad(&ctx->ac, index, stride, offset);
457 }
458
459 desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
460 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
461 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
462
463 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
464 uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
465 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
466 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
467 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
468
469 if (ctx->ac.chip_class >= GFX10) {
470 desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
471 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
472 S_008F0C_RESOURCE_LEVEL(1);
473 } else {
474 desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
475 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
476 }
477
478 LLVMValueRef desc_components[4] = {
479 LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
480 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->args->options->address32_hi), false),
481 /* High limit to support variable sizes. */
482 LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
483 LLVMConstInt(ctx->ac.i32, desc_type, false),
484 };
485
486 return ac_build_gather_values(&ctx->ac, desc_components, 4);
487 }
488
489 return desc_ptr;
490 }
491
492
493 /* The offchip buffer layout for TCS->TES is
494 *
495 * - attribute 0 of patch 0 vertex 0
496 * - attribute 0 of patch 0 vertex 1
497 * - attribute 0 of patch 0 vertex 2
498 * ...
499 * - attribute 0 of patch 1 vertex 0
500 * - attribute 0 of patch 1 vertex 1
501 * ...
502 * - attribute 1 of patch 0 vertex 0
503 * - attribute 1 of patch 0 vertex 1
504 * ...
505 * - per patch attribute 0 of patch 0
506 * - per patch attribute 0 of patch 1
507 * ...
508 *
509 * Note that every attribute has 4 components.
510 */
511 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
512 {
513 uint32_t num_patches = ctx->tcs_num_patches;
514 uint32_t num_tcs_outputs;
515 if (ctx->stage == MESA_SHADER_TESS_CTRL)
516 num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
517 else
518 num_tcs_outputs = ctx->args->options->key.tes.tcs_num_outputs;
519
520 uint32_t output_vertex_size = num_tcs_outputs * 16;
521 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
522
523 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
524 }
525
526 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
527 LLVMValueRef vertex_index)
528 {
529 LLVMValueRef param_stride;
530 if (vertex_index)
531 param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
532 else
533 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
534 return param_stride;
535 }
536
537 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
538 LLVMValueRef vertex_index,
539 LLVMValueRef param_index)
540 {
541 LLVMValueRef base_addr;
542 LLVMValueRef param_stride, constant16;
543 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
544 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
545 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
546 param_stride = calc_param_stride(ctx, vertex_index);
547 if (vertex_index) {
548 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
549 vertices_per_patch, vertex_index);
550 } else {
551 base_addr = rel_patch_id;
552 }
553
554 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
555 LLVMBuildMul(ctx->ac.builder, param_index,
556 param_stride, ""), "");
557
558 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
559
560 if (!vertex_index) {
561 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
562
563 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
564 patch_data_offset, "");
565 }
566 return base_addr;
567 }
568
569 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
570 unsigned param,
571 unsigned const_index,
572 bool is_compact,
573 LLVMValueRef vertex_index,
574 LLVMValueRef indir_index)
575 {
576 LLVMValueRef param_index;
577
578 if (indir_index)
579 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
580 indir_index, "");
581 else {
582 if (const_index && !is_compact)
583 param += const_index;
584 param_index = LLVMConstInt(ctx->ac.i32, param, false);
585 }
586 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
587 }
588
589 static LLVMValueRef
590 get_dw_address(struct radv_shader_context *ctx,
591 LLVMValueRef dw_addr,
592 unsigned param,
593 unsigned const_index,
594 bool compact_const_index,
595 LLVMValueRef vertex_index,
596 LLVMValueRef stride,
597 LLVMValueRef indir_index)
598
599 {
600
601 if (vertex_index) {
602 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
603 LLVMBuildMul(ctx->ac.builder,
604 vertex_index,
605 stride, ""), "");
606 }
607
608 if (indir_index)
609 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
610 LLVMBuildMul(ctx->ac.builder, indir_index,
611 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
612 else if (const_index && !compact_const_index)
613 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
614 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
615
616 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
617 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
618
619 if (const_index && compact_const_index)
620 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
621 LLVMConstInt(ctx->ac.i32, const_index, false), "");
622 return dw_addr;
623 }
624
625 static LLVMValueRef
626 load_tcs_varyings(struct ac_shader_abi *abi,
627 LLVMTypeRef type,
628 LLVMValueRef vertex_index,
629 LLVMValueRef indir_index,
630 unsigned const_index,
631 unsigned location,
632 unsigned driver_location,
633 unsigned component,
634 unsigned num_components,
635 bool is_patch,
636 bool is_compact,
637 bool load_input)
638 {
639 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
640 LLVMValueRef dw_addr, stride;
641 LLVMValueRef value[4], result;
642 unsigned param = shader_io_get_unique_index(location);
643
644 if (load_input) {
645 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
646 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
647 dw_addr = get_tcs_in_current_patch_offset(ctx);
648 } else {
649 if (!is_patch) {
650 stride = get_tcs_out_vertex_stride(ctx);
651 dw_addr = get_tcs_out_current_patch_offset(ctx);
652 } else {
653 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
654 stride = NULL;
655 }
656 }
657
658 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
659 indir_index);
660
661 for (unsigned i = 0; i < num_components + component; i++) {
662 value[i] = ac_lds_load(&ctx->ac, dw_addr);
663 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
664 ctx->ac.i32_1, "");
665 }
666 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
667 return result;
668 }
669
670 static void
671 store_tcs_output(struct ac_shader_abi *abi,
672 const nir_variable *var,
673 LLVMValueRef vertex_index,
674 LLVMValueRef param_index,
675 unsigned const_index,
676 LLVMValueRef src,
677 unsigned writemask)
678 {
679 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
680 const unsigned location = var->data.location;
681 unsigned component = var->data.location_frac;
682 const bool is_patch = var->data.patch;
683 const bool is_compact = var->data.compact;
684 LLVMValueRef dw_addr;
685 LLVMValueRef stride = NULL;
686 LLVMValueRef buf_addr = NULL;
687 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
688 unsigned param;
689 bool store_lds = true;
690
691 if (is_patch) {
692 if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
693 store_lds = false;
694 } else {
695 if (!(ctx->shader->info.outputs_read & (1ULL << location)))
696 store_lds = false;
697 }
698
699 param = shader_io_get_unique_index(location);
700 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
701 const_index += component;
702 component = 0;
703
704 if (const_index >= 4) {
705 const_index -= 4;
706 param++;
707 }
708 }
709
710 if (!is_patch) {
711 stride = get_tcs_out_vertex_stride(ctx);
712 dw_addr = get_tcs_out_current_patch_offset(ctx);
713 } else {
714 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
715 }
716
717 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
718 param_index);
719 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
720 vertex_index, param_index);
721
722 bool is_tess_factor = false;
723 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
724 location == VARYING_SLOT_TESS_LEVEL_OUTER)
725 is_tess_factor = true;
726
727 unsigned base = is_compact ? const_index : 0;
728 for (unsigned chan = 0; chan < 8; chan++) {
729 if (!(writemask & (1 << chan)))
730 continue;
731 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
732 value = ac_to_integer(&ctx->ac, value);
733 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
734
735 if (store_lds || is_tess_factor) {
736 LLVMValueRef dw_addr_chan =
737 LLVMBuildAdd(ctx->ac.builder, dw_addr,
738 LLVMConstInt(ctx->ac.i32, chan, false), "");
739 ac_lds_store(&ctx->ac, dw_addr_chan, value);
740 }
741
742 if (!is_tess_factor && writemask != 0xF)
743 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
744 buf_addr, oc_lds,
745 4 * (base + chan), ac_glc);
746 }
747
748 if (writemask == 0xF) {
749 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
750 buf_addr, oc_lds,
751 (base * 4), ac_glc);
752 }
753 }
754
755 static LLVMValueRef
756 load_tes_input(struct ac_shader_abi *abi,
757 LLVMTypeRef type,
758 LLVMValueRef vertex_index,
759 LLVMValueRef param_index,
760 unsigned const_index,
761 unsigned location,
762 unsigned driver_location,
763 unsigned component,
764 unsigned num_components,
765 bool is_patch,
766 bool is_compact,
767 bool load_input)
768 {
769 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
770 LLVMValueRef buf_addr;
771 LLVMValueRef result;
772 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
773 unsigned param = shader_io_get_unique_index(location);
774
775 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
776 const_index += component;
777 component = 0;
778 if (const_index >= 4) {
779 const_index -= 4;
780 param++;
781 }
782 }
783
784 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
785 is_compact, vertex_index, param_index);
786
787 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
788 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
789
790 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
791 buf_addr, oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
792 result = ac_trim_vector(&ctx->ac, result, num_components);
793 return result;
794 }
795
796 static LLVMValueRef
797 radv_emit_fetch_64bit(struct radv_shader_context *ctx,
798 LLVMTypeRef type, LLVMValueRef a, LLVMValueRef b)
799 {
800 LLVMValueRef values[2] = {
801 ac_to_integer(&ctx->ac, a),
802 ac_to_integer(&ctx->ac, b),
803 };
804 LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
805 return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
806 }
807
808 static LLVMValueRef
809 load_gs_input(struct ac_shader_abi *abi,
810 unsigned location,
811 unsigned driver_location,
812 unsigned component,
813 unsigned num_components,
814 unsigned vertex_index,
815 unsigned const_index,
816 LLVMTypeRef type)
817 {
818 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
819 LLVMValueRef vtx_offset;
820 unsigned param, vtx_offset_param;
821 LLVMValueRef value[4], result;
822
823 vtx_offset_param = vertex_index;
824 assert(vtx_offset_param < 6);
825 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
826 LLVMConstInt(ctx->ac.i32, 4, false), "");
827
828 param = shader_io_get_unique_index(location);
829
830 for (unsigned i = component; i < num_components + component; i++) {
831 if (ctx->ac.chip_class >= GFX9) {
832 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
833 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
834 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
835 value[i] = ac_lds_load(&ctx->ac, dw_addr);
836
837 if (ac_get_type_size(type) == 8) {
838 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
839 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index + 1, 0), "");
840 LLVMValueRef tmp = ac_lds_load(&ctx->ac, dw_addr);
841
842 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
843 }
844 } else {
845 LLVMValueRef soffset =
846 LLVMConstInt(ctx->ac.i32,
847 (param * 4 + i + const_index) * 256,
848 false);
849
850 value[i] = ac_build_buffer_load(&ctx->ac,
851 ctx->esgs_ring, 1,
852 ctx->ac.i32_0,
853 vtx_offset, soffset,
854 0, ac_glc, true, false);
855
856 if (ac_get_type_size(type) == 8) {
857 soffset = LLVMConstInt(ctx->ac.i32,
858 (param * 4 + i + const_index + 1) * 256,
859 false);
860
861 LLVMValueRef tmp =
862 ac_build_buffer_load(&ctx->ac,
863 ctx->esgs_ring, 1,
864 ctx->ac.i32_0,
865 vtx_offset, soffset,
866 0, ac_glc, true, false);
867
868 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
869 }
870 }
871
872 if (ac_get_type_size(type) == 2) {
873 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
874 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
875 }
876 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
877 }
878 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
879 result = ac_to_integer(&ctx->ac, result);
880 return result;
881 }
882
883
884 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
885 {
886 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
887 ac_build_kill_if_false(&ctx->ac, visible);
888 }
889
890 static uint32_t
891 radv_get_sample_pos_offset(uint32_t num_samples)
892 {
893 uint32_t sample_pos_offset = 0;
894
895 switch (num_samples) {
896 case 2:
897 sample_pos_offset = 1;
898 break;
899 case 4:
900 sample_pos_offset = 3;
901 break;
902 case 8:
903 sample_pos_offset = 7;
904 break;
905 default:
906 break;
907 }
908 return sample_pos_offset;
909 }
910
911 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
912 LLVMValueRef sample_id)
913 {
914 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
915
916 LLVMValueRef result;
917 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false);
918 LLVMValueRef ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ring_offsets, &index, 1, "");
919
920 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
921 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
922
923 uint32_t sample_pos_offset =
924 radv_get_sample_pos_offset(ctx->args->options->key.fs.num_samples);
925
926 sample_id =
927 LLVMBuildAdd(ctx->ac.builder, sample_id,
928 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
929 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
930
931 return result;
932 }
933
934
935 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
936 {
937 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
938 uint8_t log2_ps_iter_samples;
939
940 if (ctx->args->shader_info->ps.force_persample) {
941 log2_ps_iter_samples =
942 util_logbase2(ctx->args->options->key.fs.num_samples);
943 } else {
944 log2_ps_iter_samples = ctx->args->options->key.fs.log2_ps_iter_samples;
945 }
946
947 /* The bit pattern matches that used by fixed function fragment
948 * processing. */
949 static const uint16_t ps_iter_masks[] = {
950 0xffff, /* not used */
951 0x5555,
952 0x1111,
953 0x0101,
954 0x0001,
955 };
956 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
957
958 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
959
960 LLVMValueRef result, sample_id;
961 sample_id = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.ancillary), 8, 4);
962 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
963 result = LLVMBuildAnd(ctx->ac.builder, sample_id,
964 ac_get_arg(&ctx->ac, ctx->args->ac.sample_coverage), "");
965 return result;
966 }
967
968
969 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
970 unsigned stream,
971 LLVMValueRef *addrs);
972
973 static void
974 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
975 {
976 LLVMValueRef gs_next_vertex;
977 LLVMValueRef can_emit;
978 unsigned offset = 0;
979 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
980
981 if (ctx->args->options->key.vs_common_out.as_ngg) {
982 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
983 return;
984 }
985
986 /* Write vertex attribute values to GSVS ring */
987 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
988 ctx->gs_next_vertex[stream],
989 "");
990
991 /* If this thread has already emitted the declared maximum number of
992 * vertices, don't emit any more: excessive vertex emissions are not
993 * supposed to have any effect.
994 */
995 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
996 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
997
998 bool use_kill = !ctx->args->shader_info->gs.writes_memory;
999 if (use_kill)
1000 ac_build_kill_if_false(&ctx->ac, can_emit);
1001 else
1002 ac_build_ifcc(&ctx->ac, can_emit, 6505);
1003
1004 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1005 unsigned output_usage_mask =
1006 ctx->args->shader_info->gs.output_usage_mask[i];
1007 uint8_t output_stream =
1008 ctx->args->shader_info->gs.output_streams[i];
1009 LLVMValueRef *out_ptr = &addrs[i * 4];
1010 int length = util_last_bit(output_usage_mask);
1011
1012 if (!(ctx->output_mask & (1ull << i)) ||
1013 output_stream != stream)
1014 continue;
1015
1016 for (unsigned j = 0; j < length; j++) {
1017 if (!(output_usage_mask & (1 << j)))
1018 continue;
1019
1020 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1021 out_ptr[j], "");
1022 LLVMValueRef voffset =
1023 LLVMConstInt(ctx->ac.i32, offset *
1024 ctx->shader->info.gs.vertices_out, false);
1025
1026 offset++;
1027
1028 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1029 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1030
1031 out_val = ac_to_integer(&ctx->ac, out_val);
1032 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1033
1034 ac_build_buffer_store_dword(&ctx->ac,
1035 ctx->gsvs_ring[stream],
1036 out_val, 1,
1037 voffset,
1038 ac_get_arg(&ctx->ac,
1039 ctx->args->gs2vs_offset),
1040 0, ac_glc | ac_slc | ac_swizzled);
1041 }
1042 }
1043
1044 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1045 ctx->ac.i32_1, "");
1046 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
1047
1048 ac_build_sendmsg(&ctx->ac,
1049 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
1050 ctx->gs_wave_id);
1051
1052 if (!use_kill)
1053 ac_build_endif(&ctx->ac, 6505);
1054 }
1055
1056 static void
1057 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1058 {
1059 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1060
1061 if (ctx->args->options->key.vs_common_out.as_ngg) {
1062 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
1063 return;
1064 }
1065
1066 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1067 }
1068
1069 static LLVMValueRef
1070 load_tess_coord(struct ac_shader_abi *abi)
1071 {
1072 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1073
1074 LLVMValueRef coord[4] = {
1075 ac_get_arg(&ctx->ac, ctx->args->tes_u),
1076 ac_get_arg(&ctx->ac, ctx->args->tes_v),
1077 ctx->ac.f32_0,
1078 ctx->ac.f32_0,
1079 };
1080
1081 if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
1082 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1083 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1084
1085 return ac_build_gather_values(&ctx->ac, coord, 3);
1086 }
1087
1088 static LLVMValueRef
1089 load_patch_vertices_in(struct ac_shader_abi *abi)
1090 {
1091 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1092 return LLVMConstInt(ctx->ac.i32, ctx->args->options->key.tcs.input_vertices, false);
1093 }
1094
1095
1096 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1097 {
1098 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1099 return ac_get_arg(&ctx->ac, ctx->args->ac.base_vertex);
1100 }
1101
1102 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1103 LLVMValueRef buffer_ptr, bool write)
1104 {
1105 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1106 LLVMValueRef result;
1107
1108 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1109
1110 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1111 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1112
1113 return result;
1114 }
1115
1116 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1117 {
1118 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1119 LLVMValueRef result;
1120
1121 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr)) != LLVMPointerTypeKind) {
1122 /* Do not load the descriptor for inlined uniform blocks. */
1123 return buffer_ptr;
1124 }
1125
1126 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1127
1128 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1129 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1130
1131 return result;
1132 }
1133
1134 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1135 unsigned descriptor_set,
1136 unsigned base_index,
1137 unsigned constant_index,
1138 LLVMValueRef index,
1139 enum ac_descriptor_type desc_type,
1140 bool image, bool write,
1141 bool bindless)
1142 {
1143 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1144 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1145 struct radv_descriptor_set_layout *layout = ctx->args->options->layout->set[descriptor_set].layout;
1146 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1147 unsigned offset = binding->offset;
1148 unsigned stride = binding->size;
1149 unsigned type_size;
1150 LLVMBuilderRef builder = ctx->ac.builder;
1151 LLVMTypeRef type;
1152
1153 assert(base_index < layout->binding_count);
1154
1155 switch (desc_type) {
1156 case AC_DESC_IMAGE:
1157 type = ctx->ac.v8i32;
1158 type_size = 32;
1159 break;
1160 case AC_DESC_FMASK:
1161 type = ctx->ac.v8i32;
1162 offset += 32;
1163 type_size = 32;
1164 break;
1165 case AC_DESC_SAMPLER:
1166 type = ctx->ac.v4i32;
1167 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
1168 offset += radv_combined_image_descriptor_sampler_offset(binding);
1169 }
1170
1171 type_size = 16;
1172 break;
1173 case AC_DESC_BUFFER:
1174 type = ctx->ac.v4i32;
1175 type_size = 16;
1176 break;
1177 case AC_DESC_PLANE_0:
1178 case AC_DESC_PLANE_1:
1179 case AC_DESC_PLANE_2:
1180 type = ctx->ac.v8i32;
1181 type_size = 32;
1182 offset += 32 * (desc_type - AC_DESC_PLANE_0);
1183 break;
1184 default:
1185 unreachable("invalid desc_type\n");
1186 }
1187
1188 offset += constant_index * stride;
1189
1190 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1191 (!index || binding->immutable_samplers_equal)) {
1192 if (binding->immutable_samplers_equal)
1193 constant_index = 0;
1194
1195 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1196
1197 LLVMValueRef constants[] = {
1198 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1199 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1200 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1201 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1202 };
1203 return ac_build_gather_values(&ctx->ac, constants, 4);
1204 }
1205
1206 assert(stride % type_size == 0);
1207
1208 LLVMValueRef adjusted_index = index;
1209 if (!adjusted_index)
1210 adjusted_index = ctx->ac.i32_0;
1211
1212 adjusted_index = LLVMBuildMul(builder, adjusted_index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1213
1214 LLVMValueRef val_offset = LLVMConstInt(ctx->ac.i32, offset, 0);
1215 list = LLVMBuildGEP(builder, list, &val_offset, 1, "");
1216 list = LLVMBuildPointerCast(builder, list,
1217 ac_array_in_const32_addr_space(type), "");
1218
1219 LLVMValueRef descriptor = ac_build_load_to_sgpr(&ctx->ac, list, adjusted_index);
1220
1221 /* 3 plane formats always have same size and format for plane 1 & 2, so
1222 * use the tail from plane 1 so that we can store only the first 16 bytes
1223 * of the last plane. */
1224 if (desc_type == AC_DESC_PLANE_2) {
1225 LLVMValueRef descriptor2 = radv_get_sampler_desc(abi, descriptor_set, base_index, constant_index, index, AC_DESC_PLANE_1,image, write, bindless);
1226
1227 LLVMValueRef components[8];
1228 for (unsigned i = 0; i < 4; ++i)
1229 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor, i);
1230
1231 for (unsigned i = 4; i < 8; ++i)
1232 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor2, i);
1233 descriptor = ac_build_gather_values(&ctx->ac, components, 8);
1234 }
1235
1236 return descriptor;
1237 }
1238
1239 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1240 * so we may need to fix it up. */
1241 static LLVMValueRef
1242 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1243 unsigned adjustment,
1244 LLVMValueRef alpha)
1245 {
1246 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1247 return alpha;
1248
1249 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1250
1251 alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
1252
1253 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1254 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1255 else
1256 alpha = ac_to_integer(&ctx->ac, alpha);
1257
1258 /* For the integer-like cases, do a natural sign extension.
1259 *
1260 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1261 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1262 * exponent.
1263 */
1264 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1265 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1266 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1267 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1268
1269 /* Convert back to the right type. */
1270 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1271 LLVMValueRef clamp;
1272 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1273 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1274 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1275 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1276 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1277 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1278 }
1279
1280 return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
1281 }
1282
1283 static const struct vertex_format_info {
1284 uint8_t vertex_byte_size;
1285 uint8_t num_channels;
1286 uint8_t chan_byte_size;
1287 uint8_t chan_format;
1288 } vertex_format_table[] = {
1289 { 0, 4, 0, V_008F0C_BUF_DATA_FORMAT_INVALID }, /* BUF_DATA_FORMAT_INVALID */
1290 { 1, 1, 1, V_008F0C_BUF_DATA_FORMAT_8 }, /* BUF_DATA_FORMAT_8 */
1291 { 2, 1, 2, V_008F0C_BUF_DATA_FORMAT_16 }, /* BUF_DATA_FORMAT_16 */
1292 { 2, 2, 1, V_008F0C_BUF_DATA_FORMAT_8 }, /* BUF_DATA_FORMAT_8_8 */
1293 { 4, 1, 4, V_008F0C_BUF_DATA_FORMAT_32 }, /* BUF_DATA_FORMAT_32 */
1294 { 4, 2, 2, V_008F0C_BUF_DATA_FORMAT_16 }, /* BUF_DATA_FORMAT_16_16 */
1295 { 4, 3, 0, V_008F0C_BUF_DATA_FORMAT_10_11_11 }, /* BUF_DATA_FORMAT_10_11_11 */
1296 { 4, 3, 0, V_008F0C_BUF_DATA_FORMAT_11_11_10 }, /* BUF_DATA_FORMAT_11_11_10 */
1297 { 4, 4, 0, V_008F0C_BUF_DATA_FORMAT_10_10_10_2 }, /* BUF_DATA_FORMAT_10_10_10_2 */
1298 { 4, 4, 0, V_008F0C_BUF_DATA_FORMAT_2_10_10_10 }, /* BUF_DATA_FORMAT_2_10_10_10 */
1299 { 4, 4, 1, V_008F0C_BUF_DATA_FORMAT_8 }, /* BUF_DATA_FORMAT_8_8_8_8 */
1300 { 8, 2, 4, V_008F0C_BUF_DATA_FORMAT_32 }, /* BUF_DATA_FORMAT_32_32 */
1301 { 8, 4, 2, V_008F0C_BUF_DATA_FORMAT_16 }, /* BUF_DATA_FORMAT_16_16_16_16 */
1302 { 12, 3, 4, V_008F0C_BUF_DATA_FORMAT_32 }, /* BUF_DATA_FORMAT_32_32_32 */
1303 { 16, 4, 4, V_008F0C_BUF_DATA_FORMAT_32 }, /* BUF_DATA_FORMAT_32_32_32_32 */
1304 };
1305
1306 static LLVMValueRef
1307 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
1308 LLVMValueRef value,
1309 unsigned num_channels,
1310 bool is_float)
1311 {
1312 LLVMValueRef zero = is_float ? ctx->ac.f32_0 : ctx->ac.i32_0;
1313 LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
1314 LLVMValueRef chan[4];
1315
1316 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
1317 unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
1318
1319 if (num_channels == 4 && num_channels == vec_size)
1320 return value;
1321
1322 num_channels = MIN2(num_channels, vec_size);
1323
1324 for (unsigned i = 0; i < num_channels; i++)
1325 chan[i] = ac_llvm_extract_elem(&ctx->ac, value, i);
1326 } else {
1327 assert(num_channels == 1);
1328 chan[0] = value;
1329 }
1330
1331 for (unsigned i = num_channels; i < 4; i++) {
1332 chan[i] = i == 3 ? one : zero;
1333 chan[i] = ac_to_integer(&ctx->ac, chan[i]);
1334 }
1335
1336 return ac_build_gather_values(&ctx->ac, chan, 4);
1337 }
1338
1339 static void
1340 handle_vs_input_decl(struct radv_shader_context *ctx,
1341 struct nir_variable *variable)
1342 {
1343 LLVMValueRef t_list_ptr = ac_get_arg(&ctx->ac, ctx->args->vertex_buffers);
1344 LLVMValueRef t_offset;
1345 LLVMValueRef t_list;
1346 LLVMValueRef input;
1347 LLVMValueRef buffer_index;
1348 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1349 uint8_t input_usage_mask =
1350 ctx->args->shader_info->vs.input_usage_mask[variable->data.location];
1351 unsigned num_input_channels = util_last_bit(input_usage_mask);
1352
1353 variable->data.driver_location = variable->data.location * 4;
1354
1355 enum glsl_base_type type = glsl_get_base_type(variable->type);
1356 for (unsigned i = 0; i < attrib_count; ++i) {
1357 LLVMValueRef output[4];
1358 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1359 unsigned attrib_format = ctx->args->options->key.vs.vertex_attribute_formats[attrib_index];
1360 unsigned data_format = attrib_format & 0x0f;
1361 unsigned num_format = (attrib_format >> 4) & 0x07;
1362 bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
1363 num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
1364
1365 if (ctx->args->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1366 uint32_t divisor = ctx->args->options->key.vs.instance_rate_divisors[attrib_index];
1367
1368 if (divisor) {
1369 buffer_index = ctx->abi.instance_id;
1370
1371 if (divisor != 1) {
1372 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1373 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1374 }
1375 } else {
1376 buffer_index = ctx->ac.i32_0;
1377 }
1378
1379 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1380 ac_get_arg(&ctx->ac,
1381 ctx->args->ac.start_instance),\
1382 buffer_index, "");
1383 } else {
1384 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1385 ctx->abi.vertex_id,
1386 ac_get_arg(&ctx->ac,
1387 ctx->args->ac.base_vertex), "");
1388 }
1389
1390 assert(data_format < ARRAY_SIZE(vertex_format_table));
1391 const struct vertex_format_info *vtx_info = &vertex_format_table[data_format];
1392
1393 /* Adjust the number of channels to load based on the vertex
1394 * attribute format.
1395 */
1396 unsigned num_channels = MIN2(num_input_channels, vtx_info->num_channels);
1397 unsigned attrib_binding = ctx->args->options->key.vs.vertex_attribute_bindings[attrib_index];
1398 unsigned attrib_offset = ctx->args->options->key.vs.vertex_attribute_offsets[attrib_index];
1399 unsigned attrib_stride = ctx->args->options->key.vs.vertex_attribute_strides[attrib_index];
1400
1401 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1402 /* Always load, at least, 3 channels for formats that
1403 * need to be shuffled because X<->Z.
1404 */
1405 num_channels = MAX2(num_channels, 3);
1406 }
1407
1408 t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false);
1409 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1410
1411 /* Perform per-channel vertex fetch operations if unaligned
1412 * access are detected. Only GFX6 and GFX10 are affected.
1413 */
1414 bool unaligned_vertex_fetches = false;
1415 if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class == GFX10) &&
1416 vtx_info->chan_format != data_format &&
1417 ((attrib_offset % vtx_info->vertex_byte_size) ||
1418 (attrib_stride % vtx_info->vertex_byte_size)))
1419 unaligned_vertex_fetches = true;
1420
1421 if (unaligned_vertex_fetches) {
1422 unsigned chan_format = vtx_info->chan_format;
1423 LLVMValueRef values[4];
1424
1425 assert(ctx->ac.chip_class == GFX6 ||
1426 ctx->ac.chip_class == GFX10);
1427
1428 for (unsigned chan = 0; chan < num_channels; chan++) {
1429 unsigned chan_offset = attrib_offset + chan * vtx_info->chan_byte_size;
1430 LLVMValueRef chan_index = buffer_index;
1431
1432 if (attrib_stride != 0 && chan_offset > attrib_stride) {
1433 LLVMValueRef buffer_offset =
1434 LLVMConstInt(ctx->ac.i32,
1435 chan_offset / attrib_stride, false);
1436
1437 chan_index = LLVMBuildAdd(ctx->ac.builder,
1438 buffer_index,
1439 buffer_offset, "");
1440
1441 chan_offset = chan_offset % attrib_stride;
1442 }
1443
1444 values[chan] = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1445 chan_index,
1446 LLVMConstInt(ctx->ac.i32, chan_offset, false),
1447 ctx->ac.i32_0, ctx->ac.i32_0, 1,
1448 chan_format, num_format, 0, true);
1449 }
1450
1451 input = ac_build_gather_values(&ctx->ac, values, num_channels);
1452 } else {
1453 if (attrib_stride != 0 && attrib_offset > attrib_stride) {
1454 LLVMValueRef buffer_offset =
1455 LLVMConstInt(ctx->ac.i32,
1456 attrib_offset / attrib_stride, false);
1457
1458 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1459 buffer_index,
1460 buffer_offset, "");
1461
1462 attrib_offset = attrib_offset % attrib_stride;
1463 }
1464
1465 input = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1466 buffer_index,
1467 LLVMConstInt(ctx->ac.i32, attrib_offset, false),
1468 ctx->ac.i32_0, ctx->ac.i32_0,
1469 num_channels,
1470 data_format, num_format, 0, true);
1471 }
1472
1473 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1474 LLVMValueRef c[4];
1475 c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
1476 c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
1477 c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
1478 c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
1479
1480 input = ac_build_gather_values(&ctx->ac, c, 4);
1481 }
1482
1483 input = radv_fixup_vertex_input_fetches(ctx, input, num_channels,
1484 is_float);
1485
1486 for (unsigned chan = 0; chan < 4; chan++) {
1487 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1488 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1489 if (type == GLSL_TYPE_FLOAT16) {
1490 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
1491 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
1492 }
1493 }
1494
1495 unsigned alpha_adjust = (ctx->args->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
1496 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
1497
1498 for (unsigned chan = 0; chan < 4; chan++) {
1499 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
1500 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
1501 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
1502
1503 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
1504 }
1505 }
1506 }
1507
1508 static void
1509 handle_vs_inputs(struct radv_shader_context *ctx,
1510 struct nir_shader *nir) {
1511 nir_foreach_variable(variable, &nir->inputs)
1512 handle_vs_input_decl(ctx, variable);
1513 }
1514
1515 static void
1516 prepare_interp_optimize(struct radv_shader_context *ctx,
1517 struct nir_shader *nir)
1518 {
1519 bool uses_center = false;
1520 bool uses_centroid = false;
1521 nir_foreach_variable(variable, &nir->inputs) {
1522 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1523 variable->data.sample)
1524 continue;
1525
1526 if (variable->data.centroid)
1527 uses_centroid = true;
1528 else
1529 uses_center = true;
1530 }
1531
1532 ctx->abi.persp_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.persp_centroid);
1533 ctx->abi.linear_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.linear_centroid);
1534
1535 if (uses_center && uses_centroid) {
1536 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT,
1537 ac_get_arg(&ctx->ac, ctx->args->ac.prim_mask),
1538 ctx->ac.i32_0, "");
1539 ctx->abi.persp_centroid =
1540 LLVMBuildSelect(ctx->ac.builder, sel,
1541 ac_get_arg(&ctx->ac, ctx->args->ac.persp_center),
1542 ctx->abi.persp_centroid, "");
1543 ctx->abi.linear_centroid =
1544 LLVMBuildSelect(ctx->ac.builder, sel,
1545 ac_get_arg(&ctx->ac, ctx->args->ac.linear_center),
1546 ctx->abi.linear_centroid, "");
1547 }
1548 }
1549
1550 static void
1551 scan_shader_output_decl(struct radv_shader_context *ctx,
1552 struct nir_variable *variable,
1553 struct nir_shader *shader,
1554 gl_shader_stage stage)
1555 {
1556 int idx = variable->data.location + variable->data.index;
1557 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1558 uint64_t mask_attribs;
1559
1560 variable->data.driver_location = idx * 4;
1561
1562 /* tess ctrl has it's own load/store paths for outputs */
1563 if (stage == MESA_SHADER_TESS_CTRL)
1564 return;
1565
1566 if (variable->data.compact) {
1567 unsigned component_count = variable->data.location_frac +
1568 glsl_get_length(variable->type);
1569 attrib_count = (component_count + 3) / 4;
1570 }
1571
1572 mask_attribs = ((1ull << attrib_count) - 1) << idx;
1573
1574 ctx->output_mask |= mask_attribs;
1575 }
1576
1577
1578 /* Initialize arguments for the shader export intrinsic */
1579 static void
1580 si_llvm_init_export_args(struct radv_shader_context *ctx,
1581 LLVMValueRef *values,
1582 unsigned enabled_channels,
1583 unsigned target,
1584 struct ac_export_args *args)
1585 {
1586 /* Specify the channels that are enabled. */
1587 args->enabled_channels = enabled_channels;
1588
1589 /* Specify whether the EXEC mask represents the valid mask */
1590 args->valid_mask = 0;
1591
1592 /* Specify whether this is the last export */
1593 args->done = 0;
1594
1595 /* Specify the target we are exporting */
1596 args->target = target;
1597
1598 args->compr = false;
1599 args->out[0] = LLVMGetUndef(ctx->ac.f32);
1600 args->out[1] = LLVMGetUndef(ctx->ac.f32);
1601 args->out[2] = LLVMGetUndef(ctx->ac.f32);
1602 args->out[3] = LLVMGetUndef(ctx->ac.f32);
1603
1604 if (!values)
1605 return;
1606
1607 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
1608 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1609 unsigned index = target - V_008DFC_SQ_EXP_MRT;
1610 unsigned col_format = (ctx->args->options->key.fs.col_format >> (4 * index)) & 0xf;
1611 bool is_int8 = (ctx->args->options->key.fs.is_int8 >> index) & 1;
1612 bool is_int10 = (ctx->args->options->key.fs.is_int10 >> index) & 1;
1613 unsigned chan;
1614
1615 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
1616 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
1617 unsigned bits, bool hi) = NULL;
1618
1619 switch(col_format) {
1620 case V_028714_SPI_SHADER_ZERO:
1621 args->enabled_channels = 0; /* writemask */
1622 args->target = V_008DFC_SQ_EXP_NULL;
1623 break;
1624
1625 case V_028714_SPI_SHADER_32_R:
1626 args->enabled_channels = 1;
1627 args->out[0] = values[0];
1628 break;
1629
1630 case V_028714_SPI_SHADER_32_GR:
1631 args->enabled_channels = 0x3;
1632 args->out[0] = values[0];
1633 args->out[1] = values[1];
1634 break;
1635
1636 case V_028714_SPI_SHADER_32_AR:
1637 if (ctx->ac.chip_class >= GFX10) {
1638 args->enabled_channels = 0x3;
1639 args->out[0] = values[0];
1640 args->out[1] = values[3];
1641 } else {
1642 args->enabled_channels = 0x9;
1643 args->out[0] = values[0];
1644 args->out[3] = values[3];
1645 }
1646 break;
1647
1648 case V_028714_SPI_SHADER_FP16_ABGR:
1649 args->enabled_channels = 0x5;
1650 packf = ac_build_cvt_pkrtz_f16;
1651 if (is_16bit) {
1652 for (unsigned chan = 0; chan < 4; chan++)
1653 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
1654 values[chan],
1655 ctx->ac.f32, "");
1656 }
1657 break;
1658
1659 case V_028714_SPI_SHADER_UNORM16_ABGR:
1660 args->enabled_channels = 0x5;
1661 packf = ac_build_cvt_pknorm_u16;
1662 break;
1663
1664 case V_028714_SPI_SHADER_SNORM16_ABGR:
1665 args->enabled_channels = 0x5;
1666 packf = ac_build_cvt_pknorm_i16;
1667 break;
1668
1669 case V_028714_SPI_SHADER_UINT16_ABGR:
1670 args->enabled_channels = 0x5;
1671 packi = ac_build_cvt_pk_u16;
1672 if (is_16bit) {
1673 for (unsigned chan = 0; chan < 4; chan++)
1674 values[chan] = LLVMBuildZExt(ctx->ac.builder,
1675 ac_to_integer(&ctx->ac, values[chan]),
1676 ctx->ac.i32, "");
1677 }
1678 break;
1679
1680 case V_028714_SPI_SHADER_SINT16_ABGR:
1681 args->enabled_channels = 0x5;
1682 packi = ac_build_cvt_pk_i16;
1683 if (is_16bit) {
1684 for (unsigned chan = 0; chan < 4; chan++)
1685 values[chan] = LLVMBuildSExt(ctx->ac.builder,
1686 ac_to_integer(&ctx->ac, values[chan]),
1687 ctx->ac.i32, "");
1688 }
1689 break;
1690
1691 default:
1692 case V_028714_SPI_SHADER_32_ABGR:
1693 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1694 break;
1695 }
1696
1697 /* Pack f16 or norm_i16/u16. */
1698 if (packf) {
1699 for (chan = 0; chan < 2; chan++) {
1700 LLVMValueRef pack_args[2] = {
1701 values[2 * chan],
1702 values[2 * chan + 1]
1703 };
1704 LLVMValueRef packed;
1705
1706 packed = packf(&ctx->ac, pack_args);
1707 args->out[chan] = ac_to_float(&ctx->ac, packed);
1708 }
1709 args->compr = 1; /* COMPR flag */
1710 }
1711
1712 /* Pack i16/u16. */
1713 if (packi) {
1714 for (chan = 0; chan < 2; chan++) {
1715 LLVMValueRef pack_args[2] = {
1716 ac_to_integer(&ctx->ac, values[2 * chan]),
1717 ac_to_integer(&ctx->ac, values[2 * chan + 1])
1718 };
1719 LLVMValueRef packed;
1720
1721 packed = packi(&ctx->ac, pack_args,
1722 is_int8 ? 8 : is_int10 ? 10 : 16,
1723 chan == 1);
1724 args->out[chan] = ac_to_float(&ctx->ac, packed);
1725 }
1726 args->compr = 1; /* COMPR flag */
1727 }
1728 return;
1729 }
1730
1731 if (is_16bit) {
1732 for (unsigned chan = 0; chan < 4; chan++) {
1733 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
1734 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
1735 }
1736 } else
1737 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1738
1739 for (unsigned i = 0; i < 4; ++i)
1740 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
1741 }
1742
1743 static void
1744 radv_export_param(struct radv_shader_context *ctx, unsigned index,
1745 LLVMValueRef *values, unsigned enabled_channels)
1746 {
1747 struct ac_export_args args;
1748
1749 si_llvm_init_export_args(ctx, values, enabled_channels,
1750 V_008DFC_SQ_EXP_PARAM + index, &args);
1751 ac_build_export(&ctx->ac, &args);
1752 }
1753
1754 static LLVMValueRef
1755 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
1756 {
1757 LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
1758 return LLVMBuildLoad(ctx->ac.builder, output, "");
1759 }
1760
1761 static void
1762 radv_emit_stream_output(struct radv_shader_context *ctx,
1763 LLVMValueRef const *so_buffers,
1764 LLVMValueRef const *so_write_offsets,
1765 const struct radv_stream_output *output,
1766 struct radv_shader_output_values *shader_out)
1767 {
1768 unsigned num_comps = util_bitcount(output->component_mask);
1769 unsigned buf = output->buffer;
1770 unsigned offset = output->offset;
1771 unsigned start;
1772 LLVMValueRef out[4];
1773
1774 assert(num_comps && num_comps <= 4);
1775 if (!num_comps || num_comps > 4)
1776 return;
1777
1778 /* Get the first component. */
1779 start = ffs(output->component_mask) - 1;
1780
1781 /* Load the output as int. */
1782 for (int i = 0; i < num_comps; i++) {
1783 out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
1784 }
1785
1786 /* Pack the output. */
1787 LLVMValueRef vdata = NULL;
1788
1789 switch (num_comps) {
1790 case 1: /* as i32 */
1791 vdata = out[0];
1792 break;
1793 case 2: /* as v2i32 */
1794 case 3: /* as v4i32 (aligned to 4) */
1795 out[3] = LLVMGetUndef(ctx->ac.i32);
1796 /* fall through */
1797 case 4: /* as v4i32 */
1798 vdata = ac_build_gather_values(&ctx->ac, out,
1799 !ac_has_vec3_support(ctx->ac.chip_class, false) ?
1800 util_next_power_of_two(num_comps) :
1801 num_comps);
1802 break;
1803 }
1804
1805 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
1806 vdata, num_comps, so_write_offsets[buf],
1807 ctx->ac.i32_0, offset,
1808 ac_glc | ac_slc);
1809 }
1810
1811 static void
1812 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
1813 {
1814 int i;
1815
1816 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1817 assert(ctx->args->streamout_config.used);
1818 LLVMValueRef so_vtx_count =
1819 ac_build_bfe(&ctx->ac,
1820 ac_get_arg(&ctx->ac, ctx->args->streamout_config),
1821 LLVMConstInt(ctx->ac.i32, 16, false),
1822 LLVMConstInt(ctx->ac.i32, 7, false), false);
1823
1824 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
1825
1826 /* can_emit = tid < so_vtx_count; */
1827 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
1828 tid, so_vtx_count, "");
1829
1830 /* Emit the streamout code conditionally. This actually avoids
1831 * out-of-bounds buffer access. The hw tells us via the SGPR
1832 * (so_vtx_count) which threads are allowed to emit streamout data.
1833 */
1834 ac_build_ifcc(&ctx->ac, can_emit, 6501);
1835 {
1836 /* The buffer offset is computed as follows:
1837 * ByteOffset = streamout_offset[buffer_id]*4 +
1838 * (streamout_write_index + thread_id)*stride[buffer_id] +
1839 * attrib_offset
1840 */
1841 LLVMValueRef so_write_index =
1842 ac_get_arg(&ctx->ac, ctx->args->streamout_write_idx);
1843
1844 /* Compute (streamout_write_index + thread_id). */
1845 so_write_index =
1846 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
1847
1848 /* Load the descriptor and compute the write offset for each
1849 * enabled buffer.
1850 */
1851 LLVMValueRef so_write_offset[4] = {};
1852 LLVMValueRef so_buffers[4] = {};
1853 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
1854
1855 for (i = 0; i < 4; i++) {
1856 uint16_t stride = ctx->args->shader_info->so.strides[i];
1857
1858 if (!stride)
1859 continue;
1860
1861 LLVMValueRef offset =
1862 LLVMConstInt(ctx->ac.i32, i, false);
1863
1864 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
1865 buf_ptr, offset);
1866
1867 LLVMValueRef so_offset =
1868 ac_get_arg(&ctx->ac, ctx->args->streamout_offset[i]);
1869
1870 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
1871 LLVMConstInt(ctx->ac.i32, 4, false), "");
1872
1873 so_write_offset[i] =
1874 ac_build_imad(&ctx->ac, so_write_index,
1875 LLVMConstInt(ctx->ac.i32,
1876 stride * 4, false),
1877 so_offset);
1878 }
1879
1880 /* Write streamout data. */
1881 for (i = 0; i < ctx->args->shader_info->so.num_outputs; i++) {
1882 struct radv_shader_output_values shader_out = {};
1883 struct radv_stream_output *output =
1884 &ctx->args->shader_info->so.outputs[i];
1885
1886 if (stream != output->stream)
1887 continue;
1888
1889 for (int j = 0; j < 4; j++) {
1890 shader_out.values[j] =
1891 radv_load_output(ctx, output->location, j);
1892 }
1893
1894 radv_emit_stream_output(ctx, so_buffers,so_write_offset,
1895 output, &shader_out);
1896 }
1897 }
1898 ac_build_endif(&ctx->ac, 6501);
1899 }
1900
1901 static void
1902 radv_build_param_exports(struct radv_shader_context *ctx,
1903 struct radv_shader_output_values *outputs,
1904 unsigned noutput,
1905 struct radv_vs_output_info *outinfo,
1906 bool export_clip_dists)
1907 {
1908 unsigned param_count = 0;
1909
1910 for (unsigned i = 0; i < noutput; i++) {
1911 unsigned slot_name = outputs[i].slot_name;
1912 unsigned usage_mask = outputs[i].usage_mask;
1913
1914 if (slot_name != VARYING_SLOT_LAYER &&
1915 slot_name != VARYING_SLOT_PRIMITIVE_ID &&
1916 slot_name != VARYING_SLOT_CLIP_DIST0 &&
1917 slot_name != VARYING_SLOT_CLIP_DIST1 &&
1918 slot_name < VARYING_SLOT_VAR0)
1919 continue;
1920
1921 if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
1922 slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
1923 continue;
1924
1925 radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
1926
1927 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
1928 outinfo->vs_output_param_offset[slot_name] = param_count++;
1929 }
1930
1931 outinfo->param_exports = param_count;
1932 }
1933
1934 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1935 * (position and parameter data only).
1936 */
1937 static void
1938 radv_llvm_export_vs(struct radv_shader_context *ctx,
1939 struct radv_shader_output_values *outputs,
1940 unsigned noutput,
1941 struct radv_vs_output_info *outinfo,
1942 bool export_clip_dists)
1943 {
1944 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
1945 struct ac_export_args pos_args[4] = {};
1946 unsigned pos_idx, index;
1947 int i;
1948
1949 /* Build position exports */
1950 for (i = 0; i < noutput; i++) {
1951 switch (outputs[i].slot_name) {
1952 case VARYING_SLOT_POS:
1953 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1954 V_008DFC_SQ_EXP_POS, &pos_args[0]);
1955 break;
1956 case VARYING_SLOT_PSIZ:
1957 psize_value = outputs[i].values[0];
1958 break;
1959 case VARYING_SLOT_LAYER:
1960 layer_value = outputs[i].values[0];
1961 break;
1962 case VARYING_SLOT_VIEWPORT:
1963 viewport_value = outputs[i].values[0];
1964 break;
1965 case VARYING_SLOT_CLIP_DIST0:
1966 case VARYING_SLOT_CLIP_DIST1:
1967 index = 2 + outputs[i].slot_index;
1968 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1969 V_008DFC_SQ_EXP_POS + index,
1970 &pos_args[index]);
1971 break;
1972 default:
1973 break;
1974 }
1975 }
1976
1977 /* We need to add the position output manually if it's missing. */
1978 if (!pos_args[0].out[0]) {
1979 pos_args[0].enabled_channels = 0xf; /* writemask */
1980 pos_args[0].valid_mask = 0; /* EXEC mask */
1981 pos_args[0].done = 0; /* last export? */
1982 pos_args[0].target = V_008DFC_SQ_EXP_POS;
1983 pos_args[0].compr = 0; /* COMPR flag */
1984 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
1985 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
1986 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
1987 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
1988 }
1989
1990 if (outinfo->writes_pointsize ||
1991 outinfo->writes_layer ||
1992 outinfo->writes_viewport_index) {
1993 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
1994 (outinfo->writes_layer == true ? 4 : 0));
1995 pos_args[1].valid_mask = 0;
1996 pos_args[1].done = 0;
1997 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
1998 pos_args[1].compr = 0;
1999 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2000 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2001 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2002 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2003
2004 if (outinfo->writes_pointsize == true)
2005 pos_args[1].out[0] = psize_value;
2006 if (outinfo->writes_layer == true)
2007 pos_args[1].out[2] = layer_value;
2008 if (outinfo->writes_viewport_index == true) {
2009 if (ctx->args->options->chip_class >= GFX9) {
2010 /* GFX9 has the layer in out.z[10:0] and the viewport
2011 * index in out.z[19:16].
2012 */
2013 LLVMValueRef v = viewport_value;
2014 v = ac_to_integer(&ctx->ac, v);
2015 v = LLVMBuildShl(ctx->ac.builder, v,
2016 LLVMConstInt(ctx->ac.i32, 16, false),
2017 "");
2018 v = LLVMBuildOr(ctx->ac.builder, v,
2019 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2020
2021 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2022 pos_args[1].enabled_channels |= 1 << 2;
2023 } else {
2024 pos_args[1].out[3] = viewport_value;
2025 pos_args[1].enabled_channels |= 1 << 3;
2026 }
2027 }
2028 }
2029
2030 for (i = 0; i < 4; i++) {
2031 if (pos_args[i].out[0])
2032 outinfo->pos_exports++;
2033 }
2034
2035 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2036 * Setting valid_mask=1 prevents it and has no other effect.
2037 */
2038 if (ctx->ac.family == CHIP_NAVI10 ||
2039 ctx->ac.family == CHIP_NAVI12 ||
2040 ctx->ac.family == CHIP_NAVI14)
2041 pos_args[0].valid_mask = 1;
2042
2043 pos_idx = 0;
2044 for (i = 0; i < 4; i++) {
2045 if (!pos_args[i].out[0])
2046 continue;
2047
2048 /* Specify the target we are exporting */
2049 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2050
2051 if (pos_idx == outinfo->pos_exports)
2052 /* Specify that this is the last export */
2053 pos_args[i].done = 1;
2054
2055 ac_build_export(&ctx->ac, &pos_args[i]);
2056 }
2057
2058 /* Build parameter exports */
2059 radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
2060 }
2061
2062 static void
2063 handle_vs_outputs_post(struct radv_shader_context *ctx,
2064 bool export_prim_id,
2065 bool export_clip_dists,
2066 struct radv_vs_output_info *outinfo)
2067 {
2068 struct radv_shader_output_values *outputs;
2069 unsigned noutput = 0;
2070
2071 if (ctx->args->options->key.has_multiview_view_index) {
2072 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2073 if(!*tmp_out) {
2074 for(unsigned i = 0; i < 4; ++i)
2075 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2076 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2077 }
2078
2079 LLVMValueRef view_index = ac_get_arg(&ctx->ac, ctx->args->ac.view_index);
2080 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, view_index), *tmp_out);
2081 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2082 }
2083
2084 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2085 sizeof(outinfo->vs_output_param_offset));
2086 outinfo->pos_exports = 0;
2087
2088 if (!ctx->args->options->use_ngg_streamout &&
2089 ctx->args->shader_info->so.num_outputs &&
2090 !ctx->args->is_gs_copy_shader) {
2091 /* The GS copy shader emission already emits streamout. */
2092 radv_emit_streamout(ctx, 0);
2093 }
2094
2095 /* Allocate a temporary array for the output values. */
2096 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
2097 outputs = malloc(num_outputs * sizeof(outputs[0]));
2098
2099 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2100 if (!(ctx->output_mask & (1ull << i)))
2101 continue;
2102
2103 outputs[noutput].slot_name = i;
2104 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2105
2106 if (ctx->stage == MESA_SHADER_VERTEX &&
2107 !ctx->args->is_gs_copy_shader) {
2108 outputs[noutput].usage_mask =
2109 ctx->args->shader_info->vs.output_usage_mask[i];
2110 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2111 outputs[noutput].usage_mask =
2112 ctx->args->shader_info->tes.output_usage_mask[i];
2113 } else {
2114 assert(ctx->args->is_gs_copy_shader);
2115 outputs[noutput].usage_mask =
2116 ctx->args->shader_info->gs.output_usage_mask[i];
2117 }
2118
2119 for (unsigned j = 0; j < 4; j++) {
2120 outputs[noutput].values[j] =
2121 ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2122 }
2123
2124 noutput++;
2125 }
2126
2127 /* Export PrimitiveID. */
2128 if (export_prim_id) {
2129 outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
2130 outputs[noutput].slot_index = 0;
2131 outputs[noutput].usage_mask = 0x1;
2132 outputs[noutput].values[0] =
2133 ac_get_arg(&ctx->ac, ctx->args->vs_prim_id);
2134 for (unsigned j = 1; j < 4; j++)
2135 outputs[noutput].values[j] = ctx->ac.f32_0;
2136 noutput++;
2137 }
2138
2139 radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
2140
2141 free(outputs);
2142 }
2143
2144 static void
2145 handle_es_outputs_post(struct radv_shader_context *ctx,
2146 struct radv_es_output_info *outinfo)
2147 {
2148 int j;
2149 LLVMValueRef lds_base = NULL;
2150
2151 if (ctx->ac.chip_class >= GFX9) {
2152 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2153 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2154 LLVMValueRef wave_idx =
2155 ac_unpack_param(&ctx->ac,
2156 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2157 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2158 LLVMBuildMul(ctx->ac.builder, wave_idx,
2159 LLVMConstInt(ctx->ac.i32,
2160 ctx->ac.wave_size, false), ""), "");
2161 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2162 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2163 }
2164
2165 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2166 LLVMValueRef dw_addr = NULL;
2167 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2168 unsigned output_usage_mask;
2169 int param_index;
2170
2171 if (!(ctx->output_mask & (1ull << i)))
2172 continue;
2173
2174 if (ctx->stage == MESA_SHADER_VERTEX) {
2175 output_usage_mask =
2176 ctx->args->shader_info->vs.output_usage_mask[i];
2177 } else {
2178 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2179 output_usage_mask =
2180 ctx->args->shader_info->tes.output_usage_mask[i];
2181 }
2182
2183 param_index = shader_io_get_unique_index(i);
2184
2185 if (lds_base) {
2186 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2187 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2188 "");
2189 }
2190
2191 for (j = 0; j < 4; j++) {
2192 if (!(output_usage_mask & (1 << j)))
2193 continue;
2194
2195 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2196 out_val = ac_to_integer(&ctx->ac, out_val);
2197 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2198
2199 if (ctx->ac.chip_class >= GFX9) {
2200 LLVMValueRef dw_addr_offset =
2201 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2202 LLVMConstInt(ctx->ac.i32,
2203 j, false), "");
2204
2205 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2206 } else {
2207 ac_build_buffer_store_dword(&ctx->ac,
2208 ctx->esgs_ring,
2209 out_val, 1,
2210 NULL,
2211 ac_get_arg(&ctx->ac, ctx->args->es2gs_offset),
2212 (4 * param_index + j) * 4,
2213 ac_glc | ac_slc | ac_swizzled);
2214 }
2215 }
2216 }
2217 }
2218
2219 static void
2220 handle_ls_outputs_post(struct radv_shader_context *ctx)
2221 {
2222 LLVMValueRef vertex_id = ctx->rel_auto_id;
2223 uint32_t num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
2224 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2225 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2226 vertex_dw_stride, "");
2227
2228 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2229 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2230
2231 if (!(ctx->output_mask & (1ull << i)))
2232 continue;
2233
2234 int param = shader_io_get_unique_index(i);
2235 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2236 LLVMConstInt(ctx->ac.i32, param * 4, false),
2237 "");
2238 for (unsigned j = 0; j < 4; j++) {
2239 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2240 value = ac_to_integer(&ctx->ac, value);
2241 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2242 ac_lds_store(&ctx->ac, dw_addr, value);
2243 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2244 }
2245 }
2246 }
2247
2248 static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
2249 {
2250 return ac_unpack_param(&ctx->ac,
2251 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2252 }
2253
2254 static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
2255 {
2256 return ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 28, 4);
2257 }
2258
2259 static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
2260 {
2261 LLVMBuilderRef builder = ctx->ac.builder;
2262 LLVMValueRef tmp;
2263 tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
2264 LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
2265 return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
2266 }
2267
2268 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
2269 {
2270 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2271 LLVMConstInt(ctx->ac.i32, 12, false),
2272 LLVMConstInt(ctx->ac.i32, 9, false),
2273 false);
2274 }
2275
2276 static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
2277 {
2278 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2279 LLVMConstInt(ctx->ac.i32, 22, false),
2280 LLVMConstInt(ctx->ac.i32, 9, false),
2281 false);
2282 }
2283
2284 static LLVMValueRef ngg_get_ordered_id(struct radv_shader_context *ctx)
2285 {
2286 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2287 ctx->ac.i32_0,
2288 LLVMConstInt(ctx->ac.i32, 12, false),
2289 false);
2290 }
2291
2292 static LLVMValueRef
2293 ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
2294 {
2295 unsigned num_outputs = util_bitcount64(ctx->output_mask);
2296
2297 if (ctx->args->options->key.has_multiview_view_index)
2298 num_outputs++;
2299
2300 LLVMTypeRef elements[2] = {
2301 LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
2302 LLVMArrayType(ctx->ac.i8, 4),
2303 };
2304 LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
2305 type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
2306 return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
2307 }
2308
2309 /**
2310 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2311 * is in emit order; that is:
2312 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2313 * - during vertex emit, i.e. while the API GS shader invocation is running,
2314 * N = threadidx * gs_max_out_vertices + emitidx
2315 *
2316 * Goals of the LDS memory layout:
2317 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2318 * in uniform control flow
2319 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2320 * culling
2321 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2322 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2323 * 5. Avoid wasting memory.
2324 *
2325 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2326 * layout, elimination of bank conflicts requires that each vertex occupy an
2327 * odd number of dwords. We use the additional dword to store the output stream
2328 * index as well as a flag to indicate whether this vertex ends a primitive
2329 * for rasterization.
2330 *
2331 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2332 *
2333 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2334 * Indices are swizzled in groups of 32, which ensures point 1 without
2335 * disturbing point 2.
2336 *
2337 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2338 */
2339 static LLVMValueRef
2340 ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
2341 {
2342 LLVMBuilderRef builder = ctx->ac.builder;
2343 LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
2344
2345 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2346 unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
2347 if (write_stride_2exp) {
2348 LLVMValueRef row =
2349 LLVMBuildLShr(builder, vertexidx,
2350 LLVMConstInt(ctx->ac.i32, 5, false), "");
2351 LLVMValueRef swizzle =
2352 LLVMBuildAnd(builder, row,
2353 LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
2354 false), "");
2355 vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
2356 }
2357
2358 return ac_build_gep0(&ctx->ac, storage, vertexidx);
2359 }
2360
2361 static LLVMValueRef
2362 ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
2363 LLVMValueRef emitidx)
2364 {
2365 LLVMBuilderRef builder = ctx->ac.builder;
2366 LLVMValueRef tmp;
2367
2368 tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
2369 tmp = LLVMBuildMul(builder, tmp, gsthread, "");
2370 const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
2371 return ngg_gs_vertex_ptr(ctx, vertexidx);
2372 }
2373
2374 static LLVMValueRef
2375 ngg_gs_get_emit_output_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2376 unsigned out_idx)
2377 {
2378 LLVMValueRef gep_idx[3] = {
2379 ctx->ac.i32_0, /* implied C-style array */
2380 ctx->ac.i32_0, /* first struct entry */
2381 LLVMConstInt(ctx->ac.i32, out_idx, false),
2382 };
2383 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2384 }
2385
2386 static LLVMValueRef
2387 ngg_gs_get_emit_primflag_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2388 unsigned stream)
2389 {
2390 LLVMValueRef gep_idx[3] = {
2391 ctx->ac.i32_0, /* implied C-style array */
2392 ctx->ac.i32_1, /* second struct entry */
2393 LLVMConstInt(ctx->ac.i32, stream, false),
2394 };
2395 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2396 }
2397
2398 static struct radv_stream_output *
2399 radv_get_stream_output_by_loc(struct radv_streamout_info *so, unsigned location)
2400 {
2401 for (unsigned i = 0; i < so->num_outputs; ++i) {
2402 if (so->outputs[i].location == location)
2403 return &so->outputs[i];
2404 }
2405
2406 return NULL;
2407 }
2408
2409 static void build_streamout_vertex(struct radv_shader_context *ctx,
2410 LLVMValueRef *so_buffer, LLVMValueRef *wg_offset_dw,
2411 unsigned stream, LLVMValueRef offset_vtx,
2412 LLVMValueRef vertexptr)
2413 {
2414 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2415 LLVMBuilderRef builder = ctx->ac.builder;
2416 LLVMValueRef offset[4] = {};
2417 LLVMValueRef tmp;
2418
2419 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2420 if (!wg_offset_dw[buffer])
2421 continue;
2422
2423 tmp = LLVMBuildMul(builder, offset_vtx,
2424 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false), "");
2425 tmp = LLVMBuildAdd(builder, wg_offset_dw[buffer], tmp, "");
2426 offset[buffer] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
2427 }
2428
2429 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2430 struct radv_shader_output_values outputs[AC_LLVM_MAX_OUTPUTS];
2431 unsigned noutput = 0;
2432 unsigned out_idx = 0;
2433
2434 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2435 unsigned output_usage_mask =
2436 ctx->args->shader_info->gs.output_usage_mask[i];
2437 uint8_t output_stream =
2438 output_stream = ctx->args->shader_info->gs.output_streams[i];
2439
2440 if (!(ctx->output_mask & (1ull << i)) ||
2441 output_stream != stream)
2442 continue;
2443
2444 outputs[noutput].slot_name = i;
2445 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2446 outputs[noutput].usage_mask = output_usage_mask;
2447
2448 int length = util_last_bit(output_usage_mask);
2449
2450 for (unsigned j = 0; j < length; j++, out_idx++) {
2451 if (!(output_usage_mask & (1 << j)))
2452 continue;
2453
2454 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2455 LLVMConstInt(ctx->ac.i32, out_idx, false));
2456 outputs[noutput].values[j] = LLVMBuildLoad(builder, tmp, "");
2457 }
2458
2459 for (unsigned j = length; j < 4; j++)
2460 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
2461
2462 noutput++;
2463 }
2464
2465 for (unsigned i = 0; i < noutput; i++) {
2466 struct radv_stream_output *output =
2467 radv_get_stream_output_by_loc(so, outputs[i].slot_name);
2468
2469 if (!output ||
2470 output->stream != stream)
2471 continue;
2472
2473 struct radv_shader_output_values out = {};
2474
2475 for (unsigned j = 0; j < 4; j++) {
2476 out.values[j] = outputs[i].values[j];
2477 }
2478
2479 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2480 }
2481 } else {
2482 for (unsigned i = 0; i < so->num_outputs; ++i) {
2483 struct radv_stream_output *output =
2484 &ctx->args->shader_info->so.outputs[i];
2485
2486 if (stream != output->stream)
2487 continue;
2488
2489 struct radv_shader_output_values out = {};
2490
2491 for (unsigned comp = 0; comp < 4; comp++) {
2492 if (!(output->component_mask & (1 << comp)))
2493 continue;
2494
2495 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2496 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2497 out.values[comp] = LLVMBuildLoad(builder, tmp, "");
2498 }
2499
2500 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2501 }
2502 }
2503 }
2504
2505 struct ngg_streamout {
2506 LLVMValueRef num_vertices;
2507
2508 /* per-thread data */
2509 LLVMValueRef prim_enable[4]; /* i1 per stream */
2510 LLVMValueRef vertices[3]; /* [N x i32] addrspace(LDS)* */
2511
2512 /* Output */
2513 LLVMValueRef emit[4]; /* per-stream emitted primitives (only valid for used streams) */
2514 };
2515
2516 /**
2517 * Build streamout logic.
2518 *
2519 * Implies a barrier.
2520 *
2521 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2522 *
2523 * Clobbers gs_ngg_scratch[8:].
2524 */
2525 static void build_streamout(struct radv_shader_context *ctx,
2526 struct ngg_streamout *nggso)
2527 {
2528 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2529 LLVMBuilderRef builder = ctx->ac.builder;
2530 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
2531 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2532 LLVMValueRef cond, tmp, tmp2;
2533 LLVMValueRef i32_2 = LLVMConstInt(ctx->ac.i32, 2, false);
2534 LLVMValueRef i32_4 = LLVMConstInt(ctx->ac.i32, 4, false);
2535 LLVMValueRef i32_8 = LLVMConstInt(ctx->ac.i32, 8, false);
2536 LLVMValueRef so_buffer[4] = {};
2537 unsigned max_num_vertices = 1 + (nggso->vertices[1] ? 1 : 0) +
2538 (nggso->vertices[2] ? 1 : 0);
2539 LLVMValueRef prim_stride_dw[4] = {};
2540 LLVMValueRef prim_stride_dw_vgpr = LLVMGetUndef(ctx->ac.i32);
2541 int stream_for_buffer[4] = { -1, -1, -1, -1 };
2542 unsigned bufmask_for_stream[4] = {};
2543 bool isgs = ctx->stage == MESA_SHADER_GEOMETRY;
2544 unsigned scratch_emit_base = isgs ? 4 : 0;
2545 LLVMValueRef scratch_emit_basev = isgs ? i32_4 : ctx->ac.i32_0;
2546 unsigned scratch_offset_base = isgs ? 8 : 4;
2547 LLVMValueRef scratch_offset_basev = isgs ? i32_8 : i32_4;
2548
2549 ac_llvm_add_target_dep_function_attr(ctx->main_function,
2550 "amdgpu-gds-size", 256);
2551
2552 /* Determine the mapping of streamout buffers to vertex streams. */
2553 for (unsigned i = 0; i < so->num_outputs; ++i) {
2554 unsigned buf = so->outputs[i].buffer;
2555 unsigned stream = so->outputs[i].stream;
2556 assert(stream_for_buffer[buf] < 0 || stream_for_buffer[buf] == stream);
2557 stream_for_buffer[buf] = stream;
2558 bufmask_for_stream[stream] |= 1 << buf;
2559 }
2560
2561 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2562 if (stream_for_buffer[buffer] == -1)
2563 continue;
2564
2565 assert(so->strides[buffer]);
2566
2567 LLVMValueRef stride_for_buffer =
2568 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false);
2569 prim_stride_dw[buffer] =
2570 LLVMBuildMul(builder, stride_for_buffer,
2571 nggso->num_vertices, "");
2572 prim_stride_dw_vgpr = ac_build_writelane(
2573 &ctx->ac, prim_stride_dw_vgpr, prim_stride_dw[buffer],
2574 LLVMConstInt(ctx->ac.i32, buffer, false));
2575
2576 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, buffer, false);
2577 so_buffer[buffer] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr,
2578 offset);
2579 }
2580
2581 cond = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
2582 ac_build_ifcc(&ctx->ac, cond, 5200);
2583 {
2584 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
2585 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
2586
2587 /* Advance the streamout offsets in GDS. */
2588 LLVMValueRef offsets_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2589 LLVMValueRef generated_by_stream_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2590
2591 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2592 ac_build_ifcc(&ctx->ac, cond, 5210);
2593 {
2594 /* Fetch the number of generated primitives and store
2595 * it in GDS for later use.
2596 */
2597 if (isgs) {
2598 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid);
2599 tmp = LLVMBuildLoad(builder, tmp, "");
2600 } else {
2601 tmp = ac_build_writelane(&ctx->ac, ctx->ac.i32_0,
2602 ngg_get_prim_cnt(ctx), ctx->ac.i32_0);
2603 }
2604 LLVMBuildStore(builder, tmp, generated_by_stream_vgpr);
2605
2606 unsigned swizzle[4];
2607 int unused_stream = -1;
2608 for (unsigned stream = 0; stream < 4; ++stream) {
2609 if (!ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2610 unused_stream = stream;
2611 break;
2612 }
2613 }
2614 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2615 if (stream_for_buffer[buffer] >= 0) {
2616 swizzle[buffer] = stream_for_buffer[buffer];
2617 } else {
2618 assert(unused_stream >= 0);
2619 swizzle[buffer] = unused_stream;
2620 }
2621 }
2622
2623 tmp = ac_build_quad_swizzle(&ctx->ac, tmp,
2624 swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2625 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2626
2627 LLVMValueRef args[] = {
2628 LLVMBuildIntToPtr(builder, ngg_get_ordered_id(ctx), gdsptr, ""),
2629 tmp,
2630 ctx->ac.i32_0, // ordering
2631 ctx->ac.i32_0, // scope
2632 ctx->ac.i1false, // isVolatile
2633 LLVMConstInt(ctx->ac.i32, 4 << 24, false), // OA index
2634 ctx->ac.i1true, // wave release
2635 ctx->ac.i1true, // wave done
2636 };
2637
2638 tmp = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.ordered.add",
2639 ctx->ac.i32, args, ARRAY_SIZE(args), 0);
2640
2641 /* Keep offsets in a VGPR for quick retrieval via readlane by
2642 * the first wave for bounds checking, and also store in LDS
2643 * for retrieval by all waves later. */
2644 LLVMBuildStore(builder, tmp, offsets_vgpr);
2645
2646 tmp2 = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2647 scratch_offset_basev, "");
2648 tmp2 = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp2);
2649 LLVMBuildStore(builder, tmp, tmp2);
2650 }
2651 ac_build_endif(&ctx->ac, 5210);
2652
2653 /* Determine the max emit per buffer. This is done via the SALU, in part
2654 * because LLVM can't generate divide-by-multiply if we try to do this
2655 * via VALU with one lane per buffer.
2656 */
2657 LLVMValueRef max_emit[4] = {};
2658 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2659 if (stream_for_buffer[buffer] == -1)
2660 continue;
2661
2662 /* Compute the streamout buffer size in DWORD. */
2663 LLVMValueRef bufsize_dw =
2664 LLVMBuildLShr(builder,
2665 LLVMBuildExtractElement(builder, so_buffer[buffer], i32_2, ""),
2666 i32_2, "");
2667
2668 /* Load the streamout buffer offset from GDS. */
2669 tmp = LLVMBuildLoad(builder, offsets_vgpr, "");
2670 LLVMValueRef offset_dw =
2671 ac_build_readlane(&ctx->ac, tmp,
2672 LLVMConstInt(ctx->ac.i32, buffer, false));
2673
2674 /* Compute the remaining size to emit. */
2675 LLVMValueRef remaining_dw =
2676 LLVMBuildSub(builder, bufsize_dw, offset_dw, "");
2677 tmp = LLVMBuildUDiv(builder, remaining_dw,
2678 prim_stride_dw[buffer], "");
2679
2680 cond = LLVMBuildICmp(builder, LLVMIntULT,
2681 bufsize_dw, offset_dw, "");
2682 max_emit[buffer] = LLVMBuildSelect(builder, cond,
2683 ctx->ac.i32_0, tmp, "");
2684 }
2685
2686 /* Determine the number of emitted primitives per stream and fixup the
2687 * GDS counter if necessary.
2688 *
2689 * This is complicated by the fact that a single stream can emit to
2690 * multiple buffers (but luckily not vice versa).
2691 */
2692 LLVMValueRef emit_vgpr = ctx->ac.i32_0;
2693
2694 for (unsigned stream = 0; stream < 4; ++stream) {
2695 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2696 continue;
2697
2698 /* Load the number of generated primitives from GDS and
2699 * determine that number for the given stream.
2700 */
2701 tmp = LLVMBuildLoad(builder, generated_by_stream_vgpr, "");
2702 LLVMValueRef generated =
2703 ac_build_readlane(&ctx->ac, tmp,
2704 LLVMConstInt(ctx->ac.i32, stream, false));
2705
2706
2707 /* Compute the number of emitted primitives. */
2708 LLVMValueRef emit = generated;
2709 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2710 if (stream_for_buffer[buffer] == stream)
2711 emit = ac_build_umin(&ctx->ac, emit, max_emit[buffer]);
2712 }
2713
2714 /* Store the number of emitted primitives for that
2715 * stream.
2716 */
2717 emit_vgpr = ac_build_writelane(&ctx->ac, emit_vgpr, emit,
2718 LLVMConstInt(ctx->ac.i32, stream, false));
2719
2720 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2721 cond = LLVMBuildICmp(builder, LLVMIntULT, emit, generated, "");
2722 ac_build_ifcc(&ctx->ac, cond, 5221); /* scalar branch */
2723 tmp = LLVMBuildLShr(builder,
2724 LLVMConstInt(ctx->ac.i32, bufmask_for_stream[stream], false),
2725 ac_get_thread_id(&ctx->ac), "");
2726 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2727 ac_build_ifcc(&ctx->ac, tmp, 5222);
2728 {
2729 tmp = LLVMBuildSub(builder, generated, emit, "");
2730 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2731 tmp2 = LLVMBuildGEP(builder, gdsbase, &tid, 1, "");
2732 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpSub, tmp2, tmp,
2733 LLVMAtomicOrderingMonotonic, false);
2734 }
2735 ac_build_endif(&ctx->ac, 5222);
2736 ac_build_endif(&ctx->ac, 5221);
2737 }
2738
2739 /* Store the number of emitted primitives to LDS for later use. */
2740 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2741 ac_build_ifcc(&ctx->ac, cond, 5225);
2742 {
2743 tmp = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2744 scratch_emit_basev, "");
2745 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp);
2746 LLVMBuildStore(builder, emit_vgpr, tmp);
2747 }
2748 ac_build_endif(&ctx->ac, 5225);
2749 }
2750 ac_build_endif(&ctx->ac, 5200);
2751
2752 /* Determine the workgroup-relative per-thread / primitive offset into
2753 * the streamout buffers */
2754 struct ac_wg_scan primemit_scan[4] = {};
2755
2756 if (isgs) {
2757 for (unsigned stream = 0; stream < 4; ++stream) {
2758 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2759 continue;
2760
2761 primemit_scan[stream].enable_exclusive = true;
2762 primemit_scan[stream].op = nir_op_iadd;
2763 primemit_scan[stream].src = nggso->prim_enable[stream];
2764 primemit_scan[stream].scratch =
2765 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
2766 LLVMConstInt(ctx->ac.i32, 12 + 8 * stream, false));
2767 primemit_scan[stream].waveidx = get_wave_id_in_tg(ctx);
2768 primemit_scan[stream].numwaves = get_tgsize(ctx);
2769 primemit_scan[stream].maxwaves = 8;
2770 ac_build_wg_scan_top(&ctx->ac, &primemit_scan[stream]);
2771 }
2772 }
2773
2774 ac_build_s_barrier(&ctx->ac);
2775
2776 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2777 LLVMValueRef wgoffset_dw[4] = {};
2778
2779 {
2780 LLVMValueRef scratch_vgpr;
2781
2782 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ac_get_thread_id(&ctx->ac));
2783 scratch_vgpr = LLVMBuildLoad(builder, tmp, "");
2784
2785 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2786 if (stream_for_buffer[buffer] >= 0) {
2787 wgoffset_dw[buffer] = ac_build_readlane(
2788 &ctx->ac, scratch_vgpr,
2789 LLVMConstInt(ctx->ac.i32, scratch_offset_base + buffer, false));
2790 }
2791 }
2792
2793 for (unsigned stream = 0; stream < 4; ++stream) {
2794 if (ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2795 nggso->emit[stream] = ac_build_readlane(
2796 &ctx->ac, scratch_vgpr,
2797 LLVMConstInt(ctx->ac.i32, scratch_emit_base + stream, false));
2798 }
2799 }
2800 }
2801
2802 /* Write out primitive data */
2803 for (unsigned stream = 0; stream < 4; ++stream) {
2804 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2805 continue;
2806
2807 if (isgs) {
2808 ac_build_wg_scan_bottom(&ctx->ac, &primemit_scan[stream]);
2809 } else {
2810 primemit_scan[stream].result_exclusive = tid;
2811 }
2812
2813 cond = LLVMBuildICmp(builder, LLVMIntULT,
2814 primemit_scan[stream].result_exclusive,
2815 nggso->emit[stream], "");
2816 cond = LLVMBuildAnd(builder, cond, nggso->prim_enable[stream], "");
2817 ac_build_ifcc(&ctx->ac, cond, 5240);
2818 {
2819 LLVMValueRef offset_vtx =
2820 LLVMBuildMul(builder, primemit_scan[stream].result_exclusive,
2821 nggso->num_vertices, "");
2822
2823 for (unsigned i = 0; i < max_num_vertices; ++i) {
2824 cond = LLVMBuildICmp(builder, LLVMIntULT,
2825 LLVMConstInt(ctx->ac.i32, i, false),
2826 nggso->num_vertices, "");
2827 ac_build_ifcc(&ctx->ac, cond, 5241);
2828 build_streamout_vertex(ctx, so_buffer, wgoffset_dw,
2829 stream, offset_vtx, nggso->vertices[i]);
2830 ac_build_endif(&ctx->ac, 5241);
2831 offset_vtx = LLVMBuildAdd(builder, offset_vtx, ctx->ac.i32_1, "");
2832 }
2833 }
2834 ac_build_endif(&ctx->ac, 5240);
2835 }
2836 }
2837
2838 static unsigned ngg_nogs_vertex_size(struct radv_shader_context *ctx)
2839 {
2840 unsigned lds_vertex_size = 0;
2841
2842 if (ctx->args->shader_info->so.num_outputs)
2843 lds_vertex_size = 4 * ctx->args->shader_info->so.num_outputs + 1;
2844
2845 return lds_vertex_size;
2846 }
2847
2848 /**
2849 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2850 * for the vertex outputs.
2851 */
2852 static LLVMValueRef ngg_nogs_vertex_ptr(struct radv_shader_context *ctx,
2853 LLVMValueRef vtxid)
2854 {
2855 /* The extra dword is used to avoid LDS bank conflicts. */
2856 unsigned vertex_size = ngg_nogs_vertex_size(ctx);
2857 LLVMTypeRef ai32 = LLVMArrayType(ctx->ac.i32, vertex_size);
2858 LLVMTypeRef pai32 = LLVMPointerType(ai32, AC_ADDR_SPACE_LDS);
2859 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, ctx->esgs_ring, pai32, "");
2860 return LLVMBuildGEP(ctx->ac.builder, tmp, &vtxid, 1, "");
2861 }
2862
2863 static void
2864 handle_ngg_outputs_post_1(struct radv_shader_context *ctx)
2865 {
2866 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2867 LLVMBuilderRef builder = ctx->ac.builder;
2868 LLVMValueRef vertex_ptr = NULL;
2869 LLVMValueRef tmp, tmp2;
2870
2871 assert((ctx->stage == MESA_SHADER_VERTEX ||
2872 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2873
2874 if (!ctx->args->shader_info->so.num_outputs)
2875 return;
2876
2877 vertex_ptr = ngg_nogs_vertex_ptr(ctx, get_thread_id_in_tg(ctx));
2878
2879 for (unsigned i = 0; i < so->num_outputs; ++i) {
2880 struct radv_stream_output *output =
2881 &ctx->args->shader_info->so.outputs[i];
2882
2883 unsigned loc = output->location;
2884
2885 for (unsigned comp = 0; comp < 4; comp++) {
2886 if (!(output->component_mask & (1 << comp)))
2887 continue;
2888
2889 tmp = ac_build_gep0(&ctx->ac, vertex_ptr,
2890 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2891 tmp2 = LLVMBuildLoad(builder,
2892 ctx->abi.outputs[4 * loc + comp], "");
2893 tmp2 = ac_to_integer(&ctx->ac, tmp2);
2894 LLVMBuildStore(builder, tmp2, tmp);
2895 }
2896 }
2897 }
2898
2899 static void
2900 handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
2901 {
2902 LLVMBuilderRef builder = ctx->ac.builder;
2903 LLVMValueRef tmp;
2904
2905 assert((ctx->stage == MESA_SHADER_VERTEX ||
2906 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2907
2908 LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac,
2909 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
2910 LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac,
2911 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 0, 8);
2912 LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
2913 ac_get_thread_id(&ctx->ac), prims_in_wave, "");
2914 LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
2915 ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
2916 LLVMValueRef vtxindex[] = {
2917 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 0, 16),
2918 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 16, 16),
2919 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[2]), 0, 16),
2920 };
2921
2922 /* Determine the number of vertices per primitive. */
2923 unsigned num_vertices;
2924 LLVMValueRef num_vertices_val;
2925
2926 if (ctx->stage == MESA_SHADER_VERTEX) {
2927 LLVMValueRef outprim_val =
2928 LLVMConstInt(ctx->ac.i32,
2929 ctx->args->options->key.vs.outprim, false);
2930 num_vertices_val = LLVMBuildAdd(builder, outprim_val,
2931 ctx->ac.i32_1, "");
2932 num_vertices = 3; /* TODO: optimize for points & lines */
2933 } else {
2934 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2935
2936 if (ctx->shader->info.tess.point_mode)
2937 num_vertices = 1;
2938 else if (ctx->shader->info.tess.primitive_mode == GL_ISOLINES)
2939 num_vertices = 2;
2940 else
2941 num_vertices = 3;
2942
2943 num_vertices_val = LLVMConstInt(ctx->ac.i32, num_vertices, false);
2944 }
2945
2946 /* Streamout */
2947 if (ctx->args->shader_info->so.num_outputs) {
2948 struct ngg_streamout nggso = {};
2949
2950 nggso.num_vertices = num_vertices_val;
2951 nggso.prim_enable[0] = is_gs_thread;
2952
2953 for (unsigned i = 0; i < num_vertices; ++i)
2954 nggso.vertices[i] = ngg_nogs_vertex_ptr(ctx, vtxindex[i]);
2955
2956 build_streamout(ctx, &nggso);
2957 }
2958
2959 /* Copy Primitive IDs from GS threads to the LDS address corresponding
2960 * to the ES thread of the provoking vertex.
2961 */
2962 if (ctx->stage == MESA_SHADER_VERTEX &&
2963 ctx->args->options->key.vs_common_out.export_prim_id) {
2964 if (ctx->args->shader_info->so.num_outputs)
2965 ac_build_s_barrier(&ctx->ac);
2966
2967 ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
2968 /* Extract the PROVOKING_VTX_INDEX field. */
2969 LLVMValueRef provoking_vtx_in_prim =
2970 LLVMConstInt(ctx->ac.i32, 0, false);
2971
2972 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
2973 LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
2974 LLVMValueRef provoking_vtx_index =
2975 LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
2976
2977 LLVMBuildStore(builder, ac_get_arg(&ctx->ac, ctx->args->ac.gs_prim_id),
2978 ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
2979 ac_build_endif(&ctx->ac, 5400);
2980 }
2981
2982 /* TODO: primitive culling */
2983
2984 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
2985 ngg_get_vtx_cnt(ctx), ngg_get_prim_cnt(ctx));
2986
2987 /* TODO: streamout queries */
2988 /* Export primitive data to the index buffer.
2989 *
2990 * For the first version, we will always build up all three indices
2991 * independent of the primitive type. The additional garbage data
2992 * shouldn't hurt.
2993 *
2994 * TODO: culling depends on the primitive type, so can have some
2995 * interaction here.
2996 */
2997 ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
2998 {
2999 struct ac_ngg_prim prim = {};
3000
3001 if (ctx->args->options->key.vs_common_out.as_ngg_passthrough) {
3002 prim.passthrough = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]);
3003 } else {
3004 prim.num_vertices = num_vertices;
3005 prim.isnull = ctx->ac.i1false;
3006 memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
3007
3008 for (unsigned i = 0; i < num_vertices; ++i) {
3009 tmp = LLVMBuildLShr(builder,
3010 ac_get_arg(&ctx->ac, ctx->args->ac.gs_invocation_id),
3011 LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
3012 prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3013 }
3014 }
3015
3016 ac_build_export_prim(&ctx->ac, &prim);
3017 }
3018 ac_build_endif(&ctx->ac, 6001);
3019
3020 /* Export per-vertex data (positions and parameters). */
3021 ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
3022 {
3023 struct radv_vs_output_info *outinfo =
3024 ctx->stage == MESA_SHADER_TESS_EVAL ?
3025 &ctx->args->shader_info->tes.outinfo : &ctx->args->shader_info->vs.outinfo;
3026
3027 /* Exporting the primitive ID is handled below. */
3028 /* TODO: use the new VS export path */
3029 handle_vs_outputs_post(ctx, false,
3030 ctx->args->options->key.vs_common_out.export_clip_dists,
3031 outinfo);
3032
3033 if (ctx->args->options->key.vs_common_out.export_prim_id) {
3034 unsigned param_count = outinfo->param_exports;
3035 LLVMValueRef values[4];
3036
3037 if (ctx->stage == MESA_SHADER_VERTEX) {
3038 /* Wait for GS stores to finish. */
3039 ac_build_s_barrier(&ctx->ac);
3040
3041 tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
3042 get_thread_id_in_tg(ctx));
3043 values[0] = LLVMBuildLoad(builder, tmp, "");
3044 } else {
3045 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
3046 values[0] = ac_get_arg(&ctx->ac, ctx->args->ac.tes_patch_id);
3047 }
3048
3049 values[0] = ac_to_float(&ctx->ac, values[0]);
3050 for (unsigned j = 1; j < 4; j++)
3051 values[j] = ctx->ac.f32_0;
3052
3053 radv_export_param(ctx, param_count, values, 0x1);
3054
3055 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
3056 outinfo->param_exports = param_count;
3057 }
3058 }
3059 ac_build_endif(&ctx->ac, 6002);
3060 }
3061
3062 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
3063 {
3064 /* Zero out the part of LDS scratch that is used to accumulate the
3065 * per-stream generated primitive count.
3066 */
3067 LLVMBuilderRef builder = ctx->ac.builder;
3068 LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
3069 LLVMValueRef tid = get_thread_id_in_tg(ctx);
3070 LLVMBasicBlockRef merge_block;
3071 LLVMValueRef cond;
3072
3073 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
3074 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3075 merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3076
3077 cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
3078 LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
3079 LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
3080
3081 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
3082 LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
3083
3084 LLVMBuildBr(ctx->ac.builder, merge_block);
3085 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
3086
3087 ac_build_s_barrier(&ctx->ac);
3088 }
3089
3090 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
3091 {
3092 LLVMBuilderRef builder = ctx->ac.builder;
3093 LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
3094 LLVMValueRef tmp;
3095
3096 /* Zero out remaining (non-emitted) primitive flags.
3097 *
3098 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3099 * the emit threads via LDS. This is likely worse in the expected
3100 * typical case where each GS thread emits the full set of
3101 * vertices.
3102 */
3103 for (unsigned stream = 0; stream < 4; ++stream) {
3104 unsigned num_components;
3105
3106 num_components =
3107 ctx->args->shader_info->gs.num_stream_output_components[stream];
3108 if (!num_components)
3109 continue;
3110
3111 const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
3112
3113 ac_build_bgnloop(&ctx->ac, 5100);
3114
3115 const LLVMValueRef vertexidx =
3116 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3117 tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
3118 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3119 ac_build_ifcc(&ctx->ac, tmp, 5101);
3120 ac_build_break(&ctx->ac);
3121 ac_build_endif(&ctx->ac, 5101);
3122
3123 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3124 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3125
3126 tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
3127 LLVMBuildStore(builder, i8_0,
3128 ngg_gs_get_emit_primflag_ptr(ctx, tmp, stream));
3129
3130 ac_build_endloop(&ctx->ac, 5100);
3131 }
3132
3133 /* Accumulate generated primitives counts across the entire threadgroup. */
3134 for (unsigned stream = 0; stream < 4; ++stream) {
3135 unsigned num_components;
3136
3137 num_components =
3138 ctx->args->shader_info->gs.num_stream_output_components[stream];
3139 if (!num_components)
3140 continue;
3141
3142 LLVMValueRef numprims =
3143 LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3144 numprims = ac_build_reduce(&ctx->ac, numprims, nir_op_iadd, ctx->ac.wave_size);
3145
3146 tmp = LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(&ctx->ac), ctx->ac.i32_0, "");
3147 ac_build_ifcc(&ctx->ac, tmp, 5105);
3148 {
3149 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
3150 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
3151 LLVMConstInt(ctx->ac.i32, stream, false)),
3152 numprims, LLVMAtomicOrderingMonotonic, false);
3153 }
3154 ac_build_endif(&ctx->ac, 5105);
3155 }
3156 }
3157
3158 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
3159 {
3160 const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
3161 LLVMBuilderRef builder = ctx->ac.builder;
3162 LLVMValueRef tmp, tmp2;
3163
3164 ac_build_s_barrier(&ctx->ac);
3165
3166 const LLVMValueRef tid = get_thread_id_in_tg(ctx);
3167 LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
3168
3169 /* Streamout */
3170 if (ctx->args->shader_info->so.num_outputs) {
3171 struct ngg_streamout nggso = {};
3172
3173 nggso.num_vertices = LLVMConstInt(ctx->ac.i32, verts_per_prim, false);
3174
3175 LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tid);
3176 for (unsigned stream = 0; stream < 4; ++stream) {
3177 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
3178 continue;
3179
3180 tmp = LLVMBuildLoad(builder,
3181 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream), "");
3182 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3183 tmp2 = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3184 nggso.prim_enable[stream] = LLVMBuildAnd(builder, tmp, tmp2, "");
3185 }
3186
3187 for (unsigned i = 0; i < verts_per_prim; ++i) {
3188 tmp = LLVMBuildSub(builder, tid,
3189 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3190 tmp = ngg_gs_vertex_ptr(ctx, tmp);
3191 nggso.vertices[i] = ac_build_gep0(&ctx->ac, tmp, ctx->ac.i32_0);
3192 }
3193
3194 build_streamout(ctx, &nggso);
3195 }
3196
3197 /* TODO: culling */
3198
3199 /* Determine vertex liveness. */
3200 LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
3201
3202 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3203 ac_build_ifcc(&ctx->ac, tmp, 5120);
3204 {
3205 for (unsigned i = 0; i < verts_per_prim; ++i) {
3206 const LLVMValueRef primidx =
3207 LLVMBuildAdd(builder, tid,
3208 LLVMConstInt(ctx->ac.i32, i, false), "");
3209
3210 if (i > 0) {
3211 tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
3212 ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
3213 }
3214
3215 /* Load primitive liveness */
3216 tmp = ngg_gs_vertex_ptr(ctx, primidx);
3217 tmp = LLVMBuildLoad(builder,
3218 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3219 const LLVMValueRef primlive =
3220 LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3221
3222 tmp = LLVMBuildLoad(builder, vertliveptr, "");
3223 tmp = LLVMBuildOr(builder, tmp, primlive, ""),
3224 LLVMBuildStore(builder, tmp, vertliveptr);
3225
3226 if (i > 0)
3227 ac_build_endif(&ctx->ac, 5121 + i);
3228 }
3229 }
3230 ac_build_endif(&ctx->ac, 5120);
3231
3232 /* Inclusive scan addition across the current wave. */
3233 LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
3234 struct ac_wg_scan vertlive_scan = {};
3235 vertlive_scan.op = nir_op_iadd;
3236 vertlive_scan.enable_reduce = true;
3237 vertlive_scan.enable_exclusive = true;
3238 vertlive_scan.src = vertlive;
3239 vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
3240 vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
3241 vertlive_scan.numwaves = get_tgsize(ctx);
3242 vertlive_scan.maxwaves = 8;
3243
3244 ac_build_wg_scan(&ctx->ac, &vertlive_scan);
3245
3246 /* Skip all exports (including index exports) when possible. At least on
3247 * early gfx10 revisions this is also to avoid hangs.
3248 */
3249 LLVMValueRef have_exports =
3250 LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
3251 num_emit_threads =
3252 LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
3253
3254 /* Allocate export space. Send this message as early as possible, to
3255 * hide the latency of the SQ <-> SPI roundtrip.
3256 *
3257 * Note: We could consider compacting primitives for export as well.
3258 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3259 * prim data per clock and skips null primitives at no additional
3260 * cost. So compacting primitives can only be beneficial when
3261 * there are 4 or more contiguous null primitives in the export
3262 * (in the common case of single-dword prim exports).
3263 */
3264 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
3265 vertlive_scan.result_reduce, num_emit_threads);
3266
3267 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3268 * of the primitive liveness flags, relying on the fact that each
3269 * threadgroup can have at most 256 threads. */
3270 ac_build_ifcc(&ctx->ac, vertlive, 5130);
3271 {
3272 tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
3273 tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
3274 LLVMBuildStore(builder, tmp2,
3275 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1));
3276 }
3277 ac_build_endif(&ctx->ac, 5130);
3278
3279 ac_build_s_barrier(&ctx->ac);
3280
3281 /* Export primitive data */
3282 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3283 ac_build_ifcc(&ctx->ac, tmp, 5140);
3284 {
3285 LLVMValueRef flags;
3286 struct ac_ngg_prim prim = {};
3287 prim.num_vertices = verts_per_prim;
3288
3289 tmp = ngg_gs_vertex_ptr(ctx, tid);
3290 flags = LLVMBuildLoad(builder,
3291 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3292 prim.isnull = LLVMBuildNot(builder, LLVMBuildTrunc(builder, flags, ctx->ac.i1, ""), "");
3293
3294 for (unsigned i = 0; i < verts_per_prim; ++i) {
3295 prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
3296 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3297 prim.edgeflag[i] = ctx->ac.i1false;
3298 }
3299
3300 /* Geometry shaders output triangle strips, but NGG expects
3301 * triangles. We need to change the vertex order for odd
3302 * triangles to get correct front/back facing by swapping 2
3303 * vertex indices, but we also have to keep the provoking
3304 * vertex in the same place.
3305 */
3306 if (verts_per_prim == 3) {
3307 LLVMValueRef is_odd = LLVMBuildLShr(builder, flags, ctx->ac.i8_1, "");
3308 is_odd = LLVMBuildTrunc(builder, is_odd, ctx->ac.i1, "");
3309
3310 struct ac_ngg_prim in = prim;
3311 prim.index[0] = in.index[0];
3312 prim.index[1] = LLVMBuildSelect(builder, is_odd,
3313 in.index[2], in.index[1], "");
3314 prim.index[2] = LLVMBuildSelect(builder, is_odd,
3315 in.index[1], in.index[2], "");
3316 }
3317
3318 ac_build_export_prim(&ctx->ac, &prim);
3319 }
3320 ac_build_endif(&ctx->ac, 5140);
3321
3322 /* Export position and parameter data */
3323 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
3324 ac_build_ifcc(&ctx->ac, tmp, 5145);
3325 {
3326 struct radv_vs_output_info *outinfo = &ctx->args->shader_info->vs.outinfo;
3327 bool export_view_index = ctx->args->options->key.has_multiview_view_index;
3328 struct radv_shader_output_values *outputs;
3329 unsigned noutput = 0;
3330
3331 /* Allocate a temporary array for the output values. */
3332 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
3333 outputs = calloc(num_outputs, sizeof(outputs[0]));
3334
3335 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
3336 sizeof(outinfo->vs_output_param_offset));
3337 outinfo->pos_exports = 0;
3338
3339 tmp = ngg_gs_vertex_ptr(ctx, tid);
3340 tmp = LLVMBuildLoad(builder,
3341 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1), "");
3342 tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
3343 const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
3344
3345 unsigned out_idx = 0;
3346 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3347 unsigned output_usage_mask =
3348 ctx->args->shader_info->gs.output_usage_mask[i];
3349 int length = util_last_bit(output_usage_mask);
3350
3351 if (!(ctx->output_mask & (1ull << i)))
3352 continue;
3353
3354 outputs[noutput].slot_name = i;
3355 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
3356 outputs[noutput].usage_mask = output_usage_mask;
3357
3358 for (unsigned j = 0; j < length; j++, out_idx++) {
3359 if (!(output_usage_mask & (1 << j)))
3360 continue;
3361
3362 tmp = ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx);
3363 tmp = LLVMBuildLoad(builder, tmp, "");
3364
3365 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3366 if (ac_get_type_size(type) == 2) {
3367 tmp = ac_to_integer(&ctx->ac, tmp);
3368 tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
3369 }
3370
3371 outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
3372 }
3373
3374 for (unsigned j = length; j < 4; j++)
3375 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
3376
3377 noutput++;
3378 }
3379
3380 /* Export ViewIndex. */
3381 if (export_view_index) {
3382 outputs[noutput].slot_name = VARYING_SLOT_LAYER;
3383 outputs[noutput].slot_index = 0;
3384 outputs[noutput].usage_mask = 0x1;
3385 outputs[noutput].values[0] =
3386 ac_to_float(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.view_index));
3387 for (unsigned j = 1; j < 4; j++)
3388 outputs[noutput].values[j] = ctx->ac.f32_0;
3389 noutput++;
3390 }
3391
3392 radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
3393 ctx->args->options->key.vs_common_out.export_clip_dists);
3394 FREE(outputs);
3395 }
3396 ac_build_endif(&ctx->ac, 5145);
3397 }
3398
3399 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
3400 unsigned stream,
3401 LLVMValueRef *addrs)
3402 {
3403 LLVMBuilderRef builder = ctx->ac.builder;
3404 LLVMValueRef tmp;
3405 const LLVMValueRef vertexidx =
3406 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3407
3408 /* If this thread has already emitted the declared maximum number of
3409 * vertices, skip the write: excessive vertex emissions are not
3410 * supposed to have any effect.
3411 */
3412 const LLVMValueRef can_emit =
3413 LLVMBuildICmp(builder, LLVMIntULT, vertexidx,
3414 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3415 ac_build_ifcc(&ctx->ac, can_emit, 9001);
3416
3417 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3418 tmp = LLVMBuildSelect(builder, can_emit, tmp, vertexidx, "");
3419 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3420
3421 const LLVMValueRef vertexptr =
3422 ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
3423 unsigned out_idx = 0;
3424 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3425 unsigned output_usage_mask =
3426 ctx->args->shader_info->gs.output_usage_mask[i];
3427 uint8_t output_stream =
3428 ctx->args->shader_info->gs.output_streams[i];
3429 LLVMValueRef *out_ptr = &addrs[i * 4];
3430 int length = util_last_bit(output_usage_mask);
3431
3432 if (!(ctx->output_mask & (1ull << i)) ||
3433 output_stream != stream)
3434 continue;
3435
3436 for (unsigned j = 0; j < length; j++, out_idx++) {
3437 if (!(output_usage_mask & (1 << j)))
3438 continue;
3439
3440 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
3441 out_ptr[j], "");
3442 out_val = ac_to_integer(&ctx->ac, out_val);
3443 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
3444
3445 LLVMBuildStore(builder, out_val,
3446 ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx));
3447 }
3448 }
3449 assert(out_idx * 4 <= ctx->args->shader_info->gs.gsvs_vertex_size);
3450
3451 /* Determine and store whether this vertex completed a primitive. */
3452 const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
3453
3454 tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
3455 const LLVMValueRef iscompleteprim =
3456 LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
3457
3458 /* Since the geometry shader emits triangle strips, we need to
3459 * track which primitive is odd and swap vertex indices to get
3460 * the correct vertex order.
3461 */
3462 LLVMValueRef is_odd = ctx->ac.i1false;
3463 if (stream == 0 &&
3464 si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) == 3) {
3465 tmp = LLVMBuildAnd(builder, curverts, ctx->ac.i32_1, "");
3466 is_odd = LLVMBuildICmp(builder, LLVMIntEQ, tmp, ctx->ac.i32_1, "");
3467 }
3468
3469 tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
3470 LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
3471
3472 /* The per-vertex primitive flag encoding:
3473 * bit 0: whether this vertex finishes a primitive
3474 * bit 1: whether the primitive is odd (if we are emitting triangle strips)
3475 */
3476 tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
3477 tmp = LLVMBuildOr(builder, tmp,
3478 LLVMBuildShl(builder,
3479 LLVMBuildZExt(builder, is_odd, ctx->ac.i8, ""),
3480 ctx->ac.i8_1, ""), "");
3481 LLVMBuildStore(builder, tmp,
3482 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream));
3483
3484 tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3485 tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
3486 LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
3487
3488 ac_build_endif(&ctx->ac, 9001);
3489 }
3490
3491 static void
3492 write_tess_factors(struct radv_shader_context *ctx)
3493 {
3494 unsigned stride, outer_comps, inner_comps;
3495 LLVMValueRef tcs_rel_ids = ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids);
3496 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 8, 5);
3497 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 0, 8);
3498 unsigned tess_inner_index = 0, tess_outer_index;
3499 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
3500 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3501 int i;
3502 ac_emit_barrier(&ctx->ac, ctx->stage);
3503
3504 switch (ctx->args->options->key.tcs.primitive_mode) {
3505 case GL_ISOLINES:
3506 stride = 2;
3507 outer_comps = 2;
3508 inner_comps = 0;
3509 break;
3510 case GL_TRIANGLES:
3511 stride = 4;
3512 outer_comps = 3;
3513 inner_comps = 1;
3514 break;
3515 case GL_QUADS:
3516 stride = 6;
3517 outer_comps = 4;
3518 inner_comps = 2;
3519 break;
3520 default:
3521 return;
3522 }
3523
3524 ac_build_ifcc(&ctx->ac,
3525 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3526 invocation_id, ctx->ac.i32_0, ""), 6503);
3527
3528 lds_base = get_tcs_out_current_patch_data_offset(ctx);
3529
3530 if (inner_comps) {
3531 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3532 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3533 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3534 }
3535
3536 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3537 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3538 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3539
3540 for (i = 0; i < 4; i++) {
3541 inner[i] = LLVMGetUndef(ctx->ac.i32);
3542 outer[i] = LLVMGetUndef(ctx->ac.i32);
3543 }
3544
3545 // LINES reversal
3546 if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
3547 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3548 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3549 ctx->ac.i32_1, "");
3550 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3551 } else {
3552 for (i = 0; i < outer_comps; i++) {
3553 outer[i] = out[i] =
3554 ac_lds_load(&ctx->ac, lds_outer);
3555 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3556 ctx->ac.i32_1, "");
3557 }
3558 for (i = 0; i < inner_comps; i++) {
3559 inner[i] = out[outer_comps+i] =
3560 ac_lds_load(&ctx->ac, lds_inner);
3561 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3562 ctx->ac.i32_1, "");
3563 }
3564 }
3565
3566 /* Convert the outputs to vectors for stores. */
3567 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3568 vec1 = NULL;
3569
3570 if (stride > 4)
3571 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3572
3573
3574 buffer = ctx->hs_ring_tess_factor;
3575 tf_base = ac_get_arg(&ctx->ac, ctx->args->tess_factor_offset);
3576 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3577 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3578 unsigned tf_offset = 0;
3579
3580 if (ctx->ac.chip_class <= GFX8) {
3581 ac_build_ifcc(&ctx->ac,
3582 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3583 rel_patch_id, ctx->ac.i32_0, ""), 6504);
3584
3585 /* Store the dynamic HS control word. */
3586 ac_build_buffer_store_dword(&ctx->ac, buffer,
3587 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3588 1, ctx->ac.i32_0, tf_base,
3589 0, ac_glc);
3590 tf_offset += 4;
3591
3592 ac_build_endif(&ctx->ac, 6504);
3593 }
3594
3595 /* Store the tessellation factors. */
3596 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3597 MIN2(stride, 4), byteoffset, tf_base,
3598 tf_offset, ac_glc);
3599 if (vec1)
3600 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3601 stride - 4, byteoffset, tf_base,
3602 16 + tf_offset, ac_glc);
3603
3604 //store to offchip for TES to read - only if TES reads them
3605 if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
3606 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3607 LLVMValueRef tf_inner_offset;
3608 unsigned param_outer, param_inner;
3609
3610 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3611 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3612 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3613
3614 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3615 util_next_power_of_two(outer_comps));
3616
3617 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3618 outer_comps, tf_outer_offset,
3619 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3620 0, ac_glc);
3621 if (inner_comps) {
3622 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3623 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3624 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3625
3626 inner_vec = inner_comps == 1 ? inner[0] :
3627 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3628 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3629 inner_comps, tf_inner_offset,
3630 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3631 0, ac_glc);
3632 }
3633 }
3634
3635 ac_build_endif(&ctx->ac, 6503);
3636 }
3637
3638 static void
3639 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3640 {
3641 write_tess_factors(ctx);
3642 }
3643
3644 static bool
3645 si_export_mrt_color(struct radv_shader_context *ctx,
3646 LLVMValueRef *color, unsigned index,
3647 struct ac_export_args *args)
3648 {
3649 /* Export */
3650 si_llvm_init_export_args(ctx, color, 0xf,
3651 V_008DFC_SQ_EXP_MRT + index, args);
3652 if (!args->enabled_channels)
3653 return false; /* unnecessary NULL export */
3654
3655 return true;
3656 }
3657
3658 static void
3659 radv_export_mrt_z(struct radv_shader_context *ctx,
3660 LLVMValueRef depth, LLVMValueRef stencil,
3661 LLVMValueRef samplemask)
3662 {
3663 struct ac_export_args args;
3664
3665 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3666
3667 ac_build_export(&ctx->ac, &args);
3668 }
3669
3670 static void
3671 handle_fs_outputs_post(struct radv_shader_context *ctx)
3672 {
3673 unsigned index = 0;
3674 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3675 struct ac_export_args color_args[8];
3676
3677 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3678 LLVMValueRef values[4];
3679
3680 if (!(ctx->output_mask & (1ull << i)))
3681 continue;
3682
3683 if (i < FRAG_RESULT_DATA0)
3684 continue;
3685
3686 for (unsigned j = 0; j < 4; j++)
3687 values[j] = ac_to_float(&ctx->ac,
3688 radv_load_output(ctx, i, j));
3689
3690 bool ret = si_export_mrt_color(ctx, values,
3691 i - FRAG_RESULT_DATA0,
3692 &color_args[index]);
3693 if (ret)
3694 index++;
3695 }
3696
3697 /* Process depth, stencil, samplemask. */
3698 if (ctx->args->shader_info->ps.writes_z) {
3699 depth = ac_to_float(&ctx->ac,
3700 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3701 }
3702 if (ctx->args->shader_info->ps.writes_stencil) {
3703 stencil = ac_to_float(&ctx->ac,
3704 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3705 }
3706 if (ctx->args->shader_info->ps.writes_sample_mask) {
3707 samplemask = ac_to_float(&ctx->ac,
3708 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3709 }
3710
3711 /* Set the DONE bit on last non-null color export only if Z isn't
3712 * exported.
3713 */
3714 if (index > 0 &&
3715 !ctx->args->shader_info->ps.writes_z &&
3716 !ctx->args->shader_info->ps.writes_stencil &&
3717 !ctx->args->shader_info->ps.writes_sample_mask) {
3718 unsigned last = index - 1;
3719
3720 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3721 color_args[last].done = 1; /* DONE bit */
3722 }
3723
3724 /* Export PS outputs. */
3725 for (unsigned i = 0; i < index; i++)
3726 ac_build_export(&ctx->ac, &color_args[i]);
3727
3728 if (depth || stencil || samplemask)
3729 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3730 else if (!index)
3731 ac_build_export_null(&ctx->ac);
3732 }
3733
3734 static void
3735 emit_gs_epilogue(struct radv_shader_context *ctx)
3736 {
3737 if (ctx->args->options->key.vs_common_out.as_ngg) {
3738 gfx10_ngg_gs_emit_epilogue_1(ctx);
3739 return;
3740 }
3741
3742 if (ctx->ac.chip_class >= GFX10)
3743 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3744
3745 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3746 }
3747
3748 static void
3749 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3750 LLVMValueRef *addrs)
3751 {
3752 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3753
3754 switch (ctx->stage) {
3755 case MESA_SHADER_VERTEX:
3756 if (ctx->args->options->key.vs_common_out.as_ls)
3757 handle_ls_outputs_post(ctx);
3758 else if (ctx->args->options->key.vs_common_out.as_es)
3759 handle_es_outputs_post(ctx, &ctx->args->shader_info->vs.es_info);
3760 else if (ctx->args->options->key.vs_common_out.as_ngg)
3761 handle_ngg_outputs_post_1(ctx);
3762 else
3763 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3764 ctx->args->options->key.vs_common_out.export_clip_dists,
3765 &ctx->args->shader_info->vs.outinfo);
3766 break;
3767 case MESA_SHADER_FRAGMENT:
3768 handle_fs_outputs_post(ctx);
3769 break;
3770 case MESA_SHADER_GEOMETRY:
3771 emit_gs_epilogue(ctx);
3772 break;
3773 case MESA_SHADER_TESS_CTRL:
3774 handle_tcs_outputs_post(ctx);
3775 break;
3776 case MESA_SHADER_TESS_EVAL:
3777 if (ctx->args->options->key.vs_common_out.as_es)
3778 handle_es_outputs_post(ctx, &ctx->args->shader_info->tes.es_info);
3779 else if (ctx->args->options->key.vs_common_out.as_ngg)
3780 handle_ngg_outputs_post_1(ctx);
3781 else
3782 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3783 ctx->args->options->key.vs_common_out.export_clip_dists,
3784 &ctx->args->shader_info->tes.outinfo);
3785 break;
3786 default:
3787 break;
3788 }
3789 }
3790
3791 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3792 LLVMPassManagerRef passmgr,
3793 const struct radv_nir_compiler_options *options)
3794 {
3795 LLVMRunPassManager(passmgr, ctx->ac.module);
3796 LLVMDisposeBuilder(ctx->ac.builder);
3797
3798 ac_llvm_context_dispose(&ctx->ac);
3799 }
3800
3801 static void
3802 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3803 {
3804 struct radv_vs_output_info *outinfo;
3805
3806 switch (ctx->stage) {
3807 case MESA_SHADER_FRAGMENT:
3808 case MESA_SHADER_COMPUTE:
3809 case MESA_SHADER_TESS_CTRL:
3810 case MESA_SHADER_GEOMETRY:
3811 return;
3812 case MESA_SHADER_VERTEX:
3813 if (ctx->args->options->key.vs_common_out.as_ls ||
3814 ctx->args->options->key.vs_common_out.as_es)
3815 return;
3816 outinfo = &ctx->args->shader_info->vs.outinfo;
3817 break;
3818 case MESA_SHADER_TESS_EVAL:
3819 if (ctx->args->options->key.vs_common_out.as_es)
3820 return;
3821 outinfo = &ctx->args->shader_info->tes.outinfo;
3822 break;
3823 default:
3824 unreachable("Unhandled shader type");
3825 }
3826
3827 ac_optimize_vs_outputs(&ctx->ac,
3828 ctx->main_function,
3829 outinfo->vs_output_param_offset,
3830 VARYING_SLOT_MAX,
3831 &outinfo->param_exports);
3832 }
3833
3834 static void
3835 ac_setup_rings(struct radv_shader_context *ctx)
3836 {
3837 if (ctx->args->options->chip_class <= GFX8 &&
3838 (ctx->stage == MESA_SHADER_GEOMETRY ||
3839 ctx->args->options->key.vs_common_out.as_es || ctx->args->options->key.vs_common_out.as_es)) {
3840 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3841 : RING_ESGS_VS;
3842 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3843
3844 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3845 ctx->ring_offsets,
3846 offset);
3847 }
3848
3849 if (ctx->args->is_gs_copy_shader) {
3850 ctx->gsvs_ring[0] =
3851 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3852 LLVMConstInt(ctx->ac.i32,
3853 RING_GSVS_VS, false));
3854 }
3855
3856 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3857 /* The conceptual layout of the GSVS ring is
3858 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3859 * but the real memory layout is swizzled across
3860 * threads:
3861 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3862 * t16v0c0 ..
3863 * Override the buffer descriptor accordingly.
3864 */
3865 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3866 uint64_t stream_offset = 0;
3867 unsigned num_records = ctx->ac.wave_size;
3868 LLVMValueRef base_ring;
3869
3870 base_ring =
3871 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3872 LLVMConstInt(ctx->ac.i32,
3873 RING_GSVS_GS, false));
3874
3875 for (unsigned stream = 0; stream < 4; stream++) {
3876 unsigned num_components, stride;
3877 LLVMValueRef ring, tmp;
3878
3879 num_components =
3880 ctx->args->shader_info->gs.num_stream_output_components[stream];
3881
3882 if (!num_components)
3883 continue;
3884
3885 stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
3886
3887 /* Limit on the stride field for <= GFX7. */
3888 assert(stride < (1 << 14));
3889
3890 ring = LLVMBuildBitCast(ctx->ac.builder,
3891 base_ring, v2i64, "");
3892 tmp = LLVMBuildExtractElement(ctx->ac.builder,
3893 ring, ctx->ac.i32_0, "");
3894 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
3895 LLVMConstInt(ctx->ac.i64,
3896 stream_offset, 0), "");
3897 ring = LLVMBuildInsertElement(ctx->ac.builder,
3898 ring, tmp, ctx->ac.i32_0, "");
3899
3900 stream_offset += stride * ctx->ac.wave_size;
3901
3902 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
3903 ctx->ac.v4i32, "");
3904
3905 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3906 ctx->ac.i32_1, "");
3907 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3908 LLVMConstInt(ctx->ac.i32,
3909 S_008F04_STRIDE(stride), false), "");
3910 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3911 ctx->ac.i32_1, "");
3912
3913 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3914 LLVMConstInt(ctx->ac.i32,
3915 num_records, false),
3916 LLVMConstInt(ctx->ac.i32, 2, false), "");
3917
3918 ctx->gsvs_ring[stream] = ring;
3919 }
3920 }
3921
3922 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3923 ctx->stage == MESA_SHADER_TESS_EVAL) {
3924 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3925 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3926 }
3927 }
3928
3929 unsigned
3930 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
3931 gl_shader_stage stage,
3932 const struct nir_shader *nir)
3933 {
3934 const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
3935 unsigned sizes[3];
3936 for (unsigned i = 0; i < 3; i++)
3937 sizes[i] = nir ? nir->info.cs.local_size[i] : backup_sizes[i];
3938 return radv_get_max_workgroup_size(chip_class, stage, sizes);
3939 }
3940
3941 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3942 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3943 {
3944 LLVMValueRef count =
3945 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
3946 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3947 ctx->ac.i32_0, "");
3948 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3949 ac_get_arg(&ctx->ac, ctx->args->rel_auto_id),
3950 ctx->abi.instance_id, "");
3951 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3952 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
3953 ctx->rel_auto_id,
3954 "");
3955 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3956 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_patch_id),
3957 ctx->abi.vertex_id, "");
3958 }
3959
3960 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx, bool merged)
3961 {
3962 if (merged) {
3963 for(int i = 5; i >= 0; --i) {
3964 ctx->gs_vtx_offset[i] =
3965 ac_unpack_param(&ctx->ac,
3966 ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i & ~1]),
3967 (i & 1) * 16, 16);
3968 }
3969
3970 ctx->gs_wave_id = ac_unpack_param(&ctx->ac,
3971 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info),
3972 16, 8);
3973 } else {
3974 for (int i = 0; i < 6; i++)
3975 ctx->gs_vtx_offset[i] = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i]);
3976 ctx->gs_wave_id = ac_get_arg(&ctx->ac, ctx->args->gs_wave_id);
3977 }
3978 }
3979
3980 /* Ensure that the esgs ring is declared.
3981 *
3982 * We declare it with 64KB alignment as a hint that the
3983 * pointer value will always be 0.
3984 */
3985 static void declare_esgs_ring(struct radv_shader_context *ctx)
3986 {
3987 if (ctx->esgs_ring)
3988 return;
3989
3990 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
3991
3992 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
3993 ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
3994 "esgs_ring",
3995 AC_ADDR_SPACE_LDS);
3996 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
3997 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
3998 }
3999
4000 static
4001 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
4002 struct nir_shader *const *shaders,
4003 int shader_count,
4004 const struct radv_shader_args *args)
4005 {
4006 struct radv_shader_context ctx = {0};
4007 ctx.args = args;
4008
4009 enum ac_float_mode float_mode = AC_FLOAT_MODE_DEFAULT;
4010
4011 if (args->shader_info->float_controls_mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32) {
4012 float_mode = AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO;
4013 }
4014
4015 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
4016 args->options->family, float_mode,
4017 args->shader_info->wave_size, 64);
4018 ctx.context = ctx.ac.context;
4019
4020 ctx.max_workgroup_size = 0;
4021 for (int i = 0; i < shader_count; ++i) {
4022 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
4023 radv_nir_get_max_workgroup_size(args->options->chip_class,
4024 shaders[i]->info.stage,
4025 shaders[i]));
4026 }
4027
4028 if (ctx.ac.chip_class >= GFX10) {
4029 if (is_pre_gs_stage(shaders[0]->info.stage) &&
4030 args->options->key.vs_common_out.as_ngg) {
4031 ctx.max_workgroup_size = 128;
4032 }
4033 }
4034
4035 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2);
4036
4037 ctx.abi.inputs = &ctx.inputs[0];
4038 ctx.abi.emit_outputs = handle_shader_outputs_post;
4039 ctx.abi.emit_vertex = visit_emit_vertex;
4040 ctx.abi.load_ubo = radv_load_ubo;
4041 ctx.abi.load_ssbo = radv_load_ssbo;
4042 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
4043 ctx.abi.load_resource = radv_load_resource;
4044 ctx.abi.clamp_shadow_reference = false;
4045 ctx.abi.robust_buffer_access = args->options->robust_buffer_access;
4046
4047 bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && args->options->key.vs_common_out.as_ngg;
4048 if (shader_count >= 2 || is_ngg)
4049 ac_init_exec_full_mask(&ctx.ac);
4050
4051 if (args->ac.vertex_id.used)
4052 ctx.abi.vertex_id = ac_get_arg(&ctx.ac, args->ac.vertex_id);
4053 if (args->rel_auto_id.used)
4054 ctx.rel_auto_id = ac_get_arg(&ctx.ac, args->rel_auto_id);
4055 if (args->ac.instance_id.used)
4056 ctx.abi.instance_id = ac_get_arg(&ctx.ac, args->ac.instance_id);
4057
4058 if (args->options->has_ls_vgpr_init_bug &&
4059 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
4060 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
4061
4062 if (is_ngg) {
4063 /* Declare scratch space base for streamout and vertex
4064 * compaction. Whether space is actually allocated is
4065 * determined during linking / PM4 creation.
4066 *
4067 * Add an extra dword per vertex to ensure an odd stride, which
4068 * avoids bank conflicts for SoA accesses.
4069 */
4070 if (!args->options->key.vs_common_out.as_ngg_passthrough)
4071 declare_esgs_ring(&ctx);
4072
4073 /* This is really only needed when streamout and / or vertex
4074 * compaction is enabled.
4075 */
4076 if (args->shader_info->so.num_outputs) {
4077 LLVMTypeRef asi32 = LLVMArrayType(ctx.ac.i32, 8);
4078 ctx.gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4079 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4080 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(asi32));
4081 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4082 }
4083 }
4084
4085 for(int i = 0; i < shader_count; ++i) {
4086 ctx.stage = shaders[i]->info.stage;
4087 ctx.shader = shaders[i];
4088 ctx.output_mask = 0;
4089
4090 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
4091 for (int i = 0; i < 4; i++) {
4092 ctx.gs_next_vertex[i] =
4093 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4094 }
4095 if (args->options->key.vs_common_out.as_ngg) {
4096 for (unsigned i = 0; i < 4; ++i) {
4097 ctx.gs_curprim_verts[i] =
4098 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4099 ctx.gs_generated_prims[i] =
4100 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4101 }
4102
4103 unsigned scratch_size = 8;
4104 if (args->shader_info->so.num_outputs)
4105 scratch_size = 44;
4106
4107 LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, scratch_size);
4108 ctx.gs_ngg_scratch =
4109 LLVMAddGlobalInAddressSpace(ctx.ac.module,
4110 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4111 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
4112 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4113
4114 ctx.gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4115 LLVMArrayType(ctx.ac.i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
4116 LLVMSetLinkage(ctx.gs_ngg_emit, LLVMExternalLinkage);
4117 LLVMSetAlignment(ctx.gs_ngg_emit, 4);
4118 }
4119
4120 ctx.abi.load_inputs = load_gs_input;
4121 ctx.abi.emit_primitive = visit_end_primitive;
4122 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4123 ctx.abi.load_tess_varyings = load_tcs_varyings;
4124 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4125 ctx.abi.store_tcs_outputs = store_tcs_output;
4126 if (shader_count == 1)
4127 ctx.tcs_num_inputs = args->options->key.tcs.num_inputs;
4128 else
4129 ctx.tcs_num_inputs = util_last_bit64(args->shader_info->vs.ls_outputs_written);
4130 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
4131 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
4132 ctx.abi.load_tess_varyings = load_tes_input;
4133 ctx.abi.load_tess_coord = load_tess_coord;
4134 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4135 ctx.tcs_num_patches = args->options->key.tes.num_patches;
4136 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
4137 ctx.abi.load_base_vertex = radv_load_base_vertex;
4138 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
4139 ctx.abi.load_sample_position = load_sample_position;
4140 ctx.abi.load_sample_mask_in = load_sample_mask_in;
4141 ctx.abi.emit_kill = radv_emit_kill;
4142 }
4143
4144 if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
4145 args->options->key.vs_common_out.as_ngg &&
4146 args->options->key.vs_common_out.export_prim_id) {
4147 declare_esgs_ring(&ctx);
4148 }
4149
4150 bool nested_barrier = false;
4151
4152 if (i) {
4153 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4154 args->options->key.vs_common_out.as_ngg) {
4155 gfx10_ngg_gs_emit_prologue(&ctx);
4156 nested_barrier = false;
4157 } else {
4158 nested_barrier = true;
4159 }
4160 }
4161
4162 if (nested_barrier) {
4163 /* Execute a barrier before the second shader in
4164 * a merged shader.
4165 *
4166 * Execute the barrier inside the conditional block,
4167 * so that empty waves can jump directly to s_endpgm,
4168 * which will also signal the barrier.
4169 *
4170 * This is possible in gfx9, because an empty wave
4171 * for the second shader does not participate in
4172 * the epilogue. With NGG, empty waves may still
4173 * be required to export data (e.g. GS output vertices),
4174 * so we cannot let them exit early.
4175 *
4176 * If the shader is TCS and the TCS epilog is present
4177 * and contains a barrier, it will wait there and then
4178 * reach s_endpgm.
4179 */
4180 ac_emit_barrier(&ctx.ac, ctx.stage);
4181 }
4182
4183 nir_foreach_variable(variable, &shaders[i]->outputs)
4184 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
4185
4186 ac_setup_rings(&ctx);
4187
4188 LLVMBasicBlockRef merge_block;
4189 if (shader_count >= 2 || is_ngg) {
4190 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
4191 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4192 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4193
4194 LLVMValueRef count =
4195 ac_unpack_param(&ctx.ac,
4196 ac_get_arg(&ctx.ac, args->merged_wave_info),
4197 8 * i, 8);
4198 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
4199 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
4200 thread_id, count, "");
4201 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
4202
4203 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
4204 }
4205
4206 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
4207 prepare_interp_optimize(&ctx, shaders[i]);
4208 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
4209 handle_vs_inputs(&ctx, shaders[i]);
4210 else if(shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
4211 prepare_gs_input_vgprs(&ctx, shader_count >= 2);
4212
4213 ac_nir_translate(&ctx.ac, &ctx.abi, &args->ac, shaders[i]);
4214
4215 if (shader_count >= 2 || is_ngg) {
4216 LLVMBuildBr(ctx.ac.builder, merge_block);
4217 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
4218 }
4219
4220 /* This needs to be outside the if wrapping the shader body, as sometimes
4221 * the HW generates waves with 0 es/vs threads. */
4222 if (is_pre_gs_stage(shaders[i]->info.stage) &&
4223 args->options->key.vs_common_out.as_ngg &&
4224 i == shader_count - 1) {
4225 handle_ngg_outputs_post_2(&ctx);
4226 } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4227 args->options->key.vs_common_out.as_ngg) {
4228 gfx10_ngg_gs_emit_epilogue_2(&ctx);
4229 }
4230
4231 if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4232 args->shader_info->tcs.num_patches = ctx.tcs_num_patches;
4233 args->shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
4234 }
4235 }
4236
4237 LLVMBuildRetVoid(ctx.ac.builder);
4238
4239 if (args->options->dump_preoptir) {
4240 fprintf(stderr, "%s LLVM IR:\n\n",
4241 radv_get_shader_name(args->shader_info,
4242 shaders[shader_count - 1]->info.stage));
4243 ac_dump_module(ctx.ac.module);
4244 fprintf(stderr, "\n");
4245 }
4246
4247 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4248
4249 if (shader_count == 1)
4250 ac_nir_eliminate_const_vs_outputs(&ctx);
4251
4252 if (args->options->dump_shader) {
4253 args->shader_info->private_mem_vgprs =
4254 ac_count_scratch_private_memory(ctx.main_function);
4255 }
4256
4257 return ctx.ac.module;
4258 }
4259
4260 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4261 {
4262 unsigned *retval = (unsigned *)context;
4263 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4264 char *description = LLVMGetDiagInfoDescription(di);
4265
4266 if (severity == LLVMDSError) {
4267 *retval = 1;
4268 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4269 description);
4270 }
4271
4272 LLVMDisposeMessage(description);
4273 }
4274
4275 static unsigned radv_llvm_compile(LLVMModuleRef M,
4276 char **pelf_buffer, size_t *pelf_size,
4277 struct ac_llvm_compiler *ac_llvm)
4278 {
4279 unsigned retval = 0;
4280 LLVMContextRef llvm_ctx;
4281
4282 /* Setup Diagnostic Handler*/
4283 llvm_ctx = LLVMGetModuleContext(M);
4284
4285 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4286 &retval);
4287
4288 /* Compile IR*/
4289 if (!radv_compile_to_elf(ac_llvm, M, pelf_buffer, pelf_size))
4290 retval = 1;
4291 return retval;
4292 }
4293
4294 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
4295 LLVMModuleRef llvm_module,
4296 struct radv_shader_binary **rbinary,
4297 gl_shader_stage stage,
4298 const char *name,
4299 const struct radv_nir_compiler_options *options)
4300 {
4301 char *elf_buffer = NULL;
4302 size_t elf_size = 0;
4303 char *llvm_ir_string = NULL;
4304
4305 if (options->dump_shader) {
4306 fprintf(stderr, "%s LLVM IR:\n\n", name);
4307 ac_dump_module(llvm_module);
4308 fprintf(stderr, "\n");
4309 }
4310
4311 if (options->record_ir) {
4312 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
4313 llvm_ir_string = strdup(llvm_ir);
4314 LLVMDisposeMessage(llvm_ir);
4315 }
4316
4317 int v = radv_llvm_compile(llvm_module, &elf_buffer, &elf_size, ac_llvm);
4318 if (v) {
4319 fprintf(stderr, "compile failed\n");
4320 }
4321
4322 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4323 LLVMDisposeModule(llvm_module);
4324 LLVMContextDispose(ctx);
4325
4326 size_t llvm_ir_size = llvm_ir_string ? strlen(llvm_ir_string) : 0;
4327 size_t alloc_size = sizeof(struct radv_shader_binary_rtld) + elf_size + llvm_ir_size + 1;
4328 struct radv_shader_binary_rtld *rbin = calloc(1, alloc_size);
4329 memcpy(rbin->data, elf_buffer, elf_size);
4330 if (llvm_ir_string)
4331 memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
4332
4333 rbin->base.type = RADV_BINARY_TYPE_RTLD;
4334 rbin->base.stage = stage;
4335 rbin->base.total_size = alloc_size;
4336 rbin->elf_size = elf_size;
4337 rbin->llvm_ir_size = llvm_ir_size;
4338 *rbinary = &rbin->base;
4339
4340 free(llvm_ir_string);
4341 free(elf_buffer);
4342 }
4343
4344 void
4345 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
4346 struct radv_shader_binary **rbinary,
4347 const struct radv_shader_args *args,
4348 struct nir_shader *const *nir,
4349 int nir_count)
4350 {
4351
4352 LLVMModuleRef llvm_module;
4353
4354 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, args);
4355
4356 ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
4357 nir[nir_count - 1]->info.stage,
4358 radv_get_shader_name(args->shader_info,
4359 nir[nir_count - 1]->info.stage),
4360 args->options);
4361
4362 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4363 if (args->options->chip_class >= GFX9) {
4364 if (nir_count == 2 &&
4365 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
4366 args->shader_info->gs.es_type = nir[0]->info.stage;
4367 }
4368 }
4369 }
4370
4371 static void
4372 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
4373 {
4374 LLVMValueRef vtx_offset =
4375 LLVMBuildMul(ctx->ac.builder, ac_get_arg(&ctx->ac, ctx->args->ac.vertex_id),
4376 LLVMConstInt(ctx->ac.i32, 4, false), "");
4377 LLVMValueRef stream_id;
4378
4379 /* Fetch the vertex stream ID. */
4380 if (!ctx->args->options->use_ngg_streamout &&
4381 ctx->args->shader_info->so.num_outputs) {
4382 stream_id =
4383 ac_unpack_param(&ctx->ac,
4384 ac_get_arg(&ctx->ac,
4385 ctx->args->streamout_config),
4386 24, 2);
4387 } else {
4388 stream_id = ctx->ac.i32_0;
4389 }
4390
4391 LLVMBasicBlockRef end_bb;
4392 LLVMValueRef switch_inst;
4393
4394 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
4395 ctx->main_function, "end");
4396 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
4397
4398 for (unsigned stream = 0; stream < 4; stream++) {
4399 unsigned num_components =
4400 ctx->args->shader_info->gs.num_stream_output_components[stream];
4401 LLVMBasicBlockRef bb;
4402 unsigned offset;
4403
4404 if (stream > 0 && !num_components)
4405 continue;
4406
4407 if (stream > 0 && !ctx->args->shader_info->so.num_outputs)
4408 continue;
4409
4410 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
4411 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
4412 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
4413
4414 offset = 0;
4415 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4416 unsigned output_usage_mask =
4417 ctx->args->shader_info->gs.output_usage_mask[i];
4418 unsigned output_stream =
4419 ctx->args->shader_info->gs.output_streams[i];
4420 int length = util_last_bit(output_usage_mask);
4421
4422 if (!(ctx->output_mask & (1ull << i)) ||
4423 output_stream != stream)
4424 continue;
4425
4426 for (unsigned j = 0; j < length; j++) {
4427 LLVMValueRef value, soffset;
4428
4429 if (!(output_usage_mask & (1 << j)))
4430 continue;
4431
4432 soffset = LLVMConstInt(ctx->ac.i32,
4433 offset *
4434 ctx->shader->info.gs.vertices_out * 16 * 4, false);
4435
4436 offset++;
4437
4438 value = ac_build_buffer_load(&ctx->ac,
4439 ctx->gsvs_ring[0],
4440 1, ctx->ac.i32_0,
4441 vtx_offset, soffset,
4442 0, ac_glc | ac_slc, true, false);
4443
4444 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4445 if (ac_get_type_size(type) == 2) {
4446 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
4447 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
4448 }
4449
4450 LLVMBuildStore(ctx->ac.builder,
4451 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4452 }
4453 }
4454
4455 if (!ctx->args->options->use_ngg_streamout &&
4456 ctx->args->shader_info->so.num_outputs)
4457 radv_emit_streamout(ctx, stream);
4458
4459 if (stream == 0) {
4460 handle_vs_outputs_post(ctx, false, true,
4461 &ctx->args->shader_info->vs.outinfo);
4462 }
4463
4464 LLVMBuildBr(ctx->ac.builder, end_bb);
4465 }
4466
4467 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
4468 }
4469
4470 void
4471 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
4472 struct nir_shader *geom_shader,
4473 struct radv_shader_binary **rbinary,
4474 const struct radv_shader_args *args)
4475 {
4476 struct radv_shader_context ctx = {0};
4477 ctx.args = args;
4478
4479 assert(args->is_gs_copy_shader);
4480
4481 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
4482 args->options->family, AC_FLOAT_MODE_DEFAULT, 64, 64);
4483 ctx.context = ctx.ac.context;
4484
4485 ctx.stage = MESA_SHADER_VERTEX;
4486 ctx.shader = geom_shader;
4487
4488 create_function(&ctx, MESA_SHADER_VERTEX, false);
4489
4490 ac_setup_rings(&ctx);
4491
4492 nir_foreach_variable(variable, &geom_shader->outputs) {
4493 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
4494 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
4495 variable, MESA_SHADER_VERTEX);
4496 }
4497
4498 ac_gs_copy_shader_emit(&ctx);
4499
4500 LLVMBuildRetVoid(ctx.ac.builder);
4501
4502 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4503
4504 ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
4505 MESA_SHADER_VERTEX, "GS Copy Shader", args->options);
4506 (*rbinary)->is_gs_copy_shader = true;
4507
4508 }