2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_llvm_build.h"
42 #include "ac_shader_abi.h"
43 #include "ac_shader_util.h"
44 #include "ac_exp_param.h"
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 struct radv_shader_context
{
49 struct ac_llvm_context ac
;
50 const struct radv_nir_compiler_options
*options
;
51 struct radv_shader_variant_info
*shader_info
;
52 struct ac_shader_abi abi
;
54 unsigned max_workgroup_size
;
55 LLVMContextRef context
;
56 LLVMValueRef main_function
;
58 LLVMValueRef descriptor_sets
[MAX_SETS
];
59 LLVMValueRef ring_offsets
;
61 LLVMValueRef vertex_buffers
;
62 LLVMValueRef rel_auto_id
;
63 LLVMValueRef vs_prim_id
;
64 LLVMValueRef es2gs_offset
;
67 LLVMValueRef merged_wave_info
;
68 LLVMValueRef tess_factor_offset
;
69 LLVMValueRef tes_rel_patch_id
;
75 * - bits 0..10: ordered_wave_id
76 * - bits 12..20: number of vertices in group
77 * - bits 22..30: number of primitives in group
79 LLVMValueRef gs_tg_info
;
80 LLVMValueRef gs2vs_offset
;
81 LLVMValueRef gs_wave_id
;
82 LLVMValueRef gs_vtx_offset
[6];
84 LLVMValueRef esgs_ring
;
85 LLVMValueRef gsvs_ring
[4];
86 LLVMValueRef hs_ring_tess_offchip
;
87 LLVMValueRef hs_ring_tess_factor
;
90 LLVMValueRef streamout_buffers
;
91 LLVMValueRef streamout_write_idx
;
92 LLVMValueRef streamout_config
;
93 LLVMValueRef streamout_offset
[4];
95 gl_shader_stage stage
;
97 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
98 uint64_t float16_shaded_mask
;
101 uint64_t output_mask
;
103 bool is_gs_copy_shader
;
104 LLVMValueRef gs_next_vertex
[4];
105 LLVMValueRef gs_curprim_verts
[4];
106 LLVMValueRef gs_generated_prims
[4];
107 LLVMValueRef gs_ngg_emit
;
108 LLVMValueRef gs_ngg_scratch
;
109 unsigned gs_max_out_vertices
;
110 unsigned gs_output_prim
;
112 unsigned tes_primitive_mode
;
114 uint32_t tcs_patch_outputs_read
;
115 uint64_t tcs_outputs_read
;
116 uint32_t tcs_vertices_per_patch
;
117 uint32_t tcs_num_inputs
;
118 uint32_t tcs_num_patches
;
119 uint32_t max_gsvs_emit_size
;
120 uint32_t gsvs_vertex_size
;
122 LLVMValueRef vertexptr
; /* GFX10 only */
125 struct radv_shader_output_values
{
126 LLVMValueRef values
[4];
132 enum radeon_llvm_calling_convention
{
133 RADEON_LLVM_AMDGPU_VS
= 87,
134 RADEON_LLVM_AMDGPU_GS
= 88,
135 RADEON_LLVM_AMDGPU_PS
= 89,
136 RADEON_LLVM_AMDGPU_CS
= 90,
137 RADEON_LLVM_AMDGPU_HS
= 93,
140 static inline struct radv_shader_context
*
141 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
143 struct radv_shader_context
*ctx
= NULL
;
144 return container_of(abi
, ctx
, abi
);
147 struct ac_build_if_state
149 struct radv_shader_context
*ctx
;
150 LLVMValueRef condition
;
151 LLVMBasicBlockRef entry_block
;
152 LLVMBasicBlockRef true_block
;
153 LLVMBasicBlockRef false_block
;
154 LLVMBasicBlockRef merge_block
;
157 static LLVMBasicBlockRef
158 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
160 LLVMBasicBlockRef current_block
;
161 LLVMBasicBlockRef next_block
;
162 LLVMBasicBlockRef new_block
;
164 /* get current basic block */
165 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
167 /* chqeck if there's another block after this one */
168 next_block
= LLVMGetNextBasicBlock(current_block
);
170 /* insert the new block before the next block */
171 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
174 /* append new block after current block */
175 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
176 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
182 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
183 struct radv_shader_context
*ctx
,
184 LLVMValueRef condition
)
186 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
188 memset(ifthen
, 0, sizeof *ifthen
);
190 ifthen
->condition
= condition
;
191 ifthen
->entry_block
= block
;
193 /* create endif/merge basic block for the phi functions */
194 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
196 /* create/insert true_block before merge_block */
198 LLVMInsertBasicBlockInContext(ctx
->context
,
202 /* successive code goes into the true block */
203 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
210 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
212 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
214 /* Insert branch to the merge block from current block */
215 LLVMBuildBr(builder
, ifthen
->merge_block
);
218 * Now patch in the various branch instructions.
221 /* Insert the conditional branch instruction at the end of entry_block */
222 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
223 if (ifthen
->false_block
) {
224 /* we have an else clause */
225 LLVMBuildCondBr(builder
, ifthen
->condition
,
226 ifthen
->true_block
, ifthen
->false_block
);
230 LLVMBuildCondBr(builder
, ifthen
->condition
,
231 ifthen
->true_block
, ifthen
->merge_block
);
234 /* Resume building code at end of the ifthen->merge_block */
235 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
239 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
241 switch (ctx
->stage
) {
242 case MESA_SHADER_TESS_CTRL
:
243 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
244 case MESA_SHADER_TESS_EVAL
:
245 return ctx
->tes_rel_patch_id
;
248 unreachable("Illegal stage");
253 get_tcs_num_patches(struct radv_shader_context
*ctx
)
255 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
256 unsigned num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
257 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
258 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
259 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
260 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
261 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
262 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
263 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
264 unsigned num_patches
;
265 unsigned hardware_lds_size
;
267 /* Ensure that we only need one wave per SIMD so we don't need to check
268 * resource usage. Also ensures that the number of tcs in and out
269 * vertices per threadgroup are at most 256.
271 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
272 /* Make sure that the data fits in LDS. This assumes the shaders only
273 * use LDS for the inputs and outputs.
275 hardware_lds_size
= 32768;
277 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
278 * threadgroup, even though there is more than 32 KiB LDS.
280 * Test: dEQP-VK.tessellation.shader_input_output.barrier
282 if (ctx
->options
->chip_class
>= GFX7
&& ctx
->options
->family
!= CHIP_STONEY
)
283 hardware_lds_size
= 65536;
285 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
286 /* Make sure the output data fits in the offchip buffer */
287 num_patches
= MIN2(num_patches
, (ctx
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
288 /* Not necessary for correctness, but improves performance. The
289 * specific value is taken from the proprietary driver.
291 num_patches
= MIN2(num_patches
, 40);
293 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
294 if (ctx
->options
->chip_class
== GFX6
) {
295 unsigned one_wave
= ctx
->options
->wave_size
/ MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
296 num_patches
= MIN2(num_patches
, one_wave
);
302 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
304 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
305 unsigned num_tcs_output_cp
;
306 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
307 unsigned input_vertex_size
, output_vertex_size
;
308 unsigned input_patch_size
, output_patch_size
;
309 unsigned pervertex_output_patch_size
;
310 unsigned output_patch0_offset
;
311 unsigned num_patches
;
314 num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
315 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
316 num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
318 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
319 output_vertex_size
= num_tcs_outputs
* 16;
321 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
323 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
324 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
326 num_patches
= ctx
->tcs_num_patches
;
327 output_patch0_offset
= input_patch_size
* num_patches
;
329 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
333 /* Tessellation shaders pass outputs to the next shader using LDS.
335 * LS outputs = TCS inputs
336 * TCS outputs = TES inputs
339 * - TCS inputs for patch 0
340 * - TCS inputs for patch 1
341 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
343 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
344 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
345 * - TCS outputs for patch 1
346 * - Per-patch TCS outputs for patch 1
347 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
348 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
351 * All three shaders VS(LS), TCS, TES share the same LDS space.
354 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
356 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
357 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
358 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
360 input_patch_size
/= 4;
361 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
365 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
367 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
368 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
369 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
370 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
371 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
372 output_patch_size
/= 4;
373 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
377 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
379 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
380 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
381 output_vertex_size
/= 4;
382 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
386 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
388 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
389 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
390 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
391 uint32_t output_patch0_offset
= input_patch_size
;
392 unsigned num_patches
= ctx
->tcs_num_patches
;
394 output_patch0_offset
*= num_patches
;
395 output_patch0_offset
/= 4;
396 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
400 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
402 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
403 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
404 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
405 uint32_t output_patch0_offset
= input_patch_size
;
407 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
408 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
409 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
410 unsigned num_patches
= ctx
->tcs_num_patches
;
412 output_patch0_offset
*= num_patches
;
413 output_patch0_offset
+= pervertex_output_patch_size
;
414 output_patch0_offset
/= 4;
415 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
419 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
421 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
422 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
424 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
428 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
430 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
431 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
432 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
434 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
439 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
441 LLVMValueRef patch0_patch_data_offset
=
442 get_tcs_out_patch0_patch_data_offset(ctx
);
443 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
444 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
446 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
447 patch0_patch_data_offset
);
452 LLVMTypeRef types
[MAX_ARGS
];
453 LLVMValueRef
*assign
[MAX_ARGS
];
456 uint8_t num_sgprs_used
;
457 uint8_t num_vgprs_used
;
460 enum ac_arg_regfile
{
466 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
467 LLVMValueRef
*param_ptr
)
469 assert(info
->count
< MAX_ARGS
);
471 info
->assign
[info
->count
] = param_ptr
;
472 info
->types
[info
->count
] = type
;
475 if (regfile
== ARG_SGPR
) {
476 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
479 assert(regfile
== ARG_VGPR
);
480 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
484 static void assign_arguments(LLVMValueRef main_function
,
485 struct arg_info
*info
)
488 for (i
= 0; i
< info
->count
; i
++) {
490 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
495 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
496 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
497 unsigned num_return_elems
,
498 struct arg_info
*args
,
499 unsigned max_workgroup_size
,
500 const struct radv_nir_compiler_options
*options
)
502 LLVMTypeRef main_function_type
, ret_type
;
503 LLVMBasicBlockRef main_function_body
;
505 if (num_return_elems
)
506 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
507 num_return_elems
, true);
509 ret_type
= LLVMVoidTypeInContext(ctx
);
511 /* Setup the function */
513 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
514 LLVMValueRef main_function
=
515 LLVMAddFunction(module
, "main", main_function_type
);
517 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
518 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
520 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
521 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
522 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
524 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
526 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
527 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
528 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
532 if (options
->address32_hi
) {
533 ac_llvm_add_target_dep_function_attr(main_function
,
534 "amdgpu-32bit-address-high-bits",
535 options
->address32_hi
);
538 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
540 if (options
->unsafe_math
) {
541 /* These were copied from some LLVM test. */
542 LLVMAddTargetDependentFunctionAttr(main_function
,
543 "less-precise-fpmad",
545 LLVMAddTargetDependentFunctionAttr(main_function
,
548 LLVMAddTargetDependentFunctionAttr(main_function
,
551 LLVMAddTargetDependentFunctionAttr(main_function
,
554 LLVMAddTargetDependentFunctionAttr(main_function
,
555 "no-signed-zeros-fp-math",
558 return main_function
;
563 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
,
566 ud_info
->sgpr_idx
= *sgpr_idx
;
567 ud_info
->num_sgprs
= num_sgprs
;
568 *sgpr_idx
+= num_sgprs
;
572 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
575 struct radv_userdata_info
*ud_info
=
576 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
579 set_loc(ud_info
, sgpr_idx
, num_sgprs
);
583 set_loc_shader_ptr(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
585 bool use_32bit_pointers
= idx
!= AC_UD_SCRATCH_RING_OFFSETS
;
587 set_loc_shader(ctx
, idx
, sgpr_idx
, use_32bit_pointers
? 1 : 2);
591 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
593 struct radv_userdata_locations
*locs
=
594 &ctx
->shader_info
->user_sgprs_locs
;
595 struct radv_userdata_info
*ud_info
= &locs
->descriptor_sets
[idx
];
598 set_loc(ud_info
, sgpr_idx
, 1);
600 locs
->descriptor_sets_enabled
|= 1 << idx
;
603 struct user_sgpr_info
{
604 bool need_ring_offsets
;
605 bool indirect_all_descriptor_sets
;
606 uint8_t remaining_sgprs
;
609 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
610 gl_shader_stage stage
)
613 case MESA_SHADER_VERTEX
:
614 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
615 (!ctx
->options
->key
.vs_common_out
.as_es
&& !ctx
->options
->key
.vs_common_out
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
618 case MESA_SHADER_TESS_EVAL
:
619 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.vs_common_out
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
622 case MESA_SHADER_GEOMETRY
:
623 case MESA_SHADER_TESS_CTRL
:
624 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
634 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
638 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
640 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
645 static void allocate_inline_push_consts(struct radv_shader_context
*ctx
,
646 struct user_sgpr_info
*user_sgpr_info
)
648 uint8_t remaining_sgprs
= user_sgpr_info
->remaining_sgprs
;
650 /* Only supported if shaders use push constants. */
651 if (ctx
->shader_info
->info
.min_push_constant_used
== UINT8_MAX
)
654 /* Only supported if shaders don't have indirect push constants. */
655 if (ctx
->shader_info
->info
.has_indirect_push_constants
)
658 /* Only supported for 32-bit push constants. */
659 if (!ctx
->shader_info
->info
.has_only_32bit_push_constants
)
662 uint8_t num_push_consts
=
663 (ctx
->shader_info
->info
.max_push_constant_used
-
664 ctx
->shader_info
->info
.min_push_constant_used
) / 4;
666 /* Check if the number of user SGPRs is large enough. */
667 if (num_push_consts
< remaining_sgprs
) {
668 ctx
->shader_info
->info
.num_inline_push_consts
= num_push_consts
;
670 ctx
->shader_info
->info
.num_inline_push_consts
= remaining_sgprs
;
673 /* Clamp to the maximum number of allowed inlined push constants. */
674 if (ctx
->shader_info
->info
.num_inline_push_consts
> AC_MAX_INLINE_PUSH_CONSTS
)
675 ctx
->shader_info
->info
.num_inline_push_consts
= AC_MAX_INLINE_PUSH_CONSTS
;
677 if (ctx
->shader_info
->info
.num_inline_push_consts
== num_push_consts
&&
678 !ctx
->shader_info
->info
.loads_dynamic_offsets
) {
679 /* Disable the default push constants path if all constants are
680 * inlined and if shaders don't use dynamic descriptors.
682 ctx
->shader_info
->info
.loads_push_constants
= false;
685 ctx
->shader_info
->info
.base_inline_push_consts
=
686 ctx
->shader_info
->info
.min_push_constant_used
/ 4;
689 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
690 gl_shader_stage stage
,
691 bool has_previous_stage
,
692 gl_shader_stage previous_stage
,
693 bool needs_view_index
,
694 struct user_sgpr_info
*user_sgpr_info
)
696 uint8_t user_sgpr_count
= 0;
698 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
700 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
701 if (stage
== MESA_SHADER_GEOMETRY
||
702 stage
== MESA_SHADER_VERTEX
||
703 stage
== MESA_SHADER_TESS_CTRL
||
704 stage
== MESA_SHADER_TESS_EVAL
||
705 ctx
->is_gs_copy_shader
)
706 user_sgpr_info
->need_ring_offsets
= true;
708 if (stage
== MESA_SHADER_FRAGMENT
&&
709 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
710 user_sgpr_info
->need_ring_offsets
= true;
712 /* 2 user sgprs will nearly always be allocated for scratch/rings */
713 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
714 user_sgpr_count
+= 2;
718 case MESA_SHADER_COMPUTE
:
719 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
720 user_sgpr_count
+= 3;
722 case MESA_SHADER_FRAGMENT
:
723 user_sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
725 case MESA_SHADER_VERTEX
:
726 if (!ctx
->is_gs_copy_shader
)
727 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
729 case MESA_SHADER_TESS_CTRL
:
730 if (has_previous_stage
) {
731 if (previous_stage
== MESA_SHADER_VERTEX
)
732 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
735 case MESA_SHADER_TESS_EVAL
:
737 case MESA_SHADER_GEOMETRY
:
738 if (has_previous_stage
) {
739 if (previous_stage
== MESA_SHADER_VERTEX
) {
740 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
748 if (needs_view_index
)
751 if (ctx
->shader_info
->info
.loads_push_constants
)
754 if (ctx
->streamout_buffers
)
757 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
&& stage
!= MESA_SHADER_COMPUTE
? 32 : 16;
758 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_count
;
759 uint32_t num_desc_set
=
760 util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
);
762 if (remaining_sgprs
< num_desc_set
) {
763 user_sgpr_info
->indirect_all_descriptor_sets
= true;
764 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- 1;
766 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- num_desc_set
;
769 allocate_inline_push_consts(ctx
, user_sgpr_info
);
773 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
774 const struct user_sgpr_info
*user_sgpr_info
,
775 struct arg_info
*args
,
776 LLVMValueRef
*desc_sets
)
778 LLVMTypeRef type
= ac_array_in_const32_addr_space(ctx
->ac
.i8
);
780 /* 1 for each descriptor set */
781 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
782 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
785 int i
= u_bit_scan(&mask
);
787 add_arg(args
, ARG_SGPR
, type
, &ctx
->descriptor_sets
[i
]);
790 add_arg(args
, ARG_SGPR
, ac_array_in_const32_addr_space(type
),
794 if (ctx
->shader_info
->info
.loads_push_constants
) {
795 /* 1 for push constants and dynamic descriptors */
796 add_arg(args
, ARG_SGPR
, type
, &ctx
->abi
.push_constants
);
799 for (unsigned i
= 0; i
< ctx
->shader_info
->info
.num_inline_push_consts
; i
++) {
800 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
,
801 &ctx
->abi
.inline_push_consts
[i
]);
803 ctx
->abi
.num_inline_push_consts
= ctx
->shader_info
->info
.num_inline_push_consts
;
804 ctx
->abi
.base_inline_push_consts
= ctx
->shader_info
->info
.base_inline_push_consts
;
806 if (ctx
->shader_info
->info
.so
.num_outputs
) {
807 add_arg(args
, ARG_SGPR
,
808 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
809 &ctx
->streamout_buffers
);
814 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
815 gl_shader_stage stage
,
816 bool has_previous_stage
,
817 gl_shader_stage previous_stage
,
818 struct arg_info
*args
)
820 if (!ctx
->is_gs_copy_shader
&&
821 (stage
== MESA_SHADER_VERTEX
||
822 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
823 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
824 add_arg(args
, ARG_SGPR
,
825 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
826 &ctx
->vertex_buffers
);
828 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
829 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
830 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
831 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
837 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
839 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
840 if (!ctx
->is_gs_copy_shader
) {
841 if (ctx
->options
->key
.vs_common_out
.as_ls
) {
842 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
843 if (ctx
->ac
.chip_class
>= GFX10
) {
844 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
845 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
847 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
848 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
851 if (ctx
->ac
.chip_class
>= GFX10
) {
852 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
853 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
854 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
855 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
857 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
858 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
859 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
862 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
863 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
864 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
871 declare_streamout_sgprs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
872 struct arg_info
*args
)
876 /* Streamout SGPRs. */
877 if (ctx
->shader_info
->info
.so
.num_outputs
) {
878 assert(stage
== MESA_SHADER_VERTEX
||
879 stage
== MESA_SHADER_TESS_EVAL
);
881 if (stage
!= MESA_SHADER_TESS_EVAL
) {
882 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_config
);
884 args
->assign
[args
->count
- 1] = &ctx
->streamout_config
;
885 args
->types
[args
->count
- 1] = ctx
->ac
.i32
;
888 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_write_idx
);
891 /* A streamout buffer offset is loaded if the stride is non-zero. */
892 for (i
= 0; i
< 4; i
++) {
893 if (!ctx
->shader_info
->info
.so
.strides
[i
])
896 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_offset
[i
]);
901 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
903 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
904 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
905 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
906 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
910 set_global_input_locs(struct radv_shader_context
*ctx
,
911 const struct user_sgpr_info
*user_sgpr_info
,
912 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
914 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
916 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
918 int i
= u_bit_scan(&mask
);
920 set_loc_desc(ctx
, i
, user_sgpr_idx
);
923 set_loc_shader_ptr(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
927 int i
= u_bit_scan(&mask
);
929 ctx
->descriptor_sets
[i
] =
930 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
931 LLVMConstInt(ctx
->ac
.i32
, i
, false));
935 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
938 if (ctx
->shader_info
->info
.loads_push_constants
) {
939 set_loc_shader_ptr(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
);
942 if (ctx
->shader_info
->info
.num_inline_push_consts
) {
943 set_loc_shader(ctx
, AC_UD_INLINE_PUSH_CONSTANTS
, user_sgpr_idx
,
944 ctx
->shader_info
->info
.num_inline_push_consts
);
947 if (ctx
->streamout_buffers
) {
948 set_loc_shader_ptr(ctx
, AC_UD_STREAMOUT_BUFFERS
,
954 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
955 gl_shader_stage stage
, bool has_previous_stage
,
956 gl_shader_stage previous_stage
,
957 uint8_t *user_sgpr_idx
)
959 if (!ctx
->is_gs_copy_shader
&&
960 (stage
== MESA_SHADER_VERTEX
||
961 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
962 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
963 set_loc_shader_ptr(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
968 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
971 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
972 user_sgpr_idx
, vs_num
);
976 static void set_llvm_calling_convention(LLVMValueRef func
,
977 gl_shader_stage stage
)
979 enum radeon_llvm_calling_convention calling_conv
;
982 case MESA_SHADER_VERTEX
:
983 case MESA_SHADER_TESS_EVAL
:
984 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
986 case MESA_SHADER_GEOMETRY
:
987 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
989 case MESA_SHADER_TESS_CTRL
:
990 calling_conv
= RADEON_LLVM_AMDGPU_HS
;
992 case MESA_SHADER_FRAGMENT
:
993 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
995 case MESA_SHADER_COMPUTE
:
996 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
999 unreachable("Unhandle shader type");
1002 LLVMSetFunctionCallConv(func
, calling_conv
);
1005 /* Returns whether the stage is a stage that can be directly before the GS */
1006 static bool is_pre_gs_stage(gl_shader_stage stage
)
1008 return stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
;
1011 static void create_function(struct radv_shader_context
*ctx
,
1012 gl_shader_stage stage
,
1013 bool has_previous_stage
,
1014 gl_shader_stage previous_stage
)
1016 uint8_t user_sgpr_idx
;
1017 struct user_sgpr_info user_sgpr_info
;
1018 struct arg_info args
= {};
1019 LLVMValueRef desc_sets
;
1020 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
1022 if (ctx
->ac
.chip_class
>= GFX10
) {
1023 if (is_pre_gs_stage(stage
) && ctx
->options
->key
.vs_common_out
.as_ngg
) {
1024 /* On GFX10, VS is merged into GS for NGG. */
1025 previous_stage
= stage
;
1026 stage
= MESA_SHADER_GEOMETRY
;
1027 has_previous_stage
= true;
1031 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
1032 previous_stage
, needs_view_index
, &user_sgpr_info
);
1034 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
1035 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
1036 &ctx
->ring_offsets
);
1040 case MESA_SHADER_COMPUTE
:
1041 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1044 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1045 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
1046 &ctx
->abi
.num_work_groups
);
1049 for (int i
= 0; i
< 3; i
++) {
1050 ctx
->abi
.workgroup_ids
[i
] = NULL
;
1051 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
1052 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1053 &ctx
->abi
.workgroup_ids
[i
]);
1057 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
1058 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
1059 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
1060 &ctx
->abi
.local_invocation_ids
);
1062 case MESA_SHADER_VERTEX
:
1063 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1066 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
1067 previous_stage
, &args
);
1069 if (needs_view_index
)
1070 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1071 &ctx
->abi
.view_index
);
1072 if (ctx
->options
->key
.vs_common_out
.as_es
) {
1073 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1074 &ctx
->es2gs_offset
);
1075 } else if (ctx
->options
->key
.vs_common_out
.as_ls
) {
1076 /* no extra parameters */
1078 declare_streamout_sgprs(ctx
, stage
, &args
);
1081 declare_vs_input_vgprs(ctx
, &args
);
1083 case MESA_SHADER_TESS_CTRL
:
1084 if (has_previous_stage
) {
1085 // First 6 system regs
1086 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1087 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1088 &ctx
->merged_wave_info
);
1089 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1090 &ctx
->tess_factor_offset
);
1092 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1093 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1094 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1096 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1099 declare_vs_specific_input_sgprs(ctx
, stage
,
1101 previous_stage
, &args
);
1103 if (needs_view_index
)
1104 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1105 &ctx
->abi
.view_index
);
1107 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1108 &ctx
->abi
.tcs_patch_id
);
1109 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1110 &ctx
->abi
.tcs_rel_ids
);
1112 declare_vs_input_vgprs(ctx
, &args
);
1114 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1117 if (needs_view_index
)
1118 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1119 &ctx
->abi
.view_index
);
1121 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1122 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1123 &ctx
->tess_factor_offset
);
1124 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1125 &ctx
->abi
.tcs_patch_id
);
1126 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1127 &ctx
->abi
.tcs_rel_ids
);
1130 case MESA_SHADER_TESS_EVAL
:
1131 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1134 if (needs_view_index
)
1135 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1136 &ctx
->abi
.view_index
);
1138 if (ctx
->options
->key
.vs_common_out
.as_es
) {
1139 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1140 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1141 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1142 &ctx
->es2gs_offset
);
1144 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1145 declare_streamout_sgprs(ctx
, stage
, &args
);
1146 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1148 declare_tes_input_vgprs(ctx
, &args
);
1150 case MESA_SHADER_GEOMETRY
:
1151 if (has_previous_stage
) {
1152 // First 6 system regs
1153 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1154 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1157 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1158 &ctx
->gs2vs_offset
);
1161 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1162 &ctx
->merged_wave_info
);
1163 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1165 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1166 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1167 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1169 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1172 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
1173 declare_vs_specific_input_sgprs(ctx
, stage
,
1179 if (needs_view_index
)
1180 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1181 &ctx
->abi
.view_index
);
1183 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1184 &ctx
->gs_vtx_offset
[0]);
1185 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1186 &ctx
->gs_vtx_offset
[2]);
1187 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1188 &ctx
->abi
.gs_prim_id
);
1189 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1190 &ctx
->abi
.gs_invocation_id
);
1191 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1192 &ctx
->gs_vtx_offset
[4]);
1194 if (previous_stage
== MESA_SHADER_VERTEX
) {
1195 declare_vs_input_vgprs(ctx
, &args
);
1197 declare_tes_input_vgprs(ctx
, &args
);
1200 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1203 if (needs_view_index
)
1204 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1205 &ctx
->abi
.view_index
);
1207 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1208 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1209 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1210 &ctx
->gs_vtx_offset
[0]);
1211 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1212 &ctx
->gs_vtx_offset
[1]);
1213 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1214 &ctx
->abi
.gs_prim_id
);
1215 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1216 &ctx
->gs_vtx_offset
[2]);
1217 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1218 &ctx
->gs_vtx_offset
[3]);
1219 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1220 &ctx
->gs_vtx_offset
[4]);
1221 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1222 &ctx
->gs_vtx_offset
[5]);
1223 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1224 &ctx
->abi
.gs_invocation_id
);
1227 case MESA_SHADER_FRAGMENT
:
1228 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1231 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1232 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.persp_sample
);
1233 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.persp_center
);
1234 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.persp_centroid
);
1235 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1236 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.linear_sample
);
1237 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.linear_center
);
1238 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.linear_centroid
);
1239 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1240 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1241 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1242 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1243 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1244 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1245 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1246 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1247 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1250 unreachable("Shader stage not implemented");
1253 ctx
->main_function
= create_llvm_function(
1254 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1255 ctx
->max_workgroup_size
, ctx
->options
);
1256 set_llvm_calling_convention(ctx
->main_function
, stage
);
1259 ctx
->shader_info
->num_input_vgprs
= 0;
1260 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1262 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1264 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1265 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1267 assign_arguments(ctx
->main_function
, &args
);
1271 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1272 set_loc_shader_ptr(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1274 if (ctx
->options
->supports_spill
) {
1275 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1276 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
1277 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1278 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1279 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1283 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1284 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1285 if (has_previous_stage
)
1288 set_global_input_locs(ctx
, &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1291 case MESA_SHADER_COMPUTE
:
1292 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1293 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1297 case MESA_SHADER_VERTEX
:
1298 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1299 previous_stage
, &user_sgpr_idx
);
1300 if (ctx
->abi
.view_index
)
1301 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1303 case MESA_SHADER_TESS_CTRL
:
1304 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1305 previous_stage
, &user_sgpr_idx
);
1306 if (ctx
->abi
.view_index
)
1307 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1309 case MESA_SHADER_TESS_EVAL
:
1310 if (ctx
->abi
.view_index
)
1311 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1313 case MESA_SHADER_GEOMETRY
:
1314 if (has_previous_stage
) {
1315 if (previous_stage
== MESA_SHADER_VERTEX
)
1316 set_vs_specific_input_locs(ctx
, stage
,
1321 if (ctx
->abi
.view_index
)
1322 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1324 case MESA_SHADER_FRAGMENT
:
1327 unreachable("Shader stage not implemented");
1330 if (stage
== MESA_SHADER_TESS_CTRL
||
1331 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs_common_out
.as_ls
) ||
1332 /* GFX9 has the ESGS ring buffer in LDS. */
1333 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1334 ac_declare_lds_as_pointer(&ctx
->ac
);
1337 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1342 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1343 unsigned desc_set
, unsigned binding
)
1345 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1346 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1347 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
1348 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1349 unsigned base_offset
= layout
->binding
[binding
].offset
;
1350 LLVMValueRef offset
, stride
;
1352 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1353 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1354 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1355 layout
->binding
[binding
].dynamic_offset_offset
;
1356 desc_ptr
= ctx
->abi
.push_constants
;
1357 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1358 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1360 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1362 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
1364 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1365 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
1368 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
1369 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1370 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1372 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1373 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1374 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1375 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1376 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1378 if (ctx
->ac
.chip_class
>= GFX10
) {
1379 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1380 S_008F0C_OOB_SELECT(3) |
1381 S_008F0C_RESOURCE_LEVEL(1);
1383 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1384 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1387 LLVMValueRef desc_components
[4] = {
1388 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
1389 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
), false),
1390 /* High limit to support variable sizes. */
1391 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
1392 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
1395 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
1402 /* The offchip buffer layout for TCS->TES is
1404 * - attribute 0 of patch 0 vertex 0
1405 * - attribute 0 of patch 0 vertex 1
1406 * - attribute 0 of patch 0 vertex 2
1408 * - attribute 0 of patch 1 vertex 0
1409 * - attribute 0 of patch 1 vertex 1
1411 * - attribute 1 of patch 0 vertex 0
1412 * - attribute 1 of patch 0 vertex 1
1414 * - per patch attribute 0 of patch 0
1415 * - per patch attribute 0 of patch 1
1418 * Note that every attribute has 4 components.
1420 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1422 uint32_t num_patches
= ctx
->tcs_num_patches
;
1423 uint32_t num_tcs_outputs
;
1424 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1425 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
1427 num_tcs_outputs
= ctx
->options
->key
.tes
.tcs_num_outputs
;
1429 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1430 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
1432 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1435 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1436 LLVMValueRef vertex_index
)
1438 LLVMValueRef param_stride
;
1440 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
* ctx
->tcs_num_patches
, false);
1442 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1443 return param_stride
;
1446 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1447 LLVMValueRef vertex_index
,
1448 LLVMValueRef param_index
)
1450 LLVMValueRef base_addr
;
1451 LLVMValueRef param_stride
, constant16
;
1452 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1453 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
1454 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1455 param_stride
= calc_param_stride(ctx
, vertex_index
);
1457 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
1458 vertices_per_patch
, vertex_index
);
1460 base_addr
= rel_patch_id
;
1463 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1464 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1465 param_stride
, ""), "");
1467 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1469 if (!vertex_index
) {
1470 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1472 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1473 patch_data_offset
, "");
1478 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1480 unsigned const_index
,
1482 LLVMValueRef vertex_index
,
1483 LLVMValueRef indir_index
)
1485 LLVMValueRef param_index
;
1488 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1491 if (const_index
&& !is_compact
)
1492 param
+= const_index
;
1493 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1495 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1499 get_dw_address(struct radv_shader_context
*ctx
,
1500 LLVMValueRef dw_addr
,
1502 unsigned const_index
,
1503 bool compact_const_index
,
1504 LLVMValueRef vertex_index
,
1505 LLVMValueRef stride
,
1506 LLVMValueRef indir_index
)
1511 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1512 LLVMBuildMul(ctx
->ac
.builder
,
1518 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1519 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1520 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1521 else if (const_index
&& !compact_const_index
)
1522 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1523 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1525 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1526 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1528 if (const_index
&& compact_const_index
)
1529 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1530 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1535 load_tcs_varyings(struct ac_shader_abi
*abi
,
1537 LLVMValueRef vertex_index
,
1538 LLVMValueRef indir_index
,
1539 unsigned const_index
,
1541 unsigned driver_location
,
1543 unsigned num_components
,
1548 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1549 LLVMValueRef dw_addr
, stride
;
1550 LLVMValueRef value
[4], result
;
1551 unsigned param
= shader_io_get_unique_index(location
);
1554 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1555 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1556 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1559 stride
= get_tcs_out_vertex_stride(ctx
);
1560 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1562 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1567 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1570 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1571 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1572 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1575 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1580 store_tcs_output(struct ac_shader_abi
*abi
,
1581 const nir_variable
*var
,
1582 LLVMValueRef vertex_index
,
1583 LLVMValueRef param_index
,
1584 unsigned const_index
,
1588 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1589 const unsigned location
= var
->data
.location
;
1590 unsigned component
= var
->data
.location_frac
;
1591 const bool is_patch
= var
->data
.patch
;
1592 const bool is_compact
= var
->data
.compact
;
1593 LLVMValueRef dw_addr
;
1594 LLVMValueRef stride
= NULL
;
1595 LLVMValueRef buf_addr
= NULL
;
1597 bool store_lds
= true;
1600 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1603 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
1607 param
= shader_io_get_unique_index(location
);
1608 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1609 const_index
+= component
;
1612 if (const_index
>= 4) {
1619 stride
= get_tcs_out_vertex_stride(ctx
);
1620 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1622 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1625 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1627 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1628 vertex_index
, param_index
);
1630 bool is_tess_factor
= false;
1631 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1632 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1633 is_tess_factor
= true;
1635 unsigned base
= is_compact
? const_index
: 0;
1636 for (unsigned chan
= 0; chan
< 8; chan
++) {
1637 if (!(writemask
& (1 << chan
)))
1639 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1640 value
= ac_to_integer(&ctx
->ac
, value
);
1641 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
1643 if (store_lds
|| is_tess_factor
) {
1644 LLVMValueRef dw_addr_chan
=
1645 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1646 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1647 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1650 if (!is_tess_factor
&& writemask
!= 0xF)
1651 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1652 buf_addr
, ctx
->oc_lds
,
1653 4 * (base
+ chan
), ac_glc
, false);
1656 if (writemask
== 0xF) {
1657 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1658 buf_addr
, ctx
->oc_lds
,
1659 (base
* 4), ac_glc
, false);
1664 load_tes_input(struct ac_shader_abi
*abi
,
1666 LLVMValueRef vertex_index
,
1667 LLVMValueRef param_index
,
1668 unsigned const_index
,
1670 unsigned driver_location
,
1672 unsigned num_components
,
1677 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1678 LLVMValueRef buf_addr
;
1679 LLVMValueRef result
;
1680 unsigned param
= shader_io_get_unique_index(location
);
1682 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1683 const_index
+= component
;
1685 if (const_index
>= 4) {
1691 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1692 is_compact
, vertex_index
, param_index
);
1694 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1695 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1697 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1698 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
1699 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1704 load_gs_input(struct ac_shader_abi
*abi
,
1706 unsigned driver_location
,
1708 unsigned num_components
,
1709 unsigned vertex_index
,
1710 unsigned const_index
,
1713 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1714 LLVMValueRef vtx_offset
;
1715 unsigned param
, vtx_offset_param
;
1716 LLVMValueRef value
[4], result
;
1718 vtx_offset_param
= vertex_index
;
1719 assert(vtx_offset_param
< 6);
1720 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1721 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1723 param
= shader_io_get_unique_index(location
);
1725 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1726 if (ctx
->ac
.chip_class
>= GFX9
) {
1727 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1728 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1729 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1730 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1732 LLVMValueRef soffset
=
1733 LLVMConstInt(ctx
->ac
.i32
,
1734 (param
* 4 + i
+ const_index
) * 256,
1737 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1740 vtx_offset
, soffset
,
1741 0, ac_glc
, true, false);
1744 if (ac_get_type_size(type
) == 2) {
1745 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
1746 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
1748 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
1750 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1751 result
= ac_to_integer(&ctx
->ac
, result
);
1756 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1758 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1759 ac_build_kill_if_false(&ctx
->ac
, visible
);
1763 radv_get_sample_pos_offset(uint32_t num_samples
)
1765 uint32_t sample_pos_offset
= 0;
1767 switch (num_samples
) {
1769 sample_pos_offset
= 1;
1772 sample_pos_offset
= 3;
1775 sample_pos_offset
= 7;
1780 return sample_pos_offset
;
1783 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1784 LLVMValueRef sample_id
)
1786 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1788 LLVMValueRef result
;
1789 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
1790 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
1792 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1793 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1795 uint32_t sample_pos_offset
=
1796 radv_get_sample_pos_offset(ctx
->options
->key
.fs
.num_samples
);
1799 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
1800 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
1801 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1807 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1809 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1810 uint8_t log2_ps_iter_samples
;
1812 if (ctx
->shader_info
->info
.ps
.force_persample
) {
1813 log2_ps_iter_samples
=
1814 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
1816 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
1819 /* The bit pattern matches that used by fixed function fragment
1821 static const uint16_t ps_iter_masks
[] = {
1822 0xffff, /* not used */
1828 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1830 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1832 LLVMValueRef result
, sample_id
;
1833 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
1834 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1835 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
1840 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
1842 LLVMValueRef
*addrs
);
1845 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1847 LLVMValueRef gs_next_vertex
;
1848 LLVMValueRef can_emit
;
1849 unsigned offset
= 0;
1850 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1852 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1853 gfx10_ngg_gs_emit_vertex(ctx
, stream
, addrs
);
1857 /* Write vertex attribute values to GSVS ring */
1858 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1859 ctx
->gs_next_vertex
[stream
],
1862 /* If this thread has already emitted the declared maximum number of
1863 * vertices, kill it: excessive vertex emissions are not supposed to
1864 * have any effect, and GS threads have no externally observable
1865 * effects other than emitting vertices.
1867 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1868 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
1869 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1871 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1872 unsigned output_usage_mask
=
1873 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
1874 uint8_t output_stream
=
1875 ctx
->shader_info
->info
.gs
.output_streams
[i
];
1876 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1877 int length
= util_last_bit(output_usage_mask
);
1879 if (!(ctx
->output_mask
& (1ull << i
)) ||
1880 output_stream
!= stream
)
1883 for (unsigned j
= 0; j
< length
; j
++) {
1884 if (!(output_usage_mask
& (1 << j
)))
1887 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1889 LLVMValueRef voffset
=
1890 LLVMConstInt(ctx
->ac
.i32
, offset
*
1891 ctx
->gs_max_out_vertices
, false);
1895 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1896 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1898 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1899 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1901 ac_build_buffer_store_dword(&ctx
->ac
,
1902 ctx
->gsvs_ring
[stream
],
1904 voffset
, ctx
->gs2vs_offset
, 0,
1905 ac_glc
| ac_slc
, true);
1909 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1911 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1913 ac_build_sendmsg(&ctx
->ac
,
1914 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1919 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1921 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1923 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1924 LLVMBuildStore(ctx
->ac
.builder
, ctx
->ac
.i32_0
, ctx
->gs_curprim_verts
[stream
]);
1928 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1932 load_tess_coord(struct ac_shader_abi
*abi
)
1934 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1936 LLVMValueRef coord
[4] = {
1943 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
1944 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1945 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1947 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1951 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1953 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1954 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
1958 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1960 return abi
->base_vertex
;
1963 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1964 LLVMValueRef buffer_ptr
, bool write
)
1966 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1967 LLVMValueRef result
;
1969 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1971 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1972 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1977 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1979 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1980 LLVMValueRef result
;
1982 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
1983 /* Do not load the descriptor for inlined uniform blocks. */
1987 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1989 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1990 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1995 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1996 unsigned descriptor_set
,
1997 unsigned base_index
,
1998 unsigned constant_index
,
2000 enum ac_descriptor_type desc_type
,
2001 bool image
, bool write
,
2004 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2005 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
2006 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
2007 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
2008 unsigned offset
= binding
->offset
;
2009 unsigned stride
= binding
->size
;
2011 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2014 assert(base_index
< layout
->binding_count
);
2016 switch (desc_type
) {
2018 type
= ctx
->ac
.v8i32
;
2022 type
= ctx
->ac
.v8i32
;
2026 case AC_DESC_SAMPLER
:
2027 type
= ctx
->ac
.v4i32
;
2028 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
2029 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
2034 case AC_DESC_BUFFER
:
2035 type
= ctx
->ac
.v4i32
;
2038 case AC_DESC_PLANE_0
:
2039 case AC_DESC_PLANE_1
:
2040 case AC_DESC_PLANE_2
:
2041 type
= ctx
->ac
.v8i32
;
2043 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
2046 unreachable("invalid desc_type\n");
2049 offset
+= constant_index
* stride
;
2051 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
2052 (!index
|| binding
->immutable_samplers_equal
)) {
2053 if (binding
->immutable_samplers_equal
)
2056 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
2058 LLVMValueRef constants
[] = {
2059 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
2060 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
2061 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
2062 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
2064 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
2067 assert(stride
% type_size
== 0);
2069 LLVMValueRef adjusted_index
= index
;
2070 if (!adjusted_index
)
2071 adjusted_index
= ctx
->ac
.i32_0
;
2073 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
2075 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
2076 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
2077 list
= LLVMBuildPointerCast(builder
, list
,
2078 ac_array_in_const32_addr_space(type
), "");
2080 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
2082 /* 3 plane formats always have same size and format for plane 1 & 2, so
2083 * use the tail from plane 1 so that we can store only the first 16 bytes
2084 * of the last plane. */
2085 if (desc_type
== AC_DESC_PLANE_2
) {
2086 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
2088 LLVMValueRef components
[8];
2089 for (unsigned i
= 0; i
< 4; ++i
)
2090 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
2092 for (unsigned i
= 4; i
< 8; ++i
)
2093 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
2094 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
2100 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
2101 * so we may need to fix it up. */
2103 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
2104 unsigned adjustment
,
2107 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
2110 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
2112 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2114 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
2115 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2117 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
2119 /* For the integer-like cases, do a natural sign extension.
2121 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2122 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2125 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
2126 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
2127 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
2128 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
2130 /* Convert back to the right type. */
2131 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
2133 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
2134 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2135 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
2136 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
2137 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
2138 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2141 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2145 get_num_channels_from_data_format(unsigned data_format
)
2147 switch (data_format
) {
2148 case V_008F0C_BUF_DATA_FORMAT_8
:
2149 case V_008F0C_BUF_DATA_FORMAT_16
:
2150 case V_008F0C_BUF_DATA_FORMAT_32
:
2152 case V_008F0C_BUF_DATA_FORMAT_8_8
:
2153 case V_008F0C_BUF_DATA_FORMAT_16_16
:
2154 case V_008F0C_BUF_DATA_FORMAT_32_32
:
2156 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
2157 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
2158 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
2160 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
2161 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
2162 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
2163 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
2164 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
2174 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
2176 unsigned num_channels
,
2179 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
2180 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
2181 LLVMValueRef chan
[4];
2183 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
2184 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
2186 if (num_channels
== 4 && num_channels
== vec_size
)
2189 num_channels
= MIN2(num_channels
, vec_size
);
2191 for (unsigned i
= 0; i
< num_channels
; i
++)
2192 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
2195 assert(num_channels
== 1);
2200 for (unsigned i
= num_channels
; i
< 4; i
++) {
2201 chan
[i
] = i
== 3 ? one
: zero
;
2202 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
2205 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
2209 handle_vs_input_decl(struct radv_shader_context
*ctx
,
2210 struct nir_variable
*variable
)
2212 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
2213 LLVMValueRef t_offset
;
2214 LLVMValueRef t_list
;
2216 LLVMValueRef buffer_index
;
2217 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
2218 uint8_t input_usage_mask
=
2219 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
2220 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
2222 variable
->data
.driver_location
= variable
->data
.location
* 4;
2224 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
2225 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
2226 LLVMValueRef output
[4];
2227 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
2228 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
2229 unsigned data_format
= attrib_format
& 0x0f;
2230 unsigned num_format
= (attrib_format
>> 4) & 0x07;
2231 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
2232 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
2234 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
2235 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
2238 buffer_index
= ctx
->abi
.instance_id
;
2241 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
2242 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
2245 buffer_index
= ctx
->ac
.i32_0
;
2248 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.start_instance
, buffer_index
, "");
2250 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
2251 ctx
->abi
.base_vertex
, "");
2253 /* Adjust the number of channels to load based on the vertex
2256 unsigned num_format_channels
= get_num_channels_from_data_format(data_format
);
2257 unsigned num_channels
= MIN2(num_input_channels
, num_format_channels
);
2258 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
2259 unsigned attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
2260 unsigned attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
2262 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2263 /* Always load, at least, 3 channels for formats that
2264 * need to be shuffled because X<->Z.
2266 num_channels
= MAX2(num_channels
, 3);
2269 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
2270 LLVMValueRef buffer_offset
=
2271 LLVMConstInt(ctx
->ac
.i32
,
2272 attrib_offset
/ attrib_stride
, false);
2274 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
2278 attrib_offset
= attrib_offset
% attrib_stride
;
2281 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
2282 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
2284 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
2286 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
2287 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
2289 data_format
, num_format
, 0, true);
2291 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2293 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
2294 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
2295 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
2296 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
2298 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
2301 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
2304 for (unsigned chan
= 0; chan
< 4; chan
++) {
2305 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2306 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
2307 if (type
== GLSL_TYPE_FLOAT16
) {
2308 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
2309 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
2313 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
2314 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
2316 for (unsigned chan
= 0; chan
< 4; chan
++) {
2317 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
2318 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
2319 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
2321 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
2327 handle_vs_inputs(struct radv_shader_context
*ctx
,
2328 struct nir_shader
*nir
) {
2329 nir_foreach_variable(variable
, &nir
->inputs
)
2330 handle_vs_input_decl(ctx
, variable
);
2334 prepare_interp_optimize(struct radv_shader_context
*ctx
,
2335 struct nir_shader
*nir
)
2337 bool uses_center
= false;
2338 bool uses_centroid
= false;
2339 nir_foreach_variable(variable
, &nir
->inputs
) {
2340 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
2341 variable
->data
.sample
)
2344 if (variable
->data
.centroid
)
2345 uses_centroid
= true;
2350 if (uses_center
&& uses_centroid
) {
2351 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
2352 ctx
->abi
.persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->abi
.persp_center
, ctx
->abi
.persp_centroid
, "");
2353 ctx
->abi
.linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->abi
.linear_center
, ctx
->abi
.linear_centroid
, "");
2358 scan_shader_output_decl(struct radv_shader_context
*ctx
,
2359 struct nir_variable
*variable
,
2360 struct nir_shader
*shader
,
2361 gl_shader_stage stage
)
2363 int idx
= variable
->data
.location
+ variable
->data
.index
;
2364 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2365 uint64_t mask_attribs
;
2367 variable
->data
.driver_location
= idx
* 4;
2369 /* tess ctrl has it's own load/store paths for outputs */
2370 if (stage
== MESA_SHADER_TESS_CTRL
)
2373 if (variable
->data
.compact
) {
2374 unsigned component_count
= variable
->data
.location_frac
+
2375 glsl_get_length(variable
->type
);
2376 attrib_count
= (component_count
+ 3) / 4;
2379 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2380 if (stage
== MESA_SHADER_VERTEX
||
2381 stage
== MESA_SHADER_TESS_EVAL
||
2382 stage
== MESA_SHADER_GEOMETRY
) {
2383 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2384 if (stage
== MESA_SHADER_VERTEX
) {
2385 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2386 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2387 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2389 if (stage
== MESA_SHADER_TESS_EVAL
) {
2390 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2391 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2392 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2394 if (stage
== MESA_SHADER_GEOMETRY
) {
2395 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2396 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2397 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2402 ctx
->output_mask
|= mask_attribs
;
2406 /* Initialize arguments for the shader export intrinsic */
2408 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2409 LLVMValueRef
*values
,
2410 unsigned enabled_channels
,
2412 struct ac_export_args
*args
)
2414 /* Specify the channels that are enabled. */
2415 args
->enabled_channels
= enabled_channels
;
2417 /* Specify whether the EXEC mask represents the valid mask */
2418 args
->valid_mask
= 0;
2420 /* Specify whether this is the last export */
2423 /* Specify the target we are exporting */
2424 args
->target
= target
;
2426 args
->compr
= false;
2427 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2428 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2429 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2430 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2435 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
2436 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2437 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2438 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2439 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2440 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2443 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2444 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2445 unsigned bits
, bool hi
) = NULL
;
2447 switch(col_format
) {
2448 case V_028714_SPI_SHADER_ZERO
:
2449 args
->enabled_channels
= 0; /* writemask */
2450 args
->target
= V_008DFC_SQ_EXP_NULL
;
2453 case V_028714_SPI_SHADER_32_R
:
2454 args
->enabled_channels
= 1;
2455 args
->out
[0] = values
[0];
2458 case V_028714_SPI_SHADER_32_GR
:
2459 args
->enabled_channels
= 0x3;
2460 args
->out
[0] = values
[0];
2461 args
->out
[1] = values
[1];
2464 case V_028714_SPI_SHADER_32_AR
:
2465 if (ctx
->ac
.chip_class
>= GFX10
) {
2466 args
->enabled_channels
= 0x3;
2467 args
->out
[0] = values
[0];
2468 args
->out
[1] = values
[3];
2470 args
->enabled_channels
= 0x9;
2471 args
->out
[0] = values
[0];
2472 args
->out
[3] = values
[3];
2476 case V_028714_SPI_SHADER_FP16_ABGR
:
2477 args
->enabled_channels
= 0x5;
2478 packf
= ac_build_cvt_pkrtz_f16
;
2480 for (unsigned chan
= 0; chan
< 4; chan
++)
2481 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
2487 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2488 args
->enabled_channels
= 0x5;
2489 packf
= ac_build_cvt_pknorm_u16
;
2492 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2493 args
->enabled_channels
= 0x5;
2494 packf
= ac_build_cvt_pknorm_i16
;
2497 case V_028714_SPI_SHADER_UINT16_ABGR
:
2498 args
->enabled_channels
= 0x5;
2499 packi
= ac_build_cvt_pk_u16
;
2501 for (unsigned chan
= 0; chan
< 4; chan
++)
2502 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
2503 ac_to_integer(&ctx
->ac
, values
[chan
]),
2508 case V_028714_SPI_SHADER_SINT16_ABGR
:
2509 args
->enabled_channels
= 0x5;
2510 packi
= ac_build_cvt_pk_i16
;
2512 for (unsigned chan
= 0; chan
< 4; chan
++)
2513 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
2514 ac_to_integer(&ctx
->ac
, values
[chan
]),
2520 case V_028714_SPI_SHADER_32_ABGR
:
2521 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2525 /* Pack f16 or norm_i16/u16. */
2527 for (chan
= 0; chan
< 2; chan
++) {
2528 LLVMValueRef pack_args
[2] = {
2530 values
[2 * chan
+ 1]
2532 LLVMValueRef packed
;
2534 packed
= packf(&ctx
->ac
, pack_args
);
2535 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2537 args
->compr
= 1; /* COMPR flag */
2542 for (chan
= 0; chan
< 2; chan
++) {
2543 LLVMValueRef pack_args
[2] = {
2544 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2545 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2547 LLVMValueRef packed
;
2549 packed
= packi(&ctx
->ac
, pack_args
,
2550 is_int8
? 8 : is_int10
? 10 : 16,
2552 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2554 args
->compr
= 1; /* COMPR flag */
2560 for (unsigned chan
= 0; chan
< 4; chan
++) {
2561 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
2562 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
2565 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2567 for (unsigned i
= 0; i
< 4; ++i
)
2568 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2572 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2573 LLVMValueRef
*values
, unsigned enabled_channels
)
2575 struct ac_export_args args
;
2577 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2578 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2579 ac_build_export(&ctx
->ac
, &args
);
2583 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2585 LLVMValueRef output
= ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2586 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2590 radv_emit_stream_output(struct radv_shader_context
*ctx
,
2591 LLVMValueRef
const *so_buffers
,
2592 LLVMValueRef
const *so_write_offsets
,
2593 const struct radv_stream_output
*output
,
2594 struct radv_shader_output_values
*shader_out
)
2596 unsigned num_comps
= util_bitcount(output
->component_mask
);
2597 unsigned buf
= output
->buffer
;
2598 unsigned offset
= output
->offset
;
2600 LLVMValueRef out
[4];
2602 assert(num_comps
&& num_comps
<= 4);
2603 if (!num_comps
|| num_comps
> 4)
2606 /* Get the first component. */
2607 start
= ffs(output
->component_mask
) - 1;
2609 /* Load the output as int. */
2610 for (int i
= 0; i
< num_comps
; i
++) {
2611 out
[i
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ i
]);
2614 /* Pack the output. */
2615 LLVMValueRef vdata
= NULL
;
2617 switch (num_comps
) {
2618 case 1: /* as i32 */
2621 case 2: /* as v2i32 */
2622 case 3: /* as v4i32 (aligned to 4) */
2623 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
2625 case 4: /* as v4i32 */
2626 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
2627 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
2628 util_next_power_of_two(num_comps
) :
2633 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
2634 vdata
, num_comps
, so_write_offsets
[buf
],
2635 ctx
->ac
.i32_0
, offset
,
2636 ac_glc
| ac_slc
, false);
2640 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
2642 struct ac_build_if_state if_ctx
;
2645 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2646 assert(ctx
->streamout_config
);
2647 LLVMValueRef so_vtx_count
=
2648 ac_build_bfe(&ctx
->ac
, ctx
->streamout_config
,
2649 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2650 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
2652 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2654 /* can_emit = tid < so_vtx_count; */
2655 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
2656 tid
, so_vtx_count
, "");
2658 /* Emit the streamout code conditionally. This actually avoids
2659 * out-of-bounds buffer access. The hw tells us via the SGPR
2660 * (so_vtx_count) which threads are allowed to emit streamout data.
2662 ac_nir_build_if(&if_ctx
, ctx
, can_emit
);
2664 /* The buffer offset is computed as follows:
2665 * ByteOffset = streamout_offset[buffer_id]*4 +
2666 * (streamout_write_index + thread_id)*stride[buffer_id] +
2669 LLVMValueRef so_write_index
= ctx
->streamout_write_idx
;
2671 /* Compute (streamout_write_index + thread_id). */
2673 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
2675 /* Load the descriptor and compute the write offset for each
2678 LLVMValueRef so_write_offset
[4] = {};
2679 LLVMValueRef so_buffers
[4] = {};
2680 LLVMValueRef buf_ptr
= ctx
->streamout_buffers
;
2682 for (i
= 0; i
< 4; i
++) {
2683 uint16_t stride
= ctx
->shader_info
->info
.so
.strides
[i
];
2688 LLVMValueRef offset
=
2689 LLVMConstInt(ctx
->ac
.i32
, i
, false);
2691 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
2694 LLVMValueRef so_offset
= ctx
->streamout_offset
[i
];
2696 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
2697 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2699 so_write_offset
[i
] =
2700 ac_build_imad(&ctx
->ac
, so_write_index
,
2701 LLVMConstInt(ctx
->ac
.i32
,
2706 /* Write streamout data. */
2707 for (i
= 0; i
< ctx
->shader_info
->info
.so
.num_outputs
; i
++) {
2708 struct radv_shader_output_values shader_out
= {};
2709 struct radv_stream_output
*output
=
2710 &ctx
->shader_info
->info
.so
.outputs
[i
];
2712 if (stream
!= output
->stream
)
2715 for (int j
= 0; j
< 4; j
++) {
2716 shader_out
.values
[j
] =
2717 radv_load_output(ctx
, output
->location
, j
);
2720 radv_emit_stream_output(ctx
, so_buffers
,so_write_offset
,
2721 output
, &shader_out
);
2724 ac_nir_build_endif(&if_ctx
);
2728 radv_build_param_exports(struct radv_shader_context
*ctx
,
2729 struct radv_shader_output_values
*outputs
,
2731 struct radv_vs_output_info
*outinfo
,
2732 bool export_clip_dists
)
2734 unsigned param_count
= 0;
2736 for (unsigned i
= 0; i
< noutput
; i
++) {
2737 unsigned slot_name
= outputs
[i
].slot_name
;
2738 unsigned usage_mask
= outputs
[i
].usage_mask
;
2740 if (slot_name
!= VARYING_SLOT_LAYER
&&
2741 slot_name
!= VARYING_SLOT_PRIMITIVE_ID
&&
2742 slot_name
!= VARYING_SLOT_CLIP_DIST0
&&
2743 slot_name
!= VARYING_SLOT_CLIP_DIST1
&&
2744 slot_name
< VARYING_SLOT_VAR0
)
2747 if ((slot_name
== VARYING_SLOT_CLIP_DIST0
||
2748 slot_name
== VARYING_SLOT_CLIP_DIST1
) && !export_clip_dists
)
2751 radv_export_param(ctx
, param_count
, outputs
[i
].values
, usage_mask
);
2753 assert(i
< ARRAY_SIZE(outinfo
->vs_output_param_offset
));
2754 outinfo
->vs_output_param_offset
[slot_name
] = param_count
++;
2757 outinfo
->param_exports
= param_count
;
2760 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2761 * (position and parameter data only).
2764 radv_llvm_export_vs(struct radv_shader_context
*ctx
,
2765 struct radv_shader_output_values
*outputs
,
2767 struct radv_vs_output_info
*outinfo
,
2768 bool export_clip_dists
)
2770 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_value
= NULL
;
2771 struct ac_export_args pos_args
[4] = {};
2772 unsigned pos_idx
, index
;
2775 /* Build position exports */
2776 for (i
= 0; i
< noutput
; i
++) {
2777 switch (outputs
[i
].slot_name
) {
2778 case VARYING_SLOT_POS
:
2779 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
2780 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2782 case VARYING_SLOT_PSIZ
:
2783 psize_value
= outputs
[i
].values
[0];
2785 case VARYING_SLOT_LAYER
:
2786 layer_value
= outputs
[i
].values
[0];
2788 case VARYING_SLOT_VIEWPORT
:
2789 viewport_value
= outputs
[i
].values
[0];
2791 case VARYING_SLOT_CLIP_DIST0
:
2792 case VARYING_SLOT_CLIP_DIST1
:
2793 index
= 2 + outputs
[i
].slot_index
;
2794 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
2795 V_008DFC_SQ_EXP_POS
+ index
,
2803 /* We need to add the position output manually if it's missing. */
2804 if (!pos_args
[0].out
[0]) {
2805 pos_args
[0].enabled_channels
= 0xf; /* writemask */
2806 pos_args
[0].valid_mask
= 0; /* EXEC mask */
2807 pos_args
[0].done
= 0; /* last export? */
2808 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
2809 pos_args
[0].compr
= 0; /* COMPR flag */
2810 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
2811 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
2812 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
2813 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
2816 if (outinfo
->writes_pointsize
||
2817 outinfo
->writes_layer
||
2818 outinfo
->writes_viewport_index
) {
2819 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2820 (outinfo
->writes_layer
== true ? 4 : 0));
2821 pos_args
[1].valid_mask
= 0;
2822 pos_args
[1].done
= 0;
2823 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2824 pos_args
[1].compr
= 0;
2825 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2826 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2827 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2828 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2830 if (outinfo
->writes_pointsize
== true)
2831 pos_args
[1].out
[0] = psize_value
;
2832 if (outinfo
->writes_layer
== true)
2833 pos_args
[1].out
[2] = layer_value
;
2834 if (outinfo
->writes_viewport_index
== true) {
2835 if (ctx
->options
->chip_class
>= GFX9
) {
2836 /* GFX9 has the layer in out.z[10:0] and the viewport
2837 * index in out.z[19:16].
2839 LLVMValueRef v
= viewport_value
;
2840 v
= ac_to_integer(&ctx
->ac
, v
);
2841 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2842 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2844 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2845 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2847 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2848 pos_args
[1].enabled_channels
|= 1 << 2;
2850 pos_args
[1].out
[3] = viewport_value
;
2851 pos_args
[1].enabled_channels
|= 1 << 3;
2856 for (i
= 0; i
< 4; i
++) {
2857 if (pos_args
[i
].out
[0])
2858 outinfo
->pos_exports
++;
2861 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2862 * Setting valid_mask=1 prevents it and has no other effect.
2864 if (ctx
->ac
.family
== CHIP_NAVI10
||
2865 ctx
->ac
.family
== CHIP_NAVI12
||
2866 ctx
->ac
.family
== CHIP_NAVI14
)
2867 pos_args
[0].valid_mask
= 1;
2870 for (i
= 0; i
< 4; i
++) {
2871 if (!pos_args
[i
].out
[0])
2874 /* Specify the target we are exporting */
2875 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2877 if (pos_idx
== outinfo
->pos_exports
)
2878 /* Specify that this is the last export */
2879 pos_args
[i
].done
= 1;
2881 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2884 /* Build parameter exports */
2885 radv_build_param_exports(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2889 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2890 bool export_prim_id
,
2891 bool export_clip_dists
,
2892 struct radv_vs_output_info
*outinfo
)
2894 struct radv_shader_output_values
*outputs
;
2895 unsigned noutput
= 0;
2897 if (ctx
->options
->key
.has_multiview_view_index
) {
2898 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2900 for(unsigned i
= 0; i
< 4; ++i
)
2901 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2902 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2905 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
2906 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2909 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2910 sizeof(outinfo
->vs_output_param_offset
));
2911 outinfo
->pos_exports
= 0;
2913 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
2914 outinfo
->writes_pointsize
= true;
2917 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
2918 outinfo
->writes_layer
= true;
2921 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
2922 outinfo
->writes_viewport_index
= true;
2925 if (ctx
->shader_info
->info
.so
.num_outputs
&&
2926 !ctx
->is_gs_copy_shader
) {
2927 /* The GS copy shader emission already emits streamout. */
2928 radv_emit_streamout(ctx
, 0);
2931 /* Allocate a temporary array for the output values. */
2932 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_prim_id
;
2933 outputs
= malloc(num_outputs
* sizeof(outputs
[0]));
2935 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2936 if (!(ctx
->output_mask
& (1ull << i
)))
2939 outputs
[noutput
].slot_name
= i
;
2940 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2942 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2943 !ctx
->is_gs_copy_shader
) {
2944 outputs
[noutput
].usage_mask
=
2945 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2946 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2947 outputs
[noutput
].usage_mask
=
2948 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2950 assert(ctx
->is_gs_copy_shader
);
2951 outputs
[noutput
].usage_mask
=
2952 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
2955 for (unsigned j
= 0; j
< 4; j
++) {
2956 outputs
[noutput
].values
[j
] =
2957 ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2963 /* Export PrimitiveID. */
2964 if (export_prim_id
) {
2965 outinfo
->export_prim_id
= true;
2967 outputs
[noutput
].slot_name
= VARYING_SLOT_PRIMITIVE_ID
;
2968 outputs
[noutput
].slot_index
= 0;
2969 outputs
[noutput
].usage_mask
= 0x1;
2970 outputs
[noutput
].values
[0] = ctx
->vs_prim_id
;
2971 for (unsigned j
= 1; j
< 4; j
++)
2972 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
2976 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2982 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2983 struct radv_es_output_info
*outinfo
)
2986 uint64_t max_output_written
= 0;
2987 LLVMValueRef lds_base
= NULL
;
2989 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2992 if (!(ctx
->output_mask
& (1ull << i
)))
2995 param_index
= shader_io_get_unique_index(i
);
2997 max_output_written
= MAX2(param_index
, max_output_written
);
3000 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
3002 if (ctx
->ac
.chip_class
>= GFX9
) {
3003 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
3004 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
3005 LLVMValueRef wave_idx
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
3006 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
3007 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
3008 LLVMConstInt(ctx
->ac
.i32
,
3009 ctx
->ac
.wave_size
, false), ""), "");
3010 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
3011 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
3014 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3015 LLVMValueRef dw_addr
= NULL
;
3016 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
3017 unsigned output_usage_mask
;
3020 if (!(ctx
->output_mask
& (1ull << i
)))
3023 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3025 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
3027 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3029 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
3032 param_index
= shader_io_get_unique_index(i
);
3035 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3036 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
3040 for (j
= 0; j
< 4; j
++) {
3041 if (!(output_usage_mask
& (1 << j
)))
3044 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
3045 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3046 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3048 if (ctx
->ac
.chip_class
>= GFX9
) {
3049 LLVMValueRef dw_addr_offset
=
3050 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3051 LLVMConstInt(ctx
->ac
.i32
,
3054 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
3056 ac_build_buffer_store_dword(&ctx
->ac
,
3059 NULL
, ctx
->es2gs_offset
,
3060 (4 * param_index
+ j
) * 4,
3061 ac_glc
| ac_slc
, true);
3068 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
3070 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
3071 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->shader_info
->info
.vs
.ls_outputs_written
);
3072 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
3073 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
3074 vertex_dw_stride
, "");
3076 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3077 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
3079 if (!(ctx
->output_mask
& (1ull << i
)))
3082 int param
= shader_io_get_unique_index(i
);
3083 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
3084 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
3086 for (unsigned j
= 0; j
< 4; j
++) {
3087 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
3088 value
= ac_to_integer(&ctx
->ac
, value
);
3089 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
3090 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
3091 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
3096 static LLVMValueRef
get_wave_id_in_tg(struct radv_shader_context
*ctx
)
3098 return ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
3101 static LLVMValueRef
get_tgsize(struct radv_shader_context
*ctx
)
3103 return ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 28, 4);
3106 static LLVMValueRef
get_thread_id_in_tg(struct radv_shader_context
*ctx
)
3108 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3110 tmp
= LLVMBuildMul(builder
, get_wave_id_in_tg(ctx
),
3111 LLVMConstInt(ctx
->ac
.i32
, ctx
->ac
.wave_size
, false), "");
3112 return LLVMBuildAdd(builder
, tmp
, ac_get_thread_id(&ctx
->ac
), "");
3115 static LLVMValueRef
ngg_get_vtx_cnt(struct radv_shader_context
*ctx
)
3117 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
3118 LLVMConstInt(ctx
->ac
.i32
, 12, false),
3119 LLVMConstInt(ctx
->ac
.i32
, 9, false),
3123 static LLVMValueRef
ngg_get_prim_cnt(struct radv_shader_context
*ctx
)
3125 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
3126 LLVMConstInt(ctx
->ac
.i32
, 22, false),
3127 LLVMConstInt(ctx
->ac
.i32
, 9, false),
3132 ngg_gs_get_vertex_storage(struct radv_shader_context
*ctx
)
3134 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
);
3136 LLVMTypeRef elements
[2] = {
3137 LLVMArrayType(ctx
->ac
.i32
, 4 * num_outputs
),
3138 LLVMArrayType(ctx
->ac
.i8
, 4),
3140 LLVMTypeRef type
= LLVMStructTypeInContext(ctx
->ac
.context
, elements
, 2, false);
3141 type
= LLVMPointerType(LLVMArrayType(type
, 0), AC_ADDR_SPACE_LDS
);
3142 return LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gs_ngg_emit
, type
, "");
3146 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
3147 * is in emit order; that is:
3148 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
3149 * - during vertex emit, i.e. while the API GS shader invocation is running,
3150 * N = threadidx * gs_max_out_vertices + emitidx
3152 * Goals of the LDS memory layout:
3153 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
3154 * in uniform control flow
3155 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
3157 * 3. Agnostic to the number of waves (since we don't know it before compiling)
3158 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
3159 * 5. Avoid wasting memory.
3161 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
3162 * layout, elimination of bank conflicts requires that each vertex occupy an
3163 * odd number of dwords. We use the additional dword to store the output stream
3164 * index as well as a flag to indicate whether this vertex ends a primitive
3165 * for rasterization.
3167 * Swizzling is required to satisfy points 1 and 2 simultaneously.
3169 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
3170 * Indices are swizzled in groups of 32, which ensures point 1 without
3171 * disturbing point 2.
3173 * \return an LDS pointer to type {[N x i32], [4 x i8]}
3176 ngg_gs_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexidx
)
3178 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3179 LLVMValueRef storage
= ngg_gs_get_vertex_storage(ctx
);
3181 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
3182 unsigned write_stride_2exp
= ffs(ctx
->gs_max_out_vertices
) - 1;
3183 if (write_stride_2exp
) {
3185 LLVMBuildLShr(builder
, vertexidx
,
3186 LLVMConstInt(ctx
->ac
.i32
, 5, false), "");
3187 LLVMValueRef swizzle
=
3188 LLVMBuildAnd(builder
, row
,
3189 LLVMConstInt(ctx
->ac
.i32
, (1u << write_stride_2exp
) - 1,
3191 vertexidx
= LLVMBuildXor(builder
, vertexidx
, swizzle
, "");
3194 return ac_build_gep0(&ctx
->ac
, storage
, vertexidx
);
3198 ngg_gs_emit_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef gsthread
,
3199 LLVMValueRef emitidx
)
3201 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3204 tmp
= LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false);
3205 tmp
= LLVMBuildMul(builder
, tmp
, gsthread
, "");
3206 const LLVMValueRef vertexidx
= LLVMBuildAdd(builder
, tmp
, emitidx
, "");
3207 return ngg_gs_vertex_ptr(ctx
, vertexidx
);
3210 /* Send GS Alloc Req message from the first wave of the group to SPI.
3211 * Message payload is:
3212 * - bits 0..10: vertices in group
3213 * - bits 12..22: primitives in group
3215 static void build_sendmsg_gs_alloc_req(struct radv_shader_context
*ctx
,
3216 LLVMValueRef vtx_cnt
,
3217 LLVMValueRef prim_cnt
)
3219 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3222 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
3223 ac_build_ifcc(&ctx
->ac
, tmp
, 5020);
3225 tmp
= LLVMBuildShl(builder
, prim_cnt
, LLVMConstInt(ctx
->ac
.i32
, 12, false),"");
3226 tmp
= LLVMBuildOr(builder
, tmp
, vtx_cnt
, "");
3227 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_ALLOC_REQ
, tmp
);
3229 ac_build_endif(&ctx
->ac
, 5020);
3233 unsigned num_vertices
;
3234 LLVMValueRef isnull
;
3235 LLVMValueRef index
[3];
3236 LLVMValueRef edgeflag
[3];
3239 static void build_export_prim(struct radv_shader_context
*ctx
,
3240 const struct ngg_prim
*prim
)
3242 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3243 struct ac_export_args args
;
3246 tmp
= LLVMBuildZExt(builder
, prim
->isnull
, ctx
->ac
.i32
, "");
3247 args
.out
[0] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 31, false), "");
3249 for (unsigned i
= 0; i
< prim
->num_vertices
; ++i
) {
3250 tmp
= LLVMBuildShl(builder
, prim
->index
[i
],
3251 LLVMConstInt(ctx
->ac
.i32
, 10 * i
, false), "");
3252 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3253 tmp
= LLVMBuildZExt(builder
, prim
->edgeflag
[i
], ctx
->ac
.i32
, "");
3254 tmp
= LLVMBuildShl(builder
, tmp
,
3255 LLVMConstInt(ctx
->ac
.i32
, 10 * i
+ 9, false), "");
3256 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3259 args
.out
[0] = LLVMBuildBitCast(builder
, args
.out
[0], ctx
->ac
.f32
, "");
3260 args
.out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
3261 args
.out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
3262 args
.out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
3264 args
.target
= V_008DFC_SQ_EXP_PRIM
;
3265 args
.enabled_channels
= 1;
3267 args
.valid_mask
= false;
3270 ac_build_export(&ctx
->ac
, &args
);
3274 handle_ngg_outputs_post(struct radv_shader_context
*ctx
)
3276 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3277 struct ac_build_if_state if_state
;
3278 unsigned num_vertices
= 3;
3281 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
3282 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->is_gs_copy_shader
);
3284 LLVMValueRef prims_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
3285 LLVMValueRef vtx_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 0, 8);
3286 LLVMValueRef is_gs_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3287 ac_get_thread_id(&ctx
->ac
), prims_in_wave
, "");
3288 LLVMValueRef is_es_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3289 ac_get_thread_id(&ctx
->ac
), vtx_in_wave
, "");
3290 LLVMValueRef vtxindex
[] = {
3291 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 0, 16),
3292 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 16, 16),
3293 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[2], 0, 16),
3296 /* TODO: streamout */
3298 /* Copy Primitive IDs from GS threads to the LDS address corresponding
3299 * to the ES thread of the provoking vertex.
3301 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
3302 ctx
->options
->key
.vs_common_out
.export_prim_id
) {
3303 /* TODO: streamout */
3305 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 5400);
3306 /* Extract the PROVOKING_VTX_INDEX field. */
3307 LLVMValueRef provoking_vtx_in_prim
=
3308 LLVMConstInt(ctx
->ac
.i32
, 0, false);
3310 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
3311 LLVMValueRef indices
= ac_build_gather_values(&ctx
->ac
, vtxindex
, 3);
3312 LLVMValueRef provoking_vtx_index
=
3313 LLVMBuildExtractElement(builder
, indices
, provoking_vtx_in_prim
, "");
3315 LLVMBuildStore(builder
, ctx
->abi
.gs_prim_id
,
3316 ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
, provoking_vtx_index
));
3317 ac_build_endif(&ctx
->ac
, 5400);
3320 /* TODO: primitive culling */
3322 build_sendmsg_gs_alloc_req(ctx
, ngg_get_vtx_cnt(ctx
), ngg_get_prim_cnt(ctx
));
3324 /* TODO: streamout queries */
3325 /* Export primitive data to the index buffer. Format is:
3326 * - bits 0..8: index 0
3327 * - bit 9: edge flag 0
3328 * - bits 10..18: index 1
3329 * - bit 19: edge flag 1
3330 * - bits 20..28: index 2
3331 * - bit 29: edge flag 2
3332 * - bit 31: null primitive (skip)
3334 * For the first version, we will always build up all three indices
3335 * independent of the primitive type. The additional garbage data
3338 * TODO: culling depends on the primitive type, so can have some
3341 ac_nir_build_if(&if_state
, ctx
, is_gs_thread
);
3343 struct ngg_prim prim
= {};
3345 prim
.num_vertices
= num_vertices
;
3346 prim
.isnull
= ctx
->ac
.i1false
;
3347 memcpy(prim
.index
, vtxindex
, sizeof(vtxindex
[0]) * 3);
3349 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
3350 tmp
= LLVMBuildLShr(builder
, ctx
->abi
.gs_invocation_id
,
3351 LLVMConstInt(ctx
->ac
.i32
, 8 + i
, false), "");
3352 prim
.edgeflag
[i
] = LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3355 build_export_prim(ctx
, &prim
);
3357 ac_nir_build_endif(&if_state
);
3359 /* Export per-vertex data (positions and parameters). */
3360 ac_nir_build_if(&if_state
, ctx
, is_es_thread
);
3362 struct radv_vs_output_info
*outinfo
=
3363 ctx
->stage
== MESA_SHADER_TESS_EVAL
? &ctx
->shader_info
->tes
.outinfo
: &ctx
->shader_info
->vs
.outinfo
;
3365 /* Exporting the primitive ID is handled below. */
3366 /* TODO: use the new VS export path */
3367 handle_vs_outputs_post(ctx
, false,
3368 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
3371 if (ctx
->options
->key
.vs_common_out
.export_prim_id
) {
3372 unsigned param_count
= outinfo
->param_exports
;
3373 LLVMValueRef values
[4];
3375 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3376 /* Wait for GS stores to finish. */
3377 ac_build_s_barrier(&ctx
->ac
);
3379 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
,
3380 get_thread_id_in_tg(ctx
));
3381 values
[0] = LLVMBuildLoad(builder
, tmp
, "");
3383 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3384 values
[0] = ctx
->abi
.tes_patch_id
;
3387 values
[0] = ac_to_float(&ctx
->ac
, values
[0]);
3388 for (unsigned j
= 1; j
< 4; j
++)
3389 values
[j
] = ctx
->ac
.f32_0
;
3391 radv_export_param(ctx
, param_count
, values
, 0x1);
3393 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
3394 outinfo
->export_prim_id
= true;
3395 outinfo
->param_exports
= param_count
;
3398 ac_nir_build_endif(&if_state
);
3401 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context
*ctx
)
3403 /* Zero out the part of LDS scratch that is used to accumulate the
3404 * per-stream generated primitive count.
3406 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3407 LLVMValueRef scratchptr
= ctx
->gs_ngg_scratch
;
3408 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3409 LLVMBasicBlockRef merge_block
;
3412 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
3413 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3414 merge_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3416 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3417 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, then_block
, merge_block
);
3418 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, then_block
);
3420 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, scratchptr
, tid
);
3421 LLVMBuildStore(builder
, ctx
->ac
.i32_0
, ptr
);
3423 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
3424 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
3426 ac_build_s_barrier(&ctx
->ac
);
3429 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context
*ctx
)
3431 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3432 LLVMValueRef i8_0
= LLVMConstInt(ctx
->ac
.i8
, 0, false);
3435 /* Zero out remaining (non-emitted) primitive flags.
3437 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3438 * the emit threads via LDS. This is likely worse in the expected
3439 * typical case where each GS thread emits the full set of
3442 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3443 unsigned num_components
;
3446 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
3447 if (!num_components
)
3450 const LLVMValueRef gsthread
= get_thread_id_in_tg(ctx
);
3452 ac_build_bgnloop(&ctx
->ac
, 5100);
3454 const LLVMValueRef vertexidx
=
3455 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3456 tmp
= LLVMBuildICmp(builder
, LLVMIntUGE
, vertexidx
,
3457 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
3458 ac_build_ifcc(&ctx
->ac
, tmp
, 5101);
3459 ac_build_break(&ctx
->ac
);
3460 ac_build_endif(&ctx
->ac
, 5101);
3462 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3463 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3465 tmp
= ngg_gs_emit_vertex_ptr(ctx
, gsthread
, vertexidx
);
3466 LLVMValueRef gep_idx
[3] = {
3467 ctx
->ac
.i32_0
, /* implied C-style array */
3468 ctx
->ac
.i32_1
, /* second entry of struct */
3469 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3471 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3472 LLVMBuildStore(builder
, i8_0
, tmp
);
3474 ac_build_endloop(&ctx
->ac
, 5100);
3478 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context
*ctx
)
3480 const unsigned verts_per_prim
= si_conv_gl_prim_to_vertices(ctx
->gs_output_prim
);
3481 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3482 LLVMValueRef tmp
, tmp2
;
3484 ac_build_s_barrier(&ctx
->ac
);
3486 const LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3487 LLVMValueRef num_emit_threads
= ngg_get_prim_cnt(ctx
);
3489 /* TODO: streamout */
3493 /* Determine vertex liveness. */
3494 LLVMValueRef vertliveptr
= ac_build_alloca(&ctx
->ac
, ctx
->ac
.i1
, "vertexlive");
3496 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3497 ac_build_ifcc(&ctx
->ac
, tmp
, 5120);
3499 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3500 const LLVMValueRef primidx
=
3501 LLVMBuildAdd(builder
, tid
,
3502 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
3505 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, primidx
, num_emit_threads
, "");
3506 ac_build_ifcc(&ctx
->ac
, tmp
, 5121 + i
);
3509 /* Load primitive liveness */
3510 tmp
= ngg_gs_vertex_ptr(ctx
, primidx
);
3511 LLVMValueRef gep_idx
[3] = {
3512 ctx
->ac
.i32_0
, /* implicit C-style array */
3513 ctx
->ac
.i32_1
, /* second value of struct */
3514 ctx
->ac
.i32_0
, /* stream 0 */
3516 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3517 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3518 const LLVMValueRef primlive
=
3519 LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3521 tmp
= LLVMBuildLoad(builder
, vertliveptr
, "");
3522 tmp
= LLVMBuildOr(builder
, tmp
, primlive
, ""),
3523 LLVMBuildStore(builder
, tmp
, vertliveptr
);
3526 ac_build_endif(&ctx
->ac
, 5121 + i
);
3529 ac_build_endif(&ctx
->ac
, 5120);
3531 /* Inclusive scan addition across the current wave. */
3532 LLVMValueRef vertlive
= LLVMBuildLoad(builder
, vertliveptr
, "");
3533 struct ac_wg_scan vertlive_scan
= {};
3534 vertlive_scan
.op
= nir_op_iadd
;
3535 vertlive_scan
.enable_reduce
= true;
3536 vertlive_scan
.enable_exclusive
= true;
3537 vertlive_scan
.src
= vertlive
;
3538 vertlive_scan
.scratch
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ctx
->ac
.i32_0
);
3539 vertlive_scan
.waveidx
= get_wave_id_in_tg(ctx
);
3540 vertlive_scan
.numwaves
= get_tgsize(ctx
);
3541 vertlive_scan
.maxwaves
= 8;
3543 ac_build_wg_scan(&ctx
->ac
, &vertlive_scan
);
3545 /* Skip all exports (including index exports) when possible. At least on
3546 * early gfx10 revisions this is also to avoid hangs.
3548 LLVMValueRef have_exports
=
3549 LLVMBuildICmp(builder
, LLVMIntNE
, vertlive_scan
.result_reduce
, ctx
->ac
.i32_0
, "");
3551 LLVMBuildSelect(builder
, have_exports
, num_emit_threads
, ctx
->ac
.i32_0
, "");
3553 /* Allocate export space. Send this message as early as possible, to
3554 * hide the latency of the SQ <-> SPI roundtrip.
3556 * Note: We could consider compacting primitives for export as well.
3557 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3558 * prim data per clock and skips null primitives at no additional
3559 * cost. So compacting primitives can only be beneficial when
3560 * there are 4 or more contiguous null primitives in the export
3561 * (in the common case of single-dword prim exports).
3563 build_sendmsg_gs_alloc_req(ctx
, vertlive_scan
.result_reduce
, num_emit_threads
);
3565 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3566 * of the primitive liveness flags, relying on the fact that each
3567 * threadgroup can have at most 256 threads. */
3568 ac_build_ifcc(&ctx
->ac
, vertlive
, 5130);
3570 tmp
= ngg_gs_vertex_ptr(ctx
, vertlive_scan
.result_exclusive
);
3571 LLVMValueRef gep_idx
[3] = {
3572 ctx
->ac
.i32_0
, /* implicit C-style array */
3573 ctx
->ac
.i32_1
, /* second value of struct */
3574 ctx
->ac
.i32_1
, /* stream 1 */
3576 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3577 tmp2
= LLVMBuildTrunc(builder
, tid
, ctx
->ac
.i8
, "");
3578 LLVMBuildStore(builder
, tmp2
, tmp
);
3580 ac_build_endif(&ctx
->ac
, 5130);
3582 ac_build_s_barrier(&ctx
->ac
);
3584 /* Export primitive data */
3585 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3586 ac_build_ifcc(&ctx
->ac
, tmp
, 5140);
3588 struct ngg_prim prim
= {};
3589 prim
.num_vertices
= verts_per_prim
;
3591 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3592 LLVMValueRef gep_idx
[3] = {
3593 ctx
->ac
.i32_0
, /* implicit C-style array */
3594 ctx
->ac
.i32_1
, /* second value of struct */
3595 ctx
->ac
.i32_0
, /* primflag */
3597 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3598 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3599 prim
.isnull
= LLVMBuildICmp(builder
, LLVMIntEQ
, tmp
,
3600 LLVMConstInt(ctx
->ac
.i8
, 0, false), "");
3602 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3603 prim
.index
[i
] = LLVMBuildSub(builder
, vertlive_scan
.result_exclusive
,
3604 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3605 prim
.edgeflag
[i
] = ctx
->ac
.i1false
;
3608 build_export_prim(ctx
, &prim
);
3610 ac_build_endif(&ctx
->ac
, 5140);
3612 /* Export position and parameter data */
3613 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, vertlive_scan
.result_reduce
, "");
3614 ac_build_ifcc(&ctx
->ac
, tmp
, 5145);
3616 struct radv_vs_output_info
*outinfo
= &ctx
->shader_info
->vs
.outinfo
;
3617 bool export_view_index
= ctx
->options
->key
.has_multiview_view_index
;
3618 struct radv_shader_output_values
*outputs
;
3619 unsigned noutput
= 0;
3621 /* Allocate a temporary array for the output values. */
3622 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_view_index
;
3623 outputs
= calloc(num_outputs
, sizeof(outputs
[0]));
3625 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
3626 sizeof(outinfo
->vs_output_param_offset
));
3627 outinfo
->pos_exports
= 0;
3629 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3630 LLVMValueRef gep_idx
[3] = {
3631 ctx
->ac
.i32_0
, /* implicit C-style array */
3632 ctx
->ac
.i32_1
, /* second value of struct */
3633 ctx
->ac
.i32_1
, /* stream 1: source data index */
3635 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3636 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3637 tmp
= LLVMBuildZExt(builder
, tmp
, ctx
->ac
.i32
, "");
3638 const LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tmp
);
3640 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
3641 outinfo
->writes_pointsize
= true;
3644 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
3645 outinfo
->writes_layer
= true;
3648 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
3649 outinfo
->writes_viewport_index
= true;
3652 unsigned out_idx
= 0;
3653 gep_idx
[1] = ctx
->ac
.i32_0
;
3654 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3655 if (!(ctx
->output_mask
& (1ull << i
)))
3658 outputs
[noutput
].slot_name
= i
;
3659 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
3661 outputs
[noutput
].usage_mask
= ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
3662 int length
= util_last_bit(outputs
[noutput
].usage_mask
);
3664 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3665 gep_idx
[2] = LLVMConstInt(ctx
->ac
.i32
, out_idx
, false);
3666 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3667 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3669 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3670 if (ac_get_type_size(type
) == 2) {
3671 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
3672 tmp
= LLVMBuildTrunc(ctx
->ac
.builder
, tmp
, ctx
->ac
.i16
, "");
3675 outputs
[noutput
].values
[j
] = ac_to_float(&ctx
->ac
, tmp
);
3678 for (unsigned j
= length
; j
< 4; j
++)
3679 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
3684 /* Export ViewIndex. */
3685 if (export_view_index
) {
3686 outinfo
->writes_layer
= true;
3688 outputs
[noutput
].slot_name
= VARYING_SLOT_LAYER
;
3689 outputs
[noutput
].slot_index
= 0;
3690 outputs
[noutput
].usage_mask
= 0x1;
3691 outputs
[noutput
].values
[0] = ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
);
3692 for (unsigned j
= 1; j
< 4; j
++)
3693 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
3697 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
,
3698 ctx
->options
->key
.vs_common_out
.export_clip_dists
);
3701 ac_build_endif(&ctx
->ac
, 5145);
3704 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
3706 LLVMValueRef
*addrs
)
3708 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3710 const LLVMValueRef vertexidx
=
3711 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3713 /* If this thread has already emitted the declared maximum number of
3714 * vertices, skip the write: excessive vertex emissions are not
3715 * supposed to have any effect.
3717 const LLVMValueRef can_emit
=
3718 LLVMBuildICmp(builder
, LLVMIntULT
, vertexidx
,
3719 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
3720 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
3722 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3723 tmp
= LLVMBuildSelect(builder
, can_emit
, tmp
, vertexidx
, "");
3724 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3726 const LLVMValueRef vertexptr
=
3727 ngg_gs_emit_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
), vertexidx
);
3728 unsigned out_idx
= 0;
3729 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3730 unsigned output_usage_mask
=
3731 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
3732 uint8_t output_stream
=
3733 ctx
->shader_info
->info
.gs
.output_streams
[i
];
3734 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
3735 int length
= util_last_bit(output_usage_mask
);
3737 if (!(ctx
->output_mask
& (1ull << i
)) ||
3738 output_stream
!= stream
)
3741 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3742 if (!(output_usage_mask
& (1 << j
)))
3745 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
3747 LLVMValueRef gep_idx
[3] = {
3748 ctx
->ac
.i32_0
, /* implied C-style array */
3749 ctx
->ac
.i32_0
, /* first entry of struct */
3750 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false),
3752 LLVMValueRef ptr
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3754 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3755 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3757 LLVMBuildStore(builder
, out_val
, ptr
);
3760 assert(out_idx
* 4 <= ctx
->gsvs_vertex_size
);
3762 /* Determine and store whether this vertex completed a primitive. */
3763 const LLVMValueRef curverts
= LLVMBuildLoad(builder
, ctx
->gs_curprim_verts
[stream
], "");
3765 tmp
= LLVMConstInt(ctx
->ac
.i32
, si_conv_gl_prim_to_vertices(ctx
->gs_output_prim
) - 1, false);
3766 const LLVMValueRef iscompleteprim
=
3767 LLVMBuildICmp(builder
, LLVMIntUGE
, curverts
, tmp
, "");
3769 tmp
= LLVMBuildAdd(builder
, curverts
, ctx
->ac
.i32_1
, "");
3770 LLVMBuildStore(builder
, tmp
, ctx
->gs_curprim_verts
[stream
]);
3772 LLVMValueRef gep_idx
[3] = {
3773 ctx
->ac
.i32_0
, /* implied C-style array */
3774 ctx
->ac
.i32_1
, /* second struct entry */
3775 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3777 const LLVMValueRef primflagptr
=
3778 LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3780 tmp
= LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i8
, "");
3781 LLVMBuildStore(builder
, tmp
, primflagptr
);
3783 tmp
= LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3784 tmp
= LLVMBuildAdd(builder
, tmp
, LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i32
, ""), "");
3785 LLVMBuildStore(builder
, tmp
, ctx
->gs_generated_prims
[stream
]);
3789 write_tess_factors(struct radv_shader_context
*ctx
)
3791 unsigned stride
, outer_comps
, inner_comps
;
3792 struct ac_build_if_state if_ctx
, inner_if_ctx
;
3793 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3794 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
3795 unsigned tess_inner_index
= 0, tess_outer_index
;
3796 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3797 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3799 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3801 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
3821 ac_nir_build_if(&if_ctx
, ctx
,
3822 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3823 invocation_id
, ctx
->ac
.i32_0
, ""));
3825 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3828 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3829 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3830 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3833 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3834 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3835 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3837 for (i
= 0; i
< 4; i
++) {
3838 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3839 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3843 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3844 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3845 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3847 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3849 for (i
= 0; i
< outer_comps
; i
++) {
3851 ac_lds_load(&ctx
->ac
, lds_outer
);
3852 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3855 for (i
= 0; i
< inner_comps
; i
++) {
3856 inner
[i
] = out
[outer_comps
+i
] =
3857 ac_lds_load(&ctx
->ac
, lds_inner
);
3858 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3863 /* Convert the outputs to vectors for stores. */
3864 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3868 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3871 buffer
= ctx
->hs_ring_tess_factor
;
3872 tf_base
= ctx
->tess_factor_offset
;
3873 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3874 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3875 unsigned tf_offset
= 0;
3877 if (ctx
->options
->chip_class
<= GFX8
) {
3878 ac_nir_build_if(&inner_if_ctx
, ctx
,
3879 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3880 rel_patch_id
, ctx
->ac
.i32_0
, ""));
3882 /* Store the dynamic HS control word. */
3883 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3884 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3885 1, ctx
->ac
.i32_0
, tf_base
,
3889 ac_nir_build_endif(&inner_if_ctx
);
3892 /* Store the tessellation factors. */
3893 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3894 MIN2(stride
, 4), byteoffset
, tf_base
,
3895 tf_offset
, ac_glc
, false);
3897 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3898 stride
- 4, byteoffset
, tf_base
,
3899 16 + tf_offset
, ac_glc
, false);
3901 //store to offchip for TES to read - only if TES reads them
3902 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
3903 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3904 LLVMValueRef tf_inner_offset
;
3905 unsigned param_outer
, param_inner
;
3907 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3908 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3909 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3911 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3912 util_next_power_of_two(outer_comps
));
3914 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3915 outer_comps
, tf_outer_offset
,
3916 ctx
->oc_lds
, 0, ac_glc
, false);
3918 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3919 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3920 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3922 inner_vec
= inner_comps
== 1 ? inner
[0] :
3923 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3924 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3925 inner_comps
, tf_inner_offset
,
3926 ctx
->oc_lds
, 0, ac_glc
, false);
3929 ac_nir_build_endif(&if_ctx
);
3933 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3935 write_tess_factors(ctx
);
3939 si_export_mrt_color(struct radv_shader_context
*ctx
,
3940 LLVMValueRef
*color
, unsigned index
,
3941 struct ac_export_args
*args
)
3944 si_llvm_init_export_args(ctx
, color
, 0xf,
3945 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3946 if (!args
->enabled_channels
)
3947 return false; /* unnecessary NULL export */
3953 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3954 LLVMValueRef depth
, LLVMValueRef stencil
,
3955 LLVMValueRef samplemask
)
3957 struct ac_export_args args
;
3959 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3961 ac_build_export(&ctx
->ac
, &args
);
3965 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3968 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3969 struct ac_export_args color_args
[8];
3971 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3972 LLVMValueRef values
[4];
3974 if (!(ctx
->output_mask
& (1ull << i
)))
3977 if (i
< FRAG_RESULT_DATA0
)
3980 for (unsigned j
= 0; j
< 4; j
++)
3981 values
[j
] = ac_to_float(&ctx
->ac
,
3982 radv_load_output(ctx
, i
, j
));
3984 bool ret
= si_export_mrt_color(ctx
, values
,
3985 i
- FRAG_RESULT_DATA0
,
3986 &color_args
[index
]);
3991 /* Process depth, stencil, samplemask. */
3992 if (ctx
->shader_info
->info
.ps
.writes_z
) {
3993 depth
= ac_to_float(&ctx
->ac
,
3994 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3996 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
3997 stencil
= ac_to_float(&ctx
->ac
,
3998 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
4000 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
4001 samplemask
= ac_to_float(&ctx
->ac
,
4002 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
4005 /* Set the DONE bit on last non-null color export only if Z isn't
4009 !ctx
->shader_info
->info
.ps
.writes_z
&&
4010 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
4011 !ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
4012 unsigned last
= index
- 1;
4014 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
4015 color_args
[last
].done
= 1; /* DONE bit */
4018 /* Export PS outputs. */
4019 for (unsigned i
= 0; i
< index
; i
++)
4020 ac_build_export(&ctx
->ac
, &color_args
[i
]);
4022 if (depth
|| stencil
|| samplemask
)
4023 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
4025 ac_build_export_null(&ctx
->ac
);
4029 emit_gs_epilogue(struct radv_shader_context
*ctx
)
4031 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
4032 gfx10_ngg_gs_emit_epilogue_1(ctx
);
4036 if (ctx
->ac
.chip_class
>= GFX10
)
4037 LLVMBuildFence(ctx
->ac
.builder
, LLVMAtomicOrderingRelease
, false, "");
4039 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
4043 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
4044 LLVMValueRef
*addrs
)
4046 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4048 switch (ctx
->stage
) {
4049 case MESA_SHADER_VERTEX
:
4050 if (ctx
->options
->key
.vs_common_out
.as_ls
)
4051 handle_ls_outputs_post(ctx
);
4052 else if (ctx
->options
->key
.vs_common_out
.as_es
)
4053 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
4054 else if (ctx
->options
->key
.vs_common_out
.as_ngg
)
4055 break; /* handled outside of the shader body */
4057 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
4058 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
4059 &ctx
->shader_info
->vs
.outinfo
);
4061 case MESA_SHADER_FRAGMENT
:
4062 handle_fs_outputs_post(ctx
);
4064 case MESA_SHADER_GEOMETRY
:
4065 emit_gs_epilogue(ctx
);
4067 case MESA_SHADER_TESS_CTRL
:
4068 handle_tcs_outputs_post(ctx
);
4070 case MESA_SHADER_TESS_EVAL
:
4071 if (ctx
->options
->key
.vs_common_out
.as_es
)
4072 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
4073 else if (ctx
->options
->key
.vs_common_out
.as_ngg
)
4074 break; /* handled outside of the shader body */
4076 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
4077 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
4078 &ctx
->shader_info
->tes
.outinfo
);
4085 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
4086 LLVMPassManagerRef passmgr
,
4087 const struct radv_nir_compiler_options
*options
)
4089 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
4090 LLVMDisposeBuilder(ctx
->ac
.builder
);
4092 ac_llvm_context_dispose(&ctx
->ac
);
4096 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
4098 struct radv_vs_output_info
*outinfo
;
4100 switch (ctx
->stage
) {
4101 case MESA_SHADER_FRAGMENT
:
4102 case MESA_SHADER_COMPUTE
:
4103 case MESA_SHADER_TESS_CTRL
:
4104 case MESA_SHADER_GEOMETRY
:
4106 case MESA_SHADER_VERTEX
:
4107 if (ctx
->options
->key
.vs_common_out
.as_ls
||
4108 ctx
->options
->key
.vs_common_out
.as_es
)
4110 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
4112 case MESA_SHADER_TESS_EVAL
:
4113 if (ctx
->options
->key
.vs_common_out
.as_es
)
4115 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
4118 unreachable("Unhandled shader type");
4121 ac_optimize_vs_outputs(&ctx
->ac
,
4123 outinfo
->vs_output_param_offset
,
4125 &outinfo
->param_exports
);
4129 ac_setup_rings(struct radv_shader_context
*ctx
)
4131 if (ctx
->options
->chip_class
<= GFX8
&&
4132 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
4133 ctx
->options
->key
.vs_common_out
.as_es
|| ctx
->options
->key
.vs_common_out
.as_es
)) {
4134 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
4136 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
4138 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
4143 if (ctx
->is_gs_copy_shader
) {
4145 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
4146 LLVMConstInt(ctx
->ac
.i32
,
4147 RING_GSVS_VS
, false));
4150 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4151 /* The conceptual layout of the GSVS ring is
4152 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4153 * but the real memory layout is swizzled across
4155 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4157 * Override the buffer descriptor accordingly.
4159 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
4160 uint64_t stream_offset
= 0;
4161 unsigned num_records
= ctx
->ac
.wave_size
;
4162 LLVMValueRef base_ring
;
4165 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
4166 LLVMConstInt(ctx
->ac
.i32
,
4167 RING_GSVS_GS
, false));
4169 for (unsigned stream
= 0; stream
< 4; stream
++) {
4170 unsigned num_components
, stride
;
4171 LLVMValueRef ring
, tmp
;
4174 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
4176 if (!num_components
)
4179 stride
= 4 * num_components
* ctx
->gs_max_out_vertices
;
4181 /* Limit on the stride field for <= GFX7. */
4182 assert(stride
< (1 << 14));
4184 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
4185 base_ring
, v2i64
, "");
4186 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4187 ring
, ctx
->ac
.i32_0
, "");
4188 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
4189 LLVMConstInt(ctx
->ac
.i64
,
4190 stream_offset
, 0), "");
4191 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
4192 ring
, tmp
, ctx
->ac
.i32_0
, "");
4194 stream_offset
+= stride
* ctx
->ac
.wave_size
;
4196 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
4199 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
4201 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
4202 LLVMConstInt(ctx
->ac
.i32
,
4203 S_008F04_STRIDE(stride
), false), "");
4204 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
4207 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
4208 LLVMConstInt(ctx
->ac
.i32
,
4209 num_records
, false),
4210 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
4212 ctx
->gsvs_ring
[stream
] = ring
;
4216 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
4217 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4218 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
4219 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
4224 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
4225 gl_shader_stage stage
,
4226 const struct nir_shader
*nir
)
4228 const unsigned backup_sizes
[] = {chip_class
>= GFX9
? 128 : 64, 1, 1};
4229 return radv_get_max_workgroup_size(chip_class
, stage
, nir
? nir
->info
.cs
.local_size
: backup_sizes
);
4232 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
4233 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
4235 LLVMValueRef count
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
4236 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
4238 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
4239 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
4240 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
4243 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
4245 for(int i
= 5; i
>= 0; --i
) {
4246 ctx
->gs_vtx_offset
[i
] = ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
4250 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 16, 8);
4253 /* Ensure that the esgs ring is declared.
4255 * We declare it with 64KB alignment as a hint that the
4256 * pointer value will always be 0.
4258 static void declare_esgs_ring(struct radv_shader_context
*ctx
)
4263 assert(!LLVMGetNamedGlobal(ctx
->ac
.module
, "esgs_ring"));
4265 ctx
->esgs_ring
= LLVMAddGlobalInAddressSpace(
4266 ctx
->ac
.module
, LLVMArrayType(ctx
->ac
.i32
, 0),
4269 LLVMSetLinkage(ctx
->esgs_ring
, LLVMExternalLinkage
);
4270 LLVMSetAlignment(ctx
->esgs_ring
, 64 * 1024);
4274 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
4275 struct nir_shader
*const *shaders
,
4277 struct radv_shader_variant_info
*shader_info
,
4278 const struct radv_nir_compiler_options
*options
)
4280 struct radv_shader_context ctx
= {0};
4282 ctx
.options
= options
;
4283 ctx
.shader_info
= shader_info
;
4285 enum ac_float_mode float_mode
=
4286 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
4287 AC_FLOAT_MODE_DEFAULT
;
4289 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, options
->chip_class
,
4290 options
->family
, float_mode
, options
->wave_size
,
4291 options
->wave_size
);
4292 ctx
.context
= ctx
.ac
.context
;
4294 radv_nir_shader_info_init(&shader_info
->info
);
4296 for(int i
= 0; i
< shader_count
; ++i
)
4297 radv_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
4299 for (i
= 0; i
< MAX_SETS
; i
++)
4300 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
4301 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
4302 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
4304 ctx
.max_workgroup_size
= 0;
4305 for (int i
= 0; i
< shader_count
; ++i
) {
4306 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
4307 radv_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
4308 shaders
[i
]->info
.stage
,
4312 if (ctx
.ac
.chip_class
>= GFX10
) {
4313 if (is_pre_gs_stage(shaders
[0]->info
.stage
) &&
4314 options
->key
.vs_common_out
.as_ngg
) {
4315 ctx
.max_workgroup_size
= 128;
4319 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
4320 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
4322 ctx
.abi
.inputs
= &ctx
.inputs
[0];
4323 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
4324 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
4325 ctx
.abi
.load_ubo
= radv_load_ubo
;
4326 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
4327 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
4328 ctx
.abi
.load_resource
= radv_load_resource
;
4329 ctx
.abi
.clamp_shadow_reference
= false;
4330 ctx
.abi
.robust_buffer_access
= options
->robust_buffer_access
;
4332 bool is_ngg
= is_pre_gs_stage(shaders
[0]->info
.stage
) && ctx
.options
->key
.vs_common_out
.as_ngg
;
4333 if (shader_count
>= 2 || is_ngg
)
4334 ac_init_exec_full_mask(&ctx
.ac
);
4336 if (options
->has_ls_vgpr_init_bug
&&
4337 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
4338 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
4340 for(int i
= 0; i
< shader_count
; ++i
) {
4341 ctx
.stage
= shaders
[i
]->info
.stage
;
4342 ctx
.output_mask
= 0;
4344 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4345 for (int i
= 0; i
< 4; i
++) {
4346 ctx
.gs_next_vertex
[i
] =
4347 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4349 if (ctx
.options
->key
.vs_common_out
.as_ngg
) {
4350 for (unsigned i
= 0; i
< 4; ++i
) {
4351 ctx
.gs_curprim_verts
[i
] =
4352 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4353 ctx
.gs_generated_prims
[i
] =
4354 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4357 /* TODO: streamout */
4359 LLVMTypeRef ai32
= LLVMArrayType(ctx
.ac
.i32
, 8);
4360 ctx
.gs_ngg_scratch
=
4361 LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4362 ai32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4363 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(ai32
));
4364 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4366 ctx
.gs_ngg_emit
= LLVMBuildIntToPtr(ctx
.ac
.builder
, ctx
.ac
.i32_0
,
4367 LLVMPointerType(LLVMArrayType(ctx
.ac
.i32
, 0), AC_ADDR_SPACE_LDS
),
4371 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
4372 ctx
.gs_output_prim
= shaders
[i
]->info
.gs
.output_primitive
;
4373 ctx
.abi
.load_inputs
= load_gs_input
;
4374 ctx
.abi
.emit_primitive
= visit_end_primitive
;
4375 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4376 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
4377 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
4378 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
4379 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4380 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
4381 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
4382 if (shader_count
== 1)
4383 ctx
.tcs_num_inputs
= ctx
.options
->key
.tcs
.num_inputs
;
4385 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->info
.vs
.ls_outputs_written
);
4386 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
4387 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4388 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
4389 ctx
.abi
.load_tess_varyings
= load_tes_input
;
4390 ctx
.abi
.load_tess_coord
= load_tess_coord
;
4391 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4392 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
4393 ctx
.tcs_num_patches
= ctx
.options
->key
.tes
.num_patches
;
4394 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
4395 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
4396 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
4397 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
4398 ctx
.abi
.load_sample_position
= load_sample_position
;
4399 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
4400 ctx
.abi
.emit_kill
= radv_emit_kill
;
4403 if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&&
4404 ctx
.options
->key
.vs_common_out
.as_ngg
&&
4405 ctx
.options
->key
.vs_common_out
.export_prim_id
) {
4406 declare_esgs_ring(&ctx
);
4409 bool nested_barrier
= false;
4412 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4413 ctx
.options
->key
.vs_common_out
.as_ngg
) {
4414 gfx10_ngg_gs_emit_prologue(&ctx
);
4415 nested_barrier
= false;
4417 nested_barrier
= true;
4421 if (nested_barrier
) {
4422 /* Execute a barrier before the second shader in
4425 * Execute the barrier inside the conditional block,
4426 * so that empty waves can jump directly to s_endpgm,
4427 * which will also signal the barrier.
4429 * This is possible in gfx9, because an empty wave
4430 * for the second shader does not participate in
4431 * the epilogue. With NGG, empty waves may still
4432 * be required to export data (e.g. GS output vertices),
4433 * so we cannot let them exit early.
4435 * If the shader is TCS and the TCS epilog is present
4436 * and contains a barrier, it will wait there and then
4439 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
4442 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
4443 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
4445 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4446 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
4447 shaders
[i
]->info
.cull_distance_array_size
> 4;
4448 ctx
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
4449 ctx
.max_gsvs_emit_size
= ctx
.gsvs_vertex_size
*
4450 shaders
[i
]->info
.gs
.vertices_out
;
4453 ac_setup_rings(&ctx
);
4455 LLVMBasicBlockRef merge_block
;
4456 if (shader_count
>= 2 || is_ngg
) {
4457 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
4458 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4459 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4461 LLVMValueRef count
= ac_unpack_param(&ctx
.ac
, ctx
.merged_wave_info
, 8 * i
, 8);
4462 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
4463 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
4464 thread_id
, count
, "");
4465 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
4467 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
4470 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
4471 prepare_interp_optimize(&ctx
, shaders
[i
]);
4472 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
4473 handle_vs_inputs(&ctx
, shaders
[i
]);
4474 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
4475 prepare_gs_input_vgprs(&ctx
);
4477 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
4479 if (shader_count
>= 2 || is_ngg
) {
4480 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
4481 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
4484 /* This needs to be outside the if wrapping the shader body, as sometimes
4485 * the HW generates waves with 0 es/vs threads. */
4486 if (is_pre_gs_stage(shaders
[i
]->info
.stage
) &&
4487 ctx
.options
->key
.vs_common_out
.as_ngg
&&
4488 i
== shader_count
- 1) {
4489 handle_ngg_outputs_post(&ctx
);
4490 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4491 ctx
.options
->key
.vs_common_out
.as_ngg
) {
4492 gfx10_ngg_gs_emit_epilogue_2(&ctx
);
4495 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4496 shader_info
->gs
.gsvs_vertex_size
= ctx
.gsvs_vertex_size
;
4497 shader_info
->gs
.max_gsvs_emit_size
= ctx
.max_gsvs_emit_size
;
4498 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4499 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
4500 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
4504 LLVMBuildRetVoid(ctx
.ac
.builder
);
4506 if (options
->dump_preoptir
) {
4507 fprintf(stderr
, "%s LLVM IR:\n\n",
4508 radv_get_shader_name(shader_info
,
4509 shaders
[shader_count
- 1]->info
.stage
));
4510 ac_dump_module(ctx
.ac
.module
);
4511 fprintf(stderr
, "\n");
4514 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
4516 if (shader_count
== 1)
4517 ac_nir_eliminate_const_vs_outputs(&ctx
);
4519 if (options
->dump_shader
) {
4520 ctx
.shader_info
->private_mem_vgprs
=
4521 ac_count_scratch_private_memory(ctx
.main_function
);
4524 return ctx
.ac
.module
;
4527 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
4529 unsigned *retval
= (unsigned *)context
;
4530 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
4531 char *description
= LLVMGetDiagInfoDescription(di
);
4533 if (severity
== LLVMDSError
) {
4535 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
4539 LLVMDisposeMessage(description
);
4542 static unsigned radv_llvm_compile(LLVMModuleRef M
,
4543 char **pelf_buffer
, size_t *pelf_size
,
4544 struct ac_llvm_compiler
*ac_llvm
)
4546 unsigned retval
= 0;
4547 LLVMContextRef llvm_ctx
;
4549 /* Setup Diagnostic Handler*/
4550 llvm_ctx
= LLVMGetModuleContext(M
);
4552 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
4556 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
4561 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
4562 LLVMModuleRef llvm_module
,
4563 struct radv_shader_binary
**rbinary
,
4564 struct radv_shader_variant_info
*shader_info
,
4565 gl_shader_stage stage
,
4567 const struct radv_nir_compiler_options
*options
)
4569 char *elf_buffer
= NULL
;
4570 size_t elf_size
= 0;
4571 char *llvm_ir_string
= NULL
;
4573 if (options
->dump_shader
) {
4574 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
4575 ac_dump_module(llvm_module
);
4576 fprintf(stderr
, "\n");
4579 if (options
->record_llvm_ir
) {
4580 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
4581 llvm_ir_string
= strdup(llvm_ir
);
4582 LLVMDisposeMessage(llvm_ir
);
4585 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
4587 fprintf(stderr
, "compile failed\n");
4590 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
4591 LLVMDisposeModule(llvm_module
);
4592 LLVMContextDispose(ctx
);
4594 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
4595 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
4596 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
4597 memcpy(rbin
->data
, elf_buffer
, elf_size
);
4599 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
4601 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
4602 rbin
->base
.stage
= stage
;
4603 rbin
->base
.total_size
= alloc_size
;
4604 rbin
->elf_size
= elf_size
;
4605 rbin
->llvm_ir_size
= llvm_ir_size
;
4606 *rbinary
= &rbin
->base
;
4608 free(llvm_ir_string
);
4613 ac_fill_shader_info(struct radv_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct radv_nir_compiler_options
*options
)
4615 switch (nir
->info
.stage
) {
4616 case MESA_SHADER_COMPUTE
:
4617 for (int i
= 0; i
< 3; ++i
)
4618 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
4620 case MESA_SHADER_FRAGMENT
:
4621 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
4622 shader_info
->fs
.post_depth_coverage
= nir
->info
.fs
.post_depth_coverage
;
4624 case MESA_SHADER_GEOMETRY
:
4625 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
4626 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
4627 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
4628 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
4630 case MESA_SHADER_TESS_EVAL
:
4631 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
4632 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
4633 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
4634 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
4635 shader_info
->tes
.as_es
= options
->key
.vs_common_out
.as_es
;
4636 shader_info
->tes
.export_prim_id
= options
->key
.vs_common_out
.export_prim_id
;
4637 shader_info
->is_ngg
= options
->key
.vs_common_out
.as_ngg
;
4639 case MESA_SHADER_TESS_CTRL
:
4640 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
4642 case MESA_SHADER_VERTEX
:
4643 shader_info
->vs
.as_es
= options
->key
.vs_common_out
.as_es
;
4644 shader_info
->vs
.as_ls
= options
->key
.vs_common_out
.as_ls
;
4645 shader_info
->vs
.export_prim_id
= options
->key
.vs_common_out
.export_prim_id
;
4646 shader_info
->is_ngg
= options
->key
.vs_common_out
.as_ngg
;
4654 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
4655 struct radv_shader_binary
**rbinary
,
4656 struct radv_shader_variant_info
*shader_info
,
4657 struct nir_shader
*const *nir
,
4659 const struct radv_nir_compiler_options
*options
)
4662 LLVMModuleRef llvm_module
;
4664 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, shader_info
,
4667 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
, shader_info
,
4668 nir
[nir_count
- 1]->info
.stage
,
4669 radv_get_shader_name(shader_info
,
4670 nir
[nir_count
- 1]->info
.stage
),
4673 for (int i
= 0; i
< nir_count
; ++i
)
4674 ac_fill_shader_info(shader_info
, nir
[i
], options
);
4676 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4677 if (options
->chip_class
>= GFX9
) {
4678 if (nir_count
== 2 &&
4679 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4680 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
4683 shader_info
->info
.wave_size
= options
->wave_size
;
4687 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
4689 LLVMValueRef vtx_offset
=
4690 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
4691 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4692 LLVMValueRef stream_id
;
4694 /* Fetch the vertex stream ID. */
4695 if (ctx
->shader_info
->info
.so
.num_outputs
) {
4697 ac_unpack_param(&ctx
->ac
, ctx
->streamout_config
, 24, 2);
4699 stream_id
= ctx
->ac
.i32_0
;
4702 LLVMBasicBlockRef end_bb
;
4703 LLVMValueRef switch_inst
;
4705 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
4706 ctx
->main_function
, "end");
4707 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
4709 for (unsigned stream
= 0; stream
< 4; stream
++) {
4710 unsigned num_components
=
4711 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
4712 LLVMBasicBlockRef bb
;
4715 if (!num_components
)
4718 if (stream
> 0 && !ctx
->shader_info
->info
.so
.num_outputs
)
4721 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
4722 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
4723 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
4726 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4727 unsigned output_usage_mask
=
4728 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
4729 unsigned output_stream
=
4730 ctx
->shader_info
->info
.gs
.output_streams
[i
];
4731 int length
= util_last_bit(output_usage_mask
);
4733 if (!(ctx
->output_mask
& (1ull << i
)) ||
4734 output_stream
!= stream
)
4737 for (unsigned j
= 0; j
< length
; j
++) {
4738 LLVMValueRef value
, soffset
;
4740 if (!(output_usage_mask
& (1 << j
)))
4743 soffset
= LLVMConstInt(ctx
->ac
.i32
,
4745 ctx
->gs_max_out_vertices
* 16 * 4, false);
4749 value
= ac_build_buffer_load(&ctx
->ac
,
4752 vtx_offset
, soffset
,
4753 0, ac_glc
| ac_slc
, true, false);
4755 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4756 if (ac_get_type_size(type
) == 2) {
4757 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
4758 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
4761 LLVMBuildStore(ctx
->ac
.builder
,
4762 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4766 if (ctx
->shader_info
->info
.so
.num_outputs
)
4767 radv_emit_streamout(ctx
, stream
);
4770 handle_vs_outputs_post(ctx
, false, true,
4771 &ctx
->shader_info
->vs
.outinfo
);
4774 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
4777 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
4781 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
4782 struct nir_shader
*geom_shader
,
4783 struct radv_shader_binary
**rbinary
,
4784 struct radv_shader_variant_info
*shader_info
,
4785 const struct radv_nir_compiler_options
*options
)
4787 struct radv_shader_context ctx
= {0};
4788 ctx
.options
= options
;
4789 ctx
.shader_info
= shader_info
;
4791 enum ac_float_mode float_mode
=
4792 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
4793 AC_FLOAT_MODE_DEFAULT
;
4795 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, options
->chip_class
,
4796 options
->family
, float_mode
, 64, 64);
4797 ctx
.context
= ctx
.ac
.context
;
4799 ctx
.is_gs_copy_shader
= true;
4800 ctx
.stage
= MESA_SHADER_VERTEX
;
4802 radv_nir_shader_info_pass(geom_shader
, options
, &shader_info
->info
);
4804 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
4806 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
4807 ac_setup_rings(&ctx
);
4809 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
4810 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
4811 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
4812 variable
, MESA_SHADER_VERTEX
);
4815 ac_gs_copy_shader_emit(&ctx
);
4817 LLVMBuildRetVoid(ctx
.ac
.builder
);
4819 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
4821 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
, shader_info
,
4822 MESA_SHADER_VERTEX
, "GS Copy Shader", options
);
4823 (*rbinary
)->is_gs_copy_shader
= true;