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ac/nir: move ac_shader_variant_info and friends to radv folder
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "nir/nir.h"
31
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35
36 #include "sid.h"
37 #include "gfx9d.h"
38 #include "ac_binary.h"
39 #include "ac_llvm_util.h"
40 #include "ac_llvm_build.h"
41 #include "ac_shader_abi.h"
42 #include "ac_shader_util.h"
43 #include "ac_exp_param.h"
44
45 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
46
47 struct radv_shader_context {
48 struct ac_llvm_context ac;
49 const struct ac_nir_compiler_options *options;
50 struct radv_shader_variant_info *shader_info;
51 struct ac_shader_abi abi;
52
53 unsigned max_workgroup_size;
54 LLVMContextRef context;
55 LLVMValueRef main_function;
56
57 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
58 LLVMValueRef ring_offsets;
59
60 LLVMValueRef vertex_buffers;
61 LLVMValueRef rel_auto_id;
62 LLVMValueRef vs_prim_id;
63 LLVMValueRef ls_out_layout;
64 LLVMValueRef es2gs_offset;
65
66 LLVMValueRef tcs_offchip_layout;
67 LLVMValueRef tcs_out_offsets;
68 LLVMValueRef tcs_out_layout;
69 LLVMValueRef tcs_in_layout;
70 LLVMValueRef oc_lds;
71 LLVMValueRef merged_wave_info;
72 LLVMValueRef tess_factor_offset;
73 LLVMValueRef tes_rel_patch_id;
74 LLVMValueRef tes_u;
75 LLVMValueRef tes_v;
76
77 LLVMValueRef gsvs_ring_stride;
78 LLVMValueRef gsvs_num_entries;
79 LLVMValueRef gs2vs_offset;
80 LLVMValueRef gs_wave_id;
81 LLVMValueRef gs_vtx_offset[6];
82
83 LLVMValueRef esgs_ring;
84 LLVMValueRef gsvs_ring;
85 LLVMValueRef hs_ring_tess_offchip;
86 LLVMValueRef hs_ring_tess_factor;
87
88 LLVMValueRef sample_pos_offset;
89 LLVMValueRef persp_sample, persp_center, persp_centroid;
90 LLVMValueRef linear_sample, linear_center, linear_centroid;
91
92 gl_shader_stage stage;
93
94 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
95
96 uint64_t input_mask;
97 uint64_t output_mask;
98 uint8_t num_output_clips;
99 uint8_t num_output_culls;
100
101 bool is_gs_copy_shader;
102 LLVMValueRef gs_next_vertex;
103 unsigned gs_max_out_vertices;
104
105 unsigned tes_primitive_mode;
106 uint64_t tess_outputs_written;
107 uint64_t tess_patch_outputs_written;
108
109 uint32_t tcs_patch_outputs_read;
110 uint64_t tcs_outputs_read;
111 uint32_t tcs_vertices_per_patch;
112 };
113
114 enum radeon_llvm_calling_convention {
115 RADEON_LLVM_AMDGPU_VS = 87,
116 RADEON_LLVM_AMDGPU_GS = 88,
117 RADEON_LLVM_AMDGPU_PS = 89,
118 RADEON_LLVM_AMDGPU_CS = 90,
119 RADEON_LLVM_AMDGPU_HS = 93,
120 };
121
122 static inline struct radv_shader_context *
123 radv_shader_context_from_abi(struct ac_shader_abi *abi)
124 {
125 struct radv_shader_context *ctx = NULL;
126 return container_of(abi, ctx, abi);
127 }
128
129 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
130 {
131 switch (ctx->stage) {
132 case MESA_SHADER_TESS_CTRL:
133 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
134 case MESA_SHADER_TESS_EVAL:
135 return ctx->tes_rel_patch_id;
136 break;
137 default:
138 unreachable("Illegal stage");
139 }
140 }
141
142 /* Tessellation shaders pass outputs to the next shader using LDS.
143 *
144 * LS outputs = TCS inputs
145 * TCS outputs = TES inputs
146 *
147 * The LDS layout is:
148 * - TCS inputs for patch 0
149 * - TCS inputs for patch 1
150 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
151 * - ...
152 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
153 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
154 * - TCS outputs for patch 1
155 * - Per-patch TCS outputs for patch 1
156 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
157 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
158 * - ...
159 *
160 * All three shaders VS(LS), TCS, TES share the same LDS space.
161 */
162 static LLVMValueRef
163 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
164 {
165 if (ctx->stage == MESA_SHADER_VERTEX)
166 return ac_unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
167 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
168 return ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
169 else {
170 assert(0);
171 return NULL;
172 }
173 }
174
175 static LLVMValueRef
176 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
177 {
178 return ac_unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
179 }
180
181 static LLVMValueRef
182 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
183 {
184 return ac_unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
185 }
186
187 static LLVMValueRef
188 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
189 {
190 return LLVMBuildMul(ctx->ac.builder,
191 ac_unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
192 LLVMConstInt(ctx->ac.i32, 4, false), "");
193 }
194
195 static LLVMValueRef
196 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
197 {
198 return LLVMBuildMul(ctx->ac.builder,
199 ac_unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
200 LLVMConstInt(ctx->ac.i32, 4, false), "");
201 }
202
203 static LLVMValueRef
204 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
205 {
206 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
207 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
208
209 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
210 }
211
212 static LLVMValueRef
213 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
214 {
215 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
216 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
217 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
218
219 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
220 LLVMBuildMul(ctx->ac.builder, patch_stride,
221 rel_patch_id, ""),
222 "");
223 }
224
225 static LLVMValueRef
226 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
227 {
228 LLVMValueRef patch0_patch_data_offset =
229 get_tcs_out_patch0_patch_data_offset(ctx);
230 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
231 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
232
233 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
234 LLVMBuildMul(ctx->ac.builder, patch_stride,
235 rel_patch_id, ""),
236 "");
237 }
238
239 #define MAX_ARGS 23
240 struct arg_info {
241 LLVMTypeRef types[MAX_ARGS];
242 LLVMValueRef *assign[MAX_ARGS];
243 unsigned array_params_mask;
244 uint8_t count;
245 uint8_t sgpr_count;
246 uint8_t num_sgprs_used;
247 uint8_t num_vgprs_used;
248 };
249
250 enum ac_arg_regfile {
251 ARG_SGPR,
252 ARG_VGPR,
253 };
254
255 static void
256 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
257 LLVMValueRef *param_ptr)
258 {
259 assert(info->count < MAX_ARGS);
260
261 info->assign[info->count] = param_ptr;
262 info->types[info->count] = type;
263 info->count++;
264
265 if (regfile == ARG_SGPR) {
266 info->num_sgprs_used += ac_get_type_size(type) / 4;
267 info->sgpr_count++;
268 } else {
269 assert(regfile == ARG_VGPR);
270 info->num_vgprs_used += ac_get_type_size(type) / 4;
271 }
272 }
273
274 static inline void
275 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
276 {
277 info->array_params_mask |= (1 << info->count);
278 add_arg(info, ARG_SGPR, type, param_ptr);
279 }
280
281 static void assign_arguments(LLVMValueRef main_function,
282 struct arg_info *info)
283 {
284 unsigned i;
285 for (i = 0; i < info->count; i++) {
286 if (info->assign[i])
287 *info->assign[i] = LLVMGetParam(main_function, i);
288 }
289 }
290
291 static LLVMValueRef
292 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
293 LLVMBuilderRef builder, LLVMTypeRef *return_types,
294 unsigned num_return_elems,
295 struct arg_info *args,
296 unsigned max_workgroup_size,
297 bool unsafe_math)
298 {
299 LLVMTypeRef main_function_type, ret_type;
300 LLVMBasicBlockRef main_function_body;
301
302 if (num_return_elems)
303 ret_type = LLVMStructTypeInContext(ctx, return_types,
304 num_return_elems, true);
305 else
306 ret_type = LLVMVoidTypeInContext(ctx);
307
308 /* Setup the function */
309 main_function_type =
310 LLVMFunctionType(ret_type, args->types, args->count, 0);
311 LLVMValueRef main_function =
312 LLVMAddFunction(module, "main", main_function_type);
313 main_function_body =
314 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
315 LLVMPositionBuilderAtEnd(builder, main_function_body);
316
317 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
318 for (unsigned i = 0; i < args->sgpr_count; ++i) {
319 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
320
321 if (args->array_params_mask & (1 << i)) {
322 LLVMValueRef P = LLVMGetParam(main_function, i);
323 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
324 ac_add_attr_dereferenceable(P, UINT64_MAX);
325 }
326 }
327
328 if (max_workgroup_size) {
329 ac_llvm_add_target_dep_function_attr(main_function,
330 "amdgpu-max-work-group-size",
331 max_workgroup_size);
332 }
333 if (unsafe_math) {
334 /* These were copied from some LLVM test. */
335 LLVMAddTargetDependentFunctionAttr(main_function,
336 "less-precise-fpmad",
337 "true");
338 LLVMAddTargetDependentFunctionAttr(main_function,
339 "no-infs-fp-math",
340 "true");
341 LLVMAddTargetDependentFunctionAttr(main_function,
342 "no-nans-fp-math",
343 "true");
344 LLVMAddTargetDependentFunctionAttr(main_function,
345 "unsafe-fp-math",
346 "true");
347 LLVMAddTargetDependentFunctionAttr(main_function,
348 "no-signed-zeros-fp-math",
349 "true");
350 }
351 return main_function;
352 }
353
354
355 static void
356 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
357 uint32_t indirect_offset)
358 {
359 ud_info->sgpr_idx = *sgpr_idx;
360 ud_info->num_sgprs = num_sgprs;
361 ud_info->indirect = indirect_offset > 0;
362 ud_info->indirect_offset = indirect_offset;
363 *sgpr_idx += num_sgprs;
364 }
365
366 static void
367 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
368 uint8_t num_sgprs)
369 {
370 struct radv_userdata_info *ud_info =
371 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
372 assert(ud_info);
373
374 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
375 }
376
377 static void
378 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
379 uint32_t indirect_offset)
380 {
381 struct radv_userdata_info *ud_info =
382 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
383 assert(ud_info);
384
385 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
386 }
387
388 struct user_sgpr_info {
389 bool need_ring_offsets;
390 uint8_t sgpr_count;
391 bool indirect_all_descriptor_sets;
392 };
393
394 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
395 gl_shader_stage stage)
396 {
397 switch (stage) {
398 case MESA_SHADER_VERTEX:
399 if (ctx->shader_info->info.needs_multiview_view_index ||
400 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
401 return true;
402 break;
403 case MESA_SHADER_TESS_EVAL:
404 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
405 return true;
406 break;
407 case MESA_SHADER_GEOMETRY:
408 case MESA_SHADER_TESS_CTRL:
409 if (ctx->shader_info->info.needs_multiview_view_index)
410 return true;
411 break;
412 default:
413 break;
414 }
415 return false;
416 }
417
418 static uint8_t
419 count_vs_user_sgprs(struct radv_shader_context *ctx)
420 {
421 uint8_t count = 0;
422
423 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
424 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
425
426 return count;
427 }
428
429 static void allocate_user_sgprs(struct radv_shader_context *ctx,
430 gl_shader_stage stage,
431 bool has_previous_stage,
432 gl_shader_stage previous_stage,
433 bool needs_view_index,
434 struct user_sgpr_info *user_sgpr_info)
435 {
436 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
437
438 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
439 if (stage == MESA_SHADER_GEOMETRY ||
440 stage == MESA_SHADER_VERTEX ||
441 stage == MESA_SHADER_TESS_CTRL ||
442 stage == MESA_SHADER_TESS_EVAL ||
443 ctx->is_gs_copy_shader)
444 user_sgpr_info->need_ring_offsets = true;
445
446 if (stage == MESA_SHADER_FRAGMENT &&
447 ctx->shader_info->info.ps.needs_sample_positions)
448 user_sgpr_info->need_ring_offsets = true;
449
450 /* 2 user sgprs will nearly always be allocated for scratch/rings */
451 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
452 user_sgpr_info->sgpr_count += 2;
453 }
454
455 switch (stage) {
456 case MESA_SHADER_COMPUTE:
457 if (ctx->shader_info->info.cs.uses_grid_size)
458 user_sgpr_info->sgpr_count += 3;
459 break;
460 case MESA_SHADER_FRAGMENT:
461 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
462 break;
463 case MESA_SHADER_VERTEX:
464 if (!ctx->is_gs_copy_shader)
465 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
466 if (ctx->options->key.vs.as_ls)
467 user_sgpr_info->sgpr_count++;
468 break;
469 case MESA_SHADER_TESS_CTRL:
470 if (has_previous_stage) {
471 if (previous_stage == MESA_SHADER_VERTEX)
472 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
473 user_sgpr_info->sgpr_count++;
474 }
475 user_sgpr_info->sgpr_count += 4;
476 break;
477 case MESA_SHADER_TESS_EVAL:
478 user_sgpr_info->sgpr_count += 1;
479 break;
480 case MESA_SHADER_GEOMETRY:
481 if (has_previous_stage) {
482 if (previous_stage == MESA_SHADER_VERTEX) {
483 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
484 } else {
485 user_sgpr_info->sgpr_count++;
486 }
487 }
488 user_sgpr_info->sgpr_count += 2;
489 break;
490 default:
491 break;
492 }
493
494 if (needs_view_index)
495 user_sgpr_info->sgpr_count++;
496
497 if (ctx->shader_info->info.loads_push_constants)
498 user_sgpr_info->sgpr_count += 2;
499
500 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
501 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
502
503 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
504 user_sgpr_info->sgpr_count += 2;
505 user_sgpr_info->indirect_all_descriptor_sets = true;
506 } else {
507 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
508 }
509 }
510
511 static void
512 declare_global_input_sgprs(struct radv_shader_context *ctx,
513 gl_shader_stage stage,
514 bool has_previous_stage,
515 gl_shader_stage previous_stage,
516 const struct user_sgpr_info *user_sgpr_info,
517 struct arg_info *args,
518 LLVMValueRef *desc_sets)
519 {
520 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
521 unsigned num_sets = ctx->options->layout ?
522 ctx->options->layout->num_sets : 0;
523 unsigned stage_mask = 1 << stage;
524
525 if (has_previous_stage)
526 stage_mask |= 1 << previous_stage;
527
528 /* 1 for each descriptor set */
529 if (!user_sgpr_info->indirect_all_descriptor_sets) {
530 for (unsigned i = 0; i < num_sets; ++i) {
531 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
532 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
533 add_array_arg(args, type,
534 &ctx->descriptor_sets[i]);
535 }
536 }
537 } else {
538 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
539 }
540
541 if (ctx->shader_info->info.loads_push_constants) {
542 /* 1 for push constants and dynamic descriptors */
543 add_array_arg(args, type, &ctx->abi.push_constants);
544 }
545 }
546
547 static void
548 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
549 gl_shader_stage stage,
550 bool has_previous_stage,
551 gl_shader_stage previous_stage,
552 struct arg_info *args)
553 {
554 if (!ctx->is_gs_copy_shader &&
555 (stage == MESA_SHADER_VERTEX ||
556 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
557 if (ctx->shader_info->info.vs.has_vertex_buffers) {
558 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
559 &ctx->vertex_buffers);
560 }
561 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
562 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
563 if (ctx->shader_info->info.vs.needs_draw_id) {
564 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
565 }
566 }
567 }
568
569 static void
570 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
571 {
572 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
573 if (!ctx->is_gs_copy_shader) {
574 if (ctx->options->key.vs.as_ls) {
575 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
576 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
577 } else {
578 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
579 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
580 }
581 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
582 }
583 }
584
585 static void
586 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
587 {
588 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
589 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
590 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
591 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
592 }
593
594 static void
595 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
596 bool has_previous_stage, gl_shader_stage previous_stage,
597 const struct user_sgpr_info *user_sgpr_info,
598 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
599 {
600 unsigned num_sets = ctx->options->layout ?
601 ctx->options->layout->num_sets : 0;
602 unsigned stage_mask = 1 << stage;
603
604 if (has_previous_stage)
605 stage_mask |= 1 << previous_stage;
606
607 if (!user_sgpr_info->indirect_all_descriptor_sets) {
608 for (unsigned i = 0; i < num_sets; ++i) {
609 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
610 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
611 set_loc_desc(ctx, i, user_sgpr_idx, 0);
612 } else
613 ctx->descriptor_sets[i] = NULL;
614 }
615 } else {
616 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
617 user_sgpr_idx, 2);
618
619 for (unsigned i = 0; i < num_sets; ++i) {
620 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
621 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
622 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
623 ctx->descriptor_sets[i] =
624 ac_build_load_to_sgpr(&ctx->ac,
625 desc_sets,
626 LLVMConstInt(ctx->ac.i32, i, false));
627
628 } else
629 ctx->descriptor_sets[i] = NULL;
630 }
631 ctx->shader_info->need_indirect_descriptor_sets = true;
632 }
633
634 if (ctx->shader_info->info.loads_push_constants) {
635 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
636 }
637 }
638
639 static void
640 set_vs_specific_input_locs(struct radv_shader_context *ctx,
641 gl_shader_stage stage, bool has_previous_stage,
642 gl_shader_stage previous_stage,
643 uint8_t *user_sgpr_idx)
644 {
645 if (!ctx->is_gs_copy_shader &&
646 (stage == MESA_SHADER_VERTEX ||
647 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
648 if (ctx->shader_info->info.vs.has_vertex_buffers) {
649 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
650 user_sgpr_idx, 2);
651 }
652
653 unsigned vs_num = 2;
654 if (ctx->shader_info->info.vs.needs_draw_id)
655 vs_num++;
656
657 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
658 user_sgpr_idx, vs_num);
659 }
660 }
661
662 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
663 {
664 /* handle patch indices separate */
665 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
666 return 0;
667 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
668 return 1;
669 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
670 return 2 + (slot - VARYING_SLOT_PATCH0);
671
672 if (slot == VARYING_SLOT_POS)
673 return 0;
674 if (slot == VARYING_SLOT_PSIZ)
675 return 1;
676 if (slot == VARYING_SLOT_CLIP_DIST0)
677 return 2;
678 /* 3 is reserved for clip dist as well */
679 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
680 return 4 + (slot - VARYING_SLOT_VAR0);
681 unreachable("illegal slot in get unique index\n");
682 }
683
684 static void set_llvm_calling_convention(LLVMValueRef func,
685 gl_shader_stage stage)
686 {
687 enum radeon_llvm_calling_convention calling_conv;
688
689 switch (stage) {
690 case MESA_SHADER_VERTEX:
691 case MESA_SHADER_TESS_EVAL:
692 calling_conv = RADEON_LLVM_AMDGPU_VS;
693 break;
694 case MESA_SHADER_GEOMETRY:
695 calling_conv = RADEON_LLVM_AMDGPU_GS;
696 break;
697 case MESA_SHADER_TESS_CTRL:
698 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
699 break;
700 case MESA_SHADER_FRAGMENT:
701 calling_conv = RADEON_LLVM_AMDGPU_PS;
702 break;
703 case MESA_SHADER_COMPUTE:
704 calling_conv = RADEON_LLVM_AMDGPU_CS;
705 break;
706 default:
707 unreachable("Unhandle shader type");
708 }
709
710 LLVMSetFunctionCallConv(func, calling_conv);
711 }
712
713 static void create_function(struct radv_shader_context *ctx,
714 gl_shader_stage stage,
715 bool has_previous_stage,
716 gl_shader_stage previous_stage)
717 {
718 uint8_t user_sgpr_idx;
719 struct user_sgpr_info user_sgpr_info;
720 struct arg_info args = {};
721 LLVMValueRef desc_sets;
722 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
723 allocate_user_sgprs(ctx, stage, has_previous_stage,
724 previous_stage, needs_view_index, &user_sgpr_info);
725
726 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
727 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
728 &ctx->ring_offsets);
729 }
730
731 switch (stage) {
732 case MESA_SHADER_COMPUTE:
733 declare_global_input_sgprs(ctx, stage, has_previous_stage,
734 previous_stage, &user_sgpr_info,
735 &args, &desc_sets);
736
737 if (ctx->shader_info->info.cs.uses_grid_size) {
738 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
739 &ctx->abi.num_work_groups);
740 }
741
742 for (int i = 0; i < 3; i++) {
743 ctx->abi.workgroup_ids[i] = NULL;
744 if (ctx->shader_info->info.cs.uses_block_id[i]) {
745 add_arg(&args, ARG_SGPR, ctx->ac.i32,
746 &ctx->abi.workgroup_ids[i]);
747 }
748 }
749
750 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
751 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
752 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
753 &ctx->abi.local_invocation_ids);
754 break;
755 case MESA_SHADER_VERTEX:
756 declare_global_input_sgprs(ctx, stage, has_previous_stage,
757 previous_stage, &user_sgpr_info,
758 &args, &desc_sets);
759 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
760 previous_stage, &args);
761
762 if (needs_view_index)
763 add_arg(&args, ARG_SGPR, ctx->ac.i32,
764 &ctx->abi.view_index);
765 if (ctx->options->key.vs.as_es)
766 add_arg(&args, ARG_SGPR, ctx->ac.i32,
767 &ctx->es2gs_offset);
768 else if (ctx->options->key.vs.as_ls)
769 add_arg(&args, ARG_SGPR, ctx->ac.i32,
770 &ctx->ls_out_layout);
771
772 declare_vs_input_vgprs(ctx, &args);
773 break;
774 case MESA_SHADER_TESS_CTRL:
775 if (has_previous_stage) {
776 // First 6 system regs
777 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
778 add_arg(&args, ARG_SGPR, ctx->ac.i32,
779 &ctx->merged_wave_info);
780 add_arg(&args, ARG_SGPR, ctx->ac.i32,
781 &ctx->tess_factor_offset);
782
783 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
784 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
785 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
786
787 declare_global_input_sgprs(ctx, stage,
788 has_previous_stage,
789 previous_stage,
790 &user_sgpr_info, &args,
791 &desc_sets);
792 declare_vs_specific_input_sgprs(ctx, stage,
793 has_previous_stage,
794 previous_stage, &args);
795
796 add_arg(&args, ARG_SGPR, ctx->ac.i32,
797 &ctx->ls_out_layout);
798
799 add_arg(&args, ARG_SGPR, ctx->ac.i32,
800 &ctx->tcs_offchip_layout);
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->tcs_out_offsets);
803 add_arg(&args, ARG_SGPR, ctx->ac.i32,
804 &ctx->tcs_out_layout);
805 add_arg(&args, ARG_SGPR, ctx->ac.i32,
806 &ctx->tcs_in_layout);
807 if (needs_view_index)
808 add_arg(&args, ARG_SGPR, ctx->ac.i32,
809 &ctx->abi.view_index);
810
811 add_arg(&args, ARG_VGPR, ctx->ac.i32,
812 &ctx->abi.tcs_patch_id);
813 add_arg(&args, ARG_VGPR, ctx->ac.i32,
814 &ctx->abi.tcs_rel_ids);
815
816 declare_vs_input_vgprs(ctx, &args);
817 } else {
818 declare_global_input_sgprs(ctx, stage,
819 has_previous_stage,
820 previous_stage,
821 &user_sgpr_info, &args,
822 &desc_sets);
823
824 add_arg(&args, ARG_SGPR, ctx->ac.i32,
825 &ctx->tcs_offchip_layout);
826 add_arg(&args, ARG_SGPR, ctx->ac.i32,
827 &ctx->tcs_out_offsets);
828 add_arg(&args, ARG_SGPR, ctx->ac.i32,
829 &ctx->tcs_out_layout);
830 add_arg(&args, ARG_SGPR, ctx->ac.i32,
831 &ctx->tcs_in_layout);
832 if (needs_view_index)
833 add_arg(&args, ARG_SGPR, ctx->ac.i32,
834 &ctx->abi.view_index);
835
836 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tess_factor_offset);
839 add_arg(&args, ARG_VGPR, ctx->ac.i32,
840 &ctx->abi.tcs_patch_id);
841 add_arg(&args, ARG_VGPR, ctx->ac.i32,
842 &ctx->abi.tcs_rel_ids);
843 }
844 break;
845 case MESA_SHADER_TESS_EVAL:
846 declare_global_input_sgprs(ctx, stage, has_previous_stage,
847 previous_stage, &user_sgpr_info,
848 &args, &desc_sets);
849
850 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
851 if (needs_view_index)
852 add_arg(&args, ARG_SGPR, ctx->ac.i32,
853 &ctx->abi.view_index);
854
855 if (ctx->options->key.tes.as_es) {
856 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
857 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
858 add_arg(&args, ARG_SGPR, ctx->ac.i32,
859 &ctx->es2gs_offset);
860 } else {
861 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
862 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
863 }
864 declare_tes_input_vgprs(ctx, &args);
865 break;
866 case MESA_SHADER_GEOMETRY:
867 if (has_previous_stage) {
868 // First 6 system regs
869 add_arg(&args, ARG_SGPR, ctx->ac.i32,
870 &ctx->gs2vs_offset);
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->merged_wave_info);
873 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
874
875 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
876 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
877 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
878
879 declare_global_input_sgprs(ctx, stage,
880 has_previous_stage,
881 previous_stage,
882 &user_sgpr_info, &args,
883 &desc_sets);
884
885 if (previous_stage == MESA_SHADER_TESS_EVAL) {
886 add_arg(&args, ARG_SGPR, ctx->ac.i32,
887 &ctx->tcs_offchip_layout);
888 } else {
889 declare_vs_specific_input_sgprs(ctx, stage,
890 has_previous_stage,
891 previous_stage,
892 &args);
893 }
894
895 add_arg(&args, ARG_SGPR, ctx->ac.i32,
896 &ctx->gsvs_ring_stride);
897 add_arg(&args, ARG_SGPR, ctx->ac.i32,
898 &ctx->gsvs_num_entries);
899 if (needs_view_index)
900 add_arg(&args, ARG_SGPR, ctx->ac.i32,
901 &ctx->abi.view_index);
902
903 add_arg(&args, ARG_VGPR, ctx->ac.i32,
904 &ctx->gs_vtx_offset[0]);
905 add_arg(&args, ARG_VGPR, ctx->ac.i32,
906 &ctx->gs_vtx_offset[2]);
907 add_arg(&args, ARG_VGPR, ctx->ac.i32,
908 &ctx->abi.gs_prim_id);
909 add_arg(&args, ARG_VGPR, ctx->ac.i32,
910 &ctx->abi.gs_invocation_id);
911 add_arg(&args, ARG_VGPR, ctx->ac.i32,
912 &ctx->gs_vtx_offset[4]);
913
914 if (previous_stage == MESA_SHADER_VERTEX) {
915 declare_vs_input_vgprs(ctx, &args);
916 } else {
917 declare_tes_input_vgprs(ctx, &args);
918 }
919 } else {
920 declare_global_input_sgprs(ctx, stage,
921 has_previous_stage,
922 previous_stage,
923 &user_sgpr_info, &args,
924 &desc_sets);
925
926 add_arg(&args, ARG_SGPR, ctx->ac.i32,
927 &ctx->gsvs_ring_stride);
928 add_arg(&args, ARG_SGPR, ctx->ac.i32,
929 &ctx->gsvs_num_entries);
930 if (needs_view_index)
931 add_arg(&args, ARG_SGPR, ctx->ac.i32,
932 &ctx->abi.view_index);
933
934 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
935 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
936 add_arg(&args, ARG_VGPR, ctx->ac.i32,
937 &ctx->gs_vtx_offset[0]);
938 add_arg(&args, ARG_VGPR, ctx->ac.i32,
939 &ctx->gs_vtx_offset[1]);
940 add_arg(&args, ARG_VGPR, ctx->ac.i32,
941 &ctx->abi.gs_prim_id);
942 add_arg(&args, ARG_VGPR, ctx->ac.i32,
943 &ctx->gs_vtx_offset[2]);
944 add_arg(&args, ARG_VGPR, ctx->ac.i32,
945 &ctx->gs_vtx_offset[3]);
946 add_arg(&args, ARG_VGPR, ctx->ac.i32,
947 &ctx->gs_vtx_offset[4]);
948 add_arg(&args, ARG_VGPR, ctx->ac.i32,
949 &ctx->gs_vtx_offset[5]);
950 add_arg(&args, ARG_VGPR, ctx->ac.i32,
951 &ctx->abi.gs_invocation_id);
952 }
953 break;
954 case MESA_SHADER_FRAGMENT:
955 declare_global_input_sgprs(ctx, stage, has_previous_stage,
956 previous_stage, &user_sgpr_info,
957 &args, &desc_sets);
958
959 if (ctx->shader_info->info.ps.needs_sample_positions)
960 add_arg(&args, ARG_SGPR, ctx->ac.i32,
961 &ctx->sample_pos_offset);
962
963 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
964 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
965 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
966 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
967 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
968 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
969 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
970 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
971 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
972 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
973 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
974 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
975 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
977 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
979 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
980 break;
981 default:
982 unreachable("Shader stage not implemented");
983 }
984
985 ctx->main_function = create_llvm_function(
986 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
987 ctx->max_workgroup_size,
988 ctx->options->unsafe_math);
989 set_llvm_calling_convention(ctx->main_function, stage);
990
991
992 ctx->shader_info->num_input_vgprs = 0;
993 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
994
995 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
996
997 if (ctx->stage != MESA_SHADER_FRAGMENT)
998 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
999
1000 assign_arguments(ctx->main_function, &args);
1001
1002 user_sgpr_idx = 0;
1003
1004 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1005 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1006 &user_sgpr_idx, 2);
1007 if (ctx->options->supports_spill) {
1008 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1009 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1010 NULL, 0, AC_FUNC_ATTR_READNONE);
1011 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1012 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1013 }
1014 }
1015
1016 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1017 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1018 if (has_previous_stage)
1019 user_sgpr_idx = 0;
1020
1021 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1022 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1023
1024 switch (stage) {
1025 case MESA_SHADER_COMPUTE:
1026 if (ctx->shader_info->info.cs.uses_grid_size) {
1027 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1028 &user_sgpr_idx, 3);
1029 }
1030 break;
1031 case MESA_SHADER_VERTEX:
1032 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1033 previous_stage, &user_sgpr_idx);
1034 if (ctx->abi.view_index)
1035 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1036 if (ctx->options->key.vs.as_ls) {
1037 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1038 &user_sgpr_idx, 1);
1039 }
1040 break;
1041 case MESA_SHADER_TESS_CTRL:
1042 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1043 previous_stage, &user_sgpr_idx);
1044 if (has_previous_stage)
1045 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1046 &user_sgpr_idx, 1);
1047 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1048 if (ctx->abi.view_index)
1049 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1050 break;
1051 case MESA_SHADER_TESS_EVAL:
1052 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1053 if (ctx->abi.view_index)
1054 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1055 break;
1056 case MESA_SHADER_GEOMETRY:
1057 if (has_previous_stage) {
1058 if (previous_stage == MESA_SHADER_VERTEX)
1059 set_vs_specific_input_locs(ctx, stage,
1060 has_previous_stage,
1061 previous_stage,
1062 &user_sgpr_idx);
1063 else
1064 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1065 &user_sgpr_idx, 1);
1066 }
1067 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1068 &user_sgpr_idx, 2);
1069 if (ctx->abi.view_index)
1070 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1071 break;
1072 case MESA_SHADER_FRAGMENT:
1073 if (ctx->shader_info->info.ps.needs_sample_positions) {
1074 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1075 &user_sgpr_idx, 1);
1076 }
1077 break;
1078 default:
1079 unreachable("Shader stage not implemented");
1080 }
1081
1082 if (stage == MESA_SHADER_TESS_CTRL ||
1083 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1084 /* GFX9 has the ESGS ring buffer in LDS. */
1085 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1086 ac_declare_lds_as_pointer(&ctx->ac);
1087 }
1088
1089 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1090 }
1091
1092
1093 static LLVMValueRef
1094 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1095 unsigned desc_set, unsigned binding)
1096 {
1097 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1098 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1099 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1100 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1101 unsigned base_offset = layout->binding[binding].offset;
1102 LLVMValueRef offset, stride;
1103
1104 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1105 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1106 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1107 layout->binding[binding].dynamic_offset_offset;
1108 desc_ptr = ctx->abi.push_constants;
1109 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1110 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1111 } else
1112 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1113
1114 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1115 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
1116 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
1117
1118 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1119 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1120 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1121
1122 return desc_ptr;
1123 }
1124
1125
1126 /* The offchip buffer layout for TCS->TES is
1127 *
1128 * - attribute 0 of patch 0 vertex 0
1129 * - attribute 0 of patch 0 vertex 1
1130 * - attribute 0 of patch 0 vertex 2
1131 * ...
1132 * - attribute 0 of patch 1 vertex 0
1133 * - attribute 0 of patch 1 vertex 1
1134 * ...
1135 * - attribute 1 of patch 0 vertex 0
1136 * - attribute 1 of patch 0 vertex 1
1137 * ...
1138 * - per patch attribute 0 of patch 0
1139 * - per patch attribute 0 of patch 1
1140 * ...
1141 *
1142 * Note that every attribute has 4 components.
1143 */
1144 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1145 LLVMValueRef vertex_index,
1146 LLVMValueRef param_index)
1147 {
1148 LLVMValueRef base_addr, vertices_per_patch, num_patches;
1149 LLVMValueRef param_stride, constant16;
1150 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1151
1152 vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1153 num_patches = ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
1154
1155 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1156 if (vertex_index) {
1157 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
1158 vertices_per_patch, "");
1159
1160 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1161 vertex_index, "");
1162
1163 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
1164 num_patches, "");
1165 } else {
1166 base_addr = rel_patch_id;
1167 param_stride = num_patches;
1168 }
1169
1170 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1171 LLVMBuildMul(ctx->ac.builder, param_index,
1172 param_stride, ""), "");
1173
1174 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1175
1176 if (!vertex_index) {
1177 LLVMValueRef patch_data_offset =
1178 ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
1179
1180 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1181 patch_data_offset, "");
1182 }
1183 return base_addr;
1184 }
1185
1186 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1187 unsigned param,
1188 unsigned const_index,
1189 bool is_compact,
1190 LLVMValueRef vertex_index,
1191 LLVMValueRef indir_index)
1192 {
1193 LLVMValueRef param_index;
1194
1195 if (indir_index)
1196 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1197 indir_index, "");
1198 else {
1199 if (const_index && !is_compact)
1200 param += const_index;
1201 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1202 }
1203 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1204 }
1205
1206 static void
1207 mark_tess_output(struct radv_shader_context *ctx,
1208 bool is_patch, uint32_t param)
1209
1210 {
1211 if (is_patch) {
1212 ctx->tess_patch_outputs_written |= (1ull << param);
1213 } else
1214 ctx->tess_outputs_written |= (1ull << param);
1215 }
1216
1217 static LLVMValueRef
1218 get_dw_address(struct radv_shader_context *ctx,
1219 LLVMValueRef dw_addr,
1220 unsigned param,
1221 unsigned const_index,
1222 bool compact_const_index,
1223 LLVMValueRef vertex_index,
1224 LLVMValueRef stride,
1225 LLVMValueRef indir_index)
1226
1227 {
1228
1229 if (vertex_index) {
1230 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1231 LLVMBuildMul(ctx->ac.builder,
1232 vertex_index,
1233 stride, ""), "");
1234 }
1235
1236 if (indir_index)
1237 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1238 LLVMBuildMul(ctx->ac.builder, indir_index,
1239 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1240 else if (const_index && !compact_const_index)
1241 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1242 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1243
1244 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1245 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1246
1247 if (const_index && compact_const_index)
1248 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1249 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1250 return dw_addr;
1251 }
1252
1253 static LLVMValueRef
1254 load_tcs_varyings(struct ac_shader_abi *abi,
1255 LLVMTypeRef type,
1256 LLVMValueRef vertex_index,
1257 LLVMValueRef indir_index,
1258 unsigned const_index,
1259 unsigned location,
1260 unsigned driver_location,
1261 unsigned component,
1262 unsigned num_components,
1263 bool is_patch,
1264 bool is_compact,
1265 bool load_input)
1266 {
1267 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1268 LLVMValueRef dw_addr, stride;
1269 LLVMValueRef value[4], result;
1270 unsigned param = shader_io_get_unique_index(location);
1271
1272 if (load_input) {
1273 stride = ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
1274 dw_addr = get_tcs_in_current_patch_offset(ctx);
1275 } else {
1276 if (!is_patch) {
1277 stride = get_tcs_out_vertex_stride(ctx);
1278 dw_addr = get_tcs_out_current_patch_offset(ctx);
1279 } else {
1280 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1281 stride = NULL;
1282 }
1283 }
1284
1285 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1286 indir_index);
1287
1288 for (unsigned i = 0; i < num_components + component; i++) {
1289 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1290 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1291 ctx->ac.i32_1, "");
1292 }
1293 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1294 return result;
1295 }
1296
1297 static void
1298 store_tcs_output(struct ac_shader_abi *abi,
1299 LLVMValueRef vertex_index,
1300 LLVMValueRef param_index,
1301 unsigned const_index,
1302 unsigned location,
1303 unsigned driver_location,
1304 LLVMValueRef src,
1305 unsigned component,
1306 bool is_patch,
1307 bool is_compact,
1308 unsigned writemask)
1309 {
1310 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1311 LLVMValueRef dw_addr;
1312 LLVMValueRef stride = NULL;
1313 LLVMValueRef buf_addr = NULL;
1314 unsigned param;
1315 bool store_lds = true;
1316
1317 if (is_patch) {
1318 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1319 store_lds = false;
1320 } else {
1321 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1322 store_lds = false;
1323 }
1324
1325 param = shader_io_get_unique_index(location);
1326 if (location == VARYING_SLOT_CLIP_DIST0 &&
1327 is_compact && const_index > 3) {
1328 const_index -= 3;
1329 param++;
1330 }
1331
1332 if (!is_patch) {
1333 stride = get_tcs_out_vertex_stride(ctx);
1334 dw_addr = get_tcs_out_current_patch_offset(ctx);
1335 } else {
1336 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1337 }
1338
1339 mark_tess_output(ctx, is_patch, param);
1340
1341 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1342 param_index);
1343 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1344 vertex_index, param_index);
1345
1346 bool is_tess_factor = false;
1347 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1348 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1349 is_tess_factor = true;
1350
1351 unsigned base = is_compact ? const_index : 0;
1352 for (unsigned chan = 0; chan < 8; chan++) {
1353 if (!(writemask & (1 << chan)))
1354 continue;
1355 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1356
1357 if (store_lds || is_tess_factor) {
1358 LLVMValueRef dw_addr_chan =
1359 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1360 LLVMConstInt(ctx->ac.i32, chan, false), "");
1361 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1362 }
1363
1364 if (!is_tess_factor && writemask != 0xF)
1365 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1366 buf_addr, ctx->oc_lds,
1367 4 * (base + chan), 1, 0, true, false);
1368 }
1369
1370 if (writemask == 0xF) {
1371 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1372 buf_addr, ctx->oc_lds,
1373 (base * 4), 1, 0, true, false);
1374 }
1375 }
1376
1377 static LLVMValueRef
1378 load_tes_input(struct ac_shader_abi *abi,
1379 LLVMTypeRef type,
1380 LLVMValueRef vertex_index,
1381 LLVMValueRef param_index,
1382 unsigned const_index,
1383 unsigned location,
1384 unsigned driver_location,
1385 unsigned component,
1386 unsigned num_components,
1387 bool is_patch,
1388 bool is_compact,
1389 bool load_input)
1390 {
1391 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1392 LLVMValueRef buf_addr;
1393 LLVMValueRef result;
1394 unsigned param = shader_io_get_unique_index(location);
1395
1396 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1397 const_index -= 3;
1398 param++;
1399 }
1400
1401 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1402 is_compact, vertex_index, param_index);
1403
1404 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1405 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1406
1407 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1408 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1409 result = ac_trim_vector(&ctx->ac, result, num_components);
1410 return result;
1411 }
1412
1413 static LLVMValueRef
1414 load_gs_input(struct ac_shader_abi *abi,
1415 unsigned location,
1416 unsigned driver_location,
1417 unsigned component,
1418 unsigned num_components,
1419 unsigned vertex_index,
1420 unsigned const_index,
1421 LLVMTypeRef type)
1422 {
1423 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1424 LLVMValueRef vtx_offset;
1425 unsigned param, vtx_offset_param;
1426 LLVMValueRef value[4], result;
1427
1428 vtx_offset_param = vertex_index;
1429 assert(vtx_offset_param < 6);
1430 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1431 LLVMConstInt(ctx->ac.i32, 4, false), "");
1432
1433 param = shader_io_get_unique_index(location);
1434
1435 for (unsigned i = component; i < num_components + component; i++) {
1436 if (ctx->ac.chip_class >= GFX9) {
1437 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1438 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1439 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1440 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1441 } else {
1442 LLVMValueRef soffset =
1443 LLVMConstInt(ctx->ac.i32,
1444 (param * 4 + i + const_index) * 256,
1445 false);
1446
1447 value[i] = ac_build_buffer_load(&ctx->ac,
1448 ctx->esgs_ring, 1,
1449 ctx->ac.i32_0,
1450 vtx_offset, soffset,
1451 0, 1, 0, true, false);
1452
1453 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
1454 type, "");
1455 }
1456 }
1457 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1458 result = ac_to_integer(&ctx->ac, result);
1459 return result;
1460 }
1461
1462
1463 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1464 {
1465 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1466 ac_build_kill_if_false(&ctx->ac, visible);
1467 }
1468
1469 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1470 enum glsl_interp_mode interp, unsigned location)
1471 {
1472 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1473
1474 switch (interp) {
1475 case INTERP_MODE_FLAT:
1476 default:
1477 return NULL;
1478 case INTERP_MODE_SMOOTH:
1479 case INTERP_MODE_NONE:
1480 if (location == INTERP_CENTER)
1481 return ctx->persp_center;
1482 else if (location == INTERP_CENTROID)
1483 return ctx->persp_centroid;
1484 else if (location == INTERP_SAMPLE)
1485 return ctx->persp_sample;
1486 break;
1487 case INTERP_MODE_NOPERSPECTIVE:
1488 if (location == INTERP_CENTER)
1489 return ctx->linear_center;
1490 else if (location == INTERP_CENTROID)
1491 return ctx->linear_centroid;
1492 else if (location == INTERP_SAMPLE)
1493 return ctx->linear_sample;
1494 break;
1495 }
1496 return NULL;
1497 }
1498
1499 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1500 LLVMValueRef sample_id)
1501 {
1502 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1503
1504 LLVMValueRef result;
1505 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1506
1507 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1508 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1509
1510 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
1511 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1512
1513 return result;
1514 }
1515
1516
1517 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1518 {
1519 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1520 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
1521 ctx->options->key.fs.log2_num_samples :
1522 ctx->options->key.fs.log2_ps_iter_samples;
1523
1524 /* The bit pattern matches that used by fixed function fragment
1525 * processing. */
1526 static const uint16_t ps_iter_masks[] = {
1527 0xffff, /* not used */
1528 0x5555,
1529 0x1111,
1530 0x0101,
1531 0x0001,
1532 };
1533 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1534
1535 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1536
1537 LLVMValueRef result, sample_id;
1538 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1539 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1540 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1541 return result;
1542 }
1543
1544
1545 static void
1546 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1547 {
1548 LLVMValueRef gs_next_vertex;
1549 LLVMValueRef can_emit;
1550 int idx;
1551 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1552
1553 assert(stream == 0);
1554
1555 /* Write vertex attribute values to GSVS ring */
1556 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1557 ctx->gs_next_vertex,
1558 "");
1559
1560 /* If this thread has already emitted the declared maximum number of
1561 * vertices, kill it: excessive vertex emissions are not supposed to
1562 * have any effect, and GS threads have no externally observable
1563 * effects other than emitting vertices.
1564 */
1565 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1566 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1567 ac_build_kill_if_false(&ctx->ac, can_emit);
1568
1569 /* loop num outputs */
1570 idx = 0;
1571 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1572 LLVMValueRef *out_ptr = &addrs[i * 4];
1573 int length = 4;
1574 int slot = idx;
1575 int slot_inc = 1;
1576
1577 if (!(ctx->output_mask & (1ull << i)))
1578 continue;
1579
1580 if (i == VARYING_SLOT_CLIP_DIST0) {
1581 /* pack clip and cull into a single set of slots */
1582 length = ctx->num_output_clips + ctx->num_output_culls;
1583 if (length > 4)
1584 slot_inc = 2;
1585 }
1586 for (unsigned j = 0; j < length; j++) {
1587 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1588 out_ptr[j], "");
1589 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1590 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1591 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1592
1593 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1594
1595 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1596 out_val, 1,
1597 voffset, ctx->gs2vs_offset, 0,
1598 1, 1, true, true);
1599 }
1600 idx += slot_inc;
1601 }
1602
1603 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1604 ctx->ac.i32_1, "");
1605 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1606
1607 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1608 }
1609
1610 static void
1611 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1612 {
1613 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1614 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1615 }
1616
1617 static LLVMValueRef
1618 load_tess_coord(struct ac_shader_abi *abi)
1619 {
1620 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1621
1622 LLVMValueRef coord[4] = {
1623 ctx->tes_u,
1624 ctx->tes_v,
1625 ctx->ac.f32_0,
1626 ctx->ac.f32_0,
1627 };
1628
1629 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1630 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1631 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1632
1633 return ac_build_gather_values(&ctx->ac, coord, 3);
1634 }
1635
1636 static LLVMValueRef
1637 load_patch_vertices_in(struct ac_shader_abi *abi)
1638 {
1639 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1640 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1641 }
1642
1643
1644 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1645 {
1646 return abi->base_vertex;
1647 }
1648
1649 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1650 LLVMValueRef buffer_ptr, bool write)
1651 {
1652 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1653 LLVMValueRef result;
1654
1655 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1656
1657 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1658 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1659
1660 return result;
1661 }
1662
1663 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1664 {
1665 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1666 LLVMValueRef result;
1667
1668 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1669
1670 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1671 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1672
1673 return result;
1674 }
1675
1676 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1677 unsigned descriptor_set,
1678 unsigned base_index,
1679 unsigned constant_index,
1680 LLVMValueRef index,
1681 enum ac_descriptor_type desc_type,
1682 bool image, bool write)
1683 {
1684 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1685 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1686 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1687 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1688 unsigned offset = binding->offset;
1689 unsigned stride = binding->size;
1690 unsigned type_size;
1691 LLVMBuilderRef builder = ctx->ac.builder;
1692 LLVMTypeRef type;
1693
1694 assert(base_index < layout->binding_count);
1695
1696 switch (desc_type) {
1697 case AC_DESC_IMAGE:
1698 type = ctx->ac.v8i32;
1699 type_size = 32;
1700 break;
1701 case AC_DESC_FMASK:
1702 type = ctx->ac.v8i32;
1703 offset += 32;
1704 type_size = 32;
1705 break;
1706 case AC_DESC_SAMPLER:
1707 type = ctx->ac.v4i32;
1708 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1709 offset += 64;
1710
1711 type_size = 16;
1712 break;
1713 case AC_DESC_BUFFER:
1714 type = ctx->ac.v4i32;
1715 type_size = 16;
1716 break;
1717 default:
1718 unreachable("invalid desc_type\n");
1719 }
1720
1721 offset += constant_index * stride;
1722
1723 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1724 (!index || binding->immutable_samplers_equal)) {
1725 if (binding->immutable_samplers_equal)
1726 constant_index = 0;
1727
1728 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1729
1730 LLVMValueRef constants[] = {
1731 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1732 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1733 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1734 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1735 };
1736 return ac_build_gather_values(&ctx->ac, constants, 4);
1737 }
1738
1739 assert(stride % type_size == 0);
1740
1741 if (!index)
1742 index = ctx->ac.i32_0;
1743
1744 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1745
1746 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1747 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
1748
1749 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1750 }
1751
1752
1753 static void
1754 handle_vs_input_decl(struct radv_shader_context *ctx,
1755 struct nir_variable *variable)
1756 {
1757 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1758 LLVMValueRef t_offset;
1759 LLVMValueRef t_list;
1760 LLVMValueRef input;
1761 LLVMValueRef buffer_index;
1762 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
1763 int idx = variable->data.location;
1764 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1765 uint8_t input_usage_mask =
1766 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1767 unsigned num_channels = util_last_bit(input_usage_mask);
1768
1769 variable->data.driver_location = idx * 4;
1770
1771 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
1772 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
1773 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
1774 ctx->abi.start_instance, "");
1775 if (ctx->options->key.vs.as_ls) {
1776 ctx->shader_info->vs.vgpr_comp_cnt =
1777 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1778 } else {
1779 ctx->shader_info->vs.vgpr_comp_cnt =
1780 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1781 }
1782 } else
1783 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
1784 ctx->abi.base_vertex, "");
1785 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
1786
1787 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1788
1789 input = ac_build_buffer_load_format(&ctx->ac, t_list,
1790 buffer_index,
1791 ctx->ac.i32_0,
1792 num_channels, false, true);
1793
1794 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
1795
1796 for (unsigned chan = 0; chan < 4; chan++) {
1797 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1798 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
1799 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
1800 input, llvm_chan, ""));
1801 }
1802 }
1803 }
1804
1805 static void interp_fs_input(struct radv_shader_context *ctx,
1806 unsigned attr,
1807 LLVMValueRef interp_param,
1808 LLVMValueRef prim_mask,
1809 LLVMValueRef result[4])
1810 {
1811 LLVMValueRef attr_number;
1812 unsigned chan;
1813 LLVMValueRef i, j;
1814 bool interp = interp_param != NULL;
1815
1816 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
1817
1818 /* fs.constant returns the param from the middle vertex, so it's not
1819 * really useful for flat shading. It's meant to be used for custom
1820 * interpolation (but the intrinsic can't fetch from the other two
1821 * vertices).
1822 *
1823 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1824 * to do the right thing. The only reason we use fs.constant is that
1825 * fs.interp cannot be used on integers, because they can be equal
1826 * to NaN.
1827 */
1828 if (interp) {
1829 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1830 ctx->ac.v2f32, "");
1831
1832 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1833 ctx->ac.i32_0, "");
1834 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1835 ctx->ac.i32_1, "");
1836 }
1837
1838 for (chan = 0; chan < 4; chan++) {
1839 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1840
1841 if (interp) {
1842 result[chan] = ac_build_fs_interp(&ctx->ac,
1843 llvm_chan,
1844 attr_number,
1845 prim_mask, i, j);
1846 } else {
1847 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1848 LLVMConstInt(ctx->ac.i32, 2, false),
1849 llvm_chan,
1850 attr_number,
1851 prim_mask);
1852 }
1853 }
1854 }
1855
1856 static void
1857 handle_fs_input_decl(struct radv_shader_context *ctx,
1858 struct nir_variable *variable)
1859 {
1860 int idx = variable->data.location;
1861 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1862 LLVMValueRef interp;
1863
1864 variable->data.driver_location = idx * 4;
1865 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
1866
1867 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
1868 unsigned interp_type;
1869 if (variable->data.sample)
1870 interp_type = INTERP_SAMPLE;
1871 else if (variable->data.centroid)
1872 interp_type = INTERP_CENTROID;
1873 else
1874 interp_type = INTERP_CENTER;
1875
1876 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
1877 } else
1878 interp = NULL;
1879
1880 for (unsigned i = 0; i < attrib_count; ++i)
1881 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
1882
1883 }
1884
1885 static void
1886 handle_vs_inputs(struct radv_shader_context *ctx,
1887 struct nir_shader *nir) {
1888 nir_foreach_variable(variable, &nir->inputs)
1889 handle_vs_input_decl(ctx, variable);
1890 }
1891
1892 static void
1893 prepare_interp_optimize(struct radv_shader_context *ctx,
1894 struct nir_shader *nir)
1895 {
1896 if (!ctx->options->key.fs.multisample)
1897 return;
1898
1899 bool uses_center = false;
1900 bool uses_centroid = false;
1901 nir_foreach_variable(variable, &nir->inputs) {
1902 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1903 variable->data.sample)
1904 continue;
1905
1906 if (variable->data.centroid)
1907 uses_centroid = true;
1908 else
1909 uses_center = true;
1910 }
1911
1912 if (uses_center && uses_centroid) {
1913 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
1914 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
1915 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
1916 }
1917 }
1918
1919 static void
1920 handle_fs_inputs(struct radv_shader_context *ctx,
1921 struct nir_shader *nir)
1922 {
1923 prepare_interp_optimize(ctx, nir);
1924
1925 nir_foreach_variable(variable, &nir->inputs)
1926 handle_fs_input_decl(ctx, variable);
1927
1928 unsigned index = 0;
1929
1930 if (ctx->shader_info->info.ps.uses_input_attachments ||
1931 ctx->shader_info->info.needs_multiview_view_index)
1932 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
1933
1934 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
1935 LLVMValueRef interp_param;
1936 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
1937
1938 if (!(ctx->input_mask & (1ull << i)))
1939 continue;
1940
1941 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
1942 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
1943 interp_param = *inputs;
1944 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
1945 inputs);
1946
1947 if (!interp_param)
1948 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
1949 ++index;
1950 } else if (i == VARYING_SLOT_POS) {
1951 for(int i = 0; i < 3; ++i)
1952 inputs[i] = ctx->abi.frag_pos[i];
1953
1954 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
1955 ctx->abi.frag_pos[3]);
1956 }
1957 }
1958 ctx->shader_info->fs.num_interp = index;
1959 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
1960
1961 if (ctx->shader_info->info.needs_multiview_view_index)
1962 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
1963 }
1964
1965 static void
1966 scan_shader_output_decl(struct radv_shader_context *ctx,
1967 struct nir_variable *variable,
1968 struct nir_shader *shader,
1969 gl_shader_stage stage)
1970 {
1971 int idx = variable->data.location + variable->data.index;
1972 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1973 uint64_t mask_attribs;
1974
1975 variable->data.driver_location = idx * 4;
1976
1977 /* tess ctrl has it's own load/store paths for outputs */
1978 if (stage == MESA_SHADER_TESS_CTRL)
1979 return;
1980
1981 mask_attribs = ((1ull << attrib_count) - 1) << idx;
1982 if (stage == MESA_SHADER_VERTEX ||
1983 stage == MESA_SHADER_TESS_EVAL ||
1984 stage == MESA_SHADER_GEOMETRY) {
1985 if (idx == VARYING_SLOT_CLIP_DIST0) {
1986 int length = shader->info.clip_distance_array_size +
1987 shader->info.cull_distance_array_size;
1988 if (stage == MESA_SHADER_VERTEX) {
1989 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
1990 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
1991 }
1992 if (stage == MESA_SHADER_TESS_EVAL) {
1993 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
1994 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
1995 }
1996
1997 if (length > 4)
1998 attrib_count = 2;
1999 else
2000 attrib_count = 1;
2001 mask_attribs = 1ull << idx;
2002 }
2003 }
2004
2005 ctx->output_mask |= mask_attribs;
2006 }
2007
2008
2009 /* Initialize arguments for the shader export intrinsic */
2010 static void
2011 si_llvm_init_export_args(struct radv_shader_context *ctx,
2012 LLVMValueRef *values,
2013 unsigned enabled_channels,
2014 unsigned target,
2015 struct ac_export_args *args)
2016 {
2017 /* Specify the channels that are enabled. */
2018 args->enabled_channels = enabled_channels;
2019
2020 /* Specify whether the EXEC mask represents the valid mask */
2021 args->valid_mask = 0;
2022
2023 /* Specify whether this is the last export */
2024 args->done = 0;
2025
2026 /* Specify the target we are exporting */
2027 args->target = target;
2028
2029 args->compr = false;
2030 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2031 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2032 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2033 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2034
2035 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2036 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2037 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2038 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2039 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2040 unsigned chan;
2041
2042 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2043 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2044 unsigned bits, bool hi) = NULL;
2045
2046 switch(col_format) {
2047 case V_028714_SPI_SHADER_ZERO:
2048 args->enabled_channels = 0; /* writemask */
2049 args->target = V_008DFC_SQ_EXP_NULL;
2050 break;
2051
2052 case V_028714_SPI_SHADER_32_R:
2053 args->enabled_channels = 1;
2054 args->out[0] = values[0];
2055 break;
2056
2057 case V_028714_SPI_SHADER_32_GR:
2058 args->enabled_channels = 0x3;
2059 args->out[0] = values[0];
2060 args->out[1] = values[1];
2061 break;
2062
2063 case V_028714_SPI_SHADER_32_AR:
2064 args->enabled_channels = 0x9;
2065 args->out[0] = values[0];
2066 args->out[3] = values[3];
2067 break;
2068
2069 case V_028714_SPI_SHADER_FP16_ABGR:
2070 args->enabled_channels = 0x5;
2071 packf = ac_build_cvt_pkrtz_f16;
2072 break;
2073
2074 case V_028714_SPI_SHADER_UNORM16_ABGR:
2075 args->enabled_channels = 0x5;
2076 packf = ac_build_cvt_pknorm_u16;
2077 break;
2078
2079 case V_028714_SPI_SHADER_SNORM16_ABGR:
2080 args->enabled_channels = 0x5;
2081 packf = ac_build_cvt_pknorm_i16;
2082 break;
2083
2084 case V_028714_SPI_SHADER_UINT16_ABGR:
2085 args->enabled_channels = 0x5;
2086 packi = ac_build_cvt_pk_u16;
2087 break;
2088
2089 case V_028714_SPI_SHADER_SINT16_ABGR:
2090 args->enabled_channels = 0x5;
2091 packi = ac_build_cvt_pk_i16;
2092 break;
2093
2094 default:
2095 case V_028714_SPI_SHADER_32_ABGR:
2096 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2097 break;
2098 }
2099
2100 /* Pack f16 or norm_i16/u16. */
2101 if (packf) {
2102 for (chan = 0; chan < 2; chan++) {
2103 LLVMValueRef pack_args[2] = {
2104 values[2 * chan],
2105 values[2 * chan + 1]
2106 };
2107 LLVMValueRef packed;
2108
2109 packed = packf(&ctx->ac, pack_args);
2110 args->out[chan] = ac_to_float(&ctx->ac, packed);
2111 }
2112 args->compr = 1; /* COMPR flag */
2113 }
2114
2115 /* Pack i16/u16. */
2116 if (packi) {
2117 for (chan = 0; chan < 2; chan++) {
2118 LLVMValueRef pack_args[2] = {
2119 ac_to_integer(&ctx->ac, values[2 * chan]),
2120 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2121 };
2122 LLVMValueRef packed;
2123
2124 packed = packi(&ctx->ac, pack_args,
2125 is_int8 ? 8 : is_int10 ? 10 : 16,
2126 chan == 1);
2127 args->out[chan] = ac_to_float(&ctx->ac, packed);
2128 }
2129 args->compr = 1; /* COMPR flag */
2130 }
2131 return;
2132 }
2133
2134 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2135
2136 for (unsigned i = 0; i < 4; ++i) {
2137 if (!(args->enabled_channels & (1 << i)))
2138 continue;
2139
2140 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2141 }
2142 }
2143
2144 static void
2145 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2146 LLVMValueRef *values, unsigned enabled_channels)
2147 {
2148 struct ac_export_args args;
2149
2150 si_llvm_init_export_args(ctx, values, enabled_channels,
2151 V_008DFC_SQ_EXP_PARAM + index, &args);
2152 ac_build_export(&ctx->ac, &args);
2153 }
2154
2155 static LLVMValueRef
2156 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2157 {
2158 LLVMValueRef output =
2159 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
2160
2161 return LLVMBuildLoad(ctx->ac.builder, output, "");
2162 }
2163
2164 static void
2165 handle_vs_outputs_post(struct radv_shader_context *ctx,
2166 bool export_prim_id,
2167 struct radv_vs_output_info *outinfo)
2168 {
2169 uint32_t param_count = 0;
2170 unsigned target;
2171 unsigned pos_idx, num_pos_exports = 0;
2172 struct ac_export_args args, pos_args[4] = {};
2173 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2174 int i;
2175
2176 if (ctx->options->key.has_multiview_view_index) {
2177 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2178 if(!*tmp_out) {
2179 for(unsigned i = 0; i < 4; ++i)
2180 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2181 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2182 }
2183
2184 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2185 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2186 }
2187
2188 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2189 sizeof(outinfo->vs_output_param_offset));
2190
2191 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2192 LLVMValueRef slots[8];
2193 unsigned j;
2194
2195 if (outinfo->cull_dist_mask)
2196 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2197
2198 i = VARYING_SLOT_CLIP_DIST0;
2199 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
2200 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2201
2202 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
2203 slots[i] = LLVMGetUndef(ctx->ac.f32);
2204
2205 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
2206 target = V_008DFC_SQ_EXP_POS + 3;
2207 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2208 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2209 &args, sizeof(args));
2210 }
2211
2212 target = V_008DFC_SQ_EXP_POS + 2;
2213 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2214 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2215 &args, sizeof(args));
2216
2217 }
2218
2219 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2220 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2221 for (unsigned j = 0; j < 4; j++)
2222 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2223 }
2224 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2225
2226 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2227 outinfo->writes_pointsize = true;
2228 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2229 }
2230
2231 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2232 outinfo->writes_layer = true;
2233 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2234 }
2235
2236 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2237 outinfo->writes_viewport_index = true;
2238 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2239 }
2240
2241 if (outinfo->writes_pointsize ||
2242 outinfo->writes_layer ||
2243 outinfo->writes_viewport_index) {
2244 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2245 (outinfo->writes_layer == true ? 4 : 0));
2246 pos_args[1].valid_mask = 0;
2247 pos_args[1].done = 0;
2248 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2249 pos_args[1].compr = 0;
2250 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2251 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2252 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2253 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2254
2255 if (outinfo->writes_pointsize == true)
2256 pos_args[1].out[0] = psize_value;
2257 if (outinfo->writes_layer == true)
2258 pos_args[1].out[2] = layer_value;
2259 if (outinfo->writes_viewport_index == true) {
2260 if (ctx->options->chip_class >= GFX9) {
2261 /* GFX9 has the layer in out.z[10:0] and the viewport
2262 * index in out.z[19:16].
2263 */
2264 LLVMValueRef v = viewport_index_value;
2265 v = ac_to_integer(&ctx->ac, v);
2266 v = LLVMBuildShl(ctx->ac.builder, v,
2267 LLVMConstInt(ctx->ac.i32, 16, false),
2268 "");
2269 v = LLVMBuildOr(ctx->ac.builder, v,
2270 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2271
2272 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2273 pos_args[1].enabled_channels |= 1 << 2;
2274 } else {
2275 pos_args[1].out[3] = viewport_index_value;
2276 pos_args[1].enabled_channels |= 1 << 3;
2277 }
2278 }
2279 }
2280 for (i = 0; i < 4; i++) {
2281 if (pos_args[i].out[0])
2282 num_pos_exports++;
2283 }
2284
2285 pos_idx = 0;
2286 for (i = 0; i < 4; i++) {
2287 if (!pos_args[i].out[0])
2288 continue;
2289
2290 /* Specify the target we are exporting */
2291 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2292 if (pos_idx == num_pos_exports)
2293 pos_args[i].done = 1;
2294 ac_build_export(&ctx->ac, &pos_args[i]);
2295 }
2296
2297 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2298 LLVMValueRef values[4];
2299 if (!(ctx->output_mask & (1ull << i)))
2300 continue;
2301
2302 if (i != VARYING_SLOT_LAYER &&
2303 i != VARYING_SLOT_PRIMITIVE_ID &&
2304 i < VARYING_SLOT_VAR0)
2305 continue;
2306
2307 for (unsigned j = 0; j < 4; j++)
2308 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2309
2310 unsigned output_usage_mask;
2311
2312 if (ctx->stage == MESA_SHADER_VERTEX &&
2313 !ctx->is_gs_copy_shader) {
2314 output_usage_mask =
2315 ctx->shader_info->info.vs.output_usage_mask[i];
2316 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2317 output_usage_mask =
2318 ctx->shader_info->info.tes.output_usage_mask[i];
2319 } else {
2320 /* Enable all channels for the GS copy shader because
2321 * we don't know the output usage mask currently.
2322 */
2323 output_usage_mask = 0xf;
2324 }
2325
2326 radv_export_param(ctx, param_count, values, output_usage_mask);
2327
2328 outinfo->vs_output_param_offset[i] = param_count++;
2329 }
2330
2331 if (export_prim_id) {
2332 LLVMValueRef values[4];
2333
2334 values[0] = ctx->vs_prim_id;
2335 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2336 ctx->shader_info->vs.vgpr_comp_cnt);
2337 for (unsigned j = 1; j < 4; j++)
2338 values[j] = ctx->ac.f32_0;
2339
2340 radv_export_param(ctx, param_count, values, 0xf);
2341
2342 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2343 outinfo->export_prim_id = true;
2344 }
2345
2346 outinfo->pos_exports = num_pos_exports;
2347 outinfo->param_exports = param_count;
2348 }
2349
2350 static void
2351 handle_es_outputs_post(struct radv_shader_context *ctx,
2352 struct radv_es_output_info *outinfo)
2353 {
2354 int j;
2355 uint64_t max_output_written = 0;
2356 LLVMValueRef lds_base = NULL;
2357
2358 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2359 int param_index;
2360 int length = 4;
2361
2362 if (!(ctx->output_mask & (1ull << i)))
2363 continue;
2364
2365 if (i == VARYING_SLOT_CLIP_DIST0)
2366 length = ctx->num_output_clips + ctx->num_output_culls;
2367
2368 param_index = shader_io_get_unique_index(i);
2369
2370 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2371 }
2372
2373 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2374
2375 if (ctx->ac.chip_class >= GFX9) {
2376 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2377 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2378 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2379 LLVMConstInt(ctx->ac.i32, 24, false),
2380 LLVMConstInt(ctx->ac.i32, 4, false), false);
2381 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2382 LLVMBuildMul(ctx->ac.builder, wave_idx,
2383 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2384 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2385 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2386 }
2387
2388 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2389 LLVMValueRef dw_addr = NULL;
2390 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2391 int param_index;
2392 int length = 4;
2393
2394 if (!(ctx->output_mask & (1ull << i)))
2395 continue;
2396
2397 if (i == VARYING_SLOT_CLIP_DIST0)
2398 length = ctx->num_output_clips + ctx->num_output_culls;
2399
2400 param_index = shader_io_get_unique_index(i);
2401
2402 if (lds_base) {
2403 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2404 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2405 "");
2406 }
2407 for (j = 0; j < length; j++) {
2408 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2409 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2410
2411 if (ctx->ac.chip_class >= GFX9) {
2412 ac_lds_store(&ctx->ac, dw_addr,
2413 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2414 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2415 } else {
2416 ac_build_buffer_store_dword(&ctx->ac,
2417 ctx->esgs_ring,
2418 out_val, 1,
2419 NULL, ctx->es2gs_offset,
2420 (4 * param_index + j) * 4,
2421 1, 1, true, true);
2422 }
2423 }
2424 }
2425 }
2426
2427 static void
2428 handle_ls_outputs_post(struct radv_shader_context *ctx)
2429 {
2430 LLVMValueRef vertex_id = ctx->rel_auto_id;
2431 LLVMValueRef vertex_dw_stride = ac_unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
2432 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2433 vertex_dw_stride, "");
2434
2435 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2436 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2437 int length = 4;
2438
2439 if (!(ctx->output_mask & (1ull << i)))
2440 continue;
2441
2442 if (i == VARYING_SLOT_CLIP_DIST0)
2443 length = ctx->num_output_clips + ctx->num_output_culls;
2444 int param = shader_io_get_unique_index(i);
2445 mark_tess_output(ctx, false, param);
2446 if (length > 4)
2447 mark_tess_output(ctx, false, param + 1);
2448 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2449 LLVMConstInt(ctx->ac.i32, param * 4, false),
2450 "");
2451 for (unsigned j = 0; j < length; j++) {
2452 ac_lds_store(&ctx->ac, dw_addr,
2453 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2454 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2455 }
2456 }
2457 }
2458
2459 struct ac_build_if_state
2460 {
2461 struct radv_shader_context *ctx;
2462 LLVMValueRef condition;
2463 LLVMBasicBlockRef entry_block;
2464 LLVMBasicBlockRef true_block;
2465 LLVMBasicBlockRef false_block;
2466 LLVMBasicBlockRef merge_block;
2467 };
2468
2469 static LLVMBasicBlockRef
2470 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
2471 {
2472 LLVMBasicBlockRef current_block;
2473 LLVMBasicBlockRef next_block;
2474 LLVMBasicBlockRef new_block;
2475
2476 /* get current basic block */
2477 current_block = LLVMGetInsertBlock(ctx->ac.builder);
2478
2479 /* chqeck if there's another block after this one */
2480 next_block = LLVMGetNextBasicBlock(current_block);
2481 if (next_block) {
2482 /* insert the new block before the next block */
2483 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
2484 }
2485 else {
2486 /* append new block after current block */
2487 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
2488 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
2489 }
2490 return new_block;
2491 }
2492
2493 static void
2494 ac_nir_build_if(struct ac_build_if_state *ifthen,
2495 struct radv_shader_context *ctx,
2496 LLVMValueRef condition)
2497 {
2498 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
2499
2500 memset(ifthen, 0, sizeof *ifthen);
2501 ifthen->ctx = ctx;
2502 ifthen->condition = condition;
2503 ifthen->entry_block = block;
2504
2505 /* create endif/merge basic block for the phi functions */
2506 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
2507
2508 /* create/insert true_block before merge_block */
2509 ifthen->true_block =
2510 LLVMInsertBasicBlockInContext(ctx->context,
2511 ifthen->merge_block,
2512 "if-true-block");
2513
2514 /* successive code goes into the true block */
2515 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
2516 }
2517
2518 /**
2519 * End a conditional.
2520 */
2521 static void
2522 ac_nir_build_endif(struct ac_build_if_state *ifthen)
2523 {
2524 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
2525
2526 /* Insert branch to the merge block from current block */
2527 LLVMBuildBr(builder, ifthen->merge_block);
2528
2529 /*
2530 * Now patch in the various branch instructions.
2531 */
2532
2533 /* Insert the conditional branch instruction at the end of entry_block */
2534 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
2535 if (ifthen->false_block) {
2536 /* we have an else clause */
2537 LLVMBuildCondBr(builder, ifthen->condition,
2538 ifthen->true_block, ifthen->false_block);
2539 }
2540 else {
2541 /* no else clause */
2542 LLVMBuildCondBr(builder, ifthen->condition,
2543 ifthen->true_block, ifthen->merge_block);
2544 }
2545
2546 /* Resume building code at end of the ifthen->merge_block */
2547 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
2548 }
2549
2550 static void
2551 write_tess_factors(struct radv_shader_context *ctx)
2552 {
2553 unsigned stride, outer_comps, inner_comps;
2554 struct ac_build_if_state if_ctx, inner_if_ctx;
2555 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2556 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2557 unsigned tess_inner_index = 0, tess_outer_index;
2558 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2559 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2560 int i;
2561 ac_emit_barrier(&ctx->ac, ctx->stage);
2562
2563 switch (ctx->options->key.tcs.primitive_mode) {
2564 case GL_ISOLINES:
2565 stride = 2;
2566 outer_comps = 2;
2567 inner_comps = 0;
2568 break;
2569 case GL_TRIANGLES:
2570 stride = 4;
2571 outer_comps = 3;
2572 inner_comps = 1;
2573 break;
2574 case GL_QUADS:
2575 stride = 6;
2576 outer_comps = 4;
2577 inner_comps = 2;
2578 break;
2579 default:
2580 return;
2581 }
2582
2583 ac_nir_build_if(&if_ctx, ctx,
2584 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2585 invocation_id, ctx->ac.i32_0, ""));
2586
2587 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2588
2589 if (inner_comps) {
2590 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2591 mark_tess_output(ctx, true, tess_inner_index);
2592 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2593 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2594 }
2595
2596 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2597 mark_tess_output(ctx, true, tess_outer_index);
2598 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2599 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2600
2601 for (i = 0; i < 4; i++) {
2602 inner[i] = LLVMGetUndef(ctx->ac.i32);
2603 outer[i] = LLVMGetUndef(ctx->ac.i32);
2604 }
2605
2606 // LINES reverseal
2607 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2608 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2609 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2610 ctx->ac.i32_1, "");
2611 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2612 } else {
2613 for (i = 0; i < outer_comps; i++) {
2614 outer[i] = out[i] =
2615 ac_lds_load(&ctx->ac, lds_outer);
2616 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2617 ctx->ac.i32_1, "");
2618 }
2619 for (i = 0; i < inner_comps; i++) {
2620 inner[i] = out[outer_comps+i] =
2621 ac_lds_load(&ctx->ac, lds_inner);
2622 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2623 ctx->ac.i32_1, "");
2624 }
2625 }
2626
2627 /* Convert the outputs to vectors for stores. */
2628 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2629 vec1 = NULL;
2630
2631 if (stride > 4)
2632 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2633
2634
2635 buffer = ctx->hs_ring_tess_factor;
2636 tf_base = ctx->tess_factor_offset;
2637 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2638 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2639 unsigned tf_offset = 0;
2640
2641 if (ctx->options->chip_class <= VI) {
2642 ac_nir_build_if(&inner_if_ctx, ctx,
2643 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2644 rel_patch_id, ctx->ac.i32_0, ""));
2645
2646 /* Store the dynamic HS control word. */
2647 ac_build_buffer_store_dword(&ctx->ac, buffer,
2648 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2649 1, ctx->ac.i32_0, tf_base,
2650 0, 1, 0, true, false);
2651 tf_offset += 4;
2652
2653 ac_nir_build_endif(&inner_if_ctx);
2654 }
2655
2656 /* Store the tessellation factors. */
2657 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2658 MIN2(stride, 4), byteoffset, tf_base,
2659 tf_offset, 1, 0, true, false);
2660 if (vec1)
2661 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2662 stride - 4, byteoffset, tf_base,
2663 16 + tf_offset, 1, 0, true, false);
2664
2665 //store to offchip for TES to read - only if TES reads them
2666 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2667 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2668 LLVMValueRef tf_inner_offset;
2669 unsigned param_outer, param_inner;
2670
2671 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2672 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2673 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2674
2675 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2676 util_next_power_of_two(outer_comps));
2677
2678 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2679 outer_comps, tf_outer_offset,
2680 ctx->oc_lds, 0, 1, 0, true, false);
2681 if (inner_comps) {
2682 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2683 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2684 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2685
2686 inner_vec = inner_comps == 1 ? inner[0] :
2687 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2688 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2689 inner_comps, tf_inner_offset,
2690 ctx->oc_lds, 0, 1, 0, true, false);
2691 }
2692 }
2693 ac_nir_build_endif(&if_ctx);
2694 }
2695
2696 static void
2697 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2698 {
2699 write_tess_factors(ctx);
2700 }
2701
2702 static bool
2703 si_export_mrt_color(struct radv_shader_context *ctx,
2704 LLVMValueRef *color, unsigned index,
2705 struct ac_export_args *args)
2706 {
2707 /* Export */
2708 si_llvm_init_export_args(ctx, color, 0xf,
2709 V_008DFC_SQ_EXP_MRT + index, args);
2710 if (!args->enabled_channels)
2711 return false; /* unnecessary NULL export */
2712
2713 return true;
2714 }
2715
2716 static void
2717 radv_export_mrt_z(struct radv_shader_context *ctx,
2718 LLVMValueRef depth, LLVMValueRef stencil,
2719 LLVMValueRef samplemask)
2720 {
2721 struct ac_export_args args;
2722
2723 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2724
2725 ac_build_export(&ctx->ac, &args);
2726 }
2727
2728 static void
2729 handle_fs_outputs_post(struct radv_shader_context *ctx)
2730 {
2731 unsigned index = 0;
2732 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2733 struct ac_export_args color_args[8];
2734
2735 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2736 LLVMValueRef values[4];
2737
2738 if (!(ctx->output_mask & (1ull << i)))
2739 continue;
2740
2741 if (i < FRAG_RESULT_DATA0)
2742 continue;
2743
2744 for (unsigned j = 0; j < 4; j++)
2745 values[j] = ac_to_float(&ctx->ac,
2746 radv_load_output(ctx, i, j));
2747
2748 bool ret = si_export_mrt_color(ctx, values,
2749 i - FRAG_RESULT_DATA0,
2750 &color_args[index]);
2751 if (ret)
2752 index++;
2753 }
2754
2755 /* Process depth, stencil, samplemask. */
2756 if (ctx->shader_info->info.ps.writes_z) {
2757 depth = ac_to_float(&ctx->ac,
2758 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
2759 }
2760 if (ctx->shader_info->info.ps.writes_stencil) {
2761 stencil = ac_to_float(&ctx->ac,
2762 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
2763 }
2764 if (ctx->shader_info->info.ps.writes_sample_mask) {
2765 samplemask = ac_to_float(&ctx->ac,
2766 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
2767 }
2768
2769 /* Set the DONE bit on last non-null color export only if Z isn't
2770 * exported.
2771 */
2772 if (index > 0 &&
2773 !ctx->shader_info->info.ps.writes_z &&
2774 !ctx->shader_info->info.ps.writes_stencil &&
2775 !ctx->shader_info->info.ps.writes_sample_mask) {
2776 unsigned last = index - 1;
2777
2778 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
2779 color_args[last].done = 1; /* DONE bit */
2780 }
2781
2782 /* Export PS outputs. */
2783 for (unsigned i = 0; i < index; i++)
2784 ac_build_export(&ctx->ac, &color_args[i]);
2785
2786 if (depth || stencil || samplemask)
2787 radv_export_mrt_z(ctx, depth, stencil, samplemask);
2788 else if (!index)
2789 ac_build_export_null(&ctx->ac);
2790 }
2791
2792 static void
2793 emit_gs_epilogue(struct radv_shader_context *ctx)
2794 {
2795 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
2796 }
2797
2798 static void
2799 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
2800 LLVMValueRef *addrs)
2801 {
2802 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2803
2804 switch (ctx->stage) {
2805 case MESA_SHADER_VERTEX:
2806 if (ctx->options->key.vs.as_ls)
2807 handle_ls_outputs_post(ctx);
2808 else if (ctx->options->key.vs.as_es)
2809 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
2810 else
2811 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
2812 &ctx->shader_info->vs.outinfo);
2813 break;
2814 case MESA_SHADER_FRAGMENT:
2815 handle_fs_outputs_post(ctx);
2816 break;
2817 case MESA_SHADER_GEOMETRY:
2818 emit_gs_epilogue(ctx);
2819 break;
2820 case MESA_SHADER_TESS_CTRL:
2821 handle_tcs_outputs_post(ctx);
2822 break;
2823 case MESA_SHADER_TESS_EVAL:
2824 if (ctx->options->key.tes.as_es)
2825 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
2826 else
2827 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
2828 &ctx->shader_info->tes.outinfo);
2829 break;
2830 default:
2831 break;
2832 }
2833 }
2834
2835 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
2836 {
2837 LLVMPassManagerRef passmgr;
2838 /* Create the pass manager */
2839 passmgr = LLVMCreateFunctionPassManagerForModule(
2840 ctx->ac.module);
2841
2842 /* This pass should eliminate all the load and store instructions */
2843 LLVMAddPromoteMemoryToRegisterPass(passmgr);
2844
2845 /* Add some optimization passes */
2846 LLVMAddScalarReplAggregatesPass(passmgr);
2847 LLVMAddLICMPass(passmgr);
2848 LLVMAddAggressiveDCEPass(passmgr);
2849 LLVMAddCFGSimplificationPass(passmgr);
2850 LLVMAddInstructionCombiningPass(passmgr);
2851
2852 /* Run the pass */
2853 LLVMInitializeFunctionPassManager(passmgr);
2854 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
2855 LLVMFinalizeFunctionPassManager(passmgr);
2856
2857 LLVMDisposeBuilder(ctx->ac.builder);
2858 LLVMDisposePassManager(passmgr);
2859
2860 ac_llvm_context_dispose(&ctx->ac);
2861 }
2862
2863 static void
2864 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
2865 {
2866 struct radv_vs_output_info *outinfo;
2867
2868 switch (ctx->stage) {
2869 case MESA_SHADER_FRAGMENT:
2870 case MESA_SHADER_COMPUTE:
2871 case MESA_SHADER_TESS_CTRL:
2872 case MESA_SHADER_GEOMETRY:
2873 return;
2874 case MESA_SHADER_VERTEX:
2875 if (ctx->options->key.vs.as_ls ||
2876 ctx->options->key.vs.as_es)
2877 return;
2878 outinfo = &ctx->shader_info->vs.outinfo;
2879 break;
2880 case MESA_SHADER_TESS_EVAL:
2881 if (ctx->options->key.vs.as_es)
2882 return;
2883 outinfo = &ctx->shader_info->tes.outinfo;
2884 break;
2885 default:
2886 unreachable("Unhandled shader type");
2887 }
2888
2889 ac_optimize_vs_outputs(&ctx->ac,
2890 ctx->main_function,
2891 outinfo->vs_output_param_offset,
2892 VARYING_SLOT_MAX,
2893 &outinfo->param_exports);
2894 }
2895
2896 static void
2897 ac_setup_rings(struct radv_shader_context *ctx)
2898 {
2899 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
2900 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
2901 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
2902 }
2903
2904 if (ctx->is_gs_copy_shader) {
2905 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
2906 }
2907 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2908 LLVMValueRef tmp;
2909 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
2910 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
2911
2912 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
2913
2914 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
2915 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
2916 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
2917 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
2918 }
2919
2920 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
2921 ctx->stage == MESA_SHADER_TESS_EVAL) {
2922 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
2923 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
2924 }
2925 }
2926
2927 static unsigned
2928 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
2929 const struct nir_shader *nir)
2930 {
2931 switch (nir->info.stage) {
2932 case MESA_SHADER_TESS_CTRL:
2933 return chip_class >= CIK ? 128 : 64;
2934 case MESA_SHADER_GEOMETRY:
2935 return chip_class >= GFX9 ? 128 : 64;
2936 case MESA_SHADER_COMPUTE:
2937 break;
2938 default:
2939 return 0;
2940 }
2941
2942 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
2943 nir->info.cs.local_size[1] *
2944 nir->info.cs.local_size[2];
2945 return max_workgroup_size;
2946 }
2947
2948 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
2949 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
2950 {
2951 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2952 LLVMConstInt(ctx->ac.i32, 8, false),
2953 LLVMConstInt(ctx->ac.i32, 8, false), false);
2954 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
2955 ctx->ac.i32_0, "");
2956 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
2957 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
2958 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
2959 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
2960 }
2961
2962 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
2963 {
2964 for(int i = 5; i >= 0; --i) {
2965 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
2966 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
2967 LLVMConstInt(ctx->ac.i32, 16, false), false);
2968 }
2969
2970 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2971 LLVMConstInt(ctx->ac.i32, 16, false),
2972 LLVMConstInt(ctx->ac.i32, 8, false), false);
2973 }
2974
2975
2976 static
2977 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
2978 struct nir_shader *const *shaders,
2979 int shader_count,
2980 struct radv_shader_variant_info *shader_info,
2981 const struct ac_nir_compiler_options *options,
2982 bool dump_shader)
2983 {
2984 struct radv_shader_context ctx = {0};
2985 unsigned i;
2986 ctx.options = options;
2987 ctx.shader_info = shader_info;
2988 ctx.context = LLVMContextCreate();
2989
2990 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
2991 options->family);
2992 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
2993 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
2994
2995 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
2996 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
2997 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
2998 LLVMDisposeTargetData(data_layout);
2999 LLVMDisposeMessage(data_layout_str);
3000
3001 enum ac_float_mode float_mode =
3002 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3003 AC_FLOAT_MODE_DEFAULT;
3004
3005 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3006
3007 memset(shader_info, 0, sizeof(*shader_info));
3008
3009 for(int i = 0; i < shader_count; ++i)
3010 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3011
3012 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3013 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3014 for (i = 0; i < AC_UD_MAX_UD; i++)
3015 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3016
3017 ctx.max_workgroup_size = 0;
3018 for (int i = 0; i < shader_count; ++i) {
3019 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3020 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3021 shaders[i]));
3022 }
3023
3024 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3025 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3026
3027 ctx.abi.inputs = &ctx.inputs[0];
3028 ctx.abi.emit_outputs = handle_shader_outputs_post;
3029 ctx.abi.emit_vertex = visit_emit_vertex;
3030 ctx.abi.load_ubo = radv_load_ubo;
3031 ctx.abi.load_ssbo = radv_load_ssbo;
3032 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3033 ctx.abi.load_resource = radv_load_resource;
3034 ctx.abi.clamp_shadow_reference = false;
3035
3036 if (shader_count >= 2)
3037 ac_init_exec_full_mask(&ctx.ac);
3038
3039 if (ctx.ac.chip_class == GFX9 &&
3040 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3041 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3042
3043 for(int i = 0; i < shader_count; ++i) {
3044 ctx.stage = shaders[i]->info.stage;
3045 ctx.output_mask = 0;
3046 ctx.tess_outputs_written = 0;
3047 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3048 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3049
3050 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3051 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3052 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3053 ctx.abi.load_inputs = load_gs_input;
3054 ctx.abi.emit_primitive = visit_end_primitive;
3055 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3056 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3057 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3058 ctx.abi.load_tess_varyings = load_tcs_varyings;
3059 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3060 ctx.abi.store_tcs_outputs = store_tcs_output;
3061 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3062 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3063 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3064 ctx.abi.load_tess_varyings = load_tes_input;
3065 ctx.abi.load_tess_coord = load_tess_coord;
3066 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3067 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3068 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3069 if (shader_info->info.vs.needs_instance_id) {
3070 if (ctx.options->key.vs.as_ls) {
3071 ctx.shader_info->vs.vgpr_comp_cnt =
3072 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3073 } else {
3074 ctx.shader_info->vs.vgpr_comp_cnt =
3075 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3076 }
3077 }
3078 ctx.abi.load_base_vertex = radv_load_base_vertex;
3079 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3080 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3081 ctx.abi.lookup_interp_param = lookup_interp_param;
3082 ctx.abi.load_sample_position = load_sample_position;
3083 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3084 ctx.abi.emit_kill = radv_emit_kill;
3085 }
3086
3087 if (i)
3088 ac_emit_barrier(&ctx.ac, ctx.stage);
3089
3090 ac_setup_rings(&ctx);
3091
3092 LLVMBasicBlockRef merge_block;
3093 if (shader_count >= 2) {
3094 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3095 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3096 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3097
3098 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3099 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3100 LLVMConstInt(ctx.ac.i32, 8, false), false);
3101 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3102 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3103 thread_id, count, "");
3104 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3105
3106 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3107 }
3108
3109 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3110 handle_fs_inputs(&ctx, shaders[i]);
3111 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3112 handle_vs_inputs(&ctx, shaders[i]);
3113 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3114 prepare_gs_input_vgprs(&ctx);
3115
3116 nir_foreach_variable(variable, &shaders[i]->outputs)
3117 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3118
3119 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3120
3121 if (shader_count >= 2) {
3122 LLVMBuildBr(ctx.ac.builder, merge_block);
3123 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3124 }
3125
3126 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3127 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3128 shaders[i]->info.cull_distance_array_size > 4;
3129 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3130 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
3131 shaders[i]->info.gs.vertices_out;
3132 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3133 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
3134 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
3135 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
3136 shader_info->vs.outputs_written = ctx.tess_outputs_written;
3137 }
3138 }
3139
3140 LLVMBuildRetVoid(ctx.ac.builder);
3141
3142 if (options->dump_preoptir)
3143 ac_dump_module(ctx.ac.module);
3144
3145 ac_llvm_finalize_module(&ctx);
3146
3147 if (shader_count == 1)
3148 ac_nir_eliminate_const_vs_outputs(&ctx);
3149
3150 if (dump_shader) {
3151 ctx.shader_info->private_mem_vgprs =
3152 ac_count_scratch_private_memory(ctx.main_function);
3153 }
3154
3155 return ctx.ac.module;
3156 }
3157
3158 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3159 {
3160 unsigned *retval = (unsigned *)context;
3161 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3162 char *description = LLVMGetDiagInfoDescription(di);
3163
3164 if (severity == LLVMDSError) {
3165 *retval = 1;
3166 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3167 description);
3168 }
3169
3170 LLVMDisposeMessage(description);
3171 }
3172
3173 static unsigned ac_llvm_compile(LLVMModuleRef M,
3174 struct ac_shader_binary *binary,
3175 LLVMTargetMachineRef tm)
3176 {
3177 unsigned retval = 0;
3178 char *err;
3179 LLVMContextRef llvm_ctx;
3180 LLVMMemoryBufferRef out_buffer;
3181 unsigned buffer_size;
3182 const char *buffer_data;
3183 LLVMBool mem_err;
3184
3185 /* Setup Diagnostic Handler*/
3186 llvm_ctx = LLVMGetModuleContext(M);
3187
3188 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3189 &retval);
3190
3191 /* Compile IR*/
3192 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
3193 &err, &out_buffer);
3194
3195 /* Process Errors/Warnings */
3196 if (mem_err) {
3197 fprintf(stderr, "%s: %s", __FUNCTION__, err);
3198 free(err);
3199 retval = 1;
3200 goto out;
3201 }
3202
3203 /* Extract Shader Code*/
3204 buffer_size = LLVMGetBufferSize(out_buffer);
3205 buffer_data = LLVMGetBufferStart(out_buffer);
3206
3207 ac_elf_read(buffer_data, buffer_size, binary);
3208
3209 /* Clean up */
3210 LLVMDisposeMemoryBuffer(out_buffer);
3211
3212 out:
3213 return retval;
3214 }
3215
3216 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
3217 LLVMModuleRef llvm_module,
3218 struct ac_shader_binary *binary,
3219 struct ac_shader_config *config,
3220 struct radv_shader_variant_info *shader_info,
3221 gl_shader_stage stage,
3222 bool dump_shader, bool supports_spill)
3223 {
3224 if (dump_shader)
3225 ac_dump_module(llvm_module);
3226
3227 memset(binary, 0, sizeof(*binary));
3228 int v = ac_llvm_compile(llvm_module, binary, tm);
3229 if (v) {
3230 fprintf(stderr, "compile failed\n");
3231 }
3232
3233 if (dump_shader)
3234 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3235
3236 ac_shader_binary_read_config(binary, config, 0, supports_spill);
3237
3238 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3239 LLVMDisposeModule(llvm_module);
3240 LLVMContextDispose(ctx);
3241
3242 if (stage == MESA_SHADER_FRAGMENT) {
3243 shader_info->num_input_vgprs = 0;
3244 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3245 shader_info->num_input_vgprs += 2;
3246 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3247 shader_info->num_input_vgprs += 2;
3248 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3249 shader_info->num_input_vgprs += 2;
3250 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3251 shader_info->num_input_vgprs += 3;
3252 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3253 shader_info->num_input_vgprs += 2;
3254 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3255 shader_info->num_input_vgprs += 2;
3256 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3257 shader_info->num_input_vgprs += 2;
3258 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3259 shader_info->num_input_vgprs += 1;
3260 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3261 shader_info->num_input_vgprs += 1;
3262 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3263 shader_info->num_input_vgprs += 1;
3264 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3265 shader_info->num_input_vgprs += 1;
3266 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3267 shader_info->num_input_vgprs += 1;
3268 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3269 shader_info->num_input_vgprs += 1;
3270 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3271 shader_info->num_input_vgprs += 1;
3272 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3273 shader_info->num_input_vgprs += 1;
3274 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3275 shader_info->num_input_vgprs += 1;
3276 }
3277 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3278
3279 /* +3 for scratch wave offset and VCC */
3280 config->num_sgprs = MAX2(config->num_sgprs,
3281 shader_info->num_input_sgprs + 3);
3282
3283 /* Enable 64-bit and 16-bit denormals, because there is no performance
3284 * cost.
3285 *
3286 * If denormals are enabled, all floating-point output modifiers are
3287 * ignored.
3288 *
3289 * Don't enable denormals for 32-bit floats, because:
3290 * - Floating-point output modifiers would be ignored by the hw.
3291 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3292 * have to stop using those.
3293 * - SI & CI would be very slow.
3294 */
3295 config->float_mode |= V_00B028_FP_64_DENORMS;
3296 }
3297
3298 static void
3299 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
3300 {
3301 switch (nir->info.stage) {
3302 case MESA_SHADER_COMPUTE:
3303 for (int i = 0; i < 3; ++i)
3304 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3305 break;
3306 case MESA_SHADER_FRAGMENT:
3307 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3308 break;
3309 case MESA_SHADER_GEOMETRY:
3310 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3311 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3312 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3313 shader_info->gs.invocations = nir->info.gs.invocations;
3314 break;
3315 case MESA_SHADER_TESS_EVAL:
3316 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3317 shader_info->tes.spacing = nir->info.tess.spacing;
3318 shader_info->tes.ccw = nir->info.tess.ccw;
3319 shader_info->tes.point_mode = nir->info.tess.point_mode;
3320 shader_info->tes.as_es = options->key.tes.as_es;
3321 break;
3322 case MESA_SHADER_TESS_CTRL:
3323 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3324 break;
3325 case MESA_SHADER_VERTEX:
3326 shader_info->vs.as_es = options->key.vs.as_es;
3327 shader_info->vs.as_ls = options->key.vs.as_ls;
3328 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3329 if (options->key.vs.as_ls)
3330 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3331 break;
3332 default:
3333 break;
3334 }
3335 }
3336
3337 void
3338 radv_compile_nir_shader(LLVMTargetMachineRef tm,
3339 struct ac_shader_binary *binary,
3340 struct ac_shader_config *config,
3341 struct radv_shader_variant_info *shader_info,
3342 struct nir_shader *const *nir,
3343 int nir_count,
3344 const struct ac_nir_compiler_options *options,
3345 bool dump_shader)
3346 {
3347
3348 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
3349 options, dump_shader);
3350
3351 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
3352 for (int i = 0; i < nir_count; ++i)
3353 ac_fill_shader_info(shader_info, nir[i], options);
3354
3355 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3356 if (options->chip_class == GFX9) {
3357 if (nir_count == 2 &&
3358 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3359 shader_info->gs.es_type = nir[0]->info.stage;
3360 }
3361 }
3362 }
3363
3364 static void
3365 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3366 {
3367 LLVMValueRef vtx_offset =
3368 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3369 LLVMConstInt(ctx->ac.i32, 4, false), "");
3370 int idx = 0;
3371
3372 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3373 int length = 4;
3374 int slot = idx;
3375 int slot_inc = 1;
3376 if (!(ctx->output_mask & (1ull << i)))
3377 continue;
3378
3379 if (i == VARYING_SLOT_CLIP_DIST0) {
3380 /* unpack clip and cull from a single set of slots */
3381 length = ctx->num_output_clips + ctx->num_output_culls;
3382 if (length > 4)
3383 slot_inc = 2;
3384 }
3385
3386 for (unsigned j = 0; j < length; j++) {
3387 LLVMValueRef value, soffset;
3388
3389 soffset = LLVMConstInt(ctx->ac.i32,
3390 (slot * 4 + j) *
3391 ctx->gs_max_out_vertices * 16 * 4, false);
3392
3393 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3394 1, ctx->ac.i32_0,
3395 vtx_offset, soffset,
3396 0, 1, 1, true, false);
3397
3398 LLVMBuildStore(ctx->ac.builder,
3399 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
3400 }
3401 idx += slot_inc;
3402 }
3403 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
3404 }
3405
3406 void
3407 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
3408 struct nir_shader *geom_shader,
3409 struct ac_shader_binary *binary,
3410 struct ac_shader_config *config,
3411 struct radv_shader_variant_info *shader_info,
3412 const struct ac_nir_compiler_options *options,
3413 bool dump_shader)
3414 {
3415 struct radv_shader_context ctx = {0};
3416 ctx.context = LLVMContextCreate();
3417 ctx.options = options;
3418 ctx.shader_info = shader_info;
3419
3420 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3421 options->family);
3422 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3423
3424 ctx.is_gs_copy_shader = true;
3425 LLVMSetTarget(ctx.ac.module, "amdgcn--");
3426
3427 enum ac_float_mode float_mode =
3428 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3429 AC_FLOAT_MODE_DEFAULT;
3430
3431 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3432 ctx.stage = MESA_SHADER_VERTEX;
3433
3434 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3435
3436 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3437 ac_setup_rings(&ctx);
3438
3439 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3440 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3441
3442 nir_foreach_variable(variable, &geom_shader->outputs) {
3443 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3444 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3445 variable, MESA_SHADER_VERTEX);
3446 }
3447
3448 ac_gs_copy_shader_emit(&ctx);
3449
3450 LLVMBuildRetVoid(ctx.ac.builder);
3451
3452 ac_llvm_finalize_module(&ctx);
3453
3454 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
3455 MESA_SHADER_VERTEX,
3456 dump_shader, options->supports_spill);
3457 }