projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
anv,radv: Drop XML workarounds for VK_ANDROID_native_buffer
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "nir/nir.h"
31
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35 #if HAVE_LLVM >= 0x0700
36 #include <llvm-c/Transforms/Utils.h>
37 #endif
38
39 #include "sid.h"
40 #include "gfx9d.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_llvm_build.h"
44 #include "ac_shader_abi.h"
45 #include "ac_shader_util.h"
46 #include "ac_exp_param.h"
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct radv_shader_context {
51 struct ac_llvm_context ac;
52 const struct radv_nir_compiler_options *options;
53 struct radv_shader_variant_info *shader_info;
54 struct ac_shader_abi abi;
55
56 unsigned max_workgroup_size;
57 LLVMContextRef context;
58 LLVMValueRef main_function;
59
60 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
61 LLVMValueRef ring_offsets;
62
63 LLVMValueRef vertex_buffers;
64 LLVMValueRef rel_auto_id;
65 LLVMValueRef vs_prim_id;
66 LLVMValueRef es2gs_offset;
67
68 LLVMValueRef oc_lds;
69 LLVMValueRef merged_wave_info;
70 LLVMValueRef tess_factor_offset;
71 LLVMValueRef tes_rel_patch_id;
72 LLVMValueRef tes_u;
73 LLVMValueRef tes_v;
74
75 LLVMValueRef gs2vs_offset;
76 LLVMValueRef gs_wave_id;
77 LLVMValueRef gs_vtx_offset[6];
78
79 LLVMValueRef esgs_ring;
80 LLVMValueRef gsvs_ring;
81 LLVMValueRef hs_ring_tess_offchip;
82 LLVMValueRef hs_ring_tess_factor;
83
84 LLVMValueRef sample_pos_offset;
85 LLVMValueRef persp_sample, persp_center, persp_centroid;
86 LLVMValueRef linear_sample, linear_center, linear_centroid;
87
88 gl_shader_stage stage;
89
90 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
91
92 uint64_t input_mask;
93 uint64_t output_mask;
94 uint8_t num_output_clips;
95 uint8_t num_output_culls;
96
97 bool is_gs_copy_shader;
98 LLVMValueRef gs_next_vertex;
99 unsigned gs_max_out_vertices;
100
101 unsigned tes_primitive_mode;
102
103 uint32_t tcs_patch_outputs_read;
104 uint64_t tcs_outputs_read;
105 uint32_t tcs_vertices_per_patch;
106 uint32_t tcs_num_inputs;
107 uint32_t tcs_num_patches;
108 uint32_t max_gsvs_emit_size;
109 uint32_t gsvs_vertex_size;
110 };
111
112 enum radeon_llvm_calling_convention {
113 RADEON_LLVM_AMDGPU_VS = 87,
114 RADEON_LLVM_AMDGPU_GS = 88,
115 RADEON_LLVM_AMDGPU_PS = 89,
116 RADEON_LLVM_AMDGPU_CS = 90,
117 RADEON_LLVM_AMDGPU_HS = 93,
118 };
119
120 static inline struct radv_shader_context *
121 radv_shader_context_from_abi(struct ac_shader_abi *abi)
122 {
123 struct radv_shader_context *ctx = NULL;
124 return container_of(abi, ctx, abi);
125 }
126
127 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
128 {
129 switch (ctx->stage) {
130 case MESA_SHADER_TESS_CTRL:
131 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
132 case MESA_SHADER_TESS_EVAL:
133 return ctx->tes_rel_patch_id;
134 break;
135 default:
136 unreachable("Illegal stage");
137 }
138 }
139
140 static unsigned
141 get_tcs_num_patches(struct radv_shader_context *ctx)
142 {
143 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
144 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
145 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
146 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
147 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
148 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
149 uint32_t output_vertex_size = num_tcs_outputs * 16;
150 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
151 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
152 unsigned num_patches;
153 unsigned hardware_lds_size;
154
155 /* Ensure that we only need one wave per SIMD so we don't need to check
156 * resource usage. Also ensures that the number of tcs in and out
157 * vertices per threadgroup are at most 256.
158 */
159 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
160 /* Make sure that the data fits in LDS. This assumes the shaders only
161 * use LDS for the inputs and outputs.
162 */
163 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
164 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
165 /* Make sure the output data fits in the offchip buffer */
166 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
167 /* Not necessary for correctness, but improves performance. The
168 * specific value is taken from the proprietary driver.
169 */
170 num_patches = MIN2(num_patches, 40);
171
172 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
173 if (ctx->options->chip_class == SI) {
174 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
175 num_patches = MIN2(num_patches, one_wave);
176 }
177 return num_patches;
178 }
179
180 static unsigned
181 calculate_tess_lds_size(struct radv_shader_context *ctx)
182 {
183 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
184 unsigned num_tcs_output_cp;
185 unsigned num_tcs_outputs, num_tcs_patch_outputs;
186 unsigned input_vertex_size, output_vertex_size;
187 unsigned input_patch_size, output_patch_size;
188 unsigned pervertex_output_patch_size;
189 unsigned output_patch0_offset;
190 unsigned num_patches;
191 unsigned lds_size;
192
193 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
194 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
195 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
196
197 input_vertex_size = ctx->tcs_num_inputs * 16;
198 output_vertex_size = num_tcs_outputs * 16;
199
200 input_patch_size = num_tcs_input_cp * input_vertex_size;
201
202 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
203 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
204
205 num_patches = ctx->tcs_num_patches;
206 output_patch0_offset = input_patch_size * num_patches;
207
208 lds_size = output_patch0_offset + output_patch_size * num_patches;
209 return lds_size;
210 }
211
212 /* Tessellation shaders pass outputs to the next shader using LDS.
213 *
214 * LS outputs = TCS inputs
215 * TCS outputs = TES inputs
216 *
217 * The LDS layout is:
218 * - TCS inputs for patch 0
219 * - TCS inputs for patch 1
220 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
221 * - ...
222 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
223 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
224 * - TCS outputs for patch 1
225 * - Per-patch TCS outputs for patch 1
226 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
227 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
228 * - ...
229 *
230 * All three shaders VS(LS), TCS, TES share the same LDS space.
231 */
232 static LLVMValueRef
233 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
234 {
235 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
236 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
237 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
238
239 input_patch_size /= 4;
240 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
241 }
242
243 static LLVMValueRef
244 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
245 {
246 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
247 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
248 uint32_t output_vertex_size = num_tcs_outputs * 16;
249 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
250 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
251 output_patch_size /= 4;
252 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
253 }
254
255 static LLVMValueRef
256 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
257 {
258 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
259 uint32_t output_vertex_size = num_tcs_outputs * 16;
260 output_vertex_size /= 4;
261 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
262 }
263
264 static LLVMValueRef
265 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
266 {
267 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
268 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
269 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
270 uint32_t output_patch0_offset = input_patch_size;
271 unsigned num_patches = ctx->tcs_num_patches;
272
273 output_patch0_offset *= num_patches;
274 output_patch0_offset /= 4;
275 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
276 }
277
278 static LLVMValueRef
279 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
280 {
281 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
282 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
283 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
284 uint32_t output_patch0_offset = input_patch_size;
285
286 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
287 uint32_t output_vertex_size = num_tcs_outputs * 16;
288 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
289 unsigned num_patches = ctx->tcs_num_patches;
290
291 output_patch0_offset *= num_patches;
292 output_patch0_offset += pervertex_output_patch_size;
293 output_patch0_offset /= 4;
294 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
295 }
296
297 static LLVMValueRef
298 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
299 {
300 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
301 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
302
303 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
304 }
305
306 static LLVMValueRef
307 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
308 {
309 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
310 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
311 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
312
313 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
314 LLVMBuildMul(ctx->ac.builder, patch_stride,
315 rel_patch_id, ""),
316 "");
317 }
318
319 static LLVMValueRef
320 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
321 {
322 LLVMValueRef patch0_patch_data_offset =
323 get_tcs_out_patch0_patch_data_offset(ctx);
324 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
325 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
326
327 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
328 LLVMBuildMul(ctx->ac.builder, patch_stride,
329 rel_patch_id, ""),
330 "");
331 }
332
333 #define MAX_ARGS 23
334 struct arg_info {
335 LLVMTypeRef types[MAX_ARGS];
336 LLVMValueRef *assign[MAX_ARGS];
337 unsigned array_params_mask;
338 uint8_t count;
339 uint8_t sgpr_count;
340 uint8_t num_sgprs_used;
341 uint8_t num_vgprs_used;
342 };
343
344 enum ac_arg_regfile {
345 ARG_SGPR,
346 ARG_VGPR,
347 };
348
349 static void
350 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
351 LLVMValueRef *param_ptr)
352 {
353 assert(info->count < MAX_ARGS);
354
355 info->assign[info->count] = param_ptr;
356 info->types[info->count] = type;
357 info->count++;
358
359 if (regfile == ARG_SGPR) {
360 info->num_sgprs_used += ac_get_type_size(type) / 4;
361 info->sgpr_count++;
362 } else {
363 assert(regfile == ARG_VGPR);
364 info->num_vgprs_used += ac_get_type_size(type) / 4;
365 }
366 }
367
368 static inline void
369 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
370 {
371 info->array_params_mask |= (1 << info->count);
372 add_arg(info, ARG_SGPR, type, param_ptr);
373 }
374
375 static void assign_arguments(LLVMValueRef main_function,
376 struct arg_info *info)
377 {
378 unsigned i;
379 for (i = 0; i < info->count; i++) {
380 if (info->assign[i])
381 *info->assign[i] = LLVMGetParam(main_function, i);
382 }
383 }
384
385 static LLVMValueRef
386 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
387 LLVMBuilderRef builder, LLVMTypeRef *return_types,
388 unsigned num_return_elems,
389 struct arg_info *args,
390 unsigned max_workgroup_size,
391 bool unsafe_math)
392 {
393 LLVMTypeRef main_function_type, ret_type;
394 LLVMBasicBlockRef main_function_body;
395
396 if (num_return_elems)
397 ret_type = LLVMStructTypeInContext(ctx, return_types,
398 num_return_elems, true);
399 else
400 ret_type = LLVMVoidTypeInContext(ctx);
401
402 /* Setup the function */
403 main_function_type =
404 LLVMFunctionType(ret_type, args->types, args->count, 0);
405 LLVMValueRef main_function =
406 LLVMAddFunction(module, "main", main_function_type);
407 main_function_body =
408 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
409 LLVMPositionBuilderAtEnd(builder, main_function_body);
410
411 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
412 for (unsigned i = 0; i < args->sgpr_count; ++i) {
413 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
414
415 if (args->array_params_mask & (1 << i)) {
416 LLVMValueRef P = LLVMGetParam(main_function, i);
417 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
418 ac_add_attr_dereferenceable(P, UINT64_MAX);
419 }
420 }
421
422 if (max_workgroup_size) {
423 ac_llvm_add_target_dep_function_attr(main_function,
424 "amdgpu-max-work-group-size",
425 max_workgroup_size);
426 }
427 if (unsafe_math) {
428 /* These were copied from some LLVM test. */
429 LLVMAddTargetDependentFunctionAttr(main_function,
430 "less-precise-fpmad",
431 "true");
432 LLVMAddTargetDependentFunctionAttr(main_function,
433 "no-infs-fp-math",
434 "true");
435 LLVMAddTargetDependentFunctionAttr(main_function,
436 "no-nans-fp-math",
437 "true");
438 LLVMAddTargetDependentFunctionAttr(main_function,
439 "unsafe-fp-math",
440 "true");
441 LLVMAddTargetDependentFunctionAttr(main_function,
442 "no-signed-zeros-fp-math",
443 "true");
444 }
445 return main_function;
446 }
447
448
449 static void
450 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
451 uint32_t indirect_offset)
452 {
453 ud_info->sgpr_idx = *sgpr_idx;
454 ud_info->num_sgprs = num_sgprs;
455 ud_info->indirect = indirect_offset > 0;
456 ud_info->indirect_offset = indirect_offset;
457 *sgpr_idx += num_sgprs;
458 }
459
460 static void
461 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
462 uint8_t num_sgprs)
463 {
464 struct radv_userdata_info *ud_info =
465 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
466 assert(ud_info);
467
468 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
469 }
470
471 static void
472 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
473 uint32_t indirect_offset)
474 {
475 struct radv_userdata_info *ud_info =
476 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
477 assert(ud_info);
478
479 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
480 }
481
482 struct user_sgpr_info {
483 bool need_ring_offsets;
484 uint8_t sgpr_count;
485 bool indirect_all_descriptor_sets;
486 };
487
488 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
489 gl_shader_stage stage)
490 {
491 switch (stage) {
492 case MESA_SHADER_VERTEX:
493 if (ctx->shader_info->info.needs_multiview_view_index ||
494 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
495 return true;
496 break;
497 case MESA_SHADER_TESS_EVAL:
498 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
499 return true;
500 break;
501 case MESA_SHADER_GEOMETRY:
502 case MESA_SHADER_TESS_CTRL:
503 if (ctx->shader_info->info.needs_multiview_view_index)
504 return true;
505 break;
506 default:
507 break;
508 }
509 return false;
510 }
511
512 static uint8_t
513 count_vs_user_sgprs(struct radv_shader_context *ctx)
514 {
515 uint8_t count = 0;
516
517 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
518 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
519
520 return count;
521 }
522
523 static void allocate_user_sgprs(struct radv_shader_context *ctx,
524 gl_shader_stage stage,
525 bool has_previous_stage,
526 gl_shader_stage previous_stage,
527 bool needs_view_index,
528 struct user_sgpr_info *user_sgpr_info)
529 {
530 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
531
532 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
533 if (stage == MESA_SHADER_GEOMETRY ||
534 stage == MESA_SHADER_VERTEX ||
535 stage == MESA_SHADER_TESS_CTRL ||
536 stage == MESA_SHADER_TESS_EVAL ||
537 ctx->is_gs_copy_shader)
538 user_sgpr_info->need_ring_offsets = true;
539
540 if (stage == MESA_SHADER_FRAGMENT &&
541 ctx->shader_info->info.ps.needs_sample_positions)
542 user_sgpr_info->need_ring_offsets = true;
543
544 /* 2 user sgprs will nearly always be allocated for scratch/rings */
545 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
546 user_sgpr_info->sgpr_count += 2;
547 }
548
549 switch (stage) {
550 case MESA_SHADER_COMPUTE:
551 if (ctx->shader_info->info.cs.uses_grid_size)
552 user_sgpr_info->sgpr_count += 3;
553 break;
554 case MESA_SHADER_FRAGMENT:
555 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
556 break;
557 case MESA_SHADER_VERTEX:
558 if (!ctx->is_gs_copy_shader)
559 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
560 break;
561 case MESA_SHADER_TESS_CTRL:
562 if (has_previous_stage) {
563 if (previous_stage == MESA_SHADER_VERTEX)
564 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
565 }
566 break;
567 case MESA_SHADER_TESS_EVAL:
568 break;
569 case MESA_SHADER_GEOMETRY:
570 if (has_previous_stage) {
571 if (previous_stage == MESA_SHADER_VERTEX) {
572 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
573 }
574 }
575 break;
576 default:
577 break;
578 }
579
580 if (needs_view_index)
581 user_sgpr_info->sgpr_count++;
582
583 if (ctx->shader_info->info.loads_push_constants)
584 user_sgpr_info->sgpr_count += 2;
585
586 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
587 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
588
589 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
590 user_sgpr_info->sgpr_count += 2;
591 user_sgpr_info->indirect_all_descriptor_sets = true;
592 } else {
593 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
594 }
595 }
596
597 static void
598 declare_global_input_sgprs(struct radv_shader_context *ctx,
599 gl_shader_stage stage,
600 bool has_previous_stage,
601 gl_shader_stage previous_stage,
602 const struct user_sgpr_info *user_sgpr_info,
603 struct arg_info *args,
604 LLVMValueRef *desc_sets)
605 {
606 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
607 unsigned num_sets = ctx->options->layout ?
608 ctx->options->layout->num_sets : 0;
609 unsigned stage_mask = 1 << stage;
610
611 if (has_previous_stage)
612 stage_mask |= 1 << previous_stage;
613
614 /* 1 for each descriptor set */
615 if (!user_sgpr_info->indirect_all_descriptor_sets) {
616 for (unsigned i = 0; i < num_sets; ++i) {
617 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
618 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
619 add_array_arg(args, type,
620 &ctx->descriptor_sets[i]);
621 }
622 }
623 } else {
624 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
625 }
626
627 if (ctx->shader_info->info.loads_push_constants) {
628 /* 1 for push constants and dynamic descriptors */
629 add_array_arg(args, type, &ctx->abi.push_constants);
630 }
631 }
632
633 static void
634 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
635 gl_shader_stage stage,
636 bool has_previous_stage,
637 gl_shader_stage previous_stage,
638 struct arg_info *args)
639 {
640 if (!ctx->is_gs_copy_shader &&
641 (stage == MESA_SHADER_VERTEX ||
642 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
643 if (ctx->shader_info->info.vs.has_vertex_buffers) {
644 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
645 &ctx->vertex_buffers);
646 }
647 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
648 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
649 if (ctx->shader_info->info.vs.needs_draw_id) {
650 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
651 }
652 }
653 }
654
655 static void
656 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
657 {
658 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
659 if (!ctx->is_gs_copy_shader) {
660 if (ctx->options->key.vs.as_ls) {
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
662 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
663 } else {
664 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
665 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
666 }
667 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
668 }
669 }
670
671 static void
672 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
673 {
674 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
675 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
676 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
678 }
679
680 static void
681 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
682 bool has_previous_stage, gl_shader_stage previous_stage,
683 const struct user_sgpr_info *user_sgpr_info,
684 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
685 {
686 unsigned num_sets = ctx->options->layout ?
687 ctx->options->layout->num_sets : 0;
688 unsigned stage_mask = 1 << stage;
689
690 if (has_previous_stage)
691 stage_mask |= 1 << previous_stage;
692
693 if (!user_sgpr_info->indirect_all_descriptor_sets) {
694 for (unsigned i = 0; i < num_sets; ++i) {
695 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
696 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
697 set_loc_desc(ctx, i, user_sgpr_idx, 0);
698 } else
699 ctx->descriptor_sets[i] = NULL;
700 }
701 } else {
702 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
703 user_sgpr_idx, 2);
704
705 for (unsigned i = 0; i < num_sets; ++i) {
706 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
707 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
708 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
709 ctx->descriptor_sets[i] =
710 ac_build_load_to_sgpr(&ctx->ac,
711 desc_sets,
712 LLVMConstInt(ctx->ac.i32, i, false));
713
714 } else
715 ctx->descriptor_sets[i] = NULL;
716 }
717 ctx->shader_info->need_indirect_descriptor_sets = true;
718 }
719
720 if (ctx->shader_info->info.loads_push_constants) {
721 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
722 }
723 }
724
725 static void
726 set_vs_specific_input_locs(struct radv_shader_context *ctx,
727 gl_shader_stage stage, bool has_previous_stage,
728 gl_shader_stage previous_stage,
729 uint8_t *user_sgpr_idx)
730 {
731 if (!ctx->is_gs_copy_shader &&
732 (stage == MESA_SHADER_VERTEX ||
733 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
734 if (ctx->shader_info->info.vs.has_vertex_buffers) {
735 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
736 user_sgpr_idx, 2);
737 }
738
739 unsigned vs_num = 2;
740 if (ctx->shader_info->info.vs.needs_draw_id)
741 vs_num++;
742
743 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
744 user_sgpr_idx, vs_num);
745 }
746 }
747
748 static void set_llvm_calling_convention(LLVMValueRef func,
749 gl_shader_stage stage)
750 {
751 enum radeon_llvm_calling_convention calling_conv;
752
753 switch (stage) {
754 case MESA_SHADER_VERTEX:
755 case MESA_SHADER_TESS_EVAL:
756 calling_conv = RADEON_LLVM_AMDGPU_VS;
757 break;
758 case MESA_SHADER_GEOMETRY:
759 calling_conv = RADEON_LLVM_AMDGPU_GS;
760 break;
761 case MESA_SHADER_TESS_CTRL:
762 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
763 break;
764 case MESA_SHADER_FRAGMENT:
765 calling_conv = RADEON_LLVM_AMDGPU_PS;
766 break;
767 case MESA_SHADER_COMPUTE:
768 calling_conv = RADEON_LLVM_AMDGPU_CS;
769 break;
770 default:
771 unreachable("Unhandle shader type");
772 }
773
774 LLVMSetFunctionCallConv(func, calling_conv);
775 }
776
777 static void create_function(struct radv_shader_context *ctx,
778 gl_shader_stage stage,
779 bool has_previous_stage,
780 gl_shader_stage previous_stage)
781 {
782 uint8_t user_sgpr_idx;
783 struct user_sgpr_info user_sgpr_info;
784 struct arg_info args = {};
785 LLVMValueRef desc_sets;
786 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
787 allocate_user_sgprs(ctx, stage, has_previous_stage,
788 previous_stage, needs_view_index, &user_sgpr_info);
789
790 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
791 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
792 &ctx->ring_offsets);
793 }
794
795 switch (stage) {
796 case MESA_SHADER_COMPUTE:
797 declare_global_input_sgprs(ctx, stage, has_previous_stage,
798 previous_stage, &user_sgpr_info,
799 &args, &desc_sets);
800
801 if (ctx->shader_info->info.cs.uses_grid_size) {
802 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
803 &ctx->abi.num_work_groups);
804 }
805
806 for (int i = 0; i < 3; i++) {
807 ctx->abi.workgroup_ids[i] = NULL;
808 if (ctx->shader_info->info.cs.uses_block_id[i]) {
809 add_arg(&args, ARG_SGPR, ctx->ac.i32,
810 &ctx->abi.workgroup_ids[i]);
811 }
812 }
813
814 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
816 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
817 &ctx->abi.local_invocation_ids);
818 break;
819 case MESA_SHADER_VERTEX:
820 declare_global_input_sgprs(ctx, stage, has_previous_stage,
821 previous_stage, &user_sgpr_info,
822 &args, &desc_sets);
823 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
824 previous_stage, &args);
825
826 if (needs_view_index)
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->abi.view_index);
829 if (ctx->options->key.vs.as_es)
830 add_arg(&args, ARG_SGPR, ctx->ac.i32,
831 &ctx->es2gs_offset);
832
833 declare_vs_input_vgprs(ctx, &args);
834 break;
835 case MESA_SHADER_TESS_CTRL:
836 if (has_previous_stage) {
837 // First 6 system regs
838 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->merged_wave_info);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tess_factor_offset);
843
844 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
845 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
846 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
847
848 declare_global_input_sgprs(ctx, stage,
849 has_previous_stage,
850 previous_stage,
851 &user_sgpr_info, &args,
852 &desc_sets);
853 declare_vs_specific_input_sgprs(ctx, stage,
854 has_previous_stage,
855 previous_stage, &args);
856
857 if (needs_view_index)
858 add_arg(&args, ARG_SGPR, ctx->ac.i32,
859 &ctx->abi.view_index);
860
861 add_arg(&args, ARG_VGPR, ctx->ac.i32,
862 &ctx->abi.tcs_patch_id);
863 add_arg(&args, ARG_VGPR, ctx->ac.i32,
864 &ctx->abi.tcs_rel_ids);
865
866 declare_vs_input_vgprs(ctx, &args);
867 } else {
868 declare_global_input_sgprs(ctx, stage,
869 has_previous_stage,
870 previous_stage,
871 &user_sgpr_info, &args,
872 &desc_sets);
873
874 if (needs_view_index)
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->abi.view_index);
877
878 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
879 add_arg(&args, ARG_SGPR, ctx->ac.i32,
880 &ctx->tess_factor_offset);
881 add_arg(&args, ARG_VGPR, ctx->ac.i32,
882 &ctx->abi.tcs_patch_id);
883 add_arg(&args, ARG_VGPR, ctx->ac.i32,
884 &ctx->abi.tcs_rel_ids);
885 }
886 break;
887 case MESA_SHADER_TESS_EVAL:
888 declare_global_input_sgprs(ctx, stage, has_previous_stage,
889 previous_stage, &user_sgpr_info,
890 &args, &desc_sets);
891
892 if (needs_view_index)
893 add_arg(&args, ARG_SGPR, ctx->ac.i32,
894 &ctx->abi.view_index);
895
896 if (ctx->options->key.tes.as_es) {
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
898 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
899 add_arg(&args, ARG_SGPR, ctx->ac.i32,
900 &ctx->es2gs_offset);
901 } else {
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
903 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
904 }
905 declare_tes_input_vgprs(ctx, &args);
906 break;
907 case MESA_SHADER_GEOMETRY:
908 if (has_previous_stage) {
909 // First 6 system regs
910 add_arg(&args, ARG_SGPR, ctx->ac.i32,
911 &ctx->gs2vs_offset);
912 add_arg(&args, ARG_SGPR, ctx->ac.i32,
913 &ctx->merged_wave_info);
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
915
916 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
917 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
918 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
919
920 declare_global_input_sgprs(ctx, stage,
921 has_previous_stage,
922 previous_stage,
923 &user_sgpr_info, &args,
924 &desc_sets);
925
926 if (previous_stage != MESA_SHADER_TESS_EVAL) {
927 declare_vs_specific_input_sgprs(ctx, stage,
928 has_previous_stage,
929 previous_stage,
930 &args);
931 }
932
933 if (needs_view_index)
934 add_arg(&args, ARG_SGPR, ctx->ac.i32,
935 &ctx->abi.view_index);
936
937 add_arg(&args, ARG_VGPR, ctx->ac.i32,
938 &ctx->gs_vtx_offset[0]);
939 add_arg(&args, ARG_VGPR, ctx->ac.i32,
940 &ctx->gs_vtx_offset[2]);
941 add_arg(&args, ARG_VGPR, ctx->ac.i32,
942 &ctx->abi.gs_prim_id);
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->abi.gs_invocation_id);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->gs_vtx_offset[4]);
947
948 if (previous_stage == MESA_SHADER_VERTEX) {
949 declare_vs_input_vgprs(ctx, &args);
950 } else {
951 declare_tes_input_vgprs(ctx, &args);
952 }
953 } else {
954 declare_global_input_sgprs(ctx, stage,
955 has_previous_stage,
956 previous_stage,
957 &user_sgpr_info, &args,
958 &desc_sets);
959
960 if (needs_view_index)
961 add_arg(&args, ARG_SGPR, ctx->ac.i32,
962 &ctx->abi.view_index);
963
964 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
965 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
966 add_arg(&args, ARG_VGPR, ctx->ac.i32,
967 &ctx->gs_vtx_offset[0]);
968 add_arg(&args, ARG_VGPR, ctx->ac.i32,
969 &ctx->gs_vtx_offset[1]);
970 add_arg(&args, ARG_VGPR, ctx->ac.i32,
971 &ctx->abi.gs_prim_id);
972 add_arg(&args, ARG_VGPR, ctx->ac.i32,
973 &ctx->gs_vtx_offset[2]);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[3]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[4]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->gs_vtx_offset[5]);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->abi.gs_invocation_id);
982 }
983 break;
984 case MESA_SHADER_FRAGMENT:
985 declare_global_input_sgprs(ctx, stage, has_previous_stage,
986 previous_stage, &user_sgpr_info,
987 &args, &desc_sets);
988
989 if (ctx->shader_info->info.ps.needs_sample_positions)
990 add_arg(&args, ARG_SGPR, ctx->ac.i32,
991 &ctx->sample_pos_offset);
992
993 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
994 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
995 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
996 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
997 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
998 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
999 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1000 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1001 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1002 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1003 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1004 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1005 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1006 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1007 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1008 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1009 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1010 break;
1011 default:
1012 unreachable("Shader stage not implemented");
1013 }
1014
1015 ctx->main_function = create_llvm_function(
1016 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1017 ctx->max_workgroup_size,
1018 ctx->options->unsafe_math);
1019 set_llvm_calling_convention(ctx->main_function, stage);
1020
1021
1022 ctx->shader_info->num_input_vgprs = 0;
1023 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1024
1025 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1026
1027 if (ctx->stage != MESA_SHADER_FRAGMENT)
1028 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1029
1030 assign_arguments(ctx->main_function, &args);
1031
1032 user_sgpr_idx = 0;
1033
1034 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1035 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1036 &user_sgpr_idx, 2);
1037 if (ctx->options->supports_spill) {
1038 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1039 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1040 NULL, 0, AC_FUNC_ATTR_READNONE);
1041 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1042 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1043 }
1044 }
1045
1046 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1047 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1048 if (has_previous_stage)
1049 user_sgpr_idx = 0;
1050
1051 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1052 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1053
1054 switch (stage) {
1055 case MESA_SHADER_COMPUTE:
1056 if (ctx->shader_info->info.cs.uses_grid_size) {
1057 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1058 &user_sgpr_idx, 3);
1059 }
1060 break;
1061 case MESA_SHADER_VERTEX:
1062 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1063 previous_stage, &user_sgpr_idx);
1064 if (ctx->abi.view_index)
1065 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1066 break;
1067 case MESA_SHADER_TESS_CTRL:
1068 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1069 previous_stage, &user_sgpr_idx);
1070 if (ctx->abi.view_index)
1071 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1072 break;
1073 case MESA_SHADER_TESS_EVAL:
1074 if (ctx->abi.view_index)
1075 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1076 break;
1077 case MESA_SHADER_GEOMETRY:
1078 if (has_previous_stage) {
1079 if (previous_stage == MESA_SHADER_VERTEX)
1080 set_vs_specific_input_locs(ctx, stage,
1081 has_previous_stage,
1082 previous_stage,
1083 &user_sgpr_idx);
1084 }
1085 if (ctx->abi.view_index)
1086 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1087 break;
1088 case MESA_SHADER_FRAGMENT:
1089 if (ctx->shader_info->info.ps.needs_sample_positions) {
1090 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1091 &user_sgpr_idx, 1);
1092 }
1093 break;
1094 default:
1095 unreachable("Shader stage not implemented");
1096 }
1097
1098 if (stage == MESA_SHADER_TESS_CTRL ||
1099 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1100 /* GFX9 has the ESGS ring buffer in LDS. */
1101 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1102 ac_declare_lds_as_pointer(&ctx->ac);
1103 }
1104
1105 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1106 }
1107
1108
1109 static LLVMValueRef
1110 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1111 unsigned desc_set, unsigned binding)
1112 {
1113 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1114 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1115 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1116 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1117 unsigned base_offset = layout->binding[binding].offset;
1118 LLVMValueRef offset, stride;
1119
1120 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1121 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1122 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1123 layout->binding[binding].dynamic_offset_offset;
1124 desc_ptr = ctx->abi.push_constants;
1125 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1126 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1127 } else
1128 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1129
1130 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1131 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
1132 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
1133
1134 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1135 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1136 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1137
1138 return desc_ptr;
1139 }
1140
1141
1142 /* The offchip buffer layout for TCS->TES is
1143 *
1144 * - attribute 0 of patch 0 vertex 0
1145 * - attribute 0 of patch 0 vertex 1
1146 * - attribute 0 of patch 0 vertex 2
1147 * ...
1148 * - attribute 0 of patch 1 vertex 0
1149 * - attribute 0 of patch 1 vertex 1
1150 * ...
1151 * - attribute 1 of patch 0 vertex 0
1152 * - attribute 1 of patch 0 vertex 1
1153 * ...
1154 * - per patch attribute 0 of patch 0
1155 * - per patch attribute 0 of patch 1
1156 * ...
1157 *
1158 * Note that every attribute has 4 components.
1159 */
1160 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1161 {
1162 uint32_t num_patches = ctx->tcs_num_patches;
1163 uint32_t num_tcs_outputs;
1164 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1165 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1166 else
1167 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1168
1169 uint32_t output_vertex_size = num_tcs_outputs * 16;
1170 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1171
1172 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1173 }
1174
1175 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1176 LLVMValueRef vertex_index)
1177 {
1178 LLVMValueRef param_stride;
1179 if (vertex_index)
1180 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1181 else
1182 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1183 return param_stride;
1184 }
1185
1186 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1187 LLVMValueRef vertex_index,
1188 LLVMValueRef param_index)
1189 {
1190 LLVMValueRef base_addr;
1191 LLVMValueRef param_stride, constant16;
1192 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1193 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1194 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1195 param_stride = calc_param_stride(ctx, vertex_index);
1196 if (vertex_index) {
1197 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
1198 vertices_per_patch, "");
1199
1200 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1201 vertex_index, "");
1202 } else {
1203 base_addr = rel_patch_id;
1204 }
1205
1206 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1207 LLVMBuildMul(ctx->ac.builder, param_index,
1208 param_stride, ""), "");
1209
1210 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1211
1212 if (!vertex_index) {
1213 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1214
1215 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1216 patch_data_offset, "");
1217 }
1218 return base_addr;
1219 }
1220
1221 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1222 unsigned param,
1223 unsigned const_index,
1224 bool is_compact,
1225 LLVMValueRef vertex_index,
1226 LLVMValueRef indir_index)
1227 {
1228 LLVMValueRef param_index;
1229
1230 if (indir_index)
1231 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1232 indir_index, "");
1233 else {
1234 if (const_index && !is_compact)
1235 param += const_index;
1236 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1237 }
1238 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1239 }
1240
1241 static LLVMValueRef
1242 get_dw_address(struct radv_shader_context *ctx,
1243 LLVMValueRef dw_addr,
1244 unsigned param,
1245 unsigned const_index,
1246 bool compact_const_index,
1247 LLVMValueRef vertex_index,
1248 LLVMValueRef stride,
1249 LLVMValueRef indir_index)
1250
1251 {
1252
1253 if (vertex_index) {
1254 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1255 LLVMBuildMul(ctx->ac.builder,
1256 vertex_index,
1257 stride, ""), "");
1258 }
1259
1260 if (indir_index)
1261 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1262 LLVMBuildMul(ctx->ac.builder, indir_index,
1263 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1264 else if (const_index && !compact_const_index)
1265 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1266 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1267
1268 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1269 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1270
1271 if (const_index && compact_const_index)
1272 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1273 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1274 return dw_addr;
1275 }
1276
1277 static LLVMValueRef
1278 load_tcs_varyings(struct ac_shader_abi *abi,
1279 LLVMTypeRef type,
1280 LLVMValueRef vertex_index,
1281 LLVMValueRef indir_index,
1282 unsigned const_index,
1283 unsigned location,
1284 unsigned driver_location,
1285 unsigned component,
1286 unsigned num_components,
1287 bool is_patch,
1288 bool is_compact,
1289 bool load_input)
1290 {
1291 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1292 LLVMValueRef dw_addr, stride;
1293 LLVMValueRef value[4], result;
1294 unsigned param = shader_io_get_unique_index(location);
1295
1296 if (load_input) {
1297 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1298 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1299 dw_addr = get_tcs_in_current_patch_offset(ctx);
1300 } else {
1301 if (!is_patch) {
1302 stride = get_tcs_out_vertex_stride(ctx);
1303 dw_addr = get_tcs_out_current_patch_offset(ctx);
1304 } else {
1305 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1306 stride = NULL;
1307 }
1308 }
1309
1310 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1311 indir_index);
1312
1313 for (unsigned i = 0; i < num_components + component; i++) {
1314 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1315 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1316 ctx->ac.i32_1, "");
1317 }
1318 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1319 return result;
1320 }
1321
1322 static void
1323 store_tcs_output(struct ac_shader_abi *abi,
1324 const nir_variable *var,
1325 LLVMValueRef vertex_index,
1326 LLVMValueRef param_index,
1327 unsigned const_index,
1328 LLVMValueRef src,
1329 unsigned writemask)
1330 {
1331 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1332 const unsigned location = var->data.location;
1333 const unsigned component = var->data.location_frac;
1334 const bool is_patch = var->data.patch;
1335 const bool is_compact = var->data.compact;
1336 LLVMValueRef dw_addr;
1337 LLVMValueRef stride = NULL;
1338 LLVMValueRef buf_addr = NULL;
1339 unsigned param;
1340 bool store_lds = true;
1341
1342 if (is_patch) {
1343 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1344 store_lds = false;
1345 } else {
1346 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1347 store_lds = false;
1348 }
1349
1350 param = shader_io_get_unique_index(location);
1351 if (location == VARYING_SLOT_CLIP_DIST0 &&
1352 is_compact && const_index > 3) {
1353 const_index -= 3;
1354 param++;
1355 }
1356
1357 if (!is_patch) {
1358 stride = get_tcs_out_vertex_stride(ctx);
1359 dw_addr = get_tcs_out_current_patch_offset(ctx);
1360 } else {
1361 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1362 }
1363
1364 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1365 param_index);
1366 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1367 vertex_index, param_index);
1368
1369 bool is_tess_factor = false;
1370 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1371 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1372 is_tess_factor = true;
1373
1374 unsigned base = is_compact ? const_index : 0;
1375 for (unsigned chan = 0; chan < 8; chan++) {
1376 if (!(writemask & (1 << chan)))
1377 continue;
1378 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1379
1380 if (store_lds || is_tess_factor) {
1381 LLVMValueRef dw_addr_chan =
1382 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1383 LLVMConstInt(ctx->ac.i32, chan, false), "");
1384 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1385 }
1386
1387 if (!is_tess_factor && writemask != 0xF)
1388 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1389 buf_addr, ctx->oc_lds,
1390 4 * (base + chan), 1, 0, true, false);
1391 }
1392
1393 if (writemask == 0xF) {
1394 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1395 buf_addr, ctx->oc_lds,
1396 (base * 4), 1, 0, true, false);
1397 }
1398 }
1399
1400 static LLVMValueRef
1401 load_tes_input(struct ac_shader_abi *abi,
1402 LLVMTypeRef type,
1403 LLVMValueRef vertex_index,
1404 LLVMValueRef param_index,
1405 unsigned const_index,
1406 unsigned location,
1407 unsigned driver_location,
1408 unsigned component,
1409 unsigned num_components,
1410 bool is_patch,
1411 bool is_compact,
1412 bool load_input)
1413 {
1414 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1415 LLVMValueRef buf_addr;
1416 LLVMValueRef result;
1417 unsigned param = shader_io_get_unique_index(location);
1418
1419 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1420 const_index -= 3;
1421 param++;
1422 }
1423
1424 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1425 is_compact, vertex_index, param_index);
1426
1427 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1428 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1429
1430 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1431 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1432 result = ac_trim_vector(&ctx->ac, result, num_components);
1433 return result;
1434 }
1435
1436 static LLVMValueRef
1437 load_gs_input(struct ac_shader_abi *abi,
1438 unsigned location,
1439 unsigned driver_location,
1440 unsigned component,
1441 unsigned num_components,
1442 unsigned vertex_index,
1443 unsigned const_index,
1444 LLVMTypeRef type)
1445 {
1446 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1447 LLVMValueRef vtx_offset;
1448 unsigned param, vtx_offset_param;
1449 LLVMValueRef value[4], result;
1450
1451 vtx_offset_param = vertex_index;
1452 assert(vtx_offset_param < 6);
1453 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1454 LLVMConstInt(ctx->ac.i32, 4, false), "");
1455
1456 param = shader_io_get_unique_index(location);
1457
1458 for (unsigned i = component; i < num_components + component; i++) {
1459 if (ctx->ac.chip_class >= GFX9) {
1460 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1461 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1462 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1463 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1464 } else {
1465 LLVMValueRef soffset =
1466 LLVMConstInt(ctx->ac.i32,
1467 (param * 4 + i + const_index) * 256,
1468 false);
1469
1470 value[i] = ac_build_buffer_load(&ctx->ac,
1471 ctx->esgs_ring, 1,
1472 ctx->ac.i32_0,
1473 vtx_offset, soffset,
1474 0, 1, 0, true, false);
1475
1476 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
1477 type, "");
1478 }
1479 }
1480 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1481 result = ac_to_integer(&ctx->ac, result);
1482 return result;
1483 }
1484
1485
1486 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1487 {
1488 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1489 ac_build_kill_if_false(&ctx->ac, visible);
1490 }
1491
1492 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1493 enum glsl_interp_mode interp, unsigned location)
1494 {
1495 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1496
1497 switch (interp) {
1498 case INTERP_MODE_FLAT:
1499 default:
1500 return NULL;
1501 case INTERP_MODE_SMOOTH:
1502 case INTERP_MODE_NONE:
1503 if (location == INTERP_CENTER)
1504 return ctx->persp_center;
1505 else if (location == INTERP_CENTROID)
1506 return ctx->persp_centroid;
1507 else if (location == INTERP_SAMPLE)
1508 return ctx->persp_sample;
1509 break;
1510 case INTERP_MODE_NOPERSPECTIVE:
1511 if (location == INTERP_CENTER)
1512 return ctx->linear_center;
1513 else if (location == INTERP_CENTROID)
1514 return ctx->linear_centroid;
1515 else if (location == INTERP_SAMPLE)
1516 return ctx->linear_sample;
1517 break;
1518 }
1519 return NULL;
1520 }
1521
1522 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1523 LLVMValueRef sample_id)
1524 {
1525 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1526
1527 LLVMValueRef result;
1528 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1529
1530 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1531 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1532
1533 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
1534 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1535
1536 return result;
1537 }
1538
1539
1540 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1541 {
1542 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1543 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
1544 ctx->options->key.fs.log2_num_samples :
1545 ctx->options->key.fs.log2_ps_iter_samples;
1546
1547 /* The bit pattern matches that used by fixed function fragment
1548 * processing. */
1549 static const uint16_t ps_iter_masks[] = {
1550 0xffff, /* not used */
1551 0x5555,
1552 0x1111,
1553 0x0101,
1554 0x0001,
1555 };
1556 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1557
1558 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1559
1560 LLVMValueRef result, sample_id;
1561 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1562 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1563 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1564 return result;
1565 }
1566
1567
1568 static void
1569 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1570 {
1571 LLVMValueRef gs_next_vertex;
1572 LLVMValueRef can_emit;
1573 int idx;
1574 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1575
1576 assert(stream == 0);
1577
1578 /* Write vertex attribute values to GSVS ring */
1579 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1580 ctx->gs_next_vertex,
1581 "");
1582
1583 /* If this thread has already emitted the declared maximum number of
1584 * vertices, kill it: excessive vertex emissions are not supposed to
1585 * have any effect, and GS threads have no externally observable
1586 * effects other than emitting vertices.
1587 */
1588 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1589 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1590 ac_build_kill_if_false(&ctx->ac, can_emit);
1591
1592 /* loop num outputs */
1593 idx = 0;
1594 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1595 LLVMValueRef *out_ptr = &addrs[i * 4];
1596 int length = 4;
1597 int slot = idx;
1598 int slot_inc = 1;
1599
1600 if (!(ctx->output_mask & (1ull << i)))
1601 continue;
1602
1603 if (i == VARYING_SLOT_CLIP_DIST0) {
1604 /* pack clip and cull into a single set of slots */
1605 length = ctx->num_output_clips + ctx->num_output_culls;
1606 if (length > 4)
1607 slot_inc = 2;
1608 }
1609 for (unsigned j = 0; j < length; j++) {
1610 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1611 out_ptr[j], "");
1612 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1613 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1614 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1615
1616 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1617
1618 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1619 out_val, 1,
1620 voffset, ctx->gs2vs_offset, 0,
1621 1, 1, true, true);
1622 }
1623 idx += slot_inc;
1624 }
1625
1626 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1627 ctx->ac.i32_1, "");
1628 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1629
1630 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1631 }
1632
1633 static void
1634 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1635 {
1636 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1637 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1638 }
1639
1640 static LLVMValueRef
1641 load_tess_coord(struct ac_shader_abi *abi)
1642 {
1643 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1644
1645 LLVMValueRef coord[4] = {
1646 ctx->tes_u,
1647 ctx->tes_v,
1648 ctx->ac.f32_0,
1649 ctx->ac.f32_0,
1650 };
1651
1652 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1653 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1654 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1655
1656 return ac_build_gather_values(&ctx->ac, coord, 3);
1657 }
1658
1659 static LLVMValueRef
1660 load_patch_vertices_in(struct ac_shader_abi *abi)
1661 {
1662 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1663 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1664 }
1665
1666
1667 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1668 {
1669 return abi->base_vertex;
1670 }
1671
1672 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1673 LLVMValueRef buffer_ptr, bool write)
1674 {
1675 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1676 LLVMValueRef result;
1677
1678 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1679
1680 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1681 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1682
1683 return result;
1684 }
1685
1686 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1687 {
1688 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1689 LLVMValueRef result;
1690
1691 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1692
1693 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1694 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1695
1696 return result;
1697 }
1698
1699 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1700 unsigned descriptor_set,
1701 unsigned base_index,
1702 unsigned constant_index,
1703 LLVMValueRef index,
1704 enum ac_descriptor_type desc_type,
1705 bool image, bool write,
1706 bool bindless)
1707 {
1708 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1709 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1710 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1711 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1712 unsigned offset = binding->offset;
1713 unsigned stride = binding->size;
1714 unsigned type_size;
1715 LLVMBuilderRef builder = ctx->ac.builder;
1716 LLVMTypeRef type;
1717
1718 assert(base_index < layout->binding_count);
1719
1720 switch (desc_type) {
1721 case AC_DESC_IMAGE:
1722 type = ctx->ac.v8i32;
1723 type_size = 32;
1724 break;
1725 case AC_DESC_FMASK:
1726 type = ctx->ac.v8i32;
1727 offset += 32;
1728 type_size = 32;
1729 break;
1730 case AC_DESC_SAMPLER:
1731 type = ctx->ac.v4i32;
1732 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1733 offset += 64;
1734
1735 type_size = 16;
1736 break;
1737 case AC_DESC_BUFFER:
1738 type = ctx->ac.v4i32;
1739 type_size = 16;
1740 break;
1741 default:
1742 unreachable("invalid desc_type\n");
1743 }
1744
1745 offset += constant_index * stride;
1746
1747 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1748 (!index || binding->immutable_samplers_equal)) {
1749 if (binding->immutable_samplers_equal)
1750 constant_index = 0;
1751
1752 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1753
1754 LLVMValueRef constants[] = {
1755 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1756 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1757 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1758 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1759 };
1760 return ac_build_gather_values(&ctx->ac, constants, 4);
1761 }
1762
1763 assert(stride % type_size == 0);
1764
1765 if (!index)
1766 index = ctx->ac.i32_0;
1767
1768 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1769
1770 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1771 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
1772
1773 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1774 }
1775
1776
1777 static void
1778 handle_vs_input_decl(struct radv_shader_context *ctx,
1779 struct nir_variable *variable)
1780 {
1781 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1782 LLVMValueRef t_offset;
1783 LLVMValueRef t_list;
1784 LLVMValueRef input;
1785 LLVMValueRef buffer_index;
1786 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
1787 int idx = variable->data.location;
1788 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1789 uint8_t input_usage_mask =
1790 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1791 unsigned num_channels = util_last_bit(input_usage_mask);
1792
1793 variable->data.driver_location = idx * 4;
1794
1795 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
1796 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
1797 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[index + i];
1798
1799 if (divisor) {
1800 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
1801 ctx->abi.start_instance, "");
1802
1803 if (divisor != 1) {
1804 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1805 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1806 }
1807
1808 if (ctx->options->key.vs.as_ls) {
1809 ctx->shader_info->vs.vgpr_comp_cnt =
1810 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1811 } else {
1812 ctx->shader_info->vs.vgpr_comp_cnt =
1813 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1814 }
1815 } else {
1816 buffer_index = ctx->ac.i32_0;
1817 }
1818 } else
1819 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
1820 ctx->abi.base_vertex, "");
1821 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
1822
1823 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1824
1825 input = ac_build_buffer_load_format(&ctx->ac, t_list,
1826 buffer_index,
1827 ctx->ac.i32_0,
1828 num_channels, false, true);
1829
1830 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
1831
1832 for (unsigned chan = 0; chan < 4; chan++) {
1833 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1834 ctx->inputs[ac_llvm_reg_index_soa(idx, chan)] =
1835 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
1836 input, llvm_chan, ""));
1837 }
1838 }
1839 }
1840
1841 static void interp_fs_input(struct radv_shader_context *ctx,
1842 unsigned attr,
1843 LLVMValueRef interp_param,
1844 LLVMValueRef prim_mask,
1845 LLVMValueRef result[4])
1846 {
1847 LLVMValueRef attr_number;
1848 unsigned chan;
1849 LLVMValueRef i, j;
1850 bool interp = interp_param != NULL;
1851
1852 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
1853
1854 /* fs.constant returns the param from the middle vertex, so it's not
1855 * really useful for flat shading. It's meant to be used for custom
1856 * interpolation (but the intrinsic can't fetch from the other two
1857 * vertices).
1858 *
1859 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1860 * to do the right thing. The only reason we use fs.constant is that
1861 * fs.interp cannot be used on integers, because they can be equal
1862 * to NaN.
1863 */
1864 if (interp) {
1865 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1866 ctx->ac.v2f32, "");
1867
1868 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1869 ctx->ac.i32_0, "");
1870 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1871 ctx->ac.i32_1, "");
1872 }
1873
1874 for (chan = 0; chan < 4; chan++) {
1875 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1876
1877 if (interp) {
1878 result[chan] = ac_build_fs_interp(&ctx->ac,
1879 llvm_chan,
1880 attr_number,
1881 prim_mask, i, j);
1882 } else {
1883 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1884 LLVMConstInt(ctx->ac.i32, 2, false),
1885 llvm_chan,
1886 attr_number,
1887 prim_mask);
1888 }
1889 }
1890 }
1891
1892 static void
1893 handle_fs_input_decl(struct radv_shader_context *ctx,
1894 struct nir_variable *variable)
1895 {
1896 int idx = variable->data.location;
1897 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1898 LLVMValueRef interp;
1899
1900 variable->data.driver_location = idx * 4;
1901 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
1902
1903 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
1904 unsigned interp_type;
1905 if (variable->data.sample)
1906 interp_type = INTERP_SAMPLE;
1907 else if (variable->data.centroid)
1908 interp_type = INTERP_CENTROID;
1909 else
1910 interp_type = INTERP_CENTER;
1911
1912 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
1913 } else
1914 interp = NULL;
1915
1916 for (unsigned i = 0; i < attrib_count; ++i)
1917 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
1918
1919 }
1920
1921 static void
1922 handle_vs_inputs(struct radv_shader_context *ctx,
1923 struct nir_shader *nir) {
1924 nir_foreach_variable(variable, &nir->inputs)
1925 handle_vs_input_decl(ctx, variable);
1926 }
1927
1928 static void
1929 prepare_interp_optimize(struct radv_shader_context *ctx,
1930 struct nir_shader *nir)
1931 {
1932 if (!ctx->options->key.fs.multisample)
1933 return;
1934
1935 bool uses_center = false;
1936 bool uses_centroid = false;
1937 nir_foreach_variable(variable, &nir->inputs) {
1938 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1939 variable->data.sample)
1940 continue;
1941
1942 if (variable->data.centroid)
1943 uses_centroid = true;
1944 else
1945 uses_center = true;
1946 }
1947
1948 if (uses_center && uses_centroid) {
1949 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
1950 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
1951 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
1952 }
1953 }
1954
1955 static void
1956 handle_fs_inputs(struct radv_shader_context *ctx,
1957 struct nir_shader *nir)
1958 {
1959 prepare_interp_optimize(ctx, nir);
1960
1961 nir_foreach_variable(variable, &nir->inputs)
1962 handle_fs_input_decl(ctx, variable);
1963
1964 unsigned index = 0;
1965
1966 if (ctx->shader_info->info.ps.uses_input_attachments ||
1967 ctx->shader_info->info.needs_multiview_view_index)
1968 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
1969
1970 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
1971 LLVMValueRef interp_param;
1972 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
1973
1974 if (!(ctx->input_mask & (1ull << i)))
1975 continue;
1976
1977 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
1978 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
1979 interp_param = *inputs;
1980 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
1981 inputs);
1982
1983 if (!interp_param)
1984 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
1985 ++index;
1986 } else if (i == VARYING_SLOT_POS) {
1987 for(int i = 0; i < 3; ++i)
1988 inputs[i] = ctx->abi.frag_pos[i];
1989
1990 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
1991 ctx->abi.frag_pos[3]);
1992 }
1993 }
1994 ctx->shader_info->fs.num_interp = index;
1995 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
1996
1997 if (ctx->shader_info->info.needs_multiview_view_index)
1998 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
1999 }
2000
2001 static void
2002 scan_shader_output_decl(struct radv_shader_context *ctx,
2003 struct nir_variable *variable,
2004 struct nir_shader *shader,
2005 gl_shader_stage stage)
2006 {
2007 int idx = variable->data.location + variable->data.index;
2008 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2009 uint64_t mask_attribs;
2010
2011 variable->data.driver_location = idx * 4;
2012
2013 /* tess ctrl has it's own load/store paths for outputs */
2014 if (stage == MESA_SHADER_TESS_CTRL)
2015 return;
2016
2017 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2018 if (stage == MESA_SHADER_VERTEX ||
2019 stage == MESA_SHADER_TESS_EVAL ||
2020 stage == MESA_SHADER_GEOMETRY) {
2021 if (idx == VARYING_SLOT_CLIP_DIST0) {
2022 int length = shader->info.clip_distance_array_size +
2023 shader->info.cull_distance_array_size;
2024 if (stage == MESA_SHADER_VERTEX) {
2025 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2026 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2027 }
2028 if (stage == MESA_SHADER_TESS_EVAL) {
2029 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2030 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2031 }
2032
2033 if (length > 4)
2034 attrib_count = 2;
2035 else
2036 attrib_count = 1;
2037 mask_attribs = 1ull << idx;
2038 }
2039 }
2040
2041 ctx->output_mask |= mask_attribs;
2042 }
2043
2044
2045 /* Initialize arguments for the shader export intrinsic */
2046 static void
2047 si_llvm_init_export_args(struct radv_shader_context *ctx,
2048 LLVMValueRef *values,
2049 unsigned enabled_channels,
2050 unsigned target,
2051 struct ac_export_args *args)
2052 {
2053 /* Specify the channels that are enabled. */
2054 args->enabled_channels = enabled_channels;
2055
2056 /* Specify whether the EXEC mask represents the valid mask */
2057 args->valid_mask = 0;
2058
2059 /* Specify whether this is the last export */
2060 args->done = 0;
2061
2062 /* Specify the target we are exporting */
2063 args->target = target;
2064
2065 args->compr = false;
2066 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2067 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2068 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2069 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2070
2071 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2072 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2073 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2074 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2075 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2076 unsigned chan;
2077
2078 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2079 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2080 unsigned bits, bool hi) = NULL;
2081
2082 switch(col_format) {
2083 case V_028714_SPI_SHADER_ZERO:
2084 args->enabled_channels = 0; /* writemask */
2085 args->target = V_008DFC_SQ_EXP_NULL;
2086 break;
2087
2088 case V_028714_SPI_SHADER_32_R:
2089 args->enabled_channels = 1;
2090 args->out[0] = values[0];
2091 break;
2092
2093 case V_028714_SPI_SHADER_32_GR:
2094 args->enabled_channels = 0x3;
2095 args->out[0] = values[0];
2096 args->out[1] = values[1];
2097 break;
2098
2099 case V_028714_SPI_SHADER_32_AR:
2100 args->enabled_channels = 0x9;
2101 args->out[0] = values[0];
2102 args->out[3] = values[3];
2103 break;
2104
2105 case V_028714_SPI_SHADER_FP16_ABGR:
2106 args->enabled_channels = 0x5;
2107 packf = ac_build_cvt_pkrtz_f16;
2108 break;
2109
2110 case V_028714_SPI_SHADER_UNORM16_ABGR:
2111 args->enabled_channels = 0x5;
2112 packf = ac_build_cvt_pknorm_u16;
2113 break;
2114
2115 case V_028714_SPI_SHADER_SNORM16_ABGR:
2116 args->enabled_channels = 0x5;
2117 packf = ac_build_cvt_pknorm_i16;
2118 break;
2119
2120 case V_028714_SPI_SHADER_UINT16_ABGR:
2121 args->enabled_channels = 0x5;
2122 packi = ac_build_cvt_pk_u16;
2123 break;
2124
2125 case V_028714_SPI_SHADER_SINT16_ABGR:
2126 args->enabled_channels = 0x5;
2127 packi = ac_build_cvt_pk_i16;
2128 break;
2129
2130 default:
2131 case V_028714_SPI_SHADER_32_ABGR:
2132 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2133 break;
2134 }
2135
2136 /* Pack f16 or norm_i16/u16. */
2137 if (packf) {
2138 for (chan = 0; chan < 2; chan++) {
2139 LLVMValueRef pack_args[2] = {
2140 values[2 * chan],
2141 values[2 * chan + 1]
2142 };
2143 LLVMValueRef packed;
2144
2145 packed = packf(&ctx->ac, pack_args);
2146 args->out[chan] = ac_to_float(&ctx->ac, packed);
2147 }
2148 args->compr = 1; /* COMPR flag */
2149 }
2150
2151 /* Pack i16/u16. */
2152 if (packi) {
2153 for (chan = 0; chan < 2; chan++) {
2154 LLVMValueRef pack_args[2] = {
2155 ac_to_integer(&ctx->ac, values[2 * chan]),
2156 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2157 };
2158 LLVMValueRef packed;
2159
2160 packed = packi(&ctx->ac, pack_args,
2161 is_int8 ? 8 : is_int10 ? 10 : 16,
2162 chan == 1);
2163 args->out[chan] = ac_to_float(&ctx->ac, packed);
2164 }
2165 args->compr = 1; /* COMPR flag */
2166 }
2167 return;
2168 }
2169
2170 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2171
2172 for (unsigned i = 0; i < 4; ++i) {
2173 if (!(args->enabled_channels & (1 << i)))
2174 continue;
2175
2176 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2177 }
2178 }
2179
2180 static void
2181 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2182 LLVMValueRef *values, unsigned enabled_channels)
2183 {
2184 struct ac_export_args args;
2185
2186 si_llvm_init_export_args(ctx, values, enabled_channels,
2187 V_008DFC_SQ_EXP_PARAM + index, &args);
2188 ac_build_export(&ctx->ac, &args);
2189 }
2190
2191 static LLVMValueRef
2192 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2193 {
2194 LLVMValueRef output =
2195 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2196
2197 return LLVMBuildLoad(ctx->ac.builder, output, "");
2198 }
2199
2200 static void
2201 handle_vs_outputs_post(struct radv_shader_context *ctx,
2202 bool export_prim_id, bool export_layer_id,
2203 struct radv_vs_output_info *outinfo)
2204 {
2205 uint32_t param_count = 0;
2206 unsigned target;
2207 unsigned pos_idx, num_pos_exports = 0;
2208 struct ac_export_args args, pos_args[4] = {};
2209 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2210 int i;
2211
2212 if (ctx->options->key.has_multiview_view_index) {
2213 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2214 if(!*tmp_out) {
2215 for(unsigned i = 0; i < 4; ++i)
2216 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2217 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2218 }
2219
2220 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2221 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2222 }
2223
2224 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2225 sizeof(outinfo->vs_output_param_offset));
2226
2227 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2228 LLVMValueRef slots[8];
2229 unsigned j;
2230
2231 if (outinfo->cull_dist_mask)
2232 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2233
2234 i = VARYING_SLOT_CLIP_DIST0;
2235 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
2236 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2237
2238 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
2239 slots[i] = LLVMGetUndef(ctx->ac.f32);
2240
2241 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
2242 target = V_008DFC_SQ_EXP_POS + 3;
2243 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2244 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2245 &args, sizeof(args));
2246 }
2247
2248 target = V_008DFC_SQ_EXP_POS + 2;
2249 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2250 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2251 &args, sizeof(args));
2252
2253 }
2254
2255 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2256 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2257 for (unsigned j = 0; j < 4; j++)
2258 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2259 }
2260 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2261
2262 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2263 outinfo->writes_pointsize = true;
2264 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2265 }
2266
2267 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2268 outinfo->writes_layer = true;
2269 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2270 }
2271
2272 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2273 outinfo->writes_viewport_index = true;
2274 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2275 }
2276
2277 if (outinfo->writes_pointsize ||
2278 outinfo->writes_layer ||
2279 outinfo->writes_viewport_index) {
2280 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2281 (outinfo->writes_layer == true ? 4 : 0));
2282 pos_args[1].valid_mask = 0;
2283 pos_args[1].done = 0;
2284 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2285 pos_args[1].compr = 0;
2286 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2287 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2288 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2289 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2290
2291 if (outinfo->writes_pointsize == true)
2292 pos_args[1].out[0] = psize_value;
2293 if (outinfo->writes_layer == true)
2294 pos_args[1].out[2] = layer_value;
2295 if (outinfo->writes_viewport_index == true) {
2296 if (ctx->options->chip_class >= GFX9) {
2297 /* GFX9 has the layer in out.z[10:0] and the viewport
2298 * index in out.z[19:16].
2299 */
2300 LLVMValueRef v = viewport_index_value;
2301 v = ac_to_integer(&ctx->ac, v);
2302 v = LLVMBuildShl(ctx->ac.builder, v,
2303 LLVMConstInt(ctx->ac.i32, 16, false),
2304 "");
2305 v = LLVMBuildOr(ctx->ac.builder, v,
2306 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2307
2308 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2309 pos_args[1].enabled_channels |= 1 << 2;
2310 } else {
2311 pos_args[1].out[3] = viewport_index_value;
2312 pos_args[1].enabled_channels |= 1 << 3;
2313 }
2314 }
2315 }
2316 for (i = 0; i < 4; i++) {
2317 if (pos_args[i].out[0])
2318 num_pos_exports++;
2319 }
2320
2321 pos_idx = 0;
2322 for (i = 0; i < 4; i++) {
2323 if (!pos_args[i].out[0])
2324 continue;
2325
2326 /* Specify the target we are exporting */
2327 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2328 if (pos_idx == num_pos_exports)
2329 pos_args[i].done = 1;
2330 ac_build_export(&ctx->ac, &pos_args[i]);
2331 }
2332
2333 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2334 LLVMValueRef values[4];
2335 if (!(ctx->output_mask & (1ull << i)))
2336 continue;
2337
2338 if (i != VARYING_SLOT_LAYER &&
2339 i != VARYING_SLOT_PRIMITIVE_ID &&
2340 i < VARYING_SLOT_VAR0)
2341 continue;
2342
2343 for (unsigned j = 0; j < 4; j++)
2344 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2345
2346 unsigned output_usage_mask;
2347
2348 if (ctx->stage == MESA_SHADER_VERTEX &&
2349 !ctx->is_gs_copy_shader) {
2350 output_usage_mask =
2351 ctx->shader_info->info.vs.output_usage_mask[i];
2352 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2353 output_usage_mask =
2354 ctx->shader_info->info.tes.output_usage_mask[i];
2355 } else {
2356 /* Enable all channels for the GS copy shader because
2357 * we don't know the output usage mask currently.
2358 */
2359 output_usage_mask = 0xf;
2360 }
2361
2362 radv_export_param(ctx, param_count, values, output_usage_mask);
2363
2364 outinfo->vs_output_param_offset[i] = param_count++;
2365 }
2366
2367 if (export_prim_id) {
2368 LLVMValueRef values[4];
2369
2370 values[0] = ctx->vs_prim_id;
2371 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2372 ctx->shader_info->vs.vgpr_comp_cnt);
2373 for (unsigned j = 1; j < 4; j++)
2374 values[j] = ctx->ac.f32_0;
2375
2376 radv_export_param(ctx, param_count, values, 0x1);
2377
2378 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2379 outinfo->export_prim_id = true;
2380 }
2381
2382 if (export_layer_id && layer_value) {
2383 LLVMValueRef values[4];
2384
2385 values[0] = layer_value;
2386 for (unsigned j = 1; j < 4; j++)
2387 values[j] = ctx->ac.f32_0;
2388
2389 radv_export_param(ctx, param_count, values, 0x1);
2390
2391 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2392 }
2393
2394 outinfo->pos_exports = num_pos_exports;
2395 outinfo->param_exports = param_count;
2396 }
2397
2398 static void
2399 handle_es_outputs_post(struct radv_shader_context *ctx,
2400 struct radv_es_output_info *outinfo)
2401 {
2402 int j;
2403 uint64_t max_output_written = 0;
2404 LLVMValueRef lds_base = NULL;
2405
2406 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2407 int param_index;
2408 int length = 4;
2409
2410 if (!(ctx->output_mask & (1ull << i)))
2411 continue;
2412
2413 if (i == VARYING_SLOT_CLIP_DIST0)
2414 length = ctx->num_output_clips + ctx->num_output_culls;
2415
2416 param_index = shader_io_get_unique_index(i);
2417
2418 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2419 }
2420
2421 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2422
2423 if (ctx->ac.chip_class >= GFX9) {
2424 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2425 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2426 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2427 LLVMConstInt(ctx->ac.i32, 24, false),
2428 LLVMConstInt(ctx->ac.i32, 4, false), false);
2429 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2430 LLVMBuildMul(ctx->ac.builder, wave_idx,
2431 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2432 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2433 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2434 }
2435
2436 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2437 LLVMValueRef dw_addr = NULL;
2438 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2439 int param_index;
2440 int length = 4;
2441
2442 if (!(ctx->output_mask & (1ull << i)))
2443 continue;
2444
2445 if (i == VARYING_SLOT_CLIP_DIST0)
2446 length = ctx->num_output_clips + ctx->num_output_culls;
2447
2448 param_index = shader_io_get_unique_index(i);
2449
2450 if (lds_base) {
2451 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2452 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2453 "");
2454 }
2455 for (j = 0; j < length; j++) {
2456 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2457 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2458
2459 if (ctx->ac.chip_class >= GFX9) {
2460 ac_lds_store(&ctx->ac, dw_addr,
2461 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2462 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2463 } else {
2464 ac_build_buffer_store_dword(&ctx->ac,
2465 ctx->esgs_ring,
2466 out_val, 1,
2467 NULL, ctx->es2gs_offset,
2468 (4 * param_index + j) * 4,
2469 1, 1, true, true);
2470 }
2471 }
2472 }
2473 }
2474
2475 static void
2476 handle_ls_outputs_post(struct radv_shader_context *ctx)
2477 {
2478 LLVMValueRef vertex_id = ctx->rel_auto_id;
2479 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2480 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2481 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2482 vertex_dw_stride, "");
2483
2484 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2485 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2486 int length = 4;
2487
2488 if (!(ctx->output_mask & (1ull << i)))
2489 continue;
2490
2491 if (i == VARYING_SLOT_CLIP_DIST0)
2492 length = ctx->num_output_clips + ctx->num_output_culls;
2493 int param = shader_io_get_unique_index(i);
2494 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2495 LLVMConstInt(ctx->ac.i32, param * 4, false),
2496 "");
2497 for (unsigned j = 0; j < length; j++) {
2498 ac_lds_store(&ctx->ac, dw_addr,
2499 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2500 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2501 }
2502 }
2503 }
2504
2505 struct ac_build_if_state
2506 {
2507 struct radv_shader_context *ctx;
2508 LLVMValueRef condition;
2509 LLVMBasicBlockRef entry_block;
2510 LLVMBasicBlockRef true_block;
2511 LLVMBasicBlockRef false_block;
2512 LLVMBasicBlockRef merge_block;
2513 };
2514
2515 static LLVMBasicBlockRef
2516 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
2517 {
2518 LLVMBasicBlockRef current_block;
2519 LLVMBasicBlockRef next_block;
2520 LLVMBasicBlockRef new_block;
2521
2522 /* get current basic block */
2523 current_block = LLVMGetInsertBlock(ctx->ac.builder);
2524
2525 /* chqeck if there's another block after this one */
2526 next_block = LLVMGetNextBasicBlock(current_block);
2527 if (next_block) {
2528 /* insert the new block before the next block */
2529 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
2530 }
2531 else {
2532 /* append new block after current block */
2533 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
2534 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
2535 }
2536 return new_block;
2537 }
2538
2539 static void
2540 ac_nir_build_if(struct ac_build_if_state *ifthen,
2541 struct radv_shader_context *ctx,
2542 LLVMValueRef condition)
2543 {
2544 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
2545
2546 memset(ifthen, 0, sizeof *ifthen);
2547 ifthen->ctx = ctx;
2548 ifthen->condition = condition;
2549 ifthen->entry_block = block;
2550
2551 /* create endif/merge basic block for the phi functions */
2552 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
2553
2554 /* create/insert true_block before merge_block */
2555 ifthen->true_block =
2556 LLVMInsertBasicBlockInContext(ctx->context,
2557 ifthen->merge_block,
2558 "if-true-block");
2559
2560 /* successive code goes into the true block */
2561 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
2562 }
2563
2564 /**
2565 * End a conditional.
2566 */
2567 static void
2568 ac_nir_build_endif(struct ac_build_if_state *ifthen)
2569 {
2570 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
2571
2572 /* Insert branch to the merge block from current block */
2573 LLVMBuildBr(builder, ifthen->merge_block);
2574
2575 /*
2576 * Now patch in the various branch instructions.
2577 */
2578
2579 /* Insert the conditional branch instruction at the end of entry_block */
2580 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
2581 if (ifthen->false_block) {
2582 /* we have an else clause */
2583 LLVMBuildCondBr(builder, ifthen->condition,
2584 ifthen->true_block, ifthen->false_block);
2585 }
2586 else {
2587 /* no else clause */
2588 LLVMBuildCondBr(builder, ifthen->condition,
2589 ifthen->true_block, ifthen->merge_block);
2590 }
2591
2592 /* Resume building code at end of the ifthen->merge_block */
2593 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
2594 }
2595
2596 static void
2597 write_tess_factors(struct radv_shader_context *ctx)
2598 {
2599 unsigned stride, outer_comps, inner_comps;
2600 struct ac_build_if_state if_ctx, inner_if_ctx;
2601 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2602 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2603 unsigned tess_inner_index = 0, tess_outer_index;
2604 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2605 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2606 int i;
2607 ac_emit_barrier(&ctx->ac, ctx->stage);
2608
2609 switch (ctx->options->key.tcs.primitive_mode) {
2610 case GL_ISOLINES:
2611 stride = 2;
2612 outer_comps = 2;
2613 inner_comps = 0;
2614 break;
2615 case GL_TRIANGLES:
2616 stride = 4;
2617 outer_comps = 3;
2618 inner_comps = 1;
2619 break;
2620 case GL_QUADS:
2621 stride = 6;
2622 outer_comps = 4;
2623 inner_comps = 2;
2624 break;
2625 default:
2626 return;
2627 }
2628
2629 ac_nir_build_if(&if_ctx, ctx,
2630 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2631 invocation_id, ctx->ac.i32_0, ""));
2632
2633 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2634
2635 if (inner_comps) {
2636 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2637 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2638 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2639 }
2640
2641 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2642 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2643 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2644
2645 for (i = 0; i < 4; i++) {
2646 inner[i] = LLVMGetUndef(ctx->ac.i32);
2647 outer[i] = LLVMGetUndef(ctx->ac.i32);
2648 }
2649
2650 // LINES reverseal
2651 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2652 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2653 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2654 ctx->ac.i32_1, "");
2655 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2656 } else {
2657 for (i = 0; i < outer_comps; i++) {
2658 outer[i] = out[i] =
2659 ac_lds_load(&ctx->ac, lds_outer);
2660 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2661 ctx->ac.i32_1, "");
2662 }
2663 for (i = 0; i < inner_comps; i++) {
2664 inner[i] = out[outer_comps+i] =
2665 ac_lds_load(&ctx->ac, lds_inner);
2666 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2667 ctx->ac.i32_1, "");
2668 }
2669 }
2670
2671 /* Convert the outputs to vectors for stores. */
2672 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2673 vec1 = NULL;
2674
2675 if (stride > 4)
2676 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2677
2678
2679 buffer = ctx->hs_ring_tess_factor;
2680 tf_base = ctx->tess_factor_offset;
2681 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2682 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2683 unsigned tf_offset = 0;
2684
2685 if (ctx->options->chip_class <= VI) {
2686 ac_nir_build_if(&inner_if_ctx, ctx,
2687 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2688 rel_patch_id, ctx->ac.i32_0, ""));
2689
2690 /* Store the dynamic HS control word. */
2691 ac_build_buffer_store_dword(&ctx->ac, buffer,
2692 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2693 1, ctx->ac.i32_0, tf_base,
2694 0, 1, 0, true, false);
2695 tf_offset += 4;
2696
2697 ac_nir_build_endif(&inner_if_ctx);
2698 }
2699
2700 /* Store the tessellation factors. */
2701 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2702 MIN2(stride, 4), byteoffset, tf_base,
2703 tf_offset, 1, 0, true, false);
2704 if (vec1)
2705 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2706 stride - 4, byteoffset, tf_base,
2707 16 + tf_offset, 1, 0, true, false);
2708
2709 //store to offchip for TES to read - only if TES reads them
2710 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2711 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2712 LLVMValueRef tf_inner_offset;
2713 unsigned param_outer, param_inner;
2714
2715 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2716 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2717 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2718
2719 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2720 util_next_power_of_two(outer_comps));
2721
2722 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2723 outer_comps, tf_outer_offset,
2724 ctx->oc_lds, 0, 1, 0, true, false);
2725 if (inner_comps) {
2726 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2727 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2728 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2729
2730 inner_vec = inner_comps == 1 ? inner[0] :
2731 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2732 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2733 inner_comps, tf_inner_offset,
2734 ctx->oc_lds, 0, 1, 0, true, false);
2735 }
2736 }
2737 ac_nir_build_endif(&if_ctx);
2738 }
2739
2740 static void
2741 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2742 {
2743 write_tess_factors(ctx);
2744 }
2745
2746 static bool
2747 si_export_mrt_color(struct radv_shader_context *ctx,
2748 LLVMValueRef *color, unsigned index,
2749 struct ac_export_args *args)
2750 {
2751 /* Export */
2752 si_llvm_init_export_args(ctx, color, 0xf,
2753 V_008DFC_SQ_EXP_MRT + index, args);
2754 if (!args->enabled_channels)
2755 return false; /* unnecessary NULL export */
2756
2757 return true;
2758 }
2759
2760 static void
2761 radv_export_mrt_z(struct radv_shader_context *ctx,
2762 LLVMValueRef depth, LLVMValueRef stencil,
2763 LLVMValueRef samplemask)
2764 {
2765 struct ac_export_args args;
2766
2767 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2768
2769 ac_build_export(&ctx->ac, &args);
2770 }
2771
2772 static void
2773 handle_fs_outputs_post(struct radv_shader_context *ctx)
2774 {
2775 unsigned index = 0;
2776 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2777 struct ac_export_args color_args[8];
2778
2779 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2780 LLVMValueRef values[4];
2781
2782 if (!(ctx->output_mask & (1ull << i)))
2783 continue;
2784
2785 if (i < FRAG_RESULT_DATA0)
2786 continue;
2787
2788 for (unsigned j = 0; j < 4; j++)
2789 values[j] = ac_to_float(&ctx->ac,
2790 radv_load_output(ctx, i, j));
2791
2792 bool ret = si_export_mrt_color(ctx, values,
2793 i - FRAG_RESULT_DATA0,
2794 &color_args[index]);
2795 if (ret)
2796 index++;
2797 }
2798
2799 /* Process depth, stencil, samplemask. */
2800 if (ctx->shader_info->info.ps.writes_z) {
2801 depth = ac_to_float(&ctx->ac,
2802 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
2803 }
2804 if (ctx->shader_info->info.ps.writes_stencil) {
2805 stencil = ac_to_float(&ctx->ac,
2806 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
2807 }
2808 if (ctx->shader_info->info.ps.writes_sample_mask) {
2809 samplemask = ac_to_float(&ctx->ac,
2810 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
2811 }
2812
2813 /* Set the DONE bit on last non-null color export only if Z isn't
2814 * exported.
2815 */
2816 if (index > 0 &&
2817 !ctx->shader_info->info.ps.writes_z &&
2818 !ctx->shader_info->info.ps.writes_stencil &&
2819 !ctx->shader_info->info.ps.writes_sample_mask) {
2820 unsigned last = index - 1;
2821
2822 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
2823 color_args[last].done = 1; /* DONE bit */
2824 }
2825
2826 /* Export PS outputs. */
2827 for (unsigned i = 0; i < index; i++)
2828 ac_build_export(&ctx->ac, &color_args[i]);
2829
2830 if (depth || stencil || samplemask)
2831 radv_export_mrt_z(ctx, depth, stencil, samplemask);
2832 else if (!index)
2833 ac_build_export_null(&ctx->ac);
2834 }
2835
2836 static void
2837 emit_gs_epilogue(struct radv_shader_context *ctx)
2838 {
2839 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
2840 }
2841
2842 static void
2843 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
2844 LLVMValueRef *addrs)
2845 {
2846 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2847
2848 switch (ctx->stage) {
2849 case MESA_SHADER_VERTEX:
2850 if (ctx->options->key.vs.as_ls)
2851 handle_ls_outputs_post(ctx);
2852 else if (ctx->options->key.vs.as_es)
2853 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
2854 else
2855 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
2856 ctx->options->key.vs.export_layer_id,
2857 &ctx->shader_info->vs.outinfo);
2858 break;
2859 case MESA_SHADER_FRAGMENT:
2860 handle_fs_outputs_post(ctx);
2861 break;
2862 case MESA_SHADER_GEOMETRY:
2863 emit_gs_epilogue(ctx);
2864 break;
2865 case MESA_SHADER_TESS_CTRL:
2866 handle_tcs_outputs_post(ctx);
2867 break;
2868 case MESA_SHADER_TESS_EVAL:
2869 if (ctx->options->key.tes.as_es)
2870 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
2871 else
2872 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
2873 ctx->options->key.tes.export_layer_id,
2874 &ctx->shader_info->tes.outinfo);
2875 break;
2876 default:
2877 break;
2878 }
2879 }
2880
2881 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
2882 {
2883 LLVMPassManagerRef passmgr;
2884 /* Create the pass manager */
2885 passmgr = LLVMCreateFunctionPassManagerForModule(
2886 ctx->ac.module);
2887
2888 /* This pass should eliminate all the load and store instructions */
2889 LLVMAddPromoteMemoryToRegisterPass(passmgr);
2890
2891 /* Add some optimization passes */
2892 LLVMAddScalarReplAggregatesPass(passmgr);
2893 LLVMAddLICMPass(passmgr);
2894 LLVMAddAggressiveDCEPass(passmgr);
2895 LLVMAddCFGSimplificationPass(passmgr);
2896 LLVMAddInstructionCombiningPass(passmgr);
2897
2898 /* Run the pass */
2899 LLVMInitializeFunctionPassManager(passmgr);
2900 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
2901 LLVMFinalizeFunctionPassManager(passmgr);
2902
2903 LLVMDisposeBuilder(ctx->ac.builder);
2904 LLVMDisposePassManager(passmgr);
2905
2906 ac_llvm_context_dispose(&ctx->ac);
2907 }
2908
2909 static void
2910 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
2911 {
2912 struct radv_vs_output_info *outinfo;
2913
2914 switch (ctx->stage) {
2915 case MESA_SHADER_FRAGMENT:
2916 case MESA_SHADER_COMPUTE:
2917 case MESA_SHADER_TESS_CTRL:
2918 case MESA_SHADER_GEOMETRY:
2919 return;
2920 case MESA_SHADER_VERTEX:
2921 if (ctx->options->key.vs.as_ls ||
2922 ctx->options->key.vs.as_es)
2923 return;
2924 outinfo = &ctx->shader_info->vs.outinfo;
2925 break;
2926 case MESA_SHADER_TESS_EVAL:
2927 if (ctx->options->key.vs.as_es)
2928 return;
2929 outinfo = &ctx->shader_info->tes.outinfo;
2930 break;
2931 default:
2932 unreachable("Unhandled shader type");
2933 }
2934
2935 ac_optimize_vs_outputs(&ctx->ac,
2936 ctx->main_function,
2937 outinfo->vs_output_param_offset,
2938 VARYING_SLOT_MAX,
2939 &outinfo->param_exports);
2940 }
2941
2942 static void
2943 ac_setup_rings(struct radv_shader_context *ctx)
2944 {
2945 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
2946 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
2947 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
2948 }
2949
2950 if (ctx->is_gs_copy_shader) {
2951 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
2952 }
2953 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2954 LLVMValueRef tmp;
2955 uint32_t num_entries = 64;
2956 LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size, false);
2957 LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size << 16, false);
2958 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
2959 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
2960
2961 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
2962
2963 tmp = LLVMConstInt(ctx->ac.i32, num_entries, false);
2964 if (ctx->options->chip_class >= VI)
2965 tmp = LLVMBuildMul(ctx->ac.builder, gsvs_ring_stride, tmp, "");
2966 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
2967 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
2968 tmp = LLVMBuildOr(ctx->ac.builder, tmp, gsvs_ring_desc, "");
2969 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
2970 }
2971
2972 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
2973 ctx->stage == MESA_SHADER_TESS_EVAL) {
2974 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
2975 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
2976 }
2977 }
2978
2979 static unsigned
2980 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
2981 const struct nir_shader *nir)
2982 {
2983 switch (nir->info.stage) {
2984 case MESA_SHADER_TESS_CTRL:
2985 return chip_class >= CIK ? 128 : 64;
2986 case MESA_SHADER_GEOMETRY:
2987 return chip_class >= GFX9 ? 128 : 64;
2988 case MESA_SHADER_COMPUTE:
2989 break;
2990 default:
2991 return 0;
2992 }
2993
2994 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
2995 nir->info.cs.local_size[1] *
2996 nir->info.cs.local_size[2];
2997 return max_workgroup_size;
2998 }
2999
3000 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3001 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3002 {
3003 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3004 LLVMConstInt(ctx->ac.i32, 8, false),
3005 LLVMConstInt(ctx->ac.i32, 8, false), false);
3006 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3007 ctx->ac.i32_0, "");
3008 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
3009 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
3010 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
3011 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3012 }
3013
3014 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3015 {
3016 for(int i = 5; i >= 0; --i) {
3017 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3018 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
3019 LLVMConstInt(ctx->ac.i32, 16, false), false);
3020 }
3021
3022 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3023 LLVMConstInt(ctx->ac.i32, 16, false),
3024 LLVMConstInt(ctx->ac.i32, 8, false), false);
3025 }
3026
3027
3028 static
3029 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
3030 struct nir_shader *const *shaders,
3031 int shader_count,
3032 struct radv_shader_variant_info *shader_info,
3033 const struct radv_nir_compiler_options *options)
3034 {
3035 struct radv_shader_context ctx = {0};
3036 unsigned i;
3037 ctx.options = options;
3038 ctx.shader_info = shader_info;
3039 ctx.context = LLVMContextCreate();
3040
3041 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3042 options->family);
3043 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3044 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
3045
3046 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
3047 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
3048 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
3049 LLVMDisposeTargetData(data_layout);
3050 LLVMDisposeMessage(data_layout_str);
3051
3052 enum ac_float_mode float_mode =
3053 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3054 AC_FLOAT_MODE_DEFAULT;
3055
3056 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3057
3058 memset(shader_info, 0, sizeof(*shader_info));
3059
3060 for(int i = 0; i < shader_count; ++i)
3061 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3062
3063 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3064 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3065 for (i = 0; i < AC_UD_MAX_UD; i++)
3066 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3067
3068 ctx.max_workgroup_size = 0;
3069 for (int i = 0; i < shader_count; ++i) {
3070 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3071 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3072 shaders[i]));
3073 }
3074
3075 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3076 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3077
3078 ctx.abi.inputs = &ctx.inputs[0];
3079 ctx.abi.emit_outputs = handle_shader_outputs_post;
3080 ctx.abi.emit_vertex = visit_emit_vertex;
3081 ctx.abi.load_ubo = radv_load_ubo;
3082 ctx.abi.load_ssbo = radv_load_ssbo;
3083 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3084 ctx.abi.load_resource = radv_load_resource;
3085 ctx.abi.clamp_shadow_reference = false;
3086 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9;
3087
3088 if (shader_count >= 2)
3089 ac_init_exec_full_mask(&ctx.ac);
3090
3091 if (ctx.ac.chip_class == GFX9 &&
3092 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3093 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3094
3095 for(int i = 0; i < shader_count; ++i) {
3096 ctx.stage = shaders[i]->info.stage;
3097 ctx.output_mask = 0;
3098 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3099 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3100
3101 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3102 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3103 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3104 ctx.abi.load_inputs = load_gs_input;
3105 ctx.abi.emit_primitive = visit_end_primitive;
3106 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3107 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3108 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3109 ctx.abi.load_tess_varyings = load_tcs_varyings;
3110 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3111 ctx.abi.store_tcs_outputs = store_tcs_output;
3112 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3113 if (shader_count == 1)
3114 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3115 else
3116 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3117 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3118 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3119 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3120 ctx.abi.load_tess_varyings = load_tes_input;
3121 ctx.abi.load_tess_coord = load_tess_coord;
3122 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3123 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3124 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3125 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3126 if (shader_info->info.vs.needs_instance_id) {
3127 if (ctx.options->key.vs.as_ls) {
3128 ctx.shader_info->vs.vgpr_comp_cnt =
3129 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3130 } else {
3131 ctx.shader_info->vs.vgpr_comp_cnt =
3132 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3133 }
3134 }
3135 ctx.abi.load_base_vertex = radv_load_base_vertex;
3136 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3137 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3138 ctx.abi.lookup_interp_param = lookup_interp_param;
3139 ctx.abi.load_sample_position = load_sample_position;
3140 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3141 ctx.abi.emit_kill = radv_emit_kill;
3142 }
3143
3144 if (i)
3145 ac_emit_barrier(&ctx.ac, ctx.stage);
3146
3147 nir_foreach_variable(variable, &shaders[i]->outputs)
3148 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3149
3150 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3151 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3152 shaders[i]->info.cull_distance_array_size > 4;
3153 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3154 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3155 shaders[i]->info.gs.vertices_out;
3156 }
3157
3158 ac_setup_rings(&ctx);
3159
3160 LLVMBasicBlockRef merge_block;
3161 if (shader_count >= 2) {
3162 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3163 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3164 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3165
3166 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3167 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3168 LLVMConstInt(ctx.ac.i32, 8, false), false);
3169 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3170 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3171 thread_id, count, "");
3172 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3173
3174 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3175 }
3176
3177 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3178 handle_fs_inputs(&ctx, shaders[i]);
3179 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3180 handle_vs_inputs(&ctx, shaders[i]);
3181 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3182 prepare_gs_input_vgprs(&ctx);
3183
3184 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3185
3186 if (shader_count >= 2) {
3187 LLVMBuildBr(ctx.ac.builder, merge_block);
3188 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3189 }
3190
3191 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3192 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3193 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3194 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3195 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3196 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3197 }
3198 }
3199
3200 LLVMBuildRetVoid(ctx.ac.builder);
3201
3202 if (options->dump_preoptir)
3203 ac_dump_module(ctx.ac.module);
3204
3205 ac_llvm_finalize_module(&ctx);
3206
3207 if (shader_count == 1)
3208 ac_nir_eliminate_const_vs_outputs(&ctx);
3209
3210 if (options->dump_shader) {
3211 ctx.shader_info->private_mem_vgprs =
3212 ac_count_scratch_private_memory(ctx.main_function);
3213 }
3214
3215 return ctx.ac.module;
3216 }
3217
3218 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3219 {
3220 unsigned *retval = (unsigned *)context;
3221 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3222 char *description = LLVMGetDiagInfoDescription(di);
3223
3224 if (severity == LLVMDSError) {
3225 *retval = 1;
3226 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3227 description);
3228 }
3229
3230 LLVMDisposeMessage(description);
3231 }
3232
3233 static unsigned ac_llvm_compile(LLVMModuleRef M,
3234 struct ac_shader_binary *binary,
3235 LLVMTargetMachineRef tm)
3236 {
3237 unsigned retval = 0;
3238 char *err;
3239 LLVMContextRef llvm_ctx;
3240 LLVMMemoryBufferRef out_buffer;
3241 unsigned buffer_size;
3242 const char *buffer_data;
3243 LLVMBool mem_err;
3244
3245 /* Setup Diagnostic Handler*/
3246 llvm_ctx = LLVMGetModuleContext(M);
3247
3248 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3249 &retval);
3250
3251 /* Compile IR*/
3252 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
3253 &err, &out_buffer);
3254
3255 /* Process Errors/Warnings */
3256 if (mem_err) {
3257 fprintf(stderr, "%s: %s", __FUNCTION__, err);
3258 free(err);
3259 retval = 1;
3260 goto out;
3261 }
3262
3263 /* Extract Shader Code*/
3264 buffer_size = LLVMGetBufferSize(out_buffer);
3265 buffer_data = LLVMGetBufferStart(out_buffer);
3266
3267 ac_elf_read(buffer_data, buffer_size, binary);
3268
3269 /* Clean up */
3270 LLVMDisposeMemoryBuffer(out_buffer);
3271
3272 out:
3273 return retval;
3274 }
3275
3276 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
3277 LLVMModuleRef llvm_module,
3278 struct ac_shader_binary *binary,
3279 struct ac_shader_config *config,
3280 struct radv_shader_variant_info *shader_info,
3281 gl_shader_stage stage,
3282 const struct radv_nir_compiler_options *options)
3283 {
3284 if (options->dump_shader)
3285 ac_dump_module(llvm_module);
3286
3287 memset(binary, 0, sizeof(*binary));
3288
3289 if (options->record_llvm_ir) {
3290 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3291 binary->llvm_ir_string = strdup(llvm_ir);
3292 LLVMDisposeMessage(llvm_ir);
3293 }
3294
3295 int v = ac_llvm_compile(llvm_module, binary, tm);
3296 if (v) {
3297 fprintf(stderr, "compile failed\n");
3298 }
3299
3300 if (options->dump_shader)
3301 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3302
3303 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3304
3305 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3306 LLVMDisposeModule(llvm_module);
3307 LLVMContextDispose(ctx);
3308
3309 if (stage == MESA_SHADER_FRAGMENT) {
3310 shader_info->num_input_vgprs = 0;
3311 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3312 shader_info->num_input_vgprs += 2;
3313 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3314 shader_info->num_input_vgprs += 2;
3315 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3316 shader_info->num_input_vgprs += 2;
3317 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3318 shader_info->num_input_vgprs += 3;
3319 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3320 shader_info->num_input_vgprs += 2;
3321 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3322 shader_info->num_input_vgprs += 2;
3323 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3324 shader_info->num_input_vgprs += 2;
3325 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3326 shader_info->num_input_vgprs += 1;
3327 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3328 shader_info->num_input_vgprs += 1;
3329 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3330 shader_info->num_input_vgprs += 1;
3331 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3332 shader_info->num_input_vgprs += 1;
3333 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3334 shader_info->num_input_vgprs += 1;
3335 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3336 shader_info->num_input_vgprs += 1;
3337 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3338 shader_info->num_input_vgprs += 1;
3339 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3340 shader_info->num_input_vgprs += 1;
3341 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3342 shader_info->num_input_vgprs += 1;
3343 }
3344 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3345
3346 /* +3 for scratch wave offset and VCC */
3347 config->num_sgprs = MAX2(config->num_sgprs,
3348 shader_info->num_input_sgprs + 3);
3349
3350 /* Enable 64-bit and 16-bit denormals, because there is no performance
3351 * cost.
3352 *
3353 * If denormals are enabled, all floating-point output modifiers are
3354 * ignored.
3355 *
3356 * Don't enable denormals for 32-bit floats, because:
3357 * - Floating-point output modifiers would be ignored by the hw.
3358 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3359 * have to stop using those.
3360 * - SI & CI would be very slow.
3361 */
3362 config->float_mode |= V_00B028_FP_64_DENORMS;
3363 }
3364
3365 static void
3366 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3367 {
3368 switch (nir->info.stage) {
3369 case MESA_SHADER_COMPUTE:
3370 for (int i = 0; i < 3; ++i)
3371 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3372 break;
3373 case MESA_SHADER_FRAGMENT:
3374 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3375 break;
3376 case MESA_SHADER_GEOMETRY:
3377 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3378 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3379 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3380 shader_info->gs.invocations = nir->info.gs.invocations;
3381 break;
3382 case MESA_SHADER_TESS_EVAL:
3383 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3384 shader_info->tes.spacing = nir->info.tess.spacing;
3385 shader_info->tes.ccw = nir->info.tess.ccw;
3386 shader_info->tes.point_mode = nir->info.tess.point_mode;
3387 shader_info->tes.as_es = options->key.tes.as_es;
3388 break;
3389 case MESA_SHADER_TESS_CTRL:
3390 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3391 break;
3392 case MESA_SHADER_VERTEX:
3393 shader_info->vs.as_es = options->key.vs.as_es;
3394 shader_info->vs.as_ls = options->key.vs.as_ls;
3395 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3396 if (options->key.vs.as_ls)
3397 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3398 break;
3399 default:
3400 break;
3401 }
3402 }
3403
3404 void
3405 radv_compile_nir_shader(LLVMTargetMachineRef tm,
3406 struct ac_shader_binary *binary,
3407 struct ac_shader_config *config,
3408 struct radv_shader_variant_info *shader_info,
3409 struct nir_shader *const *nir,
3410 int nir_count,
3411 const struct radv_nir_compiler_options *options)
3412 {
3413
3414 LLVMModuleRef llvm_module;
3415
3416 llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
3417 options);
3418
3419 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
3420 nir[0]->info.stage, options);
3421
3422 for (int i = 0; i < nir_count; ++i)
3423 ac_fill_shader_info(shader_info, nir[i], options);
3424
3425 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3426 if (options->chip_class == GFX9) {
3427 if (nir_count == 2 &&
3428 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3429 shader_info->gs.es_type = nir[0]->info.stage;
3430 }
3431 }
3432 }
3433
3434 static void
3435 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3436 {
3437 LLVMValueRef vtx_offset =
3438 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3439 LLVMConstInt(ctx->ac.i32, 4, false), "");
3440 int idx = 0;
3441
3442 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3443 int length = 4;
3444 int slot = idx;
3445 int slot_inc = 1;
3446 if (!(ctx->output_mask & (1ull << i)))
3447 continue;
3448
3449 if (i == VARYING_SLOT_CLIP_DIST0) {
3450 /* unpack clip and cull from a single set of slots */
3451 length = ctx->num_output_clips + ctx->num_output_culls;
3452 if (length > 4)
3453 slot_inc = 2;
3454 }
3455
3456 for (unsigned j = 0; j < length; j++) {
3457 LLVMValueRef value, soffset;
3458
3459 soffset = LLVMConstInt(ctx->ac.i32,
3460 (slot * 4 + j) *
3461 ctx->gs_max_out_vertices * 16 * 4, false);
3462
3463 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3464 1, ctx->ac.i32_0,
3465 vtx_offset, soffset,
3466 0, 1, 1, true, false);
3467
3468 LLVMBuildStore(ctx->ac.builder,
3469 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3470 }
3471 idx += slot_inc;
3472 }
3473 handle_vs_outputs_post(ctx, false, false, &ctx->shader_info->vs.outinfo);
3474 }
3475
3476 void
3477 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
3478 struct nir_shader *geom_shader,
3479 struct ac_shader_binary *binary,
3480 struct ac_shader_config *config,
3481 struct radv_shader_variant_info *shader_info,
3482 const struct radv_nir_compiler_options *options)
3483 {
3484 struct radv_shader_context ctx = {0};
3485 ctx.context = LLVMContextCreate();
3486 ctx.options = options;
3487 ctx.shader_info = shader_info;
3488
3489 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3490 options->family);
3491 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3492
3493 ctx.is_gs_copy_shader = true;
3494 LLVMSetTarget(ctx.ac.module, "amdgcn--");
3495
3496 enum ac_float_mode float_mode =
3497 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3498 AC_FLOAT_MODE_DEFAULT;
3499
3500 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3501 ctx.stage = MESA_SHADER_VERTEX;
3502
3503 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3504
3505 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3506 ac_setup_rings(&ctx);
3507
3508 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3509 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3510
3511 nir_foreach_variable(variable, &geom_shader->outputs) {
3512 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3513 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3514 variable, MESA_SHADER_VERTEX);
3515 }
3516
3517 ac_gs_copy_shader_emit(&ctx);
3518
3519 LLVMBuildRetVoid(ctx.ac.builder);
3520
3521 ac_llvm_finalize_module(&ctx);
3522
3523 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
3524 MESA_SHADER_VERTEX, options);
3525 }