2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_llvm_build.h"
42 #include "ac_shader_abi.h"
43 #include "ac_shader_util.h"
44 #include "ac_exp_param.h"
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 struct radv_shader_context
{
49 struct ac_llvm_context ac
;
50 const struct radv_nir_compiler_options
*options
;
51 struct radv_shader_variant_info
*shader_info
;
52 struct ac_shader_abi abi
;
54 unsigned max_workgroup_size
;
55 LLVMContextRef context
;
56 LLVMValueRef main_function
;
58 LLVMValueRef descriptor_sets
[RADV_UD_MAX_SETS
];
59 LLVMValueRef ring_offsets
;
61 LLVMValueRef vertex_buffers
;
62 LLVMValueRef rel_auto_id
;
63 LLVMValueRef vs_prim_id
;
64 LLVMValueRef es2gs_offset
;
67 LLVMValueRef merged_wave_info
;
68 LLVMValueRef tess_factor_offset
;
69 LLVMValueRef tes_rel_patch_id
;
75 * - bits 0..10: ordered_wave_id
76 * - bits 12..20: number of vertices in group
77 * - bits 22..30: number of primitives in group
79 LLVMValueRef gs_tg_info
;
80 LLVMValueRef gs2vs_offset
;
81 LLVMValueRef gs_wave_id
;
82 LLVMValueRef gs_vtx_offset
[6];
84 LLVMValueRef esgs_ring
;
85 LLVMValueRef gsvs_ring
[4];
86 LLVMValueRef hs_ring_tess_offchip
;
87 LLVMValueRef hs_ring_tess_factor
;
89 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
90 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
93 LLVMValueRef streamout_buffers
;
94 LLVMValueRef streamout_write_idx
;
95 LLVMValueRef streamout_config
;
96 LLVMValueRef streamout_offset
[4];
98 gl_shader_stage stage
;
100 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
101 uint64_t float16_shaded_mask
;
104 uint64_t output_mask
;
106 bool is_gs_copy_shader
;
107 LLVMValueRef gs_next_vertex
[4];
108 unsigned gs_max_out_vertices
;
110 unsigned tes_primitive_mode
;
112 uint32_t tcs_patch_outputs_read
;
113 uint64_t tcs_outputs_read
;
114 uint32_t tcs_vertices_per_patch
;
115 uint32_t tcs_num_inputs
;
116 uint32_t tcs_num_patches
;
117 uint32_t max_gsvs_emit_size
;
118 uint32_t gsvs_vertex_size
;
121 enum radeon_llvm_calling_convention
{
122 RADEON_LLVM_AMDGPU_VS
= 87,
123 RADEON_LLVM_AMDGPU_GS
= 88,
124 RADEON_LLVM_AMDGPU_PS
= 89,
125 RADEON_LLVM_AMDGPU_CS
= 90,
126 RADEON_LLVM_AMDGPU_HS
= 93,
129 static inline struct radv_shader_context
*
130 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
132 struct radv_shader_context
*ctx
= NULL
;
133 return container_of(abi
, ctx
, abi
);
136 struct ac_build_if_state
138 struct radv_shader_context
*ctx
;
139 LLVMValueRef condition
;
140 LLVMBasicBlockRef entry_block
;
141 LLVMBasicBlockRef true_block
;
142 LLVMBasicBlockRef false_block
;
143 LLVMBasicBlockRef merge_block
;
146 static LLVMBasicBlockRef
147 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
149 LLVMBasicBlockRef current_block
;
150 LLVMBasicBlockRef next_block
;
151 LLVMBasicBlockRef new_block
;
153 /* get current basic block */
154 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
156 /* chqeck if there's another block after this one */
157 next_block
= LLVMGetNextBasicBlock(current_block
);
159 /* insert the new block before the next block */
160 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
163 /* append new block after current block */
164 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
165 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
171 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
172 struct radv_shader_context
*ctx
,
173 LLVMValueRef condition
)
175 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
177 memset(ifthen
, 0, sizeof *ifthen
);
179 ifthen
->condition
= condition
;
180 ifthen
->entry_block
= block
;
182 /* create endif/merge basic block for the phi functions */
183 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
185 /* create/insert true_block before merge_block */
187 LLVMInsertBasicBlockInContext(ctx
->context
,
191 /* successive code goes into the true block */
192 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
199 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
201 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
203 /* Insert branch to the merge block from current block */
204 LLVMBuildBr(builder
, ifthen
->merge_block
);
207 * Now patch in the various branch instructions.
210 /* Insert the conditional branch instruction at the end of entry_block */
211 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
212 if (ifthen
->false_block
) {
213 /* we have an else clause */
214 LLVMBuildCondBr(builder
, ifthen
->condition
,
215 ifthen
->true_block
, ifthen
->false_block
);
219 LLVMBuildCondBr(builder
, ifthen
->condition
,
220 ifthen
->true_block
, ifthen
->merge_block
);
223 /* Resume building code at end of the ifthen->merge_block */
224 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
228 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
230 switch (ctx
->stage
) {
231 case MESA_SHADER_TESS_CTRL
:
232 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
233 case MESA_SHADER_TESS_EVAL
:
234 return ctx
->tes_rel_patch_id
;
237 unreachable("Illegal stage");
242 get_tcs_num_patches(struct radv_shader_context
*ctx
)
244 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
245 unsigned num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
246 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
247 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
248 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
249 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
250 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
251 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
252 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
253 unsigned num_patches
;
254 unsigned hardware_lds_size
;
256 /* Ensure that we only need one wave per SIMD so we don't need to check
257 * resource usage. Also ensures that the number of tcs in and out
258 * vertices per threadgroup are at most 256.
260 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
261 /* Make sure that the data fits in LDS. This assumes the shaders only
262 * use LDS for the inputs and outputs.
264 hardware_lds_size
= 32768;
266 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
267 * threadgroup, even though there is more than 32 KiB LDS.
269 * Test: dEQP-VK.tessellation.shader_input_output.barrier
271 if (ctx
->options
->chip_class
>= GFX7
&& ctx
->options
->family
!= CHIP_STONEY
)
272 hardware_lds_size
= 65536;
274 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
275 /* Make sure the output data fits in the offchip buffer */
276 num_patches
= MIN2(num_patches
, (ctx
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
277 /* Not necessary for correctness, but improves performance. The
278 * specific value is taken from the proprietary driver.
280 num_patches
= MIN2(num_patches
, 40);
282 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
283 if (ctx
->options
->chip_class
== GFX6
) {
284 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
285 num_patches
= MIN2(num_patches
, one_wave
);
291 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
293 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
294 unsigned num_tcs_output_cp
;
295 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
296 unsigned input_vertex_size
, output_vertex_size
;
297 unsigned input_patch_size
, output_patch_size
;
298 unsigned pervertex_output_patch_size
;
299 unsigned output_patch0_offset
;
300 unsigned num_patches
;
303 num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
304 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
305 num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
307 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
308 output_vertex_size
= num_tcs_outputs
* 16;
310 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
312 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
313 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
315 num_patches
= ctx
->tcs_num_patches
;
316 output_patch0_offset
= input_patch_size
* num_patches
;
318 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
322 /* Tessellation shaders pass outputs to the next shader using LDS.
324 * LS outputs = TCS inputs
325 * TCS outputs = TES inputs
328 * - TCS inputs for patch 0
329 * - TCS inputs for patch 1
330 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
332 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
333 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
334 * - TCS outputs for patch 1
335 * - Per-patch TCS outputs for patch 1
336 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
337 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
340 * All three shaders VS(LS), TCS, TES share the same LDS space.
343 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
345 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
346 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
347 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
349 input_patch_size
/= 4;
350 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
354 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
356 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
357 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
358 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
359 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
360 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
361 output_patch_size
/= 4;
362 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
366 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
368 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
369 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
370 output_vertex_size
/= 4;
371 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
375 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
377 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
378 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
379 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
380 uint32_t output_patch0_offset
= input_patch_size
;
381 unsigned num_patches
= ctx
->tcs_num_patches
;
383 output_patch0_offset
*= num_patches
;
384 output_patch0_offset
/= 4;
385 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
389 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
391 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
392 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
393 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
394 uint32_t output_patch0_offset
= input_patch_size
;
396 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
397 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
398 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
399 unsigned num_patches
= ctx
->tcs_num_patches
;
401 output_patch0_offset
*= num_patches
;
402 output_patch0_offset
+= pervertex_output_patch_size
;
403 output_patch0_offset
/= 4;
404 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
408 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
410 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
411 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
413 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
417 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
419 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
420 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
421 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
423 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
428 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
430 LLVMValueRef patch0_patch_data_offset
=
431 get_tcs_out_patch0_patch_data_offset(ctx
);
432 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
433 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
435 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
436 patch0_patch_data_offset
);
441 LLVMTypeRef types
[MAX_ARGS
];
442 LLVMValueRef
*assign
[MAX_ARGS
];
445 uint8_t num_sgprs_used
;
446 uint8_t num_vgprs_used
;
449 enum ac_arg_regfile
{
455 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
456 LLVMValueRef
*param_ptr
)
458 assert(info
->count
< MAX_ARGS
);
460 info
->assign
[info
->count
] = param_ptr
;
461 info
->types
[info
->count
] = type
;
464 if (regfile
== ARG_SGPR
) {
465 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
468 assert(regfile
== ARG_VGPR
);
469 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
473 static void assign_arguments(LLVMValueRef main_function
,
474 struct arg_info
*info
)
477 for (i
= 0; i
< info
->count
; i
++) {
479 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
484 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
485 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
486 unsigned num_return_elems
,
487 struct arg_info
*args
,
488 unsigned max_workgroup_size
,
489 const struct radv_nir_compiler_options
*options
)
491 LLVMTypeRef main_function_type
, ret_type
;
492 LLVMBasicBlockRef main_function_body
;
494 if (num_return_elems
)
495 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
496 num_return_elems
, true);
498 ret_type
= LLVMVoidTypeInContext(ctx
);
500 /* Setup the function */
502 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
503 LLVMValueRef main_function
=
504 LLVMAddFunction(module
, "main", main_function_type
);
506 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
507 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
509 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
510 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
511 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
513 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
515 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
516 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
517 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
521 if (options
->address32_hi
) {
522 ac_llvm_add_target_dep_function_attr(main_function
,
523 "amdgpu-32bit-address-high-bits",
524 options
->address32_hi
);
527 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
529 if (options
->unsafe_math
) {
530 /* These were copied from some LLVM test. */
531 LLVMAddTargetDependentFunctionAttr(main_function
,
532 "less-precise-fpmad",
534 LLVMAddTargetDependentFunctionAttr(main_function
,
537 LLVMAddTargetDependentFunctionAttr(main_function
,
540 LLVMAddTargetDependentFunctionAttr(main_function
,
543 LLVMAddTargetDependentFunctionAttr(main_function
,
544 "no-signed-zeros-fp-math",
547 return main_function
;
552 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
,
555 ud_info
->sgpr_idx
= *sgpr_idx
;
556 ud_info
->num_sgprs
= num_sgprs
;
557 *sgpr_idx
+= num_sgprs
;
561 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
564 struct radv_userdata_info
*ud_info
=
565 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
568 set_loc(ud_info
, sgpr_idx
, num_sgprs
);
572 set_loc_shader_ptr(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
574 bool use_32bit_pointers
= idx
!= AC_UD_SCRATCH_RING_OFFSETS
;
576 set_loc_shader(ctx
, idx
, sgpr_idx
, use_32bit_pointers
? 1 : 2);
580 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
582 struct radv_userdata_locations
*locs
=
583 &ctx
->shader_info
->user_sgprs_locs
;
584 struct radv_userdata_info
*ud_info
= &locs
->descriptor_sets
[idx
];
587 set_loc(ud_info
, sgpr_idx
, 1);
589 locs
->descriptor_sets_enabled
|= 1 << idx
;
592 struct user_sgpr_info
{
593 bool need_ring_offsets
;
594 bool indirect_all_descriptor_sets
;
595 uint8_t remaining_sgprs
;
598 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
599 gl_shader_stage stage
)
602 case MESA_SHADER_VERTEX
:
603 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
604 (!ctx
->options
->key
.vs_common_out
.as_es
&& !ctx
->options
->key
.vs_common_out
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
607 case MESA_SHADER_TESS_EVAL
:
608 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.vs_common_out
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
611 case MESA_SHADER_GEOMETRY
:
612 case MESA_SHADER_TESS_CTRL
:
613 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
623 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
627 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
629 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
634 static void allocate_inline_push_consts(struct radv_shader_context
*ctx
,
635 struct user_sgpr_info
*user_sgpr_info
)
637 uint8_t remaining_sgprs
= user_sgpr_info
->remaining_sgprs
;
639 /* Only supported if shaders use push constants. */
640 if (ctx
->shader_info
->info
.min_push_constant_used
== UINT8_MAX
)
643 /* Only supported if shaders don't have indirect push constants. */
644 if (ctx
->shader_info
->info
.has_indirect_push_constants
)
647 /* Only supported for 32-bit push constants. */
648 if (!ctx
->shader_info
->info
.has_only_32bit_push_constants
)
651 uint8_t num_push_consts
=
652 (ctx
->shader_info
->info
.max_push_constant_used
-
653 ctx
->shader_info
->info
.min_push_constant_used
) / 4;
655 /* Check if the number of user SGPRs is large enough. */
656 if (num_push_consts
< remaining_sgprs
) {
657 ctx
->shader_info
->info
.num_inline_push_consts
= num_push_consts
;
659 ctx
->shader_info
->info
.num_inline_push_consts
= remaining_sgprs
;
662 /* Clamp to the maximum number of allowed inlined push constants. */
663 if (ctx
->shader_info
->info
.num_inline_push_consts
> AC_MAX_INLINE_PUSH_CONSTS
)
664 ctx
->shader_info
->info
.num_inline_push_consts
= AC_MAX_INLINE_PUSH_CONSTS
;
666 if (ctx
->shader_info
->info
.num_inline_push_consts
== num_push_consts
&&
667 !ctx
->shader_info
->info
.loads_dynamic_offsets
) {
668 /* Disable the default push constants path if all constants are
669 * inlined and if shaders don't use dynamic descriptors.
671 ctx
->shader_info
->info
.loads_push_constants
= false;
674 ctx
->shader_info
->info
.base_inline_push_consts
=
675 ctx
->shader_info
->info
.min_push_constant_used
/ 4;
678 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
679 gl_shader_stage stage
,
680 bool has_previous_stage
,
681 gl_shader_stage previous_stage
,
682 bool needs_view_index
,
683 struct user_sgpr_info
*user_sgpr_info
)
685 uint8_t user_sgpr_count
= 0;
687 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
689 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
690 if (stage
== MESA_SHADER_GEOMETRY
||
691 stage
== MESA_SHADER_VERTEX
||
692 stage
== MESA_SHADER_TESS_CTRL
||
693 stage
== MESA_SHADER_TESS_EVAL
||
694 ctx
->is_gs_copy_shader
)
695 user_sgpr_info
->need_ring_offsets
= true;
697 if (stage
== MESA_SHADER_FRAGMENT
&&
698 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
699 user_sgpr_info
->need_ring_offsets
= true;
701 /* 2 user sgprs will nearly always be allocated for scratch/rings */
702 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
703 user_sgpr_count
+= 2;
707 case MESA_SHADER_COMPUTE
:
708 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
709 user_sgpr_count
+= 3;
711 case MESA_SHADER_FRAGMENT
:
712 user_sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
714 case MESA_SHADER_VERTEX
:
715 if (!ctx
->is_gs_copy_shader
)
716 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
718 case MESA_SHADER_TESS_CTRL
:
719 if (has_previous_stage
) {
720 if (previous_stage
== MESA_SHADER_VERTEX
)
721 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
724 case MESA_SHADER_TESS_EVAL
:
726 case MESA_SHADER_GEOMETRY
:
727 if (has_previous_stage
) {
728 if (previous_stage
== MESA_SHADER_VERTEX
) {
729 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
737 if (needs_view_index
)
740 if (ctx
->shader_info
->info
.loads_push_constants
)
743 if (ctx
->streamout_buffers
)
746 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
&& stage
!= MESA_SHADER_COMPUTE
? 32 : 16;
747 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_count
;
748 uint32_t num_desc_set
=
749 util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
);
751 if (remaining_sgprs
< num_desc_set
) {
752 user_sgpr_info
->indirect_all_descriptor_sets
= true;
753 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- 1;
755 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- num_desc_set
;
758 allocate_inline_push_consts(ctx
, user_sgpr_info
);
762 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
763 const struct user_sgpr_info
*user_sgpr_info
,
764 struct arg_info
*args
,
765 LLVMValueRef
*desc_sets
)
767 LLVMTypeRef type
= ac_array_in_const32_addr_space(ctx
->ac
.i8
);
769 /* 1 for each descriptor set */
770 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
771 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
774 int i
= u_bit_scan(&mask
);
776 add_arg(args
, ARG_SGPR
, type
, &ctx
->descriptor_sets
[i
]);
779 add_arg(args
, ARG_SGPR
, ac_array_in_const32_addr_space(type
),
783 if (ctx
->shader_info
->info
.loads_push_constants
) {
784 /* 1 for push constants and dynamic descriptors */
785 add_arg(args
, ARG_SGPR
, type
, &ctx
->abi
.push_constants
);
788 for (unsigned i
= 0; i
< ctx
->shader_info
->info
.num_inline_push_consts
; i
++) {
789 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
,
790 &ctx
->abi
.inline_push_consts
[i
]);
792 ctx
->abi
.num_inline_push_consts
= ctx
->shader_info
->info
.num_inline_push_consts
;
793 ctx
->abi
.base_inline_push_consts
= ctx
->shader_info
->info
.base_inline_push_consts
;
795 if (ctx
->shader_info
->info
.so
.num_outputs
) {
796 add_arg(args
, ARG_SGPR
,
797 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
798 &ctx
->streamout_buffers
);
803 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
804 gl_shader_stage stage
,
805 bool has_previous_stage
,
806 gl_shader_stage previous_stage
,
807 struct arg_info
*args
)
809 if (!ctx
->is_gs_copy_shader
&&
810 (stage
== MESA_SHADER_VERTEX
||
811 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
812 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
813 add_arg(args
, ARG_SGPR
,
814 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
815 &ctx
->vertex_buffers
);
817 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
818 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
819 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
820 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
826 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
828 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
829 if (!ctx
->is_gs_copy_shader
) {
830 if (ctx
->options
->key
.vs_common_out
.as_ls
) {
831 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
832 if (ctx
->ac
.chip_class
>= GFX10
) {
833 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
834 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
836 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
837 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
840 if (ctx
->ac
.chip_class
>= GFX10
) {
841 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
842 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
843 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
845 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
846 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
847 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
854 declare_streamout_sgprs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
855 struct arg_info
*args
)
859 if (ctx
->ac
.chip_class
>= GFX10
)
862 /* Streamout SGPRs. */
863 if (ctx
->shader_info
->info
.so
.num_outputs
) {
864 assert(stage
== MESA_SHADER_VERTEX
||
865 stage
== MESA_SHADER_TESS_EVAL
);
867 if (stage
!= MESA_SHADER_TESS_EVAL
) {
868 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_config
);
870 args
->assign
[args
->count
- 1] = &ctx
->streamout_config
;
871 args
->types
[args
->count
- 1] = ctx
->ac
.i32
;
874 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_write_idx
);
877 /* A streamout buffer offset is loaded if the stride is non-zero. */
878 for (i
= 0; i
< 4; i
++) {
879 if (!ctx
->shader_info
->info
.so
.strides
[i
])
882 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_offset
[i
]);
887 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
889 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
890 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
891 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
892 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
896 set_global_input_locs(struct radv_shader_context
*ctx
,
897 const struct user_sgpr_info
*user_sgpr_info
,
898 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
900 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
902 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
904 int i
= u_bit_scan(&mask
);
906 set_loc_desc(ctx
, i
, user_sgpr_idx
);
909 set_loc_shader_ptr(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
913 int i
= u_bit_scan(&mask
);
915 ctx
->descriptor_sets
[i
] =
916 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
917 LLVMConstInt(ctx
->ac
.i32
, i
, false));
921 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
924 if (ctx
->shader_info
->info
.loads_push_constants
) {
925 set_loc_shader_ptr(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
);
928 if (ctx
->shader_info
->info
.num_inline_push_consts
) {
929 set_loc_shader(ctx
, AC_UD_INLINE_PUSH_CONSTANTS
, user_sgpr_idx
,
930 ctx
->shader_info
->info
.num_inline_push_consts
);
933 if (ctx
->streamout_buffers
) {
934 set_loc_shader_ptr(ctx
, AC_UD_STREAMOUT_BUFFERS
,
940 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
941 gl_shader_stage stage
, bool has_previous_stage
,
942 gl_shader_stage previous_stage
,
943 uint8_t *user_sgpr_idx
)
945 if (!ctx
->is_gs_copy_shader
&&
946 (stage
== MESA_SHADER_VERTEX
||
947 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
948 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
949 set_loc_shader_ptr(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
954 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
957 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
958 user_sgpr_idx
, vs_num
);
962 static void set_llvm_calling_convention(LLVMValueRef func
,
963 gl_shader_stage stage
)
965 enum radeon_llvm_calling_convention calling_conv
;
968 case MESA_SHADER_VERTEX
:
969 case MESA_SHADER_TESS_EVAL
:
970 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
972 case MESA_SHADER_GEOMETRY
:
973 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
975 case MESA_SHADER_TESS_CTRL
:
976 calling_conv
= RADEON_LLVM_AMDGPU_HS
;
978 case MESA_SHADER_FRAGMENT
:
979 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
981 case MESA_SHADER_COMPUTE
:
982 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
985 unreachable("Unhandle shader type");
988 LLVMSetFunctionCallConv(func
, calling_conv
);
991 /* Returns whether the stage is a stage that can be directly before the GS */
992 static bool is_pre_gs_stage(gl_shader_stage stage
)
994 return stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
;
997 static void create_function(struct radv_shader_context
*ctx
,
998 gl_shader_stage stage
,
999 bool has_previous_stage
,
1000 gl_shader_stage previous_stage
)
1002 uint8_t user_sgpr_idx
;
1003 struct user_sgpr_info user_sgpr_info
;
1004 struct arg_info args
= {};
1005 LLVMValueRef desc_sets
;
1006 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
1008 if (ctx
->ac
.chip_class
>= GFX10
) {
1009 if (is_pre_gs_stage(stage
) && ctx
->options
->key
.vs_common_out
.as_ngg
) {
1010 /* On GFX10, VS is merged into GS for NGG. */
1011 previous_stage
= stage
;
1012 stage
= MESA_SHADER_GEOMETRY
;
1013 has_previous_stage
= true;
1017 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
1018 previous_stage
, needs_view_index
, &user_sgpr_info
);
1020 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
1021 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
1022 &ctx
->ring_offsets
);
1026 case MESA_SHADER_COMPUTE
:
1027 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1030 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1031 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
1032 &ctx
->abi
.num_work_groups
);
1035 for (int i
= 0; i
< 3; i
++) {
1036 ctx
->abi
.workgroup_ids
[i
] = NULL
;
1037 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
1038 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1039 &ctx
->abi
.workgroup_ids
[i
]);
1043 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
1044 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
1045 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
1046 &ctx
->abi
.local_invocation_ids
);
1048 case MESA_SHADER_VERTEX
:
1049 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1052 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
1053 previous_stage
, &args
);
1055 if (needs_view_index
)
1056 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1057 &ctx
->abi
.view_index
);
1058 if (ctx
->options
->key
.vs_common_out
.as_es
) {
1059 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1060 &ctx
->es2gs_offset
);
1061 } else if (ctx
->options
->key
.vs_common_out
.as_ls
) {
1062 /* no extra parameters */
1064 declare_streamout_sgprs(ctx
, stage
, &args
);
1067 declare_vs_input_vgprs(ctx
, &args
);
1069 case MESA_SHADER_TESS_CTRL
:
1070 if (has_previous_stage
) {
1071 // First 6 system regs
1072 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1073 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1074 &ctx
->merged_wave_info
);
1075 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1076 &ctx
->tess_factor_offset
);
1078 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1079 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1080 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1082 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1085 declare_vs_specific_input_sgprs(ctx
, stage
,
1087 previous_stage
, &args
);
1089 if (needs_view_index
)
1090 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1091 &ctx
->abi
.view_index
);
1093 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1094 &ctx
->abi
.tcs_patch_id
);
1095 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1096 &ctx
->abi
.tcs_rel_ids
);
1098 declare_vs_input_vgprs(ctx
, &args
);
1100 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1103 if (needs_view_index
)
1104 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1105 &ctx
->abi
.view_index
);
1107 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1108 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1109 &ctx
->tess_factor_offset
);
1110 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1111 &ctx
->abi
.tcs_patch_id
);
1112 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1113 &ctx
->abi
.tcs_rel_ids
);
1116 case MESA_SHADER_TESS_EVAL
:
1117 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1120 if (needs_view_index
)
1121 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1122 &ctx
->abi
.view_index
);
1124 if (ctx
->options
->key
.vs_common_out
.as_es
) {
1125 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1126 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1127 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1128 &ctx
->es2gs_offset
);
1130 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1131 declare_streamout_sgprs(ctx
, stage
, &args
);
1132 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1134 declare_tes_input_vgprs(ctx
, &args
);
1136 case MESA_SHADER_GEOMETRY
:
1137 if (has_previous_stage
) {
1138 // First 6 system regs
1139 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1140 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1143 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1144 &ctx
->gs2vs_offset
);
1147 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1148 &ctx
->merged_wave_info
);
1149 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1151 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1152 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1153 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1155 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1158 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
1159 declare_vs_specific_input_sgprs(ctx
, stage
,
1165 if (needs_view_index
)
1166 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1167 &ctx
->abi
.view_index
);
1169 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1170 &ctx
->gs_vtx_offset
[0]);
1171 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1172 &ctx
->gs_vtx_offset
[2]);
1173 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1174 &ctx
->abi
.gs_prim_id
);
1175 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1176 &ctx
->abi
.gs_invocation_id
);
1177 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1178 &ctx
->gs_vtx_offset
[4]);
1180 if (previous_stage
== MESA_SHADER_VERTEX
) {
1181 declare_vs_input_vgprs(ctx
, &args
);
1183 declare_tes_input_vgprs(ctx
, &args
);
1186 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1189 if (needs_view_index
)
1190 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1191 &ctx
->abi
.view_index
);
1193 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1194 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1195 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1196 &ctx
->gs_vtx_offset
[0]);
1197 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1198 &ctx
->gs_vtx_offset
[1]);
1199 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1200 &ctx
->abi
.gs_prim_id
);
1201 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1202 &ctx
->gs_vtx_offset
[2]);
1203 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1204 &ctx
->gs_vtx_offset
[3]);
1205 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1206 &ctx
->gs_vtx_offset
[4]);
1207 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1208 &ctx
->gs_vtx_offset
[5]);
1209 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1210 &ctx
->abi
.gs_invocation_id
);
1213 case MESA_SHADER_FRAGMENT
:
1214 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1217 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1218 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1219 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1220 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1221 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1222 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1223 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1224 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1225 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1226 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1227 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1228 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1229 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1230 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1231 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1232 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1233 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1236 unreachable("Shader stage not implemented");
1239 ctx
->main_function
= create_llvm_function(
1240 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1241 ctx
->max_workgroup_size
, ctx
->options
);
1242 set_llvm_calling_convention(ctx
->main_function
, stage
);
1245 ctx
->shader_info
->num_input_vgprs
= 0;
1246 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1248 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1250 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1251 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1253 assign_arguments(ctx
->main_function
, &args
);
1257 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1258 set_loc_shader_ptr(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1260 if (ctx
->options
->supports_spill
) {
1261 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1262 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
1263 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1264 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1265 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1269 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1270 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1271 if (has_previous_stage
)
1274 set_global_input_locs(ctx
, &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1277 case MESA_SHADER_COMPUTE
:
1278 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1279 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1283 case MESA_SHADER_VERTEX
:
1284 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1285 previous_stage
, &user_sgpr_idx
);
1286 if (ctx
->abi
.view_index
)
1287 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1289 case MESA_SHADER_TESS_CTRL
:
1290 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1291 previous_stage
, &user_sgpr_idx
);
1292 if (ctx
->abi
.view_index
)
1293 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1295 case MESA_SHADER_TESS_EVAL
:
1296 if (ctx
->abi
.view_index
)
1297 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1299 case MESA_SHADER_GEOMETRY
:
1300 if (has_previous_stage
) {
1301 if (previous_stage
== MESA_SHADER_VERTEX
)
1302 set_vs_specific_input_locs(ctx
, stage
,
1307 if (ctx
->abi
.view_index
)
1308 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1310 case MESA_SHADER_FRAGMENT
:
1313 unreachable("Shader stage not implemented");
1316 if (stage
== MESA_SHADER_TESS_CTRL
||
1317 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs_common_out
.as_ls
) ||
1318 /* GFX9 has the ESGS ring buffer in LDS. */
1319 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1320 ac_declare_lds_as_pointer(&ctx
->ac
);
1323 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1328 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1329 unsigned desc_set
, unsigned binding
)
1331 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1332 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1333 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
1334 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1335 unsigned base_offset
= layout
->binding
[binding
].offset
;
1336 LLVMValueRef offset
, stride
;
1338 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1339 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1340 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1341 layout
->binding
[binding
].dynamic_offset_offset
;
1342 desc_ptr
= ctx
->abi
.push_constants
;
1343 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1344 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1346 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1348 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
1350 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1351 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
1354 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
1355 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1356 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1358 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1359 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1360 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1361 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1362 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1363 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1364 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1366 LLVMValueRef desc_components
[4] = {
1367 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
1368 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
), false),
1369 /* High limit to support variable sizes. */
1370 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
1371 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
1374 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
1381 /* The offchip buffer layout for TCS->TES is
1383 * - attribute 0 of patch 0 vertex 0
1384 * - attribute 0 of patch 0 vertex 1
1385 * - attribute 0 of patch 0 vertex 2
1387 * - attribute 0 of patch 1 vertex 0
1388 * - attribute 0 of patch 1 vertex 1
1390 * - attribute 1 of patch 0 vertex 0
1391 * - attribute 1 of patch 0 vertex 1
1393 * - per patch attribute 0 of patch 0
1394 * - per patch attribute 0 of patch 1
1397 * Note that every attribute has 4 components.
1399 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1401 uint32_t num_patches
= ctx
->tcs_num_patches
;
1402 uint32_t num_tcs_outputs
;
1403 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1404 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
1406 num_tcs_outputs
= ctx
->options
->key
.tes
.tcs_num_outputs
;
1408 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1409 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
1411 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1414 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1415 LLVMValueRef vertex_index
)
1417 LLVMValueRef param_stride
;
1419 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
* ctx
->tcs_num_patches
, false);
1421 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1422 return param_stride
;
1425 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1426 LLVMValueRef vertex_index
,
1427 LLVMValueRef param_index
)
1429 LLVMValueRef base_addr
;
1430 LLVMValueRef param_stride
, constant16
;
1431 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1432 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
1433 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1434 param_stride
= calc_param_stride(ctx
, vertex_index
);
1436 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
1437 vertices_per_patch
, vertex_index
);
1439 base_addr
= rel_patch_id
;
1442 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1443 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1444 param_stride
, ""), "");
1446 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1448 if (!vertex_index
) {
1449 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1451 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1452 patch_data_offset
, "");
1457 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1459 unsigned const_index
,
1461 LLVMValueRef vertex_index
,
1462 LLVMValueRef indir_index
)
1464 LLVMValueRef param_index
;
1467 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1470 if (const_index
&& !is_compact
)
1471 param
+= const_index
;
1472 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1474 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1478 get_dw_address(struct radv_shader_context
*ctx
,
1479 LLVMValueRef dw_addr
,
1481 unsigned const_index
,
1482 bool compact_const_index
,
1483 LLVMValueRef vertex_index
,
1484 LLVMValueRef stride
,
1485 LLVMValueRef indir_index
)
1490 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1491 LLVMBuildMul(ctx
->ac
.builder
,
1497 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1498 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1499 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1500 else if (const_index
&& !compact_const_index
)
1501 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1502 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1504 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1505 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1507 if (const_index
&& compact_const_index
)
1508 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1509 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1514 load_tcs_varyings(struct ac_shader_abi
*abi
,
1516 LLVMValueRef vertex_index
,
1517 LLVMValueRef indir_index
,
1518 unsigned const_index
,
1520 unsigned driver_location
,
1522 unsigned num_components
,
1527 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1528 LLVMValueRef dw_addr
, stride
;
1529 LLVMValueRef value
[4], result
;
1530 unsigned param
= shader_io_get_unique_index(location
);
1533 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1534 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1535 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1538 stride
= get_tcs_out_vertex_stride(ctx
);
1539 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1541 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1546 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1549 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1550 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1551 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1554 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1559 store_tcs_output(struct ac_shader_abi
*abi
,
1560 const nir_variable
*var
,
1561 LLVMValueRef vertex_index
,
1562 LLVMValueRef param_index
,
1563 unsigned const_index
,
1567 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1568 const unsigned location
= var
->data
.location
;
1569 unsigned component
= var
->data
.location_frac
;
1570 const bool is_patch
= var
->data
.patch
;
1571 const bool is_compact
= var
->data
.compact
;
1572 LLVMValueRef dw_addr
;
1573 LLVMValueRef stride
= NULL
;
1574 LLVMValueRef buf_addr
= NULL
;
1576 bool store_lds
= true;
1579 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1582 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
1586 param
= shader_io_get_unique_index(location
);
1587 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1588 const_index
+= component
;
1591 if (const_index
>= 4) {
1598 stride
= get_tcs_out_vertex_stride(ctx
);
1599 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1601 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1604 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1606 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1607 vertex_index
, param_index
);
1609 bool is_tess_factor
= false;
1610 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1611 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1612 is_tess_factor
= true;
1614 unsigned base
= is_compact
? const_index
: 0;
1615 for (unsigned chan
= 0; chan
< 8; chan
++) {
1616 if (!(writemask
& (1 << chan
)))
1618 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1619 value
= ac_to_integer(&ctx
->ac
, value
);
1620 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
1622 if (store_lds
|| is_tess_factor
) {
1623 LLVMValueRef dw_addr_chan
=
1624 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1625 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1626 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1629 if (!is_tess_factor
&& writemask
!= 0xF)
1630 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1631 buf_addr
, ctx
->oc_lds
,
1632 4 * (base
+ chan
), ac_glc
, false);
1635 if (writemask
== 0xF) {
1636 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1637 buf_addr
, ctx
->oc_lds
,
1638 (base
* 4), ac_glc
, false);
1643 load_tes_input(struct ac_shader_abi
*abi
,
1645 LLVMValueRef vertex_index
,
1646 LLVMValueRef param_index
,
1647 unsigned const_index
,
1649 unsigned driver_location
,
1651 unsigned num_components
,
1656 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1657 LLVMValueRef buf_addr
;
1658 LLVMValueRef result
;
1659 unsigned param
= shader_io_get_unique_index(location
);
1661 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1662 const_index
+= component
;
1664 if (const_index
>= 4) {
1670 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1671 is_compact
, vertex_index
, param_index
);
1673 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1674 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1676 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1677 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
1678 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1683 load_gs_input(struct ac_shader_abi
*abi
,
1685 unsigned driver_location
,
1687 unsigned num_components
,
1688 unsigned vertex_index
,
1689 unsigned const_index
,
1692 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1693 LLVMValueRef vtx_offset
;
1694 unsigned param
, vtx_offset_param
;
1695 LLVMValueRef value
[4], result
;
1697 vtx_offset_param
= vertex_index
;
1698 assert(vtx_offset_param
< 6);
1699 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1700 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1702 param
= shader_io_get_unique_index(location
);
1704 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1705 if (ctx
->ac
.chip_class
>= GFX9
) {
1706 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1707 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1708 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1709 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1711 LLVMValueRef soffset
=
1712 LLVMConstInt(ctx
->ac
.i32
,
1713 (param
* 4 + i
+ const_index
) * 256,
1716 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1719 vtx_offset
, soffset
,
1720 0, ac_glc
, true, false);
1723 if (ac_get_type_size(type
) == 2) {
1724 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
1725 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
1727 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
1729 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1730 result
= ac_to_integer(&ctx
->ac
, result
);
1735 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1737 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1738 ac_build_kill_if_false(&ctx
->ac
, visible
);
1741 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
1742 enum glsl_interp_mode interp
, unsigned location
)
1744 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1747 case INTERP_MODE_FLAT
:
1750 case INTERP_MODE_SMOOTH
:
1751 case INTERP_MODE_NONE
:
1752 if (location
== INTERP_CENTER
)
1753 return ctx
->persp_center
;
1754 else if (location
== INTERP_CENTROID
)
1755 return ctx
->persp_centroid
;
1756 else if (location
== INTERP_SAMPLE
)
1757 return ctx
->persp_sample
;
1759 case INTERP_MODE_NOPERSPECTIVE
:
1760 if (location
== INTERP_CENTER
)
1761 return ctx
->linear_center
;
1762 else if (location
== INTERP_CENTROID
)
1763 return ctx
->linear_centroid
;
1764 else if (location
== INTERP_SAMPLE
)
1765 return ctx
->linear_sample
;
1772 radv_get_sample_pos_offset(uint32_t num_samples
)
1774 uint32_t sample_pos_offset
= 0;
1776 switch (num_samples
) {
1778 sample_pos_offset
= 1;
1781 sample_pos_offset
= 3;
1784 sample_pos_offset
= 7;
1789 return sample_pos_offset
;
1792 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1793 LLVMValueRef sample_id
)
1795 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1797 LLVMValueRef result
;
1798 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
1799 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
1801 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1802 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1804 uint32_t sample_pos_offset
=
1805 radv_get_sample_pos_offset(ctx
->options
->key
.fs
.num_samples
);
1808 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
1809 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
1810 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1816 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1818 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1819 uint8_t log2_ps_iter_samples
;
1821 if (ctx
->shader_info
->info
.ps
.force_persample
) {
1822 log2_ps_iter_samples
=
1823 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
1825 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
1828 /* The bit pattern matches that used by fixed function fragment
1830 static const uint16_t ps_iter_masks
[] = {
1831 0xffff, /* not used */
1837 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1839 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1841 LLVMValueRef result
, sample_id
;
1842 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
1843 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1844 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
1850 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1852 LLVMValueRef gs_next_vertex
;
1853 LLVMValueRef can_emit
;
1854 unsigned offset
= 0;
1855 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1857 /* Write vertex attribute values to GSVS ring */
1858 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1859 ctx
->gs_next_vertex
[stream
],
1862 /* If this thread has already emitted the declared maximum number of
1863 * vertices, kill it: excessive vertex emissions are not supposed to
1864 * have any effect, and GS threads have no externally observable
1865 * effects other than emitting vertices.
1867 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1868 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
1869 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1871 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1872 unsigned output_usage_mask
=
1873 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
1874 uint8_t output_stream
=
1875 ctx
->shader_info
->info
.gs
.output_streams
[i
];
1876 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1877 int length
= util_last_bit(output_usage_mask
);
1879 if (!(ctx
->output_mask
& (1ull << i
)) ||
1880 output_stream
!= stream
)
1883 for (unsigned j
= 0; j
< length
; j
++) {
1884 if (!(output_usage_mask
& (1 << j
)))
1887 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1889 LLVMValueRef voffset
=
1890 LLVMConstInt(ctx
->ac
.i32
, offset
*
1891 ctx
->gs_max_out_vertices
, false);
1895 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1896 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1898 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1899 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1901 ac_build_buffer_store_dword(&ctx
->ac
,
1902 ctx
->gsvs_ring
[stream
],
1904 voffset
, ctx
->gs2vs_offset
, 0,
1905 ac_glc
| ac_slc
, true);
1909 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1911 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1913 ac_build_sendmsg(&ctx
->ac
,
1914 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1919 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1921 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1922 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1926 load_tess_coord(struct ac_shader_abi
*abi
)
1928 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1930 LLVMValueRef coord
[4] = {
1937 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
1938 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1939 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1941 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1945 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1947 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1948 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
1952 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1954 return abi
->base_vertex
;
1957 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1958 LLVMValueRef buffer_ptr
, bool write
)
1960 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1961 LLVMValueRef result
;
1963 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1965 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1966 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1971 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1973 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1974 LLVMValueRef result
;
1976 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
1977 /* Do not load the descriptor for inlined uniform blocks. */
1981 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1983 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1984 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1989 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1990 unsigned descriptor_set
,
1991 unsigned base_index
,
1992 unsigned constant_index
,
1994 enum ac_descriptor_type desc_type
,
1995 bool image
, bool write
,
1998 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1999 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
2000 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
2001 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
2002 unsigned offset
= binding
->offset
;
2003 unsigned stride
= binding
->size
;
2005 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2008 assert(base_index
< layout
->binding_count
);
2010 switch (desc_type
) {
2012 type
= ctx
->ac
.v8i32
;
2016 type
= ctx
->ac
.v8i32
;
2020 case AC_DESC_SAMPLER
:
2021 type
= ctx
->ac
.v4i32
;
2022 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
2023 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
2028 case AC_DESC_BUFFER
:
2029 type
= ctx
->ac
.v4i32
;
2032 case AC_DESC_PLANE_0
:
2033 case AC_DESC_PLANE_1
:
2034 case AC_DESC_PLANE_2
:
2035 type
= ctx
->ac
.v8i32
;
2037 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
2040 unreachable("invalid desc_type\n");
2043 offset
+= constant_index
* stride
;
2045 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
2046 (!index
|| binding
->immutable_samplers_equal
)) {
2047 if (binding
->immutable_samplers_equal
)
2050 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
2052 LLVMValueRef constants
[] = {
2053 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
2054 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
2055 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
2056 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
2058 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
2061 assert(stride
% type_size
== 0);
2063 LLVMValueRef adjusted_index
= index
;
2064 if (!adjusted_index
)
2065 adjusted_index
= ctx
->ac
.i32_0
;
2067 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
2069 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
2070 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
2071 list
= LLVMBuildPointerCast(builder
, list
,
2072 ac_array_in_const32_addr_space(type
), "");
2074 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
2076 /* 3 plane formats always have same size and format for plane 1 & 2, so
2077 * use the tail from plane 1 so that we can store only the first 16 bytes
2078 * of the last plane. */
2079 if (desc_type
== AC_DESC_PLANE_2
) {
2080 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
2082 LLVMValueRef components
[8];
2083 for (unsigned i
= 0; i
< 4; ++i
)
2084 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
2086 for (unsigned i
= 4; i
< 8; ++i
)
2087 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
2088 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
2094 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
2095 * so we may need to fix it up. */
2097 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
2098 unsigned adjustment
,
2101 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
2104 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
2106 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2108 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
2109 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2111 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
2113 /* For the integer-like cases, do a natural sign extension.
2115 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2116 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2119 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
2120 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
2121 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
2122 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
2124 /* Convert back to the right type. */
2125 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
2127 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
2128 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2129 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
2130 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
2131 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
2132 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2135 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2139 get_num_channels_from_data_format(unsigned data_format
)
2141 switch (data_format
) {
2142 case V_008F0C_BUF_DATA_FORMAT_8
:
2143 case V_008F0C_BUF_DATA_FORMAT_16
:
2144 case V_008F0C_BUF_DATA_FORMAT_32
:
2146 case V_008F0C_BUF_DATA_FORMAT_8_8
:
2147 case V_008F0C_BUF_DATA_FORMAT_16_16
:
2148 case V_008F0C_BUF_DATA_FORMAT_32_32
:
2150 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
2151 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
2152 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
2154 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
2155 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
2156 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
2157 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
2158 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
2168 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
2170 unsigned num_channels
,
2173 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
2174 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
2175 LLVMValueRef chan
[4];
2177 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
2178 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
2180 if (num_channels
== 4 && num_channels
== vec_size
)
2183 num_channels
= MIN2(num_channels
, vec_size
);
2185 for (unsigned i
= 0; i
< num_channels
; i
++)
2186 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
2189 assert(num_channels
== 1);
2194 for (unsigned i
= num_channels
; i
< 4; i
++) {
2195 chan
[i
] = i
== 3 ? one
: zero
;
2196 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
2199 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
2203 handle_vs_input_decl(struct radv_shader_context
*ctx
,
2204 struct nir_variable
*variable
)
2206 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
2207 LLVMValueRef t_offset
;
2208 LLVMValueRef t_list
;
2210 LLVMValueRef buffer_index
;
2211 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
2212 uint8_t input_usage_mask
=
2213 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
2214 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
2216 variable
->data
.driver_location
= variable
->data
.location
* 4;
2218 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
2219 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
2220 LLVMValueRef output
[4];
2221 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
2222 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
2223 unsigned data_format
= attrib_format
& 0x0f;
2224 unsigned num_format
= (attrib_format
>> 4) & 0x07;
2225 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
2226 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
2228 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
2229 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
2232 buffer_index
= ctx
->abi
.instance_id
;
2235 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
2236 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
2239 buffer_index
= ctx
->ac
.i32_0
;
2242 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.start_instance
, buffer_index
, "");
2244 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
2245 ctx
->abi
.base_vertex
, "");
2247 /* Adjust the number of channels to load based on the vertex
2250 unsigned num_format_channels
= get_num_channels_from_data_format(data_format
);
2251 unsigned num_channels
= MIN2(num_input_channels
, num_format_channels
);
2252 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
2253 unsigned attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
2254 unsigned attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
2256 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2257 /* Always load, at least, 3 channels for formats that
2258 * need to be shuffled because X<->Z.
2260 num_channels
= MAX2(num_channels
, 3);
2263 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
2264 LLVMValueRef buffer_offset
=
2265 LLVMConstInt(ctx
->ac
.i32
,
2266 attrib_offset
/ attrib_stride
, false);
2268 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
2272 attrib_offset
= attrib_offset
% attrib_stride
;
2275 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
2276 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
2278 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
2280 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
2281 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
2283 data_format
, num_format
, 0, true);
2285 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2287 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
2288 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
2289 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
2290 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
2292 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
2295 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
2298 for (unsigned chan
= 0; chan
< 4; chan
++) {
2299 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2300 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
2301 if (type
== GLSL_TYPE_FLOAT16
) {
2302 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
2303 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
2307 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
2308 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
2310 for (unsigned chan
= 0; chan
< 4; chan
++) {
2311 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
2312 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
2313 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
2315 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
2321 handle_vs_inputs(struct radv_shader_context
*ctx
,
2322 struct nir_shader
*nir
) {
2323 nir_foreach_variable(variable
, &nir
->inputs
)
2324 handle_vs_input_decl(ctx
, variable
);
2328 prepare_interp_optimize(struct radv_shader_context
*ctx
,
2329 struct nir_shader
*nir
)
2331 bool uses_center
= false;
2332 bool uses_centroid
= false;
2333 nir_foreach_variable(variable
, &nir
->inputs
) {
2334 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
2335 variable
->data
.sample
)
2338 if (variable
->data
.centroid
)
2339 uses_centroid
= true;
2344 if (uses_center
&& uses_centroid
) {
2345 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
2346 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
2347 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
2352 scan_shader_output_decl(struct radv_shader_context
*ctx
,
2353 struct nir_variable
*variable
,
2354 struct nir_shader
*shader
,
2355 gl_shader_stage stage
)
2357 int idx
= variable
->data
.location
+ variable
->data
.index
;
2358 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2359 uint64_t mask_attribs
;
2361 variable
->data
.driver_location
= idx
* 4;
2363 /* tess ctrl has it's own load/store paths for outputs */
2364 if (stage
== MESA_SHADER_TESS_CTRL
)
2367 if (variable
->data
.compact
) {
2368 unsigned component_count
= variable
->data
.location_frac
+
2369 glsl_get_length(variable
->type
);
2370 attrib_count
= (component_count
+ 3) / 4;
2373 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2374 if (stage
== MESA_SHADER_VERTEX
||
2375 stage
== MESA_SHADER_TESS_EVAL
||
2376 stage
== MESA_SHADER_GEOMETRY
) {
2377 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2378 if (stage
== MESA_SHADER_VERTEX
) {
2379 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2380 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2381 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2383 if (stage
== MESA_SHADER_TESS_EVAL
) {
2384 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2385 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2386 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2391 ctx
->output_mask
|= mask_attribs
;
2395 /* Initialize arguments for the shader export intrinsic */
2397 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2398 LLVMValueRef
*values
,
2399 unsigned enabled_channels
,
2401 struct ac_export_args
*args
)
2403 /* Specify the channels that are enabled. */
2404 args
->enabled_channels
= enabled_channels
;
2406 /* Specify whether the EXEC mask represents the valid mask */
2407 args
->valid_mask
= 0;
2409 /* Specify whether this is the last export */
2412 /* Specify the target we are exporting */
2413 args
->target
= target
;
2415 args
->compr
= false;
2416 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2417 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2418 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2419 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2424 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
2425 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2426 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2427 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2428 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2429 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2432 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2433 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2434 unsigned bits
, bool hi
) = NULL
;
2436 switch(col_format
) {
2437 case V_028714_SPI_SHADER_ZERO
:
2438 args
->enabled_channels
= 0; /* writemask */
2439 args
->target
= V_008DFC_SQ_EXP_NULL
;
2442 case V_028714_SPI_SHADER_32_R
:
2443 args
->enabled_channels
= 1;
2444 args
->out
[0] = values
[0];
2447 case V_028714_SPI_SHADER_32_GR
:
2448 args
->enabled_channels
= 0x3;
2449 args
->out
[0] = values
[0];
2450 args
->out
[1] = values
[1];
2453 case V_028714_SPI_SHADER_32_AR
:
2454 if (ctx
->ac
.chip_class
>= GFX10
) {
2455 args
->enabled_channels
= 0x3;
2456 args
->out
[0] = values
[0];
2457 args
->out
[1] = values
[3];
2459 args
->enabled_channels
= 0x9;
2460 args
->out
[0] = values
[0];
2461 args
->out
[3] = values
[3];
2465 case V_028714_SPI_SHADER_FP16_ABGR
:
2466 args
->enabled_channels
= 0x5;
2467 packf
= ac_build_cvt_pkrtz_f16
;
2469 for (unsigned chan
= 0; chan
< 4; chan
++)
2470 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
2476 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2477 args
->enabled_channels
= 0x5;
2478 packf
= ac_build_cvt_pknorm_u16
;
2481 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2482 args
->enabled_channels
= 0x5;
2483 packf
= ac_build_cvt_pknorm_i16
;
2486 case V_028714_SPI_SHADER_UINT16_ABGR
:
2487 args
->enabled_channels
= 0x5;
2488 packi
= ac_build_cvt_pk_u16
;
2490 for (unsigned chan
= 0; chan
< 4; chan
++)
2491 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
2492 ac_to_integer(&ctx
->ac
, values
[chan
]),
2497 case V_028714_SPI_SHADER_SINT16_ABGR
:
2498 args
->enabled_channels
= 0x5;
2499 packi
= ac_build_cvt_pk_i16
;
2501 for (unsigned chan
= 0; chan
< 4; chan
++)
2502 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
2503 ac_to_integer(&ctx
->ac
, values
[chan
]),
2509 case V_028714_SPI_SHADER_32_ABGR
:
2510 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2514 /* Pack f16 or norm_i16/u16. */
2516 for (chan
= 0; chan
< 2; chan
++) {
2517 LLVMValueRef pack_args
[2] = {
2519 values
[2 * chan
+ 1]
2521 LLVMValueRef packed
;
2523 packed
= packf(&ctx
->ac
, pack_args
);
2524 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2526 args
->compr
= 1; /* COMPR flag */
2531 for (chan
= 0; chan
< 2; chan
++) {
2532 LLVMValueRef pack_args
[2] = {
2533 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2534 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2536 LLVMValueRef packed
;
2538 packed
= packi(&ctx
->ac
, pack_args
,
2539 is_int8
? 8 : is_int10
? 10 : 16,
2541 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2543 args
->compr
= 1; /* COMPR flag */
2549 for (unsigned chan
= 0; chan
< 4; chan
++) {
2550 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
2551 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
2554 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2556 for (unsigned i
= 0; i
< 4; ++i
)
2557 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2561 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2562 LLVMValueRef
*values
, unsigned enabled_channels
)
2564 struct ac_export_args args
;
2566 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2567 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2568 ac_build_export(&ctx
->ac
, &args
);
2572 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2574 LLVMValueRef output
=
2575 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2577 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2581 radv_emit_stream_output(struct radv_shader_context
*ctx
,
2582 LLVMValueRef
const *so_buffers
,
2583 LLVMValueRef
const *so_write_offsets
,
2584 const struct radv_stream_output
*output
)
2586 unsigned num_comps
= util_bitcount(output
->component_mask
);
2587 unsigned loc
= output
->location
;
2588 unsigned buf
= output
->buffer
;
2589 unsigned offset
= output
->offset
;
2591 LLVMValueRef out
[4];
2593 assert(num_comps
&& num_comps
<= 4);
2594 if (!num_comps
|| num_comps
> 4)
2597 /* Get the first component. */
2598 start
= ffs(output
->component_mask
) - 1;
2600 /* Load the output as int. */
2601 for (int i
= 0; i
< num_comps
; i
++) {
2602 out
[i
] = ac_to_integer(&ctx
->ac
,
2603 radv_load_output(ctx
, loc
, start
+ i
));
2606 /* Pack the output. */
2607 LLVMValueRef vdata
= NULL
;
2609 switch (num_comps
) {
2610 case 1: /* as i32 */
2613 case 2: /* as v2i32 */
2614 case 3: /* as v4i32 (aligned to 4) */
2615 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
2617 case 4: /* as v4i32 */
2618 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
2619 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
2620 util_next_power_of_two(num_comps
) :
2625 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
2626 vdata
, num_comps
, so_write_offsets
[buf
],
2627 ctx
->ac
.i32_0
, offset
,
2628 ac_glc
| ac_slc
, false);
2632 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
2634 struct ac_build_if_state if_ctx
;
2637 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2638 assert(ctx
->streamout_config
);
2639 LLVMValueRef so_vtx_count
=
2640 ac_build_bfe(&ctx
->ac
, ctx
->streamout_config
,
2641 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2642 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
2644 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2646 /* can_emit = tid < so_vtx_count; */
2647 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
2648 tid
, so_vtx_count
, "");
2650 /* Emit the streamout code conditionally. This actually avoids
2651 * out-of-bounds buffer access. The hw tells us via the SGPR
2652 * (so_vtx_count) which threads are allowed to emit streamout data.
2654 ac_nir_build_if(&if_ctx
, ctx
, can_emit
);
2656 /* The buffer offset is computed as follows:
2657 * ByteOffset = streamout_offset[buffer_id]*4 +
2658 * (streamout_write_index + thread_id)*stride[buffer_id] +
2661 LLVMValueRef so_write_index
= ctx
->streamout_write_idx
;
2663 /* Compute (streamout_write_index + thread_id). */
2665 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
2667 /* Load the descriptor and compute the write offset for each
2670 LLVMValueRef so_write_offset
[4] = {};
2671 LLVMValueRef so_buffers
[4] = {};
2672 LLVMValueRef buf_ptr
= ctx
->streamout_buffers
;
2674 for (i
= 0; i
< 4; i
++) {
2675 uint16_t stride
= ctx
->shader_info
->info
.so
.strides
[i
];
2680 LLVMValueRef offset
=
2681 LLVMConstInt(ctx
->ac
.i32
, i
, false);
2683 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
2686 LLVMValueRef so_offset
= ctx
->streamout_offset
[i
];
2688 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
2689 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2691 so_write_offset
[i
] =
2692 ac_build_imad(&ctx
->ac
, so_write_index
,
2693 LLVMConstInt(ctx
->ac
.i32
,
2698 /* Write streamout data. */
2699 for (i
= 0; i
< ctx
->shader_info
->info
.so
.num_outputs
; i
++) {
2700 struct radv_stream_output
*output
=
2701 &ctx
->shader_info
->info
.so
.outputs
[i
];
2703 if (stream
!= output
->stream
)
2706 radv_emit_stream_output(ctx
, so_buffers
,
2707 so_write_offset
, output
);
2710 ac_nir_build_endif(&if_ctx
);
2714 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2715 bool export_prim_id
,
2716 bool export_clip_dists
,
2717 struct radv_vs_output_info
*outinfo
)
2719 uint32_t param_count
= 0;
2721 unsigned pos_idx
, num_pos_exports
= 0;
2722 struct ac_export_args args
, pos_args
[4] = {};
2723 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2726 if (ctx
->options
->key
.has_multiview_view_index
) {
2727 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2729 for(unsigned i
= 0; i
< 4; ++i
)
2730 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2731 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2734 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
2735 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2738 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2739 sizeof(outinfo
->vs_output_param_offset
));
2741 for(unsigned location
= VARYING_SLOT_CLIP_DIST0
; location
<= VARYING_SLOT_CLIP_DIST1
; ++location
) {
2742 if (ctx
->output_mask
& (1ull << location
)) {
2743 unsigned output_usage_mask
, length
;
2744 LLVMValueRef slots
[4];
2747 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2748 !ctx
->is_gs_copy_shader
) {
2750 ctx
->shader_info
->info
.vs
.output_usage_mask
[location
];
2751 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2753 ctx
->shader_info
->info
.tes
.output_usage_mask
[location
];
2755 assert(ctx
->is_gs_copy_shader
);
2757 ctx
->shader_info
->info
.gs
.output_usage_mask
[location
];
2760 length
= util_last_bit(output_usage_mask
);
2762 for (j
= 0; j
< length
; j
++)
2763 slots
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, location
, j
));
2765 for (i
= length
; i
< 4; i
++)
2766 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
2768 target
= V_008DFC_SQ_EXP_POS
+ 2 + (location
- VARYING_SLOT_CLIP_DIST0
);
2769 si_llvm_init_export_args(ctx
, &slots
[0], 0xf, target
, &args
);
2770 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2771 &args
, sizeof(args
));
2773 if (export_clip_dists
) {
2774 /* Export the clip/cull distances values to the next stage. */
2775 radv_export_param(ctx
, param_count
, &slots
[0], 0xf);
2776 outinfo
->vs_output_param_offset
[location
] = param_count
++;
2781 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
2782 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
2783 for (unsigned j
= 0; j
< 4; j
++)
2784 pos_values
[j
] = radv_load_output(ctx
, VARYING_SLOT_POS
, j
);
2786 si_llvm_init_export_args(ctx
, pos_values
, 0xf, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2788 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
2789 outinfo
->writes_pointsize
= true;
2790 psize_value
= radv_load_output(ctx
, VARYING_SLOT_PSIZ
, 0);
2793 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
2794 outinfo
->writes_layer
= true;
2795 layer_value
= radv_load_output(ctx
, VARYING_SLOT_LAYER
, 0);
2798 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
2799 outinfo
->writes_viewport_index
= true;
2800 viewport_index_value
= radv_load_output(ctx
, VARYING_SLOT_VIEWPORT
, 0);
2803 if (ctx
->shader_info
->info
.so
.num_outputs
&&
2804 !ctx
->is_gs_copy_shader
) {
2805 /* The GS copy shader emission already emits streamout. */
2806 radv_emit_streamout(ctx
, 0);
2809 if (outinfo
->writes_pointsize
||
2810 outinfo
->writes_layer
||
2811 outinfo
->writes_viewport_index
) {
2812 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2813 (outinfo
->writes_layer
== true ? 4 : 0));
2814 pos_args
[1].valid_mask
= 0;
2815 pos_args
[1].done
= 0;
2816 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2817 pos_args
[1].compr
= 0;
2818 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2819 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2820 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2821 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2823 if (outinfo
->writes_pointsize
== true)
2824 pos_args
[1].out
[0] = psize_value
;
2825 if (outinfo
->writes_layer
== true)
2826 pos_args
[1].out
[2] = layer_value
;
2827 if (outinfo
->writes_viewport_index
== true) {
2828 if (ctx
->options
->chip_class
>= GFX9
) {
2829 /* GFX9 has the layer in out.z[10:0] and the viewport
2830 * index in out.z[19:16].
2832 LLVMValueRef v
= viewport_index_value
;
2833 v
= ac_to_integer(&ctx
->ac
, v
);
2834 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2835 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2837 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2838 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2840 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2841 pos_args
[1].enabled_channels
|= 1 << 2;
2843 pos_args
[1].out
[3] = viewport_index_value
;
2844 pos_args
[1].enabled_channels
|= 1 << 3;
2848 for (i
= 0; i
< 4; i
++) {
2849 if (pos_args
[i
].out
[0])
2853 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2854 * Setting valid_mask=1 prevents it and has no other effect.
2856 if (ctx
->ac
.family
== CHIP_NAVI10
||
2857 ctx
->ac
.family
== CHIP_NAVI12
||
2858 ctx
->ac
.family
== CHIP_NAVI14
)
2859 pos_args
[0].valid_mask
= 1;
2862 for (i
= 0; i
< 4; i
++) {
2863 if (!pos_args
[i
].out
[0])
2866 /* Specify the target we are exporting */
2867 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2868 if (pos_idx
== num_pos_exports
)
2869 pos_args
[i
].done
= 1;
2870 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2873 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2874 LLVMValueRef values
[4];
2875 if (!(ctx
->output_mask
& (1ull << i
)))
2878 if (i
!= VARYING_SLOT_LAYER
&&
2879 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
2880 i
< VARYING_SLOT_VAR0
)
2883 for (unsigned j
= 0; j
< 4; j
++)
2884 values
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2886 unsigned output_usage_mask
;
2888 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2889 !ctx
->is_gs_copy_shader
) {
2891 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2892 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2894 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2896 assert(ctx
->is_gs_copy_shader
);
2898 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
2901 radv_export_param(ctx
, param_count
, values
, output_usage_mask
);
2903 outinfo
->vs_output_param_offset
[i
] = param_count
++;
2906 if (export_prim_id
) {
2907 LLVMValueRef values
[4];
2909 values
[0] = ctx
->vs_prim_id
;
2910 for (unsigned j
= 1; j
< 4; j
++)
2911 values
[j
] = ctx
->ac
.f32_0
;
2913 radv_export_param(ctx
, param_count
, values
, 0x1);
2915 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
2916 outinfo
->export_prim_id
= true;
2919 outinfo
->pos_exports
= num_pos_exports
;
2920 outinfo
->param_exports
= param_count
;
2924 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2925 struct radv_es_output_info
*outinfo
)
2928 uint64_t max_output_written
= 0;
2929 LLVMValueRef lds_base
= NULL
;
2931 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2934 if (!(ctx
->output_mask
& (1ull << i
)))
2937 param_index
= shader_io_get_unique_index(i
);
2939 max_output_written
= MAX2(param_index
, max_output_written
);
2942 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
2944 if (ctx
->ac
.chip_class
>= GFX9
) {
2945 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2946 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2947 LLVMValueRef wave_idx
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
2948 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2949 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2950 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
2951 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2952 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2955 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2956 LLVMValueRef dw_addr
= NULL
;
2957 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2958 unsigned output_usage_mask
;
2961 if (!(ctx
->output_mask
& (1ull << i
)))
2964 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2966 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2968 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2970 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2973 param_index
= shader_io_get_unique_index(i
);
2976 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2977 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
2981 for (j
= 0; j
< 4; j
++) {
2982 if (!(output_usage_mask
& (1 << j
)))
2985 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2986 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
2987 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
2989 if (ctx
->ac
.chip_class
>= GFX9
) {
2990 LLVMValueRef dw_addr_offset
=
2991 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2992 LLVMConstInt(ctx
->ac
.i32
,
2995 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
2997 ac_build_buffer_store_dword(&ctx
->ac
,
3000 NULL
, ctx
->es2gs_offset
,
3001 (4 * param_index
+ j
) * 4,
3002 ac_glc
| ac_slc
, true);
3009 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
3011 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
3012 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->shader_info
->info
.vs
.ls_outputs_written
);
3013 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
3014 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
3015 vertex_dw_stride
, "");
3017 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3018 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
3020 if (!(ctx
->output_mask
& (1ull << i
)))
3023 int param
= shader_io_get_unique_index(i
);
3024 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
3025 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
3027 for (unsigned j
= 0; j
< 4; j
++) {
3028 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
3029 value
= ac_to_integer(&ctx
->ac
, value
);
3030 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
3031 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
3032 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
3037 static LLVMValueRef
get_wave_id_in_tg(struct radv_shader_context
*ctx
)
3039 return ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
3042 static LLVMValueRef
ngg_get_vtx_cnt(struct radv_shader_context
*ctx
)
3044 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
3045 LLVMConstInt(ctx
->ac
.i32
, 12, false),
3046 LLVMConstInt(ctx
->ac
.i32
, 9, false),
3050 static LLVMValueRef
ngg_get_prim_cnt(struct radv_shader_context
*ctx
)
3052 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
3053 LLVMConstInt(ctx
->ac
.i32
, 22, false),
3054 LLVMConstInt(ctx
->ac
.i32
, 9, false),
3058 /* Send GS Alloc Req message from the first wave of the group to SPI.
3059 * Message payload is:
3060 * - bits 0..10: vertices in group
3061 * - bits 12..22: primitives in group
3063 static void build_sendmsg_gs_alloc_req(struct radv_shader_context
*ctx
,
3064 LLVMValueRef vtx_cnt
,
3065 LLVMValueRef prim_cnt
)
3067 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3070 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
3071 ac_build_ifcc(&ctx
->ac
, tmp
, 5020);
3073 tmp
= LLVMBuildShl(builder
, prim_cnt
, LLVMConstInt(ctx
->ac
.i32
, 12, false),"");
3074 tmp
= LLVMBuildOr(builder
, tmp
, vtx_cnt
, "");
3075 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_ALLOC_REQ
, tmp
);
3077 ac_build_endif(&ctx
->ac
, 5020);
3081 unsigned num_vertices
;
3082 LLVMValueRef isnull
;
3083 LLVMValueRef index
[3];
3084 LLVMValueRef edgeflag
[3];
3087 static void build_export_prim(struct radv_shader_context
*ctx
,
3088 const struct ngg_prim
*prim
)
3090 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3091 struct ac_export_args args
;
3094 tmp
= LLVMBuildZExt(builder
, prim
->isnull
, ctx
->ac
.i32
, "");
3095 args
.out
[0] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 31, false), "");
3097 for (unsigned i
= 0; i
< prim
->num_vertices
; ++i
) {
3098 tmp
= LLVMBuildShl(builder
, prim
->index
[i
],
3099 LLVMConstInt(ctx
->ac
.i32
, 10 * i
, false), "");
3100 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3101 tmp
= LLVMBuildZExt(builder
, prim
->edgeflag
[i
], ctx
->ac
.i32
, "");
3102 tmp
= LLVMBuildShl(builder
, tmp
,
3103 LLVMConstInt(ctx
->ac
.i32
, 10 * i
+ 9, false), "");
3104 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3107 args
.out
[0] = LLVMBuildBitCast(builder
, args
.out
[0], ctx
->ac
.f32
, "");
3108 args
.out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
3109 args
.out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
3110 args
.out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
3112 args
.target
= V_008DFC_SQ_EXP_PRIM
;
3113 args
.enabled_channels
= 1;
3115 args
.valid_mask
= false;
3118 ac_build_export(&ctx
->ac
, &args
);
3122 handle_ngg_outputs_post(struct radv_shader_context
*ctx
)
3124 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3125 struct ac_build_if_state if_state
;
3126 unsigned num_vertices
= 3;
3129 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
3130 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->is_gs_copy_shader
);
3132 LLVMValueRef prims_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
3133 LLVMValueRef vtx_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 0, 8);
3134 LLVMValueRef is_gs_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3135 ac_get_thread_id(&ctx
->ac
), prims_in_wave
, "");
3136 LLVMValueRef is_es_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3137 ac_get_thread_id(&ctx
->ac
), vtx_in_wave
, "");
3138 LLVMValueRef vtxindex
[] = {
3139 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 0, 16),
3140 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 16, 16),
3141 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[2], 0, 16),
3144 /* TODO: streamout */
3146 /* TODO: VS primitive ID */
3147 if (ctx
->options
->key
.vs_common_out
.export_prim_id
)
3150 /* TODO: primitive culling */
3152 build_sendmsg_gs_alloc_req(ctx
, ngg_get_vtx_cnt(ctx
), ngg_get_prim_cnt(ctx
));
3154 /* TODO: streamout queries */
3155 /* Export primitive data to the index buffer. Format is:
3156 * - bits 0..8: index 0
3157 * - bit 9: edge flag 0
3158 * - bits 10..18: index 1
3159 * - bit 19: edge flag 1
3160 * - bits 20..28: index 2
3161 * - bit 29: edge flag 2
3162 * - bit 31: null primitive (skip)
3164 * For the first version, we will always build up all three indices
3165 * independent of the primitive type. The additional garbage data
3168 * TODO: culling depends on the primitive type, so can have some
3171 ac_nir_build_if(&if_state
, ctx
, is_gs_thread
);
3173 struct ngg_prim prim
= {};
3175 prim
.num_vertices
= num_vertices
;
3176 prim
.isnull
= ctx
->ac
.i1false
;
3177 memcpy(prim
.index
, vtxindex
, sizeof(vtxindex
[0]) * 3);
3179 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
3180 tmp
= LLVMBuildLShr(builder
, ctx
->abi
.gs_invocation_id
,
3181 LLVMConstInt(ctx
->ac
.i32
, 8 + i
, false), "");
3182 prim
.edgeflag
[i
] = LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3185 build_export_prim(ctx
, &prim
);
3187 ac_nir_build_endif(&if_state
);
3189 /* Export per-vertex data (positions and parameters). */
3190 ac_nir_build_if(&if_state
, ctx
, is_es_thread
);
3192 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
3193 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
3194 ctx
->stage
== MESA_SHADER_TESS_EVAL
? &ctx
->shader_info
->tes
.outinfo
: &ctx
->shader_info
->vs
.outinfo
);
3196 ac_nir_build_endif(&if_state
);
3200 write_tess_factors(struct radv_shader_context
*ctx
)
3202 unsigned stride
, outer_comps
, inner_comps
;
3203 struct ac_build_if_state if_ctx
, inner_if_ctx
;
3204 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3205 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
3206 unsigned tess_inner_index
= 0, tess_outer_index
;
3207 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3208 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3210 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3212 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
3232 ac_nir_build_if(&if_ctx
, ctx
,
3233 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3234 invocation_id
, ctx
->ac
.i32_0
, ""));
3236 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3239 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3240 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3241 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3244 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3245 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3246 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3248 for (i
= 0; i
< 4; i
++) {
3249 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3250 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3254 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3255 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3256 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3258 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3260 for (i
= 0; i
< outer_comps
; i
++) {
3262 ac_lds_load(&ctx
->ac
, lds_outer
);
3263 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3266 for (i
= 0; i
< inner_comps
; i
++) {
3267 inner
[i
] = out
[outer_comps
+i
] =
3268 ac_lds_load(&ctx
->ac
, lds_inner
);
3269 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3274 /* Convert the outputs to vectors for stores. */
3275 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3279 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3282 buffer
= ctx
->hs_ring_tess_factor
;
3283 tf_base
= ctx
->tess_factor_offset
;
3284 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3285 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3286 unsigned tf_offset
= 0;
3288 if (ctx
->options
->chip_class
<= GFX8
) {
3289 ac_nir_build_if(&inner_if_ctx
, ctx
,
3290 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3291 rel_patch_id
, ctx
->ac
.i32_0
, ""));
3293 /* Store the dynamic HS control word. */
3294 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3295 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3296 1, ctx
->ac
.i32_0
, tf_base
,
3300 ac_nir_build_endif(&inner_if_ctx
);
3303 /* Store the tessellation factors. */
3304 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3305 MIN2(stride
, 4), byteoffset
, tf_base
,
3306 tf_offset
, ac_glc
, false);
3308 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3309 stride
- 4, byteoffset
, tf_base
,
3310 16 + tf_offset
, ac_glc
, false);
3312 //store to offchip for TES to read - only if TES reads them
3313 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
3314 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3315 LLVMValueRef tf_inner_offset
;
3316 unsigned param_outer
, param_inner
;
3318 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3319 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3320 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3322 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3323 util_next_power_of_two(outer_comps
));
3325 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3326 outer_comps
, tf_outer_offset
,
3327 ctx
->oc_lds
, 0, ac_glc
, false);
3329 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3330 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3331 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3333 inner_vec
= inner_comps
== 1 ? inner
[0] :
3334 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3335 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3336 inner_comps
, tf_inner_offset
,
3337 ctx
->oc_lds
, 0, ac_glc
, false);
3340 ac_nir_build_endif(&if_ctx
);
3344 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3346 write_tess_factors(ctx
);
3350 si_export_mrt_color(struct radv_shader_context
*ctx
,
3351 LLVMValueRef
*color
, unsigned index
,
3352 struct ac_export_args
*args
)
3355 si_llvm_init_export_args(ctx
, color
, 0xf,
3356 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3357 if (!args
->enabled_channels
)
3358 return false; /* unnecessary NULL export */
3364 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3365 LLVMValueRef depth
, LLVMValueRef stencil
,
3366 LLVMValueRef samplemask
)
3368 struct ac_export_args args
;
3370 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3372 ac_build_export(&ctx
->ac
, &args
);
3376 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3379 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3380 struct ac_export_args color_args
[8];
3382 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3383 LLVMValueRef values
[4];
3385 if (!(ctx
->output_mask
& (1ull << i
)))
3388 if (i
< FRAG_RESULT_DATA0
)
3391 for (unsigned j
= 0; j
< 4; j
++)
3392 values
[j
] = ac_to_float(&ctx
->ac
,
3393 radv_load_output(ctx
, i
, j
));
3395 bool ret
= si_export_mrt_color(ctx
, values
,
3396 i
- FRAG_RESULT_DATA0
,
3397 &color_args
[index
]);
3402 /* Process depth, stencil, samplemask. */
3403 if (ctx
->shader_info
->info
.ps
.writes_z
) {
3404 depth
= ac_to_float(&ctx
->ac
,
3405 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3407 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
3408 stencil
= ac_to_float(&ctx
->ac
,
3409 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
3411 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3412 samplemask
= ac_to_float(&ctx
->ac
,
3413 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
3416 /* Set the DONE bit on last non-null color export only if Z isn't
3420 !ctx
->shader_info
->info
.ps
.writes_z
&&
3421 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
3422 !ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3423 unsigned last
= index
- 1;
3425 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
3426 color_args
[last
].done
= 1; /* DONE bit */
3429 /* Export PS outputs. */
3430 for (unsigned i
= 0; i
< index
; i
++)
3431 ac_build_export(&ctx
->ac
, &color_args
[i
]);
3433 if (depth
|| stencil
|| samplemask
)
3434 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
3436 ac_build_export_null(&ctx
->ac
);
3440 emit_gs_epilogue(struct radv_shader_context
*ctx
)
3442 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
3446 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
3447 LLVMValueRef
*addrs
)
3449 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3451 switch (ctx
->stage
) {
3452 case MESA_SHADER_VERTEX
:
3453 if (ctx
->options
->key
.vs_common_out
.as_ls
)
3454 handle_ls_outputs_post(ctx
);
3455 else if (ctx
->options
->key
.vs_common_out
.as_ngg
)
3456 break; /* handled outside of the shader body */
3457 else if (ctx
->options
->key
.vs_common_out
.as_es
)
3458 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
3460 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
3461 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
3462 &ctx
->shader_info
->vs
.outinfo
);
3464 case MESA_SHADER_FRAGMENT
:
3465 handle_fs_outputs_post(ctx
);
3467 case MESA_SHADER_GEOMETRY
:
3468 emit_gs_epilogue(ctx
);
3470 case MESA_SHADER_TESS_CTRL
:
3471 handle_tcs_outputs_post(ctx
);
3473 case MESA_SHADER_TESS_EVAL
:
3474 if (ctx
->options
->key
.vs_common_out
.as_ngg
)
3475 break; /* handled outside of the shader body */
3476 else if (ctx
->options
->key
.vs_common_out
.as_es
)
3477 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
3479 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
3480 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
3481 &ctx
->shader_info
->tes
.outinfo
);
3488 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
3489 LLVMPassManagerRef passmgr
,
3490 const struct radv_nir_compiler_options
*options
)
3492 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
3493 LLVMDisposeBuilder(ctx
->ac
.builder
);
3495 ac_llvm_context_dispose(&ctx
->ac
);
3499 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
3501 struct radv_vs_output_info
*outinfo
;
3503 switch (ctx
->stage
) {
3504 case MESA_SHADER_FRAGMENT
:
3505 case MESA_SHADER_COMPUTE
:
3506 case MESA_SHADER_TESS_CTRL
:
3507 case MESA_SHADER_GEOMETRY
:
3509 case MESA_SHADER_VERTEX
:
3510 if (ctx
->options
->key
.vs_common_out
.as_ls
||
3511 ctx
->options
->key
.vs_common_out
.as_es
)
3513 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
3515 case MESA_SHADER_TESS_EVAL
:
3516 if (ctx
->options
->key
.vs_common_out
.as_es
)
3518 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
3521 unreachable("Unhandled shader type");
3524 ac_optimize_vs_outputs(&ctx
->ac
,
3526 outinfo
->vs_output_param_offset
,
3528 &outinfo
->param_exports
);
3532 ac_setup_rings(struct radv_shader_context
*ctx
)
3534 if (ctx
->options
->chip_class
<= GFX8
&&
3535 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
3536 ctx
->options
->key
.vs_common_out
.as_es
|| ctx
->options
->key
.vs_common_out
.as_es
)) {
3537 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
3539 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
3541 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
3546 if (ctx
->is_gs_copy_shader
) {
3548 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3549 LLVMConstInt(ctx
->ac
.i32
,
3550 RING_GSVS_VS
, false));
3553 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3554 /* The conceptual layout of the GSVS ring is
3555 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3556 * but the real memory layout is swizzled across
3558 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3560 * Override the buffer descriptor accordingly.
3562 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
3563 uint64_t stream_offset
= 0;
3564 unsigned num_records
= 64;
3565 LLVMValueRef base_ring
;
3568 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3569 LLVMConstInt(ctx
->ac
.i32
,
3570 RING_GSVS_GS
, false));
3572 for (unsigned stream
= 0; stream
< 4; stream
++) {
3573 unsigned num_components
, stride
;
3574 LLVMValueRef ring
, tmp
;
3577 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
3579 if (!num_components
)
3582 stride
= 4 * num_components
* ctx
->gs_max_out_vertices
;
3584 /* Limit on the stride field for <= GFX7. */
3585 assert(stride
< (1 << 14));
3587 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
3588 base_ring
, v2i64
, "");
3589 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3590 ring
, ctx
->ac
.i32_0
, "");
3591 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
3592 LLVMConstInt(ctx
->ac
.i64
,
3593 stream_offset
, 0), "");
3594 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
3595 ring
, tmp
, ctx
->ac
.i32_0
, "");
3597 stream_offset
+= stride
* 64;
3599 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
3602 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
3604 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
3605 LLVMConstInt(ctx
->ac
.i32
,
3606 S_008F04_STRIDE(stride
), false), "");
3607 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
3610 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
3611 LLVMConstInt(ctx
->ac
.i32
,
3612 num_records
, false),
3613 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3615 ctx
->gsvs_ring
[stream
] = ring
;
3619 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3620 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3621 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
3622 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
3627 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
3628 const struct nir_shader
*nir
)
3630 switch (nir
->info
.stage
) {
3631 case MESA_SHADER_TESS_CTRL
:
3632 return chip_class
>= GFX7
? 128 : 64;
3633 case MESA_SHADER_GEOMETRY
:
3634 return chip_class
>= GFX9
? 128 : 64;
3635 case MESA_SHADER_COMPUTE
:
3641 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
3642 nir
->info
.cs
.local_size
[1] *
3643 nir
->info
.cs
.local_size
[2];
3644 return max_workgroup_size
;
3647 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3648 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
3650 LLVMValueRef count
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
3651 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
3653 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
3654 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
3655 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
3658 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
3660 for(int i
= 5; i
>= 0; --i
) {
3661 ctx
->gs_vtx_offset
[i
] = ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
3665 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 16, 8);
3670 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
3671 struct nir_shader
*const *shaders
,
3673 struct radv_shader_variant_info
*shader_info
,
3674 const struct radv_nir_compiler_options
*options
)
3676 struct radv_shader_context ctx
= {0};
3678 ctx
.options
= options
;
3679 ctx
.shader_info
= shader_info
;
3681 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
3682 ctx
.context
= ctx
.ac
.context
;
3683 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
3685 enum ac_float_mode float_mode
=
3686 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
3687 AC_FLOAT_MODE_DEFAULT
;
3689 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
3691 radv_nir_shader_info_init(&shader_info
->info
);
3693 for(int i
= 0; i
< shader_count
; ++i
)
3694 radv_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
3696 for (i
= 0; i
< RADV_UD_MAX_SETS
; i
++)
3697 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
3698 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
3699 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
3701 ctx
.max_workgroup_size
= 0;
3702 for (int i
= 0; i
< shader_count
; ++i
) {
3703 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
3704 radv_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
3708 if (ctx
.ac
.chip_class
>= GFX10
) {
3709 if (is_pre_gs_stage(shaders
[0]->info
.stage
) &&
3710 options
->key
.vs_common_out
.as_ngg
) {
3711 ctx
.max_workgroup_size
= 128;
3715 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
3716 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
3718 ctx
.abi
.inputs
= &ctx
.inputs
[0];
3719 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
3720 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
3721 ctx
.abi
.load_ubo
= radv_load_ubo
;
3722 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
3723 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
3724 ctx
.abi
.load_resource
= radv_load_resource
;
3725 ctx
.abi
.clamp_shadow_reference
= false;
3726 ctx
.abi
.gfx9_stride_size_workaround
= ctx
.ac
.chip_class
== GFX9
&& HAVE_LLVM
< 0x800;
3728 /* Because the new raw/struct atomic intrinsics are buggy with LLVM 8,
3729 * we fallback to the old intrinsics for atomic buffer image operations
3730 * and thus we need to apply the indexing workaround...
3732 ctx
.abi
.gfx9_stride_size_workaround_for_atomic
= ctx
.ac
.chip_class
== GFX9
&& HAVE_LLVM
< 0x900;
3734 bool is_ngg
= is_pre_gs_stage(shaders
[0]->info
.stage
) && ctx
.options
->key
.vs_common_out
.as_ngg
;
3735 if (shader_count
>= 2 || is_ngg
)
3736 ac_init_exec_full_mask(&ctx
.ac
);
3738 if ((ctx
.ac
.family
== CHIP_VEGA10
||
3739 ctx
.ac
.family
== CHIP_RAVEN
) &&
3740 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
3741 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
3743 for(int i
= 0; i
< shader_count
; ++i
) {
3744 ctx
.stage
= shaders
[i
]->info
.stage
;
3745 ctx
.output_mask
= 0;
3747 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3748 for (int i
= 0; i
< 4; i
++) {
3749 ctx
.gs_next_vertex
[i
] =
3750 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
3752 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
3753 ctx
.abi
.load_inputs
= load_gs_input
;
3754 ctx
.abi
.emit_primitive
= visit_end_primitive
;
3755 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3756 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
3757 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
3758 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
3759 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3760 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
3761 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3762 if (shader_count
== 1)
3763 ctx
.tcs_num_inputs
= ctx
.options
->key
.tcs
.num_inputs
;
3765 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->info
.vs
.ls_outputs_written
);
3766 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
3767 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
3768 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
3769 ctx
.abi
.load_tess_varyings
= load_tes_input
;
3770 ctx
.abi
.load_tess_coord
= load_tess_coord
;
3771 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3772 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3773 ctx
.tcs_num_patches
= ctx
.options
->key
.tes
.num_patches
;
3774 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
3775 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
3776 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
3777 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
3778 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
3779 ctx
.abi
.load_sample_position
= load_sample_position
;
3780 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
3781 ctx
.abi
.emit_kill
= radv_emit_kill
;
3785 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
3787 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
3788 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
3790 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3791 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
3792 shaders
[i
]->info
.cull_distance_array_size
> 4;
3793 ctx
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
3794 ctx
.max_gsvs_emit_size
= ctx
.gsvs_vertex_size
*
3795 shaders
[i
]->info
.gs
.vertices_out
;
3798 ac_setup_rings(&ctx
);
3800 LLVMBasicBlockRef merge_block
;
3801 if (shader_count
>= 2 || is_ngg
) {
3802 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
3803 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3804 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3806 LLVMValueRef count
= ac_unpack_param(&ctx
.ac
, ctx
.merged_wave_info
, 8 * i
, 8);
3807 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
3808 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
3809 thread_id
, count
, "");
3810 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
3812 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
3815 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
3816 prepare_interp_optimize(&ctx
, shaders
[i
]);
3817 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
3818 handle_vs_inputs(&ctx
, shaders
[i
]);
3819 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
3820 prepare_gs_input_vgprs(&ctx
);
3822 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
3824 if (shader_count
>= 2 || is_ngg
) {
3825 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
3826 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
3829 /* This needs to be outside the if wrapping the shader body, as sometimes
3830 * the HW generates waves with 0 es/vs threads. */
3831 if (is_pre_gs_stage(shaders
[i
]->info
.stage
) &&
3832 ctx
.options
->key
.vs_common_out
.as_ngg
&&
3833 i
== shader_count
- 1) {
3834 handle_ngg_outputs_post(&ctx
);
3837 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3838 shader_info
->gs
.gsvs_vertex_size
= ctx
.gsvs_vertex_size
;
3839 shader_info
->gs
.max_gsvs_emit_size
= ctx
.max_gsvs_emit_size
;
3840 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3841 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
3842 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
3846 LLVMBuildRetVoid(ctx
.ac
.builder
);
3848 if (options
->dump_preoptir
)
3849 ac_dump_module(ctx
.ac
.module
);
3851 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
3853 if (shader_count
== 1)
3854 ac_nir_eliminate_const_vs_outputs(&ctx
);
3856 if (options
->dump_shader
) {
3857 ctx
.shader_info
->private_mem_vgprs
=
3858 ac_count_scratch_private_memory(ctx
.main_function
);
3861 return ctx
.ac
.module
;
3864 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
3866 unsigned *retval
= (unsigned *)context
;
3867 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
3868 char *description
= LLVMGetDiagInfoDescription(di
);
3870 if (severity
== LLVMDSError
) {
3872 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
3876 LLVMDisposeMessage(description
);
3879 static unsigned radv_llvm_compile(LLVMModuleRef M
,
3880 char **pelf_buffer
, size_t *pelf_size
,
3881 struct ac_llvm_compiler
*ac_llvm
)
3883 unsigned retval
= 0;
3884 LLVMContextRef llvm_ctx
;
3886 /* Setup Diagnostic Handler*/
3887 llvm_ctx
= LLVMGetModuleContext(M
);
3889 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
3893 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
3898 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
3899 LLVMModuleRef llvm_module
,
3900 struct radv_shader_binary
**rbinary
,
3901 struct radv_shader_variant_info
*shader_info
,
3902 gl_shader_stage stage
,
3903 const struct radv_nir_compiler_options
*options
)
3905 char *elf_buffer
= NULL
;
3906 size_t elf_size
= 0;
3907 char *llvm_ir_string
= NULL
;
3908 if (options
->dump_shader
)
3909 ac_dump_module(llvm_module
);
3911 if (options
->record_llvm_ir
) {
3912 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
3913 llvm_ir_string
= strdup(llvm_ir
);
3914 LLVMDisposeMessage(llvm_ir
);
3917 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
3919 fprintf(stderr
, "compile failed\n");
3922 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
3923 LLVMDisposeModule(llvm_module
);
3924 LLVMContextDispose(ctx
);
3926 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
3927 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
3928 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
3929 memcpy(rbin
->data
, elf_buffer
, elf_size
);
3931 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
3933 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
3934 rbin
->base
.stage
= stage
;
3935 rbin
->base
.total_size
= alloc_size
;
3936 rbin
->elf_size
= elf_size
;
3937 rbin
->llvm_ir_size
= llvm_ir_size
;
3938 *rbinary
= &rbin
->base
;
3940 free(llvm_ir_string
);
3945 ac_fill_shader_info(struct radv_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct radv_nir_compiler_options
*options
)
3947 switch (nir
->info
.stage
) {
3948 case MESA_SHADER_COMPUTE
:
3949 for (int i
= 0; i
< 3; ++i
)
3950 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
3952 case MESA_SHADER_FRAGMENT
:
3953 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
3955 case MESA_SHADER_GEOMETRY
:
3956 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
3957 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
3958 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
3959 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
3961 case MESA_SHADER_TESS_EVAL
:
3962 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
3963 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
3964 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
3965 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
3966 shader_info
->tes
.as_es
= options
->key
.vs_common_out
.as_es
;
3967 shader_info
->tes
.export_prim_id
= options
->key
.vs_common_out
.export_prim_id
;
3968 shader_info
->is_ngg
= options
->key
.vs_common_out
.as_ngg
;
3970 case MESA_SHADER_TESS_CTRL
:
3971 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
3973 case MESA_SHADER_VERTEX
:
3974 shader_info
->vs
.as_es
= options
->key
.vs_common_out
.as_es
;
3975 shader_info
->vs
.as_ls
= options
->key
.vs_common_out
.as_ls
;
3976 shader_info
->vs
.export_prim_id
= options
->key
.vs_common_out
.export_prim_id
;
3977 shader_info
->is_ngg
= options
->key
.vs_common_out
.as_ngg
;
3985 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
3986 struct radv_shader_binary
**rbinary
,
3987 struct radv_shader_variant_info
*shader_info
,
3988 struct nir_shader
*const *nir
,
3990 const struct radv_nir_compiler_options
*options
)
3993 LLVMModuleRef llvm_module
;
3995 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, shader_info
,
3998 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
, shader_info
,
3999 nir
[nir_count
- 1]->info
.stage
, options
);
4001 for (int i
= 0; i
< nir_count
; ++i
)
4002 ac_fill_shader_info(shader_info
, nir
[i
], options
);
4004 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4005 if (options
->chip_class
>= GFX9
) {
4006 if (nir_count
== 2 &&
4007 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4008 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
4014 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
4016 LLVMValueRef vtx_offset
=
4017 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
4018 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4019 LLVMValueRef stream_id
;
4021 /* Fetch the vertex stream ID. */
4022 if (ctx
->shader_info
->info
.so
.num_outputs
) {
4024 ac_unpack_param(&ctx
->ac
, ctx
->streamout_config
, 24, 2);
4026 stream_id
= ctx
->ac
.i32_0
;
4029 LLVMBasicBlockRef end_bb
;
4030 LLVMValueRef switch_inst
;
4032 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
4033 ctx
->main_function
, "end");
4034 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
4036 for (unsigned stream
= 0; stream
< 4; stream
++) {
4037 unsigned num_components
=
4038 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
4039 LLVMBasicBlockRef bb
;
4042 if (!num_components
)
4045 if (stream
> 0 && !ctx
->shader_info
->info
.so
.num_outputs
)
4048 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
4049 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
4050 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
4053 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4054 unsigned output_usage_mask
=
4055 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
4056 unsigned output_stream
=
4057 ctx
->shader_info
->info
.gs
.output_streams
[i
];
4058 int length
= util_last_bit(output_usage_mask
);
4060 if (!(ctx
->output_mask
& (1ull << i
)) ||
4061 output_stream
!= stream
)
4064 for (unsigned j
= 0; j
< length
; j
++) {
4065 LLVMValueRef value
, soffset
;
4067 if (!(output_usage_mask
& (1 << j
)))
4070 soffset
= LLVMConstInt(ctx
->ac
.i32
,
4072 ctx
->gs_max_out_vertices
* 16 * 4, false);
4076 value
= ac_build_buffer_load(&ctx
->ac
,
4079 vtx_offset
, soffset
,
4080 0, ac_glc
| ac_slc
, true, false);
4082 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4083 if (ac_get_type_size(type
) == 2) {
4084 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
4085 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
4088 LLVMBuildStore(ctx
->ac
.builder
,
4089 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4093 if (ctx
->shader_info
->info
.so
.num_outputs
)
4094 radv_emit_streamout(ctx
, stream
);
4097 handle_vs_outputs_post(ctx
, false, true,
4098 &ctx
->shader_info
->vs
.outinfo
);
4101 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
4104 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
4108 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
4109 struct nir_shader
*geom_shader
,
4110 struct radv_shader_binary
**rbinary
,
4111 struct radv_shader_variant_info
*shader_info
,
4112 const struct radv_nir_compiler_options
*options
)
4114 struct radv_shader_context ctx
= {0};
4115 ctx
.options
= options
;
4116 ctx
.shader_info
= shader_info
;
4118 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
4119 ctx
.context
= ctx
.ac
.context
;
4120 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
4122 ctx
.is_gs_copy_shader
= true;
4124 enum ac_float_mode float_mode
=
4125 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
4126 AC_FLOAT_MODE_DEFAULT
;
4128 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
4129 ctx
.stage
= MESA_SHADER_VERTEX
;
4131 radv_nir_shader_info_pass(geom_shader
, options
, &shader_info
->info
);
4133 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
4135 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
4136 ac_setup_rings(&ctx
);
4138 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
4139 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
4140 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
4141 variable
, MESA_SHADER_VERTEX
);
4144 ac_gs_copy_shader_emit(&ctx
);
4146 LLVMBuildRetVoid(ctx
.ac
.builder
);
4148 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
4150 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
, shader_info
,
4151 MESA_SHADER_VERTEX
, options
);
4152 (*rbinary
)->is_gs_copy_shader
= true;