2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_llvm_build.h"
42 #include "ac_shader_abi.h"
43 #include "ac_shader_util.h"
44 #include "ac_exp_param.h"
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 struct radv_shader_context
{
49 struct ac_llvm_context ac
;
50 const struct radv_nir_compiler_options
*options
;
51 struct radv_shader_variant_info
*shader_info
;
52 struct ac_shader_abi abi
;
54 unsigned max_workgroup_size
;
55 LLVMContextRef context
;
56 LLVMValueRef main_function
;
58 LLVMValueRef descriptor_sets
[RADV_UD_MAX_SETS
];
59 LLVMValueRef ring_offsets
;
61 LLVMValueRef vertex_buffers
;
62 LLVMValueRef rel_auto_id
;
63 LLVMValueRef vs_prim_id
;
64 LLVMValueRef es2gs_offset
;
67 LLVMValueRef merged_wave_info
;
68 LLVMValueRef tess_factor_offset
;
69 LLVMValueRef tes_rel_patch_id
;
75 * - bits 0..10: ordered_wave_id
76 * - bits 12..20: number of vertices in group
77 * - bits 22..30: number of primitives in group
79 LLVMValueRef gs_tg_info
;
80 LLVMValueRef gs2vs_offset
;
81 LLVMValueRef gs_wave_id
;
82 LLVMValueRef gs_vtx_offset
[6];
84 LLVMValueRef esgs_ring
;
85 LLVMValueRef gsvs_ring
[4];
86 LLVMValueRef hs_ring_tess_offchip
;
87 LLVMValueRef hs_ring_tess_factor
;
89 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
90 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
93 LLVMValueRef streamout_buffers
;
94 LLVMValueRef streamout_write_idx
;
95 LLVMValueRef streamout_config
;
96 LLVMValueRef streamout_offset
[4];
98 gl_shader_stage stage
;
100 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
101 uint64_t float16_shaded_mask
;
104 uint64_t output_mask
;
106 bool is_gs_copy_shader
;
107 LLVMValueRef gs_next_vertex
[4];
108 LLVMValueRef gs_curprim_verts
[4];
109 LLVMValueRef gs_generated_prims
[4];
110 LLVMValueRef gs_ngg_emit
;
111 LLVMValueRef gs_ngg_scratch
;
112 unsigned gs_max_out_vertices
;
113 unsigned gs_output_prim
;
115 unsigned tes_primitive_mode
;
117 uint32_t tcs_patch_outputs_read
;
118 uint64_t tcs_outputs_read
;
119 uint32_t tcs_vertices_per_patch
;
120 uint32_t tcs_num_inputs
;
121 uint32_t tcs_num_patches
;
122 uint32_t max_gsvs_emit_size
;
123 uint32_t gsvs_vertex_size
;
125 LLVMValueRef vertexptr
; /* GFX10 only */
128 enum radeon_llvm_calling_convention
{
129 RADEON_LLVM_AMDGPU_VS
= 87,
130 RADEON_LLVM_AMDGPU_GS
= 88,
131 RADEON_LLVM_AMDGPU_PS
= 89,
132 RADEON_LLVM_AMDGPU_CS
= 90,
133 RADEON_LLVM_AMDGPU_HS
= 93,
136 static inline struct radv_shader_context
*
137 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
139 struct radv_shader_context
*ctx
= NULL
;
140 return container_of(abi
, ctx
, abi
);
143 struct ac_build_if_state
145 struct radv_shader_context
*ctx
;
146 LLVMValueRef condition
;
147 LLVMBasicBlockRef entry_block
;
148 LLVMBasicBlockRef true_block
;
149 LLVMBasicBlockRef false_block
;
150 LLVMBasicBlockRef merge_block
;
153 static LLVMBasicBlockRef
154 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
156 LLVMBasicBlockRef current_block
;
157 LLVMBasicBlockRef next_block
;
158 LLVMBasicBlockRef new_block
;
160 /* get current basic block */
161 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
163 /* chqeck if there's another block after this one */
164 next_block
= LLVMGetNextBasicBlock(current_block
);
166 /* insert the new block before the next block */
167 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
170 /* append new block after current block */
171 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
172 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
178 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
179 struct radv_shader_context
*ctx
,
180 LLVMValueRef condition
)
182 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
184 memset(ifthen
, 0, sizeof *ifthen
);
186 ifthen
->condition
= condition
;
187 ifthen
->entry_block
= block
;
189 /* create endif/merge basic block for the phi functions */
190 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
192 /* create/insert true_block before merge_block */
194 LLVMInsertBasicBlockInContext(ctx
->context
,
198 /* successive code goes into the true block */
199 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
206 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
208 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
210 /* Insert branch to the merge block from current block */
211 LLVMBuildBr(builder
, ifthen
->merge_block
);
214 * Now patch in the various branch instructions.
217 /* Insert the conditional branch instruction at the end of entry_block */
218 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
219 if (ifthen
->false_block
) {
220 /* we have an else clause */
221 LLVMBuildCondBr(builder
, ifthen
->condition
,
222 ifthen
->true_block
, ifthen
->false_block
);
226 LLVMBuildCondBr(builder
, ifthen
->condition
,
227 ifthen
->true_block
, ifthen
->merge_block
);
230 /* Resume building code at end of the ifthen->merge_block */
231 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
235 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
237 switch (ctx
->stage
) {
238 case MESA_SHADER_TESS_CTRL
:
239 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
240 case MESA_SHADER_TESS_EVAL
:
241 return ctx
->tes_rel_patch_id
;
244 unreachable("Illegal stage");
249 get_tcs_num_patches(struct radv_shader_context
*ctx
)
251 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
252 unsigned num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
253 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
254 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
255 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
256 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
257 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
258 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
259 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
260 unsigned num_patches
;
261 unsigned hardware_lds_size
;
263 /* Ensure that we only need one wave per SIMD so we don't need to check
264 * resource usage. Also ensures that the number of tcs in and out
265 * vertices per threadgroup are at most 256.
267 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
268 /* Make sure that the data fits in LDS. This assumes the shaders only
269 * use LDS for the inputs and outputs.
271 hardware_lds_size
= 32768;
273 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
274 * threadgroup, even though there is more than 32 KiB LDS.
276 * Test: dEQP-VK.tessellation.shader_input_output.barrier
278 if (ctx
->options
->chip_class
>= GFX7
&& ctx
->options
->family
!= CHIP_STONEY
)
279 hardware_lds_size
= 65536;
281 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
282 /* Make sure the output data fits in the offchip buffer */
283 num_patches
= MIN2(num_patches
, (ctx
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
284 /* Not necessary for correctness, but improves performance. The
285 * specific value is taken from the proprietary driver.
287 num_patches
= MIN2(num_patches
, 40);
289 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
290 if (ctx
->options
->chip_class
== GFX6
) {
291 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
292 num_patches
= MIN2(num_patches
, one_wave
);
298 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
300 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
301 unsigned num_tcs_output_cp
;
302 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
303 unsigned input_vertex_size
, output_vertex_size
;
304 unsigned input_patch_size
, output_patch_size
;
305 unsigned pervertex_output_patch_size
;
306 unsigned output_patch0_offset
;
307 unsigned num_patches
;
310 num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
311 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
312 num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
314 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
315 output_vertex_size
= num_tcs_outputs
* 16;
317 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
319 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
320 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
322 num_patches
= ctx
->tcs_num_patches
;
323 output_patch0_offset
= input_patch_size
* num_patches
;
325 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
329 /* Tessellation shaders pass outputs to the next shader using LDS.
331 * LS outputs = TCS inputs
332 * TCS outputs = TES inputs
335 * - TCS inputs for patch 0
336 * - TCS inputs for patch 1
337 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
339 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
340 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
341 * - TCS outputs for patch 1
342 * - Per-patch TCS outputs for patch 1
343 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
344 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
347 * All three shaders VS(LS), TCS, TES share the same LDS space.
350 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
352 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
353 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
354 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
356 input_patch_size
/= 4;
357 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
361 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
363 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
364 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
365 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
366 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
367 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
368 output_patch_size
/= 4;
369 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
373 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
375 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
376 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
377 output_vertex_size
/= 4;
378 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
382 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
384 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
385 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
386 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
387 uint32_t output_patch0_offset
= input_patch_size
;
388 unsigned num_patches
= ctx
->tcs_num_patches
;
390 output_patch0_offset
*= num_patches
;
391 output_patch0_offset
/= 4;
392 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
396 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
398 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
399 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
400 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
401 uint32_t output_patch0_offset
= input_patch_size
;
403 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
404 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
405 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
406 unsigned num_patches
= ctx
->tcs_num_patches
;
408 output_patch0_offset
*= num_patches
;
409 output_patch0_offset
+= pervertex_output_patch_size
;
410 output_patch0_offset
/= 4;
411 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
415 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
417 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
418 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
420 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
424 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
426 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
427 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
428 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
430 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
435 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
437 LLVMValueRef patch0_patch_data_offset
=
438 get_tcs_out_patch0_patch_data_offset(ctx
);
439 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
440 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
442 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
443 patch0_patch_data_offset
);
448 LLVMTypeRef types
[MAX_ARGS
];
449 LLVMValueRef
*assign
[MAX_ARGS
];
452 uint8_t num_sgprs_used
;
453 uint8_t num_vgprs_used
;
456 enum ac_arg_regfile
{
462 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
463 LLVMValueRef
*param_ptr
)
465 assert(info
->count
< MAX_ARGS
);
467 info
->assign
[info
->count
] = param_ptr
;
468 info
->types
[info
->count
] = type
;
471 if (regfile
== ARG_SGPR
) {
472 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
475 assert(regfile
== ARG_VGPR
);
476 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
480 static void assign_arguments(LLVMValueRef main_function
,
481 struct arg_info
*info
)
484 for (i
= 0; i
< info
->count
; i
++) {
486 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
491 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
492 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
493 unsigned num_return_elems
,
494 struct arg_info
*args
,
495 unsigned max_workgroup_size
,
496 const struct radv_nir_compiler_options
*options
)
498 LLVMTypeRef main_function_type
, ret_type
;
499 LLVMBasicBlockRef main_function_body
;
501 if (num_return_elems
)
502 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
503 num_return_elems
, true);
505 ret_type
= LLVMVoidTypeInContext(ctx
);
507 /* Setup the function */
509 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
510 LLVMValueRef main_function
=
511 LLVMAddFunction(module
, "main", main_function_type
);
513 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
514 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
516 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
517 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
518 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
520 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
522 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
523 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
524 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
528 if (options
->address32_hi
) {
529 ac_llvm_add_target_dep_function_attr(main_function
,
530 "amdgpu-32bit-address-high-bits",
531 options
->address32_hi
);
534 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
536 if (options
->unsafe_math
) {
537 /* These were copied from some LLVM test. */
538 LLVMAddTargetDependentFunctionAttr(main_function
,
539 "less-precise-fpmad",
541 LLVMAddTargetDependentFunctionAttr(main_function
,
544 LLVMAddTargetDependentFunctionAttr(main_function
,
547 LLVMAddTargetDependentFunctionAttr(main_function
,
550 LLVMAddTargetDependentFunctionAttr(main_function
,
551 "no-signed-zeros-fp-math",
554 return main_function
;
559 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
,
562 ud_info
->sgpr_idx
= *sgpr_idx
;
563 ud_info
->num_sgprs
= num_sgprs
;
564 *sgpr_idx
+= num_sgprs
;
568 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
571 struct radv_userdata_info
*ud_info
=
572 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
575 set_loc(ud_info
, sgpr_idx
, num_sgprs
);
579 set_loc_shader_ptr(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
581 bool use_32bit_pointers
= idx
!= AC_UD_SCRATCH_RING_OFFSETS
;
583 set_loc_shader(ctx
, idx
, sgpr_idx
, use_32bit_pointers
? 1 : 2);
587 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
589 struct radv_userdata_locations
*locs
=
590 &ctx
->shader_info
->user_sgprs_locs
;
591 struct radv_userdata_info
*ud_info
= &locs
->descriptor_sets
[idx
];
594 set_loc(ud_info
, sgpr_idx
, 1);
596 locs
->descriptor_sets_enabled
|= 1 << idx
;
599 struct user_sgpr_info
{
600 bool need_ring_offsets
;
601 bool indirect_all_descriptor_sets
;
602 uint8_t remaining_sgprs
;
605 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
606 gl_shader_stage stage
)
609 case MESA_SHADER_VERTEX
:
610 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
611 (!ctx
->options
->key
.vs_common_out
.as_es
&& !ctx
->options
->key
.vs_common_out
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
614 case MESA_SHADER_TESS_EVAL
:
615 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.vs_common_out
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
618 case MESA_SHADER_GEOMETRY
:
619 case MESA_SHADER_TESS_CTRL
:
620 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
630 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
634 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
636 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
641 static void allocate_inline_push_consts(struct radv_shader_context
*ctx
,
642 struct user_sgpr_info
*user_sgpr_info
)
644 uint8_t remaining_sgprs
= user_sgpr_info
->remaining_sgprs
;
646 /* Only supported if shaders use push constants. */
647 if (ctx
->shader_info
->info
.min_push_constant_used
== UINT8_MAX
)
650 /* Only supported if shaders don't have indirect push constants. */
651 if (ctx
->shader_info
->info
.has_indirect_push_constants
)
654 /* Only supported for 32-bit push constants. */
655 if (!ctx
->shader_info
->info
.has_only_32bit_push_constants
)
658 uint8_t num_push_consts
=
659 (ctx
->shader_info
->info
.max_push_constant_used
-
660 ctx
->shader_info
->info
.min_push_constant_used
) / 4;
662 /* Check if the number of user SGPRs is large enough. */
663 if (num_push_consts
< remaining_sgprs
) {
664 ctx
->shader_info
->info
.num_inline_push_consts
= num_push_consts
;
666 ctx
->shader_info
->info
.num_inline_push_consts
= remaining_sgprs
;
669 /* Clamp to the maximum number of allowed inlined push constants. */
670 if (ctx
->shader_info
->info
.num_inline_push_consts
> AC_MAX_INLINE_PUSH_CONSTS
)
671 ctx
->shader_info
->info
.num_inline_push_consts
= AC_MAX_INLINE_PUSH_CONSTS
;
673 if (ctx
->shader_info
->info
.num_inline_push_consts
== num_push_consts
&&
674 !ctx
->shader_info
->info
.loads_dynamic_offsets
) {
675 /* Disable the default push constants path if all constants are
676 * inlined and if shaders don't use dynamic descriptors.
678 ctx
->shader_info
->info
.loads_push_constants
= false;
681 ctx
->shader_info
->info
.base_inline_push_consts
=
682 ctx
->shader_info
->info
.min_push_constant_used
/ 4;
685 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
686 gl_shader_stage stage
,
687 bool has_previous_stage
,
688 gl_shader_stage previous_stage
,
689 bool needs_view_index
,
690 struct user_sgpr_info
*user_sgpr_info
)
692 uint8_t user_sgpr_count
= 0;
694 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
696 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
697 if (stage
== MESA_SHADER_GEOMETRY
||
698 stage
== MESA_SHADER_VERTEX
||
699 stage
== MESA_SHADER_TESS_CTRL
||
700 stage
== MESA_SHADER_TESS_EVAL
||
701 ctx
->is_gs_copy_shader
)
702 user_sgpr_info
->need_ring_offsets
= true;
704 if (stage
== MESA_SHADER_FRAGMENT
&&
705 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
706 user_sgpr_info
->need_ring_offsets
= true;
708 /* 2 user sgprs will nearly always be allocated for scratch/rings */
709 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
710 user_sgpr_count
+= 2;
714 case MESA_SHADER_COMPUTE
:
715 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
716 user_sgpr_count
+= 3;
718 case MESA_SHADER_FRAGMENT
:
719 user_sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
721 case MESA_SHADER_VERTEX
:
722 if (!ctx
->is_gs_copy_shader
)
723 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
725 case MESA_SHADER_TESS_CTRL
:
726 if (has_previous_stage
) {
727 if (previous_stage
== MESA_SHADER_VERTEX
)
728 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
731 case MESA_SHADER_TESS_EVAL
:
733 case MESA_SHADER_GEOMETRY
:
734 if (has_previous_stage
) {
735 if (previous_stage
== MESA_SHADER_VERTEX
) {
736 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
744 if (needs_view_index
)
747 if (ctx
->shader_info
->info
.loads_push_constants
)
750 if (ctx
->streamout_buffers
)
753 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
&& stage
!= MESA_SHADER_COMPUTE
? 32 : 16;
754 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_count
;
755 uint32_t num_desc_set
=
756 util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
);
758 if (remaining_sgprs
< num_desc_set
) {
759 user_sgpr_info
->indirect_all_descriptor_sets
= true;
760 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- 1;
762 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- num_desc_set
;
765 allocate_inline_push_consts(ctx
, user_sgpr_info
);
769 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
770 const struct user_sgpr_info
*user_sgpr_info
,
771 struct arg_info
*args
,
772 LLVMValueRef
*desc_sets
)
774 LLVMTypeRef type
= ac_array_in_const32_addr_space(ctx
->ac
.i8
);
776 /* 1 for each descriptor set */
777 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
778 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
781 int i
= u_bit_scan(&mask
);
783 add_arg(args
, ARG_SGPR
, type
, &ctx
->descriptor_sets
[i
]);
786 add_arg(args
, ARG_SGPR
, ac_array_in_const32_addr_space(type
),
790 if (ctx
->shader_info
->info
.loads_push_constants
) {
791 /* 1 for push constants and dynamic descriptors */
792 add_arg(args
, ARG_SGPR
, type
, &ctx
->abi
.push_constants
);
795 for (unsigned i
= 0; i
< ctx
->shader_info
->info
.num_inline_push_consts
; i
++) {
796 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
,
797 &ctx
->abi
.inline_push_consts
[i
]);
799 ctx
->abi
.num_inline_push_consts
= ctx
->shader_info
->info
.num_inline_push_consts
;
800 ctx
->abi
.base_inline_push_consts
= ctx
->shader_info
->info
.base_inline_push_consts
;
802 if (ctx
->shader_info
->info
.so
.num_outputs
) {
803 add_arg(args
, ARG_SGPR
,
804 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
805 &ctx
->streamout_buffers
);
810 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
811 gl_shader_stage stage
,
812 bool has_previous_stage
,
813 gl_shader_stage previous_stage
,
814 struct arg_info
*args
)
816 if (!ctx
->is_gs_copy_shader
&&
817 (stage
== MESA_SHADER_VERTEX
||
818 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
819 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
820 add_arg(args
, ARG_SGPR
,
821 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
822 &ctx
->vertex_buffers
);
824 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
825 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
826 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
827 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
833 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
835 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
836 if (!ctx
->is_gs_copy_shader
) {
837 if (ctx
->options
->key
.vs_common_out
.as_ls
) {
838 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
839 if (ctx
->ac
.chip_class
>= GFX10
) {
840 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
841 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
843 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
844 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
847 if (ctx
->ac
.chip_class
>= GFX10
) {
848 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
849 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
850 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
852 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
853 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
854 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
861 declare_streamout_sgprs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
862 struct arg_info
*args
)
866 if (ctx
->ac
.chip_class
>= GFX10
)
869 /* Streamout SGPRs. */
870 if (ctx
->shader_info
->info
.so
.num_outputs
) {
871 assert(stage
== MESA_SHADER_VERTEX
||
872 stage
== MESA_SHADER_TESS_EVAL
);
874 if (stage
!= MESA_SHADER_TESS_EVAL
) {
875 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_config
);
877 args
->assign
[args
->count
- 1] = &ctx
->streamout_config
;
878 args
->types
[args
->count
- 1] = ctx
->ac
.i32
;
881 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_write_idx
);
884 /* A streamout buffer offset is loaded if the stride is non-zero. */
885 for (i
= 0; i
< 4; i
++) {
886 if (!ctx
->shader_info
->info
.so
.strides
[i
])
889 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_offset
[i
]);
894 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
896 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
897 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
898 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
899 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
903 set_global_input_locs(struct radv_shader_context
*ctx
,
904 const struct user_sgpr_info
*user_sgpr_info
,
905 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
907 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
909 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
911 int i
= u_bit_scan(&mask
);
913 set_loc_desc(ctx
, i
, user_sgpr_idx
);
916 set_loc_shader_ptr(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
920 int i
= u_bit_scan(&mask
);
922 ctx
->descriptor_sets
[i
] =
923 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
924 LLVMConstInt(ctx
->ac
.i32
, i
, false));
928 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
931 if (ctx
->shader_info
->info
.loads_push_constants
) {
932 set_loc_shader_ptr(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
);
935 if (ctx
->shader_info
->info
.num_inline_push_consts
) {
936 set_loc_shader(ctx
, AC_UD_INLINE_PUSH_CONSTANTS
, user_sgpr_idx
,
937 ctx
->shader_info
->info
.num_inline_push_consts
);
940 if (ctx
->streamout_buffers
) {
941 set_loc_shader_ptr(ctx
, AC_UD_STREAMOUT_BUFFERS
,
947 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
948 gl_shader_stage stage
, bool has_previous_stage
,
949 gl_shader_stage previous_stage
,
950 uint8_t *user_sgpr_idx
)
952 if (!ctx
->is_gs_copy_shader
&&
953 (stage
== MESA_SHADER_VERTEX
||
954 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
955 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
956 set_loc_shader_ptr(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
961 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
964 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
965 user_sgpr_idx
, vs_num
);
969 static void set_llvm_calling_convention(LLVMValueRef func
,
970 gl_shader_stage stage
)
972 enum radeon_llvm_calling_convention calling_conv
;
975 case MESA_SHADER_VERTEX
:
976 case MESA_SHADER_TESS_EVAL
:
977 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
979 case MESA_SHADER_GEOMETRY
:
980 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
982 case MESA_SHADER_TESS_CTRL
:
983 calling_conv
= RADEON_LLVM_AMDGPU_HS
;
985 case MESA_SHADER_FRAGMENT
:
986 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
988 case MESA_SHADER_COMPUTE
:
989 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
992 unreachable("Unhandle shader type");
995 LLVMSetFunctionCallConv(func
, calling_conv
);
998 /* Returns whether the stage is a stage that can be directly before the GS */
999 static bool is_pre_gs_stage(gl_shader_stage stage
)
1001 return stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
;
1004 static void create_function(struct radv_shader_context
*ctx
,
1005 gl_shader_stage stage
,
1006 bool has_previous_stage
,
1007 gl_shader_stage previous_stage
)
1009 uint8_t user_sgpr_idx
;
1010 struct user_sgpr_info user_sgpr_info
;
1011 struct arg_info args
= {};
1012 LLVMValueRef desc_sets
;
1013 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
1015 if (ctx
->ac
.chip_class
>= GFX10
) {
1016 if (is_pre_gs_stage(stage
) && ctx
->options
->key
.vs_common_out
.as_ngg
) {
1017 /* On GFX10, VS is merged into GS for NGG. */
1018 previous_stage
= stage
;
1019 stage
= MESA_SHADER_GEOMETRY
;
1020 has_previous_stage
= true;
1024 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
1025 previous_stage
, needs_view_index
, &user_sgpr_info
);
1027 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
1028 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
1029 &ctx
->ring_offsets
);
1033 case MESA_SHADER_COMPUTE
:
1034 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1037 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1038 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
1039 &ctx
->abi
.num_work_groups
);
1042 for (int i
= 0; i
< 3; i
++) {
1043 ctx
->abi
.workgroup_ids
[i
] = NULL
;
1044 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
1045 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1046 &ctx
->abi
.workgroup_ids
[i
]);
1050 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
1051 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
1052 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
1053 &ctx
->abi
.local_invocation_ids
);
1055 case MESA_SHADER_VERTEX
:
1056 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1059 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
1060 previous_stage
, &args
);
1062 if (needs_view_index
)
1063 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1064 &ctx
->abi
.view_index
);
1065 if (ctx
->options
->key
.vs_common_out
.as_es
) {
1066 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1067 &ctx
->es2gs_offset
);
1068 } else if (ctx
->options
->key
.vs_common_out
.as_ls
) {
1069 /* no extra parameters */
1071 declare_streamout_sgprs(ctx
, stage
, &args
);
1074 declare_vs_input_vgprs(ctx
, &args
);
1076 case MESA_SHADER_TESS_CTRL
:
1077 if (has_previous_stage
) {
1078 // First 6 system regs
1079 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1080 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1081 &ctx
->merged_wave_info
);
1082 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1083 &ctx
->tess_factor_offset
);
1085 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1086 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1087 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1089 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1092 declare_vs_specific_input_sgprs(ctx
, stage
,
1094 previous_stage
, &args
);
1096 if (needs_view_index
)
1097 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1098 &ctx
->abi
.view_index
);
1100 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1101 &ctx
->abi
.tcs_patch_id
);
1102 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1103 &ctx
->abi
.tcs_rel_ids
);
1105 declare_vs_input_vgprs(ctx
, &args
);
1107 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1110 if (needs_view_index
)
1111 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1112 &ctx
->abi
.view_index
);
1114 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1115 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1116 &ctx
->tess_factor_offset
);
1117 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1118 &ctx
->abi
.tcs_patch_id
);
1119 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1120 &ctx
->abi
.tcs_rel_ids
);
1123 case MESA_SHADER_TESS_EVAL
:
1124 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1127 if (needs_view_index
)
1128 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1129 &ctx
->abi
.view_index
);
1131 if (ctx
->options
->key
.vs_common_out
.as_es
) {
1132 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1133 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1134 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1135 &ctx
->es2gs_offset
);
1137 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1138 declare_streamout_sgprs(ctx
, stage
, &args
);
1139 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1141 declare_tes_input_vgprs(ctx
, &args
);
1143 case MESA_SHADER_GEOMETRY
:
1144 if (has_previous_stage
) {
1145 // First 6 system regs
1146 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1147 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1150 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1151 &ctx
->gs2vs_offset
);
1154 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1155 &ctx
->merged_wave_info
);
1156 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1158 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1159 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1160 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1162 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1165 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
1166 declare_vs_specific_input_sgprs(ctx
, stage
,
1172 if (needs_view_index
)
1173 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1174 &ctx
->abi
.view_index
);
1176 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1177 &ctx
->gs_vtx_offset
[0]);
1178 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1179 &ctx
->gs_vtx_offset
[2]);
1180 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1181 &ctx
->abi
.gs_prim_id
);
1182 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1183 &ctx
->abi
.gs_invocation_id
);
1184 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1185 &ctx
->gs_vtx_offset
[4]);
1187 if (previous_stage
== MESA_SHADER_VERTEX
) {
1188 declare_vs_input_vgprs(ctx
, &args
);
1190 declare_tes_input_vgprs(ctx
, &args
);
1193 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1196 if (needs_view_index
)
1197 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1198 &ctx
->abi
.view_index
);
1200 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1201 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1202 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1203 &ctx
->gs_vtx_offset
[0]);
1204 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1205 &ctx
->gs_vtx_offset
[1]);
1206 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1207 &ctx
->abi
.gs_prim_id
);
1208 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1209 &ctx
->gs_vtx_offset
[2]);
1210 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1211 &ctx
->gs_vtx_offset
[3]);
1212 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1213 &ctx
->gs_vtx_offset
[4]);
1214 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1215 &ctx
->gs_vtx_offset
[5]);
1216 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1217 &ctx
->abi
.gs_invocation_id
);
1220 case MESA_SHADER_FRAGMENT
:
1221 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1224 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1225 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1226 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1227 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1228 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1229 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1230 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1231 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1232 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1233 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1234 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1235 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1236 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1237 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1238 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1239 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1240 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1243 unreachable("Shader stage not implemented");
1246 ctx
->main_function
= create_llvm_function(
1247 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1248 ctx
->max_workgroup_size
, ctx
->options
);
1249 set_llvm_calling_convention(ctx
->main_function
, stage
);
1252 ctx
->shader_info
->num_input_vgprs
= 0;
1253 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1255 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1257 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1258 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1260 assign_arguments(ctx
->main_function
, &args
);
1264 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1265 set_loc_shader_ptr(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1267 if (ctx
->options
->supports_spill
) {
1268 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1269 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
1270 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1271 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1272 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1276 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1277 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1278 if (has_previous_stage
)
1281 set_global_input_locs(ctx
, &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1284 case MESA_SHADER_COMPUTE
:
1285 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1286 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1290 case MESA_SHADER_VERTEX
:
1291 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1292 previous_stage
, &user_sgpr_idx
);
1293 if (ctx
->abi
.view_index
)
1294 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1296 case MESA_SHADER_TESS_CTRL
:
1297 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1298 previous_stage
, &user_sgpr_idx
);
1299 if (ctx
->abi
.view_index
)
1300 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1302 case MESA_SHADER_TESS_EVAL
:
1303 if (ctx
->abi
.view_index
)
1304 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1306 case MESA_SHADER_GEOMETRY
:
1307 if (has_previous_stage
) {
1308 if (previous_stage
== MESA_SHADER_VERTEX
)
1309 set_vs_specific_input_locs(ctx
, stage
,
1314 if (ctx
->abi
.view_index
)
1315 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1317 case MESA_SHADER_FRAGMENT
:
1320 unreachable("Shader stage not implemented");
1323 if (stage
== MESA_SHADER_TESS_CTRL
||
1324 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs_common_out
.as_ls
) ||
1325 /* GFX9 has the ESGS ring buffer in LDS. */
1326 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1327 ac_declare_lds_as_pointer(&ctx
->ac
);
1330 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1335 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1336 unsigned desc_set
, unsigned binding
)
1338 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1339 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1340 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
1341 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1342 unsigned base_offset
= layout
->binding
[binding
].offset
;
1343 LLVMValueRef offset
, stride
;
1345 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1346 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1347 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1348 layout
->binding
[binding
].dynamic_offset_offset
;
1349 desc_ptr
= ctx
->abi
.push_constants
;
1350 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1351 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1353 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1355 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
1357 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1358 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
1361 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
1362 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1363 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1365 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1366 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1367 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1368 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1369 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1370 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1371 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1373 LLVMValueRef desc_components
[4] = {
1374 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
1375 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
), false),
1376 /* High limit to support variable sizes. */
1377 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
1378 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
1381 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
1388 /* The offchip buffer layout for TCS->TES is
1390 * - attribute 0 of patch 0 vertex 0
1391 * - attribute 0 of patch 0 vertex 1
1392 * - attribute 0 of patch 0 vertex 2
1394 * - attribute 0 of patch 1 vertex 0
1395 * - attribute 0 of patch 1 vertex 1
1397 * - attribute 1 of patch 0 vertex 0
1398 * - attribute 1 of patch 0 vertex 1
1400 * - per patch attribute 0 of patch 0
1401 * - per patch attribute 0 of patch 1
1404 * Note that every attribute has 4 components.
1406 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1408 uint32_t num_patches
= ctx
->tcs_num_patches
;
1409 uint32_t num_tcs_outputs
;
1410 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1411 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
1413 num_tcs_outputs
= ctx
->options
->key
.tes
.tcs_num_outputs
;
1415 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1416 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
1418 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1421 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1422 LLVMValueRef vertex_index
)
1424 LLVMValueRef param_stride
;
1426 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
* ctx
->tcs_num_patches
, false);
1428 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1429 return param_stride
;
1432 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1433 LLVMValueRef vertex_index
,
1434 LLVMValueRef param_index
)
1436 LLVMValueRef base_addr
;
1437 LLVMValueRef param_stride
, constant16
;
1438 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1439 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
1440 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1441 param_stride
= calc_param_stride(ctx
, vertex_index
);
1443 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
1444 vertices_per_patch
, vertex_index
);
1446 base_addr
= rel_patch_id
;
1449 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1450 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1451 param_stride
, ""), "");
1453 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1455 if (!vertex_index
) {
1456 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1458 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1459 patch_data_offset
, "");
1464 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1466 unsigned const_index
,
1468 LLVMValueRef vertex_index
,
1469 LLVMValueRef indir_index
)
1471 LLVMValueRef param_index
;
1474 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1477 if (const_index
&& !is_compact
)
1478 param
+= const_index
;
1479 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1481 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1485 get_dw_address(struct radv_shader_context
*ctx
,
1486 LLVMValueRef dw_addr
,
1488 unsigned const_index
,
1489 bool compact_const_index
,
1490 LLVMValueRef vertex_index
,
1491 LLVMValueRef stride
,
1492 LLVMValueRef indir_index
)
1497 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1498 LLVMBuildMul(ctx
->ac
.builder
,
1504 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1505 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1506 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1507 else if (const_index
&& !compact_const_index
)
1508 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1509 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1511 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1512 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1514 if (const_index
&& compact_const_index
)
1515 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1516 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1521 load_tcs_varyings(struct ac_shader_abi
*abi
,
1523 LLVMValueRef vertex_index
,
1524 LLVMValueRef indir_index
,
1525 unsigned const_index
,
1527 unsigned driver_location
,
1529 unsigned num_components
,
1534 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1535 LLVMValueRef dw_addr
, stride
;
1536 LLVMValueRef value
[4], result
;
1537 unsigned param
= shader_io_get_unique_index(location
);
1540 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1541 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1542 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1545 stride
= get_tcs_out_vertex_stride(ctx
);
1546 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1548 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1553 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1556 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1557 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1558 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1561 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1566 store_tcs_output(struct ac_shader_abi
*abi
,
1567 const nir_variable
*var
,
1568 LLVMValueRef vertex_index
,
1569 LLVMValueRef param_index
,
1570 unsigned const_index
,
1574 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1575 const unsigned location
= var
->data
.location
;
1576 unsigned component
= var
->data
.location_frac
;
1577 const bool is_patch
= var
->data
.patch
;
1578 const bool is_compact
= var
->data
.compact
;
1579 LLVMValueRef dw_addr
;
1580 LLVMValueRef stride
= NULL
;
1581 LLVMValueRef buf_addr
= NULL
;
1583 bool store_lds
= true;
1586 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1589 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
1593 param
= shader_io_get_unique_index(location
);
1594 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1595 const_index
+= component
;
1598 if (const_index
>= 4) {
1605 stride
= get_tcs_out_vertex_stride(ctx
);
1606 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1608 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1611 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1613 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1614 vertex_index
, param_index
);
1616 bool is_tess_factor
= false;
1617 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1618 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1619 is_tess_factor
= true;
1621 unsigned base
= is_compact
? const_index
: 0;
1622 for (unsigned chan
= 0; chan
< 8; chan
++) {
1623 if (!(writemask
& (1 << chan
)))
1625 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1626 value
= ac_to_integer(&ctx
->ac
, value
);
1627 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
1629 if (store_lds
|| is_tess_factor
) {
1630 LLVMValueRef dw_addr_chan
=
1631 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1632 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1633 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1636 if (!is_tess_factor
&& writemask
!= 0xF)
1637 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1638 buf_addr
, ctx
->oc_lds
,
1639 4 * (base
+ chan
), ac_glc
, false);
1642 if (writemask
== 0xF) {
1643 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1644 buf_addr
, ctx
->oc_lds
,
1645 (base
* 4), ac_glc
, false);
1650 load_tes_input(struct ac_shader_abi
*abi
,
1652 LLVMValueRef vertex_index
,
1653 LLVMValueRef param_index
,
1654 unsigned const_index
,
1656 unsigned driver_location
,
1658 unsigned num_components
,
1663 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1664 LLVMValueRef buf_addr
;
1665 LLVMValueRef result
;
1666 unsigned param
= shader_io_get_unique_index(location
);
1668 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1669 const_index
+= component
;
1671 if (const_index
>= 4) {
1677 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1678 is_compact
, vertex_index
, param_index
);
1680 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1681 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1683 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1684 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
1685 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1690 load_gs_input(struct ac_shader_abi
*abi
,
1692 unsigned driver_location
,
1694 unsigned num_components
,
1695 unsigned vertex_index
,
1696 unsigned const_index
,
1699 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1700 LLVMValueRef vtx_offset
;
1701 unsigned param
, vtx_offset_param
;
1702 LLVMValueRef value
[4], result
;
1704 vtx_offset_param
= vertex_index
;
1705 assert(vtx_offset_param
< 6);
1706 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1707 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1709 param
= shader_io_get_unique_index(location
);
1711 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1712 if (ctx
->ac
.chip_class
>= GFX9
) {
1713 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1714 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1715 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1716 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1718 LLVMValueRef soffset
=
1719 LLVMConstInt(ctx
->ac
.i32
,
1720 (param
* 4 + i
+ const_index
) * 256,
1723 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1726 vtx_offset
, soffset
,
1727 0, ac_glc
, true, false);
1730 if (ac_get_type_size(type
) == 2) {
1731 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
1732 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
1734 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
1736 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1737 result
= ac_to_integer(&ctx
->ac
, result
);
1742 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1744 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1745 ac_build_kill_if_false(&ctx
->ac
, visible
);
1748 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
1749 enum glsl_interp_mode interp
, unsigned location
)
1751 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1754 case INTERP_MODE_FLAT
:
1757 case INTERP_MODE_SMOOTH
:
1758 case INTERP_MODE_NONE
:
1759 if (location
== INTERP_CENTER
)
1760 return ctx
->persp_center
;
1761 else if (location
== INTERP_CENTROID
)
1762 return ctx
->persp_centroid
;
1763 else if (location
== INTERP_SAMPLE
)
1764 return ctx
->persp_sample
;
1766 case INTERP_MODE_NOPERSPECTIVE
:
1767 if (location
== INTERP_CENTER
)
1768 return ctx
->linear_center
;
1769 else if (location
== INTERP_CENTROID
)
1770 return ctx
->linear_centroid
;
1771 else if (location
== INTERP_SAMPLE
)
1772 return ctx
->linear_sample
;
1779 radv_get_sample_pos_offset(uint32_t num_samples
)
1781 uint32_t sample_pos_offset
= 0;
1783 switch (num_samples
) {
1785 sample_pos_offset
= 1;
1788 sample_pos_offset
= 3;
1791 sample_pos_offset
= 7;
1796 return sample_pos_offset
;
1799 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1800 LLVMValueRef sample_id
)
1802 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1804 LLVMValueRef result
;
1805 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
1806 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
1808 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1809 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1811 uint32_t sample_pos_offset
=
1812 radv_get_sample_pos_offset(ctx
->options
->key
.fs
.num_samples
);
1815 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
1816 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
1817 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1823 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1825 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1826 uint8_t log2_ps_iter_samples
;
1828 if (ctx
->shader_info
->info
.ps
.force_persample
) {
1829 log2_ps_iter_samples
=
1830 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
1832 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
1835 /* The bit pattern matches that used by fixed function fragment
1837 static const uint16_t ps_iter_masks
[] = {
1838 0xffff, /* not used */
1844 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1846 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1848 LLVMValueRef result
, sample_id
;
1849 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
1850 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1851 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
1856 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
1858 LLVMValueRef
*addrs
);
1861 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1863 LLVMValueRef gs_next_vertex
;
1864 LLVMValueRef can_emit
;
1865 unsigned offset
= 0;
1866 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1868 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1869 gfx10_ngg_gs_emit_vertex(ctx
, stream
, addrs
);
1873 /* Write vertex attribute values to GSVS ring */
1874 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1875 ctx
->gs_next_vertex
[stream
],
1878 /* If this thread has already emitted the declared maximum number of
1879 * vertices, kill it: excessive vertex emissions are not supposed to
1880 * have any effect, and GS threads have no externally observable
1881 * effects other than emitting vertices.
1883 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1884 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
1885 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1887 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1888 unsigned output_usage_mask
=
1889 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
1890 uint8_t output_stream
=
1891 ctx
->shader_info
->info
.gs
.output_streams
[i
];
1892 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1893 int length
= util_last_bit(output_usage_mask
);
1895 if (!(ctx
->output_mask
& (1ull << i
)) ||
1896 output_stream
!= stream
)
1899 for (unsigned j
= 0; j
< length
; j
++) {
1900 if (!(output_usage_mask
& (1 << j
)))
1903 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1905 LLVMValueRef voffset
=
1906 LLVMConstInt(ctx
->ac
.i32
, offset
*
1907 ctx
->gs_max_out_vertices
, false);
1911 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1912 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1914 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1915 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1917 ac_build_buffer_store_dword(&ctx
->ac
,
1918 ctx
->gsvs_ring
[stream
],
1920 voffset
, ctx
->gs2vs_offset
, 0,
1921 ac_glc
| ac_slc
, true);
1925 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1927 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1929 ac_build_sendmsg(&ctx
->ac
,
1930 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1935 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1937 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1939 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1940 LLVMBuildStore(ctx
->ac
.builder
, ctx
->ac
.i32_0
, ctx
->gs_curprim_verts
[stream
]);
1944 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1948 load_tess_coord(struct ac_shader_abi
*abi
)
1950 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1952 LLVMValueRef coord
[4] = {
1959 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
1960 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1961 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1963 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1967 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1969 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1970 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
1974 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1976 return abi
->base_vertex
;
1979 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1980 LLVMValueRef buffer_ptr
, bool write
)
1982 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1983 LLVMValueRef result
;
1985 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1987 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1988 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1993 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1995 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1996 LLVMValueRef result
;
1998 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
1999 /* Do not load the descriptor for inlined uniform blocks. */
2003 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2005 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
2006 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
2011 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
2012 unsigned descriptor_set
,
2013 unsigned base_index
,
2014 unsigned constant_index
,
2016 enum ac_descriptor_type desc_type
,
2017 bool image
, bool write
,
2020 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2021 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
2022 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
2023 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
2024 unsigned offset
= binding
->offset
;
2025 unsigned stride
= binding
->size
;
2027 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2030 assert(base_index
< layout
->binding_count
);
2032 switch (desc_type
) {
2034 type
= ctx
->ac
.v8i32
;
2038 type
= ctx
->ac
.v8i32
;
2042 case AC_DESC_SAMPLER
:
2043 type
= ctx
->ac
.v4i32
;
2044 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
2045 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
2050 case AC_DESC_BUFFER
:
2051 type
= ctx
->ac
.v4i32
;
2054 case AC_DESC_PLANE_0
:
2055 case AC_DESC_PLANE_1
:
2056 case AC_DESC_PLANE_2
:
2057 type
= ctx
->ac
.v8i32
;
2059 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
2062 unreachable("invalid desc_type\n");
2065 offset
+= constant_index
* stride
;
2067 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
2068 (!index
|| binding
->immutable_samplers_equal
)) {
2069 if (binding
->immutable_samplers_equal
)
2072 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
2074 LLVMValueRef constants
[] = {
2075 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
2076 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
2077 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
2078 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
2080 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
2083 assert(stride
% type_size
== 0);
2085 LLVMValueRef adjusted_index
= index
;
2086 if (!adjusted_index
)
2087 adjusted_index
= ctx
->ac
.i32_0
;
2089 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
2091 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
2092 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
2093 list
= LLVMBuildPointerCast(builder
, list
,
2094 ac_array_in_const32_addr_space(type
), "");
2096 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
2098 /* 3 plane formats always have same size and format for plane 1 & 2, so
2099 * use the tail from plane 1 so that we can store only the first 16 bytes
2100 * of the last plane. */
2101 if (desc_type
== AC_DESC_PLANE_2
) {
2102 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
2104 LLVMValueRef components
[8];
2105 for (unsigned i
= 0; i
< 4; ++i
)
2106 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
2108 for (unsigned i
= 4; i
< 8; ++i
)
2109 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
2110 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
2116 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
2117 * so we may need to fix it up. */
2119 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
2120 unsigned adjustment
,
2123 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
2126 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
2128 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2130 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
2131 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2133 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
2135 /* For the integer-like cases, do a natural sign extension.
2137 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2138 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2141 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
2142 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
2143 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
2144 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
2146 /* Convert back to the right type. */
2147 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
2149 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
2150 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2151 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
2152 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
2153 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
2154 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2157 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2161 get_num_channels_from_data_format(unsigned data_format
)
2163 switch (data_format
) {
2164 case V_008F0C_BUF_DATA_FORMAT_8
:
2165 case V_008F0C_BUF_DATA_FORMAT_16
:
2166 case V_008F0C_BUF_DATA_FORMAT_32
:
2168 case V_008F0C_BUF_DATA_FORMAT_8_8
:
2169 case V_008F0C_BUF_DATA_FORMAT_16_16
:
2170 case V_008F0C_BUF_DATA_FORMAT_32_32
:
2172 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
2173 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
2174 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
2176 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
2177 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
2178 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
2179 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
2180 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
2190 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
2192 unsigned num_channels
,
2195 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
2196 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
2197 LLVMValueRef chan
[4];
2199 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
2200 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
2202 if (num_channels
== 4 && num_channels
== vec_size
)
2205 num_channels
= MIN2(num_channels
, vec_size
);
2207 for (unsigned i
= 0; i
< num_channels
; i
++)
2208 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
2211 assert(num_channels
== 1);
2216 for (unsigned i
= num_channels
; i
< 4; i
++) {
2217 chan
[i
] = i
== 3 ? one
: zero
;
2218 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
2221 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
2225 handle_vs_input_decl(struct radv_shader_context
*ctx
,
2226 struct nir_variable
*variable
)
2228 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
2229 LLVMValueRef t_offset
;
2230 LLVMValueRef t_list
;
2232 LLVMValueRef buffer_index
;
2233 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
2234 uint8_t input_usage_mask
=
2235 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
2236 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
2238 variable
->data
.driver_location
= variable
->data
.location
* 4;
2240 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
2241 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
2242 LLVMValueRef output
[4];
2243 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
2244 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
2245 unsigned data_format
= attrib_format
& 0x0f;
2246 unsigned num_format
= (attrib_format
>> 4) & 0x07;
2247 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
2248 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
2250 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
2251 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
2254 buffer_index
= ctx
->abi
.instance_id
;
2257 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
2258 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
2261 buffer_index
= ctx
->ac
.i32_0
;
2264 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.start_instance
, buffer_index
, "");
2266 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
2267 ctx
->abi
.base_vertex
, "");
2269 /* Adjust the number of channels to load based on the vertex
2272 unsigned num_format_channels
= get_num_channels_from_data_format(data_format
);
2273 unsigned num_channels
= MIN2(num_input_channels
, num_format_channels
);
2274 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
2275 unsigned attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
2276 unsigned attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
2278 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2279 /* Always load, at least, 3 channels for formats that
2280 * need to be shuffled because X<->Z.
2282 num_channels
= MAX2(num_channels
, 3);
2285 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
2286 LLVMValueRef buffer_offset
=
2287 LLVMConstInt(ctx
->ac
.i32
,
2288 attrib_offset
/ attrib_stride
, false);
2290 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
2294 attrib_offset
= attrib_offset
% attrib_stride
;
2297 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
2298 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
2300 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
2302 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
2303 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
2305 data_format
, num_format
, 0, true);
2307 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2309 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
2310 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
2311 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
2312 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
2314 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
2317 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
2320 for (unsigned chan
= 0; chan
< 4; chan
++) {
2321 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2322 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
2323 if (type
== GLSL_TYPE_FLOAT16
) {
2324 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
2325 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
2329 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
2330 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
2332 for (unsigned chan
= 0; chan
< 4; chan
++) {
2333 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
2334 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
2335 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
2337 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
2343 handle_vs_inputs(struct radv_shader_context
*ctx
,
2344 struct nir_shader
*nir
) {
2345 nir_foreach_variable(variable
, &nir
->inputs
)
2346 handle_vs_input_decl(ctx
, variable
);
2350 prepare_interp_optimize(struct radv_shader_context
*ctx
,
2351 struct nir_shader
*nir
)
2353 bool uses_center
= false;
2354 bool uses_centroid
= false;
2355 nir_foreach_variable(variable
, &nir
->inputs
) {
2356 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
2357 variable
->data
.sample
)
2360 if (variable
->data
.centroid
)
2361 uses_centroid
= true;
2366 if (uses_center
&& uses_centroid
) {
2367 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
2368 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
2369 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
2374 scan_shader_output_decl(struct radv_shader_context
*ctx
,
2375 struct nir_variable
*variable
,
2376 struct nir_shader
*shader
,
2377 gl_shader_stage stage
)
2379 int idx
= variable
->data
.location
+ variable
->data
.index
;
2380 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2381 uint64_t mask_attribs
;
2383 variable
->data
.driver_location
= idx
* 4;
2385 /* tess ctrl has it's own load/store paths for outputs */
2386 if (stage
== MESA_SHADER_TESS_CTRL
)
2389 if (variable
->data
.compact
) {
2390 unsigned component_count
= variable
->data
.location_frac
+
2391 glsl_get_length(variable
->type
);
2392 attrib_count
= (component_count
+ 3) / 4;
2395 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2396 if (stage
== MESA_SHADER_VERTEX
||
2397 stage
== MESA_SHADER_TESS_EVAL
||
2398 stage
== MESA_SHADER_GEOMETRY
) {
2399 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2400 if (stage
== MESA_SHADER_VERTEX
) {
2401 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2402 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2403 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2405 if (stage
== MESA_SHADER_TESS_EVAL
) {
2406 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2407 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2408 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2413 ctx
->output_mask
|= mask_attribs
;
2417 /* Initialize arguments for the shader export intrinsic */
2419 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2420 LLVMValueRef
*values
,
2421 unsigned enabled_channels
,
2423 struct ac_export_args
*args
)
2425 /* Specify the channels that are enabled. */
2426 args
->enabled_channels
= enabled_channels
;
2428 /* Specify whether the EXEC mask represents the valid mask */
2429 args
->valid_mask
= 0;
2431 /* Specify whether this is the last export */
2434 /* Specify the target we are exporting */
2435 args
->target
= target
;
2437 args
->compr
= false;
2438 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2439 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2440 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2441 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2446 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
2447 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2448 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2449 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2450 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2451 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2454 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2455 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2456 unsigned bits
, bool hi
) = NULL
;
2458 switch(col_format
) {
2459 case V_028714_SPI_SHADER_ZERO
:
2460 args
->enabled_channels
= 0; /* writemask */
2461 args
->target
= V_008DFC_SQ_EXP_NULL
;
2464 case V_028714_SPI_SHADER_32_R
:
2465 args
->enabled_channels
= 1;
2466 args
->out
[0] = values
[0];
2469 case V_028714_SPI_SHADER_32_GR
:
2470 args
->enabled_channels
= 0x3;
2471 args
->out
[0] = values
[0];
2472 args
->out
[1] = values
[1];
2475 case V_028714_SPI_SHADER_32_AR
:
2476 if (ctx
->ac
.chip_class
>= GFX10
) {
2477 args
->enabled_channels
= 0x3;
2478 args
->out
[0] = values
[0];
2479 args
->out
[1] = values
[3];
2481 args
->enabled_channels
= 0x9;
2482 args
->out
[0] = values
[0];
2483 args
->out
[3] = values
[3];
2487 case V_028714_SPI_SHADER_FP16_ABGR
:
2488 args
->enabled_channels
= 0x5;
2489 packf
= ac_build_cvt_pkrtz_f16
;
2491 for (unsigned chan
= 0; chan
< 4; chan
++)
2492 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
2498 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2499 args
->enabled_channels
= 0x5;
2500 packf
= ac_build_cvt_pknorm_u16
;
2503 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2504 args
->enabled_channels
= 0x5;
2505 packf
= ac_build_cvt_pknorm_i16
;
2508 case V_028714_SPI_SHADER_UINT16_ABGR
:
2509 args
->enabled_channels
= 0x5;
2510 packi
= ac_build_cvt_pk_u16
;
2512 for (unsigned chan
= 0; chan
< 4; chan
++)
2513 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
2514 ac_to_integer(&ctx
->ac
, values
[chan
]),
2519 case V_028714_SPI_SHADER_SINT16_ABGR
:
2520 args
->enabled_channels
= 0x5;
2521 packi
= ac_build_cvt_pk_i16
;
2523 for (unsigned chan
= 0; chan
< 4; chan
++)
2524 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
2525 ac_to_integer(&ctx
->ac
, values
[chan
]),
2531 case V_028714_SPI_SHADER_32_ABGR
:
2532 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2536 /* Pack f16 or norm_i16/u16. */
2538 for (chan
= 0; chan
< 2; chan
++) {
2539 LLVMValueRef pack_args
[2] = {
2541 values
[2 * chan
+ 1]
2543 LLVMValueRef packed
;
2545 packed
= packf(&ctx
->ac
, pack_args
);
2546 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2548 args
->compr
= 1; /* COMPR flag */
2553 for (chan
= 0; chan
< 2; chan
++) {
2554 LLVMValueRef pack_args
[2] = {
2555 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2556 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2558 LLVMValueRef packed
;
2560 packed
= packi(&ctx
->ac
, pack_args
,
2561 is_int8
? 8 : is_int10
? 10 : 16,
2563 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2565 args
->compr
= 1; /* COMPR flag */
2571 for (unsigned chan
= 0; chan
< 4; chan
++) {
2572 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
2573 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
2576 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2578 for (unsigned i
= 0; i
< 4; ++i
)
2579 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2583 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2584 LLVMValueRef
*values
, unsigned enabled_channels
)
2586 struct ac_export_args args
;
2588 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2589 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2590 ac_build_export(&ctx
->ac
, &args
);
2594 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2596 LLVMValueRef output
;
2598 if (ctx
->vertexptr
) {
2599 LLVMValueRef gep_idx
[3] = {
2600 ctx
->ac
.i32_0
, /* implicit C-style array */
2601 ctx
->ac
.i32_0
, /* second value of struct */
2602 ctx
->ac
.i32_1
, /* stream 1: source data index */
2605 gep_idx
[2] = LLVMConstInt(ctx
->ac
.i32
, ac_llvm_reg_index_soa(index
, chan
), false);
2606 output
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->vertexptr
, gep_idx
, 3, "");
2608 output
= ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2611 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2615 radv_emit_stream_output(struct radv_shader_context
*ctx
,
2616 LLVMValueRef
const *so_buffers
,
2617 LLVMValueRef
const *so_write_offsets
,
2618 const struct radv_stream_output
*output
)
2620 unsigned num_comps
= util_bitcount(output
->component_mask
);
2621 unsigned loc
= output
->location
;
2622 unsigned buf
= output
->buffer
;
2623 unsigned offset
= output
->offset
;
2625 LLVMValueRef out
[4];
2627 assert(num_comps
&& num_comps
<= 4);
2628 if (!num_comps
|| num_comps
> 4)
2631 /* Get the first component. */
2632 start
= ffs(output
->component_mask
) - 1;
2634 /* Load the output as int. */
2635 for (int i
= 0; i
< num_comps
; i
++) {
2636 out
[i
] = ac_to_integer(&ctx
->ac
,
2637 radv_load_output(ctx
, loc
, start
+ i
));
2640 /* Pack the output. */
2641 LLVMValueRef vdata
= NULL
;
2643 switch (num_comps
) {
2644 case 1: /* as i32 */
2647 case 2: /* as v2i32 */
2648 case 3: /* as v4i32 (aligned to 4) */
2649 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
2651 case 4: /* as v4i32 */
2652 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
2653 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
2654 util_next_power_of_two(num_comps
) :
2659 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
2660 vdata
, num_comps
, so_write_offsets
[buf
],
2661 ctx
->ac
.i32_0
, offset
,
2662 ac_glc
| ac_slc
, false);
2666 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
2668 struct ac_build_if_state if_ctx
;
2671 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2672 assert(ctx
->streamout_config
);
2673 LLVMValueRef so_vtx_count
=
2674 ac_build_bfe(&ctx
->ac
, ctx
->streamout_config
,
2675 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2676 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
2678 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2680 /* can_emit = tid < so_vtx_count; */
2681 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
2682 tid
, so_vtx_count
, "");
2684 /* Emit the streamout code conditionally. This actually avoids
2685 * out-of-bounds buffer access. The hw tells us via the SGPR
2686 * (so_vtx_count) which threads are allowed to emit streamout data.
2688 ac_nir_build_if(&if_ctx
, ctx
, can_emit
);
2690 /* The buffer offset is computed as follows:
2691 * ByteOffset = streamout_offset[buffer_id]*4 +
2692 * (streamout_write_index + thread_id)*stride[buffer_id] +
2695 LLVMValueRef so_write_index
= ctx
->streamout_write_idx
;
2697 /* Compute (streamout_write_index + thread_id). */
2699 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
2701 /* Load the descriptor and compute the write offset for each
2704 LLVMValueRef so_write_offset
[4] = {};
2705 LLVMValueRef so_buffers
[4] = {};
2706 LLVMValueRef buf_ptr
= ctx
->streamout_buffers
;
2708 for (i
= 0; i
< 4; i
++) {
2709 uint16_t stride
= ctx
->shader_info
->info
.so
.strides
[i
];
2714 LLVMValueRef offset
=
2715 LLVMConstInt(ctx
->ac
.i32
, i
, false);
2717 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
2720 LLVMValueRef so_offset
= ctx
->streamout_offset
[i
];
2722 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
2723 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2725 so_write_offset
[i
] =
2726 ac_build_imad(&ctx
->ac
, so_write_index
,
2727 LLVMConstInt(ctx
->ac
.i32
,
2732 /* Write streamout data. */
2733 for (i
= 0; i
< ctx
->shader_info
->info
.so
.num_outputs
; i
++) {
2734 struct radv_stream_output
*output
=
2735 &ctx
->shader_info
->info
.so
.outputs
[i
];
2737 if (stream
!= output
->stream
)
2740 radv_emit_stream_output(ctx
, so_buffers
,
2741 so_write_offset
, output
);
2744 ac_nir_build_endif(&if_ctx
);
2747 struct radv_shader_output_values
{
2748 LLVMValueRef values
[4];
2750 unsigned slot_index
;
2751 unsigned usage_mask
;
2755 radv_build_param_exports(struct radv_shader_context
*ctx
,
2756 struct radv_shader_output_values
*outputs
,
2758 struct radv_vs_output_info
*outinfo
,
2759 bool export_clip_dists
)
2761 unsigned param_count
= 0;
2763 for (unsigned i
= 0; i
< noutput
; i
++) {
2764 unsigned slot_name
= outputs
[i
].slot_name
;
2765 unsigned usage_mask
= outputs
[i
].usage_mask
;
2767 if (slot_name
!= VARYING_SLOT_LAYER
&&
2768 slot_name
!= VARYING_SLOT_PRIMITIVE_ID
&&
2769 slot_name
!= VARYING_SLOT_CLIP_DIST0
&&
2770 slot_name
!= VARYING_SLOT_CLIP_DIST1
&&
2771 slot_name
< VARYING_SLOT_VAR0
)
2774 if ((slot_name
== VARYING_SLOT_CLIP_DIST0
||
2775 slot_name
== VARYING_SLOT_CLIP_DIST1
) && !export_clip_dists
)
2778 radv_export_param(ctx
, param_count
, outputs
[i
].values
, usage_mask
);
2780 assert(i
< ARRAY_SIZE(outinfo
->vs_output_param_offset
));
2781 outinfo
->vs_output_param_offset
[slot_name
] = param_count
++;
2784 outinfo
->param_exports
= param_count
;
2787 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2788 * (position and parameter data only).
2791 radv_llvm_export_vs(struct radv_shader_context
*ctx
,
2792 struct radv_shader_output_values
*outputs
,
2794 struct radv_vs_output_info
*outinfo
,
2795 bool export_clip_dists
)
2797 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_value
= NULL
;
2798 struct ac_export_args pos_args
[4] = {};
2799 unsigned pos_idx
, index
;
2802 /* Build position exports */
2803 for (i
= 0; i
< noutput
; i
++) {
2804 switch (outputs
[i
].slot_name
) {
2805 case VARYING_SLOT_POS
:
2806 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
2807 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2809 case VARYING_SLOT_PSIZ
:
2810 psize_value
= outputs
[i
].values
[0];
2812 case VARYING_SLOT_LAYER
:
2813 layer_value
= outputs
[i
].values
[0];
2815 case VARYING_SLOT_VIEWPORT
:
2816 viewport_value
= outputs
[i
].values
[0];
2818 case VARYING_SLOT_CLIP_DIST0
:
2819 case VARYING_SLOT_CLIP_DIST1
:
2820 index
= 2 + outputs
[i
].slot_index
;
2821 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
2822 V_008DFC_SQ_EXP_POS
+ index
,
2830 /* We need to add the position output manually if it's missing. */
2831 if (!pos_args
[0].out
[0]) {
2832 pos_args
[0].enabled_channels
= 0xf; /* writemask */
2833 pos_args
[0].valid_mask
= 0; /* EXEC mask */
2834 pos_args
[0].done
= 0; /* last export? */
2835 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
2836 pos_args
[0].compr
= 0; /* COMPR flag */
2837 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
2838 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
2839 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
2840 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
2843 if (outinfo
->writes_pointsize
||
2844 outinfo
->writes_layer
||
2845 outinfo
->writes_viewport_index
) {
2846 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2847 (outinfo
->writes_layer
== true ? 4 : 0));
2848 pos_args
[1].valid_mask
= 0;
2849 pos_args
[1].done
= 0;
2850 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2851 pos_args
[1].compr
= 0;
2852 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2853 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2854 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2855 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2857 if (outinfo
->writes_pointsize
== true)
2858 pos_args
[1].out
[0] = psize_value
;
2859 if (outinfo
->writes_layer
== true)
2860 pos_args
[1].out
[2] = layer_value
;
2861 if (outinfo
->writes_viewport_index
== true) {
2862 if (ctx
->options
->chip_class
>= GFX9
) {
2863 /* GFX9 has the layer in out.z[10:0] and the viewport
2864 * index in out.z[19:16].
2866 LLVMValueRef v
= viewport_value
;
2867 v
= ac_to_integer(&ctx
->ac
, v
);
2868 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2869 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2871 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2872 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2874 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2875 pos_args
[1].enabled_channels
|= 1 << 2;
2877 pos_args
[1].out
[3] = viewport_value
;
2878 pos_args
[1].enabled_channels
|= 1 << 3;
2883 for (i
= 0; i
< 4; i
++) {
2884 if (pos_args
[i
].out
[0])
2885 outinfo
->pos_exports
++;
2888 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2889 * Setting valid_mask=1 prevents it and has no other effect.
2891 if (ctx
->ac
.family
== CHIP_NAVI10
||
2892 ctx
->ac
.family
== CHIP_NAVI12
||
2893 ctx
->ac
.family
== CHIP_NAVI14
)
2894 pos_args
[0].valid_mask
= 1;
2897 for (i
= 0; i
< 4; i
++) {
2898 if (!pos_args
[i
].out
[0])
2901 /* Specify the target we are exporting */
2902 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2904 if (pos_idx
== outinfo
->pos_exports
)
2905 /* Specify that this is the last export */
2906 pos_args
[i
].done
= 1;
2908 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2911 /* Build parameter exports */
2912 radv_build_param_exports(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2916 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2917 bool export_prim_id
,
2918 bool export_clip_dists
,
2919 struct radv_vs_output_info
*outinfo
)
2921 struct radv_shader_output_values
*outputs
;
2922 unsigned noutput
= 0;
2924 if (ctx
->options
->key
.has_multiview_view_index
) {
2925 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2927 for(unsigned i
= 0; i
< 4; ++i
)
2928 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2929 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2932 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
2933 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2936 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2937 sizeof(outinfo
->vs_output_param_offset
));
2938 outinfo
->pos_exports
= 0;
2940 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
2941 outinfo
->writes_pointsize
= true;
2944 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
2945 outinfo
->writes_layer
= true;
2948 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
2949 outinfo
->writes_viewport_index
= true;
2952 if (ctx
->shader_info
->info
.so
.num_outputs
&&
2953 !ctx
->is_gs_copy_shader
) {
2954 /* The GS copy shader emission already emits streamout. */
2955 radv_emit_streamout(ctx
, 0);
2958 /* Allocate a temporary array for the output values. */
2959 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_prim_id
;
2960 outputs
= malloc(num_outputs
* sizeof(outputs
[0]));
2962 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2963 if (!(ctx
->output_mask
& (1ull << i
)))
2966 outputs
[noutput
].slot_name
= i
;
2967 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2969 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2970 !ctx
->is_gs_copy_shader
) {
2971 outputs
[noutput
].usage_mask
=
2972 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2973 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2974 outputs
[noutput
].usage_mask
=
2975 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2977 assert(ctx
->is_gs_copy_shader
|| ctx
->options
->key
.vs_common_out
.as_ngg
);
2978 outputs
[noutput
].usage_mask
=
2979 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
2982 for (unsigned j
= 0; j
< 4; j
++) {
2983 outputs
[noutput
].values
[j
] =
2984 ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2990 /* Export PrimitiveID. */
2991 if (export_prim_id
) {
2992 outinfo
->export_prim_id
= true;
2994 outputs
[noutput
].slot_name
= VARYING_SLOT_PRIMITIVE_ID
;
2995 outputs
[noutput
].slot_index
= 0;
2996 outputs
[noutput
].usage_mask
= 0x1;
2997 outputs
[noutput
].values
[0] = ctx
->vs_prim_id
;
2998 for (unsigned j
= 1; j
< 4; j
++)
2999 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
3003 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
3009 handle_es_outputs_post(struct radv_shader_context
*ctx
,
3010 struct radv_es_output_info
*outinfo
)
3013 uint64_t max_output_written
= 0;
3014 LLVMValueRef lds_base
= NULL
;
3016 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3019 if (!(ctx
->output_mask
& (1ull << i
)))
3022 param_index
= shader_io_get_unique_index(i
);
3024 max_output_written
= MAX2(param_index
, max_output_written
);
3027 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
3029 if (ctx
->ac
.chip_class
>= GFX9
) {
3030 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
3031 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
3032 LLVMValueRef wave_idx
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
3033 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
3034 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
3035 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
3036 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
3037 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
3040 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3041 LLVMValueRef dw_addr
= NULL
;
3042 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
3043 unsigned output_usage_mask
;
3046 if (!(ctx
->output_mask
& (1ull << i
)))
3049 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3051 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
3053 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3055 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
3058 param_index
= shader_io_get_unique_index(i
);
3061 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3062 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
3066 for (j
= 0; j
< 4; j
++) {
3067 if (!(output_usage_mask
& (1 << j
)))
3070 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
3071 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3072 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3074 if (ctx
->ac
.chip_class
>= GFX9
) {
3075 LLVMValueRef dw_addr_offset
=
3076 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3077 LLVMConstInt(ctx
->ac
.i32
,
3080 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
3082 ac_build_buffer_store_dword(&ctx
->ac
,
3085 NULL
, ctx
->es2gs_offset
,
3086 (4 * param_index
+ j
) * 4,
3087 ac_glc
| ac_slc
, true);
3094 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
3096 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
3097 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->shader_info
->info
.vs
.ls_outputs_written
);
3098 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
3099 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
3100 vertex_dw_stride
, "");
3102 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3103 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
3105 if (!(ctx
->output_mask
& (1ull << i
)))
3108 int param
= shader_io_get_unique_index(i
);
3109 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
3110 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
3112 for (unsigned j
= 0; j
< 4; j
++) {
3113 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
3114 value
= ac_to_integer(&ctx
->ac
, value
);
3115 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
3116 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
3117 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
3122 static LLVMValueRef
get_wave_id_in_tg(struct radv_shader_context
*ctx
)
3124 return ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
3127 static LLVMValueRef
get_tgsize(struct radv_shader_context
*ctx
)
3129 return ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 28, 4);
3132 static LLVMValueRef
get_thread_id_in_tg(struct radv_shader_context
*ctx
)
3134 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3136 tmp
= LLVMBuildMul(builder
, get_wave_id_in_tg(ctx
),
3137 LLVMConstInt(ctx
->ac
.i32
, 64, false), "");
3138 return LLVMBuildAdd(builder
, tmp
, ac_get_thread_id(&ctx
->ac
), "");
3141 static LLVMValueRef
ngg_get_vtx_cnt(struct radv_shader_context
*ctx
)
3143 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
3144 LLVMConstInt(ctx
->ac
.i32
, 12, false),
3145 LLVMConstInt(ctx
->ac
.i32
, 9, false),
3149 static LLVMValueRef
ngg_get_prim_cnt(struct radv_shader_context
*ctx
)
3151 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
3152 LLVMConstInt(ctx
->ac
.i32
, 22, false),
3153 LLVMConstInt(ctx
->ac
.i32
, 9, false),
3158 ngg_gs_get_vertex_storage(struct radv_shader_context
*ctx
)
3160 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
);
3162 LLVMTypeRef elements
[2] = {
3163 LLVMArrayType(ctx
->ac
.i32
, 4 * num_outputs
),
3164 LLVMArrayType(ctx
->ac
.i8
, 4),
3166 LLVMTypeRef type
= LLVMStructTypeInContext(ctx
->ac
.context
, elements
, 2, false);
3167 type
= LLVMPointerType(LLVMArrayType(type
, 0), AC_ADDR_SPACE_LDS
);
3168 return LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gs_ngg_emit
, type
, "");
3172 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
3173 * is in emit order; that is:
3174 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
3175 * - during vertex emit, i.e. while the API GS shader invocation is running,
3176 * N = threadidx * gs_max_out_vertices + emitidx
3178 * Goals of the LDS memory layout:
3179 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
3180 * in uniform control flow
3181 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
3183 * 3. Agnostic to the number of waves (since we don't know it before compiling)
3184 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
3185 * 5. Avoid wasting memory.
3187 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
3188 * layout, elimination of bank conflicts requires that each vertex occupy an
3189 * odd number of dwords. We use the additional dword to store the output stream
3190 * index as well as a flag to indicate whether this vertex ends a primitive
3191 * for rasterization.
3193 * Swizzling is required to satisfy points 1 and 2 simultaneously.
3195 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
3196 * Indices are swizzled in groups of 32, which ensures point 1 without
3197 * disturbing point 2.
3199 * \return an LDS pointer to type {[N x i32], [4 x i8]}
3202 ngg_gs_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexidx
)
3204 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3205 LLVMValueRef storage
= ngg_gs_get_vertex_storage(ctx
);
3207 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
3208 unsigned write_stride_2exp
= ffs(ctx
->gs_max_out_vertices
) - 1;
3209 if (write_stride_2exp
) {
3211 LLVMBuildLShr(builder
, vertexidx
,
3212 LLVMConstInt(ctx
->ac
.i32
, 5, false), "");
3213 LLVMValueRef swizzle
=
3214 LLVMBuildAnd(builder
, row
,
3215 LLVMConstInt(ctx
->ac
.i32
, (1u << write_stride_2exp
) - 1,
3217 vertexidx
= LLVMBuildXor(builder
, vertexidx
, swizzle
, "");
3220 return ac_build_gep0(&ctx
->ac
, storage
, vertexidx
);
3224 ngg_gs_emit_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef gsthread
,
3225 LLVMValueRef emitidx
)
3227 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3230 tmp
= LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false);
3231 tmp
= LLVMBuildMul(builder
, tmp
, gsthread
, "");
3232 const LLVMValueRef vertexidx
= LLVMBuildAdd(builder
, tmp
, emitidx
, "");
3233 return ngg_gs_vertex_ptr(ctx
, vertexidx
);
3236 /* Send GS Alloc Req message from the first wave of the group to SPI.
3237 * Message payload is:
3238 * - bits 0..10: vertices in group
3239 * - bits 12..22: primitives in group
3241 static void build_sendmsg_gs_alloc_req(struct radv_shader_context
*ctx
,
3242 LLVMValueRef vtx_cnt
,
3243 LLVMValueRef prim_cnt
)
3245 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3248 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
3249 ac_build_ifcc(&ctx
->ac
, tmp
, 5020);
3251 tmp
= LLVMBuildShl(builder
, prim_cnt
, LLVMConstInt(ctx
->ac
.i32
, 12, false),"");
3252 tmp
= LLVMBuildOr(builder
, tmp
, vtx_cnt
, "");
3253 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_ALLOC_REQ
, tmp
);
3255 ac_build_endif(&ctx
->ac
, 5020);
3259 unsigned num_vertices
;
3260 LLVMValueRef isnull
;
3261 LLVMValueRef index
[3];
3262 LLVMValueRef edgeflag
[3];
3265 static void build_export_prim(struct radv_shader_context
*ctx
,
3266 const struct ngg_prim
*prim
)
3268 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3269 struct ac_export_args args
;
3272 tmp
= LLVMBuildZExt(builder
, prim
->isnull
, ctx
->ac
.i32
, "");
3273 args
.out
[0] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 31, false), "");
3275 for (unsigned i
= 0; i
< prim
->num_vertices
; ++i
) {
3276 tmp
= LLVMBuildShl(builder
, prim
->index
[i
],
3277 LLVMConstInt(ctx
->ac
.i32
, 10 * i
, false), "");
3278 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3279 tmp
= LLVMBuildZExt(builder
, prim
->edgeflag
[i
], ctx
->ac
.i32
, "");
3280 tmp
= LLVMBuildShl(builder
, tmp
,
3281 LLVMConstInt(ctx
->ac
.i32
, 10 * i
+ 9, false), "");
3282 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3285 args
.out
[0] = LLVMBuildBitCast(builder
, args
.out
[0], ctx
->ac
.f32
, "");
3286 args
.out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
3287 args
.out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
3288 args
.out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
3290 args
.target
= V_008DFC_SQ_EXP_PRIM
;
3291 args
.enabled_channels
= 1;
3293 args
.valid_mask
= false;
3296 ac_build_export(&ctx
->ac
, &args
);
3300 handle_ngg_outputs_post(struct radv_shader_context
*ctx
)
3302 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3303 struct ac_build_if_state if_state
;
3304 unsigned num_vertices
= 3;
3307 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
3308 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->is_gs_copy_shader
);
3310 LLVMValueRef prims_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
3311 LLVMValueRef vtx_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 0, 8);
3312 LLVMValueRef is_gs_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3313 ac_get_thread_id(&ctx
->ac
), prims_in_wave
, "");
3314 LLVMValueRef is_es_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3315 ac_get_thread_id(&ctx
->ac
), vtx_in_wave
, "");
3316 LLVMValueRef vtxindex
[] = {
3317 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 0, 16),
3318 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 16, 16),
3319 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[2], 0, 16),
3322 /* TODO: streamout */
3324 /* TODO: VS primitive ID */
3325 if (ctx
->options
->key
.vs_common_out
.export_prim_id
)
3328 /* TODO: primitive culling */
3330 build_sendmsg_gs_alloc_req(ctx
, ngg_get_vtx_cnt(ctx
), ngg_get_prim_cnt(ctx
));
3332 /* TODO: streamout queries */
3333 /* Export primitive data to the index buffer. Format is:
3334 * - bits 0..8: index 0
3335 * - bit 9: edge flag 0
3336 * - bits 10..18: index 1
3337 * - bit 19: edge flag 1
3338 * - bits 20..28: index 2
3339 * - bit 29: edge flag 2
3340 * - bit 31: null primitive (skip)
3342 * For the first version, we will always build up all three indices
3343 * independent of the primitive type. The additional garbage data
3346 * TODO: culling depends on the primitive type, so can have some
3349 ac_nir_build_if(&if_state
, ctx
, is_gs_thread
);
3351 struct ngg_prim prim
= {};
3353 prim
.num_vertices
= num_vertices
;
3354 prim
.isnull
= ctx
->ac
.i1false
;
3355 memcpy(prim
.index
, vtxindex
, sizeof(vtxindex
[0]) * 3);
3357 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
3358 tmp
= LLVMBuildLShr(builder
, ctx
->abi
.gs_invocation_id
,
3359 LLVMConstInt(ctx
->ac
.i32
, 8 + i
, false), "");
3360 prim
.edgeflag
[i
] = LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3363 build_export_prim(ctx
, &prim
);
3365 ac_nir_build_endif(&if_state
);
3367 /* Export per-vertex data (positions and parameters). */
3368 ac_nir_build_if(&if_state
, ctx
, is_es_thread
);
3370 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
3371 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
3372 ctx
->stage
== MESA_SHADER_TESS_EVAL
? &ctx
->shader_info
->tes
.outinfo
: &ctx
->shader_info
->vs
.outinfo
);
3374 ac_nir_build_endif(&if_state
);
3377 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context
*ctx
)
3379 /* Zero out the part of LDS scratch that is used to accumulate the
3380 * per-stream generated primitive count.
3382 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3383 LLVMValueRef scratchptr
= ctx
->gs_ngg_scratch
;
3384 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3387 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3388 ac_build_ifcc(&ctx
->ac
, tmp
, 5090);
3390 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, scratchptr
, tid
);
3391 LLVMBuildStore(builder
, ctx
->ac
.i32_0
, ptr
);
3393 ac_build_endif(&ctx
->ac
, 5090);
3395 ac_build_s_barrier(&ctx
->ac
);
3398 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context
*ctx
)
3400 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3401 LLVMValueRef i8_0
= LLVMConstInt(ctx
->ac
.i8
, 0, false);
3404 /* Zero out remaining (non-emitted) primitive flags.
3406 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3407 * the emit threads via LDS. This is likely worse in the expected
3408 * typical case where each GS thread emits the full set of
3411 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3412 unsigned num_components
;
3415 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
3416 if (!num_components
)
3419 const LLVMValueRef gsthread
= get_thread_id_in_tg(ctx
);
3421 ac_build_bgnloop(&ctx
->ac
, 5100);
3423 const LLVMValueRef vertexidx
=
3424 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3425 tmp
= LLVMBuildICmp(builder
, LLVMIntUGE
, vertexidx
,
3426 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
3427 ac_build_ifcc(&ctx
->ac
, tmp
, 5101);
3428 ac_build_break(&ctx
->ac
);
3429 ac_build_endif(&ctx
->ac
, 5101);
3431 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3432 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3434 tmp
= ngg_gs_emit_vertex_ptr(ctx
, gsthread
, vertexidx
);
3435 LLVMValueRef gep_idx
[3] = {
3436 ctx
->ac
.i32_0
, /* implied C-style array */
3437 ctx
->ac
.i32_1
, /* second entry of struct */
3438 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3440 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3441 LLVMBuildStore(builder
, i8_0
, tmp
);
3443 ac_build_endloop(&ctx
->ac
, 5100);
3447 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context
*ctx
)
3449 const unsigned verts_per_prim
= si_conv_gl_prim_to_vertices(ctx
->gs_output_prim
);
3450 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3451 LLVMValueRef tmp
, tmp2
;
3453 ac_build_s_barrier(&ctx
->ac
);
3455 const LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3456 LLVMValueRef num_emit_threads
= ngg_get_prim_cnt(ctx
);
3458 /* TODO: streamout */
3462 /* Determine vertex liveness. */
3463 LLVMValueRef vertliveptr
= ac_build_alloca(&ctx
->ac
, ctx
->ac
.i1
, "vertexlive");
3465 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3466 ac_build_ifcc(&ctx
->ac
, tmp
, 5120);
3468 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3469 const LLVMValueRef primidx
=
3470 LLVMBuildAdd(builder
, tid
,
3471 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
3474 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, primidx
, num_emit_threads
, "");
3475 ac_build_ifcc(&ctx
->ac
, tmp
, 5121 + i
);
3478 /* Load primitive liveness */
3479 tmp
= ngg_gs_vertex_ptr(ctx
, primidx
);
3480 LLVMValueRef gep_idx
[3] = {
3481 ctx
->ac
.i32_0
, /* implicit C-style array */
3482 ctx
->ac
.i32_1
, /* second value of struct */
3483 ctx
->ac
.i32_0
, /* stream 0 */
3485 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3486 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3487 const LLVMValueRef primlive
=
3488 LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3490 tmp
= LLVMBuildLoad(builder
, vertliveptr
, "");
3491 tmp
= LLVMBuildOr(builder
, tmp
, primlive
, ""),
3492 LLVMBuildStore(builder
, tmp
, vertliveptr
);
3495 ac_build_endif(&ctx
->ac
, 5121 + i
);
3498 ac_build_endif(&ctx
->ac
, 5120);
3500 /* Inclusive scan addition across the current wave. */
3501 LLVMValueRef vertlive
= LLVMBuildLoad(builder
, vertliveptr
, "");
3502 struct ac_wg_scan vertlive_scan
= {};
3503 vertlive_scan
.op
= nir_op_iadd
;
3504 vertlive_scan
.enable_reduce
= true;
3505 vertlive_scan
.enable_exclusive
= true;
3506 vertlive_scan
.src
= vertlive
;
3507 vertlive_scan
.scratch
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ctx
->ac
.i32_0
);
3508 vertlive_scan
.waveidx
= get_wave_id_in_tg(ctx
);
3509 vertlive_scan
.numwaves
= get_tgsize(ctx
);
3510 vertlive_scan
.maxwaves
= 8;
3512 ac_build_wg_scan(&ctx
->ac
, &vertlive_scan
);
3514 /* Skip all exports (including index exports) when possible. At least on
3515 * early gfx10 revisions this is also to avoid hangs.
3517 LLVMValueRef have_exports
=
3518 LLVMBuildICmp(builder
, LLVMIntNE
, vertlive_scan
.result_reduce
, ctx
->ac
.i32_0
, "");
3520 LLVMBuildSelect(builder
, have_exports
, num_emit_threads
, ctx
->ac
.i32_0
, "");
3522 /* Allocate export space. Send this message as early as possible, to
3523 * hide the latency of the SQ <-> SPI roundtrip.
3525 * Note: We could consider compacting primitives for export as well.
3526 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3527 * prim data per clock and skips null primitives at no additional
3528 * cost. So compacting primitives can only be beneficial when
3529 * there are 4 or more contiguous null primitives in the export
3530 * (in the common case of single-dword prim exports).
3532 build_sendmsg_gs_alloc_req(ctx
, vertlive_scan
.result_reduce
, num_emit_threads
);
3534 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3535 * of the primitive liveness flags, relying on the fact that each
3536 * threadgroup can have at most 256 threads. */
3537 ac_build_ifcc(&ctx
->ac
, vertlive
, 5130);
3539 tmp
= ngg_gs_vertex_ptr(ctx
, vertlive_scan
.result_exclusive
);
3540 LLVMValueRef gep_idx
[3] = {
3541 ctx
->ac
.i32_0
, /* implicit C-style array */
3542 ctx
->ac
.i32_1
, /* second value of struct */
3543 ctx
->ac
.i32_1
, /* stream 1 */
3545 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3546 tmp2
= LLVMBuildTrunc(builder
, tid
, ctx
->ac
.i8
, "");
3547 LLVMBuildStore(builder
, tmp2
, tmp
);
3549 ac_build_endif(&ctx
->ac
, 5130);
3551 ac_build_s_barrier(&ctx
->ac
);
3553 /* Export primitive data */
3554 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3555 ac_build_ifcc(&ctx
->ac
, tmp
, 5140);
3557 struct ngg_prim prim
= {};
3558 prim
.num_vertices
= verts_per_prim
;
3560 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3561 LLVMValueRef gep_idx
[3] = {
3562 ctx
->ac
.i32_0
, /* implicit C-style array */
3563 ctx
->ac
.i32_1
, /* second value of struct */
3564 ctx
->ac
.i32_0
, /* primflag */
3566 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3567 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3568 prim
.isnull
= LLVMBuildICmp(builder
, LLVMIntEQ
, tmp
,
3569 LLVMConstInt(ctx
->ac
.i8
, 0, false), "");
3571 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3572 prim
.index
[i
] = LLVMBuildSub(builder
, vertlive_scan
.result_exclusive
,
3573 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3574 prim
.edgeflag
[i
] = ctx
->ac
.i1false
;
3577 build_export_prim(ctx
, &prim
);
3579 ac_build_endif(&ctx
->ac
, 5140);
3581 /* Export position and parameter data */
3582 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, vertlive_scan
.result_reduce
, "");
3583 ac_build_ifcc(&ctx
->ac
, tmp
, 5145);
3585 struct radv_vs_output_info
*outinfo
= &ctx
->shader_info
->vs
.outinfo
;
3586 bool export_view_index
= ctx
->options
->key
.has_multiview_view_index
;
3587 struct radv_shader_output_values
*outputs
;
3588 unsigned noutput
= 0;
3590 /* Allocate a temporary array for the output values. */
3591 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_view_index
;
3592 outputs
= calloc(num_outputs
, sizeof(outputs
[0]));
3594 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
3595 sizeof(outinfo
->vs_output_param_offset
));
3596 outinfo
->pos_exports
= 0;
3598 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3599 LLVMValueRef gep_idx
[3] = {
3600 ctx
->ac
.i32_0
, /* implicit C-style array */
3601 ctx
->ac
.i32_1
, /* second value of struct */
3602 ctx
->ac
.i32_1
, /* stream 1: source data index */
3604 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3605 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3606 tmp
= LLVMBuildZExt(builder
, tmp
, ctx
->ac
.i32
, "");
3607 const LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tmp
);
3609 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
3610 outinfo
->writes_pointsize
= true;
3613 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
3614 outinfo
->writes_layer
= true;
3617 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
3618 outinfo
->writes_viewport_index
= true;
3621 unsigned out_idx
= 0;
3622 gep_idx
[1] = ctx
->ac
.i32_0
;
3623 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3624 if (!(ctx
->output_mask
& (1ull << i
)))
3627 outputs
[noutput
].slot_name
= i
;
3628 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
3630 outputs
[noutput
].usage_mask
= ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
3631 int length
= util_last_bit(outputs
[noutput
].usage_mask
);
3633 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3634 gep_idx
[2] = LLVMConstInt(ctx
->ac
.i32
, out_idx
, false);
3635 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3636 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3637 outputs
[noutput
].values
[j
] = ac_to_float(&ctx
->ac
, tmp
);
3640 for (unsigned j
= length
; j
< 4; j
++)
3641 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
3646 /* Export ViewIndex. */
3647 if (export_view_index
) {
3648 outinfo
->writes_layer
= true;
3650 outputs
[noutput
].slot_name
= VARYING_SLOT_LAYER
;
3651 outputs
[noutput
].slot_index
= 0;
3652 outputs
[noutput
].usage_mask
= 0x1;
3653 outputs
[noutput
].values
[0] = ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
);
3654 for (unsigned j
= 1; j
< 4; j
++)
3655 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
3659 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
,
3660 ctx
->options
->key
.vs_common_out
.export_clip_dists
);
3663 ac_build_endif(&ctx
->ac
, 5145);
3666 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
3668 LLVMValueRef
*addrs
)
3670 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3672 const LLVMValueRef vertexidx
=
3673 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3675 /* If this thread has already emitted the declared maximum number of
3676 * vertices, skip the write: excessive vertex emissions are not
3677 * supposed to have any effect.
3679 const LLVMValueRef can_emit
=
3680 LLVMBuildICmp(builder
, LLVMIntULT
, vertexidx
,
3681 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
3682 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
3684 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3685 tmp
= LLVMBuildSelect(builder
, can_emit
, tmp
, vertexidx
, "");
3686 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3688 const LLVMValueRef vertexptr
=
3689 ngg_gs_emit_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
), vertexidx
);
3690 unsigned out_idx
= 0;
3691 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3692 unsigned output_usage_mask
=
3693 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
3694 uint8_t output_stream
=
3695 ctx
->shader_info
->info
.gs
.output_streams
[i
];
3696 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
3697 int length
= util_last_bit(output_usage_mask
);
3699 if (!(ctx
->output_mask
& (1ull << i
)) ||
3700 output_stream
!= stream
)
3703 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3704 if (!(output_usage_mask
& (1 << j
)))
3707 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
3709 LLVMValueRef gep_idx
[3] = {
3710 ctx
->ac
.i32_0
, /* implied C-style array */
3711 ctx
->ac
.i32_0
, /* first entry of struct */
3712 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false),
3714 LLVMValueRef ptr
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3716 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3717 LLVMBuildStore(builder
, out_val
, ptr
);
3720 assert(out_idx
* 4 <= ctx
->gsvs_vertex_size
);
3722 /* Determine and store whether this vertex completed a primitive. */
3723 const LLVMValueRef curverts
= LLVMBuildLoad(builder
, ctx
->gs_curprim_verts
[stream
], "");
3725 tmp
= LLVMConstInt(ctx
->ac
.i32
, si_conv_gl_prim_to_vertices(ctx
->gs_output_prim
) - 1, false);
3726 const LLVMValueRef iscompleteprim
=
3727 LLVMBuildICmp(builder
, LLVMIntUGE
, curverts
, tmp
, "");
3729 tmp
= LLVMBuildAdd(builder
, curverts
, ctx
->ac
.i32_1
, "");
3730 LLVMBuildStore(builder
, tmp
, ctx
->gs_curprim_verts
[stream
]);
3732 LLVMValueRef gep_idx
[3] = {
3733 ctx
->ac
.i32_0
, /* implied C-style array */
3734 ctx
->ac
.i32_1
, /* second struct entry */
3735 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3737 const LLVMValueRef primflagptr
=
3738 LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3740 tmp
= LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i8
, "");
3741 LLVMBuildStore(builder
, tmp
, primflagptr
);
3743 tmp
= LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3744 tmp
= LLVMBuildAdd(builder
, tmp
, LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i32
, ""), "");
3745 LLVMBuildStore(builder
, tmp
, ctx
->gs_generated_prims
[stream
]);
3749 write_tess_factors(struct radv_shader_context
*ctx
)
3751 unsigned stride
, outer_comps
, inner_comps
;
3752 struct ac_build_if_state if_ctx
, inner_if_ctx
;
3753 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3754 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
3755 unsigned tess_inner_index
= 0, tess_outer_index
;
3756 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3757 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3759 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3761 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
3781 ac_nir_build_if(&if_ctx
, ctx
,
3782 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3783 invocation_id
, ctx
->ac
.i32_0
, ""));
3785 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3788 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3789 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3790 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3793 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3794 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3795 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3797 for (i
= 0; i
< 4; i
++) {
3798 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3799 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3803 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3804 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3805 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3807 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3809 for (i
= 0; i
< outer_comps
; i
++) {
3811 ac_lds_load(&ctx
->ac
, lds_outer
);
3812 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3815 for (i
= 0; i
< inner_comps
; i
++) {
3816 inner
[i
] = out
[outer_comps
+i
] =
3817 ac_lds_load(&ctx
->ac
, lds_inner
);
3818 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3823 /* Convert the outputs to vectors for stores. */
3824 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3828 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3831 buffer
= ctx
->hs_ring_tess_factor
;
3832 tf_base
= ctx
->tess_factor_offset
;
3833 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3834 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3835 unsigned tf_offset
= 0;
3837 if (ctx
->options
->chip_class
<= GFX8
) {
3838 ac_nir_build_if(&inner_if_ctx
, ctx
,
3839 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3840 rel_patch_id
, ctx
->ac
.i32_0
, ""));
3842 /* Store the dynamic HS control word. */
3843 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3844 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3845 1, ctx
->ac
.i32_0
, tf_base
,
3849 ac_nir_build_endif(&inner_if_ctx
);
3852 /* Store the tessellation factors. */
3853 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3854 MIN2(stride
, 4), byteoffset
, tf_base
,
3855 tf_offset
, ac_glc
, false);
3857 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3858 stride
- 4, byteoffset
, tf_base
,
3859 16 + tf_offset
, ac_glc
, false);
3861 //store to offchip for TES to read - only if TES reads them
3862 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
3863 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3864 LLVMValueRef tf_inner_offset
;
3865 unsigned param_outer
, param_inner
;
3867 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3868 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3869 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3871 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3872 util_next_power_of_two(outer_comps
));
3874 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3875 outer_comps
, tf_outer_offset
,
3876 ctx
->oc_lds
, 0, ac_glc
, false);
3878 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3879 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3880 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3882 inner_vec
= inner_comps
== 1 ? inner
[0] :
3883 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3884 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3885 inner_comps
, tf_inner_offset
,
3886 ctx
->oc_lds
, 0, ac_glc
, false);
3889 ac_nir_build_endif(&if_ctx
);
3893 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3895 write_tess_factors(ctx
);
3899 si_export_mrt_color(struct radv_shader_context
*ctx
,
3900 LLVMValueRef
*color
, unsigned index
,
3901 struct ac_export_args
*args
)
3904 si_llvm_init_export_args(ctx
, color
, 0xf,
3905 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3906 if (!args
->enabled_channels
)
3907 return false; /* unnecessary NULL export */
3913 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3914 LLVMValueRef depth
, LLVMValueRef stencil
,
3915 LLVMValueRef samplemask
)
3917 struct ac_export_args args
;
3919 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3921 ac_build_export(&ctx
->ac
, &args
);
3925 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3928 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3929 struct ac_export_args color_args
[8];
3931 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3932 LLVMValueRef values
[4];
3934 if (!(ctx
->output_mask
& (1ull << i
)))
3937 if (i
< FRAG_RESULT_DATA0
)
3940 for (unsigned j
= 0; j
< 4; j
++)
3941 values
[j
] = ac_to_float(&ctx
->ac
,
3942 radv_load_output(ctx
, i
, j
));
3944 bool ret
= si_export_mrt_color(ctx
, values
,
3945 i
- FRAG_RESULT_DATA0
,
3946 &color_args
[index
]);
3951 /* Process depth, stencil, samplemask. */
3952 if (ctx
->shader_info
->info
.ps
.writes_z
) {
3953 depth
= ac_to_float(&ctx
->ac
,
3954 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3956 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
3957 stencil
= ac_to_float(&ctx
->ac
,
3958 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
3960 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3961 samplemask
= ac_to_float(&ctx
->ac
,
3962 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
3965 /* Set the DONE bit on last non-null color export only if Z isn't
3969 !ctx
->shader_info
->info
.ps
.writes_z
&&
3970 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
3971 !ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3972 unsigned last
= index
- 1;
3974 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
3975 color_args
[last
].done
= 1; /* DONE bit */
3978 /* Export PS outputs. */
3979 for (unsigned i
= 0; i
< index
; i
++)
3980 ac_build_export(&ctx
->ac
, &color_args
[i
]);
3982 if (depth
|| stencil
|| samplemask
)
3983 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
3985 ac_build_export_null(&ctx
->ac
);
3989 emit_gs_epilogue(struct radv_shader_context
*ctx
)
3991 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
3992 gfx10_ngg_gs_emit_epilogue_1(ctx
);
3996 if (ctx
->ac
.chip_class
>= GFX10
)
3997 LLVMBuildFence(ctx
->ac
.builder
, LLVMAtomicOrderingRelease
, false, "");
3999 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
4003 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
4004 LLVMValueRef
*addrs
)
4006 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4008 switch (ctx
->stage
) {
4009 case MESA_SHADER_VERTEX
:
4010 if (ctx
->options
->key
.vs_common_out
.as_ls
)
4011 handle_ls_outputs_post(ctx
);
4012 else if (ctx
->options
->key
.vs_common_out
.as_es
)
4013 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
4014 else if (ctx
->options
->key
.vs_common_out
.as_ngg
)
4015 break; /* handled outside of the shader body */
4017 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
4018 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
4019 &ctx
->shader_info
->vs
.outinfo
);
4021 case MESA_SHADER_FRAGMENT
:
4022 handle_fs_outputs_post(ctx
);
4024 case MESA_SHADER_GEOMETRY
:
4025 emit_gs_epilogue(ctx
);
4027 case MESA_SHADER_TESS_CTRL
:
4028 handle_tcs_outputs_post(ctx
);
4030 case MESA_SHADER_TESS_EVAL
:
4031 if (ctx
->options
->key
.vs_common_out
.as_ngg
)
4032 break; /* handled outside of the shader body */
4033 else if (ctx
->options
->key
.vs_common_out
.as_es
)
4034 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
4036 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
4037 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
4038 &ctx
->shader_info
->tes
.outinfo
);
4045 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
4046 LLVMPassManagerRef passmgr
,
4047 const struct radv_nir_compiler_options
*options
)
4049 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
4050 LLVMDisposeBuilder(ctx
->ac
.builder
);
4052 ac_llvm_context_dispose(&ctx
->ac
);
4056 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
4058 struct radv_vs_output_info
*outinfo
;
4060 switch (ctx
->stage
) {
4061 case MESA_SHADER_FRAGMENT
:
4062 case MESA_SHADER_COMPUTE
:
4063 case MESA_SHADER_TESS_CTRL
:
4064 case MESA_SHADER_GEOMETRY
:
4066 case MESA_SHADER_VERTEX
:
4067 if (ctx
->options
->key
.vs_common_out
.as_ls
||
4068 ctx
->options
->key
.vs_common_out
.as_es
)
4070 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
4072 case MESA_SHADER_TESS_EVAL
:
4073 if (ctx
->options
->key
.vs_common_out
.as_es
)
4075 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
4078 unreachable("Unhandled shader type");
4081 ac_optimize_vs_outputs(&ctx
->ac
,
4083 outinfo
->vs_output_param_offset
,
4085 &outinfo
->param_exports
);
4089 ac_setup_rings(struct radv_shader_context
*ctx
)
4091 if (ctx
->options
->chip_class
<= GFX8
&&
4092 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
4093 ctx
->options
->key
.vs_common_out
.as_es
|| ctx
->options
->key
.vs_common_out
.as_es
)) {
4094 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
4096 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
4098 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
4103 if (ctx
->is_gs_copy_shader
) {
4105 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
4106 LLVMConstInt(ctx
->ac
.i32
,
4107 RING_GSVS_VS
, false));
4110 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4111 /* The conceptual layout of the GSVS ring is
4112 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4113 * but the real memory layout is swizzled across
4115 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4117 * Override the buffer descriptor accordingly.
4119 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
4120 uint64_t stream_offset
= 0;
4121 unsigned num_records
= 64;
4122 LLVMValueRef base_ring
;
4125 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
4126 LLVMConstInt(ctx
->ac
.i32
,
4127 RING_GSVS_GS
, false));
4129 for (unsigned stream
= 0; stream
< 4; stream
++) {
4130 unsigned num_components
, stride
;
4131 LLVMValueRef ring
, tmp
;
4134 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
4136 if (!num_components
)
4139 stride
= 4 * num_components
* ctx
->gs_max_out_vertices
;
4141 /* Limit on the stride field for <= GFX7. */
4142 assert(stride
< (1 << 14));
4144 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
4145 base_ring
, v2i64
, "");
4146 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4147 ring
, ctx
->ac
.i32_0
, "");
4148 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
4149 LLVMConstInt(ctx
->ac
.i64
,
4150 stream_offset
, 0), "");
4151 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
4152 ring
, tmp
, ctx
->ac
.i32_0
, "");
4154 stream_offset
+= stride
* 64;
4156 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
4159 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
4161 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
4162 LLVMConstInt(ctx
->ac
.i32
,
4163 S_008F04_STRIDE(stride
), false), "");
4164 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
4167 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
4168 LLVMConstInt(ctx
->ac
.i32
,
4169 num_records
, false),
4170 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
4172 ctx
->gsvs_ring
[stream
] = ring
;
4176 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
4177 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4178 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
4179 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
4184 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
4185 const struct nir_shader
*nir
)
4187 switch (nir
->info
.stage
) {
4188 case MESA_SHADER_TESS_CTRL
:
4189 return chip_class
>= GFX7
? 128 : 64;
4190 case MESA_SHADER_GEOMETRY
:
4191 return chip_class
>= GFX9
? 128 : 64;
4192 case MESA_SHADER_COMPUTE
:
4198 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
4199 nir
->info
.cs
.local_size
[1] *
4200 nir
->info
.cs
.local_size
[2];
4201 return max_workgroup_size
;
4204 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
4205 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
4207 LLVMValueRef count
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
4208 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
4210 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
4211 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
4212 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
4215 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
4217 for(int i
= 5; i
>= 0; --i
) {
4218 ctx
->gs_vtx_offset
[i
] = ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
4222 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 16, 8);
4227 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
4228 struct nir_shader
*const *shaders
,
4230 struct radv_shader_variant_info
*shader_info
,
4231 const struct radv_nir_compiler_options
*options
)
4233 struct radv_shader_context ctx
= {0};
4235 ctx
.options
= options
;
4236 ctx
.shader_info
= shader_info
;
4238 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
4239 ctx
.context
= ctx
.ac
.context
;
4240 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
4242 enum ac_float_mode float_mode
=
4243 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
4244 AC_FLOAT_MODE_DEFAULT
;
4246 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
4248 radv_nir_shader_info_init(&shader_info
->info
);
4250 for(int i
= 0; i
< shader_count
; ++i
)
4251 radv_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
4253 for (i
= 0; i
< RADV_UD_MAX_SETS
; i
++)
4254 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
4255 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
4256 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
4258 ctx
.max_workgroup_size
= 0;
4259 for (int i
= 0; i
< shader_count
; ++i
) {
4260 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
4261 radv_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
4265 if (ctx
.ac
.chip_class
>= GFX10
) {
4266 if (is_pre_gs_stage(shaders
[0]->info
.stage
) &&
4267 options
->key
.vs_common_out
.as_ngg
) {
4268 ctx
.max_workgroup_size
= 128;
4272 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
4273 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
4275 ctx
.abi
.inputs
= &ctx
.inputs
[0];
4276 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
4277 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
4278 ctx
.abi
.load_ubo
= radv_load_ubo
;
4279 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
4280 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
4281 ctx
.abi
.load_resource
= radv_load_resource
;
4282 ctx
.abi
.clamp_shadow_reference
= false;
4283 ctx
.abi
.gfx9_stride_size_workaround
= ctx
.ac
.chip_class
== GFX9
&& HAVE_LLVM
< 0x800;
4285 /* Because the new raw/struct atomic intrinsics are buggy with LLVM 8,
4286 * we fallback to the old intrinsics for atomic buffer image operations
4287 * and thus we need to apply the indexing workaround...
4289 ctx
.abi
.gfx9_stride_size_workaround_for_atomic
= ctx
.ac
.chip_class
== GFX9
&& HAVE_LLVM
< 0x900;
4291 bool is_ngg
= is_pre_gs_stage(shaders
[0]->info
.stage
) && ctx
.options
->key
.vs_common_out
.as_ngg
;
4292 if (shader_count
>= 2 || is_ngg
)
4293 ac_init_exec_full_mask(&ctx
.ac
);
4295 if ((ctx
.ac
.family
== CHIP_VEGA10
||
4296 ctx
.ac
.family
== CHIP_RAVEN
) &&
4297 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
4298 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
4300 for(int i
= 0; i
< shader_count
; ++i
) {
4301 ctx
.stage
= shaders
[i
]->info
.stage
;
4302 ctx
.output_mask
= 0;
4304 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4305 for (int i
= 0; i
< 4; i
++) {
4306 ctx
.gs_next_vertex
[i
] =
4307 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4309 if (ctx
.options
->key
.vs_common_out
.as_ngg
) {
4310 for (unsigned i
= 0; i
< 4; ++i
) {
4311 ctx
.gs_curprim_verts
[i
] =
4312 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4313 ctx
.gs_generated_prims
[i
] =
4314 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4317 /* TODO: streamout */
4319 LLVMTypeRef ai32
= LLVMArrayType(ctx
.ac
.i32
, 8);
4320 ctx
.gs_ngg_scratch
=
4321 LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4322 ai32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4323 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(ai32
));
4324 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4326 ctx
.gs_ngg_emit
= LLVMBuildIntToPtr(ctx
.ac
.builder
, ctx
.ac
.i32_0
,
4327 LLVMPointerType(LLVMArrayType(ctx
.ac
.i32
, 0), AC_ADDR_SPACE_LDS
),
4329 LLVMSetAlignment(ctx
.gs_ngg_emit
, 4);
4332 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
4333 ctx
.gs_output_prim
= shaders
[i
]->info
.gs
.output_primitive
;
4334 ctx
.abi
.load_inputs
= load_gs_input
;
4335 ctx
.abi
.emit_primitive
= visit_end_primitive
;
4336 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4337 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
4338 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
4339 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
4340 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4341 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
4342 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
4343 if (shader_count
== 1)
4344 ctx
.tcs_num_inputs
= ctx
.options
->key
.tcs
.num_inputs
;
4346 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->info
.vs
.ls_outputs_written
);
4347 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
4348 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4349 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
4350 ctx
.abi
.load_tess_varyings
= load_tes_input
;
4351 ctx
.abi
.load_tess_coord
= load_tess_coord
;
4352 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4353 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
4354 ctx
.tcs_num_patches
= ctx
.options
->key
.tes
.num_patches
;
4355 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
4356 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
4357 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
4358 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
4359 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
4360 ctx
.abi
.load_sample_position
= load_sample_position
;
4361 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
4362 ctx
.abi
.emit_kill
= radv_emit_kill
;
4366 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
4368 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
4369 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
4371 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4372 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
4373 shaders
[i
]->info
.cull_distance_array_size
> 4;
4374 ctx
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
4375 ctx
.max_gsvs_emit_size
= ctx
.gsvs_vertex_size
*
4376 shaders
[i
]->info
.gs
.vertices_out
;
4379 ac_setup_rings(&ctx
);
4381 LLVMBasicBlockRef merge_block
;
4382 if (shader_count
>= 2 || is_ngg
) {
4384 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4385 ctx
.options
->key
.vs_common_out
.as_ngg
) {
4386 gfx10_ngg_gs_emit_prologue(&ctx
);
4389 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
4390 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4391 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4393 LLVMValueRef count
= ac_unpack_param(&ctx
.ac
, ctx
.merged_wave_info
, 8 * i
, 8);
4394 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
4395 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
4396 thread_id
, count
, "");
4397 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
4399 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
4402 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
4403 prepare_interp_optimize(&ctx
, shaders
[i
]);
4404 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
4405 handle_vs_inputs(&ctx
, shaders
[i
]);
4406 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
4407 prepare_gs_input_vgprs(&ctx
);
4409 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
4411 if (shader_count
>= 2 || is_ngg
) {
4412 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
4413 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
4416 /* This needs to be outside the if wrapping the shader body, as sometimes
4417 * the HW generates waves with 0 es/vs threads. */
4418 if (is_pre_gs_stage(shaders
[i
]->info
.stage
) &&
4419 ctx
.options
->key
.vs_common_out
.as_ngg
&&
4420 i
== shader_count
- 1) {
4421 handle_ngg_outputs_post(&ctx
);
4422 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4423 ctx
.options
->key
.vs_common_out
.as_ngg
) {
4424 gfx10_ngg_gs_emit_epilogue_2(&ctx
);
4427 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4428 shader_info
->gs
.gsvs_vertex_size
= ctx
.gsvs_vertex_size
;
4429 shader_info
->gs
.max_gsvs_emit_size
= ctx
.max_gsvs_emit_size
;
4430 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4431 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
4432 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
4436 LLVMBuildRetVoid(ctx
.ac
.builder
);
4438 if (options
->dump_preoptir
)
4439 ac_dump_module(ctx
.ac
.module
);
4441 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
4443 if (shader_count
== 1)
4444 ac_nir_eliminate_const_vs_outputs(&ctx
);
4446 if (options
->dump_shader
) {
4447 ctx
.shader_info
->private_mem_vgprs
=
4448 ac_count_scratch_private_memory(ctx
.main_function
);
4451 return ctx
.ac
.module
;
4454 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
4456 unsigned *retval
= (unsigned *)context
;
4457 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
4458 char *description
= LLVMGetDiagInfoDescription(di
);
4460 if (severity
== LLVMDSError
) {
4462 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
4466 LLVMDisposeMessage(description
);
4469 static unsigned radv_llvm_compile(LLVMModuleRef M
,
4470 char **pelf_buffer
, size_t *pelf_size
,
4471 struct ac_llvm_compiler
*ac_llvm
)
4473 unsigned retval
= 0;
4474 LLVMContextRef llvm_ctx
;
4476 /* Setup Diagnostic Handler*/
4477 llvm_ctx
= LLVMGetModuleContext(M
);
4479 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
4483 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
4488 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
4489 LLVMModuleRef llvm_module
,
4490 struct radv_shader_binary
**rbinary
,
4491 struct radv_shader_variant_info
*shader_info
,
4492 gl_shader_stage stage
,
4493 const struct radv_nir_compiler_options
*options
)
4495 char *elf_buffer
= NULL
;
4496 size_t elf_size
= 0;
4497 char *llvm_ir_string
= NULL
;
4498 if (options
->dump_shader
)
4499 ac_dump_module(llvm_module
);
4501 if (options
->record_llvm_ir
) {
4502 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
4503 llvm_ir_string
= strdup(llvm_ir
);
4504 LLVMDisposeMessage(llvm_ir
);
4507 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
4509 fprintf(stderr
, "compile failed\n");
4512 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
4513 LLVMDisposeModule(llvm_module
);
4514 LLVMContextDispose(ctx
);
4516 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
4517 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
4518 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
4519 memcpy(rbin
->data
, elf_buffer
, elf_size
);
4521 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
4523 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
4524 rbin
->base
.stage
= stage
;
4525 rbin
->base
.total_size
= alloc_size
;
4526 rbin
->elf_size
= elf_size
;
4527 rbin
->llvm_ir_size
= llvm_ir_size
;
4528 *rbinary
= &rbin
->base
;
4530 free(llvm_ir_string
);
4535 ac_fill_shader_info(struct radv_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct radv_nir_compiler_options
*options
)
4537 switch (nir
->info
.stage
) {
4538 case MESA_SHADER_COMPUTE
:
4539 for (int i
= 0; i
< 3; ++i
)
4540 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
4542 case MESA_SHADER_FRAGMENT
:
4543 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
4545 case MESA_SHADER_GEOMETRY
:
4546 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
4547 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
4548 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
4549 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
4551 case MESA_SHADER_TESS_EVAL
:
4552 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
4553 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
4554 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
4555 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
4556 shader_info
->tes
.as_es
= options
->key
.vs_common_out
.as_es
;
4557 shader_info
->tes
.export_prim_id
= options
->key
.vs_common_out
.export_prim_id
;
4558 shader_info
->is_ngg
= options
->key
.vs_common_out
.as_ngg
;
4560 case MESA_SHADER_TESS_CTRL
:
4561 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
4563 case MESA_SHADER_VERTEX
:
4564 shader_info
->vs
.as_es
= options
->key
.vs_common_out
.as_es
;
4565 shader_info
->vs
.as_ls
= options
->key
.vs_common_out
.as_ls
;
4566 shader_info
->vs
.export_prim_id
= options
->key
.vs_common_out
.export_prim_id
;
4567 shader_info
->is_ngg
= options
->key
.vs_common_out
.as_ngg
;
4575 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
4576 struct radv_shader_binary
**rbinary
,
4577 struct radv_shader_variant_info
*shader_info
,
4578 struct nir_shader
*const *nir
,
4580 const struct radv_nir_compiler_options
*options
)
4583 LLVMModuleRef llvm_module
;
4585 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, shader_info
,
4588 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
, shader_info
,
4589 nir
[nir_count
- 1]->info
.stage
, options
);
4591 for (int i
= 0; i
< nir_count
; ++i
)
4592 ac_fill_shader_info(shader_info
, nir
[i
], options
);
4594 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4595 if (options
->chip_class
>= GFX9
) {
4596 if (nir_count
== 2 &&
4597 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4598 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
4604 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
4606 LLVMValueRef vtx_offset
=
4607 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
4608 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4609 LLVMValueRef stream_id
;
4611 /* Fetch the vertex stream ID. */
4612 if (ctx
->shader_info
->info
.so
.num_outputs
) {
4614 ac_unpack_param(&ctx
->ac
, ctx
->streamout_config
, 24, 2);
4616 stream_id
= ctx
->ac
.i32_0
;
4619 LLVMBasicBlockRef end_bb
;
4620 LLVMValueRef switch_inst
;
4622 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
4623 ctx
->main_function
, "end");
4624 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
4626 for (unsigned stream
= 0; stream
< 4; stream
++) {
4627 unsigned num_components
=
4628 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
4629 LLVMBasicBlockRef bb
;
4632 if (!num_components
)
4635 if (stream
> 0 && !ctx
->shader_info
->info
.so
.num_outputs
)
4638 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
4639 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
4640 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
4643 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4644 unsigned output_usage_mask
=
4645 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
4646 unsigned output_stream
=
4647 ctx
->shader_info
->info
.gs
.output_streams
[i
];
4648 int length
= util_last_bit(output_usage_mask
);
4650 if (!(ctx
->output_mask
& (1ull << i
)) ||
4651 output_stream
!= stream
)
4654 for (unsigned j
= 0; j
< length
; j
++) {
4655 LLVMValueRef value
, soffset
;
4657 if (!(output_usage_mask
& (1 << j
)))
4660 soffset
= LLVMConstInt(ctx
->ac
.i32
,
4662 ctx
->gs_max_out_vertices
* 16 * 4, false);
4666 value
= ac_build_buffer_load(&ctx
->ac
,
4669 vtx_offset
, soffset
,
4670 0, ac_glc
| ac_slc
, true, false);
4672 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4673 if (ac_get_type_size(type
) == 2) {
4674 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
4675 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
4678 LLVMBuildStore(ctx
->ac
.builder
,
4679 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4683 if (ctx
->shader_info
->info
.so
.num_outputs
)
4684 radv_emit_streamout(ctx
, stream
);
4687 handle_vs_outputs_post(ctx
, false, true,
4688 &ctx
->shader_info
->vs
.outinfo
);
4691 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
4694 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
4698 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
4699 struct nir_shader
*geom_shader
,
4700 struct radv_shader_binary
**rbinary
,
4701 struct radv_shader_variant_info
*shader_info
,
4702 const struct radv_nir_compiler_options
*options
)
4704 struct radv_shader_context ctx
= {0};
4705 ctx
.options
= options
;
4706 ctx
.shader_info
= shader_info
;
4708 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
4709 ctx
.context
= ctx
.ac
.context
;
4710 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
4712 ctx
.is_gs_copy_shader
= true;
4714 enum ac_float_mode float_mode
=
4715 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
4716 AC_FLOAT_MODE_DEFAULT
;
4718 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
4719 ctx
.stage
= MESA_SHADER_VERTEX
;
4721 radv_nir_shader_info_pass(geom_shader
, options
, &shader_info
->info
);
4723 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
4725 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
4726 ac_setup_rings(&ctx
);
4728 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
4729 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
4730 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
4731 variable
, MESA_SHADER_VERTEX
);
4734 ac_gs_copy_shader_emit(&ctx
);
4736 LLVMBuildRetVoid(ctx
.ac
.builder
);
4738 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
4740 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
, shader_info
,
4741 MESA_SHADER_VERTEX
, options
);
4742 (*rbinary
)->is_gs_copy_shader
= true;