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[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "nir/nir.h"
31
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35 #if HAVE_LLVM >= 0x0700
36 #include <llvm-c/Transforms/Utils.h>
37 #endif
38
39 #include "sid.h"
40 #include "gfx9d.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_llvm_build.h"
44 #include "ac_shader_abi.h"
45 #include "ac_shader_util.h"
46 #include "ac_exp_param.h"
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct radv_shader_context {
51 struct ac_llvm_context ac;
52 const struct radv_nir_compiler_options *options;
53 struct radv_shader_variant_info *shader_info;
54 struct ac_shader_abi abi;
55
56 unsigned max_workgroup_size;
57 LLVMContextRef context;
58 LLVMValueRef main_function;
59
60 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
61 LLVMValueRef ring_offsets;
62
63 LLVMValueRef vertex_buffers;
64 LLVMValueRef rel_auto_id;
65 LLVMValueRef vs_prim_id;
66 LLVMValueRef es2gs_offset;
67
68 LLVMValueRef oc_lds;
69 LLVMValueRef merged_wave_info;
70 LLVMValueRef tess_factor_offset;
71 LLVMValueRef tes_rel_patch_id;
72 LLVMValueRef tes_u;
73 LLVMValueRef tes_v;
74
75 LLVMValueRef gs2vs_offset;
76 LLVMValueRef gs_wave_id;
77 LLVMValueRef gs_vtx_offset[6];
78
79 LLVMValueRef esgs_ring;
80 LLVMValueRef gsvs_ring;
81 LLVMValueRef hs_ring_tess_offchip;
82 LLVMValueRef hs_ring_tess_factor;
83
84 LLVMValueRef sample_pos_offset;
85 LLVMValueRef persp_sample, persp_center, persp_centroid;
86 LLVMValueRef linear_sample, linear_center, linear_centroid;
87
88 gl_shader_stage stage;
89
90 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
91
92 uint64_t input_mask;
93 uint64_t output_mask;
94 uint8_t num_output_clips;
95 uint8_t num_output_culls;
96
97 bool is_gs_copy_shader;
98 LLVMValueRef gs_next_vertex;
99 unsigned gs_max_out_vertices;
100
101 unsigned tes_primitive_mode;
102
103 uint32_t tcs_patch_outputs_read;
104 uint64_t tcs_outputs_read;
105 uint32_t tcs_vertices_per_patch;
106 uint32_t tcs_num_inputs;
107 uint32_t tcs_num_patches;
108 uint32_t max_gsvs_emit_size;
109 uint32_t gsvs_vertex_size;
110 };
111
112 enum radeon_llvm_calling_convention {
113 RADEON_LLVM_AMDGPU_VS = 87,
114 RADEON_LLVM_AMDGPU_GS = 88,
115 RADEON_LLVM_AMDGPU_PS = 89,
116 RADEON_LLVM_AMDGPU_CS = 90,
117 RADEON_LLVM_AMDGPU_HS = 93,
118 };
119
120 static inline struct radv_shader_context *
121 radv_shader_context_from_abi(struct ac_shader_abi *abi)
122 {
123 struct radv_shader_context *ctx = NULL;
124 return container_of(abi, ctx, abi);
125 }
126
127 struct ac_build_if_state
128 {
129 struct radv_shader_context *ctx;
130 LLVMValueRef condition;
131 LLVMBasicBlockRef entry_block;
132 LLVMBasicBlockRef true_block;
133 LLVMBasicBlockRef false_block;
134 LLVMBasicBlockRef merge_block;
135 };
136
137 static LLVMBasicBlockRef
138 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
139 {
140 LLVMBasicBlockRef current_block;
141 LLVMBasicBlockRef next_block;
142 LLVMBasicBlockRef new_block;
143
144 /* get current basic block */
145 current_block = LLVMGetInsertBlock(ctx->ac.builder);
146
147 /* chqeck if there's another block after this one */
148 next_block = LLVMGetNextBasicBlock(current_block);
149 if (next_block) {
150 /* insert the new block before the next block */
151 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
152 }
153 else {
154 /* append new block after current block */
155 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
156 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
157 }
158 return new_block;
159 }
160
161 static void
162 ac_nir_build_if(struct ac_build_if_state *ifthen,
163 struct radv_shader_context *ctx,
164 LLVMValueRef condition)
165 {
166 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
167
168 memset(ifthen, 0, sizeof *ifthen);
169 ifthen->ctx = ctx;
170 ifthen->condition = condition;
171 ifthen->entry_block = block;
172
173 /* create endif/merge basic block for the phi functions */
174 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
175
176 /* create/insert true_block before merge_block */
177 ifthen->true_block =
178 LLVMInsertBasicBlockInContext(ctx->context,
179 ifthen->merge_block,
180 "if-true-block");
181
182 /* successive code goes into the true block */
183 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
184 }
185
186 /**
187 * End a conditional.
188 */
189 static void
190 ac_nir_build_endif(struct ac_build_if_state *ifthen)
191 {
192 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
193
194 /* Insert branch to the merge block from current block */
195 LLVMBuildBr(builder, ifthen->merge_block);
196
197 /*
198 * Now patch in the various branch instructions.
199 */
200
201 /* Insert the conditional branch instruction at the end of entry_block */
202 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
203 if (ifthen->false_block) {
204 /* we have an else clause */
205 LLVMBuildCondBr(builder, ifthen->condition,
206 ifthen->true_block, ifthen->false_block);
207 }
208 else {
209 /* no else clause */
210 LLVMBuildCondBr(builder, ifthen->condition,
211 ifthen->true_block, ifthen->merge_block);
212 }
213
214 /* Resume building code at end of the ifthen->merge_block */
215 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
216 }
217
218
219 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
220 {
221 switch (ctx->stage) {
222 case MESA_SHADER_TESS_CTRL:
223 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
224 case MESA_SHADER_TESS_EVAL:
225 return ctx->tes_rel_patch_id;
226 break;
227 default:
228 unreachable("Illegal stage");
229 }
230 }
231
232 static unsigned
233 get_tcs_num_patches(struct radv_shader_context *ctx)
234 {
235 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
236 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
237 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
238 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
239 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
240 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
241 uint32_t output_vertex_size = num_tcs_outputs * 16;
242 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
243 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
244 unsigned num_patches;
245 unsigned hardware_lds_size;
246
247 /* Ensure that we only need one wave per SIMD so we don't need to check
248 * resource usage. Also ensures that the number of tcs in and out
249 * vertices per threadgroup are at most 256.
250 */
251 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
252 /* Make sure that the data fits in LDS. This assumes the shaders only
253 * use LDS for the inputs and outputs.
254 */
255 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
256 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
257 /* Make sure the output data fits in the offchip buffer */
258 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
259 /* Not necessary for correctness, but improves performance. The
260 * specific value is taken from the proprietary driver.
261 */
262 num_patches = MIN2(num_patches, 40);
263
264 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
265 if (ctx->options->chip_class == SI) {
266 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
267 num_patches = MIN2(num_patches, one_wave);
268 }
269 return num_patches;
270 }
271
272 static unsigned
273 calculate_tess_lds_size(struct radv_shader_context *ctx)
274 {
275 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
276 unsigned num_tcs_output_cp;
277 unsigned num_tcs_outputs, num_tcs_patch_outputs;
278 unsigned input_vertex_size, output_vertex_size;
279 unsigned input_patch_size, output_patch_size;
280 unsigned pervertex_output_patch_size;
281 unsigned output_patch0_offset;
282 unsigned num_patches;
283 unsigned lds_size;
284
285 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
286 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
287 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
288
289 input_vertex_size = ctx->tcs_num_inputs * 16;
290 output_vertex_size = num_tcs_outputs * 16;
291
292 input_patch_size = num_tcs_input_cp * input_vertex_size;
293
294 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
295 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
296
297 num_patches = ctx->tcs_num_patches;
298 output_patch0_offset = input_patch_size * num_patches;
299
300 lds_size = output_patch0_offset + output_patch_size * num_patches;
301 return lds_size;
302 }
303
304 /* Tessellation shaders pass outputs to the next shader using LDS.
305 *
306 * LS outputs = TCS inputs
307 * TCS outputs = TES inputs
308 *
309 * The LDS layout is:
310 * - TCS inputs for patch 0
311 * - TCS inputs for patch 1
312 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
313 * - ...
314 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
315 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
316 * - TCS outputs for patch 1
317 * - Per-patch TCS outputs for patch 1
318 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
319 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
320 * - ...
321 *
322 * All three shaders VS(LS), TCS, TES share the same LDS space.
323 */
324 static LLVMValueRef
325 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
326 {
327 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
328 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
329 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
330
331 input_patch_size /= 4;
332 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
333 }
334
335 static LLVMValueRef
336 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
337 {
338 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
339 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
340 uint32_t output_vertex_size = num_tcs_outputs * 16;
341 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
342 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
343 output_patch_size /= 4;
344 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
345 }
346
347 static LLVMValueRef
348 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
349 {
350 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
351 uint32_t output_vertex_size = num_tcs_outputs * 16;
352 output_vertex_size /= 4;
353 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
354 }
355
356 static LLVMValueRef
357 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
358 {
359 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
360 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
361 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
362 uint32_t output_patch0_offset = input_patch_size;
363 unsigned num_patches = ctx->tcs_num_patches;
364
365 output_patch0_offset *= num_patches;
366 output_patch0_offset /= 4;
367 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
368 }
369
370 static LLVMValueRef
371 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
372 {
373 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
374 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
375 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
376 uint32_t output_patch0_offset = input_patch_size;
377
378 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
379 uint32_t output_vertex_size = num_tcs_outputs * 16;
380 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
381 unsigned num_patches = ctx->tcs_num_patches;
382
383 output_patch0_offset *= num_patches;
384 output_patch0_offset += pervertex_output_patch_size;
385 output_patch0_offset /= 4;
386 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
387 }
388
389 static LLVMValueRef
390 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
391 {
392 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
393 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
394
395 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
396 }
397
398 static LLVMValueRef
399 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
400 {
401 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
402 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
403 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
404
405 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
406 LLVMBuildMul(ctx->ac.builder, patch_stride,
407 rel_patch_id, ""),
408 "");
409 }
410
411 static LLVMValueRef
412 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
413 {
414 LLVMValueRef patch0_patch_data_offset =
415 get_tcs_out_patch0_patch_data_offset(ctx);
416 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
417 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
418
419 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
420 LLVMBuildMul(ctx->ac.builder, patch_stride,
421 rel_patch_id, ""),
422 "");
423 }
424
425 #define MAX_ARGS 23
426 struct arg_info {
427 LLVMTypeRef types[MAX_ARGS];
428 LLVMValueRef *assign[MAX_ARGS];
429 unsigned array_params_mask;
430 uint8_t count;
431 uint8_t sgpr_count;
432 uint8_t num_sgprs_used;
433 uint8_t num_vgprs_used;
434 };
435
436 enum ac_arg_regfile {
437 ARG_SGPR,
438 ARG_VGPR,
439 };
440
441 static void
442 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
443 LLVMValueRef *param_ptr)
444 {
445 assert(info->count < MAX_ARGS);
446
447 info->assign[info->count] = param_ptr;
448 info->types[info->count] = type;
449 info->count++;
450
451 if (regfile == ARG_SGPR) {
452 info->num_sgprs_used += ac_get_type_size(type) / 4;
453 info->sgpr_count++;
454 } else {
455 assert(regfile == ARG_VGPR);
456 info->num_vgprs_used += ac_get_type_size(type) / 4;
457 }
458 }
459
460 static inline void
461 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
462 {
463 info->array_params_mask |= (1 << info->count);
464 add_arg(info, ARG_SGPR, type, param_ptr);
465 }
466
467 static void assign_arguments(LLVMValueRef main_function,
468 struct arg_info *info)
469 {
470 unsigned i;
471 for (i = 0; i < info->count; i++) {
472 if (info->assign[i])
473 *info->assign[i] = LLVMGetParam(main_function, i);
474 }
475 }
476
477 static LLVMValueRef
478 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
479 LLVMBuilderRef builder, LLVMTypeRef *return_types,
480 unsigned num_return_elems,
481 struct arg_info *args,
482 unsigned max_workgroup_size,
483 const struct radv_nir_compiler_options *options)
484 {
485 LLVMTypeRef main_function_type, ret_type;
486 LLVMBasicBlockRef main_function_body;
487
488 if (num_return_elems)
489 ret_type = LLVMStructTypeInContext(ctx, return_types,
490 num_return_elems, true);
491 else
492 ret_type = LLVMVoidTypeInContext(ctx);
493
494 /* Setup the function */
495 main_function_type =
496 LLVMFunctionType(ret_type, args->types, args->count, 0);
497 LLVMValueRef main_function =
498 LLVMAddFunction(module, "main", main_function_type);
499 main_function_body =
500 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
501 LLVMPositionBuilderAtEnd(builder, main_function_body);
502
503 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
504 for (unsigned i = 0; i < args->sgpr_count; ++i) {
505 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
506
507 if (args->array_params_mask & (1 << i)) {
508 LLVMValueRef P = LLVMGetParam(main_function, i);
509 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
510 ac_add_attr_dereferenceable(P, UINT64_MAX);
511 }
512 }
513
514 if (options->address32_hi) {
515 ac_llvm_add_target_dep_function_attr(main_function,
516 "amdgpu-32bit-address-high-bits",
517 options->address32_hi);
518 }
519
520 if (max_workgroup_size) {
521 ac_llvm_add_target_dep_function_attr(main_function,
522 "amdgpu-max-work-group-size",
523 max_workgroup_size);
524 }
525 if (options->unsafe_math) {
526 /* These were copied from some LLVM test. */
527 LLVMAddTargetDependentFunctionAttr(main_function,
528 "less-precise-fpmad",
529 "true");
530 LLVMAddTargetDependentFunctionAttr(main_function,
531 "no-infs-fp-math",
532 "true");
533 LLVMAddTargetDependentFunctionAttr(main_function,
534 "no-nans-fp-math",
535 "true");
536 LLVMAddTargetDependentFunctionAttr(main_function,
537 "unsafe-fp-math",
538 "true");
539 LLVMAddTargetDependentFunctionAttr(main_function,
540 "no-signed-zeros-fp-math",
541 "true");
542 }
543 return main_function;
544 }
545
546
547 static void
548 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
549 uint32_t indirect_offset)
550 {
551 ud_info->sgpr_idx = *sgpr_idx;
552 ud_info->num_sgprs = num_sgprs;
553 ud_info->indirect = indirect_offset > 0;
554 ud_info->indirect_offset = indirect_offset;
555 *sgpr_idx += num_sgprs;
556 }
557
558 static void
559 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
560 uint8_t num_sgprs)
561 {
562 struct radv_userdata_info *ud_info =
563 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
564 assert(ud_info);
565
566 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
567 }
568
569 static void
570 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
571 {
572 bool use_32bit_pointers = HAVE_32BIT_POINTERS &&
573 idx != AC_UD_SCRATCH_RING_OFFSETS;
574
575 set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
576 }
577
578 static void
579 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
580 uint32_t indirect_offset)
581 {
582 struct radv_userdata_info *ud_info =
583 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
584 assert(ud_info);
585
586 set_loc(ud_info, sgpr_idx, HAVE_32BIT_POINTERS ? 1 : 2, indirect_offset);
587 }
588
589 struct user_sgpr_info {
590 bool need_ring_offsets;
591 bool indirect_all_descriptor_sets;
592 };
593
594 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
595 gl_shader_stage stage)
596 {
597 switch (stage) {
598 case MESA_SHADER_VERTEX:
599 if (ctx->shader_info->info.needs_multiview_view_index ||
600 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
601 return true;
602 break;
603 case MESA_SHADER_TESS_EVAL:
604 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
605 return true;
606 break;
607 case MESA_SHADER_GEOMETRY:
608 case MESA_SHADER_TESS_CTRL:
609 if (ctx->shader_info->info.needs_multiview_view_index)
610 return true;
611 break;
612 default:
613 break;
614 }
615 return false;
616 }
617
618 static uint8_t
619 count_vs_user_sgprs(struct radv_shader_context *ctx)
620 {
621 uint8_t count = 0;
622
623 if (ctx->shader_info->info.vs.has_vertex_buffers)
624 count += HAVE_32BIT_POINTERS ? 1 : 2;
625 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
626
627 return count;
628 }
629
630 static void allocate_user_sgprs(struct radv_shader_context *ctx,
631 gl_shader_stage stage,
632 bool has_previous_stage,
633 gl_shader_stage previous_stage,
634 bool needs_view_index,
635 struct user_sgpr_info *user_sgpr_info)
636 {
637 uint8_t user_sgpr_count = 0;
638
639 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
640
641 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
642 if (stage == MESA_SHADER_GEOMETRY ||
643 stage == MESA_SHADER_VERTEX ||
644 stage == MESA_SHADER_TESS_CTRL ||
645 stage == MESA_SHADER_TESS_EVAL ||
646 ctx->is_gs_copy_shader)
647 user_sgpr_info->need_ring_offsets = true;
648
649 if (stage == MESA_SHADER_FRAGMENT &&
650 ctx->shader_info->info.ps.needs_sample_positions)
651 user_sgpr_info->need_ring_offsets = true;
652
653 /* 2 user sgprs will nearly always be allocated for scratch/rings */
654 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
655 user_sgpr_count += 2;
656 }
657
658 switch (stage) {
659 case MESA_SHADER_COMPUTE:
660 if (ctx->shader_info->info.cs.uses_grid_size)
661 user_sgpr_count += 3;
662 break;
663 case MESA_SHADER_FRAGMENT:
664 user_sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
665 break;
666 case MESA_SHADER_VERTEX:
667 if (!ctx->is_gs_copy_shader)
668 user_sgpr_count += count_vs_user_sgprs(ctx);
669 break;
670 case MESA_SHADER_TESS_CTRL:
671 if (has_previous_stage) {
672 if (previous_stage == MESA_SHADER_VERTEX)
673 user_sgpr_count += count_vs_user_sgprs(ctx);
674 }
675 break;
676 case MESA_SHADER_TESS_EVAL:
677 break;
678 case MESA_SHADER_GEOMETRY:
679 if (has_previous_stage) {
680 if (previous_stage == MESA_SHADER_VERTEX) {
681 user_sgpr_count += count_vs_user_sgprs(ctx);
682 }
683 }
684 break;
685 default:
686 break;
687 }
688
689 if (needs_view_index)
690 user_sgpr_count++;
691
692 if (ctx->shader_info->info.loads_push_constants)
693 user_sgpr_count += HAVE_32BIT_POINTERS ? 1 : 2;
694
695 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
696 uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
697 uint32_t num_desc_set =
698 util_bitcount(ctx->shader_info->info.desc_set_used_mask);
699
700 if (remaining_sgprs / (HAVE_32BIT_POINTERS ? 1 : 2) < num_desc_set) {
701 user_sgpr_info->indirect_all_descriptor_sets = true;
702 }
703 }
704
705 static void
706 declare_global_input_sgprs(struct radv_shader_context *ctx,
707 gl_shader_stage stage,
708 bool has_previous_stage,
709 gl_shader_stage previous_stage,
710 const struct user_sgpr_info *user_sgpr_info,
711 struct arg_info *args,
712 LLVMValueRef *desc_sets)
713 {
714 LLVMTypeRef type = ac_array_in_const32_addr_space(ctx->ac.i8);
715 unsigned num_sets = ctx->options->layout ?
716 ctx->options->layout->num_sets : 0;
717 unsigned stage_mask = 1 << stage;
718
719 if (has_previous_stage)
720 stage_mask |= 1 << previous_stage;
721
722 /* 1 for each descriptor set */
723 if (!user_sgpr_info->indirect_all_descriptor_sets) {
724 for (unsigned i = 0; i < num_sets; ++i) {
725 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
726 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
727 add_array_arg(args, type,
728 &ctx->descriptor_sets[i]);
729 }
730 }
731 } else {
732 add_array_arg(args, ac_array_in_const32_addr_space(type), desc_sets);
733 }
734
735 if (ctx->shader_info->info.loads_push_constants) {
736 /* 1 for push constants and dynamic descriptors */
737 add_array_arg(args, type, &ctx->abi.push_constants);
738 }
739 }
740
741 static void
742 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
743 gl_shader_stage stage,
744 bool has_previous_stage,
745 gl_shader_stage previous_stage,
746 struct arg_info *args)
747 {
748 if (!ctx->is_gs_copy_shader &&
749 (stage == MESA_SHADER_VERTEX ||
750 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
751 if (ctx->shader_info->info.vs.has_vertex_buffers) {
752 add_arg(args, ARG_SGPR,
753 ac_array_in_const32_addr_space(ctx->ac.v4i32),
754 &ctx->vertex_buffers);
755 }
756 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
757 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
758 if (ctx->shader_info->info.vs.needs_draw_id) {
759 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
760 }
761 }
762 }
763
764 static void
765 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
766 {
767 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
768 if (!ctx->is_gs_copy_shader) {
769 if (ctx->options->key.vs.as_ls) {
770 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
771 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
772 } else {
773 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
774 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
775 }
776 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
777 }
778 }
779
780 static void
781 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
782 {
783 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
784 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
785 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
786 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
787 }
788
789 static void
790 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
791 bool has_previous_stage, gl_shader_stage previous_stage,
792 const struct user_sgpr_info *user_sgpr_info,
793 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
794 {
795 unsigned num_sets = ctx->options->layout ?
796 ctx->options->layout->num_sets : 0;
797 unsigned stage_mask = 1 << stage;
798
799 if (has_previous_stage)
800 stage_mask |= 1 << previous_stage;
801
802 if (!user_sgpr_info->indirect_all_descriptor_sets) {
803 for (unsigned i = 0; i < num_sets; ++i) {
804 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
805 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
806 set_loc_desc(ctx, i, user_sgpr_idx, 0);
807 } else
808 ctx->descriptor_sets[i] = NULL;
809 }
810 } else {
811 set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
812 user_sgpr_idx);
813
814 for (unsigned i = 0; i < num_sets; ++i) {
815 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
816 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
817 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
818 ctx->descriptor_sets[i] =
819 ac_build_load_to_sgpr(&ctx->ac,
820 desc_sets,
821 LLVMConstInt(ctx->ac.i32, i, false));
822
823 } else
824 ctx->descriptor_sets[i] = NULL;
825 }
826 ctx->shader_info->need_indirect_descriptor_sets = true;
827 }
828
829 if (ctx->shader_info->info.loads_push_constants) {
830 set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
831 }
832 }
833
834 static void
835 set_vs_specific_input_locs(struct radv_shader_context *ctx,
836 gl_shader_stage stage, bool has_previous_stage,
837 gl_shader_stage previous_stage,
838 uint8_t *user_sgpr_idx)
839 {
840 if (!ctx->is_gs_copy_shader &&
841 (stage == MESA_SHADER_VERTEX ||
842 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
843 if (ctx->shader_info->info.vs.has_vertex_buffers) {
844 set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
845 user_sgpr_idx);
846 }
847
848 unsigned vs_num = 2;
849 if (ctx->shader_info->info.vs.needs_draw_id)
850 vs_num++;
851
852 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
853 user_sgpr_idx, vs_num);
854 }
855 }
856
857 static void set_llvm_calling_convention(LLVMValueRef func,
858 gl_shader_stage stage)
859 {
860 enum radeon_llvm_calling_convention calling_conv;
861
862 switch (stage) {
863 case MESA_SHADER_VERTEX:
864 case MESA_SHADER_TESS_EVAL:
865 calling_conv = RADEON_LLVM_AMDGPU_VS;
866 break;
867 case MESA_SHADER_GEOMETRY:
868 calling_conv = RADEON_LLVM_AMDGPU_GS;
869 break;
870 case MESA_SHADER_TESS_CTRL:
871 calling_conv = RADEON_LLVM_AMDGPU_HS;
872 break;
873 case MESA_SHADER_FRAGMENT:
874 calling_conv = RADEON_LLVM_AMDGPU_PS;
875 break;
876 case MESA_SHADER_COMPUTE:
877 calling_conv = RADEON_LLVM_AMDGPU_CS;
878 break;
879 default:
880 unreachable("Unhandle shader type");
881 }
882
883 LLVMSetFunctionCallConv(func, calling_conv);
884 }
885
886 static void create_function(struct radv_shader_context *ctx,
887 gl_shader_stage stage,
888 bool has_previous_stage,
889 gl_shader_stage previous_stage)
890 {
891 uint8_t user_sgpr_idx;
892 struct user_sgpr_info user_sgpr_info;
893 struct arg_info args = {};
894 LLVMValueRef desc_sets;
895 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
896 allocate_user_sgprs(ctx, stage, has_previous_stage,
897 previous_stage, needs_view_index, &user_sgpr_info);
898
899 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
900 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
901 &ctx->ring_offsets);
902 }
903
904 switch (stage) {
905 case MESA_SHADER_COMPUTE:
906 declare_global_input_sgprs(ctx, stage, has_previous_stage,
907 previous_stage, &user_sgpr_info,
908 &args, &desc_sets);
909
910 if (ctx->shader_info->info.cs.uses_grid_size) {
911 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
912 &ctx->abi.num_work_groups);
913 }
914
915 for (int i = 0; i < 3; i++) {
916 ctx->abi.workgroup_ids[i] = NULL;
917 if (ctx->shader_info->info.cs.uses_block_id[i]) {
918 add_arg(&args, ARG_SGPR, ctx->ac.i32,
919 &ctx->abi.workgroup_ids[i]);
920 }
921 }
922
923 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
924 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
925 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
926 &ctx->abi.local_invocation_ids);
927 break;
928 case MESA_SHADER_VERTEX:
929 declare_global_input_sgprs(ctx, stage, has_previous_stage,
930 previous_stage, &user_sgpr_info,
931 &args, &desc_sets);
932 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
933 previous_stage, &args);
934
935 if (needs_view_index)
936 add_arg(&args, ARG_SGPR, ctx->ac.i32,
937 &ctx->abi.view_index);
938 if (ctx->options->key.vs.as_es)
939 add_arg(&args, ARG_SGPR, ctx->ac.i32,
940 &ctx->es2gs_offset);
941
942 declare_vs_input_vgprs(ctx, &args);
943 break;
944 case MESA_SHADER_TESS_CTRL:
945 if (has_previous_stage) {
946 // First 6 system regs
947 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
948 add_arg(&args, ARG_SGPR, ctx->ac.i32,
949 &ctx->merged_wave_info);
950 add_arg(&args, ARG_SGPR, ctx->ac.i32,
951 &ctx->tess_factor_offset);
952
953 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
954 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
955 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
956
957 declare_global_input_sgprs(ctx, stage,
958 has_previous_stage,
959 previous_stage,
960 &user_sgpr_info, &args,
961 &desc_sets);
962 declare_vs_specific_input_sgprs(ctx, stage,
963 has_previous_stage,
964 previous_stage, &args);
965
966 if (needs_view_index)
967 add_arg(&args, ARG_SGPR, ctx->ac.i32,
968 &ctx->abi.view_index);
969
970 add_arg(&args, ARG_VGPR, ctx->ac.i32,
971 &ctx->abi.tcs_patch_id);
972 add_arg(&args, ARG_VGPR, ctx->ac.i32,
973 &ctx->abi.tcs_rel_ids);
974
975 declare_vs_input_vgprs(ctx, &args);
976 } else {
977 declare_global_input_sgprs(ctx, stage,
978 has_previous_stage,
979 previous_stage,
980 &user_sgpr_info, &args,
981 &desc_sets);
982
983 if (needs_view_index)
984 add_arg(&args, ARG_SGPR, ctx->ac.i32,
985 &ctx->abi.view_index);
986
987 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
988 add_arg(&args, ARG_SGPR, ctx->ac.i32,
989 &ctx->tess_factor_offset);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->abi.tcs_patch_id);
992 add_arg(&args, ARG_VGPR, ctx->ac.i32,
993 &ctx->abi.tcs_rel_ids);
994 }
995 break;
996 case MESA_SHADER_TESS_EVAL:
997 declare_global_input_sgprs(ctx, stage, has_previous_stage,
998 previous_stage, &user_sgpr_info,
999 &args, &desc_sets);
1000
1001 if (needs_view_index)
1002 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1003 &ctx->abi.view_index);
1004
1005 if (ctx->options->key.tes.as_es) {
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1007 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1008 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1009 &ctx->es2gs_offset);
1010 } else {
1011 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1012 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1013 }
1014 declare_tes_input_vgprs(ctx, &args);
1015 break;
1016 case MESA_SHADER_GEOMETRY:
1017 if (has_previous_stage) {
1018 // First 6 system regs
1019 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1020 &ctx->gs2vs_offset);
1021 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1022 &ctx->merged_wave_info);
1023 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1024
1025 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1026 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1027 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1028
1029 declare_global_input_sgprs(ctx, stage,
1030 has_previous_stage,
1031 previous_stage,
1032 &user_sgpr_info, &args,
1033 &desc_sets);
1034
1035 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1036 declare_vs_specific_input_sgprs(ctx, stage,
1037 has_previous_stage,
1038 previous_stage,
1039 &args);
1040 }
1041
1042 if (needs_view_index)
1043 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1044 &ctx->abi.view_index);
1045
1046 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1047 &ctx->gs_vtx_offset[0]);
1048 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1049 &ctx->gs_vtx_offset[2]);
1050 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1051 &ctx->abi.gs_prim_id);
1052 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1053 &ctx->abi.gs_invocation_id);
1054 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1055 &ctx->gs_vtx_offset[4]);
1056
1057 if (previous_stage == MESA_SHADER_VERTEX) {
1058 declare_vs_input_vgprs(ctx, &args);
1059 } else {
1060 declare_tes_input_vgprs(ctx, &args);
1061 }
1062 } else {
1063 declare_global_input_sgprs(ctx, stage,
1064 has_previous_stage,
1065 previous_stage,
1066 &user_sgpr_info, &args,
1067 &desc_sets);
1068
1069 if (needs_view_index)
1070 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1071 &ctx->abi.view_index);
1072
1073 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1074 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1075 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1076 &ctx->gs_vtx_offset[0]);
1077 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1078 &ctx->gs_vtx_offset[1]);
1079 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1080 &ctx->abi.gs_prim_id);
1081 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1082 &ctx->gs_vtx_offset[2]);
1083 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1084 &ctx->gs_vtx_offset[3]);
1085 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1086 &ctx->gs_vtx_offset[4]);
1087 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1088 &ctx->gs_vtx_offset[5]);
1089 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1090 &ctx->abi.gs_invocation_id);
1091 }
1092 break;
1093 case MESA_SHADER_FRAGMENT:
1094 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1095 previous_stage, &user_sgpr_info,
1096 &args, &desc_sets);
1097
1098 if (ctx->shader_info->info.ps.needs_sample_positions)
1099 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1100 &ctx->sample_pos_offset);
1101
1102 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1103 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1104 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1105 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1106 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1107 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1108 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1109 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1110 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1111 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1112 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1113 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1114 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1115 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1116 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1117 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1118 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1119 break;
1120 default:
1121 unreachable("Shader stage not implemented");
1122 }
1123
1124 ctx->main_function = create_llvm_function(
1125 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1126 ctx->max_workgroup_size, ctx->options);
1127 set_llvm_calling_convention(ctx->main_function, stage);
1128
1129
1130 ctx->shader_info->num_input_vgprs = 0;
1131 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1132
1133 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1134
1135 if (ctx->stage != MESA_SHADER_FRAGMENT)
1136 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1137
1138 assign_arguments(ctx->main_function, &args);
1139
1140 user_sgpr_idx = 0;
1141
1142 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1143 set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1144 &user_sgpr_idx);
1145 if (ctx->options->supports_spill) {
1146 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1147 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1148 NULL, 0, AC_FUNC_ATTR_READNONE);
1149 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1150 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1151 }
1152 }
1153
1154 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1155 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1156 if (has_previous_stage)
1157 user_sgpr_idx = 0;
1158
1159 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1160 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1161
1162 switch (stage) {
1163 case MESA_SHADER_COMPUTE:
1164 if (ctx->shader_info->info.cs.uses_grid_size) {
1165 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1166 &user_sgpr_idx, 3);
1167 }
1168 break;
1169 case MESA_SHADER_VERTEX:
1170 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1171 previous_stage, &user_sgpr_idx);
1172 if (ctx->abi.view_index)
1173 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1174 break;
1175 case MESA_SHADER_TESS_CTRL:
1176 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1177 previous_stage, &user_sgpr_idx);
1178 if (ctx->abi.view_index)
1179 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1180 break;
1181 case MESA_SHADER_TESS_EVAL:
1182 if (ctx->abi.view_index)
1183 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1184 break;
1185 case MESA_SHADER_GEOMETRY:
1186 if (has_previous_stage) {
1187 if (previous_stage == MESA_SHADER_VERTEX)
1188 set_vs_specific_input_locs(ctx, stage,
1189 has_previous_stage,
1190 previous_stage,
1191 &user_sgpr_idx);
1192 }
1193 if (ctx->abi.view_index)
1194 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1195 break;
1196 case MESA_SHADER_FRAGMENT:
1197 if (ctx->shader_info->info.ps.needs_sample_positions) {
1198 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1199 &user_sgpr_idx, 1);
1200 }
1201 break;
1202 default:
1203 unreachable("Shader stage not implemented");
1204 }
1205
1206 if (stage == MESA_SHADER_TESS_CTRL ||
1207 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1208 /* GFX9 has the ESGS ring buffer in LDS. */
1209 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1210 ac_declare_lds_as_pointer(&ctx->ac);
1211 }
1212
1213 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1214 }
1215
1216
1217 static LLVMValueRef
1218 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1219 unsigned desc_set, unsigned binding)
1220 {
1221 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1222 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1223 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1224 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1225 unsigned base_offset = layout->binding[binding].offset;
1226 LLVMValueRef offset, stride;
1227
1228 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1229 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1230 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1231 layout->binding[binding].dynamic_offset_offset;
1232 desc_ptr = ctx->abi.push_constants;
1233 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1234 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1235 } else
1236 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1237
1238 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1239 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
1240 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
1241
1242 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1243 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1244 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1245
1246 return desc_ptr;
1247 }
1248
1249
1250 /* The offchip buffer layout for TCS->TES is
1251 *
1252 * - attribute 0 of patch 0 vertex 0
1253 * - attribute 0 of patch 0 vertex 1
1254 * - attribute 0 of patch 0 vertex 2
1255 * ...
1256 * - attribute 0 of patch 1 vertex 0
1257 * - attribute 0 of patch 1 vertex 1
1258 * ...
1259 * - attribute 1 of patch 0 vertex 0
1260 * - attribute 1 of patch 0 vertex 1
1261 * ...
1262 * - per patch attribute 0 of patch 0
1263 * - per patch attribute 0 of patch 1
1264 * ...
1265 *
1266 * Note that every attribute has 4 components.
1267 */
1268 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1269 {
1270 uint32_t num_patches = ctx->tcs_num_patches;
1271 uint32_t num_tcs_outputs;
1272 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1273 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1274 else
1275 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1276
1277 uint32_t output_vertex_size = num_tcs_outputs * 16;
1278 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1279
1280 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1281 }
1282
1283 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1284 LLVMValueRef vertex_index)
1285 {
1286 LLVMValueRef param_stride;
1287 if (vertex_index)
1288 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1289 else
1290 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1291 return param_stride;
1292 }
1293
1294 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1295 LLVMValueRef vertex_index,
1296 LLVMValueRef param_index)
1297 {
1298 LLVMValueRef base_addr;
1299 LLVMValueRef param_stride, constant16;
1300 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1301 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1302 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1303 param_stride = calc_param_stride(ctx, vertex_index);
1304 if (vertex_index) {
1305 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
1306 vertices_per_patch, "");
1307
1308 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1309 vertex_index, "");
1310 } else {
1311 base_addr = rel_patch_id;
1312 }
1313
1314 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1315 LLVMBuildMul(ctx->ac.builder, param_index,
1316 param_stride, ""), "");
1317
1318 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1319
1320 if (!vertex_index) {
1321 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1322
1323 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1324 patch_data_offset, "");
1325 }
1326 return base_addr;
1327 }
1328
1329 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1330 unsigned param,
1331 unsigned const_index,
1332 bool is_compact,
1333 LLVMValueRef vertex_index,
1334 LLVMValueRef indir_index)
1335 {
1336 LLVMValueRef param_index;
1337
1338 if (indir_index)
1339 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1340 indir_index, "");
1341 else {
1342 if (const_index && !is_compact)
1343 param += const_index;
1344 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1345 }
1346 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1347 }
1348
1349 static LLVMValueRef
1350 get_dw_address(struct radv_shader_context *ctx,
1351 LLVMValueRef dw_addr,
1352 unsigned param,
1353 unsigned const_index,
1354 bool compact_const_index,
1355 LLVMValueRef vertex_index,
1356 LLVMValueRef stride,
1357 LLVMValueRef indir_index)
1358
1359 {
1360
1361 if (vertex_index) {
1362 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1363 LLVMBuildMul(ctx->ac.builder,
1364 vertex_index,
1365 stride, ""), "");
1366 }
1367
1368 if (indir_index)
1369 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1370 LLVMBuildMul(ctx->ac.builder, indir_index,
1371 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1372 else if (const_index && !compact_const_index)
1373 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1374 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1375
1376 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1377 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1378
1379 if (const_index && compact_const_index)
1380 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1381 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1382 return dw_addr;
1383 }
1384
1385 static LLVMValueRef
1386 load_tcs_varyings(struct ac_shader_abi *abi,
1387 LLVMTypeRef type,
1388 LLVMValueRef vertex_index,
1389 LLVMValueRef indir_index,
1390 unsigned const_index,
1391 unsigned location,
1392 unsigned driver_location,
1393 unsigned component,
1394 unsigned num_components,
1395 bool is_patch,
1396 bool is_compact,
1397 bool load_input)
1398 {
1399 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1400 LLVMValueRef dw_addr, stride;
1401 LLVMValueRef value[4], result;
1402 unsigned param = shader_io_get_unique_index(location);
1403
1404 if (load_input) {
1405 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1406 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1407 dw_addr = get_tcs_in_current_patch_offset(ctx);
1408 } else {
1409 if (!is_patch) {
1410 stride = get_tcs_out_vertex_stride(ctx);
1411 dw_addr = get_tcs_out_current_patch_offset(ctx);
1412 } else {
1413 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1414 stride = NULL;
1415 }
1416 }
1417
1418 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1419 indir_index);
1420
1421 for (unsigned i = 0; i < num_components + component; i++) {
1422 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1423 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1424 ctx->ac.i32_1, "");
1425 }
1426 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1427 return result;
1428 }
1429
1430 static void
1431 store_tcs_output(struct ac_shader_abi *abi,
1432 const nir_variable *var,
1433 LLVMValueRef vertex_index,
1434 LLVMValueRef param_index,
1435 unsigned const_index,
1436 LLVMValueRef src,
1437 unsigned writemask)
1438 {
1439 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1440 const unsigned location = var->data.location;
1441 const unsigned component = var->data.location_frac;
1442 const bool is_patch = var->data.patch;
1443 const bool is_compact = var->data.compact;
1444 LLVMValueRef dw_addr;
1445 LLVMValueRef stride = NULL;
1446 LLVMValueRef buf_addr = NULL;
1447 unsigned param;
1448 bool store_lds = true;
1449
1450 if (is_patch) {
1451 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1452 store_lds = false;
1453 } else {
1454 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1455 store_lds = false;
1456 }
1457
1458 param = shader_io_get_unique_index(location);
1459 if (location == VARYING_SLOT_CLIP_DIST0 &&
1460 is_compact && const_index > 3) {
1461 const_index -= 3;
1462 param++;
1463 }
1464
1465 if (!is_patch) {
1466 stride = get_tcs_out_vertex_stride(ctx);
1467 dw_addr = get_tcs_out_current_patch_offset(ctx);
1468 } else {
1469 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1470 }
1471
1472 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1473 param_index);
1474 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1475 vertex_index, param_index);
1476
1477 bool is_tess_factor = false;
1478 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1479 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1480 is_tess_factor = true;
1481
1482 unsigned base = is_compact ? const_index : 0;
1483 for (unsigned chan = 0; chan < 8; chan++) {
1484 if (!(writemask & (1 << chan)))
1485 continue;
1486 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1487
1488 if (store_lds || is_tess_factor) {
1489 LLVMValueRef dw_addr_chan =
1490 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1491 LLVMConstInt(ctx->ac.i32, chan, false), "");
1492 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1493 }
1494
1495 if (!is_tess_factor && writemask != 0xF)
1496 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1497 buf_addr, ctx->oc_lds,
1498 4 * (base + chan), 1, 0, true, false);
1499 }
1500
1501 if (writemask == 0xF) {
1502 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1503 buf_addr, ctx->oc_lds,
1504 (base * 4), 1, 0, true, false);
1505 }
1506 }
1507
1508 static LLVMValueRef
1509 load_tes_input(struct ac_shader_abi *abi,
1510 LLVMTypeRef type,
1511 LLVMValueRef vertex_index,
1512 LLVMValueRef param_index,
1513 unsigned const_index,
1514 unsigned location,
1515 unsigned driver_location,
1516 unsigned component,
1517 unsigned num_components,
1518 bool is_patch,
1519 bool is_compact,
1520 bool load_input)
1521 {
1522 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1523 LLVMValueRef buf_addr;
1524 LLVMValueRef result;
1525 unsigned param = shader_io_get_unique_index(location);
1526
1527 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1528 const_index -= 3;
1529 param++;
1530 }
1531
1532 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1533 is_compact, vertex_index, param_index);
1534
1535 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1536 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1537
1538 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1539 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1540 result = ac_trim_vector(&ctx->ac, result, num_components);
1541 return result;
1542 }
1543
1544 static LLVMValueRef
1545 load_gs_input(struct ac_shader_abi *abi,
1546 unsigned location,
1547 unsigned driver_location,
1548 unsigned component,
1549 unsigned num_components,
1550 unsigned vertex_index,
1551 unsigned const_index,
1552 LLVMTypeRef type)
1553 {
1554 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1555 LLVMValueRef vtx_offset;
1556 unsigned param, vtx_offset_param;
1557 LLVMValueRef value[4], result;
1558
1559 vtx_offset_param = vertex_index;
1560 assert(vtx_offset_param < 6);
1561 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1562 LLVMConstInt(ctx->ac.i32, 4, false), "");
1563
1564 param = shader_io_get_unique_index(location);
1565
1566 for (unsigned i = component; i < num_components + component; i++) {
1567 if (ctx->ac.chip_class >= GFX9) {
1568 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1569 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1570 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1571 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1572 } else {
1573 LLVMValueRef soffset =
1574 LLVMConstInt(ctx->ac.i32,
1575 (param * 4 + i + const_index) * 256,
1576 false);
1577
1578 value[i] = ac_build_buffer_load(&ctx->ac,
1579 ctx->esgs_ring, 1,
1580 ctx->ac.i32_0,
1581 vtx_offset, soffset,
1582 0, 1, 0, true, false);
1583
1584 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
1585 type, "");
1586 }
1587 }
1588 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1589 result = ac_to_integer(&ctx->ac, result);
1590 return result;
1591 }
1592
1593
1594 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1595 {
1596 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1597 ac_build_kill_if_false(&ctx->ac, visible);
1598 }
1599
1600 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1601 enum glsl_interp_mode interp, unsigned location)
1602 {
1603 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1604
1605 switch (interp) {
1606 case INTERP_MODE_FLAT:
1607 default:
1608 return NULL;
1609 case INTERP_MODE_SMOOTH:
1610 case INTERP_MODE_NONE:
1611 if (location == INTERP_CENTER)
1612 return ctx->persp_center;
1613 else if (location == INTERP_CENTROID)
1614 return ctx->persp_centroid;
1615 else if (location == INTERP_SAMPLE)
1616 return ctx->persp_sample;
1617 break;
1618 case INTERP_MODE_NOPERSPECTIVE:
1619 if (location == INTERP_CENTER)
1620 return ctx->linear_center;
1621 else if (location == INTERP_CENTROID)
1622 return ctx->linear_centroid;
1623 else if (location == INTERP_SAMPLE)
1624 return ctx->linear_sample;
1625 break;
1626 }
1627 return NULL;
1628 }
1629
1630 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1631 LLVMValueRef sample_id)
1632 {
1633 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1634
1635 LLVMValueRef result;
1636 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1637
1638 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1639 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1640
1641 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
1642 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1643
1644 return result;
1645 }
1646
1647
1648 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1649 {
1650 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1651 uint8_t log2_ps_iter_samples;
1652
1653 if (ctx->shader_info->info.ps.force_persample) {
1654 log2_ps_iter_samples =
1655 util_logbase2(ctx->options->key.fs.num_samples);
1656 } else {
1657 log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
1658 }
1659
1660 /* The bit pattern matches that used by fixed function fragment
1661 * processing. */
1662 static const uint16_t ps_iter_masks[] = {
1663 0xffff, /* not used */
1664 0x5555,
1665 0x1111,
1666 0x0101,
1667 0x0001,
1668 };
1669 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1670
1671 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1672
1673 LLVMValueRef result, sample_id;
1674 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1675 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1676 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1677 return result;
1678 }
1679
1680
1681 static void
1682 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1683 {
1684 LLVMValueRef gs_next_vertex;
1685 LLVMValueRef can_emit;
1686 int idx;
1687 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1688
1689 assert(stream == 0);
1690
1691 /* Write vertex attribute values to GSVS ring */
1692 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1693 ctx->gs_next_vertex,
1694 "");
1695
1696 /* If this thread has already emitted the declared maximum number of
1697 * vertices, kill it: excessive vertex emissions are not supposed to
1698 * have any effect, and GS threads have no externally observable
1699 * effects other than emitting vertices.
1700 */
1701 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1702 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1703 ac_build_kill_if_false(&ctx->ac, can_emit);
1704
1705 /* loop num outputs */
1706 idx = 0;
1707 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1708 unsigned output_usage_mask =
1709 ctx->shader_info->info.gs.output_usage_mask[i];
1710 LLVMValueRef *out_ptr = &addrs[i * 4];
1711 int length = 4;
1712 int slot = idx;
1713 int slot_inc = 1;
1714
1715 if (!(ctx->output_mask & (1ull << i)))
1716 continue;
1717
1718 if (i == VARYING_SLOT_CLIP_DIST0) {
1719 /* pack clip and cull into a single set of slots */
1720 length = ctx->num_output_clips + ctx->num_output_culls;
1721 if (length > 4)
1722 slot_inc = 2;
1723 output_usage_mask = (1 << length) - 1;
1724 }
1725
1726 for (unsigned j = 0; j < length; j++) {
1727 if (!(output_usage_mask & (1 << j)))
1728 continue;
1729
1730 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1731 out_ptr[j], "");
1732 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1733 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1734 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1735
1736 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1737
1738 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1739 out_val, 1,
1740 voffset, ctx->gs2vs_offset, 0,
1741 1, 1, true, true);
1742 }
1743 idx += slot_inc;
1744 }
1745
1746 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1747 ctx->ac.i32_1, "");
1748 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1749
1750 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1751 }
1752
1753 static void
1754 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1755 {
1756 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1757 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1758 }
1759
1760 static LLVMValueRef
1761 load_tess_coord(struct ac_shader_abi *abi)
1762 {
1763 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1764
1765 LLVMValueRef coord[4] = {
1766 ctx->tes_u,
1767 ctx->tes_v,
1768 ctx->ac.f32_0,
1769 ctx->ac.f32_0,
1770 };
1771
1772 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1773 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1774 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1775
1776 return ac_build_gather_values(&ctx->ac, coord, 3);
1777 }
1778
1779 static LLVMValueRef
1780 load_patch_vertices_in(struct ac_shader_abi *abi)
1781 {
1782 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1783 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1784 }
1785
1786
1787 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1788 {
1789 return abi->base_vertex;
1790 }
1791
1792 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1793 LLVMValueRef buffer_ptr, bool write)
1794 {
1795 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1796 LLVMValueRef result;
1797
1798 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1799
1800 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1801 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1802
1803 return result;
1804 }
1805
1806 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1807 {
1808 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1809 LLVMValueRef result;
1810
1811 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1812
1813 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1814 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1815
1816 return result;
1817 }
1818
1819 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1820 unsigned descriptor_set,
1821 unsigned base_index,
1822 unsigned constant_index,
1823 LLVMValueRef index,
1824 enum ac_descriptor_type desc_type,
1825 bool image, bool write,
1826 bool bindless)
1827 {
1828 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1829 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1830 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1831 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1832 unsigned offset = binding->offset;
1833 unsigned stride = binding->size;
1834 unsigned type_size;
1835 LLVMBuilderRef builder = ctx->ac.builder;
1836 LLVMTypeRef type;
1837
1838 assert(base_index < layout->binding_count);
1839
1840 switch (desc_type) {
1841 case AC_DESC_IMAGE:
1842 type = ctx->ac.v8i32;
1843 type_size = 32;
1844 break;
1845 case AC_DESC_FMASK:
1846 type = ctx->ac.v8i32;
1847 offset += 32;
1848 type_size = 32;
1849 break;
1850 case AC_DESC_SAMPLER:
1851 type = ctx->ac.v4i32;
1852 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1853 offset += 64;
1854
1855 type_size = 16;
1856 break;
1857 case AC_DESC_BUFFER:
1858 type = ctx->ac.v4i32;
1859 type_size = 16;
1860 break;
1861 default:
1862 unreachable("invalid desc_type\n");
1863 }
1864
1865 offset += constant_index * stride;
1866
1867 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1868 (!index || binding->immutable_samplers_equal)) {
1869 if (binding->immutable_samplers_equal)
1870 constant_index = 0;
1871
1872 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1873
1874 LLVMValueRef constants[] = {
1875 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1876 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1877 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1878 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1879 };
1880 return ac_build_gather_values(&ctx->ac, constants, 4);
1881 }
1882
1883 assert(stride % type_size == 0);
1884
1885 if (!index)
1886 index = ctx->ac.i32_0;
1887
1888 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1889
1890 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1891 list = LLVMBuildPointerCast(builder, list,
1892 ac_array_in_const32_addr_space(type), "");
1893
1894 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1895 }
1896
1897 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1898 * so we may need to fix it up. */
1899 static LLVMValueRef
1900 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1901 unsigned adjustment,
1902 LLVMValueRef alpha)
1903 {
1904 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1905 return alpha;
1906
1907 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1908
1909 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1910 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1911 else
1912 alpha = ac_to_integer(&ctx->ac, alpha);
1913
1914 /* For the integer-like cases, do a natural sign extension.
1915 *
1916 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1917 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1918 * exponent.
1919 */
1920 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1921 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1922 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1923 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1924
1925 /* Convert back to the right type. */
1926 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1927 LLVMValueRef clamp;
1928 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1929 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1930 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1931 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1932 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1933 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1934 }
1935
1936 return alpha;
1937 }
1938
1939 static void
1940 handle_vs_input_decl(struct radv_shader_context *ctx,
1941 struct nir_variable *variable)
1942 {
1943 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1944 LLVMValueRef t_offset;
1945 LLVMValueRef t_list;
1946 LLVMValueRef input;
1947 LLVMValueRef buffer_index;
1948 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1949 uint8_t input_usage_mask =
1950 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1951 unsigned num_channels = util_last_bit(input_usage_mask);
1952
1953 variable->data.driver_location = variable->data.location * 4;
1954
1955 for (unsigned i = 0; i < attrib_count; ++i) {
1956 LLVMValueRef output[4];
1957 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1958
1959 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1960 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
1961
1962 if (divisor) {
1963 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
1964 ctx->abi.start_instance, "");
1965
1966 if (divisor != 1) {
1967 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1968 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1969 }
1970
1971 if (ctx->options->key.vs.as_ls) {
1972 ctx->shader_info->vs.vgpr_comp_cnt =
1973 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1974 } else {
1975 ctx->shader_info->vs.vgpr_comp_cnt =
1976 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1977 }
1978 } else {
1979 buffer_index = ctx->ac.i32_0;
1980 }
1981 } else
1982 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
1983 ctx->abi.base_vertex, "");
1984 t_offset = LLVMConstInt(ctx->ac.i32, attrib_index, false);
1985
1986 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1987
1988 input = ac_build_buffer_load_format(&ctx->ac, t_list,
1989 buffer_index,
1990 ctx->ac.i32_0,
1991 num_channels, false, true);
1992
1993 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
1994
1995 for (unsigned chan = 0; chan < 4; chan++) {
1996 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1997 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1998 }
1999
2000 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
2001 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
2002
2003 for (unsigned chan = 0; chan < 4; chan++) {
2004 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] =
2005 ac_to_integer(&ctx->ac, output[chan]);
2006 }
2007 }
2008 }
2009
2010 static void interp_fs_input(struct radv_shader_context *ctx,
2011 unsigned attr,
2012 LLVMValueRef interp_param,
2013 LLVMValueRef prim_mask,
2014 LLVMValueRef result[4])
2015 {
2016 LLVMValueRef attr_number;
2017 unsigned chan;
2018 LLVMValueRef i, j;
2019 bool interp = interp_param != NULL;
2020
2021 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
2022
2023 /* fs.constant returns the param from the middle vertex, so it's not
2024 * really useful for flat shading. It's meant to be used for custom
2025 * interpolation (but the intrinsic can't fetch from the other two
2026 * vertices).
2027 *
2028 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2029 * to do the right thing. The only reason we use fs.constant is that
2030 * fs.interp cannot be used on integers, because they can be equal
2031 * to NaN.
2032 */
2033 if (interp) {
2034 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
2035 ctx->ac.v2f32, "");
2036
2037 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2038 ctx->ac.i32_0, "");
2039 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2040 ctx->ac.i32_1, "");
2041 }
2042
2043 for (chan = 0; chan < 4; chan++) {
2044 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2045
2046 if (interp) {
2047 result[chan] = ac_build_fs_interp(&ctx->ac,
2048 llvm_chan,
2049 attr_number,
2050 prim_mask, i, j);
2051 } else {
2052 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2053 LLVMConstInt(ctx->ac.i32, 2, false),
2054 llvm_chan,
2055 attr_number,
2056 prim_mask);
2057 }
2058 }
2059 }
2060
2061 static void
2062 handle_fs_input_decl(struct radv_shader_context *ctx,
2063 struct nir_variable *variable)
2064 {
2065 int idx = variable->data.location;
2066 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2067 LLVMValueRef interp;
2068
2069 variable->data.driver_location = idx * 4;
2070 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
2071
2072 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
2073 unsigned interp_type;
2074 if (variable->data.sample)
2075 interp_type = INTERP_SAMPLE;
2076 else if (variable->data.centroid)
2077 interp_type = INTERP_CENTROID;
2078 else
2079 interp_type = INTERP_CENTER;
2080
2081 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
2082 } else
2083 interp = NULL;
2084
2085 for (unsigned i = 0; i < attrib_count; ++i)
2086 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
2087
2088 }
2089
2090 static void
2091 handle_vs_inputs(struct radv_shader_context *ctx,
2092 struct nir_shader *nir) {
2093 nir_foreach_variable(variable, &nir->inputs)
2094 handle_vs_input_decl(ctx, variable);
2095 }
2096
2097 static void
2098 prepare_interp_optimize(struct radv_shader_context *ctx,
2099 struct nir_shader *nir)
2100 {
2101 bool uses_center = false;
2102 bool uses_centroid = false;
2103 nir_foreach_variable(variable, &nir->inputs) {
2104 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2105 variable->data.sample)
2106 continue;
2107
2108 if (variable->data.centroid)
2109 uses_centroid = true;
2110 else
2111 uses_center = true;
2112 }
2113
2114 if (uses_center && uses_centroid) {
2115 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2116 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
2117 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
2118 }
2119 }
2120
2121 static void
2122 handle_fs_inputs(struct radv_shader_context *ctx,
2123 struct nir_shader *nir)
2124 {
2125 prepare_interp_optimize(ctx, nir);
2126
2127 nir_foreach_variable(variable, &nir->inputs)
2128 handle_fs_input_decl(ctx, variable);
2129
2130 unsigned index = 0;
2131
2132 if (ctx->shader_info->info.ps.uses_input_attachments ||
2133 ctx->shader_info->info.needs_multiview_view_index)
2134 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
2135
2136 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
2137 LLVMValueRef interp_param;
2138 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
2139
2140 if (!(ctx->input_mask & (1ull << i)))
2141 continue;
2142
2143 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
2144 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
2145 interp_param = *inputs;
2146 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
2147 inputs);
2148
2149 if (!interp_param)
2150 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
2151 ++index;
2152 } else if (i == VARYING_SLOT_POS) {
2153 for(int i = 0; i < 3; ++i)
2154 inputs[i] = ctx->abi.frag_pos[i];
2155
2156 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2157 ctx->abi.frag_pos[3]);
2158 }
2159 }
2160 ctx->shader_info->fs.num_interp = index;
2161 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
2162
2163 if (ctx->shader_info->info.needs_multiview_view_index)
2164 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2165 }
2166
2167 static void
2168 scan_shader_output_decl(struct radv_shader_context *ctx,
2169 struct nir_variable *variable,
2170 struct nir_shader *shader,
2171 gl_shader_stage stage)
2172 {
2173 int idx = variable->data.location + variable->data.index;
2174 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2175 uint64_t mask_attribs;
2176
2177 variable->data.driver_location = idx * 4;
2178
2179 /* tess ctrl has it's own load/store paths for outputs */
2180 if (stage == MESA_SHADER_TESS_CTRL)
2181 return;
2182
2183 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2184 if (stage == MESA_SHADER_VERTEX ||
2185 stage == MESA_SHADER_TESS_EVAL ||
2186 stage == MESA_SHADER_GEOMETRY) {
2187 if (idx == VARYING_SLOT_CLIP_DIST0) {
2188 int length = shader->info.clip_distance_array_size +
2189 shader->info.cull_distance_array_size;
2190 if (stage == MESA_SHADER_VERTEX) {
2191 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2192 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2193 }
2194 if (stage == MESA_SHADER_TESS_EVAL) {
2195 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2196 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2197 }
2198
2199 if (length > 4)
2200 attrib_count = 2;
2201 else
2202 attrib_count = 1;
2203 mask_attribs = 1ull << idx;
2204 }
2205 }
2206
2207 ctx->output_mask |= mask_attribs;
2208 }
2209
2210
2211 /* Initialize arguments for the shader export intrinsic */
2212 static void
2213 si_llvm_init_export_args(struct radv_shader_context *ctx,
2214 LLVMValueRef *values,
2215 unsigned enabled_channels,
2216 unsigned target,
2217 struct ac_export_args *args)
2218 {
2219 /* Specify the channels that are enabled. */
2220 args->enabled_channels = enabled_channels;
2221
2222 /* Specify whether the EXEC mask represents the valid mask */
2223 args->valid_mask = 0;
2224
2225 /* Specify whether this is the last export */
2226 args->done = 0;
2227
2228 /* Specify the target we are exporting */
2229 args->target = target;
2230
2231 args->compr = false;
2232 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2233 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2234 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2235 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2236
2237 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2238 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2239 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2240 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2241 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2242 unsigned chan;
2243
2244 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2245 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2246 unsigned bits, bool hi) = NULL;
2247
2248 switch(col_format) {
2249 case V_028714_SPI_SHADER_ZERO:
2250 args->enabled_channels = 0; /* writemask */
2251 args->target = V_008DFC_SQ_EXP_NULL;
2252 break;
2253
2254 case V_028714_SPI_SHADER_32_R:
2255 args->enabled_channels = 1;
2256 args->out[0] = values[0];
2257 break;
2258
2259 case V_028714_SPI_SHADER_32_GR:
2260 args->enabled_channels = 0x3;
2261 args->out[0] = values[0];
2262 args->out[1] = values[1];
2263 break;
2264
2265 case V_028714_SPI_SHADER_32_AR:
2266 args->enabled_channels = 0x9;
2267 args->out[0] = values[0];
2268 args->out[3] = values[3];
2269 break;
2270
2271 case V_028714_SPI_SHADER_FP16_ABGR:
2272 args->enabled_channels = 0x5;
2273 packf = ac_build_cvt_pkrtz_f16;
2274 break;
2275
2276 case V_028714_SPI_SHADER_UNORM16_ABGR:
2277 args->enabled_channels = 0x5;
2278 packf = ac_build_cvt_pknorm_u16;
2279 break;
2280
2281 case V_028714_SPI_SHADER_SNORM16_ABGR:
2282 args->enabled_channels = 0x5;
2283 packf = ac_build_cvt_pknorm_i16;
2284 break;
2285
2286 case V_028714_SPI_SHADER_UINT16_ABGR:
2287 args->enabled_channels = 0x5;
2288 packi = ac_build_cvt_pk_u16;
2289 break;
2290
2291 case V_028714_SPI_SHADER_SINT16_ABGR:
2292 args->enabled_channels = 0x5;
2293 packi = ac_build_cvt_pk_i16;
2294 break;
2295
2296 default:
2297 case V_028714_SPI_SHADER_32_ABGR:
2298 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2299 break;
2300 }
2301
2302 /* Pack f16 or norm_i16/u16. */
2303 if (packf) {
2304 for (chan = 0; chan < 2; chan++) {
2305 LLVMValueRef pack_args[2] = {
2306 values[2 * chan],
2307 values[2 * chan + 1]
2308 };
2309 LLVMValueRef packed;
2310
2311 packed = packf(&ctx->ac, pack_args);
2312 args->out[chan] = ac_to_float(&ctx->ac, packed);
2313 }
2314 args->compr = 1; /* COMPR flag */
2315 }
2316
2317 /* Pack i16/u16. */
2318 if (packi) {
2319 for (chan = 0; chan < 2; chan++) {
2320 LLVMValueRef pack_args[2] = {
2321 ac_to_integer(&ctx->ac, values[2 * chan]),
2322 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2323 };
2324 LLVMValueRef packed;
2325
2326 packed = packi(&ctx->ac, pack_args,
2327 is_int8 ? 8 : is_int10 ? 10 : 16,
2328 chan == 1);
2329 args->out[chan] = ac_to_float(&ctx->ac, packed);
2330 }
2331 args->compr = 1; /* COMPR flag */
2332 }
2333 return;
2334 }
2335
2336 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2337
2338 for (unsigned i = 0; i < 4; ++i) {
2339 if (!(args->enabled_channels & (1 << i)))
2340 continue;
2341
2342 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2343 }
2344 }
2345
2346 static void
2347 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2348 LLVMValueRef *values, unsigned enabled_channels)
2349 {
2350 struct ac_export_args args;
2351
2352 si_llvm_init_export_args(ctx, values, enabled_channels,
2353 V_008DFC_SQ_EXP_PARAM + index, &args);
2354 ac_build_export(&ctx->ac, &args);
2355 }
2356
2357 static LLVMValueRef
2358 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2359 {
2360 LLVMValueRef output =
2361 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2362
2363 return LLVMBuildLoad(ctx->ac.builder, output, "");
2364 }
2365
2366 static void
2367 handle_vs_outputs_post(struct radv_shader_context *ctx,
2368 bool export_prim_id, bool export_layer_id,
2369 struct radv_vs_output_info *outinfo)
2370 {
2371 uint32_t param_count = 0;
2372 unsigned target;
2373 unsigned pos_idx, num_pos_exports = 0;
2374 struct ac_export_args args, pos_args[4] = {};
2375 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2376 int i;
2377
2378 if (ctx->options->key.has_multiview_view_index) {
2379 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2380 if(!*tmp_out) {
2381 for(unsigned i = 0; i < 4; ++i)
2382 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2383 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2384 }
2385
2386 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2387 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2388 }
2389
2390 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2391 sizeof(outinfo->vs_output_param_offset));
2392
2393 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2394 LLVMValueRef slots[8];
2395 unsigned j;
2396
2397 if (outinfo->cull_dist_mask)
2398 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2399
2400 i = VARYING_SLOT_CLIP_DIST0;
2401 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
2402 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2403
2404 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
2405 slots[i] = LLVMGetUndef(ctx->ac.f32);
2406
2407 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
2408 target = V_008DFC_SQ_EXP_POS + 3;
2409 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2410 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2411 &args, sizeof(args));
2412 }
2413
2414 target = V_008DFC_SQ_EXP_POS + 2;
2415 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2416 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2417 &args, sizeof(args));
2418
2419 }
2420
2421 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2422 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2423 for (unsigned j = 0; j < 4; j++)
2424 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2425 }
2426 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2427
2428 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2429 outinfo->writes_pointsize = true;
2430 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2431 }
2432
2433 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2434 outinfo->writes_layer = true;
2435 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2436 }
2437
2438 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2439 outinfo->writes_viewport_index = true;
2440 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2441 }
2442
2443 if (outinfo->writes_pointsize ||
2444 outinfo->writes_layer ||
2445 outinfo->writes_viewport_index) {
2446 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2447 (outinfo->writes_layer == true ? 4 : 0));
2448 pos_args[1].valid_mask = 0;
2449 pos_args[1].done = 0;
2450 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2451 pos_args[1].compr = 0;
2452 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2453 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2454 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2455 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2456
2457 if (outinfo->writes_pointsize == true)
2458 pos_args[1].out[0] = psize_value;
2459 if (outinfo->writes_layer == true)
2460 pos_args[1].out[2] = layer_value;
2461 if (outinfo->writes_viewport_index == true) {
2462 if (ctx->options->chip_class >= GFX9) {
2463 /* GFX9 has the layer in out.z[10:0] and the viewport
2464 * index in out.z[19:16].
2465 */
2466 LLVMValueRef v = viewport_index_value;
2467 v = ac_to_integer(&ctx->ac, v);
2468 v = LLVMBuildShl(ctx->ac.builder, v,
2469 LLVMConstInt(ctx->ac.i32, 16, false),
2470 "");
2471 v = LLVMBuildOr(ctx->ac.builder, v,
2472 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2473
2474 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2475 pos_args[1].enabled_channels |= 1 << 2;
2476 } else {
2477 pos_args[1].out[3] = viewport_index_value;
2478 pos_args[1].enabled_channels |= 1 << 3;
2479 }
2480 }
2481 }
2482 for (i = 0; i < 4; i++) {
2483 if (pos_args[i].out[0])
2484 num_pos_exports++;
2485 }
2486
2487 pos_idx = 0;
2488 for (i = 0; i < 4; i++) {
2489 if (!pos_args[i].out[0])
2490 continue;
2491
2492 /* Specify the target we are exporting */
2493 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2494 if (pos_idx == num_pos_exports)
2495 pos_args[i].done = 1;
2496 ac_build_export(&ctx->ac, &pos_args[i]);
2497 }
2498
2499 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2500 LLVMValueRef values[4];
2501 if (!(ctx->output_mask & (1ull << i)))
2502 continue;
2503
2504 if (i != VARYING_SLOT_LAYER &&
2505 i != VARYING_SLOT_PRIMITIVE_ID &&
2506 i < VARYING_SLOT_VAR0)
2507 continue;
2508
2509 for (unsigned j = 0; j < 4; j++)
2510 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2511
2512 unsigned output_usage_mask;
2513
2514 if (ctx->stage == MESA_SHADER_VERTEX &&
2515 !ctx->is_gs_copy_shader) {
2516 output_usage_mask =
2517 ctx->shader_info->info.vs.output_usage_mask[i];
2518 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2519 output_usage_mask =
2520 ctx->shader_info->info.tes.output_usage_mask[i];
2521 } else {
2522 assert(ctx->is_gs_copy_shader);
2523 output_usage_mask =
2524 ctx->shader_info->info.gs.output_usage_mask[i];
2525 }
2526
2527 radv_export_param(ctx, param_count, values, output_usage_mask);
2528
2529 outinfo->vs_output_param_offset[i] = param_count++;
2530 }
2531
2532 if (export_prim_id) {
2533 LLVMValueRef values[4];
2534
2535 values[0] = ctx->vs_prim_id;
2536 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2537 ctx->shader_info->vs.vgpr_comp_cnt);
2538 for (unsigned j = 1; j < 4; j++)
2539 values[j] = ctx->ac.f32_0;
2540
2541 radv_export_param(ctx, param_count, values, 0x1);
2542
2543 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2544 outinfo->export_prim_id = true;
2545 }
2546
2547 if (export_layer_id && layer_value) {
2548 LLVMValueRef values[4];
2549
2550 values[0] = layer_value;
2551 for (unsigned j = 1; j < 4; j++)
2552 values[j] = ctx->ac.f32_0;
2553
2554 radv_export_param(ctx, param_count, values, 0x1);
2555
2556 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2557 }
2558
2559 outinfo->pos_exports = num_pos_exports;
2560 outinfo->param_exports = param_count;
2561 }
2562
2563 static void
2564 handle_es_outputs_post(struct radv_shader_context *ctx,
2565 struct radv_es_output_info *outinfo)
2566 {
2567 int j;
2568 uint64_t max_output_written = 0;
2569 LLVMValueRef lds_base = NULL;
2570
2571 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2572 int param_index;
2573 int length = 4;
2574
2575 if (!(ctx->output_mask & (1ull << i)))
2576 continue;
2577
2578 if (i == VARYING_SLOT_CLIP_DIST0)
2579 length = ctx->num_output_clips + ctx->num_output_culls;
2580
2581 param_index = shader_io_get_unique_index(i);
2582
2583 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2584 }
2585
2586 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2587
2588 if (ctx->ac.chip_class >= GFX9) {
2589 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2590 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2591 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2592 LLVMConstInt(ctx->ac.i32, 24, false),
2593 LLVMConstInt(ctx->ac.i32, 4, false), false);
2594 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2595 LLVMBuildMul(ctx->ac.builder, wave_idx,
2596 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2597 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2598 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2599 }
2600
2601 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2602 LLVMValueRef dw_addr = NULL;
2603 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2604 unsigned output_usage_mask;
2605 int param_index;
2606 int length = 4;
2607
2608 if (!(ctx->output_mask & (1ull << i)))
2609 continue;
2610
2611 if (ctx->stage == MESA_SHADER_VERTEX) {
2612 output_usage_mask =
2613 ctx->shader_info->info.vs.output_usage_mask[i];
2614 } else {
2615 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2616 output_usage_mask =
2617 ctx->shader_info->info.tes.output_usage_mask[i];
2618 }
2619
2620 if (i == VARYING_SLOT_CLIP_DIST0) {
2621 length = ctx->num_output_clips + ctx->num_output_culls;
2622 output_usage_mask = (1 << length) - 1;
2623 }
2624
2625 param_index = shader_io_get_unique_index(i);
2626
2627 if (lds_base) {
2628 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2629 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2630 "");
2631 }
2632
2633 for (j = 0; j < length; j++) {
2634 if (!(output_usage_mask & (1 << j)))
2635 continue;
2636
2637 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2638 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2639
2640 if (ctx->ac.chip_class >= GFX9) {
2641 LLVMValueRef dw_addr_offset =
2642 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2643 LLVMConstInt(ctx->ac.i32,
2644 j, false), "");
2645
2646 ac_lds_store(&ctx->ac, dw_addr_offset,
2647 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2648 } else {
2649 ac_build_buffer_store_dword(&ctx->ac,
2650 ctx->esgs_ring,
2651 out_val, 1,
2652 NULL, ctx->es2gs_offset,
2653 (4 * param_index + j) * 4,
2654 1, 1, true, true);
2655 }
2656 }
2657 }
2658 }
2659
2660 static void
2661 handle_ls_outputs_post(struct radv_shader_context *ctx)
2662 {
2663 LLVMValueRef vertex_id = ctx->rel_auto_id;
2664 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2665 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2666 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2667 vertex_dw_stride, "");
2668
2669 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2670 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2671 int length = 4;
2672
2673 if (!(ctx->output_mask & (1ull << i)))
2674 continue;
2675
2676 if (i == VARYING_SLOT_CLIP_DIST0)
2677 length = ctx->num_output_clips + ctx->num_output_culls;
2678 int param = shader_io_get_unique_index(i);
2679 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2680 LLVMConstInt(ctx->ac.i32, param * 4, false),
2681 "");
2682 for (unsigned j = 0; j < length; j++) {
2683 ac_lds_store(&ctx->ac, dw_addr,
2684 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2685 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2686 }
2687 }
2688 }
2689
2690 static void
2691 write_tess_factors(struct radv_shader_context *ctx)
2692 {
2693 unsigned stride, outer_comps, inner_comps;
2694 struct ac_build_if_state if_ctx, inner_if_ctx;
2695 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2696 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2697 unsigned tess_inner_index = 0, tess_outer_index;
2698 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2699 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2700 int i;
2701 ac_emit_barrier(&ctx->ac, ctx->stage);
2702
2703 switch (ctx->options->key.tcs.primitive_mode) {
2704 case GL_ISOLINES:
2705 stride = 2;
2706 outer_comps = 2;
2707 inner_comps = 0;
2708 break;
2709 case GL_TRIANGLES:
2710 stride = 4;
2711 outer_comps = 3;
2712 inner_comps = 1;
2713 break;
2714 case GL_QUADS:
2715 stride = 6;
2716 outer_comps = 4;
2717 inner_comps = 2;
2718 break;
2719 default:
2720 return;
2721 }
2722
2723 ac_nir_build_if(&if_ctx, ctx,
2724 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2725 invocation_id, ctx->ac.i32_0, ""));
2726
2727 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2728
2729 if (inner_comps) {
2730 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2731 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2732 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2733 }
2734
2735 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2736 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2737 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2738
2739 for (i = 0; i < 4; i++) {
2740 inner[i] = LLVMGetUndef(ctx->ac.i32);
2741 outer[i] = LLVMGetUndef(ctx->ac.i32);
2742 }
2743
2744 // LINES reversal
2745 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2746 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2747 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2748 ctx->ac.i32_1, "");
2749 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2750 } else {
2751 for (i = 0; i < outer_comps; i++) {
2752 outer[i] = out[i] =
2753 ac_lds_load(&ctx->ac, lds_outer);
2754 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2755 ctx->ac.i32_1, "");
2756 }
2757 for (i = 0; i < inner_comps; i++) {
2758 inner[i] = out[outer_comps+i] =
2759 ac_lds_load(&ctx->ac, lds_inner);
2760 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2761 ctx->ac.i32_1, "");
2762 }
2763 }
2764
2765 /* Convert the outputs to vectors for stores. */
2766 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2767 vec1 = NULL;
2768
2769 if (stride > 4)
2770 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2771
2772
2773 buffer = ctx->hs_ring_tess_factor;
2774 tf_base = ctx->tess_factor_offset;
2775 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2776 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2777 unsigned tf_offset = 0;
2778
2779 if (ctx->options->chip_class <= VI) {
2780 ac_nir_build_if(&inner_if_ctx, ctx,
2781 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2782 rel_patch_id, ctx->ac.i32_0, ""));
2783
2784 /* Store the dynamic HS control word. */
2785 ac_build_buffer_store_dword(&ctx->ac, buffer,
2786 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2787 1, ctx->ac.i32_0, tf_base,
2788 0, 1, 0, true, false);
2789 tf_offset += 4;
2790
2791 ac_nir_build_endif(&inner_if_ctx);
2792 }
2793
2794 /* Store the tessellation factors. */
2795 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2796 MIN2(stride, 4), byteoffset, tf_base,
2797 tf_offset, 1, 0, true, false);
2798 if (vec1)
2799 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2800 stride - 4, byteoffset, tf_base,
2801 16 + tf_offset, 1, 0, true, false);
2802
2803 //store to offchip for TES to read - only if TES reads them
2804 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2805 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2806 LLVMValueRef tf_inner_offset;
2807 unsigned param_outer, param_inner;
2808
2809 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2810 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2811 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2812
2813 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2814 util_next_power_of_two(outer_comps));
2815
2816 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2817 outer_comps, tf_outer_offset,
2818 ctx->oc_lds, 0, 1, 0, true, false);
2819 if (inner_comps) {
2820 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2821 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2822 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2823
2824 inner_vec = inner_comps == 1 ? inner[0] :
2825 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2826 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2827 inner_comps, tf_inner_offset,
2828 ctx->oc_lds, 0, 1, 0, true, false);
2829 }
2830 }
2831 ac_nir_build_endif(&if_ctx);
2832 }
2833
2834 static void
2835 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2836 {
2837 write_tess_factors(ctx);
2838 }
2839
2840 static bool
2841 si_export_mrt_color(struct radv_shader_context *ctx,
2842 LLVMValueRef *color, unsigned index,
2843 struct ac_export_args *args)
2844 {
2845 /* Export */
2846 si_llvm_init_export_args(ctx, color, 0xf,
2847 V_008DFC_SQ_EXP_MRT + index, args);
2848 if (!args->enabled_channels)
2849 return false; /* unnecessary NULL export */
2850
2851 return true;
2852 }
2853
2854 static void
2855 radv_export_mrt_z(struct radv_shader_context *ctx,
2856 LLVMValueRef depth, LLVMValueRef stencil,
2857 LLVMValueRef samplemask)
2858 {
2859 struct ac_export_args args;
2860
2861 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2862
2863 ac_build_export(&ctx->ac, &args);
2864 }
2865
2866 static void
2867 handle_fs_outputs_post(struct radv_shader_context *ctx)
2868 {
2869 unsigned index = 0;
2870 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2871 struct ac_export_args color_args[8];
2872
2873 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2874 LLVMValueRef values[4];
2875
2876 if (!(ctx->output_mask & (1ull << i)))
2877 continue;
2878
2879 if (i < FRAG_RESULT_DATA0)
2880 continue;
2881
2882 for (unsigned j = 0; j < 4; j++)
2883 values[j] = ac_to_float(&ctx->ac,
2884 radv_load_output(ctx, i, j));
2885
2886 bool ret = si_export_mrt_color(ctx, values,
2887 i - FRAG_RESULT_DATA0,
2888 &color_args[index]);
2889 if (ret)
2890 index++;
2891 }
2892
2893 /* Process depth, stencil, samplemask. */
2894 if (ctx->shader_info->info.ps.writes_z) {
2895 depth = ac_to_float(&ctx->ac,
2896 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
2897 }
2898 if (ctx->shader_info->info.ps.writes_stencil) {
2899 stencil = ac_to_float(&ctx->ac,
2900 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
2901 }
2902 if (ctx->shader_info->info.ps.writes_sample_mask) {
2903 samplemask = ac_to_float(&ctx->ac,
2904 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
2905 }
2906
2907 /* Set the DONE bit on last non-null color export only if Z isn't
2908 * exported.
2909 */
2910 if (index > 0 &&
2911 !ctx->shader_info->info.ps.writes_z &&
2912 !ctx->shader_info->info.ps.writes_stencil &&
2913 !ctx->shader_info->info.ps.writes_sample_mask) {
2914 unsigned last = index - 1;
2915
2916 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
2917 color_args[last].done = 1; /* DONE bit */
2918 }
2919
2920 /* Export PS outputs. */
2921 for (unsigned i = 0; i < index; i++)
2922 ac_build_export(&ctx->ac, &color_args[i]);
2923
2924 if (depth || stencil || samplemask)
2925 radv_export_mrt_z(ctx, depth, stencil, samplemask);
2926 else if (!index)
2927 ac_build_export_null(&ctx->ac);
2928 }
2929
2930 static void
2931 emit_gs_epilogue(struct radv_shader_context *ctx)
2932 {
2933 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
2934 }
2935
2936 static void
2937 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
2938 LLVMValueRef *addrs)
2939 {
2940 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2941
2942 switch (ctx->stage) {
2943 case MESA_SHADER_VERTEX:
2944 if (ctx->options->key.vs.as_ls)
2945 handle_ls_outputs_post(ctx);
2946 else if (ctx->options->key.vs.as_es)
2947 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
2948 else
2949 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
2950 ctx->options->key.vs.export_layer_id,
2951 &ctx->shader_info->vs.outinfo);
2952 break;
2953 case MESA_SHADER_FRAGMENT:
2954 handle_fs_outputs_post(ctx);
2955 break;
2956 case MESA_SHADER_GEOMETRY:
2957 emit_gs_epilogue(ctx);
2958 break;
2959 case MESA_SHADER_TESS_CTRL:
2960 handle_tcs_outputs_post(ctx);
2961 break;
2962 case MESA_SHADER_TESS_EVAL:
2963 if (ctx->options->key.tes.as_es)
2964 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
2965 else
2966 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
2967 ctx->options->key.tes.export_layer_id,
2968 &ctx->shader_info->tes.outinfo);
2969 break;
2970 default:
2971 break;
2972 }
2973 }
2974
2975 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
2976 const struct radv_nir_compiler_options *options)
2977 {
2978 LLVMPassManagerRef passmgr;
2979 /* Create the pass manager */
2980 passmgr = LLVMCreateFunctionPassManagerForModule(
2981 ctx->ac.module);
2982
2983 if (options->check_ir)
2984 LLVMAddVerifierPass(passmgr);
2985
2986 /* This pass should eliminate all the load and store instructions */
2987 LLVMAddPromoteMemoryToRegisterPass(passmgr);
2988
2989 /* Add some optimization passes */
2990 LLVMAddScalarReplAggregatesPass(passmgr);
2991 LLVMAddLICMPass(passmgr);
2992 LLVMAddAggressiveDCEPass(passmgr);
2993 LLVMAddCFGSimplificationPass(passmgr);
2994 /* This is recommended by the instruction combining pass. */
2995 LLVMAddEarlyCSEMemSSAPass(passmgr);
2996 LLVMAddInstructionCombiningPass(passmgr);
2997
2998 /* Run the pass */
2999 LLVMInitializeFunctionPassManager(passmgr);
3000 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
3001 LLVMFinalizeFunctionPassManager(passmgr);
3002
3003 LLVMDisposeBuilder(ctx->ac.builder);
3004 LLVMDisposePassManager(passmgr);
3005
3006 ac_llvm_context_dispose(&ctx->ac);
3007 }
3008
3009 static void
3010 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3011 {
3012 struct radv_vs_output_info *outinfo;
3013
3014 switch (ctx->stage) {
3015 case MESA_SHADER_FRAGMENT:
3016 case MESA_SHADER_COMPUTE:
3017 case MESA_SHADER_TESS_CTRL:
3018 case MESA_SHADER_GEOMETRY:
3019 return;
3020 case MESA_SHADER_VERTEX:
3021 if (ctx->options->key.vs.as_ls ||
3022 ctx->options->key.vs.as_es)
3023 return;
3024 outinfo = &ctx->shader_info->vs.outinfo;
3025 break;
3026 case MESA_SHADER_TESS_EVAL:
3027 if (ctx->options->key.vs.as_es)
3028 return;
3029 outinfo = &ctx->shader_info->tes.outinfo;
3030 break;
3031 default:
3032 unreachable("Unhandled shader type");
3033 }
3034
3035 ac_optimize_vs_outputs(&ctx->ac,
3036 ctx->main_function,
3037 outinfo->vs_output_param_offset,
3038 VARYING_SLOT_MAX,
3039 &outinfo->param_exports);
3040 }
3041
3042 static void
3043 ac_setup_rings(struct radv_shader_context *ctx)
3044 {
3045 if (ctx->options->chip_class <= VI &&
3046 (ctx->stage == MESA_SHADER_GEOMETRY ||
3047 ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
3048 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3049 : RING_ESGS_VS;
3050 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3051
3052 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3053 ctx->ring_offsets,
3054 offset);
3055 }
3056
3057 if (ctx->is_gs_copy_shader) {
3058 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
3059 }
3060 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3061 LLVMValueRef tmp;
3062 uint32_t num_entries = 64;
3063 LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size, false);
3064 LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size << 16, false);
3065 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
3066
3067 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
3068
3069 tmp = LLVMConstInt(ctx->ac.i32, num_entries, false);
3070 if (ctx->options->chip_class >= VI)
3071 tmp = LLVMBuildMul(ctx->ac.builder, gsvs_ring_stride, tmp, "");
3072 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
3073 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
3074 tmp = LLVMBuildOr(ctx->ac.builder, tmp, gsvs_ring_desc, "");
3075 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
3076 }
3077
3078 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3079 ctx->stage == MESA_SHADER_TESS_EVAL) {
3080 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3081 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3082 }
3083 }
3084
3085 static unsigned
3086 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
3087 const struct nir_shader *nir)
3088 {
3089 switch (nir->info.stage) {
3090 case MESA_SHADER_TESS_CTRL:
3091 return chip_class >= CIK ? 128 : 64;
3092 case MESA_SHADER_GEOMETRY:
3093 return chip_class >= GFX9 ? 128 : 64;
3094 case MESA_SHADER_COMPUTE:
3095 break;
3096 default:
3097 return 0;
3098 }
3099
3100 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
3101 nir->info.cs.local_size[1] *
3102 nir->info.cs.local_size[2];
3103 return max_workgroup_size;
3104 }
3105
3106 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3107 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3108 {
3109 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3110 LLVMConstInt(ctx->ac.i32, 8, false),
3111 LLVMConstInt(ctx->ac.i32, 8, false), false);
3112 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3113 ctx->ac.i32_0, "");
3114 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
3115 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
3116 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3117 }
3118
3119 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3120 {
3121 for(int i = 5; i >= 0; --i) {
3122 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3123 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
3124 LLVMConstInt(ctx->ac.i32, 16, false), false);
3125 }
3126
3127 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3128 LLVMConstInt(ctx->ac.i32, 16, false),
3129 LLVMConstInt(ctx->ac.i32, 8, false), false);
3130 }
3131
3132
3133 static
3134 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
3135 struct nir_shader *const *shaders,
3136 int shader_count,
3137 struct radv_shader_variant_info *shader_info,
3138 const struct radv_nir_compiler_options *options)
3139 {
3140 struct radv_shader_context ctx = {0};
3141 unsigned i;
3142 ctx.options = options;
3143 ctx.shader_info = shader_info;
3144 ctx.context = LLVMContextCreate();
3145
3146 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3147 options->family);
3148 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3149 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
3150
3151 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
3152 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
3153 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
3154 LLVMDisposeTargetData(data_layout);
3155 LLVMDisposeMessage(data_layout_str);
3156
3157 enum ac_float_mode float_mode =
3158 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3159 AC_FLOAT_MODE_DEFAULT;
3160
3161 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3162
3163 memset(shader_info, 0, sizeof(*shader_info));
3164
3165 for(int i = 0; i < shader_count; ++i)
3166 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3167
3168 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3169 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3170 for (i = 0; i < AC_UD_MAX_UD; i++)
3171 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3172
3173 ctx.max_workgroup_size = 0;
3174 for (int i = 0; i < shader_count; ++i) {
3175 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3176 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3177 shaders[i]));
3178 }
3179
3180 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3181 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3182
3183 ctx.abi.inputs = &ctx.inputs[0];
3184 ctx.abi.emit_outputs = handle_shader_outputs_post;
3185 ctx.abi.emit_vertex = visit_emit_vertex;
3186 ctx.abi.load_ubo = radv_load_ubo;
3187 ctx.abi.load_ssbo = radv_load_ssbo;
3188 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3189 ctx.abi.load_resource = radv_load_resource;
3190 ctx.abi.clamp_shadow_reference = false;
3191 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9;
3192
3193 if (shader_count >= 2)
3194 ac_init_exec_full_mask(&ctx.ac);
3195
3196 if (ctx.ac.chip_class == GFX9 &&
3197 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3198 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3199
3200 for(int i = 0; i < shader_count; ++i) {
3201 ctx.stage = shaders[i]->info.stage;
3202 ctx.output_mask = 0;
3203 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3204 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3205
3206 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3207 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3208 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3209 ctx.abi.load_inputs = load_gs_input;
3210 ctx.abi.emit_primitive = visit_end_primitive;
3211 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3212 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3213 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3214 ctx.abi.load_tess_varyings = load_tcs_varyings;
3215 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3216 ctx.abi.store_tcs_outputs = store_tcs_output;
3217 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3218 if (shader_count == 1)
3219 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3220 else
3221 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3222 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3223 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3224 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3225 ctx.abi.load_tess_varyings = load_tes_input;
3226 ctx.abi.load_tess_coord = load_tess_coord;
3227 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3228 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3229 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3230 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3231 if (shader_info->info.vs.needs_instance_id) {
3232 if (ctx.options->key.vs.as_ls) {
3233 ctx.shader_info->vs.vgpr_comp_cnt =
3234 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3235 } else {
3236 ctx.shader_info->vs.vgpr_comp_cnt =
3237 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3238 }
3239 }
3240 ctx.abi.load_base_vertex = radv_load_base_vertex;
3241 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3242 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3243 ctx.abi.lookup_interp_param = lookup_interp_param;
3244 ctx.abi.load_sample_position = load_sample_position;
3245 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3246 ctx.abi.emit_kill = radv_emit_kill;
3247 }
3248
3249 if (i)
3250 ac_emit_barrier(&ctx.ac, ctx.stage);
3251
3252 nir_foreach_variable(variable, &shaders[i]->outputs)
3253 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3254
3255 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3256 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3257 shaders[i]->info.cull_distance_array_size > 4;
3258 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3259 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3260 shaders[i]->info.gs.vertices_out;
3261 }
3262
3263 ac_setup_rings(&ctx);
3264
3265 LLVMBasicBlockRef merge_block;
3266 if (shader_count >= 2) {
3267 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3268 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3269 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3270
3271 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3272 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3273 LLVMConstInt(ctx.ac.i32, 8, false), false);
3274 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3275 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3276 thread_id, count, "");
3277 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3278
3279 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3280 }
3281
3282 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3283 handle_fs_inputs(&ctx, shaders[i]);
3284 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3285 handle_vs_inputs(&ctx, shaders[i]);
3286 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3287 prepare_gs_input_vgprs(&ctx);
3288
3289 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3290
3291 if (shader_count >= 2) {
3292 LLVMBuildBr(ctx.ac.builder, merge_block);
3293 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3294 }
3295
3296 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3297 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3298 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3299 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3300 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3301 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3302 }
3303 }
3304
3305 LLVMBuildRetVoid(ctx.ac.builder);
3306
3307 if (options->dump_preoptir)
3308 ac_dump_module(ctx.ac.module);
3309
3310 ac_llvm_finalize_module(&ctx, options);
3311
3312 if (shader_count == 1)
3313 ac_nir_eliminate_const_vs_outputs(&ctx);
3314
3315 if (options->dump_shader) {
3316 ctx.shader_info->private_mem_vgprs =
3317 ac_count_scratch_private_memory(ctx.main_function);
3318 }
3319
3320 return ctx.ac.module;
3321 }
3322
3323 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3324 {
3325 unsigned *retval = (unsigned *)context;
3326 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3327 char *description = LLVMGetDiagInfoDescription(di);
3328
3329 if (severity == LLVMDSError) {
3330 *retval = 1;
3331 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3332 description);
3333 }
3334
3335 LLVMDisposeMessage(description);
3336 }
3337
3338 static unsigned ac_llvm_compile(LLVMModuleRef M,
3339 struct ac_shader_binary *binary,
3340 LLVMTargetMachineRef tm)
3341 {
3342 unsigned retval = 0;
3343 char *err;
3344 LLVMContextRef llvm_ctx;
3345 LLVMMemoryBufferRef out_buffer;
3346 unsigned buffer_size;
3347 const char *buffer_data;
3348 LLVMBool mem_err;
3349
3350 /* Setup Diagnostic Handler*/
3351 llvm_ctx = LLVMGetModuleContext(M);
3352
3353 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3354 &retval);
3355
3356 /* Compile IR*/
3357 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
3358 &err, &out_buffer);
3359
3360 /* Process Errors/Warnings */
3361 if (mem_err) {
3362 fprintf(stderr, "%s: %s", __FUNCTION__, err);
3363 free(err);
3364 retval = 1;
3365 goto out;
3366 }
3367
3368 /* Extract Shader Code*/
3369 buffer_size = LLVMGetBufferSize(out_buffer);
3370 buffer_data = LLVMGetBufferStart(out_buffer);
3371
3372 ac_elf_read(buffer_data, buffer_size, binary);
3373
3374 /* Clean up */
3375 LLVMDisposeMemoryBuffer(out_buffer);
3376
3377 out:
3378 return retval;
3379 }
3380
3381 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
3382 LLVMModuleRef llvm_module,
3383 struct ac_shader_binary *binary,
3384 struct ac_shader_config *config,
3385 struct radv_shader_variant_info *shader_info,
3386 gl_shader_stage stage,
3387 const struct radv_nir_compiler_options *options)
3388 {
3389 if (options->dump_shader)
3390 ac_dump_module(llvm_module);
3391
3392 memset(binary, 0, sizeof(*binary));
3393
3394 if (options->record_llvm_ir) {
3395 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3396 binary->llvm_ir_string = strdup(llvm_ir);
3397 LLVMDisposeMessage(llvm_ir);
3398 }
3399
3400 int v = ac_llvm_compile(llvm_module, binary, tm);
3401 if (v) {
3402 fprintf(stderr, "compile failed\n");
3403 }
3404
3405 if (options->dump_shader)
3406 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3407
3408 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3409
3410 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3411 LLVMDisposeModule(llvm_module);
3412 LLVMContextDispose(ctx);
3413
3414 if (stage == MESA_SHADER_FRAGMENT) {
3415 shader_info->num_input_vgprs = 0;
3416 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3417 shader_info->num_input_vgprs += 2;
3418 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3419 shader_info->num_input_vgprs += 2;
3420 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3421 shader_info->num_input_vgprs += 2;
3422 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3423 shader_info->num_input_vgprs += 3;
3424 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3425 shader_info->num_input_vgprs += 2;
3426 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3427 shader_info->num_input_vgprs += 2;
3428 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3429 shader_info->num_input_vgprs += 2;
3430 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3431 shader_info->num_input_vgprs += 1;
3432 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3433 shader_info->num_input_vgprs += 1;
3434 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3435 shader_info->num_input_vgprs += 1;
3436 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3437 shader_info->num_input_vgprs += 1;
3438 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3439 shader_info->num_input_vgprs += 1;
3440 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3441 shader_info->num_input_vgprs += 1;
3442 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3443 shader_info->num_input_vgprs += 1;
3444 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3445 shader_info->num_input_vgprs += 1;
3446 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3447 shader_info->num_input_vgprs += 1;
3448 }
3449 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3450
3451 /* +3 for scratch wave offset and VCC */
3452 config->num_sgprs = MAX2(config->num_sgprs,
3453 shader_info->num_input_sgprs + 3);
3454
3455 /* Enable 64-bit and 16-bit denormals, because there is no performance
3456 * cost.
3457 *
3458 * If denormals are enabled, all floating-point output modifiers are
3459 * ignored.
3460 *
3461 * Don't enable denormals for 32-bit floats, because:
3462 * - Floating-point output modifiers would be ignored by the hw.
3463 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3464 * have to stop using those.
3465 * - SI & CI would be very slow.
3466 */
3467 config->float_mode |= V_00B028_FP_64_DENORMS;
3468 }
3469
3470 static void
3471 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3472 {
3473 switch (nir->info.stage) {
3474 case MESA_SHADER_COMPUTE:
3475 for (int i = 0; i < 3; ++i)
3476 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3477 break;
3478 case MESA_SHADER_FRAGMENT:
3479 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3480 break;
3481 case MESA_SHADER_GEOMETRY:
3482 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3483 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3484 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3485 shader_info->gs.invocations = nir->info.gs.invocations;
3486 break;
3487 case MESA_SHADER_TESS_EVAL:
3488 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3489 shader_info->tes.spacing = nir->info.tess.spacing;
3490 shader_info->tes.ccw = nir->info.tess.ccw;
3491 shader_info->tes.point_mode = nir->info.tess.point_mode;
3492 shader_info->tes.as_es = options->key.tes.as_es;
3493 break;
3494 case MESA_SHADER_TESS_CTRL:
3495 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3496 break;
3497 case MESA_SHADER_VERTEX:
3498 shader_info->vs.as_es = options->key.vs.as_es;
3499 shader_info->vs.as_ls = options->key.vs.as_ls;
3500 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3501 if (options->key.vs.as_ls)
3502 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3503 break;
3504 default:
3505 break;
3506 }
3507 }
3508
3509 void
3510 radv_compile_nir_shader(LLVMTargetMachineRef tm,
3511 struct ac_shader_binary *binary,
3512 struct ac_shader_config *config,
3513 struct radv_shader_variant_info *shader_info,
3514 struct nir_shader *const *nir,
3515 int nir_count,
3516 const struct radv_nir_compiler_options *options)
3517 {
3518
3519 LLVMModuleRef llvm_module;
3520
3521 llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
3522 options);
3523
3524 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
3525 nir[0]->info.stage, options);
3526
3527 for (int i = 0; i < nir_count; ++i)
3528 ac_fill_shader_info(shader_info, nir[i], options);
3529
3530 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3531 if (options->chip_class == GFX9) {
3532 if (nir_count == 2 &&
3533 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3534 shader_info->gs.es_type = nir[0]->info.stage;
3535 }
3536 }
3537 }
3538
3539 static void
3540 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3541 {
3542 LLVMValueRef vtx_offset =
3543 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3544 LLVMConstInt(ctx->ac.i32, 4, false), "");
3545 int idx = 0;
3546
3547 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3548 int length = 4;
3549 int slot = idx;
3550 int slot_inc = 1;
3551 if (!(ctx->output_mask & (1ull << i)))
3552 continue;
3553
3554 if (i == VARYING_SLOT_CLIP_DIST0) {
3555 /* unpack clip and cull from a single set of slots */
3556 length = ctx->num_output_clips + ctx->num_output_culls;
3557 if (length > 4)
3558 slot_inc = 2;
3559 }
3560
3561 for (unsigned j = 0; j < length; j++) {
3562 LLVMValueRef value, soffset;
3563
3564 soffset = LLVMConstInt(ctx->ac.i32,
3565 (slot * 4 + j) *
3566 ctx->gs_max_out_vertices * 16 * 4, false);
3567
3568 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3569 1, ctx->ac.i32_0,
3570 vtx_offset, soffset,
3571 0, 1, 1, true, false);
3572
3573 LLVMBuildStore(ctx->ac.builder,
3574 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3575 }
3576 idx += slot_inc;
3577 }
3578 handle_vs_outputs_post(ctx, false, false, &ctx->shader_info->vs.outinfo);
3579 }
3580
3581 void
3582 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
3583 struct nir_shader *geom_shader,
3584 struct ac_shader_binary *binary,
3585 struct ac_shader_config *config,
3586 struct radv_shader_variant_info *shader_info,
3587 const struct radv_nir_compiler_options *options)
3588 {
3589 struct radv_shader_context ctx = {0};
3590 ctx.context = LLVMContextCreate();
3591 ctx.options = options;
3592 ctx.shader_info = shader_info;
3593
3594 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3595 options->family);
3596 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3597
3598 ctx.is_gs_copy_shader = true;
3599 LLVMSetTarget(ctx.ac.module, "amdgcn--");
3600
3601 enum ac_float_mode float_mode =
3602 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3603 AC_FLOAT_MODE_DEFAULT;
3604
3605 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3606 ctx.stage = MESA_SHADER_VERTEX;
3607
3608 radv_nir_shader_info_pass(geom_shader, options, &shader_info->info);
3609
3610 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3611
3612 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3613 ac_setup_rings(&ctx);
3614
3615 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3616 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3617
3618 nir_foreach_variable(variable, &geom_shader->outputs) {
3619 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3620 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3621 variable, MESA_SHADER_VERTEX);
3622 }
3623
3624 ac_gs_copy_shader_emit(&ctx);
3625
3626 LLVMBuildRetVoid(ctx.ac.builder);
3627
3628 ac_llvm_finalize_module(&ctx, options);
3629
3630 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
3631 MESA_SHADER_VERTEX, options);
3632 }