projects / mesa.git / blob
? search:


e80938527e5a41d28a7237927409f2ff82e61a40
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "nir/nir.h"
32
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
37
38 #include "sid.h"
39 #include "gfx9d.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct radv_shader_context {
50 struct ac_llvm_context ac;
51 const struct radv_nir_compiler_options *options;
52 struct radv_shader_variant_info *shader_info;
53 struct ac_shader_abi abi;
54
55 unsigned max_workgroup_size;
56 LLVMContextRef context;
57 LLVMValueRef main_function;
58
59 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
60 LLVMValueRef ring_offsets;
61
62 LLVMValueRef vertex_buffers;
63 LLVMValueRef rel_auto_id;
64 LLVMValueRef vs_prim_id;
65 LLVMValueRef es2gs_offset;
66
67 LLVMValueRef oc_lds;
68 LLVMValueRef merged_wave_info;
69 LLVMValueRef tess_factor_offset;
70 LLVMValueRef tes_rel_patch_id;
71 LLVMValueRef tes_u;
72 LLVMValueRef tes_v;
73
74 LLVMValueRef gs2vs_offset;
75 LLVMValueRef gs_wave_id;
76 LLVMValueRef gs_vtx_offset[6];
77
78 LLVMValueRef esgs_ring;
79 LLVMValueRef gsvs_ring[4];
80 LLVMValueRef hs_ring_tess_offchip;
81 LLVMValueRef hs_ring_tess_factor;
82
83 LLVMValueRef persp_sample, persp_center, persp_centroid;
84 LLVMValueRef linear_sample, linear_center, linear_centroid;
85
86 /* Streamout */
87 LLVMValueRef streamout_buffers;
88 LLVMValueRef streamout_write_idx;
89 LLVMValueRef streamout_config;
90 LLVMValueRef streamout_offset[4];
91
92 gl_shader_stage stage;
93
94 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
95
96 uint64_t input_mask;
97 uint64_t output_mask;
98
99 bool is_gs_copy_shader;
100 LLVMValueRef gs_next_vertex[4];
101 unsigned gs_max_out_vertices;
102
103 unsigned tes_primitive_mode;
104
105 uint32_t tcs_patch_outputs_read;
106 uint64_t tcs_outputs_read;
107 uint32_t tcs_vertices_per_patch;
108 uint32_t tcs_num_inputs;
109 uint32_t tcs_num_patches;
110 uint32_t max_gsvs_emit_size;
111 uint32_t gsvs_vertex_size;
112 };
113
114 enum radeon_llvm_calling_convention {
115 RADEON_LLVM_AMDGPU_VS = 87,
116 RADEON_LLVM_AMDGPU_GS = 88,
117 RADEON_LLVM_AMDGPU_PS = 89,
118 RADEON_LLVM_AMDGPU_CS = 90,
119 RADEON_LLVM_AMDGPU_HS = 93,
120 };
121
122 static inline struct radv_shader_context *
123 radv_shader_context_from_abi(struct ac_shader_abi *abi)
124 {
125 struct radv_shader_context *ctx = NULL;
126 return container_of(abi, ctx, abi);
127 }
128
129 struct ac_build_if_state
130 {
131 struct radv_shader_context *ctx;
132 LLVMValueRef condition;
133 LLVMBasicBlockRef entry_block;
134 LLVMBasicBlockRef true_block;
135 LLVMBasicBlockRef false_block;
136 LLVMBasicBlockRef merge_block;
137 };
138
139 static LLVMBasicBlockRef
140 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
141 {
142 LLVMBasicBlockRef current_block;
143 LLVMBasicBlockRef next_block;
144 LLVMBasicBlockRef new_block;
145
146 /* get current basic block */
147 current_block = LLVMGetInsertBlock(ctx->ac.builder);
148
149 /* chqeck if there's another block after this one */
150 next_block = LLVMGetNextBasicBlock(current_block);
151 if (next_block) {
152 /* insert the new block before the next block */
153 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
154 }
155 else {
156 /* append new block after current block */
157 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
158 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
159 }
160 return new_block;
161 }
162
163 static void
164 ac_nir_build_if(struct ac_build_if_state *ifthen,
165 struct radv_shader_context *ctx,
166 LLVMValueRef condition)
167 {
168 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
169
170 memset(ifthen, 0, sizeof *ifthen);
171 ifthen->ctx = ctx;
172 ifthen->condition = condition;
173 ifthen->entry_block = block;
174
175 /* create endif/merge basic block for the phi functions */
176 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
177
178 /* create/insert true_block before merge_block */
179 ifthen->true_block =
180 LLVMInsertBasicBlockInContext(ctx->context,
181 ifthen->merge_block,
182 "if-true-block");
183
184 /* successive code goes into the true block */
185 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
186 }
187
188 /**
189 * End a conditional.
190 */
191 static void
192 ac_nir_build_endif(struct ac_build_if_state *ifthen)
193 {
194 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
195
196 /* Insert branch to the merge block from current block */
197 LLVMBuildBr(builder, ifthen->merge_block);
198
199 /*
200 * Now patch in the various branch instructions.
201 */
202
203 /* Insert the conditional branch instruction at the end of entry_block */
204 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
205 if (ifthen->false_block) {
206 /* we have an else clause */
207 LLVMBuildCondBr(builder, ifthen->condition,
208 ifthen->true_block, ifthen->false_block);
209 }
210 else {
211 /* no else clause */
212 LLVMBuildCondBr(builder, ifthen->condition,
213 ifthen->true_block, ifthen->merge_block);
214 }
215
216 /* Resume building code at end of the ifthen->merge_block */
217 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
218 }
219
220
221 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
222 {
223 switch (ctx->stage) {
224 case MESA_SHADER_TESS_CTRL:
225 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
226 case MESA_SHADER_TESS_EVAL:
227 return ctx->tes_rel_patch_id;
228 break;
229 default:
230 unreachable("Illegal stage");
231 }
232 }
233
234 static unsigned
235 get_tcs_num_patches(struct radv_shader_context *ctx)
236 {
237 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
238 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
239 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
240 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
241 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
242 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
243 uint32_t output_vertex_size = num_tcs_outputs * 16;
244 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
245 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
246 unsigned num_patches;
247 unsigned hardware_lds_size;
248
249 /* Ensure that we only need one wave per SIMD so we don't need to check
250 * resource usage. Also ensures that the number of tcs in and out
251 * vertices per threadgroup are at most 256.
252 */
253 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
254 /* Make sure that the data fits in LDS. This assumes the shaders only
255 * use LDS for the inputs and outputs.
256 */
257 hardware_lds_size = 32768;
258
259 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
260 * threadgroup, even though there is more than 32 KiB LDS.
261 *
262 * Test: dEQP-VK.tessellation.shader_input_output.barrier
263 */
264 if (ctx->options->chip_class >= CIK && ctx->options->family != CHIP_STONEY)
265 hardware_lds_size = 65536;
266
267 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
268 /* Make sure the output data fits in the offchip buffer */
269 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
270 /* Not necessary for correctness, but improves performance. The
271 * specific value is taken from the proprietary driver.
272 */
273 num_patches = MIN2(num_patches, 40);
274
275 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
276 if (ctx->options->chip_class == SI) {
277 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
278 num_patches = MIN2(num_patches, one_wave);
279 }
280 return num_patches;
281 }
282
283 static unsigned
284 calculate_tess_lds_size(struct radv_shader_context *ctx)
285 {
286 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
287 unsigned num_tcs_output_cp;
288 unsigned num_tcs_outputs, num_tcs_patch_outputs;
289 unsigned input_vertex_size, output_vertex_size;
290 unsigned input_patch_size, output_patch_size;
291 unsigned pervertex_output_patch_size;
292 unsigned output_patch0_offset;
293 unsigned num_patches;
294 unsigned lds_size;
295
296 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
297 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
298 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
299
300 input_vertex_size = ctx->tcs_num_inputs * 16;
301 output_vertex_size = num_tcs_outputs * 16;
302
303 input_patch_size = num_tcs_input_cp * input_vertex_size;
304
305 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
306 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
307
308 num_patches = ctx->tcs_num_patches;
309 output_patch0_offset = input_patch_size * num_patches;
310
311 lds_size = output_patch0_offset + output_patch_size * num_patches;
312 return lds_size;
313 }
314
315 /* Tessellation shaders pass outputs to the next shader using LDS.
316 *
317 * LS outputs = TCS inputs
318 * TCS outputs = TES inputs
319 *
320 * The LDS layout is:
321 * - TCS inputs for patch 0
322 * - TCS inputs for patch 1
323 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
324 * - ...
325 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
326 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
327 * - TCS outputs for patch 1
328 * - Per-patch TCS outputs for patch 1
329 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
330 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
331 * - ...
332 *
333 * All three shaders VS(LS), TCS, TES share the same LDS space.
334 */
335 static LLVMValueRef
336 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
337 {
338 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
339 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
340 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
341
342 input_patch_size /= 4;
343 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
344 }
345
346 static LLVMValueRef
347 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
348 {
349 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
350 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
351 uint32_t output_vertex_size = num_tcs_outputs * 16;
352 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
353 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
354 output_patch_size /= 4;
355 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
356 }
357
358 static LLVMValueRef
359 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
360 {
361 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
362 uint32_t output_vertex_size = num_tcs_outputs * 16;
363 output_vertex_size /= 4;
364 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
365 }
366
367 static LLVMValueRef
368 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
369 {
370 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
371 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
372 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
373 uint32_t output_patch0_offset = input_patch_size;
374 unsigned num_patches = ctx->tcs_num_patches;
375
376 output_patch0_offset *= num_patches;
377 output_patch0_offset /= 4;
378 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
379 }
380
381 static LLVMValueRef
382 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
383 {
384 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
385 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
386 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
387 uint32_t output_patch0_offset = input_patch_size;
388
389 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
390 uint32_t output_vertex_size = num_tcs_outputs * 16;
391 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
392 unsigned num_patches = ctx->tcs_num_patches;
393
394 output_patch0_offset *= num_patches;
395 output_patch0_offset += pervertex_output_patch_size;
396 output_patch0_offset /= 4;
397 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
398 }
399
400 static LLVMValueRef
401 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
402 {
403 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
404 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
405
406 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
407 }
408
409 static LLVMValueRef
410 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
411 {
412 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
413 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
414 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
415
416 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
417 patch0_offset);
418 }
419
420 static LLVMValueRef
421 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
422 {
423 LLVMValueRef patch0_patch_data_offset =
424 get_tcs_out_patch0_patch_data_offset(ctx);
425 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
426 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
427
428 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
429 patch0_patch_data_offset);
430 }
431
432 #define MAX_ARGS 64
433 struct arg_info {
434 LLVMTypeRef types[MAX_ARGS];
435 LLVMValueRef *assign[MAX_ARGS];
436 uint8_t count;
437 uint8_t sgpr_count;
438 uint8_t num_sgprs_used;
439 uint8_t num_vgprs_used;
440 };
441
442 enum ac_arg_regfile {
443 ARG_SGPR,
444 ARG_VGPR,
445 };
446
447 static void
448 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
449 LLVMValueRef *param_ptr)
450 {
451 assert(info->count < MAX_ARGS);
452
453 info->assign[info->count] = param_ptr;
454 info->types[info->count] = type;
455 info->count++;
456
457 if (regfile == ARG_SGPR) {
458 info->num_sgprs_used += ac_get_type_size(type) / 4;
459 info->sgpr_count++;
460 } else {
461 assert(regfile == ARG_VGPR);
462 info->num_vgprs_used += ac_get_type_size(type) / 4;
463 }
464 }
465
466 static void assign_arguments(LLVMValueRef main_function,
467 struct arg_info *info)
468 {
469 unsigned i;
470 for (i = 0; i < info->count; i++) {
471 if (info->assign[i])
472 *info->assign[i] = LLVMGetParam(main_function, i);
473 }
474 }
475
476 static LLVMValueRef
477 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
478 LLVMBuilderRef builder, LLVMTypeRef *return_types,
479 unsigned num_return_elems,
480 struct arg_info *args,
481 unsigned max_workgroup_size,
482 const struct radv_nir_compiler_options *options)
483 {
484 LLVMTypeRef main_function_type, ret_type;
485 LLVMBasicBlockRef main_function_body;
486
487 if (num_return_elems)
488 ret_type = LLVMStructTypeInContext(ctx, return_types,
489 num_return_elems, true);
490 else
491 ret_type = LLVMVoidTypeInContext(ctx);
492
493 /* Setup the function */
494 main_function_type =
495 LLVMFunctionType(ret_type, args->types, args->count, 0);
496 LLVMValueRef main_function =
497 LLVMAddFunction(module, "main", main_function_type);
498 main_function_body =
499 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
500 LLVMPositionBuilderAtEnd(builder, main_function_body);
501
502 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
503 for (unsigned i = 0; i < args->sgpr_count; ++i) {
504 LLVMValueRef P = LLVMGetParam(main_function, i);
505
506 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
507
508 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
509 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
510 ac_add_attr_dereferenceable(P, UINT64_MAX);
511 }
512 }
513
514 if (options->address32_hi) {
515 ac_llvm_add_target_dep_function_attr(main_function,
516 "amdgpu-32bit-address-high-bits",
517 options->address32_hi);
518 }
519
520 if (max_workgroup_size) {
521 ac_llvm_add_target_dep_function_attr(main_function,
522 "amdgpu-max-work-group-size",
523 max_workgroup_size);
524 }
525 if (options->unsafe_math) {
526 /* These were copied from some LLVM test. */
527 LLVMAddTargetDependentFunctionAttr(main_function,
528 "less-precise-fpmad",
529 "true");
530 LLVMAddTargetDependentFunctionAttr(main_function,
531 "no-infs-fp-math",
532 "true");
533 LLVMAddTargetDependentFunctionAttr(main_function,
534 "no-nans-fp-math",
535 "true");
536 LLVMAddTargetDependentFunctionAttr(main_function,
537 "unsafe-fp-math",
538 "true");
539 LLVMAddTargetDependentFunctionAttr(main_function,
540 "no-signed-zeros-fp-math",
541 "true");
542 }
543 return main_function;
544 }
545
546
547 static void
548 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx,
549 uint8_t num_sgprs)
550 {
551 ud_info->sgpr_idx = *sgpr_idx;
552 ud_info->num_sgprs = num_sgprs;
553 *sgpr_idx += num_sgprs;
554 }
555
556 static void
557 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
558 uint8_t num_sgprs)
559 {
560 struct radv_userdata_info *ud_info =
561 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
562 assert(ud_info);
563
564 set_loc(ud_info, sgpr_idx, num_sgprs);
565 }
566
567 static void
568 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
569 {
570 bool use_32bit_pointers = idx != AC_UD_SCRATCH_RING_OFFSETS;
571
572 set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
573 }
574
575 static void
576 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
577 {
578 struct radv_userdata_locations *locs =
579 &ctx->shader_info->user_sgprs_locs;
580 struct radv_userdata_info *ud_info = &locs->descriptor_sets[idx];
581 assert(ud_info);
582
583 set_loc(ud_info, sgpr_idx, 1);
584
585 locs->descriptor_sets_enabled |= 1 << idx;
586 }
587
588 struct user_sgpr_info {
589 bool need_ring_offsets;
590 bool indirect_all_descriptor_sets;
591 };
592
593 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
594 gl_shader_stage stage)
595 {
596 switch (stage) {
597 case MESA_SHADER_VERTEX:
598 if (ctx->shader_info->info.needs_multiview_view_index ||
599 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
600 return true;
601 break;
602 case MESA_SHADER_TESS_EVAL:
603 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
604 return true;
605 break;
606 case MESA_SHADER_GEOMETRY:
607 case MESA_SHADER_TESS_CTRL:
608 if (ctx->shader_info->info.needs_multiview_view_index)
609 return true;
610 break;
611 default:
612 break;
613 }
614 return false;
615 }
616
617 static uint8_t
618 count_vs_user_sgprs(struct radv_shader_context *ctx)
619 {
620 uint8_t count = 0;
621
622 if (ctx->shader_info->info.vs.has_vertex_buffers)
623 count++;
624 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
625
626 return count;
627 }
628
629 static void allocate_user_sgprs(struct radv_shader_context *ctx,
630 gl_shader_stage stage,
631 bool has_previous_stage,
632 gl_shader_stage previous_stage,
633 bool needs_view_index,
634 struct user_sgpr_info *user_sgpr_info)
635 {
636 uint8_t user_sgpr_count = 0;
637
638 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
639
640 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
641 if (stage == MESA_SHADER_GEOMETRY ||
642 stage == MESA_SHADER_VERTEX ||
643 stage == MESA_SHADER_TESS_CTRL ||
644 stage == MESA_SHADER_TESS_EVAL ||
645 ctx->is_gs_copy_shader)
646 user_sgpr_info->need_ring_offsets = true;
647
648 if (stage == MESA_SHADER_FRAGMENT &&
649 ctx->shader_info->info.ps.needs_sample_positions)
650 user_sgpr_info->need_ring_offsets = true;
651
652 /* 2 user sgprs will nearly always be allocated for scratch/rings */
653 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
654 user_sgpr_count += 2;
655 }
656
657 switch (stage) {
658 case MESA_SHADER_COMPUTE:
659 if (ctx->shader_info->info.cs.uses_grid_size)
660 user_sgpr_count += 3;
661 break;
662 case MESA_SHADER_FRAGMENT:
663 user_sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
664 break;
665 case MESA_SHADER_VERTEX:
666 if (!ctx->is_gs_copy_shader)
667 user_sgpr_count += count_vs_user_sgprs(ctx);
668 break;
669 case MESA_SHADER_TESS_CTRL:
670 if (has_previous_stage) {
671 if (previous_stage == MESA_SHADER_VERTEX)
672 user_sgpr_count += count_vs_user_sgprs(ctx);
673 }
674 break;
675 case MESA_SHADER_TESS_EVAL:
676 break;
677 case MESA_SHADER_GEOMETRY:
678 if (has_previous_stage) {
679 if (previous_stage == MESA_SHADER_VERTEX) {
680 user_sgpr_count += count_vs_user_sgprs(ctx);
681 }
682 }
683 break;
684 default:
685 break;
686 }
687
688 if (needs_view_index)
689 user_sgpr_count++;
690
691 if (ctx->shader_info->info.loads_push_constants)
692 user_sgpr_count++;
693
694 if (ctx->streamout_buffers)
695 user_sgpr_count++;
696
697 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
698 uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
699 uint32_t num_desc_set =
700 util_bitcount(ctx->shader_info->info.desc_set_used_mask);
701
702 if (remaining_sgprs < num_desc_set) {
703 user_sgpr_info->indirect_all_descriptor_sets = true;
704 }
705 }
706
707 static void
708 declare_global_input_sgprs(struct radv_shader_context *ctx,
709 const struct user_sgpr_info *user_sgpr_info,
710 struct arg_info *args,
711 LLVMValueRef *desc_sets)
712 {
713 LLVMTypeRef type = ac_array_in_const32_addr_space(ctx->ac.i8);
714
715 /* 1 for each descriptor set */
716 if (!user_sgpr_info->indirect_all_descriptor_sets) {
717 uint32_t mask = ctx->shader_info->info.desc_set_used_mask;
718
719 while (mask) {
720 int i = u_bit_scan(&mask);
721
722 add_arg(args, ARG_SGPR, type, &ctx->descriptor_sets[i]);
723 }
724 } else {
725 add_arg(args, ARG_SGPR, ac_array_in_const32_addr_space(type),
726 desc_sets);
727 }
728
729 if (ctx->shader_info->info.loads_push_constants) {
730 /* 1 for push constants and dynamic descriptors */
731 add_arg(args, ARG_SGPR, type, &ctx->abi.push_constants);
732 }
733
734 if (ctx->shader_info->info.so.num_outputs) {
735 add_arg(args, ARG_SGPR,
736 ac_array_in_const32_addr_space(ctx->ac.v4i32),
737 &ctx->streamout_buffers);
738 }
739 }
740
741 static void
742 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
743 gl_shader_stage stage,
744 bool has_previous_stage,
745 gl_shader_stage previous_stage,
746 struct arg_info *args)
747 {
748 if (!ctx->is_gs_copy_shader &&
749 (stage == MESA_SHADER_VERTEX ||
750 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
751 if (ctx->shader_info->info.vs.has_vertex_buffers) {
752 add_arg(args, ARG_SGPR,
753 ac_array_in_const32_addr_space(ctx->ac.v4i32),
754 &ctx->vertex_buffers);
755 }
756 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
757 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
758 if (ctx->shader_info->info.vs.needs_draw_id) {
759 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
760 }
761 }
762 }
763
764 static void
765 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
766 {
767 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
768 if (!ctx->is_gs_copy_shader) {
769 if (ctx->options->key.vs.as_ls) {
770 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
771 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
772 } else {
773 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
774 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
775 }
776 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
777 }
778 }
779
780 static void
781 declare_streamout_sgprs(struct radv_shader_context *ctx, gl_shader_stage stage,
782 struct arg_info *args)
783 {
784 int i;
785
786 /* Streamout SGPRs. */
787 if (ctx->shader_info->info.so.num_outputs) {
788 assert(stage == MESA_SHADER_VERTEX ||
789 stage == MESA_SHADER_TESS_EVAL);
790
791 if (stage != MESA_SHADER_TESS_EVAL) {
792 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_config);
793 } else {
794 args->assign[args->count - 1] = &ctx->streamout_config;
795 args->types[args->count - 1] = ctx->ac.i32;
796 }
797
798 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_write_idx);
799 }
800
801 /* A streamout buffer offset is loaded if the stride is non-zero. */
802 for (i = 0; i < 4; i++) {
803 if (!ctx->shader_info->info.so.strides[i])
804 continue;
805
806 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_offset[i]);
807 }
808 }
809
810 static void
811 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
812 {
813 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
814 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
815 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
816 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
817 }
818
819 static void
820 set_global_input_locs(struct radv_shader_context *ctx,
821 const struct user_sgpr_info *user_sgpr_info,
822 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
823 {
824 uint32_t mask = ctx->shader_info->info.desc_set_used_mask;
825
826 if (!user_sgpr_info->indirect_all_descriptor_sets) {
827 while (mask) {
828 int i = u_bit_scan(&mask);
829
830 set_loc_desc(ctx, i, user_sgpr_idx);
831 }
832 } else {
833 set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
834 user_sgpr_idx);
835
836 while (mask) {
837 int i = u_bit_scan(&mask);
838
839 ctx->descriptor_sets[i] =
840 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
841 LLVMConstInt(ctx->ac.i32, i, false));
842
843 }
844
845 ctx->shader_info->need_indirect_descriptor_sets = true;
846 }
847
848 if (ctx->shader_info->info.loads_push_constants) {
849 set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
850 }
851
852 if (ctx->streamout_buffers) {
853 set_loc_shader_ptr(ctx, AC_UD_STREAMOUT_BUFFERS,
854 user_sgpr_idx);
855 }
856 }
857
858 static void
859 set_vs_specific_input_locs(struct radv_shader_context *ctx,
860 gl_shader_stage stage, bool has_previous_stage,
861 gl_shader_stage previous_stage,
862 uint8_t *user_sgpr_idx)
863 {
864 if (!ctx->is_gs_copy_shader &&
865 (stage == MESA_SHADER_VERTEX ||
866 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
867 if (ctx->shader_info->info.vs.has_vertex_buffers) {
868 set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
869 user_sgpr_idx);
870 }
871
872 unsigned vs_num = 2;
873 if (ctx->shader_info->info.vs.needs_draw_id)
874 vs_num++;
875
876 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
877 user_sgpr_idx, vs_num);
878 }
879 }
880
881 static void set_llvm_calling_convention(LLVMValueRef func,
882 gl_shader_stage stage)
883 {
884 enum radeon_llvm_calling_convention calling_conv;
885
886 switch (stage) {
887 case MESA_SHADER_VERTEX:
888 case MESA_SHADER_TESS_EVAL:
889 calling_conv = RADEON_LLVM_AMDGPU_VS;
890 break;
891 case MESA_SHADER_GEOMETRY:
892 calling_conv = RADEON_LLVM_AMDGPU_GS;
893 break;
894 case MESA_SHADER_TESS_CTRL:
895 calling_conv = RADEON_LLVM_AMDGPU_HS;
896 break;
897 case MESA_SHADER_FRAGMENT:
898 calling_conv = RADEON_LLVM_AMDGPU_PS;
899 break;
900 case MESA_SHADER_COMPUTE:
901 calling_conv = RADEON_LLVM_AMDGPU_CS;
902 break;
903 default:
904 unreachable("Unhandle shader type");
905 }
906
907 LLVMSetFunctionCallConv(func, calling_conv);
908 }
909
910 static void create_function(struct radv_shader_context *ctx,
911 gl_shader_stage stage,
912 bool has_previous_stage,
913 gl_shader_stage previous_stage)
914 {
915 uint8_t user_sgpr_idx;
916 struct user_sgpr_info user_sgpr_info;
917 struct arg_info args = {};
918 LLVMValueRef desc_sets;
919 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
920 allocate_user_sgprs(ctx, stage, has_previous_stage,
921 previous_stage, needs_view_index, &user_sgpr_info);
922
923 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
924 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
925 &ctx->ring_offsets);
926 }
927
928 switch (stage) {
929 case MESA_SHADER_COMPUTE:
930 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
931 &desc_sets);
932
933 if (ctx->shader_info->info.cs.uses_grid_size) {
934 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
935 &ctx->abi.num_work_groups);
936 }
937
938 for (int i = 0; i < 3; i++) {
939 ctx->abi.workgroup_ids[i] = NULL;
940 if (ctx->shader_info->info.cs.uses_block_id[i]) {
941 add_arg(&args, ARG_SGPR, ctx->ac.i32,
942 &ctx->abi.workgroup_ids[i]);
943 }
944 }
945
946 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
947 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
948 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
949 &ctx->abi.local_invocation_ids);
950 break;
951 case MESA_SHADER_VERTEX:
952 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
953 &desc_sets);
954
955 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
956 previous_stage, &args);
957
958 if (needs_view_index)
959 add_arg(&args, ARG_SGPR, ctx->ac.i32,
960 &ctx->abi.view_index);
961 if (ctx->options->key.vs.as_es) {
962 add_arg(&args, ARG_SGPR, ctx->ac.i32,
963 &ctx->es2gs_offset);
964 } else if (ctx->options->key.vs.as_ls) {
965 /* no extra parameters */
966 } else {
967 declare_streamout_sgprs(ctx, stage, &args);
968 }
969
970 declare_vs_input_vgprs(ctx, &args);
971 break;
972 case MESA_SHADER_TESS_CTRL:
973 if (has_previous_stage) {
974 // First 6 system regs
975 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
976 add_arg(&args, ARG_SGPR, ctx->ac.i32,
977 &ctx->merged_wave_info);
978 add_arg(&args, ARG_SGPR, ctx->ac.i32,
979 &ctx->tess_factor_offset);
980
981 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
982 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
983 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
984
985 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
986 &desc_sets);
987
988 declare_vs_specific_input_sgprs(ctx, stage,
989 has_previous_stage,
990 previous_stage, &args);
991
992 if (needs_view_index)
993 add_arg(&args, ARG_SGPR, ctx->ac.i32,
994 &ctx->abi.view_index);
995
996 add_arg(&args, ARG_VGPR, ctx->ac.i32,
997 &ctx->abi.tcs_patch_id);
998 add_arg(&args, ARG_VGPR, ctx->ac.i32,
999 &ctx->abi.tcs_rel_ids);
1000
1001 declare_vs_input_vgprs(ctx, &args);
1002 } else {
1003 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1004 &desc_sets);
1005
1006 if (needs_view_index)
1007 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1008 &ctx->abi.view_index);
1009
1010 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1011 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1012 &ctx->tess_factor_offset);
1013 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1014 &ctx->abi.tcs_patch_id);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1016 &ctx->abi.tcs_rel_ids);
1017 }
1018 break;
1019 case MESA_SHADER_TESS_EVAL:
1020 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1021 &desc_sets);
1022
1023 if (needs_view_index)
1024 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1025 &ctx->abi.view_index);
1026
1027 if (ctx->options->key.tes.as_es) {
1028 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1029 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1030 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1031 &ctx->es2gs_offset);
1032 } else {
1033 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1034 declare_streamout_sgprs(ctx, stage, &args);
1035 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1036 }
1037 declare_tes_input_vgprs(ctx, &args);
1038 break;
1039 case MESA_SHADER_GEOMETRY:
1040 if (has_previous_stage) {
1041 // First 6 system regs
1042 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1043 &ctx->gs2vs_offset);
1044 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1045 &ctx->merged_wave_info);
1046 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1047
1048 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1049 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1050 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1051
1052 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1053 &desc_sets);
1054
1055 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1056 declare_vs_specific_input_sgprs(ctx, stage,
1057 has_previous_stage,
1058 previous_stage,
1059 &args);
1060 }
1061
1062 if (needs_view_index)
1063 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1064 &ctx->abi.view_index);
1065
1066 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1067 &ctx->gs_vtx_offset[0]);
1068 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1069 &ctx->gs_vtx_offset[2]);
1070 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1071 &ctx->abi.gs_prim_id);
1072 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1073 &ctx->abi.gs_invocation_id);
1074 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1075 &ctx->gs_vtx_offset[4]);
1076
1077 if (previous_stage == MESA_SHADER_VERTEX) {
1078 declare_vs_input_vgprs(ctx, &args);
1079 } else {
1080 declare_tes_input_vgprs(ctx, &args);
1081 }
1082 } else {
1083 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1084 &desc_sets);
1085
1086 if (needs_view_index)
1087 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1088 &ctx->abi.view_index);
1089
1090 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1091 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1092 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1093 &ctx->gs_vtx_offset[0]);
1094 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1095 &ctx->gs_vtx_offset[1]);
1096 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1097 &ctx->abi.gs_prim_id);
1098 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1099 &ctx->gs_vtx_offset[2]);
1100 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1101 &ctx->gs_vtx_offset[3]);
1102 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1103 &ctx->gs_vtx_offset[4]);
1104 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1105 &ctx->gs_vtx_offset[5]);
1106 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1107 &ctx->abi.gs_invocation_id);
1108 }
1109 break;
1110 case MESA_SHADER_FRAGMENT:
1111 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1112 &desc_sets);
1113
1114 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1115 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1116 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1117 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1118 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1119 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1120 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1121 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1122 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1123 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1124 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1125 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1126 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1127 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1128 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1129 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1130 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1131 break;
1132 default:
1133 unreachable("Shader stage not implemented");
1134 }
1135
1136 ctx->main_function = create_llvm_function(
1137 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1138 ctx->max_workgroup_size, ctx->options);
1139 set_llvm_calling_convention(ctx->main_function, stage);
1140
1141
1142 ctx->shader_info->num_input_vgprs = 0;
1143 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1144
1145 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1146
1147 if (ctx->stage != MESA_SHADER_FRAGMENT)
1148 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1149
1150 assign_arguments(ctx->main_function, &args);
1151
1152 user_sgpr_idx = 0;
1153
1154 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1155 set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1156 &user_sgpr_idx);
1157 if (ctx->options->supports_spill) {
1158 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1159 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
1160 NULL, 0, AC_FUNC_ATTR_READNONE);
1161 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1162 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1163 }
1164 }
1165
1166 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1167 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1168 if (has_previous_stage)
1169 user_sgpr_idx = 0;
1170
1171 set_global_input_locs(ctx, &user_sgpr_info, desc_sets, &user_sgpr_idx);
1172
1173 switch (stage) {
1174 case MESA_SHADER_COMPUTE:
1175 if (ctx->shader_info->info.cs.uses_grid_size) {
1176 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1177 &user_sgpr_idx, 3);
1178 }
1179 break;
1180 case MESA_SHADER_VERTEX:
1181 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1182 previous_stage, &user_sgpr_idx);
1183 if (ctx->abi.view_index)
1184 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1185 break;
1186 case MESA_SHADER_TESS_CTRL:
1187 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1188 previous_stage, &user_sgpr_idx);
1189 if (ctx->abi.view_index)
1190 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1191 break;
1192 case MESA_SHADER_TESS_EVAL:
1193 if (ctx->abi.view_index)
1194 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1195 break;
1196 case MESA_SHADER_GEOMETRY:
1197 if (has_previous_stage) {
1198 if (previous_stage == MESA_SHADER_VERTEX)
1199 set_vs_specific_input_locs(ctx, stage,
1200 has_previous_stage,
1201 previous_stage,
1202 &user_sgpr_idx);
1203 }
1204 if (ctx->abi.view_index)
1205 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1206 break;
1207 case MESA_SHADER_FRAGMENT:
1208 break;
1209 default:
1210 unreachable("Shader stage not implemented");
1211 }
1212
1213 if (stage == MESA_SHADER_TESS_CTRL ||
1214 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1215 /* GFX9 has the ESGS ring buffer in LDS. */
1216 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1217 ac_declare_lds_as_pointer(&ctx->ac);
1218 }
1219
1220 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1221 }
1222
1223
1224 static LLVMValueRef
1225 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1226 unsigned desc_set, unsigned binding)
1227 {
1228 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1229 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1230 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1231 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1232 unsigned base_offset = layout->binding[binding].offset;
1233 LLVMValueRef offset, stride;
1234
1235 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1236 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1237 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1238 layout->binding[binding].dynamic_offset_offset;
1239 desc_ptr = ctx->abi.push_constants;
1240 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1241 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1242 } else
1243 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1244
1245 offset = ac_build_imad(&ctx->ac, index, stride,
1246 LLVMConstInt(ctx->ac.i32, base_offset, false));
1247
1248 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1249 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1250 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1251
1252 return desc_ptr;
1253 }
1254
1255
1256 /* The offchip buffer layout for TCS->TES is
1257 *
1258 * - attribute 0 of patch 0 vertex 0
1259 * - attribute 0 of patch 0 vertex 1
1260 * - attribute 0 of patch 0 vertex 2
1261 * ...
1262 * - attribute 0 of patch 1 vertex 0
1263 * - attribute 0 of patch 1 vertex 1
1264 * ...
1265 * - attribute 1 of patch 0 vertex 0
1266 * - attribute 1 of patch 0 vertex 1
1267 * ...
1268 * - per patch attribute 0 of patch 0
1269 * - per patch attribute 0 of patch 1
1270 * ...
1271 *
1272 * Note that every attribute has 4 components.
1273 */
1274 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1275 {
1276 uint32_t num_patches = ctx->tcs_num_patches;
1277 uint32_t num_tcs_outputs;
1278 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1279 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1280 else
1281 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1282
1283 uint32_t output_vertex_size = num_tcs_outputs * 16;
1284 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1285
1286 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1287 }
1288
1289 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1290 LLVMValueRef vertex_index)
1291 {
1292 LLVMValueRef param_stride;
1293 if (vertex_index)
1294 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1295 else
1296 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1297 return param_stride;
1298 }
1299
1300 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1301 LLVMValueRef vertex_index,
1302 LLVMValueRef param_index)
1303 {
1304 LLVMValueRef base_addr;
1305 LLVMValueRef param_stride, constant16;
1306 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1307 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1308 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1309 param_stride = calc_param_stride(ctx, vertex_index);
1310 if (vertex_index) {
1311 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
1312 vertices_per_patch, vertex_index);
1313 } else {
1314 base_addr = rel_patch_id;
1315 }
1316
1317 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1318 LLVMBuildMul(ctx->ac.builder, param_index,
1319 param_stride, ""), "");
1320
1321 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1322
1323 if (!vertex_index) {
1324 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1325
1326 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1327 patch_data_offset, "");
1328 }
1329 return base_addr;
1330 }
1331
1332 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1333 unsigned param,
1334 unsigned const_index,
1335 bool is_compact,
1336 LLVMValueRef vertex_index,
1337 LLVMValueRef indir_index)
1338 {
1339 LLVMValueRef param_index;
1340
1341 if (indir_index)
1342 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1343 indir_index, "");
1344 else {
1345 if (const_index && !is_compact)
1346 param += const_index;
1347 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1348 }
1349 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1350 }
1351
1352 static LLVMValueRef
1353 get_dw_address(struct radv_shader_context *ctx,
1354 LLVMValueRef dw_addr,
1355 unsigned param,
1356 unsigned const_index,
1357 bool compact_const_index,
1358 LLVMValueRef vertex_index,
1359 LLVMValueRef stride,
1360 LLVMValueRef indir_index)
1361
1362 {
1363
1364 if (vertex_index) {
1365 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1366 LLVMBuildMul(ctx->ac.builder,
1367 vertex_index,
1368 stride, ""), "");
1369 }
1370
1371 if (indir_index)
1372 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1373 LLVMBuildMul(ctx->ac.builder, indir_index,
1374 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1375 else if (const_index && !compact_const_index)
1376 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1377 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1378
1379 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1380 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1381
1382 if (const_index && compact_const_index)
1383 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1384 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1385 return dw_addr;
1386 }
1387
1388 static LLVMValueRef
1389 load_tcs_varyings(struct ac_shader_abi *abi,
1390 LLVMTypeRef type,
1391 LLVMValueRef vertex_index,
1392 LLVMValueRef indir_index,
1393 unsigned const_index,
1394 unsigned location,
1395 unsigned driver_location,
1396 unsigned component,
1397 unsigned num_components,
1398 bool is_patch,
1399 bool is_compact,
1400 bool load_input)
1401 {
1402 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1403 LLVMValueRef dw_addr, stride;
1404 LLVMValueRef value[4], result;
1405 unsigned param = shader_io_get_unique_index(location);
1406
1407 if (load_input) {
1408 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1409 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1410 dw_addr = get_tcs_in_current_patch_offset(ctx);
1411 } else {
1412 if (!is_patch) {
1413 stride = get_tcs_out_vertex_stride(ctx);
1414 dw_addr = get_tcs_out_current_patch_offset(ctx);
1415 } else {
1416 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1417 stride = NULL;
1418 }
1419 }
1420
1421 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1422 indir_index);
1423
1424 for (unsigned i = 0; i < num_components + component; i++) {
1425 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1426 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1427 ctx->ac.i32_1, "");
1428 }
1429 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1430 return result;
1431 }
1432
1433 static void
1434 store_tcs_output(struct ac_shader_abi *abi,
1435 const nir_variable *var,
1436 LLVMValueRef vertex_index,
1437 LLVMValueRef param_index,
1438 unsigned const_index,
1439 LLVMValueRef src,
1440 unsigned writemask)
1441 {
1442 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1443 const unsigned location = var->data.location;
1444 const unsigned component = var->data.location_frac;
1445 const bool is_patch = var->data.patch;
1446 const bool is_compact = var->data.compact;
1447 LLVMValueRef dw_addr;
1448 LLVMValueRef stride = NULL;
1449 LLVMValueRef buf_addr = NULL;
1450 unsigned param;
1451 bool store_lds = true;
1452
1453 if (is_patch) {
1454 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1455 store_lds = false;
1456 } else {
1457 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1458 store_lds = false;
1459 }
1460
1461 param = shader_io_get_unique_index(location);
1462 if (location == VARYING_SLOT_CLIP_DIST0 &&
1463 is_compact && const_index > 3) {
1464 const_index -= 3;
1465 param++;
1466 }
1467
1468 if (!is_patch) {
1469 stride = get_tcs_out_vertex_stride(ctx);
1470 dw_addr = get_tcs_out_current_patch_offset(ctx);
1471 } else {
1472 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1473 }
1474
1475 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1476 param_index);
1477 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1478 vertex_index, param_index);
1479
1480 bool is_tess_factor = false;
1481 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1482 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1483 is_tess_factor = true;
1484
1485 unsigned base = is_compact ? const_index : 0;
1486 for (unsigned chan = 0; chan < 8; chan++) {
1487 if (!(writemask & (1 << chan)))
1488 continue;
1489 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1490 value = ac_to_integer(&ctx->ac, value);
1491 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
1492
1493 if (store_lds || is_tess_factor) {
1494 LLVMValueRef dw_addr_chan =
1495 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1496 LLVMConstInt(ctx->ac.i32, chan, false), "");
1497 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1498 }
1499
1500 if (!is_tess_factor && writemask != 0xF)
1501 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1502 buf_addr, ctx->oc_lds,
1503 4 * (base + chan), 1, 0, true, false);
1504 }
1505
1506 if (writemask == 0xF) {
1507 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1508 buf_addr, ctx->oc_lds,
1509 (base * 4), 1, 0, true, false);
1510 }
1511 }
1512
1513 static LLVMValueRef
1514 load_tes_input(struct ac_shader_abi *abi,
1515 LLVMTypeRef type,
1516 LLVMValueRef vertex_index,
1517 LLVMValueRef param_index,
1518 unsigned const_index,
1519 unsigned location,
1520 unsigned driver_location,
1521 unsigned component,
1522 unsigned num_components,
1523 bool is_patch,
1524 bool is_compact,
1525 bool load_input)
1526 {
1527 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1528 LLVMValueRef buf_addr;
1529 LLVMValueRef result;
1530 unsigned param = shader_io_get_unique_index(location);
1531
1532 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1533 const_index -= 3;
1534 param++;
1535 }
1536
1537 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1538 is_compact, vertex_index, param_index);
1539
1540 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1541 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1542
1543 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1544 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1545 result = ac_trim_vector(&ctx->ac, result, num_components);
1546 return result;
1547 }
1548
1549 static LLVMValueRef
1550 load_gs_input(struct ac_shader_abi *abi,
1551 unsigned location,
1552 unsigned driver_location,
1553 unsigned component,
1554 unsigned num_components,
1555 unsigned vertex_index,
1556 unsigned const_index,
1557 LLVMTypeRef type)
1558 {
1559 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1560 LLVMValueRef vtx_offset;
1561 unsigned param, vtx_offset_param;
1562 LLVMValueRef value[4], result;
1563
1564 vtx_offset_param = vertex_index;
1565 assert(vtx_offset_param < 6);
1566 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1567 LLVMConstInt(ctx->ac.i32, 4, false), "");
1568
1569 param = shader_io_get_unique_index(location);
1570
1571 for (unsigned i = component; i < num_components + component; i++) {
1572 if (ctx->ac.chip_class >= GFX9) {
1573 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1574 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1575 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1576 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1577 } else {
1578 LLVMValueRef soffset =
1579 LLVMConstInt(ctx->ac.i32,
1580 (param * 4 + i + const_index) * 256,
1581 false);
1582
1583 value[i] = ac_build_buffer_load(&ctx->ac,
1584 ctx->esgs_ring, 1,
1585 ctx->ac.i32_0,
1586 vtx_offset, soffset,
1587 0, 1, 0, true, false);
1588 }
1589
1590 if (ac_get_type_size(type) == 2) {
1591 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
1592 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
1593 }
1594 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
1595 }
1596 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1597 result = ac_to_integer(&ctx->ac, result);
1598 return result;
1599 }
1600
1601
1602 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1603 {
1604 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1605 ac_build_kill_if_false(&ctx->ac, visible);
1606 }
1607
1608 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1609 enum glsl_interp_mode interp, unsigned location)
1610 {
1611 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1612
1613 switch (interp) {
1614 case INTERP_MODE_FLAT:
1615 default:
1616 return NULL;
1617 case INTERP_MODE_SMOOTH:
1618 case INTERP_MODE_NONE:
1619 if (location == INTERP_CENTER)
1620 return ctx->persp_center;
1621 else if (location == INTERP_CENTROID)
1622 return ctx->persp_centroid;
1623 else if (location == INTERP_SAMPLE)
1624 return ctx->persp_sample;
1625 break;
1626 case INTERP_MODE_NOPERSPECTIVE:
1627 if (location == INTERP_CENTER)
1628 return ctx->linear_center;
1629 else if (location == INTERP_CENTROID)
1630 return ctx->linear_centroid;
1631 else if (location == INTERP_SAMPLE)
1632 return ctx->linear_sample;
1633 break;
1634 }
1635 return NULL;
1636 }
1637
1638 static uint32_t
1639 radv_get_sample_pos_offset(uint32_t num_samples)
1640 {
1641 uint32_t sample_pos_offset = 0;
1642
1643 switch (num_samples) {
1644 case 2:
1645 sample_pos_offset = 1;
1646 break;
1647 case 4:
1648 sample_pos_offset = 3;
1649 break;
1650 case 8:
1651 sample_pos_offset = 7;
1652 break;
1653 default:
1654 break;
1655 }
1656 return sample_pos_offset;
1657 }
1658
1659 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1660 LLVMValueRef sample_id)
1661 {
1662 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1663
1664 LLVMValueRef result;
1665 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1666
1667 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1668 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1669
1670 uint32_t sample_pos_offset =
1671 radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
1672
1673 sample_id =
1674 LLVMBuildAdd(ctx->ac.builder, sample_id,
1675 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
1676 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1677
1678 return result;
1679 }
1680
1681
1682 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1683 {
1684 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1685 uint8_t log2_ps_iter_samples;
1686
1687 if (ctx->shader_info->info.ps.force_persample) {
1688 log2_ps_iter_samples =
1689 util_logbase2(ctx->options->key.fs.num_samples);
1690 } else {
1691 log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
1692 }
1693
1694 /* The bit pattern matches that used by fixed function fragment
1695 * processing. */
1696 static const uint16_t ps_iter_masks[] = {
1697 0xffff, /* not used */
1698 0x5555,
1699 0x1111,
1700 0x0101,
1701 0x0001,
1702 };
1703 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1704
1705 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1706
1707 LLVMValueRef result, sample_id;
1708 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1709 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1710 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1711 return result;
1712 }
1713
1714
1715 static void
1716 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1717 {
1718 LLVMValueRef gs_next_vertex;
1719 LLVMValueRef can_emit;
1720 unsigned offset = 0;
1721 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1722
1723 /* Write vertex attribute values to GSVS ring */
1724 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1725 ctx->gs_next_vertex[stream],
1726 "");
1727
1728 /* If this thread has already emitted the declared maximum number of
1729 * vertices, kill it: excessive vertex emissions are not supposed to
1730 * have any effect, and GS threads have no externally observable
1731 * effects other than emitting vertices.
1732 */
1733 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1734 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1735 ac_build_kill_if_false(&ctx->ac, can_emit);
1736
1737 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1738 unsigned output_usage_mask =
1739 ctx->shader_info->info.gs.output_usage_mask[i];
1740 uint8_t output_stream =
1741 ctx->shader_info->info.gs.output_streams[i];
1742 LLVMValueRef *out_ptr = &addrs[i * 4];
1743 int length = util_last_bit(output_usage_mask);
1744
1745 if (!(ctx->output_mask & (1ull << i)) ||
1746 output_stream != stream)
1747 continue;
1748
1749 for (unsigned j = 0; j < length; j++) {
1750 if (!(output_usage_mask & (1 << j)))
1751 continue;
1752
1753 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1754 out_ptr[j], "");
1755 LLVMValueRef voffset =
1756 LLVMConstInt(ctx->ac.i32, offset *
1757 ctx->gs_max_out_vertices, false);
1758
1759 offset++;
1760
1761 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1762 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1763
1764 out_val = ac_to_integer(&ctx->ac, out_val);
1765 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1766
1767 ac_build_buffer_store_dword(&ctx->ac,
1768 ctx->gsvs_ring[stream],
1769 out_val, 1,
1770 voffset, ctx->gs2vs_offset, 0,
1771 1, 1, true, true);
1772 }
1773 }
1774
1775 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1776 ctx->ac.i32_1, "");
1777 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
1778
1779 ac_build_sendmsg(&ctx->ac,
1780 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
1781 ctx->gs_wave_id);
1782 }
1783
1784 static void
1785 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1786 {
1787 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1788 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1789 }
1790
1791 static LLVMValueRef
1792 load_tess_coord(struct ac_shader_abi *abi)
1793 {
1794 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1795
1796 LLVMValueRef coord[4] = {
1797 ctx->tes_u,
1798 ctx->tes_v,
1799 ctx->ac.f32_0,
1800 ctx->ac.f32_0,
1801 };
1802
1803 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1804 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1805 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1806
1807 return ac_build_gather_values(&ctx->ac, coord, 3);
1808 }
1809
1810 static LLVMValueRef
1811 load_patch_vertices_in(struct ac_shader_abi *abi)
1812 {
1813 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1814 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1815 }
1816
1817
1818 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1819 {
1820 return abi->base_vertex;
1821 }
1822
1823 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1824 LLVMValueRef buffer_ptr, bool write)
1825 {
1826 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1827 LLVMValueRef result;
1828
1829 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1830
1831 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1832 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1833
1834 return result;
1835 }
1836
1837 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1838 {
1839 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1840 LLVMValueRef result;
1841
1842 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1843
1844 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1845 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1846
1847 return result;
1848 }
1849
1850 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1851 unsigned descriptor_set,
1852 unsigned base_index,
1853 unsigned constant_index,
1854 LLVMValueRef index,
1855 enum ac_descriptor_type desc_type,
1856 bool image, bool write,
1857 bool bindless)
1858 {
1859 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1860 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1861 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1862 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1863 unsigned offset = binding->offset;
1864 unsigned stride = binding->size;
1865 unsigned type_size;
1866 LLVMBuilderRef builder = ctx->ac.builder;
1867 LLVMTypeRef type;
1868
1869 assert(base_index < layout->binding_count);
1870
1871 switch (desc_type) {
1872 case AC_DESC_IMAGE:
1873 type = ctx->ac.v8i32;
1874 type_size = 32;
1875 break;
1876 case AC_DESC_FMASK:
1877 type = ctx->ac.v8i32;
1878 offset += 32;
1879 type_size = 32;
1880 break;
1881 case AC_DESC_SAMPLER:
1882 type = ctx->ac.v4i32;
1883 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1884 offset += 64;
1885
1886 type_size = 16;
1887 break;
1888 case AC_DESC_BUFFER:
1889 type = ctx->ac.v4i32;
1890 type_size = 16;
1891 break;
1892 default:
1893 unreachable("invalid desc_type\n");
1894 }
1895
1896 offset += constant_index * stride;
1897
1898 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1899 (!index || binding->immutable_samplers_equal)) {
1900 if (binding->immutable_samplers_equal)
1901 constant_index = 0;
1902
1903 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1904
1905 LLVMValueRef constants[] = {
1906 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1907 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1908 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1909 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1910 };
1911 return ac_build_gather_values(&ctx->ac, constants, 4);
1912 }
1913
1914 assert(stride % type_size == 0);
1915
1916 if (!index)
1917 index = ctx->ac.i32_0;
1918
1919 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1920
1921 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1922 list = LLVMBuildPointerCast(builder, list,
1923 ac_array_in_const32_addr_space(type), "");
1924
1925 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1926 }
1927
1928 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1929 * so we may need to fix it up. */
1930 static LLVMValueRef
1931 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1932 unsigned adjustment,
1933 LLVMValueRef alpha)
1934 {
1935 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1936 return alpha;
1937
1938 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1939
1940 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1941 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1942 else
1943 alpha = ac_to_integer(&ctx->ac, alpha);
1944
1945 /* For the integer-like cases, do a natural sign extension.
1946 *
1947 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1948 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1949 * exponent.
1950 */
1951 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1952 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1953 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1954 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1955
1956 /* Convert back to the right type. */
1957 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1958 LLVMValueRef clamp;
1959 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1960 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1961 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1962 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1963 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1964 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1965 }
1966
1967 return alpha;
1968 }
1969
1970 static void
1971 handle_vs_input_decl(struct radv_shader_context *ctx,
1972 struct nir_variable *variable)
1973 {
1974 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1975 LLVMValueRef t_offset;
1976 LLVMValueRef t_list;
1977 LLVMValueRef input;
1978 LLVMValueRef buffer_index;
1979 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1980 uint8_t input_usage_mask =
1981 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1982 unsigned num_channels = util_last_bit(input_usage_mask);
1983
1984 variable->data.driver_location = variable->data.location * 4;
1985
1986 enum glsl_base_type type = glsl_get_base_type(variable->type);
1987 for (unsigned i = 0; i < attrib_count; ++i) {
1988 LLVMValueRef output[4];
1989 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1990
1991 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1992 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
1993
1994 if (divisor) {
1995 buffer_index = ctx->abi.instance_id;
1996
1997 if (divisor != 1) {
1998 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1999 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
2000 }
2001
2002 if (ctx->options->key.vs.as_ls) {
2003 ctx->shader_info->vs.vgpr_comp_cnt =
2004 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
2005 } else {
2006 ctx->shader_info->vs.vgpr_comp_cnt =
2007 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
2008 }
2009 } else {
2010 buffer_index = ctx->ac.i32_0;
2011 }
2012
2013 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index, "");
2014 } else
2015 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
2016 ctx->abi.base_vertex, "");
2017 t_offset = LLVMConstInt(ctx->ac.i32, attrib_index, false);
2018
2019 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
2020
2021 input = ac_build_buffer_load_format(&ctx->ac, t_list,
2022 buffer_index,
2023 ctx->ac.i32_0,
2024 num_channels, false, true);
2025
2026 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
2027
2028 for (unsigned chan = 0; chan < 4; chan++) {
2029 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2030 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
2031 if (type == GLSL_TYPE_FLOAT16) {
2032 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
2033 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
2034 }
2035 }
2036
2037 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
2038 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
2039
2040 for (unsigned chan = 0; chan < 4; chan++) {
2041 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
2042 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
2043 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
2044
2045 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
2046 }
2047 }
2048 }
2049
2050 static void interp_fs_input(struct radv_shader_context *ctx,
2051 unsigned attr,
2052 LLVMValueRef interp_param,
2053 LLVMValueRef prim_mask,
2054 LLVMValueRef result[4])
2055 {
2056 LLVMValueRef attr_number;
2057 unsigned chan;
2058 LLVMValueRef i, j;
2059 bool interp = !LLVMIsUndef(interp_param);
2060
2061 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
2062
2063 /* fs.constant returns the param from the middle vertex, so it's not
2064 * really useful for flat shading. It's meant to be used for custom
2065 * interpolation (but the intrinsic can't fetch from the other two
2066 * vertices).
2067 *
2068 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2069 * to do the right thing. The only reason we use fs.constant is that
2070 * fs.interp cannot be used on integers, because they can be equal
2071 * to NaN.
2072 */
2073 if (interp) {
2074 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
2075 ctx->ac.v2f32, "");
2076
2077 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2078 ctx->ac.i32_0, "");
2079 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2080 ctx->ac.i32_1, "");
2081 }
2082
2083 for (chan = 0; chan < 4; chan++) {
2084 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2085
2086 if (interp) {
2087 result[chan] = ac_build_fs_interp(&ctx->ac,
2088 llvm_chan,
2089 attr_number,
2090 prim_mask, i, j);
2091 } else {
2092 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2093 LLVMConstInt(ctx->ac.i32, 2, false),
2094 llvm_chan,
2095 attr_number,
2096 prim_mask);
2097 result[chan] = LLVMBuildBitCast(ctx->ac.builder, result[chan], ctx->ac.i32, "");
2098 result[chan] = LLVMBuildTruncOrBitCast(ctx->ac.builder, result[chan], LLVMTypeOf(interp_param), "");
2099 }
2100 }
2101 }
2102
2103 static void
2104 handle_fs_input_decl(struct radv_shader_context *ctx,
2105 struct nir_variable *variable)
2106 {
2107 int idx = variable->data.location;
2108 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2109 LLVMValueRef interp = NULL;
2110 uint64_t mask;
2111
2112 variable->data.driver_location = idx * 4;
2113 mask = ((1ull << attrib_count) - 1) << variable->data.location;
2114
2115 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
2116 unsigned interp_type;
2117 if (variable->data.sample)
2118 interp_type = INTERP_SAMPLE;
2119 else if (variable->data.centroid)
2120 interp_type = INTERP_CENTROID;
2121 else
2122 interp_type = INTERP_CENTER;
2123
2124 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
2125 }
2126 bool is_16bit = glsl_type_is_16bit(glsl_without_array(variable->type));
2127 LLVMTypeRef type = is_16bit ? ctx->ac.i16 : ctx->ac.i32;
2128 if (interp == NULL)
2129 interp = LLVMGetUndef(type);
2130
2131 for (unsigned i = 0; i < attrib_count; ++i)
2132 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
2133
2134 if (idx == VARYING_SLOT_CLIP_DIST0) {
2135 /* Do not account for the number of components inside the array
2136 * of clip/cull distances because this might wrongly set other
2137 * bits like primitive ID or layer.
2138 */
2139 mask = 1ull << VARYING_SLOT_CLIP_DIST0;
2140 }
2141
2142 ctx->input_mask |= mask;
2143 }
2144
2145 static void
2146 handle_vs_inputs(struct radv_shader_context *ctx,
2147 struct nir_shader *nir) {
2148 nir_foreach_variable(variable, &nir->inputs)
2149 handle_vs_input_decl(ctx, variable);
2150 }
2151
2152 static void
2153 prepare_interp_optimize(struct radv_shader_context *ctx,
2154 struct nir_shader *nir)
2155 {
2156 bool uses_center = false;
2157 bool uses_centroid = false;
2158 nir_foreach_variable(variable, &nir->inputs) {
2159 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2160 variable->data.sample)
2161 continue;
2162
2163 if (variable->data.centroid)
2164 uses_centroid = true;
2165 else
2166 uses_center = true;
2167 }
2168
2169 if (uses_center && uses_centroid) {
2170 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2171 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
2172 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
2173 }
2174 }
2175
2176 static void
2177 handle_fs_inputs(struct radv_shader_context *ctx,
2178 struct nir_shader *nir)
2179 {
2180 prepare_interp_optimize(ctx, nir);
2181
2182 nir_foreach_variable(variable, &nir->inputs)
2183 handle_fs_input_decl(ctx, variable);
2184
2185 unsigned index = 0;
2186
2187 if (ctx->shader_info->info.ps.uses_input_attachments ||
2188 ctx->shader_info->info.needs_multiview_view_index) {
2189 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
2190 ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)] = LLVMGetUndef(ctx->ac.i32);
2191 }
2192
2193 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
2194 LLVMValueRef interp_param;
2195 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
2196
2197 if (!(ctx->input_mask & (1ull << i)))
2198 continue;
2199
2200 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
2201 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
2202 interp_param = *inputs;
2203 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
2204 inputs);
2205
2206 if (LLVMIsUndef(interp_param))
2207 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
2208 if (i >= VARYING_SLOT_VAR0)
2209 ctx->abi.fs_input_attr_indices[i - VARYING_SLOT_VAR0] = index;
2210 ++index;
2211 } else if (i == VARYING_SLOT_CLIP_DIST0) {
2212 int length = ctx->shader_info->info.ps.num_input_clips_culls;
2213
2214 for (unsigned j = 0; j < length; j += 4) {
2215 inputs = ctx->inputs + ac_llvm_reg_index_soa(i, j);
2216
2217 interp_param = *inputs;
2218 interp_fs_input(ctx, index, interp_param,
2219 ctx->abi.prim_mask, inputs);
2220 ++index;
2221 }
2222 } else if (i == VARYING_SLOT_POS) {
2223 for(int i = 0; i < 3; ++i)
2224 inputs[i] = ctx->abi.frag_pos[i];
2225
2226 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2227 ctx->abi.frag_pos[3]);
2228 }
2229 }
2230 ctx->shader_info->fs.num_interp = index;
2231 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
2232
2233 if (ctx->shader_info->info.needs_multiview_view_index)
2234 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2235 }
2236
2237 static void
2238 scan_shader_output_decl(struct radv_shader_context *ctx,
2239 struct nir_variable *variable,
2240 struct nir_shader *shader,
2241 gl_shader_stage stage)
2242 {
2243 int idx = variable->data.location + variable->data.index;
2244 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2245 uint64_t mask_attribs;
2246
2247 variable->data.driver_location = idx * 4;
2248
2249 /* tess ctrl has it's own load/store paths for outputs */
2250 if (stage == MESA_SHADER_TESS_CTRL)
2251 return;
2252
2253 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2254 if (stage == MESA_SHADER_VERTEX ||
2255 stage == MESA_SHADER_TESS_EVAL ||
2256 stage == MESA_SHADER_GEOMETRY) {
2257 if (idx == VARYING_SLOT_CLIP_DIST0) {
2258 if (stage == MESA_SHADER_VERTEX) {
2259 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2260 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2261 ctx->shader_info->vs.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
2262 }
2263 if (stage == MESA_SHADER_TESS_EVAL) {
2264 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2265 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2266 ctx->shader_info->tes.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
2267 }
2268
2269 mask_attribs = 1ull << idx;
2270 }
2271 }
2272
2273 ctx->output_mask |= mask_attribs;
2274 }
2275
2276
2277 /* Initialize arguments for the shader export intrinsic */
2278 static void
2279 si_llvm_init_export_args(struct radv_shader_context *ctx,
2280 LLVMValueRef *values,
2281 unsigned enabled_channels,
2282 unsigned target,
2283 struct ac_export_args *args)
2284 {
2285 /* Specify the channels that are enabled. */
2286 args->enabled_channels = enabled_channels;
2287
2288 /* Specify whether the EXEC mask represents the valid mask */
2289 args->valid_mask = 0;
2290
2291 /* Specify whether this is the last export */
2292 args->done = 0;
2293
2294 /* Specify the target we are exporting */
2295 args->target = target;
2296
2297 args->compr = false;
2298 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2299 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2300 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2301 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2302
2303 if (!values)
2304 return;
2305
2306 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
2307 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2308 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2309 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2310 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2311 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2312 unsigned chan;
2313
2314 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2315 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2316 unsigned bits, bool hi) = NULL;
2317
2318 switch(col_format) {
2319 case V_028714_SPI_SHADER_ZERO:
2320 args->enabled_channels = 0; /* writemask */
2321 args->target = V_008DFC_SQ_EXP_NULL;
2322 break;
2323
2324 case V_028714_SPI_SHADER_32_R:
2325 args->enabled_channels = 1;
2326 args->out[0] = values[0];
2327 break;
2328
2329 case V_028714_SPI_SHADER_32_GR:
2330 args->enabled_channels = 0x3;
2331 args->out[0] = values[0];
2332 args->out[1] = values[1];
2333 break;
2334
2335 case V_028714_SPI_SHADER_32_AR:
2336 args->enabled_channels = 0x9;
2337 args->out[0] = values[0];
2338 args->out[3] = values[3];
2339 break;
2340
2341 case V_028714_SPI_SHADER_FP16_ABGR:
2342 args->enabled_channels = 0x5;
2343 packf = ac_build_cvt_pkrtz_f16;
2344 if (is_16bit) {
2345 for (unsigned chan = 0; chan < 4; chan++)
2346 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
2347 values[chan],
2348 ctx->ac.f32, "");
2349 }
2350 break;
2351
2352 case V_028714_SPI_SHADER_UNORM16_ABGR:
2353 args->enabled_channels = 0x5;
2354 packf = ac_build_cvt_pknorm_u16;
2355 break;
2356
2357 case V_028714_SPI_SHADER_SNORM16_ABGR:
2358 args->enabled_channels = 0x5;
2359 packf = ac_build_cvt_pknorm_i16;
2360 break;
2361
2362 case V_028714_SPI_SHADER_UINT16_ABGR:
2363 args->enabled_channels = 0x5;
2364 packi = ac_build_cvt_pk_u16;
2365 if (is_16bit) {
2366 for (unsigned chan = 0; chan < 4; chan++)
2367 values[chan] = LLVMBuildZExt(ctx->ac.builder,
2368 values[chan],
2369 ctx->ac.i32, "");
2370 }
2371 break;
2372
2373 case V_028714_SPI_SHADER_SINT16_ABGR:
2374 args->enabled_channels = 0x5;
2375 packi = ac_build_cvt_pk_i16;
2376 if (is_16bit) {
2377 for (unsigned chan = 0; chan < 4; chan++)
2378 values[chan] = LLVMBuildSExt(ctx->ac.builder,
2379 values[chan],
2380 ctx->ac.i32, "");
2381 }
2382 break;
2383
2384 default:
2385 case V_028714_SPI_SHADER_32_ABGR:
2386 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2387 break;
2388 }
2389
2390 /* Pack f16 or norm_i16/u16. */
2391 if (packf) {
2392 for (chan = 0; chan < 2; chan++) {
2393 LLVMValueRef pack_args[2] = {
2394 values[2 * chan],
2395 values[2 * chan + 1]
2396 };
2397 LLVMValueRef packed;
2398
2399 packed = packf(&ctx->ac, pack_args);
2400 args->out[chan] = ac_to_float(&ctx->ac, packed);
2401 }
2402 args->compr = 1; /* COMPR flag */
2403 }
2404
2405 /* Pack i16/u16. */
2406 if (packi) {
2407 for (chan = 0; chan < 2; chan++) {
2408 LLVMValueRef pack_args[2] = {
2409 ac_to_integer(&ctx->ac, values[2 * chan]),
2410 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2411 };
2412 LLVMValueRef packed;
2413
2414 packed = packi(&ctx->ac, pack_args,
2415 is_int8 ? 8 : is_int10 ? 10 : 16,
2416 chan == 1);
2417 args->out[chan] = ac_to_float(&ctx->ac, packed);
2418 }
2419 args->compr = 1; /* COMPR flag */
2420 }
2421 return;
2422 }
2423
2424 if (is_16bit) {
2425 for (unsigned chan = 0; chan < 4; chan++) {
2426 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
2427 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
2428 }
2429 } else
2430 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2431
2432 for (unsigned i = 0; i < 4; ++i) {
2433 if (!(args->enabled_channels & (1 << i)))
2434 continue;
2435
2436 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2437 }
2438 }
2439
2440 static void
2441 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2442 LLVMValueRef *values, unsigned enabled_channels)
2443 {
2444 struct ac_export_args args;
2445
2446 si_llvm_init_export_args(ctx, values, enabled_channels,
2447 V_008DFC_SQ_EXP_PARAM + index, &args);
2448 ac_build_export(&ctx->ac, &args);
2449 }
2450
2451 static LLVMValueRef
2452 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2453 {
2454 LLVMValueRef output =
2455 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2456
2457 return LLVMBuildLoad(ctx->ac.builder, output, "");
2458 }
2459
2460 static void
2461 radv_emit_stream_output(struct radv_shader_context *ctx,
2462 LLVMValueRef const *so_buffers,
2463 LLVMValueRef const *so_write_offsets,
2464 const struct radv_stream_output *output)
2465 {
2466 unsigned num_comps = util_bitcount(output->component_mask);
2467 unsigned loc = output->location;
2468 unsigned buf = output->buffer;
2469 unsigned offset = output->offset;
2470 unsigned start;
2471 LLVMValueRef out[4];
2472
2473 assert(num_comps && num_comps <= 4);
2474 if (!num_comps || num_comps > 4)
2475 return;
2476
2477 /* Get the first component. */
2478 start = ffs(output->component_mask) - 1;
2479
2480 /* Load the output as int. */
2481 for (int i = 0; i < num_comps; i++) {
2482 out[i] = ac_to_integer(&ctx->ac,
2483 radv_load_output(ctx, loc, start + i));
2484 }
2485
2486 /* Pack the output. */
2487 LLVMValueRef vdata = NULL;
2488
2489 switch (num_comps) {
2490 case 1: /* as i32 */
2491 vdata = out[0];
2492 break;
2493 case 2: /* as v2i32 */
2494 case 3: /* as v4i32 (aligned to 4) */
2495 out[3] = LLVMGetUndef(ctx->ac.i32);
2496 /* fall through */
2497 case 4: /* as v4i32 */
2498 vdata = ac_build_gather_values(&ctx->ac, out,
2499 util_next_power_of_two(num_comps));
2500 break;
2501 }
2502
2503 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
2504 vdata, num_comps, so_write_offsets[buf],
2505 ctx->ac.i32_0, offset,
2506 1, 1, true, false);
2507 }
2508
2509 static void
2510 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
2511 {
2512 struct ac_build_if_state if_ctx;
2513 int i;
2514
2515 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2516 assert(ctx->streamout_config);
2517 LLVMValueRef so_vtx_count =
2518 ac_build_bfe(&ctx->ac, ctx->streamout_config,
2519 LLVMConstInt(ctx->ac.i32, 16, false),
2520 LLVMConstInt(ctx->ac.i32, 7, false), false);
2521
2522 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2523
2524 /* can_emit = tid < so_vtx_count; */
2525 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
2526 tid, so_vtx_count, "");
2527
2528 /* Emit the streamout code conditionally. This actually avoids
2529 * out-of-bounds buffer access. The hw tells us via the SGPR
2530 * (so_vtx_count) which threads are allowed to emit streamout data.
2531 */
2532 ac_nir_build_if(&if_ctx, ctx, can_emit);
2533 {
2534 /* The buffer offset is computed as follows:
2535 * ByteOffset = streamout_offset[buffer_id]*4 +
2536 * (streamout_write_index + thread_id)*stride[buffer_id] +
2537 * attrib_offset
2538 */
2539 LLVMValueRef so_write_index = ctx->streamout_write_idx;
2540
2541 /* Compute (streamout_write_index + thread_id). */
2542 so_write_index =
2543 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
2544
2545 /* Load the descriptor and compute the write offset for each
2546 * enabled buffer.
2547 */
2548 LLVMValueRef so_write_offset[4] = {};
2549 LLVMValueRef so_buffers[4] = {};
2550 LLVMValueRef buf_ptr = ctx->streamout_buffers;
2551
2552 for (i = 0; i < 4; i++) {
2553 uint16_t stride = ctx->shader_info->info.so.strides[i];
2554
2555 if (!stride)
2556 continue;
2557
2558 LLVMValueRef offset =
2559 LLVMConstInt(ctx->ac.i32, i, false);
2560
2561 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
2562 buf_ptr, offset);
2563
2564 LLVMValueRef so_offset = ctx->streamout_offset[i];
2565
2566 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
2567 LLVMConstInt(ctx->ac.i32, 4, false), "");
2568
2569 so_write_offset[i] =
2570 ac_build_imad(&ctx->ac, so_write_index,
2571 LLVMConstInt(ctx->ac.i32,
2572 stride * 4, false),
2573 so_offset);
2574 }
2575
2576 /* Write streamout data. */
2577 for (i = 0; i < ctx->shader_info->info.so.num_outputs; i++) {
2578 struct radv_stream_output *output =
2579 &ctx->shader_info->info.so.outputs[i];
2580
2581 if (stream != output->stream)
2582 continue;
2583
2584 radv_emit_stream_output(ctx, so_buffers,
2585 so_write_offset, output);
2586 }
2587 }
2588 ac_nir_build_endif(&if_ctx);
2589 }
2590
2591 static void
2592 handle_vs_outputs_post(struct radv_shader_context *ctx,
2593 bool export_prim_id, bool export_layer_id,
2594 struct radv_vs_output_info *outinfo)
2595 {
2596 uint32_t param_count = 0;
2597 unsigned target;
2598 unsigned pos_idx, num_pos_exports = 0;
2599 struct ac_export_args args, pos_args[4] = {};
2600 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2601 int i;
2602
2603 if (ctx->options->key.has_multiview_view_index) {
2604 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2605 if(!*tmp_out) {
2606 for(unsigned i = 0; i < 4; ++i)
2607 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2608 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2609 }
2610
2611 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2612 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2613 }
2614
2615 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2616 sizeof(outinfo->vs_output_param_offset));
2617
2618 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2619 unsigned output_usage_mask, length;
2620 LLVMValueRef slots[8];
2621 unsigned j;
2622
2623 if (ctx->stage == MESA_SHADER_VERTEX &&
2624 !ctx->is_gs_copy_shader) {
2625 output_usage_mask =
2626 ctx->shader_info->info.vs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2627 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2628 output_usage_mask =
2629 ctx->shader_info->info.tes.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2630 } else {
2631 assert(ctx->is_gs_copy_shader);
2632 output_usage_mask =
2633 ctx->shader_info->info.gs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2634 }
2635
2636 length = util_last_bit(output_usage_mask);
2637
2638 i = VARYING_SLOT_CLIP_DIST0;
2639 for (j = 0; j < length; j++)
2640 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2641
2642 for (i = length; i < 8; i++)
2643 slots[i] = LLVMGetUndef(ctx->ac.f32);
2644
2645 if (length > 4) {
2646 target = V_008DFC_SQ_EXP_POS + 3;
2647 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2648 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2649 &args, sizeof(args));
2650 }
2651
2652 target = V_008DFC_SQ_EXP_POS + 2;
2653 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2654 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2655 &args, sizeof(args));
2656
2657 /* Export the clip/cull distances values to the next stage. */
2658 radv_export_param(ctx, param_count, &slots[0], 0xf);
2659 outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0] = param_count++;
2660 if (length > 4) {
2661 radv_export_param(ctx, param_count, &slots[4], 0xf);
2662 outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1] = param_count++;
2663 }
2664 }
2665
2666 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2667 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2668 for (unsigned j = 0; j < 4; j++)
2669 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2670 }
2671 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2672
2673 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2674 outinfo->writes_pointsize = true;
2675 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2676 }
2677
2678 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2679 outinfo->writes_layer = true;
2680 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2681 }
2682
2683 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2684 outinfo->writes_viewport_index = true;
2685 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2686 }
2687
2688 if (ctx->shader_info->info.so.num_outputs &&
2689 !ctx->is_gs_copy_shader) {
2690 /* The GS copy shader emission already emits streamout. */
2691 radv_emit_streamout(ctx, 0);
2692 }
2693
2694 if (outinfo->writes_pointsize ||
2695 outinfo->writes_layer ||
2696 outinfo->writes_viewport_index) {
2697 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2698 (outinfo->writes_layer == true ? 4 : 0));
2699 pos_args[1].valid_mask = 0;
2700 pos_args[1].done = 0;
2701 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2702 pos_args[1].compr = 0;
2703 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2704 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2705 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2706 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2707
2708 if (outinfo->writes_pointsize == true)
2709 pos_args[1].out[0] = psize_value;
2710 if (outinfo->writes_layer == true)
2711 pos_args[1].out[2] = layer_value;
2712 if (outinfo->writes_viewport_index == true) {
2713 if (ctx->options->chip_class >= GFX9) {
2714 /* GFX9 has the layer in out.z[10:0] and the viewport
2715 * index in out.z[19:16].
2716 */
2717 LLVMValueRef v = viewport_index_value;
2718 v = ac_to_integer(&ctx->ac, v);
2719 v = LLVMBuildShl(ctx->ac.builder, v,
2720 LLVMConstInt(ctx->ac.i32, 16, false),
2721 "");
2722 v = LLVMBuildOr(ctx->ac.builder, v,
2723 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2724
2725 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2726 pos_args[1].enabled_channels |= 1 << 2;
2727 } else {
2728 pos_args[1].out[3] = viewport_index_value;
2729 pos_args[1].enabled_channels |= 1 << 3;
2730 }
2731 }
2732 }
2733 for (i = 0; i < 4; i++) {
2734 if (pos_args[i].out[0])
2735 num_pos_exports++;
2736 }
2737
2738 pos_idx = 0;
2739 for (i = 0; i < 4; i++) {
2740 if (!pos_args[i].out[0])
2741 continue;
2742
2743 /* Specify the target we are exporting */
2744 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2745 if (pos_idx == num_pos_exports)
2746 pos_args[i].done = 1;
2747 ac_build_export(&ctx->ac, &pos_args[i]);
2748 }
2749
2750 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2751 LLVMValueRef values[4];
2752 if (!(ctx->output_mask & (1ull << i)))
2753 continue;
2754
2755 if (i != VARYING_SLOT_LAYER &&
2756 i != VARYING_SLOT_PRIMITIVE_ID &&
2757 i < VARYING_SLOT_VAR0)
2758 continue;
2759
2760 for (unsigned j = 0; j < 4; j++)
2761 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2762
2763 unsigned output_usage_mask;
2764
2765 if (ctx->stage == MESA_SHADER_VERTEX &&
2766 !ctx->is_gs_copy_shader) {
2767 output_usage_mask =
2768 ctx->shader_info->info.vs.output_usage_mask[i];
2769 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2770 output_usage_mask =
2771 ctx->shader_info->info.tes.output_usage_mask[i];
2772 } else {
2773 assert(ctx->is_gs_copy_shader);
2774 output_usage_mask =
2775 ctx->shader_info->info.gs.output_usage_mask[i];
2776 }
2777
2778 radv_export_param(ctx, param_count, values, output_usage_mask);
2779
2780 outinfo->vs_output_param_offset[i] = param_count++;
2781 }
2782
2783 if (export_prim_id) {
2784 LLVMValueRef values[4];
2785
2786 values[0] = ctx->vs_prim_id;
2787 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2788 ctx->shader_info->vs.vgpr_comp_cnt);
2789 for (unsigned j = 1; j < 4; j++)
2790 values[j] = ctx->ac.f32_0;
2791
2792 radv_export_param(ctx, param_count, values, 0x1);
2793
2794 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2795 outinfo->export_prim_id = true;
2796 }
2797
2798 if (export_layer_id && layer_value) {
2799 LLVMValueRef values[4];
2800
2801 values[0] = layer_value;
2802 for (unsigned j = 1; j < 4; j++)
2803 values[j] = ctx->ac.f32_0;
2804
2805 radv_export_param(ctx, param_count, values, 0x1);
2806
2807 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2808 }
2809
2810 outinfo->pos_exports = num_pos_exports;
2811 outinfo->param_exports = param_count;
2812 }
2813
2814 static void
2815 handle_es_outputs_post(struct radv_shader_context *ctx,
2816 struct radv_es_output_info *outinfo)
2817 {
2818 int j;
2819 uint64_t max_output_written = 0;
2820 LLVMValueRef lds_base = NULL;
2821
2822 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2823 unsigned output_usage_mask;
2824 int param_index;
2825 int length = 4;
2826
2827 if (!(ctx->output_mask & (1ull << i)))
2828 continue;
2829
2830 if (ctx->stage == MESA_SHADER_VERTEX) {
2831 output_usage_mask =
2832 ctx->shader_info->info.vs.output_usage_mask[i];
2833 } else {
2834 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2835 output_usage_mask =
2836 ctx->shader_info->info.tes.output_usage_mask[i];
2837 }
2838
2839 if (i == VARYING_SLOT_CLIP_DIST0)
2840 length = util_last_bit(output_usage_mask);
2841
2842 param_index = shader_io_get_unique_index(i);
2843
2844 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2845 }
2846
2847 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2848
2849 if (ctx->ac.chip_class >= GFX9) {
2850 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2851 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2852 LLVMValueRef wave_idx = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
2853 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2854 LLVMBuildMul(ctx->ac.builder, wave_idx,
2855 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2856 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2857 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2858 }
2859
2860 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2861 LLVMValueRef dw_addr = NULL;
2862 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2863 unsigned output_usage_mask;
2864 int param_index;
2865 int length = 4;
2866
2867 if (!(ctx->output_mask & (1ull << i)))
2868 continue;
2869
2870 if (ctx->stage == MESA_SHADER_VERTEX) {
2871 output_usage_mask =
2872 ctx->shader_info->info.vs.output_usage_mask[i];
2873 } else {
2874 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2875 output_usage_mask =
2876 ctx->shader_info->info.tes.output_usage_mask[i];
2877 }
2878
2879 if (i == VARYING_SLOT_CLIP_DIST0)
2880 length = util_last_bit(output_usage_mask);
2881
2882 param_index = shader_io_get_unique_index(i);
2883
2884 if (lds_base) {
2885 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2886 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2887 "");
2888 }
2889
2890 for (j = 0; j < length; j++) {
2891 if (!(output_usage_mask & (1 << j)))
2892 continue;
2893
2894 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2895 out_val = ac_to_integer(&ctx->ac, out_val);
2896 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2897
2898 if (ctx->ac.chip_class >= GFX9) {
2899 LLVMValueRef dw_addr_offset =
2900 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2901 LLVMConstInt(ctx->ac.i32,
2902 j, false), "");
2903
2904 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2905 } else {
2906 ac_build_buffer_store_dword(&ctx->ac,
2907 ctx->esgs_ring,
2908 out_val, 1,
2909 NULL, ctx->es2gs_offset,
2910 (4 * param_index + j) * 4,
2911 1, 1, true, true);
2912 }
2913 }
2914 }
2915 }
2916
2917 static void
2918 handle_ls_outputs_post(struct radv_shader_context *ctx)
2919 {
2920 LLVMValueRef vertex_id = ctx->rel_auto_id;
2921 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2922 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2923 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2924 vertex_dw_stride, "");
2925
2926 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2927 unsigned output_usage_mask =
2928 ctx->shader_info->info.vs.output_usage_mask[i];
2929 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2930 int length = 4;
2931
2932 if (!(ctx->output_mask & (1ull << i)))
2933 continue;
2934
2935 if (i == VARYING_SLOT_CLIP_DIST0)
2936 length = util_last_bit(output_usage_mask);
2937
2938 int param = shader_io_get_unique_index(i);
2939 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2940 LLVMConstInt(ctx->ac.i32, param * 4, false),
2941 "");
2942 for (unsigned j = 0; j < length; j++) {
2943 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2944 value = ac_to_integer(&ctx->ac, value);
2945 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2946 ac_lds_store(&ctx->ac, dw_addr, value);
2947 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2948 }
2949 }
2950 }
2951
2952 static void
2953 write_tess_factors(struct radv_shader_context *ctx)
2954 {
2955 unsigned stride, outer_comps, inner_comps;
2956 struct ac_build_if_state if_ctx, inner_if_ctx;
2957 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2958 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2959 unsigned tess_inner_index = 0, tess_outer_index;
2960 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2961 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2962 int i;
2963 ac_emit_barrier(&ctx->ac, ctx->stage);
2964
2965 switch (ctx->options->key.tcs.primitive_mode) {
2966 case GL_ISOLINES:
2967 stride = 2;
2968 outer_comps = 2;
2969 inner_comps = 0;
2970 break;
2971 case GL_TRIANGLES:
2972 stride = 4;
2973 outer_comps = 3;
2974 inner_comps = 1;
2975 break;
2976 case GL_QUADS:
2977 stride = 6;
2978 outer_comps = 4;
2979 inner_comps = 2;
2980 break;
2981 default:
2982 return;
2983 }
2984
2985 ac_nir_build_if(&if_ctx, ctx,
2986 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2987 invocation_id, ctx->ac.i32_0, ""));
2988
2989 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2990
2991 if (inner_comps) {
2992 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2993 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2994 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2995 }
2996
2997 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2998 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2999 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3000
3001 for (i = 0; i < 4; i++) {
3002 inner[i] = LLVMGetUndef(ctx->ac.i32);
3003 outer[i] = LLVMGetUndef(ctx->ac.i32);
3004 }
3005
3006 // LINES reversal
3007 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
3008 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3009 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3010 ctx->ac.i32_1, "");
3011 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3012 } else {
3013 for (i = 0; i < outer_comps; i++) {
3014 outer[i] = out[i] =
3015 ac_lds_load(&ctx->ac, lds_outer);
3016 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3017 ctx->ac.i32_1, "");
3018 }
3019 for (i = 0; i < inner_comps; i++) {
3020 inner[i] = out[outer_comps+i] =
3021 ac_lds_load(&ctx->ac, lds_inner);
3022 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3023 ctx->ac.i32_1, "");
3024 }
3025 }
3026
3027 /* Convert the outputs to vectors for stores. */
3028 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3029 vec1 = NULL;
3030
3031 if (stride > 4)
3032 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3033
3034
3035 buffer = ctx->hs_ring_tess_factor;
3036 tf_base = ctx->tess_factor_offset;
3037 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3038 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3039 unsigned tf_offset = 0;
3040
3041 if (ctx->options->chip_class <= VI) {
3042 ac_nir_build_if(&inner_if_ctx, ctx,
3043 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3044 rel_patch_id, ctx->ac.i32_0, ""));
3045
3046 /* Store the dynamic HS control word. */
3047 ac_build_buffer_store_dword(&ctx->ac, buffer,
3048 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3049 1, ctx->ac.i32_0, tf_base,
3050 0, 1, 0, true, false);
3051 tf_offset += 4;
3052
3053 ac_nir_build_endif(&inner_if_ctx);
3054 }
3055
3056 /* Store the tessellation factors. */
3057 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3058 MIN2(stride, 4), byteoffset, tf_base,
3059 tf_offset, 1, 0, true, false);
3060 if (vec1)
3061 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3062 stride - 4, byteoffset, tf_base,
3063 16 + tf_offset, 1, 0, true, false);
3064
3065 //store to offchip for TES to read - only if TES reads them
3066 if (ctx->options->key.tcs.tes_reads_tess_factors) {
3067 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3068 LLVMValueRef tf_inner_offset;
3069 unsigned param_outer, param_inner;
3070
3071 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3072 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3073 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3074
3075 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3076 util_next_power_of_two(outer_comps));
3077
3078 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3079 outer_comps, tf_outer_offset,
3080 ctx->oc_lds, 0, 1, 0, true, false);
3081 if (inner_comps) {
3082 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3083 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3084 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3085
3086 inner_vec = inner_comps == 1 ? inner[0] :
3087 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3088 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3089 inner_comps, tf_inner_offset,
3090 ctx->oc_lds, 0, 1, 0, true, false);
3091 }
3092 }
3093 ac_nir_build_endif(&if_ctx);
3094 }
3095
3096 static void
3097 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3098 {
3099 write_tess_factors(ctx);
3100 }
3101
3102 static bool
3103 si_export_mrt_color(struct radv_shader_context *ctx,
3104 LLVMValueRef *color, unsigned index,
3105 struct ac_export_args *args)
3106 {
3107 /* Export */
3108 si_llvm_init_export_args(ctx, color, 0xf,
3109 V_008DFC_SQ_EXP_MRT + index, args);
3110 if (!args->enabled_channels)
3111 return false; /* unnecessary NULL export */
3112
3113 return true;
3114 }
3115
3116 static void
3117 radv_export_mrt_z(struct radv_shader_context *ctx,
3118 LLVMValueRef depth, LLVMValueRef stencil,
3119 LLVMValueRef samplemask)
3120 {
3121 struct ac_export_args args;
3122
3123 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3124
3125 ac_build_export(&ctx->ac, &args);
3126 }
3127
3128 static void
3129 handle_fs_outputs_post(struct radv_shader_context *ctx)
3130 {
3131 unsigned index = 0;
3132 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3133 struct ac_export_args color_args[8];
3134
3135 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3136 LLVMValueRef values[4];
3137
3138 if (!(ctx->output_mask & (1ull << i)))
3139 continue;
3140
3141 if (i < FRAG_RESULT_DATA0)
3142 continue;
3143
3144 for (unsigned j = 0; j < 4; j++)
3145 values[j] = ac_to_float(&ctx->ac,
3146 radv_load_output(ctx, i, j));
3147
3148 bool ret = si_export_mrt_color(ctx, values,
3149 i - FRAG_RESULT_DATA0,
3150 &color_args[index]);
3151 if (ret)
3152 index++;
3153 }
3154
3155 /* Process depth, stencil, samplemask. */
3156 if (ctx->shader_info->info.ps.writes_z) {
3157 depth = ac_to_float(&ctx->ac,
3158 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3159 }
3160 if (ctx->shader_info->info.ps.writes_stencil) {
3161 stencil = ac_to_float(&ctx->ac,
3162 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3163 }
3164 if (ctx->shader_info->info.ps.writes_sample_mask) {
3165 samplemask = ac_to_float(&ctx->ac,
3166 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3167 }
3168
3169 /* Set the DONE bit on last non-null color export only if Z isn't
3170 * exported.
3171 */
3172 if (index > 0 &&
3173 !ctx->shader_info->info.ps.writes_z &&
3174 !ctx->shader_info->info.ps.writes_stencil &&
3175 !ctx->shader_info->info.ps.writes_sample_mask) {
3176 unsigned last = index - 1;
3177
3178 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3179 color_args[last].done = 1; /* DONE bit */
3180 }
3181
3182 /* Export PS outputs. */
3183 for (unsigned i = 0; i < index; i++)
3184 ac_build_export(&ctx->ac, &color_args[i]);
3185
3186 if (depth || stencil || samplemask)
3187 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3188 else if (!index)
3189 ac_build_export_null(&ctx->ac);
3190 }
3191
3192 static void
3193 emit_gs_epilogue(struct radv_shader_context *ctx)
3194 {
3195 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3196 }
3197
3198 static void
3199 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3200 LLVMValueRef *addrs)
3201 {
3202 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3203
3204 switch (ctx->stage) {
3205 case MESA_SHADER_VERTEX:
3206 if (ctx->options->key.vs.as_ls)
3207 handle_ls_outputs_post(ctx);
3208 else if (ctx->options->key.vs.as_es)
3209 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
3210 else
3211 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
3212 ctx->options->key.vs.export_layer_id,
3213 &ctx->shader_info->vs.outinfo);
3214 break;
3215 case MESA_SHADER_FRAGMENT:
3216 handle_fs_outputs_post(ctx);
3217 break;
3218 case MESA_SHADER_GEOMETRY:
3219 emit_gs_epilogue(ctx);
3220 break;
3221 case MESA_SHADER_TESS_CTRL:
3222 handle_tcs_outputs_post(ctx);
3223 break;
3224 case MESA_SHADER_TESS_EVAL:
3225 if (ctx->options->key.tes.as_es)
3226 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
3227 else
3228 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
3229 ctx->options->key.tes.export_layer_id,
3230 &ctx->shader_info->tes.outinfo);
3231 break;
3232 default:
3233 break;
3234 }
3235 }
3236
3237 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3238 LLVMPassManagerRef passmgr,
3239 const struct radv_nir_compiler_options *options)
3240 {
3241 LLVMRunPassManager(passmgr, ctx->ac.module);
3242 LLVMDisposeBuilder(ctx->ac.builder);
3243
3244 ac_llvm_context_dispose(&ctx->ac);
3245 }
3246
3247 static void
3248 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3249 {
3250 struct radv_vs_output_info *outinfo;
3251
3252 switch (ctx->stage) {
3253 case MESA_SHADER_FRAGMENT:
3254 case MESA_SHADER_COMPUTE:
3255 case MESA_SHADER_TESS_CTRL:
3256 case MESA_SHADER_GEOMETRY:
3257 return;
3258 case MESA_SHADER_VERTEX:
3259 if (ctx->options->key.vs.as_ls ||
3260 ctx->options->key.vs.as_es)
3261 return;
3262 outinfo = &ctx->shader_info->vs.outinfo;
3263 break;
3264 case MESA_SHADER_TESS_EVAL:
3265 if (ctx->options->key.vs.as_es)
3266 return;
3267 outinfo = &ctx->shader_info->tes.outinfo;
3268 break;
3269 default:
3270 unreachable("Unhandled shader type");
3271 }
3272
3273 ac_optimize_vs_outputs(&ctx->ac,
3274 ctx->main_function,
3275 outinfo->vs_output_param_offset,
3276 VARYING_SLOT_MAX,
3277 &outinfo->param_exports);
3278 }
3279
3280 static void
3281 ac_setup_rings(struct radv_shader_context *ctx)
3282 {
3283 if (ctx->options->chip_class <= VI &&
3284 (ctx->stage == MESA_SHADER_GEOMETRY ||
3285 ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
3286 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3287 : RING_ESGS_VS;
3288 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3289
3290 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3291 ctx->ring_offsets,
3292 offset);
3293 }
3294
3295 if (ctx->is_gs_copy_shader) {
3296 ctx->gsvs_ring[0] =
3297 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3298 LLVMConstInt(ctx->ac.i32,
3299 RING_GSVS_VS, false));
3300 }
3301
3302 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3303 /* The conceptual layout of the GSVS ring is
3304 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3305 * but the real memory layout is swizzled across
3306 * threads:
3307 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3308 * t16v0c0 ..
3309 * Override the buffer descriptor accordingly.
3310 */
3311 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3312 uint64_t stream_offset = 0;
3313 unsigned num_records = 64;
3314 LLVMValueRef base_ring;
3315
3316 base_ring =
3317 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3318 LLVMConstInt(ctx->ac.i32,
3319 RING_GSVS_GS, false));
3320
3321 for (unsigned stream = 0; stream < 4; stream++) {
3322 unsigned num_components, stride;
3323 LLVMValueRef ring, tmp;
3324
3325 num_components =
3326 ctx->shader_info->info.gs.num_stream_output_components[stream];
3327
3328 if (!num_components)
3329 continue;
3330
3331 stride = 4 * num_components * ctx->gs_max_out_vertices;
3332
3333 /* Limit on the stride field for <= CIK. */
3334 assert(stride < (1 << 14));
3335
3336 ring = LLVMBuildBitCast(ctx->ac.builder,
3337 base_ring, v2i64, "");
3338 tmp = LLVMBuildExtractElement(ctx->ac.builder,
3339 ring, ctx->ac.i32_0, "");
3340 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
3341 LLVMConstInt(ctx->ac.i64,
3342 stream_offset, 0), "");
3343 ring = LLVMBuildInsertElement(ctx->ac.builder,
3344 ring, tmp, ctx->ac.i32_0, "");
3345
3346 stream_offset += stride * 64;
3347
3348 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
3349 ctx->ac.v4i32, "");
3350
3351 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3352 ctx->ac.i32_1, "");
3353 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3354 LLVMConstInt(ctx->ac.i32,
3355 S_008F04_STRIDE(stride), false), "");
3356 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3357 ctx->ac.i32_1, "");
3358
3359 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3360 LLVMConstInt(ctx->ac.i32,
3361 num_records, false),
3362 LLVMConstInt(ctx->ac.i32, 2, false), "");
3363
3364 ctx->gsvs_ring[stream] = ring;
3365 }
3366 }
3367
3368 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3369 ctx->stage == MESA_SHADER_TESS_EVAL) {
3370 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3371 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3372 }
3373 }
3374
3375 static unsigned
3376 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
3377 const struct nir_shader *nir)
3378 {
3379 switch (nir->info.stage) {
3380 case MESA_SHADER_TESS_CTRL:
3381 return chip_class >= CIK ? 128 : 64;
3382 case MESA_SHADER_GEOMETRY:
3383 return chip_class >= GFX9 ? 128 : 64;
3384 case MESA_SHADER_COMPUTE:
3385 break;
3386 default:
3387 return 0;
3388 }
3389
3390 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
3391 nir->info.cs.local_size[1] *
3392 nir->info.cs.local_size[2];
3393 return max_workgroup_size;
3394 }
3395
3396 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3397 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3398 {
3399 LLVMValueRef count = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
3400 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3401 ctx->ac.i32_0, "");
3402 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
3403 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
3404 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3405 }
3406
3407 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3408 {
3409 for(int i = 5; i >= 0; --i) {
3410 ctx->gs_vtx_offset[i] = ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3411 (i & 1) * 16, 16);
3412 }
3413
3414 ctx->gs_wave_id = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 16, 8);
3415 }
3416
3417
3418 static
3419 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
3420 struct nir_shader *const *shaders,
3421 int shader_count,
3422 struct radv_shader_variant_info *shader_info,
3423 const struct radv_nir_compiler_options *options)
3424 {
3425 struct radv_shader_context ctx = {0};
3426 unsigned i;
3427 ctx.options = options;
3428 ctx.shader_info = shader_info;
3429
3430 ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
3431 ctx.context = ctx.ac.context;
3432 ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
3433
3434 enum ac_float_mode float_mode =
3435 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3436 AC_FLOAT_MODE_DEFAULT;
3437
3438 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3439
3440 memset(shader_info, 0, sizeof(*shader_info));
3441
3442 for(int i = 0; i < shader_count; ++i)
3443 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3444
3445 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3446 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3447 for (i = 0; i < AC_UD_MAX_UD; i++)
3448 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3449
3450 ctx.max_workgroup_size = 0;
3451 for (int i = 0; i < shader_count; ++i) {
3452 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3453 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3454 shaders[i]));
3455 }
3456
3457 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3458 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3459
3460 ctx.abi.inputs = &ctx.inputs[0];
3461 ctx.abi.emit_outputs = handle_shader_outputs_post;
3462 ctx.abi.emit_vertex = visit_emit_vertex;
3463 ctx.abi.load_ubo = radv_load_ubo;
3464 ctx.abi.load_ssbo = radv_load_ssbo;
3465 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3466 ctx.abi.load_resource = radv_load_resource;
3467 ctx.abi.clamp_shadow_reference = false;
3468 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9 && HAVE_LLVM < 0x800;
3469
3470 if (shader_count >= 2)
3471 ac_init_exec_full_mask(&ctx.ac);
3472
3473 if (ctx.ac.chip_class == GFX9 &&
3474 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3475 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3476
3477 for(int i = 0; i < shader_count; ++i) {
3478 ctx.stage = shaders[i]->info.stage;
3479 ctx.output_mask = 0;
3480
3481 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3482 for (int i = 0; i < 4; i++) {
3483 ctx.gs_next_vertex[i] =
3484 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
3485 }
3486 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3487 ctx.abi.load_inputs = load_gs_input;
3488 ctx.abi.emit_primitive = visit_end_primitive;
3489 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3490 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3491 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3492 ctx.abi.load_tess_varyings = load_tcs_varyings;
3493 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3494 ctx.abi.store_tcs_outputs = store_tcs_output;
3495 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3496 if (shader_count == 1)
3497 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3498 else
3499 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3500 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3501 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3502 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3503 ctx.abi.load_tess_varyings = load_tes_input;
3504 ctx.abi.load_tess_coord = load_tess_coord;
3505 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3506 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3507 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3508 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3509 if (shader_info->info.vs.needs_instance_id) {
3510 if (ctx.options->key.vs.as_ls) {
3511 ctx.shader_info->vs.vgpr_comp_cnt =
3512 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3513 } else {
3514 ctx.shader_info->vs.vgpr_comp_cnt =
3515 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3516 }
3517 }
3518 ctx.abi.load_base_vertex = radv_load_base_vertex;
3519 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3520 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3521 ctx.abi.lookup_interp_param = lookup_interp_param;
3522 ctx.abi.load_sample_position = load_sample_position;
3523 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3524 ctx.abi.emit_kill = radv_emit_kill;
3525 }
3526
3527 if (i)
3528 ac_emit_barrier(&ctx.ac, ctx.stage);
3529
3530 nir_foreach_variable(variable, &shaders[i]->outputs)
3531 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3532
3533 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3534 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3535 shaders[i]->info.cull_distance_array_size > 4;
3536 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3537 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3538 shaders[i]->info.gs.vertices_out;
3539 }
3540
3541 ac_setup_rings(&ctx);
3542
3543 LLVMBasicBlockRef merge_block;
3544 if (shader_count >= 2) {
3545 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3546 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3547 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3548
3549 LLVMValueRef count = ac_unpack_param(&ctx.ac, ctx.merged_wave_info, 8 * i, 8);
3550 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3551 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3552 thread_id, count, "");
3553 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3554
3555 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3556 }
3557
3558 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3559 handle_fs_inputs(&ctx, shaders[i]);
3560 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3561 handle_vs_inputs(&ctx, shaders[i]);
3562 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3563 prepare_gs_input_vgprs(&ctx);
3564
3565 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3566
3567 if (shader_count >= 2) {
3568 LLVMBuildBr(ctx.ac.builder, merge_block);
3569 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3570 }
3571
3572 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3573 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3574 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3575 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3576 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3577 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3578 }
3579 }
3580
3581 LLVMBuildRetVoid(ctx.ac.builder);
3582
3583 if (options->dump_preoptir)
3584 ac_dump_module(ctx.ac.module);
3585
3586 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
3587
3588 if (shader_count == 1)
3589 ac_nir_eliminate_const_vs_outputs(&ctx);
3590
3591 if (options->dump_shader) {
3592 ctx.shader_info->private_mem_vgprs =
3593 ac_count_scratch_private_memory(ctx.main_function);
3594 }
3595
3596 return ctx.ac.module;
3597 }
3598
3599 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3600 {
3601 unsigned *retval = (unsigned *)context;
3602 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3603 char *description = LLVMGetDiagInfoDescription(di);
3604
3605 if (severity == LLVMDSError) {
3606 *retval = 1;
3607 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3608 description);
3609 }
3610
3611 LLVMDisposeMessage(description);
3612 }
3613
3614 static unsigned ac_llvm_compile(LLVMModuleRef M,
3615 struct ac_shader_binary *binary,
3616 struct ac_llvm_compiler *ac_llvm)
3617 {
3618 unsigned retval = 0;
3619 LLVMContextRef llvm_ctx;
3620
3621 /* Setup Diagnostic Handler*/
3622 llvm_ctx = LLVMGetModuleContext(M);
3623
3624 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3625 &retval);
3626
3627 /* Compile IR*/
3628 if (!radv_compile_to_binary(ac_llvm, M, binary))
3629 retval = 1;
3630 return retval;
3631 }
3632
3633 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
3634 LLVMModuleRef llvm_module,
3635 struct ac_shader_binary *binary,
3636 struct ac_shader_config *config,
3637 struct radv_shader_variant_info *shader_info,
3638 gl_shader_stage stage,
3639 const struct radv_nir_compiler_options *options)
3640 {
3641 if (options->dump_shader)
3642 ac_dump_module(llvm_module);
3643
3644 memset(binary, 0, sizeof(*binary));
3645
3646 if (options->record_llvm_ir) {
3647 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3648 binary->llvm_ir_string = strdup(llvm_ir);
3649 LLVMDisposeMessage(llvm_ir);
3650 }
3651
3652 int v = ac_llvm_compile(llvm_module, binary, ac_llvm);
3653 if (v) {
3654 fprintf(stderr, "compile failed\n");
3655 }
3656
3657 if (options->dump_shader)
3658 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3659
3660 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3661
3662 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3663 LLVMDisposeModule(llvm_module);
3664 LLVMContextDispose(ctx);
3665
3666 if (stage == MESA_SHADER_FRAGMENT) {
3667 shader_info->num_input_vgprs = 0;
3668 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3669 shader_info->num_input_vgprs += 2;
3670 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3671 shader_info->num_input_vgprs += 2;
3672 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3673 shader_info->num_input_vgprs += 2;
3674 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3675 shader_info->num_input_vgprs += 3;
3676 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3677 shader_info->num_input_vgprs += 2;
3678 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3679 shader_info->num_input_vgprs += 2;
3680 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3681 shader_info->num_input_vgprs += 2;
3682 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3683 shader_info->num_input_vgprs += 1;
3684 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3685 shader_info->num_input_vgprs += 1;
3686 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3687 shader_info->num_input_vgprs += 1;
3688 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3689 shader_info->num_input_vgprs += 1;
3690 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3691 shader_info->num_input_vgprs += 1;
3692 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3693 shader_info->num_input_vgprs += 1;
3694 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3695 shader_info->num_input_vgprs += 1;
3696 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3697 shader_info->num_input_vgprs += 1;
3698 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3699 shader_info->num_input_vgprs += 1;
3700 }
3701 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3702
3703 /* +3 for scratch wave offset and VCC */
3704 config->num_sgprs = MAX2(config->num_sgprs,
3705 shader_info->num_input_sgprs + 3);
3706
3707 /* Enable 64-bit and 16-bit denormals, because there is no performance
3708 * cost.
3709 *
3710 * If denormals are enabled, all floating-point output modifiers are
3711 * ignored.
3712 *
3713 * Don't enable denormals for 32-bit floats, because:
3714 * - Floating-point output modifiers would be ignored by the hw.
3715 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3716 * have to stop using those.
3717 * - SI & CI would be very slow.
3718 */
3719 config->float_mode |= V_00B028_FP_64_DENORMS;
3720 }
3721
3722 static void
3723 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3724 {
3725 switch (nir->info.stage) {
3726 case MESA_SHADER_COMPUTE:
3727 for (int i = 0; i < 3; ++i)
3728 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3729 break;
3730 case MESA_SHADER_FRAGMENT:
3731 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3732 break;
3733 case MESA_SHADER_GEOMETRY:
3734 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3735 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3736 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3737 shader_info->gs.invocations = nir->info.gs.invocations;
3738 break;
3739 case MESA_SHADER_TESS_EVAL:
3740 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3741 shader_info->tes.spacing = nir->info.tess.spacing;
3742 shader_info->tes.ccw = nir->info.tess.ccw;
3743 shader_info->tes.point_mode = nir->info.tess.point_mode;
3744 shader_info->tes.as_es = options->key.tes.as_es;
3745 break;
3746 case MESA_SHADER_TESS_CTRL:
3747 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3748 break;
3749 case MESA_SHADER_VERTEX:
3750 shader_info->vs.as_es = options->key.vs.as_es;
3751 shader_info->vs.as_ls = options->key.vs.as_ls;
3752 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3753 if (options->key.vs.as_ls)
3754 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3755 break;
3756 default:
3757 break;
3758 }
3759 }
3760
3761 void
3762 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
3763 struct ac_shader_binary *binary,
3764 struct ac_shader_config *config,
3765 struct radv_shader_variant_info *shader_info,
3766 struct nir_shader *const *nir,
3767 int nir_count,
3768 const struct radv_nir_compiler_options *options)
3769 {
3770
3771 LLVMModuleRef llvm_module;
3772
3773 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, shader_info,
3774 options);
3775
3776 ac_compile_llvm_module(ac_llvm, llvm_module, binary, config, shader_info,
3777 nir[0]->info.stage, options);
3778
3779 for (int i = 0; i < nir_count; ++i)
3780 ac_fill_shader_info(shader_info, nir[i], options);
3781
3782 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3783 if (options->chip_class == GFX9) {
3784 if (nir_count == 2 &&
3785 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3786 shader_info->gs.es_type = nir[0]->info.stage;
3787 }
3788 }
3789 }
3790
3791 static void
3792 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3793 {
3794 LLVMValueRef vtx_offset =
3795 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3796 LLVMConstInt(ctx->ac.i32, 4, false), "");
3797 LLVMValueRef stream_id;
3798
3799 /* Fetch the vertex stream ID. */
3800 if (ctx->shader_info->info.so.num_outputs) {
3801 stream_id =
3802 ac_unpack_param(&ctx->ac, ctx->streamout_config, 24, 2);
3803 } else {
3804 stream_id = ctx->ac.i32_0;
3805 }
3806
3807 LLVMBasicBlockRef end_bb;
3808 LLVMValueRef switch_inst;
3809
3810 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
3811 ctx->main_function, "end");
3812 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
3813
3814 for (unsigned stream = 0; stream < 4; stream++) {
3815 unsigned num_components =
3816 ctx->shader_info->info.gs.num_stream_output_components[stream];
3817 LLVMBasicBlockRef bb;
3818 unsigned offset;
3819
3820 if (!num_components)
3821 continue;
3822
3823 if (stream > 0 && !ctx->shader_info->info.so.num_outputs)
3824 continue;
3825
3826 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
3827 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
3828 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
3829
3830 offset = 0;
3831 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3832 unsigned output_usage_mask =
3833 ctx->shader_info->info.gs.output_usage_mask[i];
3834 unsigned output_stream =
3835 ctx->shader_info->info.gs.output_streams[i];
3836 int length = util_last_bit(output_usage_mask);
3837
3838 if (!(ctx->output_mask & (1ull << i)) ||
3839 output_stream != stream)
3840 continue;
3841
3842 for (unsigned j = 0; j < length; j++) {
3843 LLVMValueRef value, soffset;
3844
3845 if (!(output_usage_mask & (1 << j)))
3846 continue;
3847
3848 soffset = LLVMConstInt(ctx->ac.i32,
3849 offset *
3850 ctx->gs_max_out_vertices * 16 * 4, false);
3851
3852 offset++;
3853
3854 value = ac_build_buffer_load(&ctx->ac,
3855 ctx->gsvs_ring[0],
3856 1, ctx->ac.i32_0,
3857 vtx_offset, soffset,
3858 0, 1, 1, true, false);
3859
3860 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3861 if (ac_get_type_size(type) == 2) {
3862 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
3863 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
3864 }
3865
3866 LLVMBuildStore(ctx->ac.builder,
3867 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3868 }
3869 }
3870
3871 if (ctx->shader_info->info.so.num_outputs)
3872 radv_emit_streamout(ctx, stream);
3873
3874 if (stream == 0) {
3875 handle_vs_outputs_post(ctx, false, false,
3876 &ctx->shader_info->vs.outinfo);
3877 }
3878
3879 LLVMBuildBr(ctx->ac.builder, end_bb);
3880 }
3881
3882 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
3883 }
3884
3885 void
3886 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
3887 struct nir_shader *geom_shader,
3888 struct ac_shader_binary *binary,
3889 struct ac_shader_config *config,
3890 struct radv_shader_variant_info *shader_info,
3891 const struct radv_nir_compiler_options *options)
3892 {
3893 struct radv_shader_context ctx = {0};
3894 ctx.options = options;
3895 ctx.shader_info = shader_info;
3896
3897 ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
3898 ctx.context = ctx.ac.context;
3899 ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
3900
3901 ctx.is_gs_copy_shader = true;
3902
3903 enum ac_float_mode float_mode =
3904 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3905 AC_FLOAT_MODE_DEFAULT;
3906
3907 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3908 ctx.stage = MESA_SHADER_VERTEX;
3909
3910 radv_nir_shader_info_pass(geom_shader, options, &shader_info->info);
3911
3912 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3913
3914 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3915 ac_setup_rings(&ctx);
3916
3917 nir_foreach_variable(variable, &geom_shader->outputs) {
3918 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3919 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3920 variable, MESA_SHADER_VERTEX);
3921 }
3922
3923 ac_gs_copy_shader_emit(&ctx);
3924
3925 LLVMBuildRetVoid(ctx.ac.builder);
3926
3927 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
3928
3929 ac_compile_llvm_module(ac_llvm, ctx.ac.module, binary, config, shader_info,
3930 MESA_SHADER_VERTEX, options);
3931 }