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radv: drop tess offchip layout for tcs.
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "nir/nir.h"
31
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35
36 #include "sid.h"
37 #include "gfx9d.h"
38 #include "ac_binary.h"
39 #include "ac_llvm_util.h"
40 #include "ac_llvm_build.h"
41 #include "ac_shader_abi.h"
42 #include "ac_shader_util.h"
43 #include "ac_exp_param.h"
44
45 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
46
47 struct radv_shader_context {
48 struct ac_llvm_context ac;
49 const struct radv_nir_compiler_options *options;
50 struct radv_shader_variant_info *shader_info;
51 struct ac_shader_abi abi;
52
53 unsigned max_workgroup_size;
54 LLVMContextRef context;
55 LLVMValueRef main_function;
56
57 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
58 LLVMValueRef ring_offsets;
59
60 LLVMValueRef vertex_buffers;
61 LLVMValueRef rel_auto_id;
62 LLVMValueRef vs_prim_id;
63 LLVMValueRef es2gs_offset;
64
65 LLVMValueRef tcs_offchip_layout;
66 LLVMValueRef oc_lds;
67 LLVMValueRef merged_wave_info;
68 LLVMValueRef tess_factor_offset;
69 LLVMValueRef tes_rel_patch_id;
70 LLVMValueRef tes_u;
71 LLVMValueRef tes_v;
72
73 LLVMValueRef gsvs_ring_stride;
74 LLVMValueRef gsvs_num_entries;
75 LLVMValueRef gs2vs_offset;
76 LLVMValueRef gs_wave_id;
77 LLVMValueRef gs_vtx_offset[6];
78
79 LLVMValueRef esgs_ring;
80 LLVMValueRef gsvs_ring;
81 LLVMValueRef hs_ring_tess_offchip;
82 LLVMValueRef hs_ring_tess_factor;
83
84 LLVMValueRef sample_pos_offset;
85 LLVMValueRef persp_sample, persp_center, persp_centroid;
86 LLVMValueRef linear_sample, linear_center, linear_centroid;
87
88 gl_shader_stage stage;
89
90 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
91
92 uint64_t input_mask;
93 uint64_t output_mask;
94 uint8_t num_output_clips;
95 uint8_t num_output_culls;
96
97 bool is_gs_copy_shader;
98 LLVMValueRef gs_next_vertex;
99 unsigned gs_max_out_vertices;
100
101 unsigned tes_primitive_mode;
102 uint64_t tess_outputs_written;
103 uint64_t tess_patch_outputs_written;
104
105 uint32_t tcs_patch_outputs_read;
106 uint64_t tcs_outputs_read;
107 uint32_t tcs_vertices_per_patch;
108 uint32_t tcs_num_inputs;
109 uint32_t tcs_num_patches;
110 };
111
112 enum radeon_llvm_calling_convention {
113 RADEON_LLVM_AMDGPU_VS = 87,
114 RADEON_LLVM_AMDGPU_GS = 88,
115 RADEON_LLVM_AMDGPU_PS = 89,
116 RADEON_LLVM_AMDGPU_CS = 90,
117 RADEON_LLVM_AMDGPU_HS = 93,
118 };
119
120 static inline struct radv_shader_context *
121 radv_shader_context_from_abi(struct ac_shader_abi *abi)
122 {
123 struct radv_shader_context *ctx = NULL;
124 return container_of(abi, ctx, abi);
125 }
126
127 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
128 {
129 switch (ctx->stage) {
130 case MESA_SHADER_TESS_CTRL:
131 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
132 case MESA_SHADER_TESS_EVAL:
133 return ctx->tes_rel_patch_id;
134 break;
135 default:
136 unreachable("Illegal stage");
137 }
138 }
139
140 static unsigned
141 get_tcs_num_patches(struct radv_shader_context *ctx)
142 {
143 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
144 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
145 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
146 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
147 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
148 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
149 uint32_t output_vertex_size = num_tcs_outputs * 16;
150 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
151 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
152 unsigned num_patches;
153 unsigned hardware_lds_size;
154
155 /* Ensure that we only need one wave per SIMD so we don't need to check
156 * resource usage. Also ensures that the number of tcs in and out
157 * vertices per threadgroup are at most 256.
158 */
159 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
160 /* Make sure that the data fits in LDS. This assumes the shaders only
161 * use LDS for the inputs and outputs.
162 */
163 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
164 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
165 /* Make sure the output data fits in the offchip buffer */
166 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
167 /* Not necessary for correctness, but improves performance. The
168 * specific value is taken from the proprietary driver.
169 */
170 num_patches = MIN2(num_patches, 40);
171
172 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
173 if (ctx->options->chip_class == SI) {
174 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
175 num_patches = MIN2(num_patches, one_wave);
176 }
177 return num_patches;
178 }
179
180 /* Tessellation shaders pass outputs to the next shader using LDS.
181 *
182 * LS outputs = TCS inputs
183 * TCS outputs = TES inputs
184 *
185 * The LDS layout is:
186 * - TCS inputs for patch 0
187 * - TCS inputs for patch 1
188 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
189 * - ...
190 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
191 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
192 * - TCS outputs for patch 1
193 * - Per-patch TCS outputs for patch 1
194 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
195 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
196 * - ...
197 *
198 * All three shaders VS(LS), TCS, TES share the same LDS space.
199 */
200 static LLVMValueRef
201 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
202 {
203 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
204 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
205 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
206
207 input_patch_size /= 4;
208 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
209 }
210
211 static LLVMValueRef
212 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
213 {
214 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
215 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
216 uint32_t output_vertex_size = num_tcs_outputs * 16;
217 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
218 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
219 output_patch_size /= 4;
220 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
221 }
222
223 static LLVMValueRef
224 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
225 {
226 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
227 uint32_t output_vertex_size = num_tcs_outputs * 16;
228 output_vertex_size /= 4;
229 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
230 }
231
232 static LLVMValueRef
233 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
234 {
235 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
236 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
237 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
238 uint32_t output_patch0_offset = input_patch_size;
239 unsigned num_patches = ctx->tcs_num_patches;
240
241 output_patch0_offset *= num_patches;
242 output_patch0_offset /= 4;
243 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
244 }
245
246 static LLVMValueRef
247 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
248 {
249 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
250 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
251 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
252 uint32_t output_patch0_offset = input_patch_size;
253
254 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
255 uint32_t output_vertex_size = num_tcs_outputs * 16;
256 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
257 unsigned num_patches = ctx->tcs_num_patches;
258
259 output_patch0_offset *= num_patches;
260 output_patch0_offset += pervertex_output_patch_size;
261 output_patch0_offset /= 4;
262 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
263 }
264
265 static LLVMValueRef
266 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
267 {
268 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
269 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
270
271 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
272 }
273
274 static LLVMValueRef
275 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
276 {
277 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
278 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
279 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
280
281 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
282 LLVMBuildMul(ctx->ac.builder, patch_stride,
283 rel_patch_id, ""),
284 "");
285 }
286
287 static LLVMValueRef
288 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
289 {
290 LLVMValueRef patch0_patch_data_offset =
291 get_tcs_out_patch0_patch_data_offset(ctx);
292 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
293 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
294
295 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
296 LLVMBuildMul(ctx->ac.builder, patch_stride,
297 rel_patch_id, ""),
298 "");
299 }
300
301 #define MAX_ARGS 23
302 struct arg_info {
303 LLVMTypeRef types[MAX_ARGS];
304 LLVMValueRef *assign[MAX_ARGS];
305 unsigned array_params_mask;
306 uint8_t count;
307 uint8_t sgpr_count;
308 uint8_t num_sgprs_used;
309 uint8_t num_vgprs_used;
310 };
311
312 enum ac_arg_regfile {
313 ARG_SGPR,
314 ARG_VGPR,
315 };
316
317 static void
318 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
319 LLVMValueRef *param_ptr)
320 {
321 assert(info->count < MAX_ARGS);
322
323 info->assign[info->count] = param_ptr;
324 info->types[info->count] = type;
325 info->count++;
326
327 if (regfile == ARG_SGPR) {
328 info->num_sgprs_used += ac_get_type_size(type) / 4;
329 info->sgpr_count++;
330 } else {
331 assert(regfile == ARG_VGPR);
332 info->num_vgprs_used += ac_get_type_size(type) / 4;
333 }
334 }
335
336 static inline void
337 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
338 {
339 info->array_params_mask |= (1 << info->count);
340 add_arg(info, ARG_SGPR, type, param_ptr);
341 }
342
343 static void assign_arguments(LLVMValueRef main_function,
344 struct arg_info *info)
345 {
346 unsigned i;
347 for (i = 0; i < info->count; i++) {
348 if (info->assign[i])
349 *info->assign[i] = LLVMGetParam(main_function, i);
350 }
351 }
352
353 static LLVMValueRef
354 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
355 LLVMBuilderRef builder, LLVMTypeRef *return_types,
356 unsigned num_return_elems,
357 struct arg_info *args,
358 unsigned max_workgroup_size,
359 bool unsafe_math)
360 {
361 LLVMTypeRef main_function_type, ret_type;
362 LLVMBasicBlockRef main_function_body;
363
364 if (num_return_elems)
365 ret_type = LLVMStructTypeInContext(ctx, return_types,
366 num_return_elems, true);
367 else
368 ret_type = LLVMVoidTypeInContext(ctx);
369
370 /* Setup the function */
371 main_function_type =
372 LLVMFunctionType(ret_type, args->types, args->count, 0);
373 LLVMValueRef main_function =
374 LLVMAddFunction(module, "main", main_function_type);
375 main_function_body =
376 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
377 LLVMPositionBuilderAtEnd(builder, main_function_body);
378
379 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
380 for (unsigned i = 0; i < args->sgpr_count; ++i) {
381 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
382
383 if (args->array_params_mask & (1 << i)) {
384 LLVMValueRef P = LLVMGetParam(main_function, i);
385 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
386 ac_add_attr_dereferenceable(P, UINT64_MAX);
387 }
388 }
389
390 if (max_workgroup_size) {
391 ac_llvm_add_target_dep_function_attr(main_function,
392 "amdgpu-max-work-group-size",
393 max_workgroup_size);
394 }
395 if (unsafe_math) {
396 /* These were copied from some LLVM test. */
397 LLVMAddTargetDependentFunctionAttr(main_function,
398 "less-precise-fpmad",
399 "true");
400 LLVMAddTargetDependentFunctionAttr(main_function,
401 "no-infs-fp-math",
402 "true");
403 LLVMAddTargetDependentFunctionAttr(main_function,
404 "no-nans-fp-math",
405 "true");
406 LLVMAddTargetDependentFunctionAttr(main_function,
407 "unsafe-fp-math",
408 "true");
409 LLVMAddTargetDependentFunctionAttr(main_function,
410 "no-signed-zeros-fp-math",
411 "true");
412 }
413 return main_function;
414 }
415
416
417 static void
418 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
419 uint32_t indirect_offset)
420 {
421 ud_info->sgpr_idx = *sgpr_idx;
422 ud_info->num_sgprs = num_sgprs;
423 ud_info->indirect = indirect_offset > 0;
424 ud_info->indirect_offset = indirect_offset;
425 *sgpr_idx += num_sgprs;
426 }
427
428 static void
429 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
430 uint8_t num_sgprs)
431 {
432 struct radv_userdata_info *ud_info =
433 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
434 assert(ud_info);
435
436 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
437 }
438
439 static void
440 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
441 uint32_t indirect_offset)
442 {
443 struct radv_userdata_info *ud_info =
444 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
445 assert(ud_info);
446
447 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
448 }
449
450 struct user_sgpr_info {
451 bool need_ring_offsets;
452 uint8_t sgpr_count;
453 bool indirect_all_descriptor_sets;
454 };
455
456 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
457 gl_shader_stage stage)
458 {
459 switch (stage) {
460 case MESA_SHADER_VERTEX:
461 if (ctx->shader_info->info.needs_multiview_view_index ||
462 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
463 return true;
464 break;
465 case MESA_SHADER_TESS_EVAL:
466 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
467 return true;
468 break;
469 case MESA_SHADER_GEOMETRY:
470 case MESA_SHADER_TESS_CTRL:
471 if (ctx->shader_info->info.needs_multiview_view_index)
472 return true;
473 break;
474 default:
475 break;
476 }
477 return false;
478 }
479
480 static uint8_t
481 count_vs_user_sgprs(struct radv_shader_context *ctx)
482 {
483 uint8_t count = 0;
484
485 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
486 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
487
488 return count;
489 }
490
491 static void allocate_user_sgprs(struct radv_shader_context *ctx,
492 gl_shader_stage stage,
493 bool has_previous_stage,
494 gl_shader_stage previous_stage,
495 bool needs_view_index,
496 struct user_sgpr_info *user_sgpr_info)
497 {
498 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
499
500 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
501 if (stage == MESA_SHADER_GEOMETRY ||
502 stage == MESA_SHADER_VERTEX ||
503 stage == MESA_SHADER_TESS_CTRL ||
504 stage == MESA_SHADER_TESS_EVAL ||
505 ctx->is_gs_copy_shader)
506 user_sgpr_info->need_ring_offsets = true;
507
508 if (stage == MESA_SHADER_FRAGMENT &&
509 ctx->shader_info->info.ps.needs_sample_positions)
510 user_sgpr_info->need_ring_offsets = true;
511
512 /* 2 user sgprs will nearly always be allocated for scratch/rings */
513 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
514 user_sgpr_info->sgpr_count += 2;
515 }
516
517 switch (stage) {
518 case MESA_SHADER_COMPUTE:
519 if (ctx->shader_info->info.cs.uses_grid_size)
520 user_sgpr_info->sgpr_count += 3;
521 break;
522 case MESA_SHADER_FRAGMENT:
523 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
524 break;
525 case MESA_SHADER_VERTEX:
526 if (!ctx->is_gs_copy_shader)
527 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
528 break;
529 case MESA_SHADER_TESS_CTRL:
530 if (has_previous_stage) {
531 if (previous_stage == MESA_SHADER_VERTEX)
532 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
533 }
534 break;
535 case MESA_SHADER_TESS_EVAL:
536 user_sgpr_info->sgpr_count += 1;
537 break;
538 case MESA_SHADER_GEOMETRY:
539 if (has_previous_stage) {
540 if (previous_stage == MESA_SHADER_VERTEX) {
541 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
542 } else {
543 user_sgpr_info->sgpr_count++;
544 }
545 }
546 user_sgpr_info->sgpr_count += 2;
547 break;
548 default:
549 break;
550 }
551
552 if (needs_view_index)
553 user_sgpr_info->sgpr_count++;
554
555 if (ctx->shader_info->info.loads_push_constants)
556 user_sgpr_info->sgpr_count += 2;
557
558 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
559 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
560
561 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
562 user_sgpr_info->sgpr_count += 2;
563 user_sgpr_info->indirect_all_descriptor_sets = true;
564 } else {
565 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
566 }
567 }
568
569 static void
570 declare_global_input_sgprs(struct radv_shader_context *ctx,
571 gl_shader_stage stage,
572 bool has_previous_stage,
573 gl_shader_stage previous_stage,
574 const struct user_sgpr_info *user_sgpr_info,
575 struct arg_info *args,
576 LLVMValueRef *desc_sets)
577 {
578 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
579 unsigned num_sets = ctx->options->layout ?
580 ctx->options->layout->num_sets : 0;
581 unsigned stage_mask = 1 << stage;
582
583 if (has_previous_stage)
584 stage_mask |= 1 << previous_stage;
585
586 /* 1 for each descriptor set */
587 if (!user_sgpr_info->indirect_all_descriptor_sets) {
588 for (unsigned i = 0; i < num_sets; ++i) {
589 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
590 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
591 add_array_arg(args, type,
592 &ctx->descriptor_sets[i]);
593 }
594 }
595 } else {
596 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
597 }
598
599 if (ctx->shader_info->info.loads_push_constants) {
600 /* 1 for push constants and dynamic descriptors */
601 add_array_arg(args, type, &ctx->abi.push_constants);
602 }
603 }
604
605 static void
606 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
607 gl_shader_stage stage,
608 bool has_previous_stage,
609 gl_shader_stage previous_stage,
610 struct arg_info *args)
611 {
612 if (!ctx->is_gs_copy_shader &&
613 (stage == MESA_SHADER_VERTEX ||
614 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
615 if (ctx->shader_info->info.vs.has_vertex_buffers) {
616 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
617 &ctx->vertex_buffers);
618 }
619 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
620 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
621 if (ctx->shader_info->info.vs.needs_draw_id) {
622 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
623 }
624 }
625 }
626
627 static void
628 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
629 {
630 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
631 if (!ctx->is_gs_copy_shader) {
632 if (ctx->options->key.vs.as_ls) {
633 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
634 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
635 } else {
636 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
637 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
638 }
639 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
640 }
641 }
642
643 static void
644 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
645 {
646 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
647 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
648 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
649 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
650 }
651
652 static void
653 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
654 bool has_previous_stage, gl_shader_stage previous_stage,
655 const struct user_sgpr_info *user_sgpr_info,
656 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
657 {
658 unsigned num_sets = ctx->options->layout ?
659 ctx->options->layout->num_sets : 0;
660 unsigned stage_mask = 1 << stage;
661
662 if (has_previous_stage)
663 stage_mask |= 1 << previous_stage;
664
665 if (!user_sgpr_info->indirect_all_descriptor_sets) {
666 for (unsigned i = 0; i < num_sets; ++i) {
667 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
668 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
669 set_loc_desc(ctx, i, user_sgpr_idx, 0);
670 } else
671 ctx->descriptor_sets[i] = NULL;
672 }
673 } else {
674 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
675 user_sgpr_idx, 2);
676
677 for (unsigned i = 0; i < num_sets; ++i) {
678 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
679 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
680 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
681 ctx->descriptor_sets[i] =
682 ac_build_load_to_sgpr(&ctx->ac,
683 desc_sets,
684 LLVMConstInt(ctx->ac.i32, i, false));
685
686 } else
687 ctx->descriptor_sets[i] = NULL;
688 }
689 ctx->shader_info->need_indirect_descriptor_sets = true;
690 }
691
692 if (ctx->shader_info->info.loads_push_constants) {
693 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
694 }
695 }
696
697 static void
698 set_vs_specific_input_locs(struct radv_shader_context *ctx,
699 gl_shader_stage stage, bool has_previous_stage,
700 gl_shader_stage previous_stage,
701 uint8_t *user_sgpr_idx)
702 {
703 if (!ctx->is_gs_copy_shader &&
704 (stage == MESA_SHADER_VERTEX ||
705 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
706 if (ctx->shader_info->info.vs.has_vertex_buffers) {
707 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
708 user_sgpr_idx, 2);
709 }
710
711 unsigned vs_num = 2;
712 if (ctx->shader_info->info.vs.needs_draw_id)
713 vs_num++;
714
715 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
716 user_sgpr_idx, vs_num);
717 }
718 }
719
720 static void set_llvm_calling_convention(LLVMValueRef func,
721 gl_shader_stage stage)
722 {
723 enum radeon_llvm_calling_convention calling_conv;
724
725 switch (stage) {
726 case MESA_SHADER_VERTEX:
727 case MESA_SHADER_TESS_EVAL:
728 calling_conv = RADEON_LLVM_AMDGPU_VS;
729 break;
730 case MESA_SHADER_GEOMETRY:
731 calling_conv = RADEON_LLVM_AMDGPU_GS;
732 break;
733 case MESA_SHADER_TESS_CTRL:
734 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
735 break;
736 case MESA_SHADER_FRAGMENT:
737 calling_conv = RADEON_LLVM_AMDGPU_PS;
738 break;
739 case MESA_SHADER_COMPUTE:
740 calling_conv = RADEON_LLVM_AMDGPU_CS;
741 break;
742 default:
743 unreachable("Unhandle shader type");
744 }
745
746 LLVMSetFunctionCallConv(func, calling_conv);
747 }
748
749 static void create_function(struct radv_shader_context *ctx,
750 gl_shader_stage stage,
751 bool has_previous_stage,
752 gl_shader_stage previous_stage)
753 {
754 uint8_t user_sgpr_idx;
755 struct user_sgpr_info user_sgpr_info;
756 struct arg_info args = {};
757 LLVMValueRef desc_sets;
758 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
759 allocate_user_sgprs(ctx, stage, has_previous_stage,
760 previous_stage, needs_view_index, &user_sgpr_info);
761
762 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
763 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
764 &ctx->ring_offsets);
765 }
766
767 switch (stage) {
768 case MESA_SHADER_COMPUTE:
769 declare_global_input_sgprs(ctx, stage, has_previous_stage,
770 previous_stage, &user_sgpr_info,
771 &args, &desc_sets);
772
773 if (ctx->shader_info->info.cs.uses_grid_size) {
774 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
775 &ctx->abi.num_work_groups);
776 }
777
778 for (int i = 0; i < 3; i++) {
779 ctx->abi.workgroup_ids[i] = NULL;
780 if (ctx->shader_info->info.cs.uses_block_id[i]) {
781 add_arg(&args, ARG_SGPR, ctx->ac.i32,
782 &ctx->abi.workgroup_ids[i]);
783 }
784 }
785
786 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
787 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
788 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
789 &ctx->abi.local_invocation_ids);
790 break;
791 case MESA_SHADER_VERTEX:
792 declare_global_input_sgprs(ctx, stage, has_previous_stage,
793 previous_stage, &user_sgpr_info,
794 &args, &desc_sets);
795 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
796 previous_stage, &args);
797
798 if (needs_view_index)
799 add_arg(&args, ARG_SGPR, ctx->ac.i32,
800 &ctx->abi.view_index);
801 if (ctx->options->key.vs.as_es)
802 add_arg(&args, ARG_SGPR, ctx->ac.i32,
803 &ctx->es2gs_offset);
804
805 declare_vs_input_vgprs(ctx, &args);
806 break;
807 case MESA_SHADER_TESS_CTRL:
808 if (has_previous_stage) {
809 // First 6 system regs
810 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
811 add_arg(&args, ARG_SGPR, ctx->ac.i32,
812 &ctx->merged_wave_info);
813 add_arg(&args, ARG_SGPR, ctx->ac.i32,
814 &ctx->tess_factor_offset);
815
816 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
817 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
818 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
819
820 declare_global_input_sgprs(ctx, stage,
821 has_previous_stage,
822 previous_stage,
823 &user_sgpr_info, &args,
824 &desc_sets);
825 declare_vs_specific_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage, &args);
828
829 if (needs_view_index)
830 add_arg(&args, ARG_SGPR, ctx->ac.i32,
831 &ctx->abi.view_index);
832
833 add_arg(&args, ARG_VGPR, ctx->ac.i32,
834 &ctx->abi.tcs_patch_id);
835 add_arg(&args, ARG_VGPR, ctx->ac.i32,
836 &ctx->abi.tcs_rel_ids);
837
838 declare_vs_input_vgprs(ctx, &args);
839 } else {
840 declare_global_input_sgprs(ctx, stage,
841 has_previous_stage,
842 previous_stage,
843 &user_sgpr_info, &args,
844 &desc_sets);
845
846 if (needs_view_index)
847 add_arg(&args, ARG_SGPR, ctx->ac.i32,
848 &ctx->abi.view_index);
849
850 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
851 add_arg(&args, ARG_SGPR, ctx->ac.i32,
852 &ctx->tess_factor_offset);
853 add_arg(&args, ARG_VGPR, ctx->ac.i32,
854 &ctx->abi.tcs_patch_id);
855 add_arg(&args, ARG_VGPR, ctx->ac.i32,
856 &ctx->abi.tcs_rel_ids);
857 }
858 break;
859 case MESA_SHADER_TESS_EVAL:
860 declare_global_input_sgprs(ctx, stage, has_previous_stage,
861 previous_stage, &user_sgpr_info,
862 &args, &desc_sets);
863
864 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
865 if (needs_view_index)
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->abi.view_index);
868
869 if (ctx->options->key.tes.as_es) {
870 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
871 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
872 add_arg(&args, ARG_SGPR, ctx->ac.i32,
873 &ctx->es2gs_offset);
874 } else {
875 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
876 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
877 }
878 declare_tes_input_vgprs(ctx, &args);
879 break;
880 case MESA_SHADER_GEOMETRY:
881 if (has_previous_stage) {
882 // First 6 system regs
883 add_arg(&args, ARG_SGPR, ctx->ac.i32,
884 &ctx->gs2vs_offset);
885 add_arg(&args, ARG_SGPR, ctx->ac.i32,
886 &ctx->merged_wave_info);
887 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
888
889 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
890 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
891 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
892
893 declare_global_input_sgprs(ctx, stage,
894 has_previous_stage,
895 previous_stage,
896 &user_sgpr_info, &args,
897 &desc_sets);
898
899 if (previous_stage == MESA_SHADER_TESS_EVAL) {
900 add_arg(&args, ARG_SGPR, ctx->ac.i32,
901 &ctx->tcs_offchip_layout);
902 } else {
903 declare_vs_specific_input_sgprs(ctx, stage,
904 has_previous_stage,
905 previous_stage,
906 &args);
907 }
908
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->gsvs_ring_stride);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32,
912 &ctx->gsvs_num_entries);
913 if (needs_view_index)
914 add_arg(&args, ARG_SGPR, ctx->ac.i32,
915 &ctx->abi.view_index);
916
917 add_arg(&args, ARG_VGPR, ctx->ac.i32,
918 &ctx->gs_vtx_offset[0]);
919 add_arg(&args, ARG_VGPR, ctx->ac.i32,
920 &ctx->gs_vtx_offset[2]);
921 add_arg(&args, ARG_VGPR, ctx->ac.i32,
922 &ctx->abi.gs_prim_id);
923 add_arg(&args, ARG_VGPR, ctx->ac.i32,
924 &ctx->abi.gs_invocation_id);
925 add_arg(&args, ARG_VGPR, ctx->ac.i32,
926 &ctx->gs_vtx_offset[4]);
927
928 if (previous_stage == MESA_SHADER_VERTEX) {
929 declare_vs_input_vgprs(ctx, &args);
930 } else {
931 declare_tes_input_vgprs(ctx, &args);
932 }
933 } else {
934 declare_global_input_sgprs(ctx, stage,
935 has_previous_stage,
936 previous_stage,
937 &user_sgpr_info, &args,
938 &desc_sets);
939
940 add_arg(&args, ARG_SGPR, ctx->ac.i32,
941 &ctx->gsvs_ring_stride);
942 add_arg(&args, ARG_SGPR, ctx->ac.i32,
943 &ctx->gsvs_num_entries);
944 if (needs_view_index)
945 add_arg(&args, ARG_SGPR, ctx->ac.i32,
946 &ctx->abi.view_index);
947
948 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
949 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
950 add_arg(&args, ARG_VGPR, ctx->ac.i32,
951 &ctx->gs_vtx_offset[0]);
952 add_arg(&args, ARG_VGPR, ctx->ac.i32,
953 &ctx->gs_vtx_offset[1]);
954 add_arg(&args, ARG_VGPR, ctx->ac.i32,
955 &ctx->abi.gs_prim_id);
956 add_arg(&args, ARG_VGPR, ctx->ac.i32,
957 &ctx->gs_vtx_offset[2]);
958 add_arg(&args, ARG_VGPR, ctx->ac.i32,
959 &ctx->gs_vtx_offset[3]);
960 add_arg(&args, ARG_VGPR, ctx->ac.i32,
961 &ctx->gs_vtx_offset[4]);
962 add_arg(&args, ARG_VGPR, ctx->ac.i32,
963 &ctx->gs_vtx_offset[5]);
964 add_arg(&args, ARG_VGPR, ctx->ac.i32,
965 &ctx->abi.gs_invocation_id);
966 }
967 break;
968 case MESA_SHADER_FRAGMENT:
969 declare_global_input_sgprs(ctx, stage, has_previous_stage,
970 previous_stage, &user_sgpr_info,
971 &args, &desc_sets);
972
973 if (ctx->shader_info->info.ps.needs_sample_positions)
974 add_arg(&args, ARG_SGPR, ctx->ac.i32,
975 &ctx->sample_pos_offset);
976
977 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
978 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
979 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
980 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
981 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
982 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
983 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
984 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
985 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
986 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
987 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
988 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
989 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
991 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
992 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
993 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
994 break;
995 default:
996 unreachable("Shader stage not implemented");
997 }
998
999 ctx->main_function = create_llvm_function(
1000 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1001 ctx->max_workgroup_size,
1002 ctx->options->unsafe_math);
1003 set_llvm_calling_convention(ctx->main_function, stage);
1004
1005
1006 ctx->shader_info->num_input_vgprs = 0;
1007 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1008
1009 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1010
1011 if (ctx->stage != MESA_SHADER_FRAGMENT)
1012 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1013
1014 assign_arguments(ctx->main_function, &args);
1015
1016 user_sgpr_idx = 0;
1017
1018 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1019 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1020 &user_sgpr_idx, 2);
1021 if (ctx->options->supports_spill) {
1022 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1023 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1024 NULL, 0, AC_FUNC_ATTR_READNONE);
1025 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1026 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1027 }
1028 }
1029
1030 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1031 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1032 if (has_previous_stage)
1033 user_sgpr_idx = 0;
1034
1035 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1036 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1037
1038 switch (stage) {
1039 case MESA_SHADER_COMPUTE:
1040 if (ctx->shader_info->info.cs.uses_grid_size) {
1041 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1042 &user_sgpr_idx, 3);
1043 }
1044 break;
1045 case MESA_SHADER_VERTEX:
1046 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1047 previous_stage, &user_sgpr_idx);
1048 if (ctx->abi.view_index)
1049 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1050 break;
1051 case MESA_SHADER_TESS_CTRL:
1052 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1053 previous_stage, &user_sgpr_idx);
1054 if (ctx->abi.view_index)
1055 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1056 break;
1057 case MESA_SHADER_TESS_EVAL:
1058 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1059 if (ctx->abi.view_index)
1060 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1061 break;
1062 case MESA_SHADER_GEOMETRY:
1063 if (has_previous_stage) {
1064 if (previous_stage == MESA_SHADER_VERTEX)
1065 set_vs_specific_input_locs(ctx, stage,
1066 has_previous_stage,
1067 previous_stage,
1068 &user_sgpr_idx);
1069 else
1070 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1071 &user_sgpr_idx, 1);
1072 }
1073 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1074 &user_sgpr_idx, 2);
1075 if (ctx->abi.view_index)
1076 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1077 break;
1078 case MESA_SHADER_FRAGMENT:
1079 if (ctx->shader_info->info.ps.needs_sample_positions) {
1080 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1081 &user_sgpr_idx, 1);
1082 }
1083 break;
1084 default:
1085 unreachable("Shader stage not implemented");
1086 }
1087
1088 if (stage == MESA_SHADER_TESS_CTRL ||
1089 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1090 /* GFX9 has the ESGS ring buffer in LDS. */
1091 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1092 ac_declare_lds_as_pointer(&ctx->ac);
1093 }
1094
1095 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1096 }
1097
1098
1099 static LLVMValueRef
1100 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1101 unsigned desc_set, unsigned binding)
1102 {
1103 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1104 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1105 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1106 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1107 unsigned base_offset = layout->binding[binding].offset;
1108 LLVMValueRef offset, stride;
1109
1110 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1111 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1112 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1113 layout->binding[binding].dynamic_offset_offset;
1114 desc_ptr = ctx->abi.push_constants;
1115 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1116 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1117 } else
1118 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1119
1120 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1121 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
1122 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
1123
1124 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1125 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1126 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1127
1128 return desc_ptr;
1129 }
1130
1131
1132 /* The offchip buffer layout for TCS->TES is
1133 *
1134 * - attribute 0 of patch 0 vertex 0
1135 * - attribute 0 of patch 0 vertex 1
1136 * - attribute 0 of patch 0 vertex 2
1137 * ...
1138 * - attribute 0 of patch 1 vertex 0
1139 * - attribute 0 of patch 1 vertex 1
1140 * ...
1141 * - attribute 1 of patch 0 vertex 0
1142 * - attribute 1 of patch 0 vertex 1
1143 * ...
1144 * - per patch attribute 0 of patch 0
1145 * - per patch attribute 0 of patch 1
1146 * ...
1147 *
1148 * Note that every attribute has 4 components.
1149 */
1150 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1151 {
1152 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
1153 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1154 uint32_t output_vertex_size = num_tcs_outputs * 16;
1155 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1156 uint32_t num_patches = ctx->tcs_num_patches;
1157
1158 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1159 } else
1160 return ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
1161 }
1162
1163 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1164 LLVMValueRef vertex_index)
1165 {
1166 LLVMValueRef param_stride;
1167 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
1168 if (vertex_index)
1169 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1170 else
1171 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1172 } else {
1173 LLVMValueRef num_patches = ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
1174 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1175 if (vertex_index)
1176 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
1177 num_patches, "");
1178 else
1179 param_stride = num_patches;
1180 }
1181 return param_stride;
1182 }
1183
1184 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1185 LLVMValueRef vertex_index,
1186 LLVMValueRef param_index)
1187 {
1188 LLVMValueRef base_addr;
1189 LLVMValueRef param_stride, constant16;
1190 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1191 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1192 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1193 param_stride = calc_param_stride(ctx, vertex_index);
1194 if (vertex_index) {
1195 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
1196 vertices_per_patch, "");
1197
1198 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1199 vertex_index, "");
1200 } else {
1201 base_addr = rel_patch_id;
1202 }
1203
1204 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1205 LLVMBuildMul(ctx->ac.builder, param_index,
1206 param_stride, ""), "");
1207
1208 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1209
1210 if (!vertex_index) {
1211 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1212
1213 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1214 patch_data_offset, "");
1215 }
1216 return base_addr;
1217 }
1218
1219 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1220 unsigned param,
1221 unsigned const_index,
1222 bool is_compact,
1223 LLVMValueRef vertex_index,
1224 LLVMValueRef indir_index)
1225 {
1226 LLVMValueRef param_index;
1227
1228 if (indir_index)
1229 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1230 indir_index, "");
1231 else {
1232 if (const_index && !is_compact)
1233 param += const_index;
1234 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1235 }
1236 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1237 }
1238
1239 static void
1240 mark_tess_output(struct radv_shader_context *ctx,
1241 bool is_patch, uint32_t param, int num_slots)
1242
1243 {
1244 uint64_t slot_mask = (1ull << num_slots) - 1;
1245 if (is_patch) {
1246 ctx->tess_patch_outputs_written |= (slot_mask << param);
1247 } else
1248 ctx->tess_outputs_written |= (slot_mask << param);
1249 }
1250
1251 static LLVMValueRef
1252 get_dw_address(struct radv_shader_context *ctx,
1253 LLVMValueRef dw_addr,
1254 unsigned param,
1255 unsigned const_index,
1256 bool compact_const_index,
1257 LLVMValueRef vertex_index,
1258 LLVMValueRef stride,
1259 LLVMValueRef indir_index)
1260
1261 {
1262
1263 if (vertex_index) {
1264 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1265 LLVMBuildMul(ctx->ac.builder,
1266 vertex_index,
1267 stride, ""), "");
1268 }
1269
1270 if (indir_index)
1271 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1272 LLVMBuildMul(ctx->ac.builder, indir_index,
1273 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1274 else if (const_index && !compact_const_index)
1275 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1276 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1277
1278 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1279 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1280
1281 if (const_index && compact_const_index)
1282 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1283 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1284 return dw_addr;
1285 }
1286
1287 static LLVMValueRef
1288 load_tcs_varyings(struct ac_shader_abi *abi,
1289 LLVMTypeRef type,
1290 LLVMValueRef vertex_index,
1291 LLVMValueRef indir_index,
1292 unsigned const_index,
1293 unsigned location,
1294 unsigned driver_location,
1295 unsigned component,
1296 unsigned num_components,
1297 bool is_patch,
1298 bool is_compact,
1299 bool load_input)
1300 {
1301 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1302 LLVMValueRef dw_addr, stride;
1303 LLVMValueRef value[4], result;
1304 unsigned param = shader_io_get_unique_index(location);
1305
1306 if (load_input) {
1307 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1308 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1309 dw_addr = get_tcs_in_current_patch_offset(ctx);
1310 } else {
1311 if (!is_patch) {
1312 stride = get_tcs_out_vertex_stride(ctx);
1313 dw_addr = get_tcs_out_current_patch_offset(ctx);
1314 } else {
1315 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1316 stride = NULL;
1317 }
1318 }
1319
1320 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1321 indir_index);
1322
1323 for (unsigned i = 0; i < num_components + component; i++) {
1324 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1325 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1326 ctx->ac.i32_1, "");
1327 }
1328 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1329 return result;
1330 }
1331
1332 static void
1333 store_tcs_output(struct ac_shader_abi *abi,
1334 const nir_variable *var,
1335 LLVMValueRef vertex_index,
1336 LLVMValueRef param_index,
1337 unsigned const_index,
1338 LLVMValueRef src,
1339 unsigned writemask)
1340 {
1341 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1342 const unsigned location = var->data.location;
1343 const unsigned component = var->data.location_frac;
1344 const bool is_patch = var->data.patch;
1345 const bool is_compact = var->data.compact;
1346 const unsigned count = glsl_count_attribute_slots(var->type, false);
1347 LLVMValueRef dw_addr;
1348 LLVMValueRef stride = NULL;
1349 LLVMValueRef buf_addr = NULL;
1350 unsigned param;
1351 bool store_lds = true;
1352
1353 if (is_patch) {
1354 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1355 store_lds = false;
1356 } else {
1357 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1358 store_lds = false;
1359 }
1360
1361 param = shader_io_get_unique_index(location);
1362 if (location == VARYING_SLOT_CLIP_DIST0 &&
1363 is_compact && const_index > 3) {
1364 const_index -= 3;
1365 param++;
1366 }
1367
1368 if (!is_patch) {
1369 stride = get_tcs_out_vertex_stride(ctx);
1370 dw_addr = get_tcs_out_current_patch_offset(ctx);
1371 } else {
1372 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1373 }
1374
1375 if (param_index)
1376 mark_tess_output(ctx, is_patch, param, count);
1377 else
1378 mark_tess_output(ctx, is_patch, param, 1);
1379
1380 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1381 param_index);
1382 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1383 vertex_index, param_index);
1384
1385 bool is_tess_factor = false;
1386 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1387 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1388 is_tess_factor = true;
1389
1390 unsigned base = is_compact ? const_index : 0;
1391 for (unsigned chan = 0; chan < 8; chan++) {
1392 if (!(writemask & (1 << chan)))
1393 continue;
1394 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1395
1396 if (store_lds || is_tess_factor) {
1397 LLVMValueRef dw_addr_chan =
1398 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1399 LLVMConstInt(ctx->ac.i32, chan, false), "");
1400 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1401 }
1402
1403 if (!is_tess_factor && writemask != 0xF)
1404 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1405 buf_addr, ctx->oc_lds,
1406 4 * (base + chan), 1, 0, true, false);
1407 }
1408
1409 if (writemask == 0xF) {
1410 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1411 buf_addr, ctx->oc_lds,
1412 (base * 4), 1, 0, true, false);
1413 }
1414 }
1415
1416 static LLVMValueRef
1417 load_tes_input(struct ac_shader_abi *abi,
1418 LLVMTypeRef type,
1419 LLVMValueRef vertex_index,
1420 LLVMValueRef param_index,
1421 unsigned const_index,
1422 unsigned location,
1423 unsigned driver_location,
1424 unsigned component,
1425 unsigned num_components,
1426 bool is_patch,
1427 bool is_compact,
1428 bool load_input)
1429 {
1430 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1431 LLVMValueRef buf_addr;
1432 LLVMValueRef result;
1433 unsigned param = shader_io_get_unique_index(location);
1434
1435 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1436 const_index -= 3;
1437 param++;
1438 }
1439
1440 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1441 is_compact, vertex_index, param_index);
1442
1443 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1444 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1445
1446 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1447 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1448 result = ac_trim_vector(&ctx->ac, result, num_components);
1449 return result;
1450 }
1451
1452 static LLVMValueRef
1453 load_gs_input(struct ac_shader_abi *abi,
1454 unsigned location,
1455 unsigned driver_location,
1456 unsigned component,
1457 unsigned num_components,
1458 unsigned vertex_index,
1459 unsigned const_index,
1460 LLVMTypeRef type)
1461 {
1462 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1463 LLVMValueRef vtx_offset;
1464 unsigned param, vtx_offset_param;
1465 LLVMValueRef value[4], result;
1466
1467 vtx_offset_param = vertex_index;
1468 assert(vtx_offset_param < 6);
1469 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1470 LLVMConstInt(ctx->ac.i32, 4, false), "");
1471
1472 param = shader_io_get_unique_index(location);
1473
1474 for (unsigned i = component; i < num_components + component; i++) {
1475 if (ctx->ac.chip_class >= GFX9) {
1476 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1477 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1478 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1479 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1480 } else {
1481 LLVMValueRef soffset =
1482 LLVMConstInt(ctx->ac.i32,
1483 (param * 4 + i + const_index) * 256,
1484 false);
1485
1486 value[i] = ac_build_buffer_load(&ctx->ac,
1487 ctx->esgs_ring, 1,
1488 ctx->ac.i32_0,
1489 vtx_offset, soffset,
1490 0, 1, 0, true, false);
1491
1492 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
1493 type, "");
1494 }
1495 }
1496 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1497 result = ac_to_integer(&ctx->ac, result);
1498 return result;
1499 }
1500
1501
1502 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1503 {
1504 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1505 ac_build_kill_if_false(&ctx->ac, visible);
1506 }
1507
1508 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1509 enum glsl_interp_mode interp, unsigned location)
1510 {
1511 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1512
1513 switch (interp) {
1514 case INTERP_MODE_FLAT:
1515 default:
1516 return NULL;
1517 case INTERP_MODE_SMOOTH:
1518 case INTERP_MODE_NONE:
1519 if (location == INTERP_CENTER)
1520 return ctx->persp_center;
1521 else if (location == INTERP_CENTROID)
1522 return ctx->persp_centroid;
1523 else if (location == INTERP_SAMPLE)
1524 return ctx->persp_sample;
1525 break;
1526 case INTERP_MODE_NOPERSPECTIVE:
1527 if (location == INTERP_CENTER)
1528 return ctx->linear_center;
1529 else if (location == INTERP_CENTROID)
1530 return ctx->linear_centroid;
1531 else if (location == INTERP_SAMPLE)
1532 return ctx->linear_sample;
1533 break;
1534 }
1535 return NULL;
1536 }
1537
1538 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1539 LLVMValueRef sample_id)
1540 {
1541 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1542
1543 LLVMValueRef result;
1544 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1545
1546 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1547 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1548
1549 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
1550 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1551
1552 return result;
1553 }
1554
1555
1556 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1557 {
1558 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1559 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
1560 ctx->options->key.fs.log2_num_samples :
1561 ctx->options->key.fs.log2_ps_iter_samples;
1562
1563 /* The bit pattern matches that used by fixed function fragment
1564 * processing. */
1565 static const uint16_t ps_iter_masks[] = {
1566 0xffff, /* not used */
1567 0x5555,
1568 0x1111,
1569 0x0101,
1570 0x0001,
1571 };
1572 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1573
1574 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1575
1576 LLVMValueRef result, sample_id;
1577 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1578 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1579 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1580 return result;
1581 }
1582
1583
1584 static void
1585 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1586 {
1587 LLVMValueRef gs_next_vertex;
1588 LLVMValueRef can_emit;
1589 int idx;
1590 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1591
1592 assert(stream == 0);
1593
1594 /* Write vertex attribute values to GSVS ring */
1595 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1596 ctx->gs_next_vertex,
1597 "");
1598
1599 /* If this thread has already emitted the declared maximum number of
1600 * vertices, kill it: excessive vertex emissions are not supposed to
1601 * have any effect, and GS threads have no externally observable
1602 * effects other than emitting vertices.
1603 */
1604 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1605 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1606 ac_build_kill_if_false(&ctx->ac, can_emit);
1607
1608 /* loop num outputs */
1609 idx = 0;
1610 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1611 LLVMValueRef *out_ptr = &addrs[i * 4];
1612 int length = 4;
1613 int slot = idx;
1614 int slot_inc = 1;
1615
1616 if (!(ctx->output_mask & (1ull << i)))
1617 continue;
1618
1619 if (i == VARYING_SLOT_CLIP_DIST0) {
1620 /* pack clip and cull into a single set of slots */
1621 length = ctx->num_output_clips + ctx->num_output_culls;
1622 if (length > 4)
1623 slot_inc = 2;
1624 }
1625 for (unsigned j = 0; j < length; j++) {
1626 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1627 out_ptr[j], "");
1628 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1629 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1630 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1631
1632 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1633
1634 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1635 out_val, 1,
1636 voffset, ctx->gs2vs_offset, 0,
1637 1, 1, true, true);
1638 }
1639 idx += slot_inc;
1640 }
1641
1642 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1643 ctx->ac.i32_1, "");
1644 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1645
1646 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1647 }
1648
1649 static void
1650 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1651 {
1652 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1653 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1654 }
1655
1656 static LLVMValueRef
1657 load_tess_coord(struct ac_shader_abi *abi)
1658 {
1659 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1660
1661 LLVMValueRef coord[4] = {
1662 ctx->tes_u,
1663 ctx->tes_v,
1664 ctx->ac.f32_0,
1665 ctx->ac.f32_0,
1666 };
1667
1668 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1669 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1670 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1671
1672 return ac_build_gather_values(&ctx->ac, coord, 3);
1673 }
1674
1675 static LLVMValueRef
1676 load_patch_vertices_in(struct ac_shader_abi *abi)
1677 {
1678 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1679 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1680 }
1681
1682
1683 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1684 {
1685 return abi->base_vertex;
1686 }
1687
1688 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1689 LLVMValueRef buffer_ptr, bool write)
1690 {
1691 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1692 LLVMValueRef result;
1693
1694 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1695
1696 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1697 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1698
1699 return result;
1700 }
1701
1702 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1703 {
1704 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1705 LLVMValueRef result;
1706
1707 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1708
1709 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1710 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1711
1712 return result;
1713 }
1714
1715 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1716 unsigned descriptor_set,
1717 unsigned base_index,
1718 unsigned constant_index,
1719 LLVMValueRef index,
1720 enum ac_descriptor_type desc_type,
1721 bool image, bool write)
1722 {
1723 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1724 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1725 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1726 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1727 unsigned offset = binding->offset;
1728 unsigned stride = binding->size;
1729 unsigned type_size;
1730 LLVMBuilderRef builder = ctx->ac.builder;
1731 LLVMTypeRef type;
1732
1733 assert(base_index < layout->binding_count);
1734
1735 switch (desc_type) {
1736 case AC_DESC_IMAGE:
1737 type = ctx->ac.v8i32;
1738 type_size = 32;
1739 break;
1740 case AC_DESC_FMASK:
1741 type = ctx->ac.v8i32;
1742 offset += 32;
1743 type_size = 32;
1744 break;
1745 case AC_DESC_SAMPLER:
1746 type = ctx->ac.v4i32;
1747 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1748 offset += 64;
1749
1750 type_size = 16;
1751 break;
1752 case AC_DESC_BUFFER:
1753 type = ctx->ac.v4i32;
1754 type_size = 16;
1755 break;
1756 default:
1757 unreachable("invalid desc_type\n");
1758 }
1759
1760 offset += constant_index * stride;
1761
1762 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1763 (!index || binding->immutable_samplers_equal)) {
1764 if (binding->immutable_samplers_equal)
1765 constant_index = 0;
1766
1767 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1768
1769 LLVMValueRef constants[] = {
1770 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1771 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1772 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1773 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1774 };
1775 return ac_build_gather_values(&ctx->ac, constants, 4);
1776 }
1777
1778 assert(stride % type_size == 0);
1779
1780 if (!index)
1781 index = ctx->ac.i32_0;
1782
1783 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1784
1785 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1786 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
1787
1788 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1789 }
1790
1791
1792 static void
1793 handle_vs_input_decl(struct radv_shader_context *ctx,
1794 struct nir_variable *variable)
1795 {
1796 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1797 LLVMValueRef t_offset;
1798 LLVMValueRef t_list;
1799 LLVMValueRef input;
1800 LLVMValueRef buffer_index;
1801 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
1802 int idx = variable->data.location;
1803 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1804 uint8_t input_usage_mask =
1805 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1806 unsigned num_channels = util_last_bit(input_usage_mask);
1807
1808 variable->data.driver_location = idx * 4;
1809
1810 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
1811 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
1812 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
1813 ctx->abi.start_instance, "");
1814 if (ctx->options->key.vs.as_ls) {
1815 ctx->shader_info->vs.vgpr_comp_cnt =
1816 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1817 } else {
1818 ctx->shader_info->vs.vgpr_comp_cnt =
1819 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1820 }
1821 } else
1822 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
1823 ctx->abi.base_vertex, "");
1824 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
1825
1826 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1827
1828 input = ac_build_buffer_load_format(&ctx->ac, t_list,
1829 buffer_index,
1830 ctx->ac.i32_0,
1831 num_channels, false, true);
1832
1833 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
1834
1835 for (unsigned chan = 0; chan < 4; chan++) {
1836 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1837 ctx->inputs[ac_llvm_reg_index_soa(idx, chan)] =
1838 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
1839 input, llvm_chan, ""));
1840 }
1841 }
1842 }
1843
1844 static void interp_fs_input(struct radv_shader_context *ctx,
1845 unsigned attr,
1846 LLVMValueRef interp_param,
1847 LLVMValueRef prim_mask,
1848 LLVMValueRef result[4])
1849 {
1850 LLVMValueRef attr_number;
1851 unsigned chan;
1852 LLVMValueRef i, j;
1853 bool interp = interp_param != NULL;
1854
1855 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
1856
1857 /* fs.constant returns the param from the middle vertex, so it's not
1858 * really useful for flat shading. It's meant to be used for custom
1859 * interpolation (but the intrinsic can't fetch from the other two
1860 * vertices).
1861 *
1862 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1863 * to do the right thing. The only reason we use fs.constant is that
1864 * fs.interp cannot be used on integers, because they can be equal
1865 * to NaN.
1866 */
1867 if (interp) {
1868 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1869 ctx->ac.v2f32, "");
1870
1871 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1872 ctx->ac.i32_0, "");
1873 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1874 ctx->ac.i32_1, "");
1875 }
1876
1877 for (chan = 0; chan < 4; chan++) {
1878 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1879
1880 if (interp) {
1881 result[chan] = ac_build_fs_interp(&ctx->ac,
1882 llvm_chan,
1883 attr_number,
1884 prim_mask, i, j);
1885 } else {
1886 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1887 LLVMConstInt(ctx->ac.i32, 2, false),
1888 llvm_chan,
1889 attr_number,
1890 prim_mask);
1891 }
1892 }
1893 }
1894
1895 static void
1896 handle_fs_input_decl(struct radv_shader_context *ctx,
1897 struct nir_variable *variable)
1898 {
1899 int idx = variable->data.location;
1900 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1901 LLVMValueRef interp;
1902
1903 variable->data.driver_location = idx * 4;
1904 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
1905
1906 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
1907 unsigned interp_type;
1908 if (variable->data.sample)
1909 interp_type = INTERP_SAMPLE;
1910 else if (variable->data.centroid)
1911 interp_type = INTERP_CENTROID;
1912 else
1913 interp_type = INTERP_CENTER;
1914
1915 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
1916 } else
1917 interp = NULL;
1918
1919 for (unsigned i = 0; i < attrib_count; ++i)
1920 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
1921
1922 }
1923
1924 static void
1925 handle_vs_inputs(struct radv_shader_context *ctx,
1926 struct nir_shader *nir) {
1927 nir_foreach_variable(variable, &nir->inputs)
1928 handle_vs_input_decl(ctx, variable);
1929 }
1930
1931 static void
1932 prepare_interp_optimize(struct radv_shader_context *ctx,
1933 struct nir_shader *nir)
1934 {
1935 if (!ctx->options->key.fs.multisample)
1936 return;
1937
1938 bool uses_center = false;
1939 bool uses_centroid = false;
1940 nir_foreach_variable(variable, &nir->inputs) {
1941 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1942 variable->data.sample)
1943 continue;
1944
1945 if (variable->data.centroid)
1946 uses_centroid = true;
1947 else
1948 uses_center = true;
1949 }
1950
1951 if (uses_center && uses_centroid) {
1952 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
1953 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
1954 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
1955 }
1956 }
1957
1958 static void
1959 handle_fs_inputs(struct radv_shader_context *ctx,
1960 struct nir_shader *nir)
1961 {
1962 prepare_interp_optimize(ctx, nir);
1963
1964 nir_foreach_variable(variable, &nir->inputs)
1965 handle_fs_input_decl(ctx, variable);
1966
1967 unsigned index = 0;
1968
1969 if (ctx->shader_info->info.ps.uses_input_attachments ||
1970 ctx->shader_info->info.needs_multiview_view_index)
1971 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
1972
1973 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
1974 LLVMValueRef interp_param;
1975 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
1976
1977 if (!(ctx->input_mask & (1ull << i)))
1978 continue;
1979
1980 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
1981 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
1982 interp_param = *inputs;
1983 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
1984 inputs);
1985
1986 if (!interp_param)
1987 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
1988 ++index;
1989 } else if (i == VARYING_SLOT_POS) {
1990 for(int i = 0; i < 3; ++i)
1991 inputs[i] = ctx->abi.frag_pos[i];
1992
1993 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
1994 ctx->abi.frag_pos[3]);
1995 }
1996 }
1997 ctx->shader_info->fs.num_interp = index;
1998 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
1999
2000 if (ctx->shader_info->info.needs_multiview_view_index)
2001 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2002 }
2003
2004 static void
2005 scan_shader_output_decl(struct radv_shader_context *ctx,
2006 struct nir_variable *variable,
2007 struct nir_shader *shader,
2008 gl_shader_stage stage)
2009 {
2010 int idx = variable->data.location + variable->data.index;
2011 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2012 uint64_t mask_attribs;
2013
2014 variable->data.driver_location = idx * 4;
2015
2016 /* tess ctrl has it's own load/store paths for outputs */
2017 if (stage == MESA_SHADER_TESS_CTRL)
2018 return;
2019
2020 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2021 if (stage == MESA_SHADER_VERTEX ||
2022 stage == MESA_SHADER_TESS_EVAL ||
2023 stage == MESA_SHADER_GEOMETRY) {
2024 if (idx == VARYING_SLOT_CLIP_DIST0) {
2025 int length = shader->info.clip_distance_array_size +
2026 shader->info.cull_distance_array_size;
2027 if (stage == MESA_SHADER_VERTEX) {
2028 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2029 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2030 }
2031 if (stage == MESA_SHADER_TESS_EVAL) {
2032 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2033 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2034 }
2035
2036 if (length > 4)
2037 attrib_count = 2;
2038 else
2039 attrib_count = 1;
2040 mask_attribs = 1ull << idx;
2041 }
2042 }
2043
2044 ctx->output_mask |= mask_attribs;
2045 }
2046
2047
2048 /* Initialize arguments for the shader export intrinsic */
2049 static void
2050 si_llvm_init_export_args(struct radv_shader_context *ctx,
2051 LLVMValueRef *values,
2052 unsigned enabled_channels,
2053 unsigned target,
2054 struct ac_export_args *args)
2055 {
2056 /* Specify the channels that are enabled. */
2057 args->enabled_channels = enabled_channels;
2058
2059 /* Specify whether the EXEC mask represents the valid mask */
2060 args->valid_mask = 0;
2061
2062 /* Specify whether this is the last export */
2063 args->done = 0;
2064
2065 /* Specify the target we are exporting */
2066 args->target = target;
2067
2068 args->compr = false;
2069 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2070 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2071 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2072 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2073
2074 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2075 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2076 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2077 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2078 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2079 unsigned chan;
2080
2081 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2082 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2083 unsigned bits, bool hi) = NULL;
2084
2085 switch(col_format) {
2086 case V_028714_SPI_SHADER_ZERO:
2087 args->enabled_channels = 0; /* writemask */
2088 args->target = V_008DFC_SQ_EXP_NULL;
2089 break;
2090
2091 case V_028714_SPI_SHADER_32_R:
2092 args->enabled_channels = 1;
2093 args->out[0] = values[0];
2094 break;
2095
2096 case V_028714_SPI_SHADER_32_GR:
2097 args->enabled_channels = 0x3;
2098 args->out[0] = values[0];
2099 args->out[1] = values[1];
2100 break;
2101
2102 case V_028714_SPI_SHADER_32_AR:
2103 args->enabled_channels = 0x9;
2104 args->out[0] = values[0];
2105 args->out[3] = values[3];
2106 break;
2107
2108 case V_028714_SPI_SHADER_FP16_ABGR:
2109 args->enabled_channels = 0x5;
2110 packf = ac_build_cvt_pkrtz_f16;
2111 break;
2112
2113 case V_028714_SPI_SHADER_UNORM16_ABGR:
2114 args->enabled_channels = 0x5;
2115 packf = ac_build_cvt_pknorm_u16;
2116 break;
2117
2118 case V_028714_SPI_SHADER_SNORM16_ABGR:
2119 args->enabled_channels = 0x5;
2120 packf = ac_build_cvt_pknorm_i16;
2121 break;
2122
2123 case V_028714_SPI_SHADER_UINT16_ABGR:
2124 args->enabled_channels = 0x5;
2125 packi = ac_build_cvt_pk_u16;
2126 break;
2127
2128 case V_028714_SPI_SHADER_SINT16_ABGR:
2129 args->enabled_channels = 0x5;
2130 packi = ac_build_cvt_pk_i16;
2131 break;
2132
2133 default:
2134 case V_028714_SPI_SHADER_32_ABGR:
2135 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2136 break;
2137 }
2138
2139 /* Pack f16 or norm_i16/u16. */
2140 if (packf) {
2141 for (chan = 0; chan < 2; chan++) {
2142 LLVMValueRef pack_args[2] = {
2143 values[2 * chan],
2144 values[2 * chan + 1]
2145 };
2146 LLVMValueRef packed;
2147
2148 packed = packf(&ctx->ac, pack_args);
2149 args->out[chan] = ac_to_float(&ctx->ac, packed);
2150 }
2151 args->compr = 1; /* COMPR flag */
2152 }
2153
2154 /* Pack i16/u16. */
2155 if (packi) {
2156 for (chan = 0; chan < 2; chan++) {
2157 LLVMValueRef pack_args[2] = {
2158 ac_to_integer(&ctx->ac, values[2 * chan]),
2159 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2160 };
2161 LLVMValueRef packed;
2162
2163 packed = packi(&ctx->ac, pack_args,
2164 is_int8 ? 8 : is_int10 ? 10 : 16,
2165 chan == 1);
2166 args->out[chan] = ac_to_float(&ctx->ac, packed);
2167 }
2168 args->compr = 1; /* COMPR flag */
2169 }
2170 return;
2171 }
2172
2173 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2174
2175 for (unsigned i = 0; i < 4; ++i) {
2176 if (!(args->enabled_channels & (1 << i)))
2177 continue;
2178
2179 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2180 }
2181 }
2182
2183 static void
2184 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2185 LLVMValueRef *values, unsigned enabled_channels)
2186 {
2187 struct ac_export_args args;
2188
2189 si_llvm_init_export_args(ctx, values, enabled_channels,
2190 V_008DFC_SQ_EXP_PARAM + index, &args);
2191 ac_build_export(&ctx->ac, &args);
2192 }
2193
2194 static LLVMValueRef
2195 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2196 {
2197 LLVMValueRef output =
2198 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2199
2200 return LLVMBuildLoad(ctx->ac.builder, output, "");
2201 }
2202
2203 static void
2204 handle_vs_outputs_post(struct radv_shader_context *ctx,
2205 bool export_prim_id,
2206 struct radv_vs_output_info *outinfo)
2207 {
2208 uint32_t param_count = 0;
2209 unsigned target;
2210 unsigned pos_idx, num_pos_exports = 0;
2211 struct ac_export_args args, pos_args[4] = {};
2212 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2213 int i;
2214
2215 if (ctx->options->key.has_multiview_view_index) {
2216 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2217 if(!*tmp_out) {
2218 for(unsigned i = 0; i < 4; ++i)
2219 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2220 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2221 }
2222
2223 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2224 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2225 }
2226
2227 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2228 sizeof(outinfo->vs_output_param_offset));
2229
2230 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2231 LLVMValueRef slots[8];
2232 unsigned j;
2233
2234 if (outinfo->cull_dist_mask)
2235 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2236
2237 i = VARYING_SLOT_CLIP_DIST0;
2238 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
2239 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2240
2241 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
2242 slots[i] = LLVMGetUndef(ctx->ac.f32);
2243
2244 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
2245 target = V_008DFC_SQ_EXP_POS + 3;
2246 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2247 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2248 &args, sizeof(args));
2249 }
2250
2251 target = V_008DFC_SQ_EXP_POS + 2;
2252 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2253 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2254 &args, sizeof(args));
2255
2256 }
2257
2258 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2259 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2260 for (unsigned j = 0; j < 4; j++)
2261 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2262 }
2263 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2264
2265 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2266 outinfo->writes_pointsize = true;
2267 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2268 }
2269
2270 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2271 outinfo->writes_layer = true;
2272 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2273 }
2274
2275 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2276 outinfo->writes_viewport_index = true;
2277 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2278 }
2279
2280 if (outinfo->writes_pointsize ||
2281 outinfo->writes_layer ||
2282 outinfo->writes_viewport_index) {
2283 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2284 (outinfo->writes_layer == true ? 4 : 0));
2285 pos_args[1].valid_mask = 0;
2286 pos_args[1].done = 0;
2287 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2288 pos_args[1].compr = 0;
2289 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2290 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2291 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2292 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2293
2294 if (outinfo->writes_pointsize == true)
2295 pos_args[1].out[0] = psize_value;
2296 if (outinfo->writes_layer == true)
2297 pos_args[1].out[2] = layer_value;
2298 if (outinfo->writes_viewport_index == true) {
2299 if (ctx->options->chip_class >= GFX9) {
2300 /* GFX9 has the layer in out.z[10:0] and the viewport
2301 * index in out.z[19:16].
2302 */
2303 LLVMValueRef v = viewport_index_value;
2304 v = ac_to_integer(&ctx->ac, v);
2305 v = LLVMBuildShl(ctx->ac.builder, v,
2306 LLVMConstInt(ctx->ac.i32, 16, false),
2307 "");
2308 v = LLVMBuildOr(ctx->ac.builder, v,
2309 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2310
2311 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2312 pos_args[1].enabled_channels |= 1 << 2;
2313 } else {
2314 pos_args[1].out[3] = viewport_index_value;
2315 pos_args[1].enabled_channels |= 1 << 3;
2316 }
2317 }
2318 }
2319 for (i = 0; i < 4; i++) {
2320 if (pos_args[i].out[0])
2321 num_pos_exports++;
2322 }
2323
2324 pos_idx = 0;
2325 for (i = 0; i < 4; i++) {
2326 if (!pos_args[i].out[0])
2327 continue;
2328
2329 /* Specify the target we are exporting */
2330 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2331 if (pos_idx == num_pos_exports)
2332 pos_args[i].done = 1;
2333 ac_build_export(&ctx->ac, &pos_args[i]);
2334 }
2335
2336 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2337 LLVMValueRef values[4];
2338 if (!(ctx->output_mask & (1ull << i)))
2339 continue;
2340
2341 if (i != VARYING_SLOT_LAYER &&
2342 i != VARYING_SLOT_PRIMITIVE_ID &&
2343 i < VARYING_SLOT_VAR0)
2344 continue;
2345
2346 for (unsigned j = 0; j < 4; j++)
2347 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2348
2349 unsigned output_usage_mask;
2350
2351 if (ctx->stage == MESA_SHADER_VERTEX &&
2352 !ctx->is_gs_copy_shader) {
2353 output_usage_mask =
2354 ctx->shader_info->info.vs.output_usage_mask[i];
2355 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2356 output_usage_mask =
2357 ctx->shader_info->info.tes.output_usage_mask[i];
2358 } else {
2359 /* Enable all channels for the GS copy shader because
2360 * we don't know the output usage mask currently.
2361 */
2362 output_usage_mask = 0xf;
2363 }
2364
2365 radv_export_param(ctx, param_count, values, output_usage_mask);
2366
2367 outinfo->vs_output_param_offset[i] = param_count++;
2368 }
2369
2370 if (export_prim_id) {
2371 LLVMValueRef values[4];
2372
2373 values[0] = ctx->vs_prim_id;
2374 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2375 ctx->shader_info->vs.vgpr_comp_cnt);
2376 for (unsigned j = 1; j < 4; j++)
2377 values[j] = ctx->ac.f32_0;
2378
2379 radv_export_param(ctx, param_count, values, 0xf);
2380
2381 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2382 outinfo->export_prim_id = true;
2383 }
2384
2385 outinfo->pos_exports = num_pos_exports;
2386 outinfo->param_exports = param_count;
2387 }
2388
2389 static void
2390 handle_es_outputs_post(struct radv_shader_context *ctx,
2391 struct radv_es_output_info *outinfo)
2392 {
2393 int j;
2394 uint64_t max_output_written = 0;
2395 LLVMValueRef lds_base = NULL;
2396
2397 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2398 int param_index;
2399 int length = 4;
2400
2401 if (!(ctx->output_mask & (1ull << i)))
2402 continue;
2403
2404 if (i == VARYING_SLOT_CLIP_DIST0)
2405 length = ctx->num_output_clips + ctx->num_output_culls;
2406
2407 param_index = shader_io_get_unique_index(i);
2408
2409 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2410 }
2411
2412 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2413
2414 if (ctx->ac.chip_class >= GFX9) {
2415 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2416 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2417 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2418 LLVMConstInt(ctx->ac.i32, 24, false),
2419 LLVMConstInt(ctx->ac.i32, 4, false), false);
2420 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2421 LLVMBuildMul(ctx->ac.builder, wave_idx,
2422 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2423 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2424 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2425 }
2426
2427 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2428 LLVMValueRef dw_addr = NULL;
2429 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2430 int param_index;
2431 int length = 4;
2432
2433 if (!(ctx->output_mask & (1ull << i)))
2434 continue;
2435
2436 if (i == VARYING_SLOT_CLIP_DIST0)
2437 length = ctx->num_output_clips + ctx->num_output_culls;
2438
2439 param_index = shader_io_get_unique_index(i);
2440
2441 if (lds_base) {
2442 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2443 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2444 "");
2445 }
2446 for (j = 0; j < length; j++) {
2447 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2448 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2449
2450 if (ctx->ac.chip_class >= GFX9) {
2451 ac_lds_store(&ctx->ac, dw_addr,
2452 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2453 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2454 } else {
2455 ac_build_buffer_store_dword(&ctx->ac,
2456 ctx->esgs_ring,
2457 out_val, 1,
2458 NULL, ctx->es2gs_offset,
2459 (4 * param_index + j) * 4,
2460 1, 1, true, true);
2461 }
2462 }
2463 }
2464 }
2465
2466 static void
2467 handle_ls_outputs_post(struct radv_shader_context *ctx)
2468 {
2469 LLVMValueRef vertex_id = ctx->rel_auto_id;
2470 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2471 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2472 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2473 vertex_dw_stride, "");
2474
2475 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2476 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2477 int length = 4;
2478
2479 if (!(ctx->output_mask & (1ull << i)))
2480 continue;
2481
2482 if (i == VARYING_SLOT_CLIP_DIST0)
2483 length = ctx->num_output_clips + ctx->num_output_culls;
2484 int param = shader_io_get_unique_index(i);
2485 mark_tess_output(ctx, false, param, 1);
2486 if (length > 4)
2487 mark_tess_output(ctx, false, param + 1, 1);
2488 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2489 LLVMConstInt(ctx->ac.i32, param * 4, false),
2490 "");
2491 for (unsigned j = 0; j < length; j++) {
2492 ac_lds_store(&ctx->ac, dw_addr,
2493 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2494 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2495 }
2496 }
2497 }
2498
2499 struct ac_build_if_state
2500 {
2501 struct radv_shader_context *ctx;
2502 LLVMValueRef condition;
2503 LLVMBasicBlockRef entry_block;
2504 LLVMBasicBlockRef true_block;
2505 LLVMBasicBlockRef false_block;
2506 LLVMBasicBlockRef merge_block;
2507 };
2508
2509 static LLVMBasicBlockRef
2510 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
2511 {
2512 LLVMBasicBlockRef current_block;
2513 LLVMBasicBlockRef next_block;
2514 LLVMBasicBlockRef new_block;
2515
2516 /* get current basic block */
2517 current_block = LLVMGetInsertBlock(ctx->ac.builder);
2518
2519 /* chqeck if there's another block after this one */
2520 next_block = LLVMGetNextBasicBlock(current_block);
2521 if (next_block) {
2522 /* insert the new block before the next block */
2523 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
2524 }
2525 else {
2526 /* append new block after current block */
2527 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
2528 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
2529 }
2530 return new_block;
2531 }
2532
2533 static void
2534 ac_nir_build_if(struct ac_build_if_state *ifthen,
2535 struct radv_shader_context *ctx,
2536 LLVMValueRef condition)
2537 {
2538 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
2539
2540 memset(ifthen, 0, sizeof *ifthen);
2541 ifthen->ctx = ctx;
2542 ifthen->condition = condition;
2543 ifthen->entry_block = block;
2544
2545 /* create endif/merge basic block for the phi functions */
2546 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
2547
2548 /* create/insert true_block before merge_block */
2549 ifthen->true_block =
2550 LLVMInsertBasicBlockInContext(ctx->context,
2551 ifthen->merge_block,
2552 "if-true-block");
2553
2554 /* successive code goes into the true block */
2555 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
2556 }
2557
2558 /**
2559 * End a conditional.
2560 */
2561 static void
2562 ac_nir_build_endif(struct ac_build_if_state *ifthen)
2563 {
2564 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
2565
2566 /* Insert branch to the merge block from current block */
2567 LLVMBuildBr(builder, ifthen->merge_block);
2568
2569 /*
2570 * Now patch in the various branch instructions.
2571 */
2572
2573 /* Insert the conditional branch instruction at the end of entry_block */
2574 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
2575 if (ifthen->false_block) {
2576 /* we have an else clause */
2577 LLVMBuildCondBr(builder, ifthen->condition,
2578 ifthen->true_block, ifthen->false_block);
2579 }
2580 else {
2581 /* no else clause */
2582 LLVMBuildCondBr(builder, ifthen->condition,
2583 ifthen->true_block, ifthen->merge_block);
2584 }
2585
2586 /* Resume building code at end of the ifthen->merge_block */
2587 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
2588 }
2589
2590 static void
2591 write_tess_factors(struct radv_shader_context *ctx)
2592 {
2593 unsigned stride, outer_comps, inner_comps;
2594 struct ac_build_if_state if_ctx, inner_if_ctx;
2595 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2596 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2597 unsigned tess_inner_index = 0, tess_outer_index;
2598 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2599 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2600 int i;
2601 ac_emit_barrier(&ctx->ac, ctx->stage);
2602
2603 switch (ctx->options->key.tcs.primitive_mode) {
2604 case GL_ISOLINES:
2605 stride = 2;
2606 outer_comps = 2;
2607 inner_comps = 0;
2608 break;
2609 case GL_TRIANGLES:
2610 stride = 4;
2611 outer_comps = 3;
2612 inner_comps = 1;
2613 break;
2614 case GL_QUADS:
2615 stride = 6;
2616 outer_comps = 4;
2617 inner_comps = 2;
2618 break;
2619 default:
2620 return;
2621 }
2622
2623 ac_nir_build_if(&if_ctx, ctx,
2624 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2625 invocation_id, ctx->ac.i32_0, ""));
2626
2627 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2628
2629 if (inner_comps) {
2630 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2631 mark_tess_output(ctx, true, tess_inner_index, 1);
2632 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2633 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2634 }
2635
2636 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2637 mark_tess_output(ctx, true, tess_outer_index, 1);
2638 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2639 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2640
2641 for (i = 0; i < 4; i++) {
2642 inner[i] = LLVMGetUndef(ctx->ac.i32);
2643 outer[i] = LLVMGetUndef(ctx->ac.i32);
2644 }
2645
2646 // LINES reverseal
2647 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2648 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2649 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2650 ctx->ac.i32_1, "");
2651 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2652 } else {
2653 for (i = 0; i < outer_comps; i++) {
2654 outer[i] = out[i] =
2655 ac_lds_load(&ctx->ac, lds_outer);
2656 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2657 ctx->ac.i32_1, "");
2658 }
2659 for (i = 0; i < inner_comps; i++) {
2660 inner[i] = out[outer_comps+i] =
2661 ac_lds_load(&ctx->ac, lds_inner);
2662 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2663 ctx->ac.i32_1, "");
2664 }
2665 }
2666
2667 /* Convert the outputs to vectors for stores. */
2668 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2669 vec1 = NULL;
2670
2671 if (stride > 4)
2672 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2673
2674
2675 buffer = ctx->hs_ring_tess_factor;
2676 tf_base = ctx->tess_factor_offset;
2677 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2678 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2679 unsigned tf_offset = 0;
2680
2681 if (ctx->options->chip_class <= VI) {
2682 ac_nir_build_if(&inner_if_ctx, ctx,
2683 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2684 rel_patch_id, ctx->ac.i32_0, ""));
2685
2686 /* Store the dynamic HS control word. */
2687 ac_build_buffer_store_dword(&ctx->ac, buffer,
2688 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2689 1, ctx->ac.i32_0, tf_base,
2690 0, 1, 0, true, false);
2691 tf_offset += 4;
2692
2693 ac_nir_build_endif(&inner_if_ctx);
2694 }
2695
2696 /* Store the tessellation factors. */
2697 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2698 MIN2(stride, 4), byteoffset, tf_base,
2699 tf_offset, 1, 0, true, false);
2700 if (vec1)
2701 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2702 stride - 4, byteoffset, tf_base,
2703 16 + tf_offset, 1, 0, true, false);
2704
2705 //store to offchip for TES to read - only if TES reads them
2706 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2707 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2708 LLVMValueRef tf_inner_offset;
2709 unsigned param_outer, param_inner;
2710
2711 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2712 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2713 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2714
2715 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2716 util_next_power_of_two(outer_comps));
2717
2718 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2719 outer_comps, tf_outer_offset,
2720 ctx->oc_lds, 0, 1, 0, true, false);
2721 if (inner_comps) {
2722 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2723 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2724 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2725
2726 inner_vec = inner_comps == 1 ? inner[0] :
2727 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2728 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2729 inner_comps, tf_inner_offset,
2730 ctx->oc_lds, 0, 1, 0, true, false);
2731 }
2732 }
2733 ac_nir_build_endif(&if_ctx);
2734 }
2735
2736 static void
2737 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2738 {
2739 write_tess_factors(ctx);
2740 }
2741
2742 static bool
2743 si_export_mrt_color(struct radv_shader_context *ctx,
2744 LLVMValueRef *color, unsigned index,
2745 struct ac_export_args *args)
2746 {
2747 /* Export */
2748 si_llvm_init_export_args(ctx, color, 0xf,
2749 V_008DFC_SQ_EXP_MRT + index, args);
2750 if (!args->enabled_channels)
2751 return false; /* unnecessary NULL export */
2752
2753 return true;
2754 }
2755
2756 static void
2757 radv_export_mrt_z(struct radv_shader_context *ctx,
2758 LLVMValueRef depth, LLVMValueRef stencil,
2759 LLVMValueRef samplemask)
2760 {
2761 struct ac_export_args args;
2762
2763 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2764
2765 ac_build_export(&ctx->ac, &args);
2766 }
2767
2768 static void
2769 handle_fs_outputs_post(struct radv_shader_context *ctx)
2770 {
2771 unsigned index = 0;
2772 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2773 struct ac_export_args color_args[8];
2774
2775 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2776 LLVMValueRef values[4];
2777
2778 if (!(ctx->output_mask & (1ull << i)))
2779 continue;
2780
2781 if (i < FRAG_RESULT_DATA0)
2782 continue;
2783
2784 for (unsigned j = 0; j < 4; j++)
2785 values[j] = ac_to_float(&ctx->ac,
2786 radv_load_output(ctx, i, j));
2787
2788 bool ret = si_export_mrt_color(ctx, values,
2789 i - FRAG_RESULT_DATA0,
2790 &color_args[index]);
2791 if (ret)
2792 index++;
2793 }
2794
2795 /* Process depth, stencil, samplemask. */
2796 if (ctx->shader_info->info.ps.writes_z) {
2797 depth = ac_to_float(&ctx->ac,
2798 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
2799 }
2800 if (ctx->shader_info->info.ps.writes_stencil) {
2801 stencil = ac_to_float(&ctx->ac,
2802 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
2803 }
2804 if (ctx->shader_info->info.ps.writes_sample_mask) {
2805 samplemask = ac_to_float(&ctx->ac,
2806 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
2807 }
2808
2809 /* Set the DONE bit on last non-null color export only if Z isn't
2810 * exported.
2811 */
2812 if (index > 0 &&
2813 !ctx->shader_info->info.ps.writes_z &&
2814 !ctx->shader_info->info.ps.writes_stencil &&
2815 !ctx->shader_info->info.ps.writes_sample_mask) {
2816 unsigned last = index - 1;
2817
2818 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
2819 color_args[last].done = 1; /* DONE bit */
2820 }
2821
2822 /* Export PS outputs. */
2823 for (unsigned i = 0; i < index; i++)
2824 ac_build_export(&ctx->ac, &color_args[i]);
2825
2826 if (depth || stencil || samplemask)
2827 radv_export_mrt_z(ctx, depth, stencil, samplemask);
2828 else if (!index)
2829 ac_build_export_null(&ctx->ac);
2830 }
2831
2832 static void
2833 emit_gs_epilogue(struct radv_shader_context *ctx)
2834 {
2835 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
2836 }
2837
2838 static void
2839 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
2840 LLVMValueRef *addrs)
2841 {
2842 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2843
2844 switch (ctx->stage) {
2845 case MESA_SHADER_VERTEX:
2846 if (ctx->options->key.vs.as_ls)
2847 handle_ls_outputs_post(ctx);
2848 else if (ctx->options->key.vs.as_es)
2849 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
2850 else
2851 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
2852 &ctx->shader_info->vs.outinfo);
2853 break;
2854 case MESA_SHADER_FRAGMENT:
2855 handle_fs_outputs_post(ctx);
2856 break;
2857 case MESA_SHADER_GEOMETRY:
2858 emit_gs_epilogue(ctx);
2859 break;
2860 case MESA_SHADER_TESS_CTRL:
2861 handle_tcs_outputs_post(ctx);
2862 break;
2863 case MESA_SHADER_TESS_EVAL:
2864 if (ctx->options->key.tes.as_es)
2865 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
2866 else
2867 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
2868 &ctx->shader_info->tes.outinfo);
2869 break;
2870 default:
2871 break;
2872 }
2873 }
2874
2875 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
2876 {
2877 LLVMPassManagerRef passmgr;
2878 /* Create the pass manager */
2879 passmgr = LLVMCreateFunctionPassManagerForModule(
2880 ctx->ac.module);
2881
2882 /* This pass should eliminate all the load and store instructions */
2883 LLVMAddPromoteMemoryToRegisterPass(passmgr);
2884
2885 /* Add some optimization passes */
2886 LLVMAddScalarReplAggregatesPass(passmgr);
2887 LLVMAddLICMPass(passmgr);
2888 LLVMAddAggressiveDCEPass(passmgr);
2889 LLVMAddCFGSimplificationPass(passmgr);
2890 LLVMAddInstructionCombiningPass(passmgr);
2891
2892 /* Run the pass */
2893 LLVMInitializeFunctionPassManager(passmgr);
2894 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
2895 LLVMFinalizeFunctionPassManager(passmgr);
2896
2897 LLVMDisposeBuilder(ctx->ac.builder);
2898 LLVMDisposePassManager(passmgr);
2899
2900 ac_llvm_context_dispose(&ctx->ac);
2901 }
2902
2903 static void
2904 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
2905 {
2906 struct radv_vs_output_info *outinfo;
2907
2908 switch (ctx->stage) {
2909 case MESA_SHADER_FRAGMENT:
2910 case MESA_SHADER_COMPUTE:
2911 case MESA_SHADER_TESS_CTRL:
2912 case MESA_SHADER_GEOMETRY:
2913 return;
2914 case MESA_SHADER_VERTEX:
2915 if (ctx->options->key.vs.as_ls ||
2916 ctx->options->key.vs.as_es)
2917 return;
2918 outinfo = &ctx->shader_info->vs.outinfo;
2919 break;
2920 case MESA_SHADER_TESS_EVAL:
2921 if (ctx->options->key.vs.as_es)
2922 return;
2923 outinfo = &ctx->shader_info->tes.outinfo;
2924 break;
2925 default:
2926 unreachable("Unhandled shader type");
2927 }
2928
2929 ac_optimize_vs_outputs(&ctx->ac,
2930 ctx->main_function,
2931 outinfo->vs_output_param_offset,
2932 VARYING_SLOT_MAX,
2933 &outinfo->param_exports);
2934 }
2935
2936 static void
2937 ac_setup_rings(struct radv_shader_context *ctx)
2938 {
2939 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
2940 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
2941 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
2942 }
2943
2944 if (ctx->is_gs_copy_shader) {
2945 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
2946 }
2947 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2948 LLVMValueRef tmp;
2949 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
2950 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
2951
2952 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
2953
2954 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
2955 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
2956 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
2957 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
2958 }
2959
2960 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
2961 ctx->stage == MESA_SHADER_TESS_EVAL) {
2962 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
2963 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
2964 }
2965 }
2966
2967 static unsigned
2968 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
2969 const struct nir_shader *nir)
2970 {
2971 switch (nir->info.stage) {
2972 case MESA_SHADER_TESS_CTRL:
2973 return chip_class >= CIK ? 128 : 64;
2974 case MESA_SHADER_GEOMETRY:
2975 return chip_class >= GFX9 ? 128 : 64;
2976 case MESA_SHADER_COMPUTE:
2977 break;
2978 default:
2979 return 0;
2980 }
2981
2982 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
2983 nir->info.cs.local_size[1] *
2984 nir->info.cs.local_size[2];
2985 return max_workgroup_size;
2986 }
2987
2988 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
2989 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
2990 {
2991 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2992 LLVMConstInt(ctx->ac.i32, 8, false),
2993 LLVMConstInt(ctx->ac.i32, 8, false), false);
2994 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
2995 ctx->ac.i32_0, "");
2996 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
2997 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
2998 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
2999 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3000 }
3001
3002 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3003 {
3004 for(int i = 5; i >= 0; --i) {
3005 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3006 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
3007 LLVMConstInt(ctx->ac.i32, 16, false), false);
3008 }
3009
3010 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3011 LLVMConstInt(ctx->ac.i32, 16, false),
3012 LLVMConstInt(ctx->ac.i32, 8, false), false);
3013 }
3014
3015
3016 static
3017 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
3018 struct nir_shader *const *shaders,
3019 int shader_count,
3020 struct radv_shader_variant_info *shader_info,
3021 const struct radv_nir_compiler_options *options)
3022 {
3023 struct radv_shader_context ctx = {0};
3024 unsigned i;
3025 ctx.options = options;
3026 ctx.shader_info = shader_info;
3027 ctx.context = LLVMContextCreate();
3028
3029 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3030 options->family);
3031 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3032 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
3033
3034 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
3035 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
3036 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
3037 LLVMDisposeTargetData(data_layout);
3038 LLVMDisposeMessage(data_layout_str);
3039
3040 enum ac_float_mode float_mode =
3041 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3042 AC_FLOAT_MODE_DEFAULT;
3043
3044 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3045
3046 memset(shader_info, 0, sizeof(*shader_info));
3047
3048 for(int i = 0; i < shader_count; ++i)
3049 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3050
3051 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3052 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3053 for (i = 0; i < AC_UD_MAX_UD; i++)
3054 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3055
3056 ctx.max_workgroup_size = 0;
3057 for (int i = 0; i < shader_count; ++i) {
3058 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3059 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3060 shaders[i]));
3061 }
3062
3063 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3064 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3065
3066 ctx.abi.inputs = &ctx.inputs[0];
3067 ctx.abi.emit_outputs = handle_shader_outputs_post;
3068 ctx.abi.emit_vertex = visit_emit_vertex;
3069 ctx.abi.load_ubo = radv_load_ubo;
3070 ctx.abi.load_ssbo = radv_load_ssbo;
3071 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3072 ctx.abi.load_resource = radv_load_resource;
3073 ctx.abi.clamp_shadow_reference = false;
3074
3075 if (shader_count >= 2)
3076 ac_init_exec_full_mask(&ctx.ac);
3077
3078 if (ctx.ac.chip_class == GFX9 &&
3079 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3080 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3081
3082 for(int i = 0; i < shader_count; ++i) {
3083 ctx.stage = shaders[i]->info.stage;
3084 ctx.output_mask = 0;
3085 ctx.tess_outputs_written = 0;
3086 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3087 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3088
3089 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3090 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3091 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3092 ctx.abi.load_inputs = load_gs_input;
3093 ctx.abi.emit_primitive = visit_end_primitive;
3094 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3095 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3096 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3097 ctx.abi.load_tess_varyings = load_tcs_varyings;
3098 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3099 ctx.abi.store_tcs_outputs = store_tcs_output;
3100 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3101 if (shader_count == 1)
3102 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3103 else
3104 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3105 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3106 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3107 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3108 ctx.abi.load_tess_varyings = load_tes_input;
3109 ctx.abi.load_tess_coord = load_tess_coord;
3110 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3111 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3112 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3113 if (shader_info->info.vs.needs_instance_id) {
3114 if (ctx.options->key.vs.as_ls) {
3115 ctx.shader_info->vs.vgpr_comp_cnt =
3116 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3117 } else {
3118 ctx.shader_info->vs.vgpr_comp_cnt =
3119 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3120 }
3121 }
3122 ctx.abi.load_base_vertex = radv_load_base_vertex;
3123 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3124 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3125 ctx.abi.lookup_interp_param = lookup_interp_param;
3126 ctx.abi.load_sample_position = load_sample_position;
3127 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3128 ctx.abi.emit_kill = radv_emit_kill;
3129 }
3130
3131 if (i)
3132 ac_emit_barrier(&ctx.ac, ctx.stage);
3133
3134 ac_setup_rings(&ctx);
3135
3136 LLVMBasicBlockRef merge_block;
3137 if (shader_count >= 2) {
3138 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3139 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3140 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3141
3142 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3143 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3144 LLVMConstInt(ctx.ac.i32, 8, false), false);
3145 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3146 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3147 thread_id, count, "");
3148 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3149
3150 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3151 }
3152
3153 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3154 handle_fs_inputs(&ctx, shaders[i]);
3155 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3156 handle_vs_inputs(&ctx, shaders[i]);
3157 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3158 prepare_gs_input_vgprs(&ctx);
3159
3160 nir_foreach_variable(variable, &shaders[i]->outputs)
3161 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3162
3163 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3164
3165 if (shader_count >= 2) {
3166 LLVMBuildBr(ctx.ac.builder, merge_block);
3167 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3168 }
3169
3170 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3171 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3172 shaders[i]->info.cull_distance_array_size > 4;
3173 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3174 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
3175 shaders[i]->info.gs.vertices_out;
3176 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3177 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
3178 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
3179 assert(ctx.tess_outputs_written == ctx.shader_info->info.tcs.outputs_written);
3180 assert(ctx.tess_patch_outputs_written == ctx.shader_info->info.tcs.patch_outputs_written);
3181 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
3182 shader_info->vs.outputs_written = ctx.tess_outputs_written;
3183 assert(ctx.tess_outputs_written == ctx.shader_info->info.vs.ls_outputs_written);
3184 }
3185 }
3186
3187 LLVMBuildRetVoid(ctx.ac.builder);
3188
3189 if (options->dump_preoptir)
3190 ac_dump_module(ctx.ac.module);
3191
3192 ac_llvm_finalize_module(&ctx);
3193
3194 if (shader_count == 1)
3195 ac_nir_eliminate_const_vs_outputs(&ctx);
3196
3197 if (options->dump_shader) {
3198 ctx.shader_info->private_mem_vgprs =
3199 ac_count_scratch_private_memory(ctx.main_function);
3200 }
3201
3202 return ctx.ac.module;
3203 }
3204
3205 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3206 {
3207 unsigned *retval = (unsigned *)context;
3208 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3209 char *description = LLVMGetDiagInfoDescription(di);
3210
3211 if (severity == LLVMDSError) {
3212 *retval = 1;
3213 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3214 description);
3215 }
3216
3217 LLVMDisposeMessage(description);
3218 }
3219
3220 static unsigned ac_llvm_compile(LLVMModuleRef M,
3221 struct ac_shader_binary *binary,
3222 LLVMTargetMachineRef tm)
3223 {
3224 unsigned retval = 0;
3225 char *err;
3226 LLVMContextRef llvm_ctx;
3227 LLVMMemoryBufferRef out_buffer;
3228 unsigned buffer_size;
3229 const char *buffer_data;
3230 LLVMBool mem_err;
3231
3232 /* Setup Diagnostic Handler*/
3233 llvm_ctx = LLVMGetModuleContext(M);
3234
3235 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3236 &retval);
3237
3238 /* Compile IR*/
3239 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
3240 &err, &out_buffer);
3241
3242 /* Process Errors/Warnings */
3243 if (mem_err) {
3244 fprintf(stderr, "%s: %s", __FUNCTION__, err);
3245 free(err);
3246 retval = 1;
3247 goto out;
3248 }
3249
3250 /* Extract Shader Code*/
3251 buffer_size = LLVMGetBufferSize(out_buffer);
3252 buffer_data = LLVMGetBufferStart(out_buffer);
3253
3254 ac_elf_read(buffer_data, buffer_size, binary);
3255
3256 /* Clean up */
3257 LLVMDisposeMemoryBuffer(out_buffer);
3258
3259 out:
3260 return retval;
3261 }
3262
3263 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
3264 LLVMModuleRef llvm_module,
3265 struct ac_shader_binary *binary,
3266 struct ac_shader_config *config,
3267 struct radv_shader_variant_info *shader_info,
3268 gl_shader_stage stage,
3269 const struct radv_nir_compiler_options *options)
3270 {
3271 if (options->dump_shader)
3272 ac_dump_module(llvm_module);
3273
3274 memset(binary, 0, sizeof(*binary));
3275
3276 if (options->record_llvm_ir) {
3277 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3278 binary->llvm_ir_string = strdup(llvm_ir);
3279 LLVMDisposeMessage(llvm_ir);
3280 }
3281
3282 int v = ac_llvm_compile(llvm_module, binary, tm);
3283 if (v) {
3284 fprintf(stderr, "compile failed\n");
3285 }
3286
3287 if (options->dump_shader)
3288 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3289
3290 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3291
3292 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3293 LLVMDisposeModule(llvm_module);
3294 LLVMContextDispose(ctx);
3295
3296 if (stage == MESA_SHADER_FRAGMENT) {
3297 shader_info->num_input_vgprs = 0;
3298 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3299 shader_info->num_input_vgprs += 2;
3300 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3301 shader_info->num_input_vgprs += 2;
3302 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3303 shader_info->num_input_vgprs += 2;
3304 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3305 shader_info->num_input_vgprs += 3;
3306 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3307 shader_info->num_input_vgprs += 2;
3308 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3309 shader_info->num_input_vgprs += 2;
3310 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3311 shader_info->num_input_vgprs += 2;
3312 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3313 shader_info->num_input_vgprs += 1;
3314 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3315 shader_info->num_input_vgprs += 1;
3316 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3317 shader_info->num_input_vgprs += 1;
3318 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3319 shader_info->num_input_vgprs += 1;
3320 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3321 shader_info->num_input_vgprs += 1;
3322 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3323 shader_info->num_input_vgprs += 1;
3324 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3325 shader_info->num_input_vgprs += 1;
3326 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3327 shader_info->num_input_vgprs += 1;
3328 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3329 shader_info->num_input_vgprs += 1;
3330 }
3331 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3332
3333 /* +3 for scratch wave offset and VCC */
3334 config->num_sgprs = MAX2(config->num_sgprs,
3335 shader_info->num_input_sgprs + 3);
3336
3337 /* Enable 64-bit and 16-bit denormals, because there is no performance
3338 * cost.
3339 *
3340 * If denormals are enabled, all floating-point output modifiers are
3341 * ignored.
3342 *
3343 * Don't enable denormals for 32-bit floats, because:
3344 * - Floating-point output modifiers would be ignored by the hw.
3345 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3346 * have to stop using those.
3347 * - SI & CI would be very slow.
3348 */
3349 config->float_mode |= V_00B028_FP_64_DENORMS;
3350 }
3351
3352 static void
3353 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3354 {
3355 switch (nir->info.stage) {
3356 case MESA_SHADER_COMPUTE:
3357 for (int i = 0; i < 3; ++i)
3358 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3359 break;
3360 case MESA_SHADER_FRAGMENT:
3361 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3362 break;
3363 case MESA_SHADER_GEOMETRY:
3364 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3365 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3366 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3367 shader_info->gs.invocations = nir->info.gs.invocations;
3368 break;
3369 case MESA_SHADER_TESS_EVAL:
3370 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3371 shader_info->tes.spacing = nir->info.tess.spacing;
3372 shader_info->tes.ccw = nir->info.tess.ccw;
3373 shader_info->tes.point_mode = nir->info.tess.point_mode;
3374 shader_info->tes.as_es = options->key.tes.as_es;
3375 break;
3376 case MESA_SHADER_TESS_CTRL:
3377 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3378 break;
3379 case MESA_SHADER_VERTEX:
3380 shader_info->vs.as_es = options->key.vs.as_es;
3381 shader_info->vs.as_ls = options->key.vs.as_ls;
3382 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3383 if (options->key.vs.as_ls)
3384 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3385 break;
3386 default:
3387 break;
3388 }
3389 }
3390
3391 void
3392 radv_compile_nir_shader(LLVMTargetMachineRef tm,
3393 struct ac_shader_binary *binary,
3394 struct ac_shader_config *config,
3395 struct radv_shader_variant_info *shader_info,
3396 struct nir_shader *const *nir,
3397 int nir_count,
3398 const struct radv_nir_compiler_options *options)
3399 {
3400
3401 LLVMModuleRef llvm_module;
3402
3403 llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
3404 options);
3405
3406 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
3407 nir[0]->info.stage, options);
3408
3409 for (int i = 0; i < nir_count; ++i)
3410 ac_fill_shader_info(shader_info, nir[i], options);
3411
3412 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3413 if (options->chip_class == GFX9) {
3414 if (nir_count == 2 &&
3415 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3416 shader_info->gs.es_type = nir[0]->info.stage;
3417 }
3418 }
3419 }
3420
3421 static void
3422 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3423 {
3424 LLVMValueRef vtx_offset =
3425 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3426 LLVMConstInt(ctx->ac.i32, 4, false), "");
3427 int idx = 0;
3428
3429 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3430 int length = 4;
3431 int slot = idx;
3432 int slot_inc = 1;
3433 if (!(ctx->output_mask & (1ull << i)))
3434 continue;
3435
3436 if (i == VARYING_SLOT_CLIP_DIST0) {
3437 /* unpack clip and cull from a single set of slots */
3438 length = ctx->num_output_clips + ctx->num_output_culls;
3439 if (length > 4)
3440 slot_inc = 2;
3441 }
3442
3443 for (unsigned j = 0; j < length; j++) {
3444 LLVMValueRef value, soffset;
3445
3446 soffset = LLVMConstInt(ctx->ac.i32,
3447 (slot * 4 + j) *
3448 ctx->gs_max_out_vertices * 16 * 4, false);
3449
3450 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3451 1, ctx->ac.i32_0,
3452 vtx_offset, soffset,
3453 0, 1, 1, true, false);
3454
3455 LLVMBuildStore(ctx->ac.builder,
3456 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3457 }
3458 idx += slot_inc;
3459 }
3460 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
3461 }
3462
3463 void
3464 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
3465 struct nir_shader *geom_shader,
3466 struct ac_shader_binary *binary,
3467 struct ac_shader_config *config,
3468 struct radv_shader_variant_info *shader_info,
3469 const struct radv_nir_compiler_options *options)
3470 {
3471 struct radv_shader_context ctx = {0};
3472 ctx.context = LLVMContextCreate();
3473 ctx.options = options;
3474 ctx.shader_info = shader_info;
3475
3476 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3477 options->family);
3478 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3479
3480 ctx.is_gs_copy_shader = true;
3481 LLVMSetTarget(ctx.ac.module, "amdgcn--");
3482
3483 enum ac_float_mode float_mode =
3484 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3485 AC_FLOAT_MODE_DEFAULT;
3486
3487 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3488 ctx.stage = MESA_SHADER_VERTEX;
3489
3490 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3491
3492 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3493 ac_setup_rings(&ctx);
3494
3495 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3496 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3497
3498 nir_foreach_variable(variable, &geom_shader->outputs) {
3499 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3500 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3501 variable, MESA_SHADER_VERTEX);
3502 }
3503
3504 ac_gs_copy_shader_emit(&ctx);
3505
3506 LLVMBuildRetVoid(ctx.ac.builder);
3507
3508 ac_llvm_finalize_module(&ctx);
3509
3510 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
3511 MESA_SHADER_VERTEX, options);
3512 }