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radv: only declare the ESGS rings for pre GFX9 chips
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "nir/nir.h"
31
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35 #if HAVE_LLVM >= 0x0700
36 #include <llvm-c/Transforms/Utils.h>
37 #endif
38
39 #include "sid.h"
40 #include "gfx9d.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_llvm_build.h"
44 #include "ac_shader_abi.h"
45 #include "ac_shader_util.h"
46 #include "ac_exp_param.h"
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct radv_shader_context {
51 struct ac_llvm_context ac;
52 const struct radv_nir_compiler_options *options;
53 struct radv_shader_variant_info *shader_info;
54 struct ac_shader_abi abi;
55
56 unsigned max_workgroup_size;
57 LLVMContextRef context;
58 LLVMValueRef main_function;
59
60 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
61 LLVMValueRef ring_offsets;
62
63 LLVMValueRef vertex_buffers;
64 LLVMValueRef rel_auto_id;
65 LLVMValueRef vs_prim_id;
66 LLVMValueRef es2gs_offset;
67
68 LLVMValueRef oc_lds;
69 LLVMValueRef merged_wave_info;
70 LLVMValueRef tess_factor_offset;
71 LLVMValueRef tes_rel_patch_id;
72 LLVMValueRef tes_u;
73 LLVMValueRef tes_v;
74
75 LLVMValueRef gs2vs_offset;
76 LLVMValueRef gs_wave_id;
77 LLVMValueRef gs_vtx_offset[6];
78
79 LLVMValueRef esgs_ring;
80 LLVMValueRef gsvs_ring;
81 LLVMValueRef hs_ring_tess_offchip;
82 LLVMValueRef hs_ring_tess_factor;
83
84 LLVMValueRef sample_pos_offset;
85 LLVMValueRef persp_sample, persp_center, persp_centroid;
86 LLVMValueRef linear_sample, linear_center, linear_centroid;
87
88 gl_shader_stage stage;
89
90 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
91
92 uint64_t input_mask;
93 uint64_t output_mask;
94 uint8_t num_output_clips;
95 uint8_t num_output_culls;
96
97 bool is_gs_copy_shader;
98 LLVMValueRef gs_next_vertex;
99 unsigned gs_max_out_vertices;
100
101 unsigned tes_primitive_mode;
102
103 uint32_t tcs_patch_outputs_read;
104 uint64_t tcs_outputs_read;
105 uint32_t tcs_vertices_per_patch;
106 uint32_t tcs_num_inputs;
107 uint32_t tcs_num_patches;
108 uint32_t max_gsvs_emit_size;
109 uint32_t gsvs_vertex_size;
110 };
111
112 enum radeon_llvm_calling_convention {
113 RADEON_LLVM_AMDGPU_VS = 87,
114 RADEON_LLVM_AMDGPU_GS = 88,
115 RADEON_LLVM_AMDGPU_PS = 89,
116 RADEON_LLVM_AMDGPU_CS = 90,
117 RADEON_LLVM_AMDGPU_HS = 93,
118 };
119
120 static inline struct radv_shader_context *
121 radv_shader_context_from_abi(struct ac_shader_abi *abi)
122 {
123 struct radv_shader_context *ctx = NULL;
124 return container_of(abi, ctx, abi);
125 }
126
127 struct ac_build_if_state
128 {
129 struct radv_shader_context *ctx;
130 LLVMValueRef condition;
131 LLVMBasicBlockRef entry_block;
132 LLVMBasicBlockRef true_block;
133 LLVMBasicBlockRef false_block;
134 LLVMBasicBlockRef merge_block;
135 };
136
137 static LLVMBasicBlockRef
138 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
139 {
140 LLVMBasicBlockRef current_block;
141 LLVMBasicBlockRef next_block;
142 LLVMBasicBlockRef new_block;
143
144 /* get current basic block */
145 current_block = LLVMGetInsertBlock(ctx->ac.builder);
146
147 /* chqeck if there's another block after this one */
148 next_block = LLVMGetNextBasicBlock(current_block);
149 if (next_block) {
150 /* insert the new block before the next block */
151 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
152 }
153 else {
154 /* append new block after current block */
155 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
156 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
157 }
158 return new_block;
159 }
160
161 static void
162 ac_nir_build_if(struct ac_build_if_state *ifthen,
163 struct radv_shader_context *ctx,
164 LLVMValueRef condition)
165 {
166 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
167
168 memset(ifthen, 0, sizeof *ifthen);
169 ifthen->ctx = ctx;
170 ifthen->condition = condition;
171 ifthen->entry_block = block;
172
173 /* create endif/merge basic block for the phi functions */
174 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
175
176 /* create/insert true_block before merge_block */
177 ifthen->true_block =
178 LLVMInsertBasicBlockInContext(ctx->context,
179 ifthen->merge_block,
180 "if-true-block");
181
182 /* successive code goes into the true block */
183 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
184 }
185
186 /**
187 * End a conditional.
188 */
189 static void
190 ac_nir_build_endif(struct ac_build_if_state *ifthen)
191 {
192 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
193
194 /* Insert branch to the merge block from current block */
195 LLVMBuildBr(builder, ifthen->merge_block);
196
197 /*
198 * Now patch in the various branch instructions.
199 */
200
201 /* Insert the conditional branch instruction at the end of entry_block */
202 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
203 if (ifthen->false_block) {
204 /* we have an else clause */
205 LLVMBuildCondBr(builder, ifthen->condition,
206 ifthen->true_block, ifthen->false_block);
207 }
208 else {
209 /* no else clause */
210 LLVMBuildCondBr(builder, ifthen->condition,
211 ifthen->true_block, ifthen->merge_block);
212 }
213
214 /* Resume building code at end of the ifthen->merge_block */
215 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
216 }
217
218
219 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
220 {
221 switch (ctx->stage) {
222 case MESA_SHADER_TESS_CTRL:
223 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
224 case MESA_SHADER_TESS_EVAL:
225 return ctx->tes_rel_patch_id;
226 break;
227 default:
228 unreachable("Illegal stage");
229 }
230 }
231
232 static unsigned
233 get_tcs_num_patches(struct radv_shader_context *ctx)
234 {
235 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
236 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
237 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
238 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
239 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
240 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
241 uint32_t output_vertex_size = num_tcs_outputs * 16;
242 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
243 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
244 unsigned num_patches;
245 unsigned hardware_lds_size;
246
247 /* Ensure that we only need one wave per SIMD so we don't need to check
248 * resource usage. Also ensures that the number of tcs in and out
249 * vertices per threadgroup are at most 256.
250 */
251 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
252 /* Make sure that the data fits in LDS. This assumes the shaders only
253 * use LDS for the inputs and outputs.
254 */
255 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
256 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
257 /* Make sure the output data fits in the offchip buffer */
258 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
259 /* Not necessary for correctness, but improves performance. The
260 * specific value is taken from the proprietary driver.
261 */
262 num_patches = MIN2(num_patches, 40);
263
264 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
265 if (ctx->options->chip_class == SI) {
266 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
267 num_patches = MIN2(num_patches, one_wave);
268 }
269 return num_patches;
270 }
271
272 static unsigned
273 calculate_tess_lds_size(struct radv_shader_context *ctx)
274 {
275 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
276 unsigned num_tcs_output_cp;
277 unsigned num_tcs_outputs, num_tcs_patch_outputs;
278 unsigned input_vertex_size, output_vertex_size;
279 unsigned input_patch_size, output_patch_size;
280 unsigned pervertex_output_patch_size;
281 unsigned output_patch0_offset;
282 unsigned num_patches;
283 unsigned lds_size;
284
285 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
286 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
287 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
288
289 input_vertex_size = ctx->tcs_num_inputs * 16;
290 output_vertex_size = num_tcs_outputs * 16;
291
292 input_patch_size = num_tcs_input_cp * input_vertex_size;
293
294 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
295 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
296
297 num_patches = ctx->tcs_num_patches;
298 output_patch0_offset = input_patch_size * num_patches;
299
300 lds_size = output_patch0_offset + output_patch_size * num_patches;
301 return lds_size;
302 }
303
304 /* Tessellation shaders pass outputs to the next shader using LDS.
305 *
306 * LS outputs = TCS inputs
307 * TCS outputs = TES inputs
308 *
309 * The LDS layout is:
310 * - TCS inputs for patch 0
311 * - TCS inputs for patch 1
312 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
313 * - ...
314 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
315 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
316 * - TCS outputs for patch 1
317 * - Per-patch TCS outputs for patch 1
318 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
319 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
320 * - ...
321 *
322 * All three shaders VS(LS), TCS, TES share the same LDS space.
323 */
324 static LLVMValueRef
325 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
326 {
327 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
328 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
329 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
330
331 input_patch_size /= 4;
332 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
333 }
334
335 static LLVMValueRef
336 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
337 {
338 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
339 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
340 uint32_t output_vertex_size = num_tcs_outputs * 16;
341 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
342 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
343 output_patch_size /= 4;
344 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
345 }
346
347 static LLVMValueRef
348 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
349 {
350 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
351 uint32_t output_vertex_size = num_tcs_outputs * 16;
352 output_vertex_size /= 4;
353 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
354 }
355
356 static LLVMValueRef
357 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
358 {
359 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
360 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
361 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
362 uint32_t output_patch0_offset = input_patch_size;
363 unsigned num_patches = ctx->tcs_num_patches;
364
365 output_patch0_offset *= num_patches;
366 output_patch0_offset /= 4;
367 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
368 }
369
370 static LLVMValueRef
371 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
372 {
373 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
374 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
375 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
376 uint32_t output_patch0_offset = input_patch_size;
377
378 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
379 uint32_t output_vertex_size = num_tcs_outputs * 16;
380 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
381 unsigned num_patches = ctx->tcs_num_patches;
382
383 output_patch0_offset *= num_patches;
384 output_patch0_offset += pervertex_output_patch_size;
385 output_patch0_offset /= 4;
386 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
387 }
388
389 static LLVMValueRef
390 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
391 {
392 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
393 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
394
395 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
396 }
397
398 static LLVMValueRef
399 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
400 {
401 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
402 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
403 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
404
405 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
406 LLVMBuildMul(ctx->ac.builder, patch_stride,
407 rel_patch_id, ""),
408 "");
409 }
410
411 static LLVMValueRef
412 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
413 {
414 LLVMValueRef patch0_patch_data_offset =
415 get_tcs_out_patch0_patch_data_offset(ctx);
416 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
417 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
418
419 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
420 LLVMBuildMul(ctx->ac.builder, patch_stride,
421 rel_patch_id, ""),
422 "");
423 }
424
425 #define MAX_ARGS 23
426 struct arg_info {
427 LLVMTypeRef types[MAX_ARGS];
428 LLVMValueRef *assign[MAX_ARGS];
429 unsigned array_params_mask;
430 uint8_t count;
431 uint8_t sgpr_count;
432 uint8_t num_sgprs_used;
433 uint8_t num_vgprs_used;
434 };
435
436 enum ac_arg_regfile {
437 ARG_SGPR,
438 ARG_VGPR,
439 };
440
441 static void
442 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
443 LLVMValueRef *param_ptr)
444 {
445 assert(info->count < MAX_ARGS);
446
447 info->assign[info->count] = param_ptr;
448 info->types[info->count] = type;
449 info->count++;
450
451 if (regfile == ARG_SGPR) {
452 info->num_sgprs_used += ac_get_type_size(type) / 4;
453 info->sgpr_count++;
454 } else {
455 assert(regfile == ARG_VGPR);
456 info->num_vgprs_used += ac_get_type_size(type) / 4;
457 }
458 }
459
460 static inline void
461 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
462 {
463 info->array_params_mask |= (1 << info->count);
464 add_arg(info, ARG_SGPR, type, param_ptr);
465 }
466
467 static void assign_arguments(LLVMValueRef main_function,
468 struct arg_info *info)
469 {
470 unsigned i;
471 for (i = 0; i < info->count; i++) {
472 if (info->assign[i])
473 *info->assign[i] = LLVMGetParam(main_function, i);
474 }
475 }
476
477 static LLVMValueRef
478 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
479 LLVMBuilderRef builder, LLVMTypeRef *return_types,
480 unsigned num_return_elems,
481 struct arg_info *args,
482 unsigned max_workgroup_size,
483 bool unsafe_math)
484 {
485 LLVMTypeRef main_function_type, ret_type;
486 LLVMBasicBlockRef main_function_body;
487
488 if (num_return_elems)
489 ret_type = LLVMStructTypeInContext(ctx, return_types,
490 num_return_elems, true);
491 else
492 ret_type = LLVMVoidTypeInContext(ctx);
493
494 /* Setup the function */
495 main_function_type =
496 LLVMFunctionType(ret_type, args->types, args->count, 0);
497 LLVMValueRef main_function =
498 LLVMAddFunction(module, "main", main_function_type);
499 main_function_body =
500 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
501 LLVMPositionBuilderAtEnd(builder, main_function_body);
502
503 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
504 for (unsigned i = 0; i < args->sgpr_count; ++i) {
505 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
506
507 if (args->array_params_mask & (1 << i)) {
508 LLVMValueRef P = LLVMGetParam(main_function, i);
509 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
510 ac_add_attr_dereferenceable(P, UINT64_MAX);
511 }
512 }
513
514 if (max_workgroup_size) {
515 ac_llvm_add_target_dep_function_attr(main_function,
516 "amdgpu-max-work-group-size",
517 max_workgroup_size);
518 }
519 if (unsafe_math) {
520 /* These were copied from some LLVM test. */
521 LLVMAddTargetDependentFunctionAttr(main_function,
522 "less-precise-fpmad",
523 "true");
524 LLVMAddTargetDependentFunctionAttr(main_function,
525 "no-infs-fp-math",
526 "true");
527 LLVMAddTargetDependentFunctionAttr(main_function,
528 "no-nans-fp-math",
529 "true");
530 LLVMAddTargetDependentFunctionAttr(main_function,
531 "unsafe-fp-math",
532 "true");
533 LLVMAddTargetDependentFunctionAttr(main_function,
534 "no-signed-zeros-fp-math",
535 "true");
536 }
537 return main_function;
538 }
539
540
541 static void
542 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
543 uint32_t indirect_offset)
544 {
545 ud_info->sgpr_idx = *sgpr_idx;
546 ud_info->num_sgprs = num_sgprs;
547 ud_info->indirect = indirect_offset > 0;
548 ud_info->indirect_offset = indirect_offset;
549 *sgpr_idx += num_sgprs;
550 }
551
552 static void
553 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
554 uint8_t num_sgprs)
555 {
556 struct radv_userdata_info *ud_info =
557 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
558 assert(ud_info);
559
560 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
561 }
562
563 static void
564 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
565 uint32_t indirect_offset)
566 {
567 struct radv_userdata_info *ud_info =
568 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
569 assert(ud_info);
570
571 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
572 }
573
574 struct user_sgpr_info {
575 bool need_ring_offsets;
576 uint8_t sgpr_count;
577 bool indirect_all_descriptor_sets;
578 };
579
580 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
581 gl_shader_stage stage)
582 {
583 switch (stage) {
584 case MESA_SHADER_VERTEX:
585 if (ctx->shader_info->info.needs_multiview_view_index ||
586 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
587 return true;
588 break;
589 case MESA_SHADER_TESS_EVAL:
590 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
591 return true;
592 break;
593 case MESA_SHADER_GEOMETRY:
594 case MESA_SHADER_TESS_CTRL:
595 if (ctx->shader_info->info.needs_multiview_view_index)
596 return true;
597 break;
598 default:
599 break;
600 }
601 return false;
602 }
603
604 static uint8_t
605 count_vs_user_sgprs(struct radv_shader_context *ctx)
606 {
607 uint8_t count = 0;
608
609 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
610 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
611
612 return count;
613 }
614
615 static void allocate_user_sgprs(struct radv_shader_context *ctx,
616 gl_shader_stage stage,
617 bool has_previous_stage,
618 gl_shader_stage previous_stage,
619 bool needs_view_index,
620 struct user_sgpr_info *user_sgpr_info)
621 {
622 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
623
624 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
625 if (stage == MESA_SHADER_GEOMETRY ||
626 stage == MESA_SHADER_VERTEX ||
627 stage == MESA_SHADER_TESS_CTRL ||
628 stage == MESA_SHADER_TESS_EVAL ||
629 ctx->is_gs_copy_shader)
630 user_sgpr_info->need_ring_offsets = true;
631
632 if (stage == MESA_SHADER_FRAGMENT &&
633 ctx->shader_info->info.ps.needs_sample_positions)
634 user_sgpr_info->need_ring_offsets = true;
635
636 /* 2 user sgprs will nearly always be allocated for scratch/rings */
637 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
638 user_sgpr_info->sgpr_count += 2;
639 }
640
641 switch (stage) {
642 case MESA_SHADER_COMPUTE:
643 if (ctx->shader_info->info.cs.uses_grid_size)
644 user_sgpr_info->sgpr_count += 3;
645 break;
646 case MESA_SHADER_FRAGMENT:
647 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
648 break;
649 case MESA_SHADER_VERTEX:
650 if (!ctx->is_gs_copy_shader)
651 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
652 break;
653 case MESA_SHADER_TESS_CTRL:
654 if (has_previous_stage) {
655 if (previous_stage == MESA_SHADER_VERTEX)
656 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
657 }
658 break;
659 case MESA_SHADER_TESS_EVAL:
660 break;
661 case MESA_SHADER_GEOMETRY:
662 if (has_previous_stage) {
663 if (previous_stage == MESA_SHADER_VERTEX) {
664 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
665 }
666 }
667 break;
668 default:
669 break;
670 }
671
672 if (needs_view_index)
673 user_sgpr_info->sgpr_count++;
674
675 if (ctx->shader_info->info.loads_push_constants)
676 user_sgpr_info->sgpr_count += 2;
677
678 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
679 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
680
681 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
682 user_sgpr_info->sgpr_count += 2;
683 user_sgpr_info->indirect_all_descriptor_sets = true;
684 } else {
685 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
686 }
687 }
688
689 static void
690 declare_global_input_sgprs(struct radv_shader_context *ctx,
691 gl_shader_stage stage,
692 bool has_previous_stage,
693 gl_shader_stage previous_stage,
694 const struct user_sgpr_info *user_sgpr_info,
695 struct arg_info *args,
696 LLVMValueRef *desc_sets)
697 {
698 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
699 unsigned num_sets = ctx->options->layout ?
700 ctx->options->layout->num_sets : 0;
701 unsigned stage_mask = 1 << stage;
702
703 if (has_previous_stage)
704 stage_mask |= 1 << previous_stage;
705
706 /* 1 for each descriptor set */
707 if (!user_sgpr_info->indirect_all_descriptor_sets) {
708 for (unsigned i = 0; i < num_sets; ++i) {
709 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
710 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
711 add_array_arg(args, type,
712 &ctx->descriptor_sets[i]);
713 }
714 }
715 } else {
716 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
717 }
718
719 if (ctx->shader_info->info.loads_push_constants) {
720 /* 1 for push constants and dynamic descriptors */
721 add_array_arg(args, type, &ctx->abi.push_constants);
722 }
723 }
724
725 static void
726 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
727 gl_shader_stage stage,
728 bool has_previous_stage,
729 gl_shader_stage previous_stage,
730 struct arg_info *args)
731 {
732 if (!ctx->is_gs_copy_shader &&
733 (stage == MESA_SHADER_VERTEX ||
734 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
735 if (ctx->shader_info->info.vs.has_vertex_buffers) {
736 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
737 &ctx->vertex_buffers);
738 }
739 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
740 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
741 if (ctx->shader_info->info.vs.needs_draw_id) {
742 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
743 }
744 }
745 }
746
747 static void
748 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
749 {
750 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
751 if (!ctx->is_gs_copy_shader) {
752 if (ctx->options->key.vs.as_ls) {
753 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
754 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
755 } else {
756 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
757 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
758 }
759 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
760 }
761 }
762
763 static void
764 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
765 {
766 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
767 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
768 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
769 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
770 }
771
772 static void
773 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
774 bool has_previous_stage, gl_shader_stage previous_stage,
775 const struct user_sgpr_info *user_sgpr_info,
776 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
777 {
778 unsigned num_sets = ctx->options->layout ?
779 ctx->options->layout->num_sets : 0;
780 unsigned stage_mask = 1 << stage;
781
782 if (has_previous_stage)
783 stage_mask |= 1 << previous_stage;
784
785 if (!user_sgpr_info->indirect_all_descriptor_sets) {
786 for (unsigned i = 0; i < num_sets; ++i) {
787 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
788 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
789 set_loc_desc(ctx, i, user_sgpr_idx, 0);
790 } else
791 ctx->descriptor_sets[i] = NULL;
792 }
793 } else {
794 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
795 user_sgpr_idx, 2);
796
797 for (unsigned i = 0; i < num_sets; ++i) {
798 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
799 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
800 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
801 ctx->descriptor_sets[i] =
802 ac_build_load_to_sgpr(&ctx->ac,
803 desc_sets,
804 LLVMConstInt(ctx->ac.i32, i, false));
805
806 } else
807 ctx->descriptor_sets[i] = NULL;
808 }
809 ctx->shader_info->need_indirect_descriptor_sets = true;
810 }
811
812 if (ctx->shader_info->info.loads_push_constants) {
813 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
814 }
815 }
816
817 static void
818 set_vs_specific_input_locs(struct radv_shader_context *ctx,
819 gl_shader_stage stage, bool has_previous_stage,
820 gl_shader_stage previous_stage,
821 uint8_t *user_sgpr_idx)
822 {
823 if (!ctx->is_gs_copy_shader &&
824 (stage == MESA_SHADER_VERTEX ||
825 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
826 if (ctx->shader_info->info.vs.has_vertex_buffers) {
827 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
828 user_sgpr_idx, 2);
829 }
830
831 unsigned vs_num = 2;
832 if (ctx->shader_info->info.vs.needs_draw_id)
833 vs_num++;
834
835 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
836 user_sgpr_idx, vs_num);
837 }
838 }
839
840 static void set_llvm_calling_convention(LLVMValueRef func,
841 gl_shader_stage stage)
842 {
843 enum radeon_llvm_calling_convention calling_conv;
844
845 switch (stage) {
846 case MESA_SHADER_VERTEX:
847 case MESA_SHADER_TESS_EVAL:
848 calling_conv = RADEON_LLVM_AMDGPU_VS;
849 break;
850 case MESA_SHADER_GEOMETRY:
851 calling_conv = RADEON_LLVM_AMDGPU_GS;
852 break;
853 case MESA_SHADER_TESS_CTRL:
854 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
855 break;
856 case MESA_SHADER_FRAGMENT:
857 calling_conv = RADEON_LLVM_AMDGPU_PS;
858 break;
859 case MESA_SHADER_COMPUTE:
860 calling_conv = RADEON_LLVM_AMDGPU_CS;
861 break;
862 default:
863 unreachable("Unhandle shader type");
864 }
865
866 LLVMSetFunctionCallConv(func, calling_conv);
867 }
868
869 static void create_function(struct radv_shader_context *ctx,
870 gl_shader_stage stage,
871 bool has_previous_stage,
872 gl_shader_stage previous_stage)
873 {
874 uint8_t user_sgpr_idx;
875 struct user_sgpr_info user_sgpr_info;
876 struct arg_info args = {};
877 LLVMValueRef desc_sets;
878 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
879 allocate_user_sgprs(ctx, stage, has_previous_stage,
880 previous_stage, needs_view_index, &user_sgpr_info);
881
882 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
883 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
884 &ctx->ring_offsets);
885 }
886
887 switch (stage) {
888 case MESA_SHADER_COMPUTE:
889 declare_global_input_sgprs(ctx, stage, has_previous_stage,
890 previous_stage, &user_sgpr_info,
891 &args, &desc_sets);
892
893 if (ctx->shader_info->info.cs.uses_grid_size) {
894 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
895 &ctx->abi.num_work_groups);
896 }
897
898 for (int i = 0; i < 3; i++) {
899 ctx->abi.workgroup_ids[i] = NULL;
900 if (ctx->shader_info->info.cs.uses_block_id[i]) {
901 add_arg(&args, ARG_SGPR, ctx->ac.i32,
902 &ctx->abi.workgroup_ids[i]);
903 }
904 }
905
906 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
907 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
908 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
909 &ctx->abi.local_invocation_ids);
910 break;
911 case MESA_SHADER_VERTEX:
912 declare_global_input_sgprs(ctx, stage, has_previous_stage,
913 previous_stage, &user_sgpr_info,
914 &args, &desc_sets);
915 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
916 previous_stage, &args);
917
918 if (needs_view_index)
919 add_arg(&args, ARG_SGPR, ctx->ac.i32,
920 &ctx->abi.view_index);
921 if (ctx->options->key.vs.as_es)
922 add_arg(&args, ARG_SGPR, ctx->ac.i32,
923 &ctx->es2gs_offset);
924
925 declare_vs_input_vgprs(ctx, &args);
926 break;
927 case MESA_SHADER_TESS_CTRL:
928 if (has_previous_stage) {
929 // First 6 system regs
930 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
931 add_arg(&args, ARG_SGPR, ctx->ac.i32,
932 &ctx->merged_wave_info);
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->tess_factor_offset);
935
936 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
937 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
938 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
939
940 declare_global_input_sgprs(ctx, stage,
941 has_previous_stage,
942 previous_stage,
943 &user_sgpr_info, &args,
944 &desc_sets);
945 declare_vs_specific_input_sgprs(ctx, stage,
946 has_previous_stage,
947 previous_stage, &args);
948
949 if (needs_view_index)
950 add_arg(&args, ARG_SGPR, ctx->ac.i32,
951 &ctx->abi.view_index);
952
953 add_arg(&args, ARG_VGPR, ctx->ac.i32,
954 &ctx->abi.tcs_patch_id);
955 add_arg(&args, ARG_VGPR, ctx->ac.i32,
956 &ctx->abi.tcs_rel_ids);
957
958 declare_vs_input_vgprs(ctx, &args);
959 } else {
960 declare_global_input_sgprs(ctx, stage,
961 has_previous_stage,
962 previous_stage,
963 &user_sgpr_info, &args,
964 &desc_sets);
965
966 if (needs_view_index)
967 add_arg(&args, ARG_SGPR, ctx->ac.i32,
968 &ctx->abi.view_index);
969
970 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->tess_factor_offset);
973 add_arg(&args, ARG_VGPR, ctx->ac.i32,
974 &ctx->abi.tcs_patch_id);
975 add_arg(&args, ARG_VGPR, ctx->ac.i32,
976 &ctx->abi.tcs_rel_ids);
977 }
978 break;
979 case MESA_SHADER_TESS_EVAL:
980 declare_global_input_sgprs(ctx, stage, has_previous_stage,
981 previous_stage, &user_sgpr_info,
982 &args, &desc_sets);
983
984 if (needs_view_index)
985 add_arg(&args, ARG_SGPR, ctx->ac.i32,
986 &ctx->abi.view_index);
987
988 if (ctx->options->key.tes.as_es) {
989 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
990 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
991 add_arg(&args, ARG_SGPR, ctx->ac.i32,
992 &ctx->es2gs_offset);
993 } else {
994 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
995 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
996 }
997 declare_tes_input_vgprs(ctx, &args);
998 break;
999 case MESA_SHADER_GEOMETRY:
1000 if (has_previous_stage) {
1001 // First 6 system regs
1002 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1003 &ctx->gs2vs_offset);
1004 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1005 &ctx->merged_wave_info);
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1007
1008 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1009 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1010 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1011
1012 declare_global_input_sgprs(ctx, stage,
1013 has_previous_stage,
1014 previous_stage,
1015 &user_sgpr_info, &args,
1016 &desc_sets);
1017
1018 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1019 declare_vs_specific_input_sgprs(ctx, stage,
1020 has_previous_stage,
1021 previous_stage,
1022 &args);
1023 }
1024
1025 if (needs_view_index)
1026 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1027 &ctx->abi.view_index);
1028
1029 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1030 &ctx->gs_vtx_offset[0]);
1031 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1032 &ctx->gs_vtx_offset[2]);
1033 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1034 &ctx->abi.gs_prim_id);
1035 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1036 &ctx->abi.gs_invocation_id);
1037 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1038 &ctx->gs_vtx_offset[4]);
1039
1040 if (previous_stage == MESA_SHADER_VERTEX) {
1041 declare_vs_input_vgprs(ctx, &args);
1042 } else {
1043 declare_tes_input_vgprs(ctx, &args);
1044 }
1045 } else {
1046 declare_global_input_sgprs(ctx, stage,
1047 has_previous_stage,
1048 previous_stage,
1049 &user_sgpr_info, &args,
1050 &desc_sets);
1051
1052 if (needs_view_index)
1053 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1054 &ctx->abi.view_index);
1055
1056 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1057 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1058 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1059 &ctx->gs_vtx_offset[0]);
1060 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1061 &ctx->gs_vtx_offset[1]);
1062 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1063 &ctx->abi.gs_prim_id);
1064 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1065 &ctx->gs_vtx_offset[2]);
1066 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1067 &ctx->gs_vtx_offset[3]);
1068 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1069 &ctx->gs_vtx_offset[4]);
1070 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1071 &ctx->gs_vtx_offset[5]);
1072 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1073 &ctx->abi.gs_invocation_id);
1074 }
1075 break;
1076 case MESA_SHADER_FRAGMENT:
1077 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1078 previous_stage, &user_sgpr_info,
1079 &args, &desc_sets);
1080
1081 if (ctx->shader_info->info.ps.needs_sample_positions)
1082 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1083 &ctx->sample_pos_offset);
1084
1085 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1086 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1087 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1088 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1089 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1090 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1091 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1092 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1093 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1094 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1095 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1096 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1097 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1098 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1099 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1100 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1101 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1102 break;
1103 default:
1104 unreachable("Shader stage not implemented");
1105 }
1106
1107 ctx->main_function = create_llvm_function(
1108 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1109 ctx->max_workgroup_size,
1110 ctx->options->unsafe_math);
1111 set_llvm_calling_convention(ctx->main_function, stage);
1112
1113
1114 ctx->shader_info->num_input_vgprs = 0;
1115 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1116
1117 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1118
1119 if (ctx->stage != MESA_SHADER_FRAGMENT)
1120 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1121
1122 assign_arguments(ctx->main_function, &args);
1123
1124 user_sgpr_idx = 0;
1125
1126 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1127 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1128 &user_sgpr_idx, 2);
1129 if (ctx->options->supports_spill) {
1130 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1131 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1132 NULL, 0, AC_FUNC_ATTR_READNONE);
1133 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1134 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1135 }
1136 }
1137
1138 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1139 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1140 if (has_previous_stage)
1141 user_sgpr_idx = 0;
1142
1143 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1144 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1145
1146 switch (stage) {
1147 case MESA_SHADER_COMPUTE:
1148 if (ctx->shader_info->info.cs.uses_grid_size) {
1149 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1150 &user_sgpr_idx, 3);
1151 }
1152 break;
1153 case MESA_SHADER_VERTEX:
1154 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1155 previous_stage, &user_sgpr_idx);
1156 if (ctx->abi.view_index)
1157 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1158 break;
1159 case MESA_SHADER_TESS_CTRL:
1160 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1161 previous_stage, &user_sgpr_idx);
1162 if (ctx->abi.view_index)
1163 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1164 break;
1165 case MESA_SHADER_TESS_EVAL:
1166 if (ctx->abi.view_index)
1167 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1168 break;
1169 case MESA_SHADER_GEOMETRY:
1170 if (has_previous_stage) {
1171 if (previous_stage == MESA_SHADER_VERTEX)
1172 set_vs_specific_input_locs(ctx, stage,
1173 has_previous_stage,
1174 previous_stage,
1175 &user_sgpr_idx);
1176 }
1177 if (ctx->abi.view_index)
1178 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1179 break;
1180 case MESA_SHADER_FRAGMENT:
1181 if (ctx->shader_info->info.ps.needs_sample_positions) {
1182 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1183 &user_sgpr_idx, 1);
1184 }
1185 break;
1186 default:
1187 unreachable("Shader stage not implemented");
1188 }
1189
1190 if (stage == MESA_SHADER_TESS_CTRL ||
1191 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1192 /* GFX9 has the ESGS ring buffer in LDS. */
1193 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1194 ac_declare_lds_as_pointer(&ctx->ac);
1195 }
1196
1197 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1198 }
1199
1200
1201 static LLVMValueRef
1202 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1203 unsigned desc_set, unsigned binding)
1204 {
1205 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1206 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1207 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1208 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1209 unsigned base_offset = layout->binding[binding].offset;
1210 LLVMValueRef offset, stride;
1211
1212 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1213 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1214 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1215 layout->binding[binding].dynamic_offset_offset;
1216 desc_ptr = ctx->abi.push_constants;
1217 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1218 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1219 } else
1220 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1221
1222 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1223 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
1224 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
1225
1226 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1227 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1228 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1229
1230 return desc_ptr;
1231 }
1232
1233
1234 /* The offchip buffer layout for TCS->TES is
1235 *
1236 * - attribute 0 of patch 0 vertex 0
1237 * - attribute 0 of patch 0 vertex 1
1238 * - attribute 0 of patch 0 vertex 2
1239 * ...
1240 * - attribute 0 of patch 1 vertex 0
1241 * - attribute 0 of patch 1 vertex 1
1242 * ...
1243 * - attribute 1 of patch 0 vertex 0
1244 * - attribute 1 of patch 0 vertex 1
1245 * ...
1246 * - per patch attribute 0 of patch 0
1247 * - per patch attribute 0 of patch 1
1248 * ...
1249 *
1250 * Note that every attribute has 4 components.
1251 */
1252 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1253 {
1254 uint32_t num_patches = ctx->tcs_num_patches;
1255 uint32_t num_tcs_outputs;
1256 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1257 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1258 else
1259 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1260
1261 uint32_t output_vertex_size = num_tcs_outputs * 16;
1262 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1263
1264 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1265 }
1266
1267 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1268 LLVMValueRef vertex_index)
1269 {
1270 LLVMValueRef param_stride;
1271 if (vertex_index)
1272 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1273 else
1274 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1275 return param_stride;
1276 }
1277
1278 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1279 LLVMValueRef vertex_index,
1280 LLVMValueRef param_index)
1281 {
1282 LLVMValueRef base_addr;
1283 LLVMValueRef param_stride, constant16;
1284 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1285 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1286 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1287 param_stride = calc_param_stride(ctx, vertex_index);
1288 if (vertex_index) {
1289 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
1290 vertices_per_patch, "");
1291
1292 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1293 vertex_index, "");
1294 } else {
1295 base_addr = rel_patch_id;
1296 }
1297
1298 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1299 LLVMBuildMul(ctx->ac.builder, param_index,
1300 param_stride, ""), "");
1301
1302 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1303
1304 if (!vertex_index) {
1305 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1306
1307 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1308 patch_data_offset, "");
1309 }
1310 return base_addr;
1311 }
1312
1313 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1314 unsigned param,
1315 unsigned const_index,
1316 bool is_compact,
1317 LLVMValueRef vertex_index,
1318 LLVMValueRef indir_index)
1319 {
1320 LLVMValueRef param_index;
1321
1322 if (indir_index)
1323 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1324 indir_index, "");
1325 else {
1326 if (const_index && !is_compact)
1327 param += const_index;
1328 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1329 }
1330 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1331 }
1332
1333 static LLVMValueRef
1334 get_dw_address(struct radv_shader_context *ctx,
1335 LLVMValueRef dw_addr,
1336 unsigned param,
1337 unsigned const_index,
1338 bool compact_const_index,
1339 LLVMValueRef vertex_index,
1340 LLVMValueRef stride,
1341 LLVMValueRef indir_index)
1342
1343 {
1344
1345 if (vertex_index) {
1346 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1347 LLVMBuildMul(ctx->ac.builder,
1348 vertex_index,
1349 stride, ""), "");
1350 }
1351
1352 if (indir_index)
1353 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1354 LLVMBuildMul(ctx->ac.builder, indir_index,
1355 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1356 else if (const_index && !compact_const_index)
1357 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1358 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1359
1360 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1361 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1362
1363 if (const_index && compact_const_index)
1364 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1365 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1366 return dw_addr;
1367 }
1368
1369 static LLVMValueRef
1370 load_tcs_varyings(struct ac_shader_abi *abi,
1371 LLVMTypeRef type,
1372 LLVMValueRef vertex_index,
1373 LLVMValueRef indir_index,
1374 unsigned const_index,
1375 unsigned location,
1376 unsigned driver_location,
1377 unsigned component,
1378 unsigned num_components,
1379 bool is_patch,
1380 bool is_compact,
1381 bool load_input)
1382 {
1383 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1384 LLVMValueRef dw_addr, stride;
1385 LLVMValueRef value[4], result;
1386 unsigned param = shader_io_get_unique_index(location);
1387
1388 if (load_input) {
1389 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1390 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1391 dw_addr = get_tcs_in_current_patch_offset(ctx);
1392 } else {
1393 if (!is_patch) {
1394 stride = get_tcs_out_vertex_stride(ctx);
1395 dw_addr = get_tcs_out_current_patch_offset(ctx);
1396 } else {
1397 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1398 stride = NULL;
1399 }
1400 }
1401
1402 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1403 indir_index);
1404
1405 for (unsigned i = 0; i < num_components + component; i++) {
1406 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1407 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1408 ctx->ac.i32_1, "");
1409 }
1410 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1411 return result;
1412 }
1413
1414 static void
1415 store_tcs_output(struct ac_shader_abi *abi,
1416 const nir_variable *var,
1417 LLVMValueRef vertex_index,
1418 LLVMValueRef param_index,
1419 unsigned const_index,
1420 LLVMValueRef src,
1421 unsigned writemask)
1422 {
1423 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1424 const unsigned location = var->data.location;
1425 const unsigned component = var->data.location_frac;
1426 const bool is_patch = var->data.patch;
1427 const bool is_compact = var->data.compact;
1428 LLVMValueRef dw_addr;
1429 LLVMValueRef stride = NULL;
1430 LLVMValueRef buf_addr = NULL;
1431 unsigned param;
1432 bool store_lds = true;
1433
1434 if (is_patch) {
1435 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1436 store_lds = false;
1437 } else {
1438 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1439 store_lds = false;
1440 }
1441
1442 param = shader_io_get_unique_index(location);
1443 if (location == VARYING_SLOT_CLIP_DIST0 &&
1444 is_compact && const_index > 3) {
1445 const_index -= 3;
1446 param++;
1447 }
1448
1449 if (!is_patch) {
1450 stride = get_tcs_out_vertex_stride(ctx);
1451 dw_addr = get_tcs_out_current_patch_offset(ctx);
1452 } else {
1453 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1454 }
1455
1456 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1457 param_index);
1458 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1459 vertex_index, param_index);
1460
1461 bool is_tess_factor = false;
1462 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1463 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1464 is_tess_factor = true;
1465
1466 unsigned base = is_compact ? const_index : 0;
1467 for (unsigned chan = 0; chan < 8; chan++) {
1468 if (!(writemask & (1 << chan)))
1469 continue;
1470 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1471
1472 if (store_lds || is_tess_factor) {
1473 LLVMValueRef dw_addr_chan =
1474 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1475 LLVMConstInt(ctx->ac.i32, chan, false), "");
1476 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1477 }
1478
1479 if (!is_tess_factor && writemask != 0xF)
1480 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1481 buf_addr, ctx->oc_lds,
1482 4 * (base + chan), 1, 0, true, false);
1483 }
1484
1485 if (writemask == 0xF) {
1486 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1487 buf_addr, ctx->oc_lds,
1488 (base * 4), 1, 0, true, false);
1489 }
1490 }
1491
1492 static LLVMValueRef
1493 load_tes_input(struct ac_shader_abi *abi,
1494 LLVMTypeRef type,
1495 LLVMValueRef vertex_index,
1496 LLVMValueRef param_index,
1497 unsigned const_index,
1498 unsigned location,
1499 unsigned driver_location,
1500 unsigned component,
1501 unsigned num_components,
1502 bool is_patch,
1503 bool is_compact,
1504 bool load_input)
1505 {
1506 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1507 LLVMValueRef buf_addr;
1508 LLVMValueRef result;
1509 unsigned param = shader_io_get_unique_index(location);
1510
1511 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1512 const_index -= 3;
1513 param++;
1514 }
1515
1516 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1517 is_compact, vertex_index, param_index);
1518
1519 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1520 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1521
1522 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1523 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1524 result = ac_trim_vector(&ctx->ac, result, num_components);
1525 return result;
1526 }
1527
1528 static LLVMValueRef
1529 load_gs_input(struct ac_shader_abi *abi,
1530 unsigned location,
1531 unsigned driver_location,
1532 unsigned component,
1533 unsigned num_components,
1534 unsigned vertex_index,
1535 unsigned const_index,
1536 LLVMTypeRef type)
1537 {
1538 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1539 LLVMValueRef vtx_offset;
1540 unsigned param, vtx_offset_param;
1541 LLVMValueRef value[4], result;
1542
1543 vtx_offset_param = vertex_index;
1544 assert(vtx_offset_param < 6);
1545 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1546 LLVMConstInt(ctx->ac.i32, 4, false), "");
1547
1548 param = shader_io_get_unique_index(location);
1549
1550 for (unsigned i = component; i < num_components + component; i++) {
1551 if (ctx->ac.chip_class >= GFX9) {
1552 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1553 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1554 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1555 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1556 } else {
1557 LLVMValueRef soffset =
1558 LLVMConstInt(ctx->ac.i32,
1559 (param * 4 + i + const_index) * 256,
1560 false);
1561
1562 value[i] = ac_build_buffer_load(&ctx->ac,
1563 ctx->esgs_ring, 1,
1564 ctx->ac.i32_0,
1565 vtx_offset, soffset,
1566 0, 1, 0, true, false);
1567
1568 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
1569 type, "");
1570 }
1571 }
1572 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1573 result = ac_to_integer(&ctx->ac, result);
1574 return result;
1575 }
1576
1577
1578 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1579 {
1580 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1581 ac_build_kill_if_false(&ctx->ac, visible);
1582 }
1583
1584 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1585 enum glsl_interp_mode interp, unsigned location)
1586 {
1587 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1588
1589 switch (interp) {
1590 case INTERP_MODE_FLAT:
1591 default:
1592 return NULL;
1593 case INTERP_MODE_SMOOTH:
1594 case INTERP_MODE_NONE:
1595 if (location == INTERP_CENTER)
1596 return ctx->persp_center;
1597 else if (location == INTERP_CENTROID)
1598 return ctx->persp_centroid;
1599 else if (location == INTERP_SAMPLE)
1600 return ctx->persp_sample;
1601 break;
1602 case INTERP_MODE_NOPERSPECTIVE:
1603 if (location == INTERP_CENTER)
1604 return ctx->linear_center;
1605 else if (location == INTERP_CENTROID)
1606 return ctx->linear_centroid;
1607 else if (location == INTERP_SAMPLE)
1608 return ctx->linear_sample;
1609 break;
1610 }
1611 return NULL;
1612 }
1613
1614 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1615 LLVMValueRef sample_id)
1616 {
1617 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1618
1619 LLVMValueRef result;
1620 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1621
1622 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1623 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1624
1625 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
1626 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1627
1628 return result;
1629 }
1630
1631
1632 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1633 {
1634 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1635 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
1636 ctx->options->key.fs.log2_num_samples :
1637 ctx->options->key.fs.log2_ps_iter_samples;
1638
1639 /* The bit pattern matches that used by fixed function fragment
1640 * processing. */
1641 static const uint16_t ps_iter_masks[] = {
1642 0xffff, /* not used */
1643 0x5555,
1644 0x1111,
1645 0x0101,
1646 0x0001,
1647 };
1648 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1649
1650 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1651
1652 LLVMValueRef result, sample_id;
1653 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1654 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1655 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1656 return result;
1657 }
1658
1659
1660 static void
1661 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1662 {
1663 LLVMValueRef gs_next_vertex;
1664 LLVMValueRef can_emit;
1665 int idx;
1666 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1667
1668 assert(stream == 0);
1669
1670 /* Write vertex attribute values to GSVS ring */
1671 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1672 ctx->gs_next_vertex,
1673 "");
1674
1675 /* If this thread has already emitted the declared maximum number of
1676 * vertices, kill it: excessive vertex emissions are not supposed to
1677 * have any effect, and GS threads have no externally observable
1678 * effects other than emitting vertices.
1679 */
1680 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1681 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1682 ac_build_kill_if_false(&ctx->ac, can_emit);
1683
1684 /* loop num outputs */
1685 idx = 0;
1686 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1687 unsigned output_usage_mask =
1688 ctx->shader_info->info.gs.output_usage_mask[i];
1689 LLVMValueRef *out_ptr = &addrs[i * 4];
1690 int length = 4;
1691 int slot = idx;
1692 int slot_inc = 1;
1693
1694 if (!(ctx->output_mask & (1ull << i)))
1695 continue;
1696
1697 if (i == VARYING_SLOT_CLIP_DIST0) {
1698 /* pack clip and cull into a single set of slots */
1699 length = ctx->num_output_clips + ctx->num_output_culls;
1700 if (length > 4)
1701 slot_inc = 2;
1702 output_usage_mask = (1 << length) - 1;
1703 }
1704
1705 for (unsigned j = 0; j < length; j++) {
1706 if (!(output_usage_mask & (1 << j)))
1707 continue;
1708
1709 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1710 out_ptr[j], "");
1711 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1712 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1713 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1714
1715 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1716
1717 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1718 out_val, 1,
1719 voffset, ctx->gs2vs_offset, 0,
1720 1, 1, true, true);
1721 }
1722 idx += slot_inc;
1723 }
1724
1725 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1726 ctx->ac.i32_1, "");
1727 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1728
1729 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1730 }
1731
1732 static void
1733 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1734 {
1735 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1736 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1737 }
1738
1739 static LLVMValueRef
1740 load_tess_coord(struct ac_shader_abi *abi)
1741 {
1742 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1743
1744 LLVMValueRef coord[4] = {
1745 ctx->tes_u,
1746 ctx->tes_v,
1747 ctx->ac.f32_0,
1748 ctx->ac.f32_0,
1749 };
1750
1751 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1752 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1753 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1754
1755 return ac_build_gather_values(&ctx->ac, coord, 3);
1756 }
1757
1758 static LLVMValueRef
1759 load_patch_vertices_in(struct ac_shader_abi *abi)
1760 {
1761 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1762 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1763 }
1764
1765
1766 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1767 {
1768 return abi->base_vertex;
1769 }
1770
1771 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1772 LLVMValueRef buffer_ptr, bool write)
1773 {
1774 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1775 LLVMValueRef result;
1776
1777 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1778
1779 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1780 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1781
1782 return result;
1783 }
1784
1785 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1786 {
1787 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1788 LLVMValueRef result;
1789
1790 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1791
1792 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1793 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1794
1795 return result;
1796 }
1797
1798 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1799 unsigned descriptor_set,
1800 unsigned base_index,
1801 unsigned constant_index,
1802 LLVMValueRef index,
1803 enum ac_descriptor_type desc_type,
1804 bool image, bool write,
1805 bool bindless)
1806 {
1807 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1808 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1809 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1810 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1811 unsigned offset = binding->offset;
1812 unsigned stride = binding->size;
1813 unsigned type_size;
1814 LLVMBuilderRef builder = ctx->ac.builder;
1815 LLVMTypeRef type;
1816
1817 assert(base_index < layout->binding_count);
1818
1819 switch (desc_type) {
1820 case AC_DESC_IMAGE:
1821 type = ctx->ac.v8i32;
1822 type_size = 32;
1823 break;
1824 case AC_DESC_FMASK:
1825 type = ctx->ac.v8i32;
1826 offset += 32;
1827 type_size = 32;
1828 break;
1829 case AC_DESC_SAMPLER:
1830 type = ctx->ac.v4i32;
1831 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1832 offset += 64;
1833
1834 type_size = 16;
1835 break;
1836 case AC_DESC_BUFFER:
1837 type = ctx->ac.v4i32;
1838 type_size = 16;
1839 break;
1840 default:
1841 unreachable("invalid desc_type\n");
1842 }
1843
1844 offset += constant_index * stride;
1845
1846 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1847 (!index || binding->immutable_samplers_equal)) {
1848 if (binding->immutable_samplers_equal)
1849 constant_index = 0;
1850
1851 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1852
1853 LLVMValueRef constants[] = {
1854 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1855 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1856 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1857 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1858 };
1859 return ac_build_gather_values(&ctx->ac, constants, 4);
1860 }
1861
1862 assert(stride % type_size == 0);
1863
1864 if (!index)
1865 index = ctx->ac.i32_0;
1866
1867 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1868
1869 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1870 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
1871
1872 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1873 }
1874
1875 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1876 * so we may need to fix it up. */
1877 static LLVMValueRef
1878 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1879 unsigned adjustment,
1880 LLVMValueRef alpha)
1881 {
1882 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1883 return alpha;
1884
1885 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1886
1887 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1888 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1889 else
1890 alpha = ac_to_integer(&ctx->ac, alpha);
1891
1892 /* For the integer-like cases, do a natural sign extension.
1893 *
1894 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1895 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1896 * exponent.
1897 */
1898 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1899 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1900 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1901 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1902
1903 /* Convert back to the right type. */
1904 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1905 LLVMValueRef clamp;
1906 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1907 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1908 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1909 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1910 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1911 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1912 }
1913
1914 return alpha;
1915 }
1916
1917 static void
1918 handle_vs_input_decl(struct radv_shader_context *ctx,
1919 struct nir_variable *variable)
1920 {
1921 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1922 LLVMValueRef t_offset;
1923 LLVMValueRef t_list;
1924 LLVMValueRef input;
1925 LLVMValueRef buffer_index;
1926 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1927 uint8_t input_usage_mask =
1928 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1929 unsigned num_channels = util_last_bit(input_usage_mask);
1930
1931 variable->data.driver_location = variable->data.location * 4;
1932
1933 for (unsigned i = 0; i < attrib_count; ++i) {
1934 LLVMValueRef output[4];
1935 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1936
1937 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1938 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
1939
1940 if (divisor) {
1941 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
1942 ctx->abi.start_instance, "");
1943
1944 if (divisor != 1) {
1945 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1946 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1947 }
1948
1949 if (ctx->options->key.vs.as_ls) {
1950 ctx->shader_info->vs.vgpr_comp_cnt =
1951 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1952 } else {
1953 ctx->shader_info->vs.vgpr_comp_cnt =
1954 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1955 }
1956 } else {
1957 buffer_index = ctx->ac.i32_0;
1958 }
1959 } else
1960 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
1961 ctx->abi.base_vertex, "");
1962 t_offset = LLVMConstInt(ctx->ac.i32, attrib_index, false);
1963
1964 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1965
1966 input = ac_build_buffer_load_format(&ctx->ac, t_list,
1967 buffer_index,
1968 ctx->ac.i32_0,
1969 num_channels, false, true);
1970
1971 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
1972
1973 for (unsigned chan = 0; chan < 4; chan++) {
1974 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1975 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1976 }
1977
1978 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
1979 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
1980
1981 for (unsigned chan = 0; chan < 4; chan++) {
1982 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] =
1983 ac_to_integer(&ctx->ac, output[chan]);
1984 }
1985 }
1986 }
1987
1988 static void interp_fs_input(struct radv_shader_context *ctx,
1989 unsigned attr,
1990 LLVMValueRef interp_param,
1991 LLVMValueRef prim_mask,
1992 LLVMValueRef result[4])
1993 {
1994 LLVMValueRef attr_number;
1995 unsigned chan;
1996 LLVMValueRef i, j;
1997 bool interp = interp_param != NULL;
1998
1999 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
2000
2001 /* fs.constant returns the param from the middle vertex, so it's not
2002 * really useful for flat shading. It's meant to be used for custom
2003 * interpolation (but the intrinsic can't fetch from the other two
2004 * vertices).
2005 *
2006 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2007 * to do the right thing. The only reason we use fs.constant is that
2008 * fs.interp cannot be used on integers, because they can be equal
2009 * to NaN.
2010 */
2011 if (interp) {
2012 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
2013 ctx->ac.v2f32, "");
2014
2015 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2016 ctx->ac.i32_0, "");
2017 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2018 ctx->ac.i32_1, "");
2019 }
2020
2021 for (chan = 0; chan < 4; chan++) {
2022 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2023
2024 if (interp) {
2025 result[chan] = ac_build_fs_interp(&ctx->ac,
2026 llvm_chan,
2027 attr_number,
2028 prim_mask, i, j);
2029 } else {
2030 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2031 LLVMConstInt(ctx->ac.i32, 2, false),
2032 llvm_chan,
2033 attr_number,
2034 prim_mask);
2035 }
2036 }
2037 }
2038
2039 static void
2040 handle_fs_input_decl(struct radv_shader_context *ctx,
2041 struct nir_variable *variable)
2042 {
2043 int idx = variable->data.location;
2044 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2045 LLVMValueRef interp;
2046
2047 variable->data.driver_location = idx * 4;
2048 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
2049
2050 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
2051 unsigned interp_type;
2052 if (variable->data.sample)
2053 interp_type = INTERP_SAMPLE;
2054 else if (variable->data.centroid)
2055 interp_type = INTERP_CENTROID;
2056 else
2057 interp_type = INTERP_CENTER;
2058
2059 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
2060 } else
2061 interp = NULL;
2062
2063 for (unsigned i = 0; i < attrib_count; ++i)
2064 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
2065
2066 }
2067
2068 static void
2069 handle_vs_inputs(struct radv_shader_context *ctx,
2070 struct nir_shader *nir) {
2071 nir_foreach_variable(variable, &nir->inputs)
2072 handle_vs_input_decl(ctx, variable);
2073 }
2074
2075 static void
2076 prepare_interp_optimize(struct radv_shader_context *ctx,
2077 struct nir_shader *nir)
2078 {
2079 if (!ctx->options->key.fs.multisample)
2080 return;
2081
2082 bool uses_center = false;
2083 bool uses_centroid = false;
2084 nir_foreach_variable(variable, &nir->inputs) {
2085 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2086 variable->data.sample)
2087 continue;
2088
2089 if (variable->data.centroid)
2090 uses_centroid = true;
2091 else
2092 uses_center = true;
2093 }
2094
2095 if (uses_center && uses_centroid) {
2096 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2097 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
2098 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
2099 }
2100 }
2101
2102 static void
2103 handle_fs_inputs(struct radv_shader_context *ctx,
2104 struct nir_shader *nir)
2105 {
2106 prepare_interp_optimize(ctx, nir);
2107
2108 nir_foreach_variable(variable, &nir->inputs)
2109 handle_fs_input_decl(ctx, variable);
2110
2111 unsigned index = 0;
2112
2113 if (ctx->shader_info->info.ps.uses_input_attachments ||
2114 ctx->shader_info->info.needs_multiview_view_index)
2115 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
2116
2117 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
2118 LLVMValueRef interp_param;
2119 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
2120
2121 if (!(ctx->input_mask & (1ull << i)))
2122 continue;
2123
2124 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
2125 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
2126 interp_param = *inputs;
2127 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
2128 inputs);
2129
2130 if (!interp_param)
2131 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
2132 ++index;
2133 } else if (i == VARYING_SLOT_POS) {
2134 for(int i = 0; i < 3; ++i)
2135 inputs[i] = ctx->abi.frag_pos[i];
2136
2137 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2138 ctx->abi.frag_pos[3]);
2139 }
2140 }
2141 ctx->shader_info->fs.num_interp = index;
2142 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
2143
2144 if (ctx->shader_info->info.needs_multiview_view_index)
2145 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2146 }
2147
2148 static void
2149 scan_shader_output_decl(struct radv_shader_context *ctx,
2150 struct nir_variable *variable,
2151 struct nir_shader *shader,
2152 gl_shader_stage stage)
2153 {
2154 int idx = variable->data.location + variable->data.index;
2155 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2156 uint64_t mask_attribs;
2157
2158 variable->data.driver_location = idx * 4;
2159
2160 /* tess ctrl has it's own load/store paths for outputs */
2161 if (stage == MESA_SHADER_TESS_CTRL)
2162 return;
2163
2164 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2165 if (stage == MESA_SHADER_VERTEX ||
2166 stage == MESA_SHADER_TESS_EVAL ||
2167 stage == MESA_SHADER_GEOMETRY) {
2168 if (idx == VARYING_SLOT_CLIP_DIST0) {
2169 int length = shader->info.clip_distance_array_size +
2170 shader->info.cull_distance_array_size;
2171 if (stage == MESA_SHADER_VERTEX) {
2172 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2173 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2174 }
2175 if (stage == MESA_SHADER_TESS_EVAL) {
2176 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2177 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2178 }
2179
2180 if (length > 4)
2181 attrib_count = 2;
2182 else
2183 attrib_count = 1;
2184 mask_attribs = 1ull << idx;
2185 }
2186 }
2187
2188 ctx->output_mask |= mask_attribs;
2189 }
2190
2191
2192 /* Initialize arguments for the shader export intrinsic */
2193 static void
2194 si_llvm_init_export_args(struct radv_shader_context *ctx,
2195 LLVMValueRef *values,
2196 unsigned enabled_channels,
2197 unsigned target,
2198 struct ac_export_args *args)
2199 {
2200 /* Specify the channels that are enabled. */
2201 args->enabled_channels = enabled_channels;
2202
2203 /* Specify whether the EXEC mask represents the valid mask */
2204 args->valid_mask = 0;
2205
2206 /* Specify whether this is the last export */
2207 args->done = 0;
2208
2209 /* Specify the target we are exporting */
2210 args->target = target;
2211
2212 args->compr = false;
2213 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2214 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2215 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2216 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2217
2218 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2219 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2220 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2221 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2222 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2223 unsigned chan;
2224
2225 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2226 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2227 unsigned bits, bool hi) = NULL;
2228
2229 switch(col_format) {
2230 case V_028714_SPI_SHADER_ZERO:
2231 args->enabled_channels = 0; /* writemask */
2232 args->target = V_008DFC_SQ_EXP_NULL;
2233 break;
2234
2235 case V_028714_SPI_SHADER_32_R:
2236 args->enabled_channels = 1;
2237 args->out[0] = values[0];
2238 break;
2239
2240 case V_028714_SPI_SHADER_32_GR:
2241 args->enabled_channels = 0x3;
2242 args->out[0] = values[0];
2243 args->out[1] = values[1];
2244 break;
2245
2246 case V_028714_SPI_SHADER_32_AR:
2247 args->enabled_channels = 0x9;
2248 args->out[0] = values[0];
2249 args->out[3] = values[3];
2250 break;
2251
2252 case V_028714_SPI_SHADER_FP16_ABGR:
2253 args->enabled_channels = 0x5;
2254 packf = ac_build_cvt_pkrtz_f16;
2255 break;
2256
2257 case V_028714_SPI_SHADER_UNORM16_ABGR:
2258 args->enabled_channels = 0x5;
2259 packf = ac_build_cvt_pknorm_u16;
2260 break;
2261
2262 case V_028714_SPI_SHADER_SNORM16_ABGR:
2263 args->enabled_channels = 0x5;
2264 packf = ac_build_cvt_pknorm_i16;
2265 break;
2266
2267 case V_028714_SPI_SHADER_UINT16_ABGR:
2268 args->enabled_channels = 0x5;
2269 packi = ac_build_cvt_pk_u16;
2270 break;
2271
2272 case V_028714_SPI_SHADER_SINT16_ABGR:
2273 args->enabled_channels = 0x5;
2274 packi = ac_build_cvt_pk_i16;
2275 break;
2276
2277 default:
2278 case V_028714_SPI_SHADER_32_ABGR:
2279 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2280 break;
2281 }
2282
2283 /* Pack f16 or norm_i16/u16. */
2284 if (packf) {
2285 for (chan = 0; chan < 2; chan++) {
2286 LLVMValueRef pack_args[2] = {
2287 values[2 * chan],
2288 values[2 * chan + 1]
2289 };
2290 LLVMValueRef packed;
2291
2292 packed = packf(&ctx->ac, pack_args);
2293 args->out[chan] = ac_to_float(&ctx->ac, packed);
2294 }
2295 args->compr = 1; /* COMPR flag */
2296 }
2297
2298 /* Pack i16/u16. */
2299 if (packi) {
2300 for (chan = 0; chan < 2; chan++) {
2301 LLVMValueRef pack_args[2] = {
2302 ac_to_integer(&ctx->ac, values[2 * chan]),
2303 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2304 };
2305 LLVMValueRef packed;
2306
2307 packed = packi(&ctx->ac, pack_args,
2308 is_int8 ? 8 : is_int10 ? 10 : 16,
2309 chan == 1);
2310 args->out[chan] = ac_to_float(&ctx->ac, packed);
2311 }
2312 args->compr = 1; /* COMPR flag */
2313 }
2314 return;
2315 }
2316
2317 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2318
2319 for (unsigned i = 0; i < 4; ++i) {
2320 if (!(args->enabled_channels & (1 << i)))
2321 continue;
2322
2323 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2324 }
2325 }
2326
2327 static void
2328 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2329 LLVMValueRef *values, unsigned enabled_channels)
2330 {
2331 struct ac_export_args args;
2332
2333 si_llvm_init_export_args(ctx, values, enabled_channels,
2334 V_008DFC_SQ_EXP_PARAM + index, &args);
2335 ac_build_export(&ctx->ac, &args);
2336 }
2337
2338 static LLVMValueRef
2339 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2340 {
2341 LLVMValueRef output =
2342 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2343
2344 return LLVMBuildLoad(ctx->ac.builder, output, "");
2345 }
2346
2347 static void
2348 handle_vs_outputs_post(struct radv_shader_context *ctx,
2349 bool export_prim_id, bool export_layer_id,
2350 struct radv_vs_output_info *outinfo)
2351 {
2352 uint32_t param_count = 0;
2353 unsigned target;
2354 unsigned pos_idx, num_pos_exports = 0;
2355 struct ac_export_args args, pos_args[4] = {};
2356 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2357 int i;
2358
2359 if (ctx->options->key.has_multiview_view_index) {
2360 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2361 if(!*tmp_out) {
2362 for(unsigned i = 0; i < 4; ++i)
2363 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2364 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2365 }
2366
2367 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2368 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2369 }
2370
2371 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2372 sizeof(outinfo->vs_output_param_offset));
2373
2374 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2375 LLVMValueRef slots[8];
2376 unsigned j;
2377
2378 if (outinfo->cull_dist_mask)
2379 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2380
2381 i = VARYING_SLOT_CLIP_DIST0;
2382 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
2383 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2384
2385 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
2386 slots[i] = LLVMGetUndef(ctx->ac.f32);
2387
2388 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
2389 target = V_008DFC_SQ_EXP_POS + 3;
2390 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2391 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2392 &args, sizeof(args));
2393 }
2394
2395 target = V_008DFC_SQ_EXP_POS + 2;
2396 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2397 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2398 &args, sizeof(args));
2399
2400 }
2401
2402 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2403 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2404 for (unsigned j = 0; j < 4; j++)
2405 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2406 }
2407 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2408
2409 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2410 outinfo->writes_pointsize = true;
2411 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2412 }
2413
2414 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2415 outinfo->writes_layer = true;
2416 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2417 }
2418
2419 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2420 outinfo->writes_viewport_index = true;
2421 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2422 }
2423
2424 if (outinfo->writes_pointsize ||
2425 outinfo->writes_layer ||
2426 outinfo->writes_viewport_index) {
2427 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2428 (outinfo->writes_layer == true ? 4 : 0));
2429 pos_args[1].valid_mask = 0;
2430 pos_args[1].done = 0;
2431 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2432 pos_args[1].compr = 0;
2433 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2434 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2435 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2436 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2437
2438 if (outinfo->writes_pointsize == true)
2439 pos_args[1].out[0] = psize_value;
2440 if (outinfo->writes_layer == true)
2441 pos_args[1].out[2] = layer_value;
2442 if (outinfo->writes_viewport_index == true) {
2443 if (ctx->options->chip_class >= GFX9) {
2444 /* GFX9 has the layer in out.z[10:0] and the viewport
2445 * index in out.z[19:16].
2446 */
2447 LLVMValueRef v = viewport_index_value;
2448 v = ac_to_integer(&ctx->ac, v);
2449 v = LLVMBuildShl(ctx->ac.builder, v,
2450 LLVMConstInt(ctx->ac.i32, 16, false),
2451 "");
2452 v = LLVMBuildOr(ctx->ac.builder, v,
2453 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2454
2455 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2456 pos_args[1].enabled_channels |= 1 << 2;
2457 } else {
2458 pos_args[1].out[3] = viewport_index_value;
2459 pos_args[1].enabled_channels |= 1 << 3;
2460 }
2461 }
2462 }
2463 for (i = 0; i < 4; i++) {
2464 if (pos_args[i].out[0])
2465 num_pos_exports++;
2466 }
2467
2468 pos_idx = 0;
2469 for (i = 0; i < 4; i++) {
2470 if (!pos_args[i].out[0])
2471 continue;
2472
2473 /* Specify the target we are exporting */
2474 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2475 if (pos_idx == num_pos_exports)
2476 pos_args[i].done = 1;
2477 ac_build_export(&ctx->ac, &pos_args[i]);
2478 }
2479
2480 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2481 LLVMValueRef values[4];
2482 if (!(ctx->output_mask & (1ull << i)))
2483 continue;
2484
2485 if (i != VARYING_SLOT_LAYER &&
2486 i != VARYING_SLOT_PRIMITIVE_ID &&
2487 i < VARYING_SLOT_VAR0)
2488 continue;
2489
2490 for (unsigned j = 0; j < 4; j++)
2491 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2492
2493 unsigned output_usage_mask;
2494
2495 if (ctx->stage == MESA_SHADER_VERTEX &&
2496 !ctx->is_gs_copy_shader) {
2497 output_usage_mask =
2498 ctx->shader_info->info.vs.output_usage_mask[i];
2499 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2500 output_usage_mask =
2501 ctx->shader_info->info.tes.output_usage_mask[i];
2502 } else {
2503 assert(ctx->is_gs_copy_shader);
2504 output_usage_mask =
2505 ctx->shader_info->info.gs.output_usage_mask[i];
2506 }
2507
2508 radv_export_param(ctx, param_count, values, output_usage_mask);
2509
2510 outinfo->vs_output_param_offset[i] = param_count++;
2511 }
2512
2513 if (export_prim_id) {
2514 LLVMValueRef values[4];
2515
2516 values[0] = ctx->vs_prim_id;
2517 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2518 ctx->shader_info->vs.vgpr_comp_cnt);
2519 for (unsigned j = 1; j < 4; j++)
2520 values[j] = ctx->ac.f32_0;
2521
2522 radv_export_param(ctx, param_count, values, 0x1);
2523
2524 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2525 outinfo->export_prim_id = true;
2526 }
2527
2528 if (export_layer_id && layer_value) {
2529 LLVMValueRef values[4];
2530
2531 values[0] = layer_value;
2532 for (unsigned j = 1; j < 4; j++)
2533 values[j] = ctx->ac.f32_0;
2534
2535 radv_export_param(ctx, param_count, values, 0x1);
2536
2537 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2538 }
2539
2540 outinfo->pos_exports = num_pos_exports;
2541 outinfo->param_exports = param_count;
2542 }
2543
2544 static void
2545 handle_es_outputs_post(struct radv_shader_context *ctx,
2546 struct radv_es_output_info *outinfo)
2547 {
2548 int j;
2549 uint64_t max_output_written = 0;
2550 LLVMValueRef lds_base = NULL;
2551
2552 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2553 int param_index;
2554 int length = 4;
2555
2556 if (!(ctx->output_mask & (1ull << i)))
2557 continue;
2558
2559 if (i == VARYING_SLOT_CLIP_DIST0)
2560 length = ctx->num_output_clips + ctx->num_output_culls;
2561
2562 param_index = shader_io_get_unique_index(i);
2563
2564 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2565 }
2566
2567 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2568
2569 if (ctx->ac.chip_class >= GFX9) {
2570 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2571 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2572 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2573 LLVMConstInt(ctx->ac.i32, 24, false),
2574 LLVMConstInt(ctx->ac.i32, 4, false), false);
2575 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2576 LLVMBuildMul(ctx->ac.builder, wave_idx,
2577 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2578 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2579 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2580 }
2581
2582 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2583 LLVMValueRef dw_addr = NULL;
2584 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2585 unsigned output_usage_mask;
2586 int param_index;
2587 int length = 4;
2588
2589 if (!(ctx->output_mask & (1ull << i)))
2590 continue;
2591
2592 if (ctx->stage == MESA_SHADER_VERTEX) {
2593 output_usage_mask =
2594 ctx->shader_info->info.vs.output_usage_mask[i];
2595 } else {
2596 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2597 output_usage_mask =
2598 ctx->shader_info->info.tes.output_usage_mask[i];
2599 }
2600
2601 if (i == VARYING_SLOT_CLIP_DIST0) {
2602 length = ctx->num_output_clips + ctx->num_output_culls;
2603 output_usage_mask = (1 << length) - 1;
2604 }
2605
2606 param_index = shader_io_get_unique_index(i);
2607
2608 if (lds_base) {
2609 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2610 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2611 "");
2612 }
2613
2614 for (j = 0; j < length; j++) {
2615 if (!(output_usage_mask & (1 << j)))
2616 continue;
2617
2618 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2619 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2620
2621 if (ctx->ac.chip_class >= GFX9) {
2622 LLVMValueRef dw_addr_offset =
2623 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2624 LLVMConstInt(ctx->ac.i32,
2625 j, false), "");
2626
2627 ac_lds_store(&ctx->ac, dw_addr_offset,
2628 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2629 } else {
2630 ac_build_buffer_store_dword(&ctx->ac,
2631 ctx->esgs_ring,
2632 out_val, 1,
2633 NULL, ctx->es2gs_offset,
2634 (4 * param_index + j) * 4,
2635 1, 1, true, true);
2636 }
2637 }
2638 }
2639 }
2640
2641 static void
2642 handle_ls_outputs_post(struct radv_shader_context *ctx)
2643 {
2644 LLVMValueRef vertex_id = ctx->rel_auto_id;
2645 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2646 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2647 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2648 vertex_dw_stride, "");
2649
2650 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2651 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2652 int length = 4;
2653
2654 if (!(ctx->output_mask & (1ull << i)))
2655 continue;
2656
2657 if (i == VARYING_SLOT_CLIP_DIST0)
2658 length = ctx->num_output_clips + ctx->num_output_culls;
2659 int param = shader_io_get_unique_index(i);
2660 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2661 LLVMConstInt(ctx->ac.i32, param * 4, false),
2662 "");
2663 for (unsigned j = 0; j < length; j++) {
2664 ac_lds_store(&ctx->ac, dw_addr,
2665 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2666 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2667 }
2668 }
2669 }
2670
2671 static void
2672 write_tess_factors(struct radv_shader_context *ctx)
2673 {
2674 unsigned stride, outer_comps, inner_comps;
2675 struct ac_build_if_state if_ctx, inner_if_ctx;
2676 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2677 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2678 unsigned tess_inner_index = 0, tess_outer_index;
2679 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2680 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2681 int i;
2682 ac_emit_barrier(&ctx->ac, ctx->stage);
2683
2684 switch (ctx->options->key.tcs.primitive_mode) {
2685 case GL_ISOLINES:
2686 stride = 2;
2687 outer_comps = 2;
2688 inner_comps = 0;
2689 break;
2690 case GL_TRIANGLES:
2691 stride = 4;
2692 outer_comps = 3;
2693 inner_comps = 1;
2694 break;
2695 case GL_QUADS:
2696 stride = 6;
2697 outer_comps = 4;
2698 inner_comps = 2;
2699 break;
2700 default:
2701 return;
2702 }
2703
2704 ac_nir_build_if(&if_ctx, ctx,
2705 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2706 invocation_id, ctx->ac.i32_0, ""));
2707
2708 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2709
2710 if (inner_comps) {
2711 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2712 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2713 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2714 }
2715
2716 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2717 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2718 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2719
2720 for (i = 0; i < 4; i++) {
2721 inner[i] = LLVMGetUndef(ctx->ac.i32);
2722 outer[i] = LLVMGetUndef(ctx->ac.i32);
2723 }
2724
2725 // LINES reversal
2726 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2727 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2728 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2729 ctx->ac.i32_1, "");
2730 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2731 } else {
2732 for (i = 0; i < outer_comps; i++) {
2733 outer[i] = out[i] =
2734 ac_lds_load(&ctx->ac, lds_outer);
2735 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2736 ctx->ac.i32_1, "");
2737 }
2738 for (i = 0; i < inner_comps; i++) {
2739 inner[i] = out[outer_comps+i] =
2740 ac_lds_load(&ctx->ac, lds_inner);
2741 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2742 ctx->ac.i32_1, "");
2743 }
2744 }
2745
2746 /* Convert the outputs to vectors for stores. */
2747 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2748 vec1 = NULL;
2749
2750 if (stride > 4)
2751 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2752
2753
2754 buffer = ctx->hs_ring_tess_factor;
2755 tf_base = ctx->tess_factor_offset;
2756 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2757 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2758 unsigned tf_offset = 0;
2759
2760 if (ctx->options->chip_class <= VI) {
2761 ac_nir_build_if(&inner_if_ctx, ctx,
2762 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2763 rel_patch_id, ctx->ac.i32_0, ""));
2764
2765 /* Store the dynamic HS control word. */
2766 ac_build_buffer_store_dword(&ctx->ac, buffer,
2767 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2768 1, ctx->ac.i32_0, tf_base,
2769 0, 1, 0, true, false);
2770 tf_offset += 4;
2771
2772 ac_nir_build_endif(&inner_if_ctx);
2773 }
2774
2775 /* Store the tessellation factors. */
2776 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2777 MIN2(stride, 4), byteoffset, tf_base,
2778 tf_offset, 1, 0, true, false);
2779 if (vec1)
2780 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2781 stride - 4, byteoffset, tf_base,
2782 16 + tf_offset, 1, 0, true, false);
2783
2784 //store to offchip for TES to read - only if TES reads them
2785 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2786 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2787 LLVMValueRef tf_inner_offset;
2788 unsigned param_outer, param_inner;
2789
2790 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2791 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2792 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2793
2794 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2795 util_next_power_of_two(outer_comps));
2796
2797 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2798 outer_comps, tf_outer_offset,
2799 ctx->oc_lds, 0, 1, 0, true, false);
2800 if (inner_comps) {
2801 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2802 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2803 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2804
2805 inner_vec = inner_comps == 1 ? inner[0] :
2806 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2807 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2808 inner_comps, tf_inner_offset,
2809 ctx->oc_lds, 0, 1, 0, true, false);
2810 }
2811 }
2812 ac_nir_build_endif(&if_ctx);
2813 }
2814
2815 static void
2816 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2817 {
2818 write_tess_factors(ctx);
2819 }
2820
2821 static bool
2822 si_export_mrt_color(struct radv_shader_context *ctx,
2823 LLVMValueRef *color, unsigned index,
2824 struct ac_export_args *args)
2825 {
2826 /* Export */
2827 si_llvm_init_export_args(ctx, color, 0xf,
2828 V_008DFC_SQ_EXP_MRT + index, args);
2829 if (!args->enabled_channels)
2830 return false; /* unnecessary NULL export */
2831
2832 return true;
2833 }
2834
2835 static void
2836 radv_export_mrt_z(struct radv_shader_context *ctx,
2837 LLVMValueRef depth, LLVMValueRef stencil,
2838 LLVMValueRef samplemask)
2839 {
2840 struct ac_export_args args;
2841
2842 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2843
2844 ac_build_export(&ctx->ac, &args);
2845 }
2846
2847 static void
2848 handle_fs_outputs_post(struct radv_shader_context *ctx)
2849 {
2850 unsigned index = 0;
2851 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2852 struct ac_export_args color_args[8];
2853
2854 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2855 LLVMValueRef values[4];
2856
2857 if (!(ctx->output_mask & (1ull << i)))
2858 continue;
2859
2860 if (i < FRAG_RESULT_DATA0)
2861 continue;
2862
2863 for (unsigned j = 0; j < 4; j++)
2864 values[j] = ac_to_float(&ctx->ac,
2865 radv_load_output(ctx, i, j));
2866
2867 bool ret = si_export_mrt_color(ctx, values,
2868 i - FRAG_RESULT_DATA0,
2869 &color_args[index]);
2870 if (ret)
2871 index++;
2872 }
2873
2874 /* Process depth, stencil, samplemask. */
2875 if (ctx->shader_info->info.ps.writes_z) {
2876 depth = ac_to_float(&ctx->ac,
2877 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
2878 }
2879 if (ctx->shader_info->info.ps.writes_stencil) {
2880 stencil = ac_to_float(&ctx->ac,
2881 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
2882 }
2883 if (ctx->shader_info->info.ps.writes_sample_mask) {
2884 samplemask = ac_to_float(&ctx->ac,
2885 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
2886 }
2887
2888 /* Set the DONE bit on last non-null color export only if Z isn't
2889 * exported.
2890 */
2891 if (index > 0 &&
2892 !ctx->shader_info->info.ps.writes_z &&
2893 !ctx->shader_info->info.ps.writes_stencil &&
2894 !ctx->shader_info->info.ps.writes_sample_mask) {
2895 unsigned last = index - 1;
2896
2897 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
2898 color_args[last].done = 1; /* DONE bit */
2899 }
2900
2901 /* Export PS outputs. */
2902 for (unsigned i = 0; i < index; i++)
2903 ac_build_export(&ctx->ac, &color_args[i]);
2904
2905 if (depth || stencil || samplemask)
2906 radv_export_mrt_z(ctx, depth, stencil, samplemask);
2907 else if (!index)
2908 ac_build_export_null(&ctx->ac);
2909 }
2910
2911 static void
2912 emit_gs_epilogue(struct radv_shader_context *ctx)
2913 {
2914 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
2915 }
2916
2917 static void
2918 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
2919 LLVMValueRef *addrs)
2920 {
2921 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2922
2923 switch (ctx->stage) {
2924 case MESA_SHADER_VERTEX:
2925 if (ctx->options->key.vs.as_ls)
2926 handle_ls_outputs_post(ctx);
2927 else if (ctx->options->key.vs.as_es)
2928 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
2929 else
2930 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
2931 ctx->options->key.vs.export_layer_id,
2932 &ctx->shader_info->vs.outinfo);
2933 break;
2934 case MESA_SHADER_FRAGMENT:
2935 handle_fs_outputs_post(ctx);
2936 break;
2937 case MESA_SHADER_GEOMETRY:
2938 emit_gs_epilogue(ctx);
2939 break;
2940 case MESA_SHADER_TESS_CTRL:
2941 handle_tcs_outputs_post(ctx);
2942 break;
2943 case MESA_SHADER_TESS_EVAL:
2944 if (ctx->options->key.tes.as_es)
2945 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
2946 else
2947 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
2948 ctx->options->key.tes.export_layer_id,
2949 &ctx->shader_info->tes.outinfo);
2950 break;
2951 default:
2952 break;
2953 }
2954 }
2955
2956 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
2957 {
2958 LLVMPassManagerRef passmgr;
2959 /* Create the pass manager */
2960 passmgr = LLVMCreateFunctionPassManagerForModule(
2961 ctx->ac.module);
2962
2963 /* This pass should eliminate all the load and store instructions */
2964 LLVMAddPromoteMemoryToRegisterPass(passmgr);
2965
2966 /* Add some optimization passes */
2967 LLVMAddScalarReplAggregatesPass(passmgr);
2968 LLVMAddLICMPass(passmgr);
2969 LLVMAddAggressiveDCEPass(passmgr);
2970 LLVMAddCFGSimplificationPass(passmgr);
2971 LLVMAddInstructionCombiningPass(passmgr);
2972
2973 /* Run the pass */
2974 LLVMInitializeFunctionPassManager(passmgr);
2975 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
2976 LLVMFinalizeFunctionPassManager(passmgr);
2977
2978 LLVMDisposeBuilder(ctx->ac.builder);
2979 LLVMDisposePassManager(passmgr);
2980
2981 ac_llvm_context_dispose(&ctx->ac);
2982 }
2983
2984 static void
2985 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
2986 {
2987 struct radv_vs_output_info *outinfo;
2988
2989 switch (ctx->stage) {
2990 case MESA_SHADER_FRAGMENT:
2991 case MESA_SHADER_COMPUTE:
2992 case MESA_SHADER_TESS_CTRL:
2993 case MESA_SHADER_GEOMETRY:
2994 return;
2995 case MESA_SHADER_VERTEX:
2996 if (ctx->options->key.vs.as_ls ||
2997 ctx->options->key.vs.as_es)
2998 return;
2999 outinfo = &ctx->shader_info->vs.outinfo;
3000 break;
3001 case MESA_SHADER_TESS_EVAL:
3002 if (ctx->options->key.vs.as_es)
3003 return;
3004 outinfo = &ctx->shader_info->tes.outinfo;
3005 break;
3006 default:
3007 unreachable("Unhandled shader type");
3008 }
3009
3010 ac_optimize_vs_outputs(&ctx->ac,
3011 ctx->main_function,
3012 outinfo->vs_output_param_offset,
3013 VARYING_SLOT_MAX,
3014 &outinfo->param_exports);
3015 }
3016
3017 static void
3018 ac_setup_rings(struct radv_shader_context *ctx)
3019 {
3020 if (ctx->options->chip_class <= VI &&
3021 (ctx->stage == MESA_SHADER_GEOMETRY ||
3022 ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
3023 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3024 : RING_ESGS_VS;
3025 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3026
3027 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3028 ctx->ring_offsets,
3029 offset);
3030 }
3031
3032 if (ctx->is_gs_copy_shader) {
3033 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
3034 }
3035 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3036 LLVMValueRef tmp;
3037 uint32_t num_entries = 64;
3038 LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size, false);
3039 LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size << 16, false);
3040 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
3041
3042 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
3043
3044 tmp = LLVMConstInt(ctx->ac.i32, num_entries, false);
3045 if (ctx->options->chip_class >= VI)
3046 tmp = LLVMBuildMul(ctx->ac.builder, gsvs_ring_stride, tmp, "");
3047 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
3048 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
3049 tmp = LLVMBuildOr(ctx->ac.builder, tmp, gsvs_ring_desc, "");
3050 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
3051 }
3052
3053 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3054 ctx->stage == MESA_SHADER_TESS_EVAL) {
3055 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3056 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3057 }
3058 }
3059
3060 static unsigned
3061 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
3062 const struct nir_shader *nir)
3063 {
3064 switch (nir->info.stage) {
3065 case MESA_SHADER_TESS_CTRL:
3066 return chip_class >= CIK ? 128 : 64;
3067 case MESA_SHADER_GEOMETRY:
3068 return chip_class >= GFX9 ? 128 : 64;
3069 case MESA_SHADER_COMPUTE:
3070 break;
3071 default:
3072 return 0;
3073 }
3074
3075 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
3076 nir->info.cs.local_size[1] *
3077 nir->info.cs.local_size[2];
3078 return max_workgroup_size;
3079 }
3080
3081 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3082 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3083 {
3084 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3085 LLVMConstInt(ctx->ac.i32, 8, false),
3086 LLVMConstInt(ctx->ac.i32, 8, false), false);
3087 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3088 ctx->ac.i32_0, "");
3089 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
3090 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
3091 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
3092 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3093 }
3094
3095 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3096 {
3097 for(int i = 5; i >= 0; --i) {
3098 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3099 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
3100 LLVMConstInt(ctx->ac.i32, 16, false), false);
3101 }
3102
3103 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3104 LLVMConstInt(ctx->ac.i32, 16, false),
3105 LLVMConstInt(ctx->ac.i32, 8, false), false);
3106 }
3107
3108
3109 static
3110 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
3111 struct nir_shader *const *shaders,
3112 int shader_count,
3113 struct radv_shader_variant_info *shader_info,
3114 const struct radv_nir_compiler_options *options)
3115 {
3116 struct radv_shader_context ctx = {0};
3117 unsigned i;
3118 ctx.options = options;
3119 ctx.shader_info = shader_info;
3120 ctx.context = LLVMContextCreate();
3121
3122 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3123 options->family);
3124 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3125 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
3126
3127 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
3128 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
3129 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
3130 LLVMDisposeTargetData(data_layout);
3131 LLVMDisposeMessage(data_layout_str);
3132
3133 enum ac_float_mode float_mode =
3134 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3135 AC_FLOAT_MODE_DEFAULT;
3136
3137 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3138
3139 memset(shader_info, 0, sizeof(*shader_info));
3140
3141 for(int i = 0; i < shader_count; ++i)
3142 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3143
3144 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3145 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3146 for (i = 0; i < AC_UD_MAX_UD; i++)
3147 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3148
3149 ctx.max_workgroup_size = 0;
3150 for (int i = 0; i < shader_count; ++i) {
3151 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3152 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3153 shaders[i]));
3154 }
3155
3156 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3157 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3158
3159 ctx.abi.inputs = &ctx.inputs[0];
3160 ctx.abi.emit_outputs = handle_shader_outputs_post;
3161 ctx.abi.emit_vertex = visit_emit_vertex;
3162 ctx.abi.load_ubo = radv_load_ubo;
3163 ctx.abi.load_ssbo = radv_load_ssbo;
3164 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3165 ctx.abi.load_resource = radv_load_resource;
3166 ctx.abi.clamp_shadow_reference = false;
3167 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9;
3168
3169 if (shader_count >= 2)
3170 ac_init_exec_full_mask(&ctx.ac);
3171
3172 if (ctx.ac.chip_class == GFX9 &&
3173 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3174 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3175
3176 for(int i = 0; i < shader_count; ++i) {
3177 ctx.stage = shaders[i]->info.stage;
3178 ctx.output_mask = 0;
3179 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3180 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3181
3182 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3183 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3184 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3185 ctx.abi.load_inputs = load_gs_input;
3186 ctx.abi.emit_primitive = visit_end_primitive;
3187 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3188 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3189 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3190 ctx.abi.load_tess_varyings = load_tcs_varyings;
3191 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3192 ctx.abi.store_tcs_outputs = store_tcs_output;
3193 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3194 if (shader_count == 1)
3195 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3196 else
3197 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3198 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3199 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3200 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3201 ctx.abi.load_tess_varyings = load_tes_input;
3202 ctx.abi.load_tess_coord = load_tess_coord;
3203 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3204 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3205 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3206 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3207 if (shader_info->info.vs.needs_instance_id) {
3208 if (ctx.options->key.vs.as_ls) {
3209 ctx.shader_info->vs.vgpr_comp_cnt =
3210 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3211 } else {
3212 ctx.shader_info->vs.vgpr_comp_cnt =
3213 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3214 }
3215 }
3216 ctx.abi.load_base_vertex = radv_load_base_vertex;
3217 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3218 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3219 ctx.abi.lookup_interp_param = lookup_interp_param;
3220 ctx.abi.load_sample_position = load_sample_position;
3221 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3222 ctx.abi.emit_kill = radv_emit_kill;
3223 }
3224
3225 if (i)
3226 ac_emit_barrier(&ctx.ac, ctx.stage);
3227
3228 nir_foreach_variable(variable, &shaders[i]->outputs)
3229 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3230
3231 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3232 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3233 shaders[i]->info.cull_distance_array_size > 4;
3234 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3235 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3236 shaders[i]->info.gs.vertices_out;
3237 }
3238
3239 ac_setup_rings(&ctx);
3240
3241 LLVMBasicBlockRef merge_block;
3242 if (shader_count >= 2) {
3243 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3244 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3245 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3246
3247 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3248 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3249 LLVMConstInt(ctx.ac.i32, 8, false), false);
3250 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3251 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3252 thread_id, count, "");
3253 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3254
3255 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3256 }
3257
3258 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3259 handle_fs_inputs(&ctx, shaders[i]);
3260 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3261 handle_vs_inputs(&ctx, shaders[i]);
3262 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3263 prepare_gs_input_vgprs(&ctx);
3264
3265 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3266
3267 if (shader_count >= 2) {
3268 LLVMBuildBr(ctx.ac.builder, merge_block);
3269 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3270 }
3271
3272 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3273 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3274 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3275 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3276 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3277 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3278 }
3279 }
3280
3281 LLVMBuildRetVoid(ctx.ac.builder);
3282
3283 if (options->dump_preoptir)
3284 ac_dump_module(ctx.ac.module);
3285
3286 ac_llvm_finalize_module(&ctx);
3287
3288 if (shader_count == 1)
3289 ac_nir_eliminate_const_vs_outputs(&ctx);
3290
3291 if (options->dump_shader) {
3292 ctx.shader_info->private_mem_vgprs =
3293 ac_count_scratch_private_memory(ctx.main_function);
3294 }
3295
3296 return ctx.ac.module;
3297 }
3298
3299 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3300 {
3301 unsigned *retval = (unsigned *)context;
3302 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3303 char *description = LLVMGetDiagInfoDescription(di);
3304
3305 if (severity == LLVMDSError) {
3306 *retval = 1;
3307 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3308 description);
3309 }
3310
3311 LLVMDisposeMessage(description);
3312 }
3313
3314 static unsigned ac_llvm_compile(LLVMModuleRef M,
3315 struct ac_shader_binary *binary,
3316 LLVMTargetMachineRef tm)
3317 {
3318 unsigned retval = 0;
3319 char *err;
3320 LLVMContextRef llvm_ctx;
3321 LLVMMemoryBufferRef out_buffer;
3322 unsigned buffer_size;
3323 const char *buffer_data;
3324 LLVMBool mem_err;
3325
3326 /* Setup Diagnostic Handler*/
3327 llvm_ctx = LLVMGetModuleContext(M);
3328
3329 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3330 &retval);
3331
3332 /* Compile IR*/
3333 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
3334 &err, &out_buffer);
3335
3336 /* Process Errors/Warnings */
3337 if (mem_err) {
3338 fprintf(stderr, "%s: %s", __FUNCTION__, err);
3339 free(err);
3340 retval = 1;
3341 goto out;
3342 }
3343
3344 /* Extract Shader Code*/
3345 buffer_size = LLVMGetBufferSize(out_buffer);
3346 buffer_data = LLVMGetBufferStart(out_buffer);
3347
3348 ac_elf_read(buffer_data, buffer_size, binary);
3349
3350 /* Clean up */
3351 LLVMDisposeMemoryBuffer(out_buffer);
3352
3353 out:
3354 return retval;
3355 }
3356
3357 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
3358 LLVMModuleRef llvm_module,
3359 struct ac_shader_binary *binary,
3360 struct ac_shader_config *config,
3361 struct radv_shader_variant_info *shader_info,
3362 gl_shader_stage stage,
3363 const struct radv_nir_compiler_options *options)
3364 {
3365 if (options->dump_shader)
3366 ac_dump_module(llvm_module);
3367
3368 memset(binary, 0, sizeof(*binary));
3369
3370 if (options->record_llvm_ir) {
3371 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3372 binary->llvm_ir_string = strdup(llvm_ir);
3373 LLVMDisposeMessage(llvm_ir);
3374 }
3375
3376 int v = ac_llvm_compile(llvm_module, binary, tm);
3377 if (v) {
3378 fprintf(stderr, "compile failed\n");
3379 }
3380
3381 if (options->dump_shader)
3382 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3383
3384 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3385
3386 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3387 LLVMDisposeModule(llvm_module);
3388 LLVMContextDispose(ctx);
3389
3390 if (stage == MESA_SHADER_FRAGMENT) {
3391 shader_info->num_input_vgprs = 0;
3392 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3393 shader_info->num_input_vgprs += 2;
3394 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3395 shader_info->num_input_vgprs += 2;
3396 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3397 shader_info->num_input_vgprs += 2;
3398 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3399 shader_info->num_input_vgprs += 3;
3400 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3401 shader_info->num_input_vgprs += 2;
3402 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3403 shader_info->num_input_vgprs += 2;
3404 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3405 shader_info->num_input_vgprs += 2;
3406 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3407 shader_info->num_input_vgprs += 1;
3408 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3409 shader_info->num_input_vgprs += 1;
3410 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3411 shader_info->num_input_vgprs += 1;
3412 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3413 shader_info->num_input_vgprs += 1;
3414 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3415 shader_info->num_input_vgprs += 1;
3416 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3417 shader_info->num_input_vgprs += 1;
3418 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3419 shader_info->num_input_vgprs += 1;
3420 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3421 shader_info->num_input_vgprs += 1;
3422 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3423 shader_info->num_input_vgprs += 1;
3424 }
3425 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3426
3427 /* +3 for scratch wave offset and VCC */
3428 config->num_sgprs = MAX2(config->num_sgprs,
3429 shader_info->num_input_sgprs + 3);
3430
3431 /* Enable 64-bit and 16-bit denormals, because there is no performance
3432 * cost.
3433 *
3434 * If denormals are enabled, all floating-point output modifiers are
3435 * ignored.
3436 *
3437 * Don't enable denormals for 32-bit floats, because:
3438 * - Floating-point output modifiers would be ignored by the hw.
3439 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3440 * have to stop using those.
3441 * - SI & CI would be very slow.
3442 */
3443 config->float_mode |= V_00B028_FP_64_DENORMS;
3444 }
3445
3446 static void
3447 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3448 {
3449 switch (nir->info.stage) {
3450 case MESA_SHADER_COMPUTE:
3451 for (int i = 0; i < 3; ++i)
3452 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3453 break;
3454 case MESA_SHADER_FRAGMENT:
3455 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3456 break;
3457 case MESA_SHADER_GEOMETRY:
3458 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3459 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3460 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3461 shader_info->gs.invocations = nir->info.gs.invocations;
3462 break;
3463 case MESA_SHADER_TESS_EVAL:
3464 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3465 shader_info->tes.spacing = nir->info.tess.spacing;
3466 shader_info->tes.ccw = nir->info.tess.ccw;
3467 shader_info->tes.point_mode = nir->info.tess.point_mode;
3468 shader_info->tes.as_es = options->key.tes.as_es;
3469 break;
3470 case MESA_SHADER_TESS_CTRL:
3471 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3472 break;
3473 case MESA_SHADER_VERTEX:
3474 shader_info->vs.as_es = options->key.vs.as_es;
3475 shader_info->vs.as_ls = options->key.vs.as_ls;
3476 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3477 if (options->key.vs.as_ls)
3478 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3479 break;
3480 default:
3481 break;
3482 }
3483 }
3484
3485 void
3486 radv_compile_nir_shader(LLVMTargetMachineRef tm,
3487 struct ac_shader_binary *binary,
3488 struct ac_shader_config *config,
3489 struct radv_shader_variant_info *shader_info,
3490 struct nir_shader *const *nir,
3491 int nir_count,
3492 const struct radv_nir_compiler_options *options)
3493 {
3494
3495 LLVMModuleRef llvm_module;
3496
3497 llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
3498 options);
3499
3500 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
3501 nir[0]->info.stage, options);
3502
3503 for (int i = 0; i < nir_count; ++i)
3504 ac_fill_shader_info(shader_info, nir[i], options);
3505
3506 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3507 if (options->chip_class == GFX9) {
3508 if (nir_count == 2 &&
3509 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3510 shader_info->gs.es_type = nir[0]->info.stage;
3511 }
3512 }
3513 }
3514
3515 static void
3516 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3517 {
3518 LLVMValueRef vtx_offset =
3519 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3520 LLVMConstInt(ctx->ac.i32, 4, false), "");
3521 int idx = 0;
3522
3523 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3524 int length = 4;
3525 int slot = idx;
3526 int slot_inc = 1;
3527 if (!(ctx->output_mask & (1ull << i)))
3528 continue;
3529
3530 if (i == VARYING_SLOT_CLIP_DIST0) {
3531 /* unpack clip and cull from a single set of slots */
3532 length = ctx->num_output_clips + ctx->num_output_culls;
3533 if (length > 4)
3534 slot_inc = 2;
3535 }
3536
3537 for (unsigned j = 0; j < length; j++) {
3538 LLVMValueRef value, soffset;
3539
3540 soffset = LLVMConstInt(ctx->ac.i32,
3541 (slot * 4 + j) *
3542 ctx->gs_max_out_vertices * 16 * 4, false);
3543
3544 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3545 1, ctx->ac.i32_0,
3546 vtx_offset, soffset,
3547 0, 1, 1, true, false);
3548
3549 LLVMBuildStore(ctx->ac.builder,
3550 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3551 }
3552 idx += slot_inc;
3553 }
3554 handle_vs_outputs_post(ctx, false, false, &ctx->shader_info->vs.outinfo);
3555 }
3556
3557 void
3558 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
3559 struct nir_shader *geom_shader,
3560 struct ac_shader_binary *binary,
3561 struct ac_shader_config *config,
3562 struct radv_shader_variant_info *shader_info,
3563 const struct radv_nir_compiler_options *options)
3564 {
3565 struct radv_shader_context ctx = {0};
3566 ctx.context = LLVMContextCreate();
3567 ctx.options = options;
3568 ctx.shader_info = shader_info;
3569
3570 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3571 options->family);
3572 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3573
3574 ctx.is_gs_copy_shader = true;
3575 LLVMSetTarget(ctx.ac.module, "amdgcn--");
3576
3577 enum ac_float_mode float_mode =
3578 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3579 AC_FLOAT_MODE_DEFAULT;
3580
3581 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3582 ctx.stage = MESA_SHADER_VERTEX;
3583
3584 radv_nir_shader_info_pass(geom_shader, options, &shader_info->info);
3585
3586 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3587
3588 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3589 ac_setup_rings(&ctx);
3590
3591 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3592 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3593
3594 nir_foreach_variable(variable, &geom_shader->outputs) {
3595 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3596 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3597 variable, MESA_SHADER_VERTEX);
3598 }
3599
3600 ac_gs_copy_shader_emit(&ctx);
3601
3602 LLVMBuildRetVoid(ctx.ac.builder);
3603
3604 ac_llvm_finalize_module(&ctx);
3605
3606 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
3607 MESA_SHADER_VERTEX, options);
3608 }