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amd: remove support for LLVM 6.0
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "nir/nir.h"
32
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
37
38 #include "sid.h"
39 #include "gfx9d.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct radv_shader_context {
50 struct ac_llvm_context ac;
51 const struct radv_nir_compiler_options *options;
52 struct radv_shader_variant_info *shader_info;
53 struct ac_shader_abi abi;
54
55 unsigned max_workgroup_size;
56 LLVMContextRef context;
57 LLVMValueRef main_function;
58
59 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
60 LLVMValueRef ring_offsets;
61
62 LLVMValueRef vertex_buffers;
63 LLVMValueRef rel_auto_id;
64 LLVMValueRef vs_prim_id;
65 LLVMValueRef es2gs_offset;
66
67 LLVMValueRef oc_lds;
68 LLVMValueRef merged_wave_info;
69 LLVMValueRef tess_factor_offset;
70 LLVMValueRef tes_rel_patch_id;
71 LLVMValueRef tes_u;
72 LLVMValueRef tes_v;
73
74 LLVMValueRef gs2vs_offset;
75 LLVMValueRef gs_wave_id;
76 LLVMValueRef gs_vtx_offset[6];
77
78 LLVMValueRef esgs_ring;
79 LLVMValueRef gsvs_ring[4];
80 LLVMValueRef hs_ring_tess_offchip;
81 LLVMValueRef hs_ring_tess_factor;
82
83 LLVMValueRef persp_sample, persp_center, persp_centroid;
84 LLVMValueRef linear_sample, linear_center, linear_centroid;
85
86 /* Streamout */
87 LLVMValueRef streamout_buffers;
88 LLVMValueRef streamout_write_idx;
89 LLVMValueRef streamout_config;
90 LLVMValueRef streamout_offset[4];
91
92 gl_shader_stage stage;
93
94 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
95
96 uint64_t input_mask;
97 uint64_t output_mask;
98
99 bool is_gs_copy_shader;
100 LLVMValueRef gs_next_vertex[4];
101 unsigned gs_max_out_vertices;
102
103 unsigned tes_primitive_mode;
104
105 uint32_t tcs_patch_outputs_read;
106 uint64_t tcs_outputs_read;
107 uint32_t tcs_vertices_per_patch;
108 uint32_t tcs_num_inputs;
109 uint32_t tcs_num_patches;
110 uint32_t max_gsvs_emit_size;
111 uint32_t gsvs_vertex_size;
112 };
113
114 enum radeon_llvm_calling_convention {
115 RADEON_LLVM_AMDGPU_VS = 87,
116 RADEON_LLVM_AMDGPU_GS = 88,
117 RADEON_LLVM_AMDGPU_PS = 89,
118 RADEON_LLVM_AMDGPU_CS = 90,
119 RADEON_LLVM_AMDGPU_HS = 93,
120 };
121
122 static inline struct radv_shader_context *
123 radv_shader_context_from_abi(struct ac_shader_abi *abi)
124 {
125 struct radv_shader_context *ctx = NULL;
126 return container_of(abi, ctx, abi);
127 }
128
129 struct ac_build_if_state
130 {
131 struct radv_shader_context *ctx;
132 LLVMValueRef condition;
133 LLVMBasicBlockRef entry_block;
134 LLVMBasicBlockRef true_block;
135 LLVMBasicBlockRef false_block;
136 LLVMBasicBlockRef merge_block;
137 };
138
139 static LLVMBasicBlockRef
140 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
141 {
142 LLVMBasicBlockRef current_block;
143 LLVMBasicBlockRef next_block;
144 LLVMBasicBlockRef new_block;
145
146 /* get current basic block */
147 current_block = LLVMGetInsertBlock(ctx->ac.builder);
148
149 /* chqeck if there's another block after this one */
150 next_block = LLVMGetNextBasicBlock(current_block);
151 if (next_block) {
152 /* insert the new block before the next block */
153 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
154 }
155 else {
156 /* append new block after current block */
157 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
158 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
159 }
160 return new_block;
161 }
162
163 static void
164 ac_nir_build_if(struct ac_build_if_state *ifthen,
165 struct radv_shader_context *ctx,
166 LLVMValueRef condition)
167 {
168 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
169
170 memset(ifthen, 0, sizeof *ifthen);
171 ifthen->ctx = ctx;
172 ifthen->condition = condition;
173 ifthen->entry_block = block;
174
175 /* create endif/merge basic block for the phi functions */
176 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
177
178 /* create/insert true_block before merge_block */
179 ifthen->true_block =
180 LLVMInsertBasicBlockInContext(ctx->context,
181 ifthen->merge_block,
182 "if-true-block");
183
184 /* successive code goes into the true block */
185 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
186 }
187
188 /**
189 * End a conditional.
190 */
191 static void
192 ac_nir_build_endif(struct ac_build_if_state *ifthen)
193 {
194 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
195
196 /* Insert branch to the merge block from current block */
197 LLVMBuildBr(builder, ifthen->merge_block);
198
199 /*
200 * Now patch in the various branch instructions.
201 */
202
203 /* Insert the conditional branch instruction at the end of entry_block */
204 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
205 if (ifthen->false_block) {
206 /* we have an else clause */
207 LLVMBuildCondBr(builder, ifthen->condition,
208 ifthen->true_block, ifthen->false_block);
209 }
210 else {
211 /* no else clause */
212 LLVMBuildCondBr(builder, ifthen->condition,
213 ifthen->true_block, ifthen->merge_block);
214 }
215
216 /* Resume building code at end of the ifthen->merge_block */
217 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
218 }
219
220
221 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
222 {
223 switch (ctx->stage) {
224 case MESA_SHADER_TESS_CTRL:
225 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
226 case MESA_SHADER_TESS_EVAL:
227 return ctx->tes_rel_patch_id;
228 break;
229 default:
230 unreachable("Illegal stage");
231 }
232 }
233
234 static unsigned
235 get_tcs_num_patches(struct radv_shader_context *ctx)
236 {
237 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
238 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
239 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
240 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
241 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
242 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
243 uint32_t output_vertex_size = num_tcs_outputs * 16;
244 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
245 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
246 unsigned num_patches;
247 unsigned hardware_lds_size;
248
249 /* Ensure that we only need one wave per SIMD so we don't need to check
250 * resource usage. Also ensures that the number of tcs in and out
251 * vertices per threadgroup are at most 256.
252 */
253 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
254 /* Make sure that the data fits in LDS. This assumes the shaders only
255 * use LDS for the inputs and outputs.
256 */
257 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
258 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
259 /* Make sure the output data fits in the offchip buffer */
260 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
261 /* Not necessary for correctness, but improves performance. The
262 * specific value is taken from the proprietary driver.
263 */
264 num_patches = MIN2(num_patches, 40);
265
266 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
267 if (ctx->options->chip_class == SI) {
268 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
269 num_patches = MIN2(num_patches, one_wave);
270 }
271 return num_patches;
272 }
273
274 static unsigned
275 calculate_tess_lds_size(struct radv_shader_context *ctx)
276 {
277 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
278 unsigned num_tcs_output_cp;
279 unsigned num_tcs_outputs, num_tcs_patch_outputs;
280 unsigned input_vertex_size, output_vertex_size;
281 unsigned input_patch_size, output_patch_size;
282 unsigned pervertex_output_patch_size;
283 unsigned output_patch0_offset;
284 unsigned num_patches;
285 unsigned lds_size;
286
287 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
288 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
289 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
290
291 input_vertex_size = ctx->tcs_num_inputs * 16;
292 output_vertex_size = num_tcs_outputs * 16;
293
294 input_patch_size = num_tcs_input_cp * input_vertex_size;
295
296 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
297 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
298
299 num_patches = ctx->tcs_num_patches;
300 output_patch0_offset = input_patch_size * num_patches;
301
302 lds_size = output_patch0_offset + output_patch_size * num_patches;
303 return lds_size;
304 }
305
306 /* Tessellation shaders pass outputs to the next shader using LDS.
307 *
308 * LS outputs = TCS inputs
309 * TCS outputs = TES inputs
310 *
311 * The LDS layout is:
312 * - TCS inputs for patch 0
313 * - TCS inputs for patch 1
314 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
315 * - ...
316 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
317 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
318 * - TCS outputs for patch 1
319 * - Per-patch TCS outputs for patch 1
320 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
321 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
322 * - ...
323 *
324 * All three shaders VS(LS), TCS, TES share the same LDS space.
325 */
326 static LLVMValueRef
327 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
328 {
329 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
330 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
331 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
332
333 input_patch_size /= 4;
334 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
335 }
336
337 static LLVMValueRef
338 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
339 {
340 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
341 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
342 uint32_t output_vertex_size = num_tcs_outputs * 16;
343 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
344 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
345 output_patch_size /= 4;
346 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
347 }
348
349 static LLVMValueRef
350 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
351 {
352 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
353 uint32_t output_vertex_size = num_tcs_outputs * 16;
354 output_vertex_size /= 4;
355 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
356 }
357
358 static LLVMValueRef
359 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
360 {
361 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
362 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
363 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
364 uint32_t output_patch0_offset = input_patch_size;
365 unsigned num_patches = ctx->tcs_num_patches;
366
367 output_patch0_offset *= num_patches;
368 output_patch0_offset /= 4;
369 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
370 }
371
372 static LLVMValueRef
373 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
374 {
375 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
376 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
377 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
378 uint32_t output_patch0_offset = input_patch_size;
379
380 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
381 uint32_t output_vertex_size = num_tcs_outputs * 16;
382 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
383 unsigned num_patches = ctx->tcs_num_patches;
384
385 output_patch0_offset *= num_patches;
386 output_patch0_offset += pervertex_output_patch_size;
387 output_patch0_offset /= 4;
388 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
389 }
390
391 static LLVMValueRef
392 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
393 {
394 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
395 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
396
397 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
398 }
399
400 static LLVMValueRef
401 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
402 {
403 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
404 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
405 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
406
407 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
408 patch0_offset);
409 }
410
411 static LLVMValueRef
412 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
413 {
414 LLVMValueRef patch0_patch_data_offset =
415 get_tcs_out_patch0_patch_data_offset(ctx);
416 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
417 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
418
419 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
420 patch0_patch_data_offset);
421 }
422
423 #define MAX_ARGS 64
424 struct arg_info {
425 LLVMTypeRef types[MAX_ARGS];
426 LLVMValueRef *assign[MAX_ARGS];
427 unsigned array_params_mask;
428 uint8_t count;
429 uint8_t sgpr_count;
430 uint8_t num_sgprs_used;
431 uint8_t num_vgprs_used;
432 };
433
434 enum ac_arg_regfile {
435 ARG_SGPR,
436 ARG_VGPR,
437 };
438
439 static void
440 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
441 LLVMValueRef *param_ptr)
442 {
443 assert(info->count < MAX_ARGS);
444
445 info->assign[info->count] = param_ptr;
446 info->types[info->count] = type;
447 info->count++;
448
449 if (regfile == ARG_SGPR) {
450 info->num_sgprs_used += ac_get_type_size(type) / 4;
451 info->sgpr_count++;
452 } else {
453 assert(regfile == ARG_VGPR);
454 info->num_vgprs_used += ac_get_type_size(type) / 4;
455 }
456 }
457
458 static inline void
459 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
460 {
461 info->array_params_mask |= (1 << info->count);
462 add_arg(info, ARG_SGPR, type, param_ptr);
463 }
464
465 static void assign_arguments(LLVMValueRef main_function,
466 struct arg_info *info)
467 {
468 unsigned i;
469 for (i = 0; i < info->count; i++) {
470 if (info->assign[i])
471 *info->assign[i] = LLVMGetParam(main_function, i);
472 }
473 }
474
475 static LLVMValueRef
476 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
477 LLVMBuilderRef builder, LLVMTypeRef *return_types,
478 unsigned num_return_elems,
479 struct arg_info *args,
480 unsigned max_workgroup_size,
481 const struct radv_nir_compiler_options *options)
482 {
483 LLVMTypeRef main_function_type, ret_type;
484 LLVMBasicBlockRef main_function_body;
485
486 if (num_return_elems)
487 ret_type = LLVMStructTypeInContext(ctx, return_types,
488 num_return_elems, true);
489 else
490 ret_type = LLVMVoidTypeInContext(ctx);
491
492 /* Setup the function */
493 main_function_type =
494 LLVMFunctionType(ret_type, args->types, args->count, 0);
495 LLVMValueRef main_function =
496 LLVMAddFunction(module, "main", main_function_type);
497 main_function_body =
498 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
499 LLVMPositionBuilderAtEnd(builder, main_function_body);
500
501 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
502 for (unsigned i = 0; i < args->sgpr_count; ++i) {
503 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
504
505 if (args->array_params_mask & (1 << i)) {
506 LLVMValueRef P = LLVMGetParam(main_function, i);
507 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
508 ac_add_attr_dereferenceable(P, UINT64_MAX);
509 }
510 }
511
512 if (options->address32_hi) {
513 ac_llvm_add_target_dep_function_attr(main_function,
514 "amdgpu-32bit-address-high-bits",
515 options->address32_hi);
516 }
517
518 if (max_workgroup_size) {
519 ac_llvm_add_target_dep_function_attr(main_function,
520 "amdgpu-max-work-group-size",
521 max_workgroup_size);
522 }
523 if (options->unsafe_math) {
524 /* These were copied from some LLVM test. */
525 LLVMAddTargetDependentFunctionAttr(main_function,
526 "less-precise-fpmad",
527 "true");
528 LLVMAddTargetDependentFunctionAttr(main_function,
529 "no-infs-fp-math",
530 "true");
531 LLVMAddTargetDependentFunctionAttr(main_function,
532 "no-nans-fp-math",
533 "true");
534 LLVMAddTargetDependentFunctionAttr(main_function,
535 "unsafe-fp-math",
536 "true");
537 LLVMAddTargetDependentFunctionAttr(main_function,
538 "no-signed-zeros-fp-math",
539 "true");
540 }
541 return main_function;
542 }
543
544
545 static void
546 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx,
547 uint8_t num_sgprs, bool indirect)
548 {
549 ud_info->sgpr_idx = *sgpr_idx;
550 ud_info->num_sgprs = num_sgprs;
551 ud_info->indirect = indirect;
552 *sgpr_idx += num_sgprs;
553 }
554
555 static void
556 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
557 uint8_t num_sgprs)
558 {
559 struct radv_userdata_info *ud_info =
560 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
561 assert(ud_info);
562
563 set_loc(ud_info, sgpr_idx, num_sgprs, false);
564 }
565
566 static void
567 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
568 {
569 bool use_32bit_pointers = idx != AC_UD_SCRATCH_RING_OFFSETS;
570
571 set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
572 }
573
574 static void
575 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
576 bool indirect)
577 {
578 struct radv_userdata_locations *locs =
579 &ctx->shader_info->user_sgprs_locs;
580 struct radv_userdata_info *ud_info = &locs->descriptor_sets[idx];
581 assert(ud_info);
582
583 set_loc(ud_info, sgpr_idx, 1, indirect);
584
585 if (!indirect)
586 locs->descriptor_sets_enabled |= 1 << idx;
587 }
588
589 struct user_sgpr_info {
590 bool need_ring_offsets;
591 bool indirect_all_descriptor_sets;
592 };
593
594 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
595 gl_shader_stage stage)
596 {
597 switch (stage) {
598 case MESA_SHADER_VERTEX:
599 if (ctx->shader_info->info.needs_multiview_view_index ||
600 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
601 return true;
602 break;
603 case MESA_SHADER_TESS_EVAL:
604 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
605 return true;
606 break;
607 case MESA_SHADER_GEOMETRY:
608 case MESA_SHADER_TESS_CTRL:
609 if (ctx->shader_info->info.needs_multiview_view_index)
610 return true;
611 break;
612 default:
613 break;
614 }
615 return false;
616 }
617
618 static uint8_t
619 count_vs_user_sgprs(struct radv_shader_context *ctx)
620 {
621 uint8_t count = 0;
622
623 if (ctx->shader_info->info.vs.has_vertex_buffers)
624 count++;
625 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
626
627 return count;
628 }
629
630 static void allocate_user_sgprs(struct radv_shader_context *ctx,
631 gl_shader_stage stage,
632 bool has_previous_stage,
633 gl_shader_stage previous_stage,
634 bool needs_view_index,
635 struct user_sgpr_info *user_sgpr_info)
636 {
637 uint8_t user_sgpr_count = 0;
638
639 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
640
641 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
642 if (stage == MESA_SHADER_GEOMETRY ||
643 stage == MESA_SHADER_VERTEX ||
644 stage == MESA_SHADER_TESS_CTRL ||
645 stage == MESA_SHADER_TESS_EVAL ||
646 ctx->is_gs_copy_shader)
647 user_sgpr_info->need_ring_offsets = true;
648
649 if (stage == MESA_SHADER_FRAGMENT &&
650 ctx->shader_info->info.ps.needs_sample_positions)
651 user_sgpr_info->need_ring_offsets = true;
652
653 /* 2 user sgprs will nearly always be allocated for scratch/rings */
654 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
655 user_sgpr_count += 2;
656 }
657
658 switch (stage) {
659 case MESA_SHADER_COMPUTE:
660 if (ctx->shader_info->info.cs.uses_grid_size)
661 user_sgpr_count += 3;
662 break;
663 case MESA_SHADER_FRAGMENT:
664 user_sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
665 break;
666 case MESA_SHADER_VERTEX:
667 if (!ctx->is_gs_copy_shader)
668 user_sgpr_count += count_vs_user_sgprs(ctx);
669 break;
670 case MESA_SHADER_TESS_CTRL:
671 if (has_previous_stage) {
672 if (previous_stage == MESA_SHADER_VERTEX)
673 user_sgpr_count += count_vs_user_sgprs(ctx);
674 }
675 break;
676 case MESA_SHADER_TESS_EVAL:
677 break;
678 case MESA_SHADER_GEOMETRY:
679 if (has_previous_stage) {
680 if (previous_stage == MESA_SHADER_VERTEX) {
681 user_sgpr_count += count_vs_user_sgprs(ctx);
682 }
683 }
684 break;
685 default:
686 break;
687 }
688
689 if (needs_view_index)
690 user_sgpr_count++;
691
692 if (ctx->shader_info->info.loads_push_constants)
693 user_sgpr_count++;
694
695 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
696 uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
697 uint32_t num_desc_set =
698 util_bitcount(ctx->shader_info->info.desc_set_used_mask);
699
700 if (remaining_sgprs < num_desc_set) {
701 user_sgpr_info->indirect_all_descriptor_sets = true;
702 }
703 }
704
705 static void
706 declare_global_input_sgprs(struct radv_shader_context *ctx,
707 gl_shader_stage stage,
708 bool has_previous_stage,
709 gl_shader_stage previous_stage,
710 const struct user_sgpr_info *user_sgpr_info,
711 struct arg_info *args,
712 LLVMValueRef *desc_sets)
713 {
714 LLVMTypeRef type = ac_array_in_const32_addr_space(ctx->ac.i8);
715 unsigned num_sets = ctx->options->layout ?
716 ctx->options->layout->num_sets : 0;
717 unsigned stage_mask = 1 << stage;
718
719 if (has_previous_stage)
720 stage_mask |= 1 << previous_stage;
721
722 /* 1 for each descriptor set */
723 if (!user_sgpr_info->indirect_all_descriptor_sets) {
724 for (unsigned i = 0; i < num_sets; ++i) {
725 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
726 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
727 add_array_arg(args, type,
728 &ctx->descriptor_sets[i]);
729 }
730 }
731 } else {
732 add_array_arg(args, ac_array_in_const32_addr_space(type), desc_sets);
733 }
734
735 if (ctx->shader_info->info.loads_push_constants) {
736 /* 1 for push constants and dynamic descriptors */
737 add_array_arg(args, type, &ctx->abi.push_constants);
738 }
739
740 if (ctx->shader_info->info.so.num_outputs) {
741 add_arg(args, ARG_SGPR,
742 ac_array_in_const32_addr_space(ctx->ac.v4i32),
743 &ctx->streamout_buffers);
744 }
745 }
746
747 static void
748 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
749 gl_shader_stage stage,
750 bool has_previous_stage,
751 gl_shader_stage previous_stage,
752 struct arg_info *args)
753 {
754 if (!ctx->is_gs_copy_shader &&
755 (stage == MESA_SHADER_VERTEX ||
756 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
757 if (ctx->shader_info->info.vs.has_vertex_buffers) {
758 add_arg(args, ARG_SGPR,
759 ac_array_in_const32_addr_space(ctx->ac.v4i32),
760 &ctx->vertex_buffers);
761 }
762 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
763 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
764 if (ctx->shader_info->info.vs.needs_draw_id) {
765 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
766 }
767 }
768 }
769
770 static void
771 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
772 {
773 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
774 if (!ctx->is_gs_copy_shader) {
775 if (ctx->options->key.vs.as_ls) {
776 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
777 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
778 } else {
779 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
780 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
781 }
782 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
783 }
784 }
785
786 static void
787 declare_streamout_sgprs(struct radv_shader_context *ctx, gl_shader_stage stage,
788 struct arg_info *args)
789 {
790 int i;
791
792 /* Streamout SGPRs. */
793 if (ctx->shader_info->info.so.num_outputs) {
794 assert(stage == MESA_SHADER_VERTEX ||
795 stage == MESA_SHADER_TESS_EVAL);
796
797 if (stage != MESA_SHADER_TESS_EVAL) {
798 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_config);
799 } else {
800 args->assign[args->count - 1] = &ctx->streamout_config;
801 args->types[args->count - 1] = ctx->ac.i32;
802 }
803
804 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_write_idx);
805 }
806
807 /* A streamout buffer offset is loaded if the stride is non-zero. */
808 for (i = 0; i < 4; i++) {
809 if (!ctx->shader_info->info.so.strides[i])
810 continue;
811
812 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_offset[i]);
813 }
814 }
815
816 static void
817 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
818 {
819 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
820 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
821 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
822 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
823 }
824
825 static void
826 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
827 bool has_previous_stage, gl_shader_stage previous_stage,
828 const struct user_sgpr_info *user_sgpr_info,
829 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
830 {
831 unsigned num_sets = ctx->options->layout ?
832 ctx->options->layout->num_sets : 0;
833 unsigned stage_mask = 1 << stage;
834
835 if (has_previous_stage)
836 stage_mask |= 1 << previous_stage;
837
838 if (!user_sgpr_info->indirect_all_descriptor_sets) {
839 for (unsigned i = 0; i < num_sets; ++i) {
840 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
841 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
842 set_loc_desc(ctx, i, user_sgpr_idx, false);
843 } else
844 ctx->descriptor_sets[i] = NULL;
845 }
846 } else {
847 set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
848 user_sgpr_idx);
849
850 for (unsigned i = 0; i < num_sets; ++i) {
851 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
852 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
853 ctx->descriptor_sets[i] =
854 ac_build_load_to_sgpr(&ctx->ac,
855 desc_sets,
856 LLVMConstInt(ctx->ac.i32, i, false));
857
858 } else
859 ctx->descriptor_sets[i] = NULL;
860 }
861 ctx->shader_info->need_indirect_descriptor_sets = true;
862 }
863
864 if (ctx->shader_info->info.loads_push_constants) {
865 set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
866 }
867
868 if (ctx->streamout_buffers) {
869 set_loc_shader_ptr(ctx, AC_UD_STREAMOUT_BUFFERS,
870 user_sgpr_idx);
871 }
872 }
873
874 static void
875 set_vs_specific_input_locs(struct radv_shader_context *ctx,
876 gl_shader_stage stage, bool has_previous_stage,
877 gl_shader_stage previous_stage,
878 uint8_t *user_sgpr_idx)
879 {
880 if (!ctx->is_gs_copy_shader &&
881 (stage == MESA_SHADER_VERTEX ||
882 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
883 if (ctx->shader_info->info.vs.has_vertex_buffers) {
884 set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
885 user_sgpr_idx);
886 }
887
888 unsigned vs_num = 2;
889 if (ctx->shader_info->info.vs.needs_draw_id)
890 vs_num++;
891
892 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
893 user_sgpr_idx, vs_num);
894 }
895 }
896
897 static void set_llvm_calling_convention(LLVMValueRef func,
898 gl_shader_stage stage)
899 {
900 enum radeon_llvm_calling_convention calling_conv;
901
902 switch (stage) {
903 case MESA_SHADER_VERTEX:
904 case MESA_SHADER_TESS_EVAL:
905 calling_conv = RADEON_LLVM_AMDGPU_VS;
906 break;
907 case MESA_SHADER_GEOMETRY:
908 calling_conv = RADEON_LLVM_AMDGPU_GS;
909 break;
910 case MESA_SHADER_TESS_CTRL:
911 calling_conv = RADEON_LLVM_AMDGPU_HS;
912 break;
913 case MESA_SHADER_FRAGMENT:
914 calling_conv = RADEON_LLVM_AMDGPU_PS;
915 break;
916 case MESA_SHADER_COMPUTE:
917 calling_conv = RADEON_LLVM_AMDGPU_CS;
918 break;
919 default:
920 unreachable("Unhandle shader type");
921 }
922
923 LLVMSetFunctionCallConv(func, calling_conv);
924 }
925
926 static void create_function(struct radv_shader_context *ctx,
927 gl_shader_stage stage,
928 bool has_previous_stage,
929 gl_shader_stage previous_stage)
930 {
931 uint8_t user_sgpr_idx;
932 struct user_sgpr_info user_sgpr_info;
933 struct arg_info args = {};
934 LLVMValueRef desc_sets;
935 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
936 allocate_user_sgprs(ctx, stage, has_previous_stage,
937 previous_stage, needs_view_index, &user_sgpr_info);
938
939 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
940 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
941 &ctx->ring_offsets);
942 }
943
944 switch (stage) {
945 case MESA_SHADER_COMPUTE:
946 declare_global_input_sgprs(ctx, stage, has_previous_stage,
947 previous_stage, &user_sgpr_info,
948 &args, &desc_sets);
949
950 if (ctx->shader_info->info.cs.uses_grid_size) {
951 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
952 &ctx->abi.num_work_groups);
953 }
954
955 for (int i = 0; i < 3; i++) {
956 ctx->abi.workgroup_ids[i] = NULL;
957 if (ctx->shader_info->info.cs.uses_block_id[i]) {
958 add_arg(&args, ARG_SGPR, ctx->ac.i32,
959 &ctx->abi.workgroup_ids[i]);
960 }
961 }
962
963 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
964 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
965 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
966 &ctx->abi.local_invocation_ids);
967 break;
968 case MESA_SHADER_VERTEX:
969 declare_global_input_sgprs(ctx, stage, has_previous_stage,
970 previous_stage, &user_sgpr_info,
971 &args, &desc_sets);
972 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
973 previous_stage, &args);
974
975 if (needs_view_index)
976 add_arg(&args, ARG_SGPR, ctx->ac.i32,
977 &ctx->abi.view_index);
978 if (ctx->options->key.vs.as_es) {
979 add_arg(&args, ARG_SGPR, ctx->ac.i32,
980 &ctx->es2gs_offset);
981 } else if (ctx->options->key.vs.as_ls) {
982 /* no extra parameters */
983 } else {
984 declare_streamout_sgprs(ctx, stage, &args);
985 }
986
987 declare_vs_input_vgprs(ctx, &args);
988 break;
989 case MESA_SHADER_TESS_CTRL:
990 if (has_previous_stage) {
991 // First 6 system regs
992 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
993 add_arg(&args, ARG_SGPR, ctx->ac.i32,
994 &ctx->merged_wave_info);
995 add_arg(&args, ARG_SGPR, ctx->ac.i32,
996 &ctx->tess_factor_offset);
997
998 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
999 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1000 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1001
1002 declare_global_input_sgprs(ctx, stage,
1003 has_previous_stage,
1004 previous_stage,
1005 &user_sgpr_info, &args,
1006 &desc_sets);
1007 declare_vs_specific_input_sgprs(ctx, stage,
1008 has_previous_stage,
1009 previous_stage, &args);
1010
1011 if (needs_view_index)
1012 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1013 &ctx->abi.view_index);
1014
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1016 &ctx->abi.tcs_patch_id);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1018 &ctx->abi.tcs_rel_ids);
1019
1020 declare_vs_input_vgprs(ctx, &args);
1021 } else {
1022 declare_global_input_sgprs(ctx, stage,
1023 has_previous_stage,
1024 previous_stage,
1025 &user_sgpr_info, &args,
1026 &desc_sets);
1027
1028 if (needs_view_index)
1029 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1030 &ctx->abi.view_index);
1031
1032 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1033 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1034 &ctx->tess_factor_offset);
1035 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1036 &ctx->abi.tcs_patch_id);
1037 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1038 &ctx->abi.tcs_rel_ids);
1039 }
1040 break;
1041 case MESA_SHADER_TESS_EVAL:
1042 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1043 previous_stage, &user_sgpr_info,
1044 &args, &desc_sets);
1045
1046 if (needs_view_index)
1047 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1048 &ctx->abi.view_index);
1049
1050 if (ctx->options->key.tes.as_es) {
1051 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1052 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1053 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1054 &ctx->es2gs_offset);
1055 } else {
1056 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1057 declare_streamout_sgprs(ctx, stage, &args);
1058 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1059 }
1060 declare_tes_input_vgprs(ctx, &args);
1061 break;
1062 case MESA_SHADER_GEOMETRY:
1063 if (has_previous_stage) {
1064 // First 6 system regs
1065 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1066 &ctx->gs2vs_offset);
1067 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1068 &ctx->merged_wave_info);
1069 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1070
1071 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1072 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1073 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1074
1075 declare_global_input_sgprs(ctx, stage,
1076 has_previous_stage,
1077 previous_stage,
1078 &user_sgpr_info, &args,
1079 &desc_sets);
1080
1081 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1082 declare_vs_specific_input_sgprs(ctx, stage,
1083 has_previous_stage,
1084 previous_stage,
1085 &args);
1086 }
1087
1088 if (needs_view_index)
1089 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1090 &ctx->abi.view_index);
1091
1092 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1093 &ctx->gs_vtx_offset[0]);
1094 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1095 &ctx->gs_vtx_offset[2]);
1096 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1097 &ctx->abi.gs_prim_id);
1098 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1099 &ctx->abi.gs_invocation_id);
1100 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1101 &ctx->gs_vtx_offset[4]);
1102
1103 if (previous_stage == MESA_SHADER_VERTEX) {
1104 declare_vs_input_vgprs(ctx, &args);
1105 } else {
1106 declare_tes_input_vgprs(ctx, &args);
1107 }
1108 } else {
1109 declare_global_input_sgprs(ctx, stage,
1110 has_previous_stage,
1111 previous_stage,
1112 &user_sgpr_info, &args,
1113 &desc_sets);
1114
1115 if (needs_view_index)
1116 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1117 &ctx->abi.view_index);
1118
1119 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1120 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1121 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1122 &ctx->gs_vtx_offset[0]);
1123 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1124 &ctx->gs_vtx_offset[1]);
1125 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1126 &ctx->abi.gs_prim_id);
1127 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1128 &ctx->gs_vtx_offset[2]);
1129 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1130 &ctx->gs_vtx_offset[3]);
1131 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1132 &ctx->gs_vtx_offset[4]);
1133 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1134 &ctx->gs_vtx_offset[5]);
1135 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1136 &ctx->abi.gs_invocation_id);
1137 }
1138 break;
1139 case MESA_SHADER_FRAGMENT:
1140 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1141 previous_stage, &user_sgpr_info,
1142 &args, &desc_sets);
1143
1144 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1145 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1146 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1147 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1148 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1149 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1150 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1151 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1152 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1153 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1154 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1155 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1156 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1157 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1158 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1159 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1160 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1161 break;
1162 default:
1163 unreachable("Shader stage not implemented");
1164 }
1165
1166 ctx->main_function = create_llvm_function(
1167 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1168 ctx->max_workgroup_size, ctx->options);
1169 set_llvm_calling_convention(ctx->main_function, stage);
1170
1171
1172 ctx->shader_info->num_input_vgprs = 0;
1173 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1174
1175 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1176
1177 if (ctx->stage != MESA_SHADER_FRAGMENT)
1178 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1179
1180 assign_arguments(ctx->main_function, &args);
1181
1182 user_sgpr_idx = 0;
1183
1184 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1185 set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1186 &user_sgpr_idx);
1187 if (ctx->options->supports_spill) {
1188 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1189 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
1190 NULL, 0, AC_FUNC_ATTR_READNONE);
1191 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1192 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1193 }
1194 }
1195
1196 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1197 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1198 if (has_previous_stage)
1199 user_sgpr_idx = 0;
1200
1201 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1202 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1203
1204 switch (stage) {
1205 case MESA_SHADER_COMPUTE:
1206 if (ctx->shader_info->info.cs.uses_grid_size) {
1207 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1208 &user_sgpr_idx, 3);
1209 }
1210 break;
1211 case MESA_SHADER_VERTEX:
1212 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1213 previous_stage, &user_sgpr_idx);
1214 if (ctx->abi.view_index)
1215 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1216 break;
1217 case MESA_SHADER_TESS_CTRL:
1218 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1219 previous_stage, &user_sgpr_idx);
1220 if (ctx->abi.view_index)
1221 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1222 break;
1223 case MESA_SHADER_TESS_EVAL:
1224 if (ctx->abi.view_index)
1225 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1226 break;
1227 case MESA_SHADER_GEOMETRY:
1228 if (has_previous_stage) {
1229 if (previous_stage == MESA_SHADER_VERTEX)
1230 set_vs_specific_input_locs(ctx, stage,
1231 has_previous_stage,
1232 previous_stage,
1233 &user_sgpr_idx);
1234 }
1235 if (ctx->abi.view_index)
1236 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1237 break;
1238 case MESA_SHADER_FRAGMENT:
1239 break;
1240 default:
1241 unreachable("Shader stage not implemented");
1242 }
1243
1244 if (stage == MESA_SHADER_TESS_CTRL ||
1245 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1246 /* GFX9 has the ESGS ring buffer in LDS. */
1247 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1248 ac_declare_lds_as_pointer(&ctx->ac);
1249 }
1250
1251 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1252 }
1253
1254
1255 static LLVMValueRef
1256 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1257 unsigned desc_set, unsigned binding)
1258 {
1259 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1260 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1261 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1262 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1263 unsigned base_offset = layout->binding[binding].offset;
1264 LLVMValueRef offset, stride;
1265
1266 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1267 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1268 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1269 layout->binding[binding].dynamic_offset_offset;
1270 desc_ptr = ctx->abi.push_constants;
1271 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1272 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1273 } else
1274 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1275
1276 offset = ac_build_imad(&ctx->ac, index, stride,
1277 LLVMConstInt(ctx->ac.i32, base_offset, false));
1278
1279 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1280 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1281 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1282
1283 return desc_ptr;
1284 }
1285
1286
1287 /* The offchip buffer layout for TCS->TES is
1288 *
1289 * - attribute 0 of patch 0 vertex 0
1290 * - attribute 0 of patch 0 vertex 1
1291 * - attribute 0 of patch 0 vertex 2
1292 * ...
1293 * - attribute 0 of patch 1 vertex 0
1294 * - attribute 0 of patch 1 vertex 1
1295 * ...
1296 * - attribute 1 of patch 0 vertex 0
1297 * - attribute 1 of patch 0 vertex 1
1298 * ...
1299 * - per patch attribute 0 of patch 0
1300 * - per patch attribute 0 of patch 1
1301 * ...
1302 *
1303 * Note that every attribute has 4 components.
1304 */
1305 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1306 {
1307 uint32_t num_patches = ctx->tcs_num_patches;
1308 uint32_t num_tcs_outputs;
1309 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1310 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1311 else
1312 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1313
1314 uint32_t output_vertex_size = num_tcs_outputs * 16;
1315 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1316
1317 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1318 }
1319
1320 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1321 LLVMValueRef vertex_index)
1322 {
1323 LLVMValueRef param_stride;
1324 if (vertex_index)
1325 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1326 else
1327 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1328 return param_stride;
1329 }
1330
1331 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1332 LLVMValueRef vertex_index,
1333 LLVMValueRef param_index)
1334 {
1335 LLVMValueRef base_addr;
1336 LLVMValueRef param_stride, constant16;
1337 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1338 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1339 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1340 param_stride = calc_param_stride(ctx, vertex_index);
1341 if (vertex_index) {
1342 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
1343 vertices_per_patch, vertex_index);
1344 } else {
1345 base_addr = rel_patch_id;
1346 }
1347
1348 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1349 LLVMBuildMul(ctx->ac.builder, param_index,
1350 param_stride, ""), "");
1351
1352 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1353
1354 if (!vertex_index) {
1355 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1356
1357 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1358 patch_data_offset, "");
1359 }
1360 return base_addr;
1361 }
1362
1363 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1364 unsigned param,
1365 unsigned const_index,
1366 bool is_compact,
1367 LLVMValueRef vertex_index,
1368 LLVMValueRef indir_index)
1369 {
1370 LLVMValueRef param_index;
1371
1372 if (indir_index)
1373 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1374 indir_index, "");
1375 else {
1376 if (const_index && !is_compact)
1377 param += const_index;
1378 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1379 }
1380 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1381 }
1382
1383 static LLVMValueRef
1384 get_dw_address(struct radv_shader_context *ctx,
1385 LLVMValueRef dw_addr,
1386 unsigned param,
1387 unsigned const_index,
1388 bool compact_const_index,
1389 LLVMValueRef vertex_index,
1390 LLVMValueRef stride,
1391 LLVMValueRef indir_index)
1392
1393 {
1394
1395 if (vertex_index) {
1396 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1397 LLVMBuildMul(ctx->ac.builder,
1398 vertex_index,
1399 stride, ""), "");
1400 }
1401
1402 if (indir_index)
1403 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1404 LLVMBuildMul(ctx->ac.builder, indir_index,
1405 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1406 else if (const_index && !compact_const_index)
1407 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1408 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1409
1410 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1411 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1412
1413 if (const_index && compact_const_index)
1414 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1415 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1416 return dw_addr;
1417 }
1418
1419 static LLVMValueRef
1420 load_tcs_varyings(struct ac_shader_abi *abi,
1421 LLVMTypeRef type,
1422 LLVMValueRef vertex_index,
1423 LLVMValueRef indir_index,
1424 unsigned const_index,
1425 unsigned location,
1426 unsigned driver_location,
1427 unsigned component,
1428 unsigned num_components,
1429 bool is_patch,
1430 bool is_compact,
1431 bool load_input)
1432 {
1433 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1434 LLVMValueRef dw_addr, stride;
1435 LLVMValueRef value[4], result;
1436 unsigned param = shader_io_get_unique_index(location);
1437
1438 if (load_input) {
1439 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1440 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1441 dw_addr = get_tcs_in_current_patch_offset(ctx);
1442 } else {
1443 if (!is_patch) {
1444 stride = get_tcs_out_vertex_stride(ctx);
1445 dw_addr = get_tcs_out_current_patch_offset(ctx);
1446 } else {
1447 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1448 stride = NULL;
1449 }
1450 }
1451
1452 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1453 indir_index);
1454
1455 for (unsigned i = 0; i < num_components + component; i++) {
1456 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1457 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1458 ctx->ac.i32_1, "");
1459 }
1460 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1461 return result;
1462 }
1463
1464 static void
1465 store_tcs_output(struct ac_shader_abi *abi,
1466 const nir_variable *var,
1467 LLVMValueRef vertex_index,
1468 LLVMValueRef param_index,
1469 unsigned const_index,
1470 LLVMValueRef src,
1471 unsigned writemask)
1472 {
1473 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1474 const unsigned location = var->data.location;
1475 const unsigned component = var->data.location_frac;
1476 const bool is_patch = var->data.patch;
1477 const bool is_compact = var->data.compact;
1478 LLVMValueRef dw_addr;
1479 LLVMValueRef stride = NULL;
1480 LLVMValueRef buf_addr = NULL;
1481 unsigned param;
1482 bool store_lds = true;
1483
1484 if (is_patch) {
1485 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1486 store_lds = false;
1487 } else {
1488 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1489 store_lds = false;
1490 }
1491
1492 param = shader_io_get_unique_index(location);
1493 if (location == VARYING_SLOT_CLIP_DIST0 &&
1494 is_compact && const_index > 3) {
1495 const_index -= 3;
1496 param++;
1497 }
1498
1499 if (!is_patch) {
1500 stride = get_tcs_out_vertex_stride(ctx);
1501 dw_addr = get_tcs_out_current_patch_offset(ctx);
1502 } else {
1503 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1504 }
1505
1506 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1507 param_index);
1508 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1509 vertex_index, param_index);
1510
1511 bool is_tess_factor = false;
1512 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1513 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1514 is_tess_factor = true;
1515
1516 unsigned base = is_compact ? const_index : 0;
1517 for (unsigned chan = 0; chan < 8; chan++) {
1518 if (!(writemask & (1 << chan)))
1519 continue;
1520 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1521 value = ac_to_integer(&ctx->ac, value);
1522 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
1523
1524 if (store_lds || is_tess_factor) {
1525 LLVMValueRef dw_addr_chan =
1526 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1527 LLVMConstInt(ctx->ac.i32, chan, false), "");
1528 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1529 }
1530
1531 if (!is_tess_factor && writemask != 0xF)
1532 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1533 buf_addr, ctx->oc_lds,
1534 4 * (base + chan), 1, 0, true, false);
1535 }
1536
1537 if (writemask == 0xF) {
1538 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1539 buf_addr, ctx->oc_lds,
1540 (base * 4), 1, 0, true, false);
1541 }
1542 }
1543
1544 static LLVMValueRef
1545 load_tes_input(struct ac_shader_abi *abi,
1546 LLVMTypeRef type,
1547 LLVMValueRef vertex_index,
1548 LLVMValueRef param_index,
1549 unsigned const_index,
1550 unsigned location,
1551 unsigned driver_location,
1552 unsigned component,
1553 unsigned num_components,
1554 bool is_patch,
1555 bool is_compact,
1556 bool load_input)
1557 {
1558 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1559 LLVMValueRef buf_addr;
1560 LLVMValueRef result;
1561 unsigned param = shader_io_get_unique_index(location);
1562
1563 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1564 const_index -= 3;
1565 param++;
1566 }
1567
1568 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1569 is_compact, vertex_index, param_index);
1570
1571 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1572 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1573
1574 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1575 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1576 result = ac_trim_vector(&ctx->ac, result, num_components);
1577 return result;
1578 }
1579
1580 static LLVMValueRef
1581 load_gs_input(struct ac_shader_abi *abi,
1582 unsigned location,
1583 unsigned driver_location,
1584 unsigned component,
1585 unsigned num_components,
1586 unsigned vertex_index,
1587 unsigned const_index,
1588 LLVMTypeRef type)
1589 {
1590 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1591 LLVMValueRef vtx_offset;
1592 unsigned param, vtx_offset_param;
1593 LLVMValueRef value[4], result;
1594
1595 vtx_offset_param = vertex_index;
1596 assert(vtx_offset_param < 6);
1597 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1598 LLVMConstInt(ctx->ac.i32, 4, false), "");
1599
1600 param = shader_io_get_unique_index(location);
1601
1602 for (unsigned i = component; i < num_components + component; i++) {
1603 if (ctx->ac.chip_class >= GFX9) {
1604 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1605 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1606 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1607 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1608 } else {
1609 LLVMValueRef soffset =
1610 LLVMConstInt(ctx->ac.i32,
1611 (param * 4 + i + const_index) * 256,
1612 false);
1613
1614 value[i] = ac_build_buffer_load(&ctx->ac,
1615 ctx->esgs_ring, 1,
1616 ctx->ac.i32_0,
1617 vtx_offset, soffset,
1618 0, 1, 0, true, false);
1619 }
1620
1621 if (ac_get_type_size(type) == 2) {
1622 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
1623 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
1624 }
1625 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
1626 }
1627 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1628 result = ac_to_integer(&ctx->ac, result);
1629 return result;
1630 }
1631
1632
1633 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1634 {
1635 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1636 ac_build_kill_if_false(&ctx->ac, visible);
1637 }
1638
1639 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1640 enum glsl_interp_mode interp, unsigned location)
1641 {
1642 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1643
1644 switch (interp) {
1645 case INTERP_MODE_FLAT:
1646 default:
1647 return NULL;
1648 case INTERP_MODE_SMOOTH:
1649 case INTERP_MODE_NONE:
1650 if (location == INTERP_CENTER)
1651 return ctx->persp_center;
1652 else if (location == INTERP_CENTROID)
1653 return ctx->persp_centroid;
1654 else if (location == INTERP_SAMPLE)
1655 return ctx->persp_sample;
1656 break;
1657 case INTERP_MODE_NOPERSPECTIVE:
1658 if (location == INTERP_CENTER)
1659 return ctx->linear_center;
1660 else if (location == INTERP_CENTROID)
1661 return ctx->linear_centroid;
1662 else if (location == INTERP_SAMPLE)
1663 return ctx->linear_sample;
1664 break;
1665 }
1666 return NULL;
1667 }
1668
1669 static uint32_t
1670 radv_get_sample_pos_offset(uint32_t num_samples)
1671 {
1672 uint32_t sample_pos_offset = 0;
1673
1674 switch (num_samples) {
1675 case 2:
1676 sample_pos_offset = 1;
1677 break;
1678 case 4:
1679 sample_pos_offset = 3;
1680 break;
1681 case 8:
1682 sample_pos_offset = 7;
1683 break;
1684 case 16:
1685 sample_pos_offset = 15;
1686 break;
1687 default:
1688 break;
1689 }
1690 return sample_pos_offset;
1691 }
1692
1693 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1694 LLVMValueRef sample_id)
1695 {
1696 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1697
1698 LLVMValueRef result;
1699 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1700
1701 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1702 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1703
1704 uint32_t sample_pos_offset =
1705 radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
1706
1707 sample_id =
1708 LLVMBuildAdd(ctx->ac.builder, sample_id,
1709 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
1710 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1711
1712 return result;
1713 }
1714
1715
1716 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1717 {
1718 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1719 uint8_t log2_ps_iter_samples;
1720
1721 if (ctx->shader_info->info.ps.force_persample) {
1722 log2_ps_iter_samples =
1723 util_logbase2(ctx->options->key.fs.num_samples);
1724 } else {
1725 log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
1726 }
1727
1728 /* The bit pattern matches that used by fixed function fragment
1729 * processing. */
1730 static const uint16_t ps_iter_masks[] = {
1731 0xffff, /* not used */
1732 0x5555,
1733 0x1111,
1734 0x0101,
1735 0x0001,
1736 };
1737 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1738
1739 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1740
1741 LLVMValueRef result, sample_id;
1742 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1743 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1744 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1745 return result;
1746 }
1747
1748
1749 static void
1750 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1751 {
1752 LLVMValueRef gs_next_vertex;
1753 LLVMValueRef can_emit;
1754 unsigned offset = 0;
1755 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1756
1757 /* Write vertex attribute values to GSVS ring */
1758 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1759 ctx->gs_next_vertex[stream],
1760 "");
1761
1762 /* If this thread has already emitted the declared maximum number of
1763 * vertices, kill it: excessive vertex emissions are not supposed to
1764 * have any effect, and GS threads have no externally observable
1765 * effects other than emitting vertices.
1766 */
1767 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1768 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1769 ac_build_kill_if_false(&ctx->ac, can_emit);
1770
1771 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1772 unsigned output_usage_mask =
1773 ctx->shader_info->info.gs.output_usage_mask[i];
1774 uint8_t output_stream =
1775 ctx->shader_info->info.gs.output_streams[i];
1776 LLVMValueRef *out_ptr = &addrs[i * 4];
1777 int length = util_last_bit(output_usage_mask);
1778
1779 if (!(ctx->output_mask & (1ull << i)) ||
1780 output_stream != stream)
1781 continue;
1782
1783 for (unsigned j = 0; j < length; j++) {
1784 if (!(output_usage_mask & (1 << j)))
1785 continue;
1786
1787 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1788 out_ptr[j], "");
1789 LLVMValueRef voffset =
1790 LLVMConstInt(ctx->ac.i32, offset *
1791 ctx->gs_max_out_vertices, false);
1792
1793 offset++;
1794
1795 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1796 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1797
1798 out_val = ac_to_integer(&ctx->ac, out_val);
1799 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1800
1801 ac_build_buffer_store_dword(&ctx->ac,
1802 ctx->gsvs_ring[stream],
1803 out_val, 1,
1804 voffset, ctx->gs2vs_offset, 0,
1805 1, 1, true, true);
1806 }
1807 }
1808
1809 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1810 ctx->ac.i32_1, "");
1811 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
1812
1813 ac_build_sendmsg(&ctx->ac,
1814 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
1815 ctx->gs_wave_id);
1816 }
1817
1818 static void
1819 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1820 {
1821 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1822 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1823 }
1824
1825 static LLVMValueRef
1826 load_tess_coord(struct ac_shader_abi *abi)
1827 {
1828 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1829
1830 LLVMValueRef coord[4] = {
1831 ctx->tes_u,
1832 ctx->tes_v,
1833 ctx->ac.f32_0,
1834 ctx->ac.f32_0,
1835 };
1836
1837 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1838 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1839 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1840
1841 return ac_build_gather_values(&ctx->ac, coord, 3);
1842 }
1843
1844 static LLVMValueRef
1845 load_patch_vertices_in(struct ac_shader_abi *abi)
1846 {
1847 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1848 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1849 }
1850
1851
1852 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1853 {
1854 return abi->base_vertex;
1855 }
1856
1857 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1858 LLVMValueRef buffer_ptr, bool write)
1859 {
1860 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1861 LLVMValueRef result;
1862
1863 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1864
1865 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1866 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1867
1868 return result;
1869 }
1870
1871 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1872 {
1873 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1874 LLVMValueRef result;
1875
1876 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1877
1878 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1879 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1880
1881 return result;
1882 }
1883
1884 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1885 unsigned descriptor_set,
1886 unsigned base_index,
1887 unsigned constant_index,
1888 LLVMValueRef index,
1889 enum ac_descriptor_type desc_type,
1890 bool image, bool write,
1891 bool bindless)
1892 {
1893 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1894 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1895 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1896 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1897 unsigned offset = binding->offset;
1898 unsigned stride = binding->size;
1899 unsigned type_size;
1900 LLVMBuilderRef builder = ctx->ac.builder;
1901 LLVMTypeRef type;
1902
1903 assert(base_index < layout->binding_count);
1904
1905 switch (desc_type) {
1906 case AC_DESC_IMAGE:
1907 type = ctx->ac.v8i32;
1908 type_size = 32;
1909 break;
1910 case AC_DESC_FMASK:
1911 type = ctx->ac.v8i32;
1912 offset += 32;
1913 type_size = 32;
1914 break;
1915 case AC_DESC_SAMPLER:
1916 type = ctx->ac.v4i32;
1917 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1918 offset += 64;
1919
1920 type_size = 16;
1921 break;
1922 case AC_DESC_BUFFER:
1923 type = ctx->ac.v4i32;
1924 type_size = 16;
1925 break;
1926 default:
1927 unreachable("invalid desc_type\n");
1928 }
1929
1930 offset += constant_index * stride;
1931
1932 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1933 (!index || binding->immutable_samplers_equal)) {
1934 if (binding->immutable_samplers_equal)
1935 constant_index = 0;
1936
1937 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1938
1939 LLVMValueRef constants[] = {
1940 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1941 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1942 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1943 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1944 };
1945 return ac_build_gather_values(&ctx->ac, constants, 4);
1946 }
1947
1948 assert(stride % type_size == 0);
1949
1950 if (!index)
1951 index = ctx->ac.i32_0;
1952
1953 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1954
1955 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1956 list = LLVMBuildPointerCast(builder, list,
1957 ac_array_in_const32_addr_space(type), "");
1958
1959 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1960 }
1961
1962 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1963 * so we may need to fix it up. */
1964 static LLVMValueRef
1965 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1966 unsigned adjustment,
1967 LLVMValueRef alpha)
1968 {
1969 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1970 return alpha;
1971
1972 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1973
1974 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1975 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1976 else
1977 alpha = ac_to_integer(&ctx->ac, alpha);
1978
1979 /* For the integer-like cases, do a natural sign extension.
1980 *
1981 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1982 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1983 * exponent.
1984 */
1985 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1986 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1987 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1988 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1989
1990 /* Convert back to the right type. */
1991 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1992 LLVMValueRef clamp;
1993 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1994 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1995 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1996 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1997 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1998 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1999 }
2000
2001 return alpha;
2002 }
2003
2004 static void
2005 handle_vs_input_decl(struct radv_shader_context *ctx,
2006 struct nir_variable *variable)
2007 {
2008 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
2009 LLVMValueRef t_offset;
2010 LLVMValueRef t_list;
2011 LLVMValueRef input;
2012 LLVMValueRef buffer_index;
2013 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
2014 uint8_t input_usage_mask =
2015 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
2016 unsigned num_channels = util_last_bit(input_usage_mask);
2017
2018 variable->data.driver_location = variable->data.location * 4;
2019
2020 enum glsl_base_type type = glsl_get_base_type(variable->type);
2021 for (unsigned i = 0; i < attrib_count; ++i) {
2022 LLVMValueRef output[4];
2023 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
2024
2025 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
2026 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
2027
2028 if (divisor) {
2029 buffer_index = ctx->abi.instance_id;
2030
2031 if (divisor != 1) {
2032 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
2033 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
2034 }
2035
2036 if (ctx->options->key.vs.as_ls) {
2037 ctx->shader_info->vs.vgpr_comp_cnt =
2038 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
2039 } else {
2040 ctx->shader_info->vs.vgpr_comp_cnt =
2041 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
2042 }
2043 } else {
2044 buffer_index = ctx->ac.i32_0;
2045 }
2046
2047 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index, "");
2048 } else
2049 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
2050 ctx->abi.base_vertex, "");
2051 t_offset = LLVMConstInt(ctx->ac.i32, attrib_index, false);
2052
2053 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
2054
2055 input = ac_build_buffer_load_format(&ctx->ac, t_list,
2056 buffer_index,
2057 ctx->ac.i32_0,
2058 num_channels, false, true);
2059
2060 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
2061
2062 for (unsigned chan = 0; chan < 4; chan++) {
2063 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2064 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
2065 if (type == GLSL_TYPE_FLOAT16) {
2066 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
2067 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
2068 }
2069 }
2070
2071 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
2072 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
2073
2074 for (unsigned chan = 0; chan < 4; chan++) {
2075 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
2076 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
2077 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
2078
2079 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
2080 }
2081 }
2082 }
2083
2084 static void interp_fs_input(struct radv_shader_context *ctx,
2085 unsigned attr,
2086 LLVMValueRef interp_param,
2087 LLVMValueRef prim_mask,
2088 LLVMValueRef result[4])
2089 {
2090 LLVMValueRef attr_number;
2091 unsigned chan;
2092 LLVMValueRef i, j;
2093 bool interp = !LLVMIsUndef(interp_param);
2094
2095 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
2096
2097 /* fs.constant returns the param from the middle vertex, so it's not
2098 * really useful for flat shading. It's meant to be used for custom
2099 * interpolation (but the intrinsic can't fetch from the other two
2100 * vertices).
2101 *
2102 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2103 * to do the right thing. The only reason we use fs.constant is that
2104 * fs.interp cannot be used on integers, because they can be equal
2105 * to NaN.
2106 */
2107 if (interp) {
2108 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
2109 ctx->ac.v2f32, "");
2110
2111 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2112 ctx->ac.i32_0, "");
2113 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2114 ctx->ac.i32_1, "");
2115 }
2116
2117 for (chan = 0; chan < 4; chan++) {
2118 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2119
2120 if (interp) {
2121 result[chan] = ac_build_fs_interp(&ctx->ac,
2122 llvm_chan,
2123 attr_number,
2124 prim_mask, i, j);
2125 } else {
2126 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2127 LLVMConstInt(ctx->ac.i32, 2, false),
2128 llvm_chan,
2129 attr_number,
2130 prim_mask);
2131 result[chan] = LLVMBuildBitCast(ctx->ac.builder, result[chan], ctx->ac.i32, "");
2132 result[chan] = LLVMBuildTruncOrBitCast(ctx->ac.builder, result[chan], LLVMTypeOf(interp_param), "");
2133 }
2134 }
2135 }
2136
2137 static void
2138 handle_fs_input_decl(struct radv_shader_context *ctx,
2139 struct nir_variable *variable)
2140 {
2141 int idx = variable->data.location;
2142 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2143 LLVMValueRef interp = NULL;
2144 uint64_t mask;
2145
2146 variable->data.driver_location = idx * 4;
2147 mask = ((1ull << attrib_count) - 1) << variable->data.location;
2148
2149 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
2150 unsigned interp_type;
2151 if (variable->data.sample)
2152 interp_type = INTERP_SAMPLE;
2153 else if (variable->data.centroid)
2154 interp_type = INTERP_CENTROID;
2155 else
2156 interp_type = INTERP_CENTER;
2157
2158 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
2159 }
2160 bool is_16bit = glsl_type_is_16bit(variable->type);
2161 LLVMTypeRef type = is_16bit ? ctx->ac.i16 : ctx->ac.i32;
2162 if (interp == NULL)
2163 interp = LLVMGetUndef(type);
2164
2165 for (unsigned i = 0; i < attrib_count; ++i)
2166 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
2167
2168 if (idx == VARYING_SLOT_CLIP_DIST0) {
2169 /* Do not account for the number of components inside the array
2170 * of clip/cull distances because this might wrongly set other
2171 * bits like primitive ID or layer.
2172 */
2173 mask = 1ull << VARYING_SLOT_CLIP_DIST0;
2174 }
2175
2176 ctx->input_mask |= mask;
2177 }
2178
2179 static void
2180 handle_vs_inputs(struct radv_shader_context *ctx,
2181 struct nir_shader *nir) {
2182 nir_foreach_variable(variable, &nir->inputs)
2183 handle_vs_input_decl(ctx, variable);
2184 }
2185
2186 static void
2187 prepare_interp_optimize(struct radv_shader_context *ctx,
2188 struct nir_shader *nir)
2189 {
2190 bool uses_center = false;
2191 bool uses_centroid = false;
2192 nir_foreach_variable(variable, &nir->inputs) {
2193 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2194 variable->data.sample)
2195 continue;
2196
2197 if (variable->data.centroid)
2198 uses_centroid = true;
2199 else
2200 uses_center = true;
2201 }
2202
2203 if (uses_center && uses_centroid) {
2204 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2205 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
2206 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
2207 }
2208 }
2209
2210 static void
2211 handle_fs_inputs(struct radv_shader_context *ctx,
2212 struct nir_shader *nir)
2213 {
2214 prepare_interp_optimize(ctx, nir);
2215
2216 nir_foreach_variable(variable, &nir->inputs)
2217 handle_fs_input_decl(ctx, variable);
2218
2219 unsigned index = 0;
2220
2221 if (ctx->shader_info->info.ps.uses_input_attachments ||
2222 ctx->shader_info->info.needs_multiview_view_index) {
2223 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
2224 ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)] = LLVMGetUndef(ctx->ac.i32);
2225 }
2226
2227 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
2228 LLVMValueRef interp_param;
2229 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
2230
2231 if (!(ctx->input_mask & (1ull << i)))
2232 continue;
2233
2234 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
2235 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
2236 interp_param = *inputs;
2237 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
2238 inputs);
2239
2240 if (LLVMIsUndef(interp_param))
2241 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
2242 ++index;
2243 } else if (i == VARYING_SLOT_CLIP_DIST0) {
2244 int length = ctx->shader_info->info.ps.num_input_clips_culls;
2245
2246 for (unsigned j = 0; j < length; j += 4) {
2247 inputs = ctx->inputs + ac_llvm_reg_index_soa(i, j);
2248
2249 interp_param = *inputs;
2250 interp_fs_input(ctx, index, interp_param,
2251 ctx->abi.prim_mask, inputs);
2252 ++index;
2253 }
2254 } else if (i == VARYING_SLOT_POS) {
2255 for(int i = 0; i < 3; ++i)
2256 inputs[i] = ctx->abi.frag_pos[i];
2257
2258 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2259 ctx->abi.frag_pos[3]);
2260 }
2261 }
2262 ctx->shader_info->fs.num_interp = index;
2263 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
2264
2265 if (ctx->shader_info->info.needs_multiview_view_index)
2266 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2267 }
2268
2269 static void
2270 scan_shader_output_decl(struct radv_shader_context *ctx,
2271 struct nir_variable *variable,
2272 struct nir_shader *shader,
2273 gl_shader_stage stage)
2274 {
2275 int idx = variable->data.location + variable->data.index;
2276 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2277 uint64_t mask_attribs;
2278
2279 variable->data.driver_location = idx * 4;
2280
2281 /* tess ctrl has it's own load/store paths for outputs */
2282 if (stage == MESA_SHADER_TESS_CTRL)
2283 return;
2284
2285 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2286 if (stage == MESA_SHADER_VERTEX ||
2287 stage == MESA_SHADER_TESS_EVAL ||
2288 stage == MESA_SHADER_GEOMETRY) {
2289 if (idx == VARYING_SLOT_CLIP_DIST0) {
2290 if (stage == MESA_SHADER_VERTEX) {
2291 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2292 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2293 ctx->shader_info->vs.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
2294 }
2295 if (stage == MESA_SHADER_TESS_EVAL) {
2296 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2297 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2298 ctx->shader_info->tes.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
2299 }
2300
2301 mask_attribs = 1ull << idx;
2302 }
2303 }
2304
2305 ctx->output_mask |= mask_attribs;
2306 }
2307
2308
2309 /* Initialize arguments for the shader export intrinsic */
2310 static void
2311 si_llvm_init_export_args(struct radv_shader_context *ctx,
2312 LLVMValueRef *values,
2313 unsigned enabled_channels,
2314 unsigned target,
2315 struct ac_export_args *args)
2316 {
2317 /* Specify the channels that are enabled. */
2318 args->enabled_channels = enabled_channels;
2319
2320 /* Specify whether the EXEC mask represents the valid mask */
2321 args->valid_mask = 0;
2322
2323 /* Specify whether this is the last export */
2324 args->done = 0;
2325
2326 /* Specify the target we are exporting */
2327 args->target = target;
2328
2329 args->compr = false;
2330 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2331 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2332 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2333 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2334
2335 if (!values)
2336 return;
2337
2338 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
2339 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2340 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2341 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2342 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2343 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2344 unsigned chan;
2345
2346 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2347 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2348 unsigned bits, bool hi) = NULL;
2349
2350 switch(col_format) {
2351 case V_028714_SPI_SHADER_ZERO:
2352 args->enabled_channels = 0; /* writemask */
2353 args->target = V_008DFC_SQ_EXP_NULL;
2354 break;
2355
2356 case V_028714_SPI_SHADER_32_R:
2357 args->enabled_channels = 1;
2358 args->out[0] = values[0];
2359 break;
2360
2361 case V_028714_SPI_SHADER_32_GR:
2362 args->enabled_channels = 0x3;
2363 args->out[0] = values[0];
2364 args->out[1] = values[1];
2365 break;
2366
2367 case V_028714_SPI_SHADER_32_AR:
2368 args->enabled_channels = 0x9;
2369 args->out[0] = values[0];
2370 args->out[3] = values[3];
2371 break;
2372
2373 case V_028714_SPI_SHADER_FP16_ABGR:
2374 args->enabled_channels = 0x5;
2375 packf = ac_build_cvt_pkrtz_f16;
2376 if (is_16bit) {
2377 for (unsigned chan = 0; chan < 4; chan++)
2378 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
2379 values[chan],
2380 ctx->ac.f32, "");
2381 }
2382 break;
2383
2384 case V_028714_SPI_SHADER_UNORM16_ABGR:
2385 args->enabled_channels = 0x5;
2386 packf = ac_build_cvt_pknorm_u16;
2387 break;
2388
2389 case V_028714_SPI_SHADER_SNORM16_ABGR:
2390 args->enabled_channels = 0x5;
2391 packf = ac_build_cvt_pknorm_i16;
2392 break;
2393
2394 case V_028714_SPI_SHADER_UINT16_ABGR:
2395 args->enabled_channels = 0x5;
2396 packi = ac_build_cvt_pk_u16;
2397 if (is_16bit) {
2398 for (unsigned chan = 0; chan < 4; chan++)
2399 values[chan] = LLVMBuildZExt(ctx->ac.builder,
2400 values[chan],
2401 ctx->ac.i32, "");
2402 }
2403 break;
2404
2405 case V_028714_SPI_SHADER_SINT16_ABGR:
2406 args->enabled_channels = 0x5;
2407 packi = ac_build_cvt_pk_i16;
2408 if (is_16bit) {
2409 for (unsigned chan = 0; chan < 4; chan++)
2410 values[chan] = LLVMBuildSExt(ctx->ac.builder,
2411 values[chan],
2412 ctx->ac.i32, "");
2413 }
2414 break;
2415
2416 default:
2417 case V_028714_SPI_SHADER_32_ABGR:
2418 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2419 break;
2420 }
2421
2422 /* Pack f16 or norm_i16/u16. */
2423 if (packf) {
2424 for (chan = 0; chan < 2; chan++) {
2425 LLVMValueRef pack_args[2] = {
2426 values[2 * chan],
2427 values[2 * chan + 1]
2428 };
2429 LLVMValueRef packed;
2430
2431 packed = packf(&ctx->ac, pack_args);
2432 args->out[chan] = ac_to_float(&ctx->ac, packed);
2433 }
2434 args->compr = 1; /* COMPR flag */
2435 }
2436
2437 /* Pack i16/u16. */
2438 if (packi) {
2439 for (chan = 0; chan < 2; chan++) {
2440 LLVMValueRef pack_args[2] = {
2441 ac_to_integer(&ctx->ac, values[2 * chan]),
2442 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2443 };
2444 LLVMValueRef packed;
2445
2446 packed = packi(&ctx->ac, pack_args,
2447 is_int8 ? 8 : is_int10 ? 10 : 16,
2448 chan == 1);
2449 args->out[chan] = ac_to_float(&ctx->ac, packed);
2450 }
2451 args->compr = 1; /* COMPR flag */
2452 }
2453 return;
2454 }
2455
2456 if (is_16bit) {
2457 for (unsigned chan = 0; chan < 4; chan++) {
2458 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
2459 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
2460 }
2461 } else
2462 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2463
2464 for (unsigned i = 0; i < 4; ++i) {
2465 if (!(args->enabled_channels & (1 << i)))
2466 continue;
2467
2468 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2469 }
2470 }
2471
2472 static void
2473 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2474 LLVMValueRef *values, unsigned enabled_channels)
2475 {
2476 struct ac_export_args args;
2477
2478 si_llvm_init_export_args(ctx, values, enabled_channels,
2479 V_008DFC_SQ_EXP_PARAM + index, &args);
2480 ac_build_export(&ctx->ac, &args);
2481 }
2482
2483 static LLVMValueRef
2484 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2485 {
2486 LLVMValueRef output =
2487 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2488
2489 return LLVMBuildLoad(ctx->ac.builder, output, "");
2490 }
2491
2492 static void
2493 radv_emit_stream_output(struct radv_shader_context *ctx,
2494 LLVMValueRef const *so_buffers,
2495 LLVMValueRef const *so_write_offsets,
2496 const struct radv_stream_output *output)
2497 {
2498 unsigned num_comps = util_bitcount(output->component_mask);
2499 unsigned loc = output->location;
2500 unsigned buf = output->buffer;
2501 unsigned offset = output->offset;
2502 unsigned start;
2503 LLVMValueRef out[4];
2504
2505 assert(num_comps && num_comps <= 4);
2506 if (!num_comps || num_comps > 4)
2507 return;
2508
2509 /* Get the first component. */
2510 start = ffs(output->component_mask) - 1;
2511
2512 /* Load the output as int. */
2513 for (int i = 0; i < num_comps; i++) {
2514 out[i] = ac_to_integer(&ctx->ac,
2515 radv_load_output(ctx, loc, start + i));
2516 }
2517
2518 /* Pack the output. */
2519 LLVMValueRef vdata = NULL;
2520
2521 switch (num_comps) {
2522 case 1: /* as i32 */
2523 vdata = out[0];
2524 break;
2525 case 2: /* as v2i32 */
2526 case 3: /* as v4i32 (aligned to 4) */
2527 out[3] = LLVMGetUndef(ctx->ac.i32);
2528 /* fall through */
2529 case 4: /* as v4i32 */
2530 vdata = ac_build_gather_values(&ctx->ac, out,
2531 util_next_power_of_two(num_comps));
2532 break;
2533 }
2534
2535 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
2536 vdata, num_comps, so_write_offsets[buf],
2537 ctx->ac.i32_0, offset,
2538 1, 1, true, false);
2539 }
2540
2541 static void
2542 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
2543 {
2544 struct ac_build_if_state if_ctx;
2545 int i;
2546
2547 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2548 assert(ctx->streamout_config);
2549 LLVMValueRef so_vtx_count =
2550 ac_build_bfe(&ctx->ac, ctx->streamout_config,
2551 LLVMConstInt(ctx->ac.i32, 16, false),
2552 LLVMConstInt(ctx->ac.i32, 7, false), false);
2553
2554 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2555
2556 /* can_emit = tid < so_vtx_count; */
2557 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
2558 tid, so_vtx_count, "");
2559
2560 /* Emit the streamout code conditionally. This actually avoids
2561 * out-of-bounds buffer access. The hw tells us via the SGPR
2562 * (so_vtx_count) which threads are allowed to emit streamout data.
2563 */
2564 ac_nir_build_if(&if_ctx, ctx, can_emit);
2565 {
2566 /* The buffer offset is computed as follows:
2567 * ByteOffset = streamout_offset[buffer_id]*4 +
2568 * (streamout_write_index + thread_id)*stride[buffer_id] +
2569 * attrib_offset
2570 */
2571 LLVMValueRef so_write_index = ctx->streamout_write_idx;
2572
2573 /* Compute (streamout_write_index + thread_id). */
2574 so_write_index =
2575 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
2576
2577 /* Load the descriptor and compute the write offset for each
2578 * enabled buffer.
2579 */
2580 LLVMValueRef so_write_offset[4] = {};
2581 LLVMValueRef so_buffers[4] = {};
2582 LLVMValueRef buf_ptr = ctx->streamout_buffers;
2583
2584 for (i = 0; i < 4; i++) {
2585 uint16_t stride = ctx->shader_info->info.so.strides[i];
2586
2587 if (!stride)
2588 continue;
2589
2590 LLVMValueRef offset =
2591 LLVMConstInt(ctx->ac.i32, i, false);
2592
2593 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
2594 buf_ptr, offset);
2595
2596 LLVMValueRef so_offset = ctx->streamout_offset[i];
2597
2598 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
2599 LLVMConstInt(ctx->ac.i32, 4, false), "");
2600
2601 so_write_offset[i] =
2602 ac_build_imad(&ctx->ac, so_write_index,
2603 LLVMConstInt(ctx->ac.i32,
2604 stride * 4, false),
2605 so_offset);
2606 }
2607
2608 /* Write streamout data. */
2609 for (i = 0; i < ctx->shader_info->info.so.num_outputs; i++) {
2610 struct radv_stream_output *output =
2611 &ctx->shader_info->info.so.outputs[i];
2612
2613 if (stream != output->stream)
2614 continue;
2615
2616 radv_emit_stream_output(ctx, so_buffers,
2617 so_write_offset, output);
2618 }
2619 }
2620 ac_nir_build_endif(&if_ctx);
2621 }
2622
2623 static void
2624 handle_vs_outputs_post(struct radv_shader_context *ctx,
2625 bool export_prim_id, bool export_layer_id,
2626 struct radv_vs_output_info *outinfo)
2627 {
2628 uint32_t param_count = 0;
2629 unsigned target;
2630 unsigned pos_idx, num_pos_exports = 0;
2631 struct ac_export_args args, pos_args[4] = {};
2632 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2633 int i;
2634
2635 if (ctx->options->key.has_multiview_view_index) {
2636 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2637 if(!*tmp_out) {
2638 for(unsigned i = 0; i < 4; ++i)
2639 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2640 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2641 }
2642
2643 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2644 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2645 }
2646
2647 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2648 sizeof(outinfo->vs_output_param_offset));
2649
2650 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2651 unsigned output_usage_mask, length;
2652 LLVMValueRef slots[8];
2653 unsigned j;
2654
2655 if (ctx->stage == MESA_SHADER_VERTEX &&
2656 !ctx->is_gs_copy_shader) {
2657 output_usage_mask =
2658 ctx->shader_info->info.vs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2659 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2660 output_usage_mask =
2661 ctx->shader_info->info.tes.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2662 } else {
2663 assert(ctx->is_gs_copy_shader);
2664 output_usage_mask =
2665 ctx->shader_info->info.gs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2666 }
2667
2668 length = util_last_bit(output_usage_mask);
2669
2670 i = VARYING_SLOT_CLIP_DIST0;
2671 for (j = 0; j < length; j++)
2672 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2673
2674 for (i = length; i < 8; i++)
2675 slots[i] = LLVMGetUndef(ctx->ac.f32);
2676
2677 if (length > 4) {
2678 target = V_008DFC_SQ_EXP_POS + 3;
2679 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2680 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2681 &args, sizeof(args));
2682 }
2683
2684 target = V_008DFC_SQ_EXP_POS + 2;
2685 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2686 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2687 &args, sizeof(args));
2688
2689 /* Export the clip/cull distances values to the next stage. */
2690 radv_export_param(ctx, param_count, &slots[0], 0xf);
2691 outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0] = param_count++;
2692 if (length > 4) {
2693 radv_export_param(ctx, param_count, &slots[4], 0xf);
2694 outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1] = param_count++;
2695 }
2696 }
2697
2698 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2699 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2700 for (unsigned j = 0; j < 4; j++)
2701 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2702 }
2703 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2704
2705 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2706 outinfo->writes_pointsize = true;
2707 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2708 }
2709
2710 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2711 outinfo->writes_layer = true;
2712 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2713 }
2714
2715 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2716 outinfo->writes_viewport_index = true;
2717 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2718 }
2719
2720 if (ctx->shader_info->info.so.num_outputs &&
2721 !ctx->is_gs_copy_shader) {
2722 /* The GS copy shader emission already emits streamout. */
2723 radv_emit_streamout(ctx, 0);
2724 }
2725
2726 if (outinfo->writes_pointsize ||
2727 outinfo->writes_layer ||
2728 outinfo->writes_viewport_index) {
2729 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2730 (outinfo->writes_layer == true ? 4 : 0));
2731 pos_args[1].valid_mask = 0;
2732 pos_args[1].done = 0;
2733 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2734 pos_args[1].compr = 0;
2735 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2736 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2737 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2738 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2739
2740 if (outinfo->writes_pointsize == true)
2741 pos_args[1].out[0] = psize_value;
2742 if (outinfo->writes_layer == true)
2743 pos_args[1].out[2] = layer_value;
2744 if (outinfo->writes_viewport_index == true) {
2745 if (ctx->options->chip_class >= GFX9) {
2746 /* GFX9 has the layer in out.z[10:0] and the viewport
2747 * index in out.z[19:16].
2748 */
2749 LLVMValueRef v = viewport_index_value;
2750 v = ac_to_integer(&ctx->ac, v);
2751 v = LLVMBuildShl(ctx->ac.builder, v,
2752 LLVMConstInt(ctx->ac.i32, 16, false),
2753 "");
2754 v = LLVMBuildOr(ctx->ac.builder, v,
2755 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2756
2757 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2758 pos_args[1].enabled_channels |= 1 << 2;
2759 } else {
2760 pos_args[1].out[3] = viewport_index_value;
2761 pos_args[1].enabled_channels |= 1 << 3;
2762 }
2763 }
2764 }
2765 for (i = 0; i < 4; i++) {
2766 if (pos_args[i].out[0])
2767 num_pos_exports++;
2768 }
2769
2770 pos_idx = 0;
2771 for (i = 0; i < 4; i++) {
2772 if (!pos_args[i].out[0])
2773 continue;
2774
2775 /* Specify the target we are exporting */
2776 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2777 if (pos_idx == num_pos_exports)
2778 pos_args[i].done = 1;
2779 ac_build_export(&ctx->ac, &pos_args[i]);
2780 }
2781
2782 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2783 LLVMValueRef values[4];
2784 if (!(ctx->output_mask & (1ull << i)))
2785 continue;
2786
2787 if (i != VARYING_SLOT_LAYER &&
2788 i != VARYING_SLOT_PRIMITIVE_ID &&
2789 i < VARYING_SLOT_VAR0)
2790 continue;
2791
2792 for (unsigned j = 0; j < 4; j++)
2793 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2794
2795 unsigned output_usage_mask;
2796
2797 if (ctx->stage == MESA_SHADER_VERTEX &&
2798 !ctx->is_gs_copy_shader) {
2799 output_usage_mask =
2800 ctx->shader_info->info.vs.output_usage_mask[i];
2801 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2802 output_usage_mask =
2803 ctx->shader_info->info.tes.output_usage_mask[i];
2804 } else {
2805 assert(ctx->is_gs_copy_shader);
2806 output_usage_mask =
2807 ctx->shader_info->info.gs.output_usage_mask[i];
2808 }
2809
2810 radv_export_param(ctx, param_count, values, output_usage_mask);
2811
2812 outinfo->vs_output_param_offset[i] = param_count++;
2813 }
2814
2815 if (export_prim_id) {
2816 LLVMValueRef values[4];
2817
2818 values[0] = ctx->vs_prim_id;
2819 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2820 ctx->shader_info->vs.vgpr_comp_cnt);
2821 for (unsigned j = 1; j < 4; j++)
2822 values[j] = ctx->ac.f32_0;
2823
2824 radv_export_param(ctx, param_count, values, 0x1);
2825
2826 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2827 outinfo->export_prim_id = true;
2828 }
2829
2830 if (export_layer_id && layer_value) {
2831 LLVMValueRef values[4];
2832
2833 values[0] = layer_value;
2834 for (unsigned j = 1; j < 4; j++)
2835 values[j] = ctx->ac.f32_0;
2836
2837 radv_export_param(ctx, param_count, values, 0x1);
2838
2839 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2840 }
2841
2842 outinfo->pos_exports = num_pos_exports;
2843 outinfo->param_exports = param_count;
2844 }
2845
2846 static void
2847 handle_es_outputs_post(struct radv_shader_context *ctx,
2848 struct radv_es_output_info *outinfo)
2849 {
2850 int j;
2851 uint64_t max_output_written = 0;
2852 LLVMValueRef lds_base = NULL;
2853
2854 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2855 unsigned output_usage_mask;
2856 int param_index;
2857 int length = 4;
2858
2859 if (!(ctx->output_mask & (1ull << i)))
2860 continue;
2861
2862 if (ctx->stage == MESA_SHADER_VERTEX) {
2863 output_usage_mask =
2864 ctx->shader_info->info.vs.output_usage_mask[i];
2865 } else {
2866 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2867 output_usage_mask =
2868 ctx->shader_info->info.tes.output_usage_mask[i];
2869 }
2870
2871 if (i == VARYING_SLOT_CLIP_DIST0)
2872 length = util_last_bit(output_usage_mask);
2873
2874 param_index = shader_io_get_unique_index(i);
2875
2876 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2877 }
2878
2879 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2880
2881 if (ctx->ac.chip_class >= GFX9) {
2882 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2883 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2884 LLVMValueRef wave_idx = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
2885 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2886 LLVMBuildMul(ctx->ac.builder, wave_idx,
2887 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2888 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2889 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2890 }
2891
2892 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2893 LLVMValueRef dw_addr = NULL;
2894 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2895 unsigned output_usage_mask;
2896 int param_index;
2897 int length = 4;
2898
2899 if (!(ctx->output_mask & (1ull << i)))
2900 continue;
2901
2902 if (ctx->stage == MESA_SHADER_VERTEX) {
2903 output_usage_mask =
2904 ctx->shader_info->info.vs.output_usage_mask[i];
2905 } else {
2906 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2907 output_usage_mask =
2908 ctx->shader_info->info.tes.output_usage_mask[i];
2909 }
2910
2911 if (i == VARYING_SLOT_CLIP_DIST0)
2912 length = util_last_bit(output_usage_mask);
2913
2914 param_index = shader_io_get_unique_index(i);
2915
2916 if (lds_base) {
2917 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2918 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2919 "");
2920 }
2921
2922 for (j = 0; j < length; j++) {
2923 if (!(output_usage_mask & (1 << j)))
2924 continue;
2925
2926 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2927 out_val = ac_to_integer(&ctx->ac, out_val);
2928 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2929
2930 if (ctx->ac.chip_class >= GFX9) {
2931 LLVMValueRef dw_addr_offset =
2932 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2933 LLVMConstInt(ctx->ac.i32,
2934 j, false), "");
2935
2936 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2937 } else {
2938 ac_build_buffer_store_dword(&ctx->ac,
2939 ctx->esgs_ring,
2940 out_val, 1,
2941 NULL, ctx->es2gs_offset,
2942 (4 * param_index + j) * 4,
2943 1, 1, true, true);
2944 }
2945 }
2946 }
2947 }
2948
2949 static void
2950 handle_ls_outputs_post(struct radv_shader_context *ctx)
2951 {
2952 LLVMValueRef vertex_id = ctx->rel_auto_id;
2953 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2954 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2955 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2956 vertex_dw_stride, "");
2957
2958 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2959 unsigned output_usage_mask =
2960 ctx->shader_info->info.vs.output_usage_mask[i];
2961 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2962 int length = 4;
2963
2964 if (!(ctx->output_mask & (1ull << i)))
2965 continue;
2966
2967 if (i == VARYING_SLOT_CLIP_DIST0)
2968 length = util_last_bit(output_usage_mask);
2969
2970 int param = shader_io_get_unique_index(i);
2971 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2972 LLVMConstInt(ctx->ac.i32, param * 4, false),
2973 "");
2974 for (unsigned j = 0; j < length; j++) {
2975 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2976 value = ac_to_integer(&ctx->ac, value);
2977 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2978 ac_lds_store(&ctx->ac, dw_addr, value);
2979 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2980 }
2981 }
2982 }
2983
2984 static void
2985 write_tess_factors(struct radv_shader_context *ctx)
2986 {
2987 unsigned stride, outer_comps, inner_comps;
2988 struct ac_build_if_state if_ctx, inner_if_ctx;
2989 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2990 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2991 unsigned tess_inner_index = 0, tess_outer_index;
2992 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2993 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2994 int i;
2995 ac_emit_barrier(&ctx->ac, ctx->stage);
2996
2997 switch (ctx->options->key.tcs.primitive_mode) {
2998 case GL_ISOLINES:
2999 stride = 2;
3000 outer_comps = 2;
3001 inner_comps = 0;
3002 break;
3003 case GL_TRIANGLES:
3004 stride = 4;
3005 outer_comps = 3;
3006 inner_comps = 1;
3007 break;
3008 case GL_QUADS:
3009 stride = 6;
3010 outer_comps = 4;
3011 inner_comps = 2;
3012 break;
3013 default:
3014 return;
3015 }
3016
3017 ac_nir_build_if(&if_ctx, ctx,
3018 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3019 invocation_id, ctx->ac.i32_0, ""));
3020
3021 lds_base = get_tcs_out_current_patch_data_offset(ctx);
3022
3023 if (inner_comps) {
3024 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3025 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3026 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3027 }
3028
3029 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3030 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3031 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3032
3033 for (i = 0; i < 4; i++) {
3034 inner[i] = LLVMGetUndef(ctx->ac.i32);
3035 outer[i] = LLVMGetUndef(ctx->ac.i32);
3036 }
3037
3038 // LINES reversal
3039 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
3040 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3041 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3042 ctx->ac.i32_1, "");
3043 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3044 } else {
3045 for (i = 0; i < outer_comps; i++) {
3046 outer[i] = out[i] =
3047 ac_lds_load(&ctx->ac, lds_outer);
3048 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3049 ctx->ac.i32_1, "");
3050 }
3051 for (i = 0; i < inner_comps; i++) {
3052 inner[i] = out[outer_comps+i] =
3053 ac_lds_load(&ctx->ac, lds_inner);
3054 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3055 ctx->ac.i32_1, "");
3056 }
3057 }
3058
3059 /* Convert the outputs to vectors for stores. */
3060 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3061 vec1 = NULL;
3062
3063 if (stride > 4)
3064 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3065
3066
3067 buffer = ctx->hs_ring_tess_factor;
3068 tf_base = ctx->tess_factor_offset;
3069 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3070 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3071 unsigned tf_offset = 0;
3072
3073 if (ctx->options->chip_class <= VI) {
3074 ac_nir_build_if(&inner_if_ctx, ctx,
3075 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3076 rel_patch_id, ctx->ac.i32_0, ""));
3077
3078 /* Store the dynamic HS control word. */
3079 ac_build_buffer_store_dword(&ctx->ac, buffer,
3080 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3081 1, ctx->ac.i32_0, tf_base,
3082 0, 1, 0, true, false);
3083 tf_offset += 4;
3084
3085 ac_nir_build_endif(&inner_if_ctx);
3086 }
3087
3088 /* Store the tessellation factors. */
3089 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3090 MIN2(stride, 4), byteoffset, tf_base,
3091 tf_offset, 1, 0, true, false);
3092 if (vec1)
3093 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3094 stride - 4, byteoffset, tf_base,
3095 16 + tf_offset, 1, 0, true, false);
3096
3097 //store to offchip for TES to read - only if TES reads them
3098 if (ctx->options->key.tcs.tes_reads_tess_factors) {
3099 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3100 LLVMValueRef tf_inner_offset;
3101 unsigned param_outer, param_inner;
3102
3103 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3104 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3105 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3106
3107 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3108 util_next_power_of_two(outer_comps));
3109
3110 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3111 outer_comps, tf_outer_offset,
3112 ctx->oc_lds, 0, 1, 0, true, false);
3113 if (inner_comps) {
3114 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3115 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3116 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3117
3118 inner_vec = inner_comps == 1 ? inner[0] :
3119 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3120 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3121 inner_comps, tf_inner_offset,
3122 ctx->oc_lds, 0, 1, 0, true, false);
3123 }
3124 }
3125 ac_nir_build_endif(&if_ctx);
3126 }
3127
3128 static void
3129 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3130 {
3131 write_tess_factors(ctx);
3132 }
3133
3134 static bool
3135 si_export_mrt_color(struct radv_shader_context *ctx,
3136 LLVMValueRef *color, unsigned index,
3137 struct ac_export_args *args)
3138 {
3139 /* Export */
3140 si_llvm_init_export_args(ctx, color, 0xf,
3141 V_008DFC_SQ_EXP_MRT + index, args);
3142 if (!args->enabled_channels)
3143 return false; /* unnecessary NULL export */
3144
3145 return true;
3146 }
3147
3148 static void
3149 radv_export_mrt_z(struct radv_shader_context *ctx,
3150 LLVMValueRef depth, LLVMValueRef stencil,
3151 LLVMValueRef samplemask)
3152 {
3153 struct ac_export_args args;
3154
3155 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3156
3157 ac_build_export(&ctx->ac, &args);
3158 }
3159
3160 static void
3161 handle_fs_outputs_post(struct radv_shader_context *ctx)
3162 {
3163 unsigned index = 0;
3164 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3165 struct ac_export_args color_args[8];
3166
3167 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3168 LLVMValueRef values[4];
3169
3170 if (!(ctx->output_mask & (1ull << i)))
3171 continue;
3172
3173 if (i < FRAG_RESULT_DATA0)
3174 continue;
3175
3176 for (unsigned j = 0; j < 4; j++)
3177 values[j] = ac_to_float(&ctx->ac,
3178 radv_load_output(ctx, i, j));
3179
3180 bool ret = si_export_mrt_color(ctx, values,
3181 i - FRAG_RESULT_DATA0,
3182 &color_args[index]);
3183 if (ret)
3184 index++;
3185 }
3186
3187 /* Process depth, stencil, samplemask. */
3188 if (ctx->shader_info->info.ps.writes_z) {
3189 depth = ac_to_float(&ctx->ac,
3190 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3191 }
3192 if (ctx->shader_info->info.ps.writes_stencil) {
3193 stencil = ac_to_float(&ctx->ac,
3194 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3195 }
3196 if (ctx->shader_info->info.ps.writes_sample_mask) {
3197 samplemask = ac_to_float(&ctx->ac,
3198 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3199 }
3200
3201 /* Set the DONE bit on last non-null color export only if Z isn't
3202 * exported.
3203 */
3204 if (index > 0 &&
3205 !ctx->shader_info->info.ps.writes_z &&
3206 !ctx->shader_info->info.ps.writes_stencil &&
3207 !ctx->shader_info->info.ps.writes_sample_mask) {
3208 unsigned last = index - 1;
3209
3210 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3211 color_args[last].done = 1; /* DONE bit */
3212 }
3213
3214 /* Export PS outputs. */
3215 for (unsigned i = 0; i < index; i++)
3216 ac_build_export(&ctx->ac, &color_args[i]);
3217
3218 if (depth || stencil || samplemask)
3219 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3220 else if (!index)
3221 ac_build_export_null(&ctx->ac);
3222 }
3223
3224 static void
3225 emit_gs_epilogue(struct radv_shader_context *ctx)
3226 {
3227 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3228 }
3229
3230 static void
3231 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3232 LLVMValueRef *addrs)
3233 {
3234 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3235
3236 switch (ctx->stage) {
3237 case MESA_SHADER_VERTEX:
3238 if (ctx->options->key.vs.as_ls)
3239 handle_ls_outputs_post(ctx);
3240 else if (ctx->options->key.vs.as_es)
3241 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
3242 else
3243 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
3244 ctx->options->key.vs.export_layer_id,
3245 &ctx->shader_info->vs.outinfo);
3246 break;
3247 case MESA_SHADER_FRAGMENT:
3248 handle_fs_outputs_post(ctx);
3249 break;
3250 case MESA_SHADER_GEOMETRY:
3251 emit_gs_epilogue(ctx);
3252 break;
3253 case MESA_SHADER_TESS_CTRL:
3254 handle_tcs_outputs_post(ctx);
3255 break;
3256 case MESA_SHADER_TESS_EVAL:
3257 if (ctx->options->key.tes.as_es)
3258 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
3259 else
3260 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
3261 ctx->options->key.tes.export_layer_id,
3262 &ctx->shader_info->tes.outinfo);
3263 break;
3264 default:
3265 break;
3266 }
3267 }
3268
3269 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3270 LLVMPassManagerRef passmgr,
3271 const struct radv_nir_compiler_options *options)
3272 {
3273 LLVMRunPassManager(passmgr, ctx->ac.module);
3274 LLVMDisposeBuilder(ctx->ac.builder);
3275
3276 ac_llvm_context_dispose(&ctx->ac);
3277 }
3278
3279 static void
3280 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3281 {
3282 struct radv_vs_output_info *outinfo;
3283
3284 switch (ctx->stage) {
3285 case MESA_SHADER_FRAGMENT:
3286 case MESA_SHADER_COMPUTE:
3287 case MESA_SHADER_TESS_CTRL:
3288 case MESA_SHADER_GEOMETRY:
3289 return;
3290 case MESA_SHADER_VERTEX:
3291 if (ctx->options->key.vs.as_ls ||
3292 ctx->options->key.vs.as_es)
3293 return;
3294 outinfo = &ctx->shader_info->vs.outinfo;
3295 break;
3296 case MESA_SHADER_TESS_EVAL:
3297 if (ctx->options->key.vs.as_es)
3298 return;
3299 outinfo = &ctx->shader_info->tes.outinfo;
3300 break;
3301 default:
3302 unreachable("Unhandled shader type");
3303 }
3304
3305 ac_optimize_vs_outputs(&ctx->ac,
3306 ctx->main_function,
3307 outinfo->vs_output_param_offset,
3308 VARYING_SLOT_MAX,
3309 &outinfo->param_exports);
3310 }
3311
3312 static void
3313 ac_setup_rings(struct radv_shader_context *ctx)
3314 {
3315 if (ctx->options->chip_class <= VI &&
3316 (ctx->stage == MESA_SHADER_GEOMETRY ||
3317 ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
3318 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3319 : RING_ESGS_VS;
3320 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3321
3322 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3323 ctx->ring_offsets,
3324 offset);
3325 }
3326
3327 if (ctx->is_gs_copy_shader) {
3328 ctx->gsvs_ring[0] =
3329 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3330 LLVMConstInt(ctx->ac.i32,
3331 RING_GSVS_VS, false));
3332 }
3333
3334 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3335 /* The conceptual layout of the GSVS ring is
3336 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3337 * but the real memory layout is swizzled across
3338 * threads:
3339 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3340 * t16v0c0 ..
3341 * Override the buffer descriptor accordingly.
3342 */
3343 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3344 uint64_t stream_offset = 0;
3345 unsigned num_records = 64;
3346 LLVMValueRef base_ring;
3347
3348 base_ring =
3349 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3350 LLVMConstInt(ctx->ac.i32,
3351 RING_GSVS_GS, false));
3352
3353 for (unsigned stream = 0; stream < 4; stream++) {
3354 unsigned num_components, stride;
3355 LLVMValueRef ring, tmp;
3356
3357 num_components =
3358 ctx->shader_info->info.gs.num_stream_output_components[stream];
3359
3360 if (!num_components)
3361 continue;
3362
3363 stride = 4 * num_components * ctx->gs_max_out_vertices;
3364
3365 /* Limit on the stride field for <= CIK. */
3366 assert(stride < (1 << 14));
3367
3368 ring = LLVMBuildBitCast(ctx->ac.builder,
3369 base_ring, v2i64, "");
3370 tmp = LLVMBuildExtractElement(ctx->ac.builder,
3371 ring, ctx->ac.i32_0, "");
3372 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
3373 LLVMConstInt(ctx->ac.i64,
3374 stream_offset, 0), "");
3375 ring = LLVMBuildInsertElement(ctx->ac.builder,
3376 ring, tmp, ctx->ac.i32_0, "");
3377
3378 stream_offset += stride * 64;
3379
3380 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
3381 ctx->ac.v4i32, "");
3382
3383 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3384 ctx->ac.i32_1, "");
3385 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3386 LLVMConstInt(ctx->ac.i32,
3387 S_008F04_STRIDE(stride), false), "");
3388 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3389 ctx->ac.i32_1, "");
3390
3391 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3392 LLVMConstInt(ctx->ac.i32,
3393 num_records, false),
3394 LLVMConstInt(ctx->ac.i32, 2, false), "");
3395
3396 ctx->gsvs_ring[stream] = ring;
3397 }
3398 }
3399
3400 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3401 ctx->stage == MESA_SHADER_TESS_EVAL) {
3402 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3403 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3404 }
3405 }
3406
3407 static unsigned
3408 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
3409 const struct nir_shader *nir)
3410 {
3411 switch (nir->info.stage) {
3412 case MESA_SHADER_TESS_CTRL:
3413 return chip_class >= CIK ? 128 : 64;
3414 case MESA_SHADER_GEOMETRY:
3415 return chip_class >= GFX9 ? 128 : 64;
3416 case MESA_SHADER_COMPUTE:
3417 break;
3418 default:
3419 return 0;
3420 }
3421
3422 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
3423 nir->info.cs.local_size[1] *
3424 nir->info.cs.local_size[2];
3425 return max_workgroup_size;
3426 }
3427
3428 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3429 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3430 {
3431 LLVMValueRef count = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
3432 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3433 ctx->ac.i32_0, "");
3434 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
3435 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
3436 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3437 }
3438
3439 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3440 {
3441 for(int i = 5; i >= 0; --i) {
3442 ctx->gs_vtx_offset[i] = ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3443 (i & 1) * 16, 16);
3444 }
3445
3446 ctx->gs_wave_id = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 16, 8);
3447 }
3448
3449
3450 static
3451 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
3452 struct nir_shader *const *shaders,
3453 int shader_count,
3454 struct radv_shader_variant_info *shader_info,
3455 const struct radv_nir_compiler_options *options)
3456 {
3457 struct radv_shader_context ctx = {0};
3458 unsigned i;
3459 ctx.options = options;
3460 ctx.shader_info = shader_info;
3461
3462 ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
3463 ctx.context = ctx.ac.context;
3464 ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
3465
3466 enum ac_float_mode float_mode =
3467 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3468 AC_FLOAT_MODE_DEFAULT;
3469
3470 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3471
3472 memset(shader_info, 0, sizeof(*shader_info));
3473
3474 for(int i = 0; i < shader_count; ++i)
3475 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3476
3477 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3478 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3479 for (i = 0; i < AC_UD_MAX_UD; i++)
3480 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3481
3482 ctx.max_workgroup_size = 0;
3483 for (int i = 0; i < shader_count; ++i) {
3484 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3485 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3486 shaders[i]));
3487 }
3488
3489 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3490 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3491
3492 ctx.abi.inputs = &ctx.inputs[0];
3493 ctx.abi.emit_outputs = handle_shader_outputs_post;
3494 ctx.abi.emit_vertex = visit_emit_vertex;
3495 ctx.abi.load_ubo = radv_load_ubo;
3496 ctx.abi.load_ssbo = radv_load_ssbo;
3497 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3498 ctx.abi.load_resource = radv_load_resource;
3499 ctx.abi.clamp_shadow_reference = false;
3500 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9 && HAVE_LLVM < 0x800;
3501
3502 if (shader_count >= 2)
3503 ac_init_exec_full_mask(&ctx.ac);
3504
3505 if (ctx.ac.chip_class == GFX9 &&
3506 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3507 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3508
3509 for(int i = 0; i < shader_count; ++i) {
3510 ctx.stage = shaders[i]->info.stage;
3511 ctx.output_mask = 0;
3512
3513 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3514 for (int i = 0; i < 4; i++) {
3515 ctx.gs_next_vertex[i] =
3516 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
3517 }
3518 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3519 ctx.abi.load_inputs = load_gs_input;
3520 ctx.abi.emit_primitive = visit_end_primitive;
3521 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3522 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3523 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3524 ctx.abi.load_tess_varyings = load_tcs_varyings;
3525 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3526 ctx.abi.store_tcs_outputs = store_tcs_output;
3527 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3528 if (shader_count == 1)
3529 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3530 else
3531 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3532 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3533 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3534 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3535 ctx.abi.load_tess_varyings = load_tes_input;
3536 ctx.abi.load_tess_coord = load_tess_coord;
3537 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3538 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3539 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3540 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3541 if (shader_info->info.vs.needs_instance_id) {
3542 if (ctx.options->key.vs.as_ls) {
3543 ctx.shader_info->vs.vgpr_comp_cnt =
3544 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3545 } else {
3546 ctx.shader_info->vs.vgpr_comp_cnt =
3547 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3548 }
3549 }
3550 ctx.abi.load_base_vertex = radv_load_base_vertex;
3551 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3552 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3553 ctx.abi.lookup_interp_param = lookup_interp_param;
3554 ctx.abi.load_sample_position = load_sample_position;
3555 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3556 ctx.abi.emit_kill = radv_emit_kill;
3557 }
3558
3559 if (i)
3560 ac_emit_barrier(&ctx.ac, ctx.stage);
3561
3562 nir_foreach_variable(variable, &shaders[i]->outputs)
3563 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3564
3565 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3566 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3567 shaders[i]->info.cull_distance_array_size > 4;
3568 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3569 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3570 shaders[i]->info.gs.vertices_out;
3571 }
3572
3573 ac_setup_rings(&ctx);
3574
3575 LLVMBasicBlockRef merge_block;
3576 if (shader_count >= 2) {
3577 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3578 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3579 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3580
3581 LLVMValueRef count = ac_unpack_param(&ctx.ac, ctx.merged_wave_info, 8 * i, 8);
3582 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3583 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3584 thread_id, count, "");
3585 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3586
3587 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3588 }
3589
3590 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3591 handle_fs_inputs(&ctx, shaders[i]);
3592 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3593 handle_vs_inputs(&ctx, shaders[i]);
3594 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3595 prepare_gs_input_vgprs(&ctx);
3596
3597 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3598
3599 if (shader_count >= 2) {
3600 LLVMBuildBr(ctx.ac.builder, merge_block);
3601 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3602 }
3603
3604 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3605 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3606 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3607 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3608 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3609 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3610 }
3611 }
3612
3613 LLVMBuildRetVoid(ctx.ac.builder);
3614
3615 if (options->dump_preoptir)
3616 ac_dump_module(ctx.ac.module);
3617
3618 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
3619
3620 if (shader_count == 1)
3621 ac_nir_eliminate_const_vs_outputs(&ctx);
3622
3623 if (options->dump_shader) {
3624 ctx.shader_info->private_mem_vgprs =
3625 ac_count_scratch_private_memory(ctx.main_function);
3626 }
3627
3628 return ctx.ac.module;
3629 }
3630
3631 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3632 {
3633 unsigned *retval = (unsigned *)context;
3634 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3635 char *description = LLVMGetDiagInfoDescription(di);
3636
3637 if (severity == LLVMDSError) {
3638 *retval = 1;
3639 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3640 description);
3641 }
3642
3643 LLVMDisposeMessage(description);
3644 }
3645
3646 static unsigned ac_llvm_compile(LLVMModuleRef M,
3647 struct ac_shader_binary *binary,
3648 struct ac_llvm_compiler *ac_llvm)
3649 {
3650 unsigned retval = 0;
3651 LLVMContextRef llvm_ctx;
3652
3653 /* Setup Diagnostic Handler*/
3654 llvm_ctx = LLVMGetModuleContext(M);
3655
3656 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3657 &retval);
3658
3659 /* Compile IR*/
3660 if (!radv_compile_to_binary(ac_llvm, M, binary))
3661 retval = 1;
3662 return retval;
3663 }
3664
3665 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
3666 LLVMModuleRef llvm_module,
3667 struct ac_shader_binary *binary,
3668 struct ac_shader_config *config,
3669 struct radv_shader_variant_info *shader_info,
3670 gl_shader_stage stage,
3671 const struct radv_nir_compiler_options *options)
3672 {
3673 if (options->dump_shader)
3674 ac_dump_module(llvm_module);
3675
3676 memset(binary, 0, sizeof(*binary));
3677
3678 if (options->record_llvm_ir) {
3679 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3680 binary->llvm_ir_string = strdup(llvm_ir);
3681 LLVMDisposeMessage(llvm_ir);
3682 }
3683
3684 int v = ac_llvm_compile(llvm_module, binary, ac_llvm);
3685 if (v) {
3686 fprintf(stderr, "compile failed\n");
3687 }
3688
3689 if (options->dump_shader)
3690 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3691
3692 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3693
3694 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3695 LLVMDisposeModule(llvm_module);
3696 LLVMContextDispose(ctx);
3697
3698 if (stage == MESA_SHADER_FRAGMENT) {
3699 shader_info->num_input_vgprs = 0;
3700 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3701 shader_info->num_input_vgprs += 2;
3702 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3703 shader_info->num_input_vgprs += 2;
3704 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3705 shader_info->num_input_vgprs += 2;
3706 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3707 shader_info->num_input_vgprs += 3;
3708 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3709 shader_info->num_input_vgprs += 2;
3710 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3711 shader_info->num_input_vgprs += 2;
3712 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3713 shader_info->num_input_vgprs += 2;
3714 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3715 shader_info->num_input_vgprs += 1;
3716 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3717 shader_info->num_input_vgprs += 1;
3718 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3719 shader_info->num_input_vgprs += 1;
3720 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3721 shader_info->num_input_vgprs += 1;
3722 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3723 shader_info->num_input_vgprs += 1;
3724 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3725 shader_info->num_input_vgprs += 1;
3726 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3727 shader_info->num_input_vgprs += 1;
3728 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3729 shader_info->num_input_vgprs += 1;
3730 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3731 shader_info->num_input_vgprs += 1;
3732 }
3733 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3734
3735 /* +3 for scratch wave offset and VCC */
3736 config->num_sgprs = MAX2(config->num_sgprs,
3737 shader_info->num_input_sgprs + 3);
3738
3739 /* Enable 64-bit and 16-bit denormals, because there is no performance
3740 * cost.
3741 *
3742 * If denormals are enabled, all floating-point output modifiers are
3743 * ignored.
3744 *
3745 * Don't enable denormals for 32-bit floats, because:
3746 * - Floating-point output modifiers would be ignored by the hw.
3747 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3748 * have to stop using those.
3749 * - SI & CI would be very slow.
3750 */
3751 config->float_mode |= V_00B028_FP_64_DENORMS;
3752 }
3753
3754 static void
3755 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3756 {
3757 switch (nir->info.stage) {
3758 case MESA_SHADER_COMPUTE:
3759 for (int i = 0; i < 3; ++i)
3760 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3761 break;
3762 case MESA_SHADER_FRAGMENT:
3763 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3764 break;
3765 case MESA_SHADER_GEOMETRY:
3766 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3767 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3768 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3769 shader_info->gs.invocations = nir->info.gs.invocations;
3770 break;
3771 case MESA_SHADER_TESS_EVAL:
3772 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3773 shader_info->tes.spacing = nir->info.tess.spacing;
3774 shader_info->tes.ccw = nir->info.tess.ccw;
3775 shader_info->tes.point_mode = nir->info.tess.point_mode;
3776 shader_info->tes.as_es = options->key.tes.as_es;
3777 break;
3778 case MESA_SHADER_TESS_CTRL:
3779 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3780 break;
3781 case MESA_SHADER_VERTEX:
3782 shader_info->vs.as_es = options->key.vs.as_es;
3783 shader_info->vs.as_ls = options->key.vs.as_ls;
3784 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3785 if (options->key.vs.as_ls)
3786 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3787 break;
3788 default:
3789 break;
3790 }
3791 }
3792
3793 void
3794 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
3795 struct ac_shader_binary *binary,
3796 struct ac_shader_config *config,
3797 struct radv_shader_variant_info *shader_info,
3798 struct nir_shader *const *nir,
3799 int nir_count,
3800 const struct radv_nir_compiler_options *options)
3801 {
3802
3803 LLVMModuleRef llvm_module;
3804
3805 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, shader_info,
3806 options);
3807
3808 ac_compile_llvm_module(ac_llvm, llvm_module, binary, config, shader_info,
3809 nir[0]->info.stage, options);
3810
3811 for (int i = 0; i < nir_count; ++i)
3812 ac_fill_shader_info(shader_info, nir[i], options);
3813
3814 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3815 if (options->chip_class == GFX9) {
3816 if (nir_count == 2 &&
3817 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3818 shader_info->gs.es_type = nir[0]->info.stage;
3819 }
3820 }
3821 }
3822
3823 static void
3824 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3825 {
3826 LLVMValueRef vtx_offset =
3827 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3828 LLVMConstInt(ctx->ac.i32, 4, false), "");
3829 LLVMValueRef stream_id;
3830
3831 /* Fetch the vertex stream ID. */
3832 if (ctx->shader_info->info.so.num_outputs) {
3833 stream_id =
3834 ac_unpack_param(&ctx->ac, ctx->streamout_config, 24, 2);
3835 } else {
3836 stream_id = ctx->ac.i32_0;
3837 }
3838
3839 LLVMBasicBlockRef end_bb;
3840 LLVMValueRef switch_inst;
3841
3842 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
3843 ctx->main_function, "end");
3844 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
3845
3846 for (unsigned stream = 0; stream < 4; stream++) {
3847 unsigned num_components =
3848 ctx->shader_info->info.gs.num_stream_output_components[stream];
3849 LLVMBasicBlockRef bb;
3850 unsigned offset;
3851
3852 if (!num_components)
3853 continue;
3854
3855 if (stream > 0 && !ctx->shader_info->info.so.num_outputs)
3856 continue;
3857
3858 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
3859 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
3860 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
3861
3862 offset = 0;
3863 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3864 unsigned output_usage_mask =
3865 ctx->shader_info->info.gs.output_usage_mask[i];
3866 unsigned output_stream =
3867 ctx->shader_info->info.gs.output_streams[i];
3868 int length = util_last_bit(output_usage_mask);
3869
3870 if (!(ctx->output_mask & (1ull << i)) ||
3871 output_stream != stream)
3872 continue;
3873
3874 for (unsigned j = 0; j < length; j++) {
3875 LLVMValueRef value, soffset;
3876
3877 if (!(output_usage_mask & (1 << j)))
3878 continue;
3879
3880 soffset = LLVMConstInt(ctx->ac.i32,
3881 offset *
3882 ctx->gs_max_out_vertices * 16 * 4, false);
3883
3884 offset++;
3885
3886 value = ac_build_buffer_load(&ctx->ac,
3887 ctx->gsvs_ring[0],
3888 1, ctx->ac.i32_0,
3889 vtx_offset, soffset,
3890 0, 1, 1, true, false);
3891
3892 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3893 if (ac_get_type_size(type) == 2) {
3894 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
3895 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
3896 }
3897
3898 LLVMBuildStore(ctx->ac.builder,
3899 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3900 }
3901 }
3902
3903 if (ctx->shader_info->info.so.num_outputs)
3904 radv_emit_streamout(ctx, stream);
3905
3906 if (stream == 0) {
3907 handle_vs_outputs_post(ctx, false, false,
3908 &ctx->shader_info->vs.outinfo);
3909 }
3910
3911 LLVMBuildBr(ctx->ac.builder, end_bb);
3912 }
3913
3914 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
3915 }
3916
3917 void
3918 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
3919 struct nir_shader *geom_shader,
3920 struct ac_shader_binary *binary,
3921 struct ac_shader_config *config,
3922 struct radv_shader_variant_info *shader_info,
3923 const struct radv_nir_compiler_options *options)
3924 {
3925 struct radv_shader_context ctx = {0};
3926 ctx.options = options;
3927 ctx.shader_info = shader_info;
3928
3929 ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
3930 ctx.context = ctx.ac.context;
3931 ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
3932
3933 ctx.is_gs_copy_shader = true;
3934
3935 enum ac_float_mode float_mode =
3936 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3937 AC_FLOAT_MODE_DEFAULT;
3938
3939 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3940 ctx.stage = MESA_SHADER_VERTEX;
3941
3942 radv_nir_shader_info_pass(geom_shader, options, &shader_info->info);
3943
3944 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3945
3946 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3947 ac_setup_rings(&ctx);
3948
3949 nir_foreach_variable(variable, &geom_shader->outputs) {
3950 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3951 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3952 variable, MESA_SHADER_VERTEX);
3953 }
3954
3955 ac_gs_copy_shader_emit(&ctx);
3956
3957 LLVMBuildRetVoid(ctx.ac.builder);
3958
3959 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
3960
3961 ac_compile_llvm_module(ac_llvm, ctx.ac.module, binary, config, shader_info,
3962 MESA_SHADER_VERTEX, options);
3963 }