2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
38 #include "ac_binary.h"
39 #include "ac_llvm_util.h"
40 #include "ac_llvm_build.h"
41 #include "ac_shader_abi.h"
42 #include "ac_shader_util.h"
43 #include "ac_exp_param.h"
45 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 struct radv_shader_context
{
48 struct ac_llvm_context ac
;
49 const struct radv_nir_compiler_options
*options
;
50 struct radv_shader_variant_info
*shader_info
;
51 struct ac_shader_abi abi
;
53 unsigned max_workgroup_size
;
54 LLVMContextRef context
;
55 LLVMValueRef main_function
;
57 LLVMValueRef descriptor_sets
[RADV_UD_MAX_SETS
];
58 LLVMValueRef ring_offsets
;
60 LLVMValueRef vertex_buffers
;
61 LLVMValueRef rel_auto_id
;
62 LLVMValueRef vs_prim_id
;
63 LLVMValueRef es2gs_offset
;
66 LLVMValueRef merged_wave_info
;
67 LLVMValueRef tess_factor_offset
;
68 LLVMValueRef tes_rel_patch_id
;
72 LLVMValueRef gs2vs_offset
;
73 LLVMValueRef gs_wave_id
;
74 LLVMValueRef gs_vtx_offset
[6];
76 LLVMValueRef esgs_ring
;
77 LLVMValueRef gsvs_ring
;
78 LLVMValueRef hs_ring_tess_offchip
;
79 LLVMValueRef hs_ring_tess_factor
;
81 LLVMValueRef sample_pos_offset
;
82 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
83 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
85 gl_shader_stage stage
;
87 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
91 uint8_t num_output_clips
;
92 uint8_t num_output_culls
;
94 bool is_gs_copy_shader
;
95 LLVMValueRef gs_next_vertex
;
96 unsigned gs_max_out_vertices
;
98 unsigned tes_primitive_mode
;
100 uint32_t tcs_patch_outputs_read
;
101 uint64_t tcs_outputs_read
;
102 uint32_t tcs_vertices_per_patch
;
103 uint32_t tcs_num_inputs
;
104 uint32_t tcs_num_patches
;
105 uint32_t max_gsvs_emit_size
;
106 uint32_t gsvs_vertex_size
;
109 enum radeon_llvm_calling_convention
{
110 RADEON_LLVM_AMDGPU_VS
= 87,
111 RADEON_LLVM_AMDGPU_GS
= 88,
112 RADEON_LLVM_AMDGPU_PS
= 89,
113 RADEON_LLVM_AMDGPU_CS
= 90,
114 RADEON_LLVM_AMDGPU_HS
= 93,
117 static inline struct radv_shader_context
*
118 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
120 struct radv_shader_context
*ctx
= NULL
;
121 return container_of(abi
, ctx
, abi
);
124 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
126 switch (ctx
->stage
) {
127 case MESA_SHADER_TESS_CTRL
:
128 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
129 case MESA_SHADER_TESS_EVAL
:
130 return ctx
->tes_rel_patch_id
;
133 unreachable("Illegal stage");
138 get_tcs_num_patches(struct radv_shader_context
*ctx
)
140 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
141 unsigned num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
142 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
143 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
144 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
145 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
146 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
147 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
148 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
149 unsigned num_patches
;
150 unsigned hardware_lds_size
;
152 /* Ensure that we only need one wave per SIMD so we don't need to check
153 * resource usage. Also ensures that the number of tcs in and out
154 * vertices per threadgroup are at most 256.
156 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
157 /* Make sure that the data fits in LDS. This assumes the shaders only
158 * use LDS for the inputs and outputs.
160 hardware_lds_size
= ctx
->options
->chip_class
>= CIK
? 65536 : 32768;
161 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
162 /* Make sure the output data fits in the offchip buffer */
163 num_patches
= MIN2(num_patches
, (ctx
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
164 /* Not necessary for correctness, but improves performance. The
165 * specific value is taken from the proprietary driver.
167 num_patches
= MIN2(num_patches
, 40);
169 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
170 if (ctx
->options
->chip_class
== SI
) {
171 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
172 num_patches
= MIN2(num_patches
, one_wave
);
178 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
180 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
181 unsigned num_tcs_output_cp
;
182 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
183 unsigned input_vertex_size
, output_vertex_size
;
184 unsigned input_patch_size
, output_patch_size
;
185 unsigned pervertex_output_patch_size
;
186 unsigned output_patch0_offset
;
187 unsigned num_patches
;
190 num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
191 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
192 num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
194 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
195 output_vertex_size
= num_tcs_outputs
* 16;
197 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
199 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
200 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
202 num_patches
= ctx
->tcs_num_patches
;
203 output_patch0_offset
= input_patch_size
* num_patches
;
205 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
209 /* Tessellation shaders pass outputs to the next shader using LDS.
211 * LS outputs = TCS inputs
212 * TCS outputs = TES inputs
215 * - TCS inputs for patch 0
216 * - TCS inputs for patch 1
217 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
219 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
220 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
221 * - TCS outputs for patch 1
222 * - Per-patch TCS outputs for patch 1
223 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
224 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
227 * All three shaders VS(LS), TCS, TES share the same LDS space.
230 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
232 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
233 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
234 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
236 input_patch_size
/= 4;
237 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
241 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
243 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
244 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
245 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
246 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
247 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
248 output_patch_size
/= 4;
249 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
253 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
255 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
256 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
257 output_vertex_size
/= 4;
258 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
262 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
264 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
265 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
266 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
267 uint32_t output_patch0_offset
= input_patch_size
;
268 unsigned num_patches
= ctx
->tcs_num_patches
;
270 output_patch0_offset
*= num_patches
;
271 output_patch0_offset
/= 4;
272 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
276 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
278 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
279 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
280 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
281 uint32_t output_patch0_offset
= input_patch_size
;
283 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
284 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
285 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
286 unsigned num_patches
= ctx
->tcs_num_patches
;
288 output_patch0_offset
*= num_patches
;
289 output_patch0_offset
+= pervertex_output_patch_size
;
290 output_patch0_offset
/= 4;
291 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
295 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
297 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
298 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
300 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
304 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
306 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
307 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
308 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
310 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_offset
,
311 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
317 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
319 LLVMValueRef patch0_patch_data_offset
=
320 get_tcs_out_patch0_patch_data_offset(ctx
);
321 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
322 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
324 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_patch_data_offset
,
325 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
332 LLVMTypeRef types
[MAX_ARGS
];
333 LLVMValueRef
*assign
[MAX_ARGS
];
334 unsigned array_params_mask
;
337 uint8_t num_sgprs_used
;
338 uint8_t num_vgprs_used
;
341 enum ac_arg_regfile
{
347 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
348 LLVMValueRef
*param_ptr
)
350 assert(info
->count
< MAX_ARGS
);
352 info
->assign
[info
->count
] = param_ptr
;
353 info
->types
[info
->count
] = type
;
356 if (regfile
== ARG_SGPR
) {
357 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
360 assert(regfile
== ARG_VGPR
);
361 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
366 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
368 info
->array_params_mask
|= (1 << info
->count
);
369 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
372 static void assign_arguments(LLVMValueRef main_function
,
373 struct arg_info
*info
)
376 for (i
= 0; i
< info
->count
; i
++) {
378 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
383 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
384 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
385 unsigned num_return_elems
,
386 struct arg_info
*args
,
387 unsigned max_workgroup_size
,
390 LLVMTypeRef main_function_type
, ret_type
;
391 LLVMBasicBlockRef main_function_body
;
393 if (num_return_elems
)
394 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
395 num_return_elems
, true);
397 ret_type
= LLVMVoidTypeInContext(ctx
);
399 /* Setup the function */
401 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
402 LLVMValueRef main_function
=
403 LLVMAddFunction(module
, "main", main_function_type
);
405 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
406 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
408 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
409 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
410 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
412 if (args
->array_params_mask
& (1 << i
)) {
413 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
414 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
415 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
419 if (max_workgroup_size
) {
420 ac_llvm_add_target_dep_function_attr(main_function
,
421 "amdgpu-max-work-group-size",
425 /* These were copied from some LLVM test. */
426 LLVMAddTargetDependentFunctionAttr(main_function
,
427 "less-precise-fpmad",
429 LLVMAddTargetDependentFunctionAttr(main_function
,
432 LLVMAddTargetDependentFunctionAttr(main_function
,
435 LLVMAddTargetDependentFunctionAttr(main_function
,
438 LLVMAddTargetDependentFunctionAttr(main_function
,
439 "no-signed-zeros-fp-math",
442 return main_function
;
447 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
,
448 uint32_t indirect_offset
)
450 ud_info
->sgpr_idx
= *sgpr_idx
;
451 ud_info
->num_sgprs
= num_sgprs
;
452 ud_info
->indirect
= indirect_offset
> 0;
453 ud_info
->indirect_offset
= indirect_offset
;
454 *sgpr_idx
+= num_sgprs
;
458 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
461 struct radv_userdata_info
*ud_info
=
462 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
465 set_loc(ud_info
, sgpr_idx
, num_sgprs
, 0);
469 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
470 uint32_t indirect_offset
)
472 struct radv_userdata_info
*ud_info
=
473 &ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[idx
];
476 set_loc(ud_info
, sgpr_idx
, 2, indirect_offset
);
479 struct user_sgpr_info
{
480 bool need_ring_offsets
;
482 bool indirect_all_descriptor_sets
;
485 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
486 gl_shader_stage stage
)
489 case MESA_SHADER_VERTEX
:
490 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
491 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
494 case MESA_SHADER_TESS_EVAL
:
495 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
498 case MESA_SHADER_GEOMETRY
:
499 case MESA_SHADER_TESS_CTRL
:
500 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
510 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
514 count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
515 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
520 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
521 gl_shader_stage stage
,
522 bool has_previous_stage
,
523 gl_shader_stage previous_stage
,
524 bool needs_view_index
,
525 struct user_sgpr_info
*user_sgpr_info
)
527 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
529 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
530 if (stage
== MESA_SHADER_GEOMETRY
||
531 stage
== MESA_SHADER_VERTEX
||
532 stage
== MESA_SHADER_TESS_CTRL
||
533 stage
== MESA_SHADER_TESS_EVAL
||
534 ctx
->is_gs_copy_shader
)
535 user_sgpr_info
->need_ring_offsets
= true;
537 if (stage
== MESA_SHADER_FRAGMENT
&&
538 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
539 user_sgpr_info
->need_ring_offsets
= true;
541 /* 2 user sgprs will nearly always be allocated for scratch/rings */
542 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
543 user_sgpr_info
->sgpr_count
+= 2;
547 case MESA_SHADER_COMPUTE
:
548 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
549 user_sgpr_info
->sgpr_count
+= 3;
551 case MESA_SHADER_FRAGMENT
:
552 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
554 case MESA_SHADER_VERTEX
:
555 if (!ctx
->is_gs_copy_shader
)
556 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
558 case MESA_SHADER_TESS_CTRL
:
559 if (has_previous_stage
) {
560 if (previous_stage
== MESA_SHADER_VERTEX
)
561 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
564 case MESA_SHADER_TESS_EVAL
:
566 case MESA_SHADER_GEOMETRY
:
567 if (has_previous_stage
) {
568 if (previous_stage
== MESA_SHADER_VERTEX
) {
569 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
577 if (needs_view_index
)
578 user_sgpr_info
->sgpr_count
++;
580 if (ctx
->shader_info
->info
.loads_push_constants
)
581 user_sgpr_info
->sgpr_count
+= 2;
583 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
? 32 : 16;
584 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_info
->sgpr_count
;
586 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
587 user_sgpr_info
->sgpr_count
+= 2;
588 user_sgpr_info
->indirect_all_descriptor_sets
= true;
590 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
595 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
596 gl_shader_stage stage
,
597 bool has_previous_stage
,
598 gl_shader_stage previous_stage
,
599 const struct user_sgpr_info
*user_sgpr_info
,
600 struct arg_info
*args
,
601 LLVMValueRef
*desc_sets
)
603 LLVMTypeRef type
= ac_array_in_const_addr_space(ctx
->ac
.i8
);
604 unsigned num_sets
= ctx
->options
->layout
?
605 ctx
->options
->layout
->num_sets
: 0;
606 unsigned stage_mask
= 1 << stage
;
608 if (has_previous_stage
)
609 stage_mask
|= 1 << previous_stage
;
611 /* 1 for each descriptor set */
612 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
613 for (unsigned i
= 0; i
< num_sets
; ++i
) {
614 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
615 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
616 add_array_arg(args
, type
,
617 &ctx
->descriptor_sets
[i
]);
621 add_array_arg(args
, ac_array_in_const_addr_space(type
), desc_sets
);
624 if (ctx
->shader_info
->info
.loads_push_constants
) {
625 /* 1 for push constants and dynamic descriptors */
626 add_array_arg(args
, type
, &ctx
->abi
.push_constants
);
631 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
632 gl_shader_stage stage
,
633 bool has_previous_stage
,
634 gl_shader_stage previous_stage
,
635 struct arg_info
*args
)
637 if (!ctx
->is_gs_copy_shader
&&
638 (stage
== MESA_SHADER_VERTEX
||
639 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
640 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
641 add_arg(args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
642 &ctx
->vertex_buffers
);
644 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
645 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
646 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
647 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
653 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
655 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
656 if (!ctx
->is_gs_copy_shader
) {
657 if (ctx
->options
->key
.vs
.as_ls
) {
658 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
659 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
661 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
662 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
664 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
669 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
671 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
672 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
673 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
674 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
678 set_global_input_locs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
679 bool has_previous_stage
, gl_shader_stage previous_stage
,
680 const struct user_sgpr_info
*user_sgpr_info
,
681 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
683 unsigned num_sets
= ctx
->options
->layout
?
684 ctx
->options
->layout
->num_sets
: 0;
685 unsigned stage_mask
= 1 << stage
;
687 if (has_previous_stage
)
688 stage_mask
|= 1 << previous_stage
;
690 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
691 for (unsigned i
= 0; i
< num_sets
; ++i
) {
692 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
693 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
694 set_loc_desc(ctx
, i
, user_sgpr_idx
, 0);
696 ctx
->descriptor_sets
[i
] = NULL
;
699 set_loc_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
702 for (unsigned i
= 0; i
< num_sets
; ++i
) {
703 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
704 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
705 set_loc_desc(ctx
, i
, user_sgpr_idx
, i
* 8);
706 ctx
->descriptor_sets
[i
] =
707 ac_build_load_to_sgpr(&ctx
->ac
,
709 LLVMConstInt(ctx
->ac
.i32
, i
, false));
712 ctx
->descriptor_sets
[i
] = NULL
;
714 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
717 if (ctx
->shader_info
->info
.loads_push_constants
) {
718 set_loc_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
723 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
724 gl_shader_stage stage
, bool has_previous_stage
,
725 gl_shader_stage previous_stage
,
726 uint8_t *user_sgpr_idx
)
728 if (!ctx
->is_gs_copy_shader
&&
729 (stage
== MESA_SHADER_VERTEX
||
730 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
731 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
732 set_loc_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
737 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
740 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
741 user_sgpr_idx
, vs_num
);
745 static void set_llvm_calling_convention(LLVMValueRef func
,
746 gl_shader_stage stage
)
748 enum radeon_llvm_calling_convention calling_conv
;
751 case MESA_SHADER_VERTEX
:
752 case MESA_SHADER_TESS_EVAL
:
753 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
755 case MESA_SHADER_GEOMETRY
:
756 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
758 case MESA_SHADER_TESS_CTRL
:
759 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
761 case MESA_SHADER_FRAGMENT
:
762 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
764 case MESA_SHADER_COMPUTE
:
765 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
768 unreachable("Unhandle shader type");
771 LLVMSetFunctionCallConv(func
, calling_conv
);
774 static void create_function(struct radv_shader_context
*ctx
,
775 gl_shader_stage stage
,
776 bool has_previous_stage
,
777 gl_shader_stage previous_stage
)
779 uint8_t user_sgpr_idx
;
780 struct user_sgpr_info user_sgpr_info
;
781 struct arg_info args
= {};
782 LLVMValueRef desc_sets
;
783 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
784 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
785 previous_stage
, needs_view_index
, &user_sgpr_info
);
787 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
788 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
793 case MESA_SHADER_COMPUTE
:
794 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
795 previous_stage
, &user_sgpr_info
,
798 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
799 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
800 &ctx
->abi
.num_work_groups
);
803 for (int i
= 0; i
< 3; i
++) {
804 ctx
->abi
.workgroup_ids
[i
] = NULL
;
805 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
806 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
807 &ctx
->abi
.workgroup_ids
[i
]);
811 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
812 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
813 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
814 &ctx
->abi
.local_invocation_ids
);
816 case MESA_SHADER_VERTEX
:
817 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
818 previous_stage
, &user_sgpr_info
,
820 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
821 previous_stage
, &args
);
823 if (needs_view_index
)
824 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
825 &ctx
->abi
.view_index
);
826 if (ctx
->options
->key
.vs
.as_es
)
827 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
830 declare_vs_input_vgprs(ctx
, &args
);
832 case MESA_SHADER_TESS_CTRL
:
833 if (has_previous_stage
) {
834 // First 6 system regs
835 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
836 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
837 &ctx
->merged_wave_info
);
838 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
839 &ctx
->tess_factor_offset
);
841 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
842 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
843 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
845 declare_global_input_sgprs(ctx
, stage
,
848 &user_sgpr_info
, &args
,
850 declare_vs_specific_input_sgprs(ctx
, stage
,
852 previous_stage
, &args
);
854 if (needs_view_index
)
855 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
856 &ctx
->abi
.view_index
);
858 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
859 &ctx
->abi
.tcs_patch_id
);
860 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
861 &ctx
->abi
.tcs_rel_ids
);
863 declare_vs_input_vgprs(ctx
, &args
);
865 declare_global_input_sgprs(ctx
, stage
,
868 &user_sgpr_info
, &args
,
871 if (needs_view_index
)
872 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
873 &ctx
->abi
.view_index
);
875 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
876 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
877 &ctx
->tess_factor_offset
);
878 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
879 &ctx
->abi
.tcs_patch_id
);
880 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
881 &ctx
->abi
.tcs_rel_ids
);
884 case MESA_SHADER_TESS_EVAL
:
885 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
886 previous_stage
, &user_sgpr_info
,
889 if (needs_view_index
)
890 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
891 &ctx
->abi
.view_index
);
893 if (ctx
->options
->key
.tes
.as_es
) {
894 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
895 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
896 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
899 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
900 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
902 declare_tes_input_vgprs(ctx
, &args
);
904 case MESA_SHADER_GEOMETRY
:
905 if (has_previous_stage
) {
906 // First 6 system regs
907 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
909 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
910 &ctx
->merged_wave_info
);
911 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
913 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
914 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
915 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
917 declare_global_input_sgprs(ctx
, stage
,
920 &user_sgpr_info
, &args
,
923 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
924 declare_vs_specific_input_sgprs(ctx
, stage
,
930 if (needs_view_index
)
931 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
932 &ctx
->abi
.view_index
);
934 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
935 &ctx
->gs_vtx_offset
[0]);
936 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
937 &ctx
->gs_vtx_offset
[2]);
938 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
939 &ctx
->abi
.gs_prim_id
);
940 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
941 &ctx
->abi
.gs_invocation_id
);
942 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
943 &ctx
->gs_vtx_offset
[4]);
945 if (previous_stage
== MESA_SHADER_VERTEX
) {
946 declare_vs_input_vgprs(ctx
, &args
);
948 declare_tes_input_vgprs(ctx
, &args
);
951 declare_global_input_sgprs(ctx
, stage
,
954 &user_sgpr_info
, &args
,
957 if (needs_view_index
)
958 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
959 &ctx
->abi
.view_index
);
961 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
962 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
963 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
964 &ctx
->gs_vtx_offset
[0]);
965 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
966 &ctx
->gs_vtx_offset
[1]);
967 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
968 &ctx
->abi
.gs_prim_id
);
969 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
970 &ctx
->gs_vtx_offset
[2]);
971 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
972 &ctx
->gs_vtx_offset
[3]);
973 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
974 &ctx
->gs_vtx_offset
[4]);
975 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
976 &ctx
->gs_vtx_offset
[5]);
977 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
978 &ctx
->abi
.gs_invocation_id
);
981 case MESA_SHADER_FRAGMENT
:
982 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
983 previous_stage
, &user_sgpr_info
,
986 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
987 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
988 &ctx
->sample_pos_offset
);
990 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
991 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
992 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
993 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
994 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
995 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
996 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
997 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
998 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
999 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1000 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1001 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1002 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1003 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1004 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1005 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1006 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1009 unreachable("Shader stage not implemented");
1012 ctx
->main_function
= create_llvm_function(
1013 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1014 ctx
->max_workgroup_size
,
1015 ctx
->options
->unsafe_math
);
1016 set_llvm_calling_convention(ctx
->main_function
, stage
);
1019 ctx
->shader_info
->num_input_vgprs
= 0;
1020 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1022 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1024 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1025 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1027 assign_arguments(ctx
->main_function
, &args
);
1031 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1032 set_loc_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1034 if (ctx
->options
->supports_spill
) {
1035 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1036 LLVMPointerType(ctx
->ac
.i8
, AC_CONST_ADDR_SPACE
),
1037 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1038 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1039 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1043 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1044 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1045 if (has_previous_stage
)
1048 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1049 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1052 case MESA_SHADER_COMPUTE
:
1053 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1054 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1058 case MESA_SHADER_VERTEX
:
1059 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1060 previous_stage
, &user_sgpr_idx
);
1061 if (ctx
->abi
.view_index
)
1062 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1064 case MESA_SHADER_TESS_CTRL
:
1065 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1066 previous_stage
, &user_sgpr_idx
);
1067 if (ctx
->abi
.view_index
)
1068 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1070 case MESA_SHADER_TESS_EVAL
:
1071 if (ctx
->abi
.view_index
)
1072 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1074 case MESA_SHADER_GEOMETRY
:
1075 if (has_previous_stage
) {
1076 if (previous_stage
== MESA_SHADER_VERTEX
)
1077 set_vs_specific_input_locs(ctx
, stage
,
1082 if (ctx
->abi
.view_index
)
1083 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1085 case MESA_SHADER_FRAGMENT
:
1086 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1087 set_loc_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
,
1092 unreachable("Shader stage not implemented");
1095 if (stage
== MESA_SHADER_TESS_CTRL
||
1096 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_ls
) ||
1097 /* GFX9 has the ESGS ring buffer in LDS. */
1098 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1099 ac_declare_lds_as_pointer(&ctx
->ac
);
1102 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1107 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1108 unsigned desc_set
, unsigned binding
)
1110 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1111 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1112 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
1113 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1114 unsigned base_offset
= layout
->binding
[binding
].offset
;
1115 LLVMValueRef offset
, stride
;
1117 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1118 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1119 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1120 layout
->binding
[binding
].dynamic_offset_offset
;
1121 desc_ptr
= ctx
->abi
.push_constants
;
1122 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1123 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1125 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1127 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
1128 index
= LLVMBuildMul(ctx
->ac
.builder
, index
, stride
, "");
1129 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, index
, "");
1131 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
1132 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1133 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1139 /* The offchip buffer layout for TCS->TES is
1141 * - attribute 0 of patch 0 vertex 0
1142 * - attribute 0 of patch 0 vertex 1
1143 * - attribute 0 of patch 0 vertex 2
1145 * - attribute 0 of patch 1 vertex 0
1146 * - attribute 0 of patch 1 vertex 1
1148 * - attribute 1 of patch 0 vertex 0
1149 * - attribute 1 of patch 0 vertex 1
1151 * - per patch attribute 0 of patch 0
1152 * - per patch attribute 0 of patch 1
1155 * Note that every attribute has 4 components.
1157 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1159 uint32_t num_patches
= ctx
->tcs_num_patches
;
1160 uint32_t num_tcs_outputs
;
1161 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1162 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
1164 num_tcs_outputs
= ctx
->options
->key
.tes
.tcs_num_outputs
;
1166 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1167 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
1169 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1172 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1173 LLVMValueRef vertex_index
)
1175 LLVMValueRef param_stride
;
1177 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
* ctx
->tcs_num_patches
, false);
1179 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1180 return param_stride
;
1183 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1184 LLVMValueRef vertex_index
,
1185 LLVMValueRef param_index
)
1187 LLVMValueRef base_addr
;
1188 LLVMValueRef param_stride
, constant16
;
1189 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1190 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
1191 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1192 param_stride
= calc_param_stride(ctx
, vertex_index
);
1194 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
1195 vertices_per_patch
, "");
1197 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1200 base_addr
= rel_patch_id
;
1203 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1204 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1205 param_stride
, ""), "");
1207 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1209 if (!vertex_index
) {
1210 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1212 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1213 patch_data_offset
, "");
1218 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1220 unsigned const_index
,
1222 LLVMValueRef vertex_index
,
1223 LLVMValueRef indir_index
)
1225 LLVMValueRef param_index
;
1228 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1231 if (const_index
&& !is_compact
)
1232 param
+= const_index
;
1233 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1235 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1239 get_dw_address(struct radv_shader_context
*ctx
,
1240 LLVMValueRef dw_addr
,
1242 unsigned const_index
,
1243 bool compact_const_index
,
1244 LLVMValueRef vertex_index
,
1245 LLVMValueRef stride
,
1246 LLVMValueRef indir_index
)
1251 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1252 LLVMBuildMul(ctx
->ac
.builder
,
1258 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1259 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1260 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1261 else if (const_index
&& !compact_const_index
)
1262 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1263 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1265 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1266 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1268 if (const_index
&& compact_const_index
)
1269 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1270 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1275 load_tcs_varyings(struct ac_shader_abi
*abi
,
1277 LLVMValueRef vertex_index
,
1278 LLVMValueRef indir_index
,
1279 unsigned const_index
,
1281 unsigned driver_location
,
1283 unsigned num_components
,
1288 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1289 LLVMValueRef dw_addr
, stride
;
1290 LLVMValueRef value
[4], result
;
1291 unsigned param
= shader_io_get_unique_index(location
);
1294 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1295 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1296 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1299 stride
= get_tcs_out_vertex_stride(ctx
);
1300 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1302 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1307 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1310 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1311 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1312 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1315 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1320 store_tcs_output(struct ac_shader_abi
*abi
,
1321 const nir_variable
*var
,
1322 LLVMValueRef vertex_index
,
1323 LLVMValueRef param_index
,
1324 unsigned const_index
,
1328 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1329 const unsigned location
= var
->data
.location
;
1330 const unsigned component
= var
->data
.location_frac
;
1331 const bool is_patch
= var
->data
.patch
;
1332 const bool is_compact
= var
->data
.compact
;
1333 LLVMValueRef dw_addr
;
1334 LLVMValueRef stride
= NULL
;
1335 LLVMValueRef buf_addr
= NULL
;
1337 bool store_lds
= true;
1340 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1343 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
1347 param
= shader_io_get_unique_index(location
);
1348 if (location
== VARYING_SLOT_CLIP_DIST0
&&
1349 is_compact
&& const_index
> 3) {
1355 stride
= get_tcs_out_vertex_stride(ctx
);
1356 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1358 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1361 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1363 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1364 vertex_index
, param_index
);
1366 bool is_tess_factor
= false;
1367 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1368 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1369 is_tess_factor
= true;
1371 unsigned base
= is_compact
? const_index
: 0;
1372 for (unsigned chan
= 0; chan
< 8; chan
++) {
1373 if (!(writemask
& (1 << chan
)))
1375 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1377 if (store_lds
|| is_tess_factor
) {
1378 LLVMValueRef dw_addr_chan
=
1379 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1380 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1381 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1384 if (!is_tess_factor
&& writemask
!= 0xF)
1385 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1386 buf_addr
, ctx
->oc_lds
,
1387 4 * (base
+ chan
), 1, 0, true, false);
1390 if (writemask
== 0xF) {
1391 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1392 buf_addr
, ctx
->oc_lds
,
1393 (base
* 4), 1, 0, true, false);
1398 load_tes_input(struct ac_shader_abi
*abi
,
1400 LLVMValueRef vertex_index
,
1401 LLVMValueRef param_index
,
1402 unsigned const_index
,
1404 unsigned driver_location
,
1406 unsigned num_components
,
1411 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1412 LLVMValueRef buf_addr
;
1413 LLVMValueRef result
;
1414 unsigned param
= shader_io_get_unique_index(location
);
1416 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
1421 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1422 is_compact
, vertex_index
, param_index
);
1424 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1425 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1427 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1428 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
1429 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1434 load_gs_input(struct ac_shader_abi
*abi
,
1436 unsigned driver_location
,
1438 unsigned num_components
,
1439 unsigned vertex_index
,
1440 unsigned const_index
,
1443 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1444 LLVMValueRef vtx_offset
;
1445 unsigned param
, vtx_offset_param
;
1446 LLVMValueRef value
[4], result
;
1448 vtx_offset_param
= vertex_index
;
1449 assert(vtx_offset_param
< 6);
1450 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1451 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1453 param
= shader_io_get_unique_index(location
);
1455 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1456 if (ctx
->ac
.chip_class
>= GFX9
) {
1457 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1458 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1459 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1460 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1462 LLVMValueRef soffset
=
1463 LLVMConstInt(ctx
->ac
.i32
,
1464 (param
* 4 + i
+ const_index
) * 256,
1467 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1470 vtx_offset
, soffset
,
1471 0, 1, 0, true, false);
1473 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
],
1477 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1478 result
= ac_to_integer(&ctx
->ac
, result
);
1483 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1485 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1486 ac_build_kill_if_false(&ctx
->ac
, visible
);
1489 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
1490 enum glsl_interp_mode interp
, unsigned location
)
1492 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1495 case INTERP_MODE_FLAT
:
1498 case INTERP_MODE_SMOOTH
:
1499 case INTERP_MODE_NONE
:
1500 if (location
== INTERP_CENTER
)
1501 return ctx
->persp_center
;
1502 else if (location
== INTERP_CENTROID
)
1503 return ctx
->persp_centroid
;
1504 else if (location
== INTERP_SAMPLE
)
1505 return ctx
->persp_sample
;
1507 case INTERP_MODE_NOPERSPECTIVE
:
1508 if (location
== INTERP_CENTER
)
1509 return ctx
->linear_center
;
1510 else if (location
== INTERP_CENTROID
)
1511 return ctx
->linear_centroid
;
1512 else if (location
== INTERP_SAMPLE
)
1513 return ctx
->linear_sample
;
1519 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1520 LLVMValueRef sample_id
)
1522 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1524 LLVMValueRef result
;
1525 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
1527 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1528 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1530 sample_id
= LLVMBuildAdd(ctx
->ac
.builder
, sample_id
, ctx
->sample_pos_offset
, "");
1531 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1537 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1539 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1540 uint8_t log2_ps_iter_samples
= ctx
->shader_info
->info
.ps
.force_persample
?
1541 ctx
->options
->key
.fs
.log2_num_samples
:
1542 ctx
->options
->key
.fs
.log2_ps_iter_samples
;
1544 /* The bit pattern matches that used by fixed function fragment
1546 static const uint16_t ps_iter_masks
[] = {
1547 0xffff, /* not used */
1553 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1555 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1557 LLVMValueRef result
, sample_id
;
1558 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
1559 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1560 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
1566 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1568 LLVMValueRef gs_next_vertex
;
1569 LLVMValueRef can_emit
;
1571 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1573 assert(stream
== 0);
1575 /* Write vertex attribute values to GSVS ring */
1576 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1577 ctx
->gs_next_vertex
,
1580 /* If this thread has already emitted the declared maximum number of
1581 * vertices, kill it: excessive vertex emissions are not supposed to
1582 * have any effect, and GS threads have no externally observable
1583 * effects other than emitting vertices.
1585 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1586 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
1587 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1589 /* loop num outputs */
1591 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1592 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1597 if (!(ctx
->output_mask
& (1ull << i
)))
1600 if (i
== VARYING_SLOT_CLIP_DIST0
) {
1601 /* pack clip and cull into a single set of slots */
1602 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
1606 for (unsigned j
= 0; j
< length
; j
++) {
1607 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1609 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
1610 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1611 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1613 out_val
= LLVMBuildBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1615 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
1617 voffset
, ctx
->gs2vs_offset
, 0,
1623 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1625 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
1627 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
1631 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1633 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1634 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1638 load_tess_coord(struct ac_shader_abi
*abi
)
1640 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1642 LLVMValueRef coord
[4] = {
1649 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
1650 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1651 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1653 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1657 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1659 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1660 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
1664 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1666 return abi
->base_vertex
;
1669 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1670 LLVMValueRef buffer_ptr
, bool write
)
1672 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1673 LLVMValueRef result
;
1675 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1677 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1678 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1683 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1685 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1686 LLVMValueRef result
;
1688 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1690 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1691 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1696 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1697 unsigned descriptor_set
,
1698 unsigned base_index
,
1699 unsigned constant_index
,
1701 enum ac_descriptor_type desc_type
,
1702 bool image
, bool write
)
1704 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1705 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1706 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
1707 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1708 unsigned offset
= binding
->offset
;
1709 unsigned stride
= binding
->size
;
1711 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1714 assert(base_index
< layout
->binding_count
);
1716 switch (desc_type
) {
1718 type
= ctx
->ac
.v8i32
;
1722 type
= ctx
->ac
.v8i32
;
1726 case AC_DESC_SAMPLER
:
1727 type
= ctx
->ac
.v4i32
;
1728 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1733 case AC_DESC_BUFFER
:
1734 type
= ctx
->ac
.v4i32
;
1738 unreachable("invalid desc_type\n");
1741 offset
+= constant_index
* stride
;
1743 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
1744 (!index
|| binding
->immutable_samplers_equal
)) {
1745 if (binding
->immutable_samplers_equal
)
1748 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
1750 LLVMValueRef constants
[] = {
1751 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
1752 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
1753 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
1754 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
1756 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
1759 assert(stride
% type_size
== 0);
1762 index
= ctx
->ac
.i32_0
;
1764 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
1766 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
1767 list
= LLVMBuildPointerCast(builder
, list
, ac_array_in_const_addr_space(type
), "");
1769 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
1774 handle_vs_input_decl(struct radv_shader_context
*ctx
,
1775 struct nir_variable
*variable
)
1777 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
1778 LLVMValueRef t_offset
;
1779 LLVMValueRef t_list
;
1781 LLVMValueRef buffer_index
;
1782 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
1783 int idx
= variable
->data
.location
;
1784 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
1785 uint8_t input_usage_mask
=
1786 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
1787 unsigned num_channels
= util_last_bit(input_usage_mask
);
1789 variable
->data
.driver_location
= idx
* 4;
1791 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
1792 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << (index
+ i
))) {
1793 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.instance_id
,
1794 ctx
->abi
.start_instance
, "");
1795 if (ctx
->options
->key
.vs
.as_ls
) {
1796 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
1797 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
1799 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
1800 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
1803 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
1804 ctx
->abi
.base_vertex
, "");
1805 t_offset
= LLVMConstInt(ctx
->ac
.i32
, index
+ i
, false);
1807 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
1809 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
1812 num_channels
, false, true);
1814 input
= ac_build_expand_to_vec4(&ctx
->ac
, input
, num_channels
);
1816 for (unsigned chan
= 0; chan
< 4; chan
++) {
1817 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
1818 ctx
->inputs
[ac_llvm_reg_index_soa(idx
, chan
)] =
1819 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
,
1820 input
, llvm_chan
, ""));
1825 static void interp_fs_input(struct radv_shader_context
*ctx
,
1827 LLVMValueRef interp_param
,
1828 LLVMValueRef prim_mask
,
1829 LLVMValueRef result
[4])
1831 LLVMValueRef attr_number
;
1834 bool interp
= interp_param
!= NULL
;
1836 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
1838 /* fs.constant returns the param from the middle vertex, so it's not
1839 * really useful for flat shading. It's meant to be used for custom
1840 * interpolation (but the intrinsic can't fetch from the other two
1843 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1844 * to do the right thing. The only reason we use fs.constant is that
1845 * fs.interp cannot be used on integers, because they can be equal
1849 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
1852 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1854 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1858 for (chan
= 0; chan
< 4; chan
++) {
1859 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
1862 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
1867 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
1868 LLVMConstInt(ctx
->ac
.i32
, 2, false),
1877 handle_fs_input_decl(struct radv_shader_context
*ctx
,
1878 struct nir_variable
*variable
)
1880 int idx
= variable
->data
.location
;
1881 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
1882 LLVMValueRef interp
;
1884 variable
->data
.driver_location
= idx
* 4;
1885 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
1887 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
1888 unsigned interp_type
;
1889 if (variable
->data
.sample
)
1890 interp_type
= INTERP_SAMPLE
;
1891 else if (variable
->data
.centroid
)
1892 interp_type
= INTERP_CENTROID
;
1894 interp_type
= INTERP_CENTER
;
1896 interp
= lookup_interp_param(&ctx
->abi
, variable
->data
.interpolation
, interp_type
);
1900 for (unsigned i
= 0; i
< attrib_count
; ++i
)
1901 ctx
->inputs
[ac_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
1906 handle_vs_inputs(struct radv_shader_context
*ctx
,
1907 struct nir_shader
*nir
) {
1908 nir_foreach_variable(variable
, &nir
->inputs
)
1909 handle_vs_input_decl(ctx
, variable
);
1913 prepare_interp_optimize(struct radv_shader_context
*ctx
,
1914 struct nir_shader
*nir
)
1916 if (!ctx
->options
->key
.fs
.multisample
)
1919 bool uses_center
= false;
1920 bool uses_centroid
= false;
1921 nir_foreach_variable(variable
, &nir
->inputs
) {
1922 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
1923 variable
->data
.sample
)
1926 if (variable
->data
.centroid
)
1927 uses_centroid
= true;
1932 if (uses_center
&& uses_centroid
) {
1933 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
1934 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
1935 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
1940 handle_fs_inputs(struct radv_shader_context
*ctx
,
1941 struct nir_shader
*nir
)
1943 prepare_interp_optimize(ctx
, nir
);
1945 nir_foreach_variable(variable
, &nir
->inputs
)
1946 handle_fs_input_decl(ctx
, variable
);
1950 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
1951 ctx
->shader_info
->info
.needs_multiview_view_index
)
1952 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
1954 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
1955 LLVMValueRef interp_param
;
1956 LLVMValueRef
*inputs
= ctx
->inputs
+ac_llvm_reg_index_soa(i
, 0);
1958 if (!(ctx
->input_mask
& (1ull << i
)))
1961 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
1962 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
1963 interp_param
= *inputs
;
1964 interp_fs_input(ctx
, index
, interp_param
, ctx
->abi
.prim_mask
,
1968 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
1970 } else if (i
== VARYING_SLOT_POS
) {
1971 for(int i
= 0; i
< 3; ++i
)
1972 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
1974 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
1975 ctx
->abi
.frag_pos
[3]);
1978 ctx
->shader_info
->fs
.num_interp
= index
;
1979 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
1981 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
1982 ctx
->abi
.view_index
= ctx
->inputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
1986 scan_shader_output_decl(struct radv_shader_context
*ctx
,
1987 struct nir_variable
*variable
,
1988 struct nir_shader
*shader
,
1989 gl_shader_stage stage
)
1991 int idx
= variable
->data
.location
+ variable
->data
.index
;
1992 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
1993 uint64_t mask_attribs
;
1995 variable
->data
.driver_location
= idx
* 4;
1997 /* tess ctrl has it's own load/store paths for outputs */
1998 if (stage
== MESA_SHADER_TESS_CTRL
)
2001 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2002 if (stage
== MESA_SHADER_VERTEX
||
2003 stage
== MESA_SHADER_TESS_EVAL
||
2004 stage
== MESA_SHADER_GEOMETRY
) {
2005 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2006 int length
= shader
->info
.clip_distance_array_size
+
2007 shader
->info
.cull_distance_array_size
;
2008 if (stage
== MESA_SHADER_VERTEX
) {
2009 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2010 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2012 if (stage
== MESA_SHADER_TESS_EVAL
) {
2013 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2014 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2021 mask_attribs
= 1ull << idx
;
2025 ctx
->output_mask
|= mask_attribs
;
2029 /* Initialize arguments for the shader export intrinsic */
2031 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2032 LLVMValueRef
*values
,
2033 unsigned enabled_channels
,
2035 struct ac_export_args
*args
)
2037 /* Specify the channels that are enabled. */
2038 args
->enabled_channels
= enabled_channels
;
2040 /* Specify whether the EXEC mask represents the valid mask */
2041 args
->valid_mask
= 0;
2043 /* Specify whether this is the last export */
2046 /* Specify the target we are exporting */
2047 args
->target
= target
;
2049 args
->compr
= false;
2050 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2051 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2052 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2053 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2055 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
2056 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2057 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2058 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2059 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2062 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2063 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2064 unsigned bits
, bool hi
) = NULL
;
2066 switch(col_format
) {
2067 case V_028714_SPI_SHADER_ZERO
:
2068 args
->enabled_channels
= 0; /* writemask */
2069 args
->target
= V_008DFC_SQ_EXP_NULL
;
2072 case V_028714_SPI_SHADER_32_R
:
2073 args
->enabled_channels
= 1;
2074 args
->out
[0] = values
[0];
2077 case V_028714_SPI_SHADER_32_GR
:
2078 args
->enabled_channels
= 0x3;
2079 args
->out
[0] = values
[0];
2080 args
->out
[1] = values
[1];
2083 case V_028714_SPI_SHADER_32_AR
:
2084 args
->enabled_channels
= 0x9;
2085 args
->out
[0] = values
[0];
2086 args
->out
[3] = values
[3];
2089 case V_028714_SPI_SHADER_FP16_ABGR
:
2090 args
->enabled_channels
= 0x5;
2091 packf
= ac_build_cvt_pkrtz_f16
;
2094 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2095 args
->enabled_channels
= 0x5;
2096 packf
= ac_build_cvt_pknorm_u16
;
2099 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2100 args
->enabled_channels
= 0x5;
2101 packf
= ac_build_cvt_pknorm_i16
;
2104 case V_028714_SPI_SHADER_UINT16_ABGR
:
2105 args
->enabled_channels
= 0x5;
2106 packi
= ac_build_cvt_pk_u16
;
2109 case V_028714_SPI_SHADER_SINT16_ABGR
:
2110 args
->enabled_channels
= 0x5;
2111 packi
= ac_build_cvt_pk_i16
;
2115 case V_028714_SPI_SHADER_32_ABGR
:
2116 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2120 /* Pack f16 or norm_i16/u16. */
2122 for (chan
= 0; chan
< 2; chan
++) {
2123 LLVMValueRef pack_args
[2] = {
2125 values
[2 * chan
+ 1]
2127 LLVMValueRef packed
;
2129 packed
= packf(&ctx
->ac
, pack_args
);
2130 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2132 args
->compr
= 1; /* COMPR flag */
2137 for (chan
= 0; chan
< 2; chan
++) {
2138 LLVMValueRef pack_args
[2] = {
2139 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2140 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2142 LLVMValueRef packed
;
2144 packed
= packi(&ctx
->ac
, pack_args
,
2145 is_int8
? 8 : is_int10
? 10 : 16,
2147 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2149 args
->compr
= 1; /* COMPR flag */
2154 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2156 for (unsigned i
= 0; i
< 4; ++i
) {
2157 if (!(args
->enabled_channels
& (1 << i
)))
2160 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2165 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2166 LLVMValueRef
*values
, unsigned enabled_channels
)
2168 struct ac_export_args args
;
2170 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2171 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2172 ac_build_export(&ctx
->ac
, &args
);
2176 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2178 LLVMValueRef output
=
2179 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2181 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2185 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2186 bool export_prim_id
, bool export_layer_id
,
2187 struct radv_vs_output_info
*outinfo
)
2189 uint32_t param_count
= 0;
2191 unsigned pos_idx
, num_pos_exports
= 0;
2192 struct ac_export_args args
, pos_args
[4] = {};
2193 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2196 if (ctx
->options
->key
.has_multiview_view_index
) {
2197 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2199 for(unsigned i
= 0; i
< 4; ++i
)
2200 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2201 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2204 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
2205 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2208 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2209 sizeof(outinfo
->vs_output_param_offset
));
2211 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
2212 LLVMValueRef slots
[8];
2215 if (outinfo
->cull_dist_mask
)
2216 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
2218 i
= VARYING_SLOT_CLIP_DIST0
;
2219 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
2220 slots
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2222 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
2223 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
2225 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
2226 target
= V_008DFC_SQ_EXP_POS
+ 3;
2227 si_llvm_init_export_args(ctx
, &slots
[4], 0xf, target
, &args
);
2228 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2229 &args
, sizeof(args
));
2232 target
= V_008DFC_SQ_EXP_POS
+ 2;
2233 si_llvm_init_export_args(ctx
, &slots
[0], 0xf, target
, &args
);
2234 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2235 &args
, sizeof(args
));
2239 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
2240 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
2241 for (unsigned j
= 0; j
< 4; j
++)
2242 pos_values
[j
] = radv_load_output(ctx
, VARYING_SLOT_POS
, j
);
2244 si_llvm_init_export_args(ctx
, pos_values
, 0xf, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2246 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
2247 outinfo
->writes_pointsize
= true;
2248 psize_value
= radv_load_output(ctx
, VARYING_SLOT_PSIZ
, 0);
2251 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
2252 outinfo
->writes_layer
= true;
2253 layer_value
= radv_load_output(ctx
, VARYING_SLOT_LAYER
, 0);
2256 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
2257 outinfo
->writes_viewport_index
= true;
2258 viewport_index_value
= radv_load_output(ctx
, VARYING_SLOT_VIEWPORT
, 0);
2261 if (outinfo
->writes_pointsize
||
2262 outinfo
->writes_layer
||
2263 outinfo
->writes_viewport_index
) {
2264 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2265 (outinfo
->writes_layer
== true ? 4 : 0));
2266 pos_args
[1].valid_mask
= 0;
2267 pos_args
[1].done
= 0;
2268 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2269 pos_args
[1].compr
= 0;
2270 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2271 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2272 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2273 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2275 if (outinfo
->writes_pointsize
== true)
2276 pos_args
[1].out
[0] = psize_value
;
2277 if (outinfo
->writes_layer
== true)
2278 pos_args
[1].out
[2] = layer_value
;
2279 if (outinfo
->writes_viewport_index
== true) {
2280 if (ctx
->options
->chip_class
>= GFX9
) {
2281 /* GFX9 has the layer in out.z[10:0] and the viewport
2282 * index in out.z[19:16].
2284 LLVMValueRef v
= viewport_index_value
;
2285 v
= ac_to_integer(&ctx
->ac
, v
);
2286 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2287 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2289 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2290 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2292 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2293 pos_args
[1].enabled_channels
|= 1 << 2;
2295 pos_args
[1].out
[3] = viewport_index_value
;
2296 pos_args
[1].enabled_channels
|= 1 << 3;
2300 for (i
= 0; i
< 4; i
++) {
2301 if (pos_args
[i
].out
[0])
2306 for (i
= 0; i
< 4; i
++) {
2307 if (!pos_args
[i
].out
[0])
2310 /* Specify the target we are exporting */
2311 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2312 if (pos_idx
== num_pos_exports
)
2313 pos_args
[i
].done
= 1;
2314 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2317 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2318 LLVMValueRef values
[4];
2319 if (!(ctx
->output_mask
& (1ull << i
)))
2322 if (i
!= VARYING_SLOT_LAYER
&&
2323 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
2324 i
< VARYING_SLOT_VAR0
)
2327 for (unsigned j
= 0; j
< 4; j
++)
2328 values
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2330 unsigned output_usage_mask
;
2332 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2333 !ctx
->is_gs_copy_shader
) {
2335 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2336 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2338 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2340 /* Enable all channels for the GS copy shader because
2341 * we don't know the output usage mask currently.
2343 output_usage_mask
= 0xf;
2346 radv_export_param(ctx
, param_count
, values
, output_usage_mask
);
2348 outinfo
->vs_output_param_offset
[i
] = param_count
++;
2351 if (export_prim_id
) {
2352 LLVMValueRef values
[4];
2354 values
[0] = ctx
->vs_prim_id
;
2355 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
2356 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
2357 for (unsigned j
= 1; j
< 4; j
++)
2358 values
[j
] = ctx
->ac
.f32_0
;
2360 radv_export_param(ctx
, param_count
, values
, 0x1);
2362 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
2363 outinfo
->export_prim_id
= true;
2366 if (export_layer_id
&& layer_value
) {
2367 LLVMValueRef values
[4];
2369 values
[0] = layer_value
;
2370 for (unsigned j
= 1; j
< 4; j
++)
2371 values
[j
] = ctx
->ac
.f32_0
;
2373 radv_export_param(ctx
, param_count
, values
, 0x1);
2375 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
++;
2378 outinfo
->pos_exports
= num_pos_exports
;
2379 outinfo
->param_exports
= param_count
;
2383 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2384 struct radv_es_output_info
*outinfo
)
2387 uint64_t max_output_written
= 0;
2388 LLVMValueRef lds_base
= NULL
;
2390 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2394 if (!(ctx
->output_mask
& (1ull << i
)))
2397 if (i
== VARYING_SLOT_CLIP_DIST0
)
2398 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
2400 param_index
= shader_io_get_unique_index(i
);
2402 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
2405 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
2407 if (ctx
->ac
.chip_class
>= GFX9
) {
2408 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2409 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2410 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
2411 LLVMConstInt(ctx
->ac
.i32
, 24, false),
2412 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
2413 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2414 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2415 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
2416 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2417 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2420 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2421 LLVMValueRef dw_addr
= NULL
;
2422 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2426 if (!(ctx
->output_mask
& (1ull << i
)))
2429 if (i
== VARYING_SLOT_CLIP_DIST0
)
2430 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
2432 param_index
= shader_io_get_unique_index(i
);
2435 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2436 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
2439 for (j
= 0; j
< length
; j
++) {
2440 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2441 out_val
= LLVMBuildBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
2443 if (ctx
->ac
.chip_class
>= GFX9
) {
2444 ac_lds_store(&ctx
->ac
, dw_addr
,
2445 LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], ""));
2446 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
2448 ac_build_buffer_store_dword(&ctx
->ac
,
2451 NULL
, ctx
->es2gs_offset
,
2452 (4 * param_index
+ j
) * 4,
2460 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
2462 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
2463 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->shader_info
->info
.vs
.ls_outputs_written
);
2464 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
2465 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
2466 vertex_dw_stride
, "");
2468 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2469 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2472 if (!(ctx
->output_mask
& (1ull << i
)))
2475 if (i
== VARYING_SLOT_CLIP_DIST0
)
2476 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
2477 int param
= shader_io_get_unique_index(i
);
2478 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
2479 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
2481 for (unsigned j
= 0; j
< length
; j
++) {
2482 ac_lds_store(&ctx
->ac
, dw_addr
,
2483 LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], ""));
2484 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
2489 struct ac_build_if_state
2491 struct radv_shader_context
*ctx
;
2492 LLVMValueRef condition
;
2493 LLVMBasicBlockRef entry_block
;
2494 LLVMBasicBlockRef true_block
;
2495 LLVMBasicBlockRef false_block
;
2496 LLVMBasicBlockRef merge_block
;
2499 static LLVMBasicBlockRef
2500 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
2502 LLVMBasicBlockRef current_block
;
2503 LLVMBasicBlockRef next_block
;
2504 LLVMBasicBlockRef new_block
;
2506 /* get current basic block */
2507 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
2509 /* chqeck if there's another block after this one */
2510 next_block
= LLVMGetNextBasicBlock(current_block
);
2512 /* insert the new block before the next block */
2513 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
2516 /* append new block after current block */
2517 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
2518 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
2524 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
2525 struct radv_shader_context
*ctx
,
2526 LLVMValueRef condition
)
2528 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
2530 memset(ifthen
, 0, sizeof *ifthen
);
2532 ifthen
->condition
= condition
;
2533 ifthen
->entry_block
= block
;
2535 /* create endif/merge basic block for the phi functions */
2536 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
2538 /* create/insert true_block before merge_block */
2539 ifthen
->true_block
=
2540 LLVMInsertBasicBlockInContext(ctx
->context
,
2541 ifthen
->merge_block
,
2544 /* successive code goes into the true block */
2545 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
2549 * End a conditional.
2552 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
2554 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
2556 /* Insert branch to the merge block from current block */
2557 LLVMBuildBr(builder
, ifthen
->merge_block
);
2560 * Now patch in the various branch instructions.
2563 /* Insert the conditional branch instruction at the end of entry_block */
2564 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
2565 if (ifthen
->false_block
) {
2566 /* we have an else clause */
2567 LLVMBuildCondBr(builder
, ifthen
->condition
,
2568 ifthen
->true_block
, ifthen
->false_block
);
2571 /* no else clause */
2572 LLVMBuildCondBr(builder
, ifthen
->condition
,
2573 ifthen
->true_block
, ifthen
->merge_block
);
2576 /* Resume building code at end of the ifthen->merge_block */
2577 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
2581 write_tess_factors(struct radv_shader_context
*ctx
)
2583 unsigned stride
, outer_comps
, inner_comps
;
2584 struct ac_build_if_state if_ctx
, inner_if_ctx
;
2585 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
2586 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
2587 unsigned tess_inner_index
= 0, tess_outer_index
;
2588 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
2589 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
2591 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
2593 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
2613 ac_nir_build_if(&if_ctx
, ctx
,
2614 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
2615 invocation_id
, ctx
->ac
.i32_0
, ""));
2617 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
2620 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
2621 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2622 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
2625 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
2626 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2627 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
2629 for (i
= 0; i
< 4; i
++) {
2630 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
2631 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
2635 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
2636 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
2637 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
2639 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
2641 for (i
= 0; i
< outer_comps
; i
++) {
2643 ac_lds_load(&ctx
->ac
, lds_outer
);
2644 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
2647 for (i
= 0; i
< inner_comps
; i
++) {
2648 inner
[i
] = out
[outer_comps
+i
] =
2649 ac_lds_load(&ctx
->ac
, lds_inner
);
2650 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
2655 /* Convert the outputs to vectors for stores. */
2656 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
2660 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
2663 buffer
= ctx
->hs_ring_tess_factor
;
2664 tf_base
= ctx
->tess_factor_offset
;
2665 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
2666 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
2667 unsigned tf_offset
= 0;
2669 if (ctx
->options
->chip_class
<= VI
) {
2670 ac_nir_build_if(&inner_if_ctx
, ctx
,
2671 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
2672 rel_patch_id
, ctx
->ac
.i32_0
, ""));
2674 /* Store the dynamic HS control word. */
2675 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
2676 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
2677 1, ctx
->ac
.i32_0
, tf_base
,
2678 0, 1, 0, true, false);
2681 ac_nir_build_endif(&inner_if_ctx
);
2684 /* Store the tessellation factors. */
2685 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
2686 MIN2(stride
, 4), byteoffset
, tf_base
,
2687 tf_offset
, 1, 0, true, false);
2689 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
2690 stride
- 4, byteoffset
, tf_base
,
2691 16 + tf_offset
, 1, 0, true, false);
2693 //store to offchip for TES to read - only if TES reads them
2694 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
2695 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
2696 LLVMValueRef tf_inner_offset
;
2697 unsigned param_outer
, param_inner
;
2699 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
2700 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
2701 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
2703 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
2704 util_next_power_of_two(outer_comps
));
2706 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
2707 outer_comps
, tf_outer_offset
,
2708 ctx
->oc_lds
, 0, 1, 0, true, false);
2710 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
2711 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
2712 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
2714 inner_vec
= inner_comps
== 1 ? inner
[0] :
2715 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
2716 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
2717 inner_comps
, tf_inner_offset
,
2718 ctx
->oc_lds
, 0, 1, 0, true, false);
2721 ac_nir_build_endif(&if_ctx
);
2725 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
2727 write_tess_factors(ctx
);
2731 si_export_mrt_color(struct radv_shader_context
*ctx
,
2732 LLVMValueRef
*color
, unsigned index
,
2733 struct ac_export_args
*args
)
2736 si_llvm_init_export_args(ctx
, color
, 0xf,
2737 V_008DFC_SQ_EXP_MRT
+ index
, args
);
2738 if (!args
->enabled_channels
)
2739 return false; /* unnecessary NULL export */
2745 radv_export_mrt_z(struct radv_shader_context
*ctx
,
2746 LLVMValueRef depth
, LLVMValueRef stencil
,
2747 LLVMValueRef samplemask
)
2749 struct ac_export_args args
;
2751 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
2753 ac_build_export(&ctx
->ac
, &args
);
2757 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
2760 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
2761 struct ac_export_args color_args
[8];
2763 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2764 LLVMValueRef values
[4];
2766 if (!(ctx
->output_mask
& (1ull << i
)))
2769 if (i
< FRAG_RESULT_DATA0
)
2772 for (unsigned j
= 0; j
< 4; j
++)
2773 values
[j
] = ac_to_float(&ctx
->ac
,
2774 radv_load_output(ctx
, i
, j
));
2776 bool ret
= si_export_mrt_color(ctx
, values
,
2777 i
- FRAG_RESULT_DATA0
,
2778 &color_args
[index
]);
2783 /* Process depth, stencil, samplemask. */
2784 if (ctx
->shader_info
->info
.ps
.writes_z
) {
2785 depth
= ac_to_float(&ctx
->ac
,
2786 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
2788 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
2789 stencil
= ac_to_float(&ctx
->ac
,
2790 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
2792 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
2793 samplemask
= ac_to_float(&ctx
->ac
,
2794 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
2797 /* Set the DONE bit on last non-null color export only if Z isn't
2801 !ctx
->shader_info
->info
.ps
.writes_z
&&
2802 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
2803 !ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
2804 unsigned last
= index
- 1;
2806 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
2807 color_args
[last
].done
= 1; /* DONE bit */
2810 /* Export PS outputs. */
2811 for (unsigned i
= 0; i
< index
; i
++)
2812 ac_build_export(&ctx
->ac
, &color_args
[i
]);
2814 if (depth
|| stencil
|| samplemask
)
2815 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
2817 ac_build_export_null(&ctx
->ac
);
2821 emit_gs_epilogue(struct radv_shader_context
*ctx
)
2823 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
2827 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
2828 LLVMValueRef
*addrs
)
2830 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2832 switch (ctx
->stage
) {
2833 case MESA_SHADER_VERTEX
:
2834 if (ctx
->options
->key
.vs
.as_ls
)
2835 handle_ls_outputs_post(ctx
);
2836 else if (ctx
->options
->key
.vs
.as_es
)
2837 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
2839 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
2840 ctx
->options
->key
.vs
.export_layer_id
,
2841 &ctx
->shader_info
->vs
.outinfo
);
2843 case MESA_SHADER_FRAGMENT
:
2844 handle_fs_outputs_post(ctx
);
2846 case MESA_SHADER_GEOMETRY
:
2847 emit_gs_epilogue(ctx
);
2849 case MESA_SHADER_TESS_CTRL
:
2850 handle_tcs_outputs_post(ctx
);
2852 case MESA_SHADER_TESS_EVAL
:
2853 if (ctx
->options
->key
.tes
.as_es
)
2854 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
2856 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
2857 ctx
->options
->key
.tes
.export_layer_id
,
2858 &ctx
->shader_info
->tes
.outinfo
);
2865 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
)
2867 LLVMPassManagerRef passmgr
;
2868 /* Create the pass manager */
2869 passmgr
= LLVMCreateFunctionPassManagerForModule(
2872 /* This pass should eliminate all the load and store instructions */
2873 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
2875 /* Add some optimization passes */
2876 LLVMAddScalarReplAggregatesPass(passmgr
);
2877 LLVMAddLICMPass(passmgr
);
2878 LLVMAddAggressiveDCEPass(passmgr
);
2879 LLVMAddCFGSimplificationPass(passmgr
);
2880 LLVMAddInstructionCombiningPass(passmgr
);
2883 LLVMInitializeFunctionPassManager(passmgr
);
2884 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
2885 LLVMFinalizeFunctionPassManager(passmgr
);
2887 LLVMDisposeBuilder(ctx
->ac
.builder
);
2888 LLVMDisposePassManager(passmgr
);
2890 ac_llvm_context_dispose(&ctx
->ac
);
2894 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
2896 struct radv_vs_output_info
*outinfo
;
2898 switch (ctx
->stage
) {
2899 case MESA_SHADER_FRAGMENT
:
2900 case MESA_SHADER_COMPUTE
:
2901 case MESA_SHADER_TESS_CTRL
:
2902 case MESA_SHADER_GEOMETRY
:
2904 case MESA_SHADER_VERTEX
:
2905 if (ctx
->options
->key
.vs
.as_ls
||
2906 ctx
->options
->key
.vs
.as_es
)
2908 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
2910 case MESA_SHADER_TESS_EVAL
:
2911 if (ctx
->options
->key
.vs
.as_es
)
2913 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
2916 unreachable("Unhandled shader type");
2919 ac_optimize_vs_outputs(&ctx
->ac
,
2921 outinfo
->vs_output_param_offset
,
2923 &outinfo
->param_exports
);
2927 ac_setup_rings(struct radv_shader_context
*ctx
)
2929 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
2930 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
2931 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_VS
, false));
2934 if (ctx
->is_gs_copy_shader
) {
2935 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
2937 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
2939 uint32_t num_entries
= 64;
2940 LLVMValueRef gsvs_ring_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->max_gsvs_emit_size
, false);
2941 LLVMValueRef gsvs_ring_desc
= LLVMConstInt(ctx
->ac
.i32
, ctx
->max_gsvs_emit_size
<< 16, false);
2942 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_GS
, false));
2943 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
2945 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
2947 tmp
= LLVMConstInt(ctx
->ac
.i32
, num_entries
, false);
2948 if (ctx
->options
->chip_class
>= VI
)
2949 tmp
= LLVMBuildMul(ctx
->ac
.builder
, gsvs_ring_stride
, tmp
, "");
2950 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2951 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
2952 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
, gsvs_ring_desc
, "");
2953 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
2956 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
2957 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2958 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
2959 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
2964 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
2965 const struct nir_shader
*nir
)
2967 switch (nir
->info
.stage
) {
2968 case MESA_SHADER_TESS_CTRL
:
2969 return chip_class
>= CIK
? 128 : 64;
2970 case MESA_SHADER_GEOMETRY
:
2971 return chip_class
>= GFX9
? 128 : 64;
2972 case MESA_SHADER_COMPUTE
:
2978 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
2979 nir
->info
.cs
.local_size
[1] *
2980 nir
->info
.cs
.local_size
[2];
2981 return max_workgroup_size
;
2984 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
2985 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
2987 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
2988 LLVMConstInt(ctx
->ac
.i32
, 8, false),
2989 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
2990 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
2992 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
2993 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
2994 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
2995 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
2998 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
3000 for(int i
= 5; i
>= 0; --i
) {
3001 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
3002 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
3003 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
3006 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
3007 LLVMConstInt(ctx
->ac
.i32
, 16, false),
3008 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
3013 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
3014 struct nir_shader
*const *shaders
,
3016 struct radv_shader_variant_info
*shader_info
,
3017 const struct radv_nir_compiler_options
*options
)
3019 struct radv_shader_context ctx
= {0};
3021 ctx
.options
= options
;
3022 ctx
.shader_info
= shader_info
;
3023 ctx
.context
= LLVMContextCreate();
3025 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
3027 ctx
.ac
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
3028 LLVMSetTarget(ctx
.ac
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
3030 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
3031 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
3032 LLVMSetDataLayout(ctx
.ac
.module
, data_layout_str
);
3033 LLVMDisposeTargetData(data_layout
);
3034 LLVMDisposeMessage(data_layout_str
);
3036 enum ac_float_mode float_mode
=
3037 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
3038 AC_FLOAT_MODE_DEFAULT
;
3040 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
3042 memset(shader_info
, 0, sizeof(*shader_info
));
3044 for(int i
= 0; i
< shader_count
; ++i
)
3045 radv_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
3047 for (i
= 0; i
< RADV_UD_MAX_SETS
; i
++)
3048 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
3049 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
3050 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
3052 ctx
.max_workgroup_size
= 0;
3053 for (int i
= 0; i
< shader_count
; ++i
) {
3054 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
3055 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
3059 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
3060 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
3062 ctx
.abi
.inputs
= &ctx
.inputs
[0];
3063 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
3064 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
3065 ctx
.abi
.load_ubo
= radv_load_ubo
;
3066 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
3067 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
3068 ctx
.abi
.load_resource
= radv_load_resource
;
3069 ctx
.abi
.clamp_shadow_reference
= false;
3071 if (shader_count
>= 2)
3072 ac_init_exec_full_mask(&ctx
.ac
);
3074 if (ctx
.ac
.chip_class
== GFX9
&&
3075 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
3076 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
3078 for(int i
= 0; i
< shader_count
; ++i
) {
3079 ctx
.stage
= shaders
[i
]->info
.stage
;
3080 ctx
.output_mask
= 0;
3081 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
3082 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
3084 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3085 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
3086 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
3087 ctx
.abi
.load_inputs
= load_gs_input
;
3088 ctx
.abi
.emit_primitive
= visit_end_primitive
;
3089 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3090 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
3091 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
3092 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
3093 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3094 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
3095 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3096 if (shader_count
== 1)
3097 ctx
.tcs_num_inputs
= ctx
.options
->key
.tcs
.num_inputs
;
3099 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->info
.vs
.ls_outputs_written
);
3100 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
3101 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
3102 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
3103 ctx
.abi
.load_tess_varyings
= load_tes_input
;
3104 ctx
.abi
.load_tess_coord
= load_tess_coord
;
3105 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3106 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3107 ctx
.tcs_num_patches
= ctx
.options
->key
.tes
.num_patches
;
3108 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
3109 if (shader_info
->info
.vs
.needs_instance_id
) {
3110 if (ctx
.options
->key
.vs
.as_ls
) {
3111 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
3112 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
3114 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
3115 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
3118 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
3119 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
3120 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
3121 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
3122 ctx
.abi
.load_sample_position
= load_sample_position
;
3123 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
3124 ctx
.abi
.emit_kill
= radv_emit_kill
;
3128 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
3130 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
3131 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
3133 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3134 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
3135 shaders
[i
]->info
.cull_distance_array_size
> 4;
3136 ctx
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
3137 ctx
.max_gsvs_emit_size
= ctx
.gsvs_vertex_size
*
3138 shaders
[i
]->info
.gs
.vertices_out
;
3141 ac_setup_rings(&ctx
);
3143 LLVMBasicBlockRef merge_block
;
3144 if (shader_count
>= 2) {
3145 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
3146 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3147 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3149 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
3150 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
3151 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
3152 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
3153 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
3154 thread_id
, count
, "");
3155 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
3157 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
3160 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
3161 handle_fs_inputs(&ctx
, shaders
[i
]);
3162 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
3163 handle_vs_inputs(&ctx
, shaders
[i
]);
3164 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
3165 prepare_gs_input_vgprs(&ctx
);
3167 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
3169 if (shader_count
>= 2) {
3170 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
3171 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
3174 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3175 shader_info
->gs
.gsvs_vertex_size
= ctx
.gsvs_vertex_size
;
3176 shader_info
->gs
.max_gsvs_emit_size
= ctx
.max_gsvs_emit_size
;
3177 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3178 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
3179 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
3183 LLVMBuildRetVoid(ctx
.ac
.builder
);
3185 if (options
->dump_preoptir
)
3186 ac_dump_module(ctx
.ac
.module
);
3188 ac_llvm_finalize_module(&ctx
);
3190 if (shader_count
== 1)
3191 ac_nir_eliminate_const_vs_outputs(&ctx
);
3193 if (options
->dump_shader
) {
3194 ctx
.shader_info
->private_mem_vgprs
=
3195 ac_count_scratch_private_memory(ctx
.main_function
);
3198 return ctx
.ac
.module
;
3201 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
3203 unsigned *retval
= (unsigned *)context
;
3204 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
3205 char *description
= LLVMGetDiagInfoDescription(di
);
3207 if (severity
== LLVMDSError
) {
3209 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
3213 LLVMDisposeMessage(description
);
3216 static unsigned ac_llvm_compile(LLVMModuleRef M
,
3217 struct ac_shader_binary
*binary
,
3218 LLVMTargetMachineRef tm
)
3220 unsigned retval
= 0;
3222 LLVMContextRef llvm_ctx
;
3223 LLVMMemoryBufferRef out_buffer
;
3224 unsigned buffer_size
;
3225 const char *buffer_data
;
3228 /* Setup Diagnostic Handler*/
3229 llvm_ctx
= LLVMGetModuleContext(M
);
3231 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
3235 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
3238 /* Process Errors/Warnings */
3240 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
3246 /* Extract Shader Code*/
3247 buffer_size
= LLVMGetBufferSize(out_buffer
);
3248 buffer_data
= LLVMGetBufferStart(out_buffer
);
3250 ac_elf_read(buffer_data
, buffer_size
, binary
);
3253 LLVMDisposeMemoryBuffer(out_buffer
);
3259 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
3260 LLVMModuleRef llvm_module
,
3261 struct ac_shader_binary
*binary
,
3262 struct ac_shader_config
*config
,
3263 struct radv_shader_variant_info
*shader_info
,
3264 gl_shader_stage stage
,
3265 const struct radv_nir_compiler_options
*options
)
3267 if (options
->dump_shader
)
3268 ac_dump_module(llvm_module
);
3270 memset(binary
, 0, sizeof(*binary
));
3272 if (options
->record_llvm_ir
) {
3273 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
3274 binary
->llvm_ir_string
= strdup(llvm_ir
);
3275 LLVMDisposeMessage(llvm_ir
);
3278 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
3280 fprintf(stderr
, "compile failed\n");
3283 if (options
->dump_shader
)
3284 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
3286 ac_shader_binary_read_config(binary
, config
, 0, options
->supports_spill
);
3288 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
3289 LLVMDisposeModule(llvm_module
);
3290 LLVMContextDispose(ctx
);
3292 if (stage
== MESA_SHADER_FRAGMENT
) {
3293 shader_info
->num_input_vgprs
= 0;
3294 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
3295 shader_info
->num_input_vgprs
+= 2;
3296 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
3297 shader_info
->num_input_vgprs
+= 2;
3298 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
3299 shader_info
->num_input_vgprs
+= 2;
3300 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
3301 shader_info
->num_input_vgprs
+= 3;
3302 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
3303 shader_info
->num_input_vgprs
+= 2;
3304 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
3305 shader_info
->num_input_vgprs
+= 2;
3306 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
3307 shader_info
->num_input_vgprs
+= 2;
3308 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
3309 shader_info
->num_input_vgprs
+= 1;
3310 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
3311 shader_info
->num_input_vgprs
+= 1;
3312 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
3313 shader_info
->num_input_vgprs
+= 1;
3314 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
3315 shader_info
->num_input_vgprs
+= 1;
3316 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
3317 shader_info
->num_input_vgprs
+= 1;
3318 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
3319 shader_info
->num_input_vgprs
+= 1;
3320 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
3321 shader_info
->num_input_vgprs
+= 1;
3322 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
3323 shader_info
->num_input_vgprs
+= 1;
3324 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
3325 shader_info
->num_input_vgprs
+= 1;
3327 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
3329 /* +3 for scratch wave offset and VCC */
3330 config
->num_sgprs
= MAX2(config
->num_sgprs
,
3331 shader_info
->num_input_sgprs
+ 3);
3333 /* Enable 64-bit and 16-bit denormals, because there is no performance
3336 * If denormals are enabled, all floating-point output modifiers are
3339 * Don't enable denormals for 32-bit floats, because:
3340 * - Floating-point output modifiers would be ignored by the hw.
3341 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3342 * have to stop using those.
3343 * - SI & CI would be very slow.
3345 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
3349 ac_fill_shader_info(struct radv_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct radv_nir_compiler_options
*options
)
3351 switch (nir
->info
.stage
) {
3352 case MESA_SHADER_COMPUTE
:
3353 for (int i
= 0; i
< 3; ++i
)
3354 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
3356 case MESA_SHADER_FRAGMENT
:
3357 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
3359 case MESA_SHADER_GEOMETRY
:
3360 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
3361 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
3362 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
3363 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
3365 case MESA_SHADER_TESS_EVAL
:
3366 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
3367 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
3368 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
3369 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
3370 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
3372 case MESA_SHADER_TESS_CTRL
:
3373 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
3375 case MESA_SHADER_VERTEX
:
3376 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
3377 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
3378 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3379 if (options
->key
.vs
.as_ls
)
3380 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
3388 radv_compile_nir_shader(LLVMTargetMachineRef tm
,
3389 struct ac_shader_binary
*binary
,
3390 struct ac_shader_config
*config
,
3391 struct radv_shader_variant_info
*shader_info
,
3392 struct nir_shader
*const *nir
,
3394 const struct radv_nir_compiler_options
*options
)
3397 LLVMModuleRef llvm_module
;
3399 llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
3402 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
,
3403 nir
[0]->info
.stage
, options
);
3405 for (int i
= 0; i
< nir_count
; ++i
)
3406 ac_fill_shader_info(shader_info
, nir
[i
], options
);
3408 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3409 if (options
->chip_class
== GFX9
) {
3410 if (nir_count
== 2 &&
3411 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3412 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
3418 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
3420 LLVMValueRef vtx_offset
=
3421 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
3422 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3425 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3429 if (!(ctx
->output_mask
& (1ull << i
)))
3432 if (i
== VARYING_SLOT_CLIP_DIST0
) {
3433 /* unpack clip and cull from a single set of slots */
3434 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
3439 for (unsigned j
= 0; j
< length
; j
++) {
3440 LLVMValueRef value
, soffset
;
3442 soffset
= LLVMConstInt(ctx
->ac
.i32
,
3444 ctx
->gs_max_out_vertices
* 16 * 4, false);
3446 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->gsvs_ring
,
3448 vtx_offset
, soffset
,
3449 0, 1, 1, true, false);
3451 LLVMBuildStore(ctx
->ac
.builder
,
3452 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3456 handle_vs_outputs_post(ctx
, false, false, &ctx
->shader_info
->vs
.outinfo
);
3460 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm
,
3461 struct nir_shader
*geom_shader
,
3462 struct ac_shader_binary
*binary
,
3463 struct ac_shader_config
*config
,
3464 struct radv_shader_variant_info
*shader_info
,
3465 const struct radv_nir_compiler_options
*options
)
3467 struct radv_shader_context ctx
= {0};
3468 ctx
.context
= LLVMContextCreate();
3469 ctx
.options
= options
;
3470 ctx
.shader_info
= shader_info
;
3472 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
3474 ctx
.ac
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
3476 ctx
.is_gs_copy_shader
= true;
3477 LLVMSetTarget(ctx
.ac
.module
, "amdgcn--");
3479 enum ac_float_mode float_mode
=
3480 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
3481 AC_FLOAT_MODE_DEFAULT
;
3483 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
3484 ctx
.stage
= MESA_SHADER_VERTEX
;
3486 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
3488 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
3489 ac_setup_rings(&ctx
);
3491 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
3492 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
3494 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
3495 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
3496 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
3497 variable
, MESA_SHADER_VERTEX
);
3500 ac_gs_copy_shader_emit(&ctx
);
3502 LLVMBuildRetVoid(ctx
.ac
.builder
);
3504 ac_llvm_finalize_module(&ctx
);
3506 ac_compile_llvm_module(tm
, ctx
.ac
.module
, binary
, config
, shader_info
,
3507 MESA_SHADER_VERTEX
, options
);