2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 struct radv_shader_context
{
50 struct ac_llvm_context ac
;
51 const struct radv_nir_compiler_options
*options
;
52 struct radv_shader_variant_info
*shader_info
;
53 struct ac_shader_abi abi
;
55 unsigned max_workgroup_size
;
56 LLVMContextRef context
;
57 LLVMValueRef main_function
;
59 LLVMValueRef descriptor_sets
[RADV_UD_MAX_SETS
];
60 LLVMValueRef ring_offsets
;
62 LLVMValueRef vertex_buffers
;
63 LLVMValueRef rel_auto_id
;
64 LLVMValueRef vs_prim_id
;
65 LLVMValueRef es2gs_offset
;
68 LLVMValueRef merged_wave_info
;
69 LLVMValueRef tess_factor_offset
;
70 LLVMValueRef tes_rel_patch_id
;
74 LLVMValueRef gs2vs_offset
;
75 LLVMValueRef gs_wave_id
;
76 LLVMValueRef gs_vtx_offset
[6];
78 LLVMValueRef esgs_ring
;
79 LLVMValueRef gsvs_ring
[4];
80 LLVMValueRef hs_ring_tess_offchip
;
81 LLVMValueRef hs_ring_tess_factor
;
83 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
84 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
87 LLVMValueRef streamout_buffers
;
88 LLVMValueRef streamout_write_idx
;
89 LLVMValueRef streamout_config
;
90 LLVMValueRef streamout_offset
[4];
92 gl_shader_stage stage
;
94 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
99 bool is_gs_copy_shader
;
100 LLVMValueRef gs_next_vertex
[4];
101 unsigned gs_max_out_vertices
;
103 unsigned tes_primitive_mode
;
105 uint32_t tcs_patch_outputs_read
;
106 uint64_t tcs_outputs_read
;
107 uint32_t tcs_vertices_per_patch
;
108 uint32_t tcs_num_inputs
;
109 uint32_t tcs_num_patches
;
110 uint32_t max_gsvs_emit_size
;
111 uint32_t gsvs_vertex_size
;
114 enum radeon_llvm_calling_convention
{
115 RADEON_LLVM_AMDGPU_VS
= 87,
116 RADEON_LLVM_AMDGPU_GS
= 88,
117 RADEON_LLVM_AMDGPU_PS
= 89,
118 RADEON_LLVM_AMDGPU_CS
= 90,
119 RADEON_LLVM_AMDGPU_HS
= 93,
122 static inline struct radv_shader_context
*
123 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
125 struct radv_shader_context
*ctx
= NULL
;
126 return container_of(abi
, ctx
, abi
);
129 struct ac_build_if_state
131 struct radv_shader_context
*ctx
;
132 LLVMValueRef condition
;
133 LLVMBasicBlockRef entry_block
;
134 LLVMBasicBlockRef true_block
;
135 LLVMBasicBlockRef false_block
;
136 LLVMBasicBlockRef merge_block
;
139 static LLVMBasicBlockRef
140 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
142 LLVMBasicBlockRef current_block
;
143 LLVMBasicBlockRef next_block
;
144 LLVMBasicBlockRef new_block
;
146 /* get current basic block */
147 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
149 /* chqeck if there's another block after this one */
150 next_block
= LLVMGetNextBasicBlock(current_block
);
152 /* insert the new block before the next block */
153 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
156 /* append new block after current block */
157 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
158 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
164 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
165 struct radv_shader_context
*ctx
,
166 LLVMValueRef condition
)
168 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
170 memset(ifthen
, 0, sizeof *ifthen
);
172 ifthen
->condition
= condition
;
173 ifthen
->entry_block
= block
;
175 /* create endif/merge basic block for the phi functions */
176 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
178 /* create/insert true_block before merge_block */
180 LLVMInsertBasicBlockInContext(ctx
->context
,
184 /* successive code goes into the true block */
185 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
192 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
194 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
196 /* Insert branch to the merge block from current block */
197 LLVMBuildBr(builder
, ifthen
->merge_block
);
200 * Now patch in the various branch instructions.
203 /* Insert the conditional branch instruction at the end of entry_block */
204 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
205 if (ifthen
->false_block
) {
206 /* we have an else clause */
207 LLVMBuildCondBr(builder
, ifthen
->condition
,
208 ifthen
->true_block
, ifthen
->false_block
);
212 LLVMBuildCondBr(builder
, ifthen
->condition
,
213 ifthen
->true_block
, ifthen
->merge_block
);
216 /* Resume building code at end of the ifthen->merge_block */
217 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
221 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
223 switch (ctx
->stage
) {
224 case MESA_SHADER_TESS_CTRL
:
225 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
226 case MESA_SHADER_TESS_EVAL
:
227 return ctx
->tes_rel_patch_id
;
230 unreachable("Illegal stage");
235 get_tcs_num_patches(struct radv_shader_context
*ctx
)
237 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
238 unsigned num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
239 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
240 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
241 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
242 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
243 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
244 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
245 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
246 unsigned num_patches
;
247 unsigned hardware_lds_size
;
249 /* Ensure that we only need one wave per SIMD so we don't need to check
250 * resource usage. Also ensures that the number of tcs in and out
251 * vertices per threadgroup are at most 256.
253 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
254 /* Make sure that the data fits in LDS. This assumes the shaders only
255 * use LDS for the inputs and outputs.
257 hardware_lds_size
= 32768;
259 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
260 * threadgroup, even though there is more than 32 KiB LDS.
262 * Test: dEQP-VK.tessellation.shader_input_output.barrier
264 if (ctx
->options
->chip_class
>= CIK
&& ctx
->options
->family
!= CHIP_STONEY
)
265 hardware_lds_size
= 65536;
267 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
268 /* Make sure the output data fits in the offchip buffer */
269 num_patches
= MIN2(num_patches
, (ctx
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
270 /* Not necessary for correctness, but improves performance. The
271 * specific value is taken from the proprietary driver.
273 num_patches
= MIN2(num_patches
, 40);
275 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
276 if (ctx
->options
->chip_class
== SI
) {
277 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
278 num_patches
= MIN2(num_patches
, one_wave
);
284 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
286 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
287 unsigned num_tcs_output_cp
;
288 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
289 unsigned input_vertex_size
, output_vertex_size
;
290 unsigned input_patch_size
, output_patch_size
;
291 unsigned pervertex_output_patch_size
;
292 unsigned output_patch0_offset
;
293 unsigned num_patches
;
296 num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
297 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
298 num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
300 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
301 output_vertex_size
= num_tcs_outputs
* 16;
303 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
305 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
306 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
308 num_patches
= ctx
->tcs_num_patches
;
309 output_patch0_offset
= input_patch_size
* num_patches
;
311 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
315 /* Tessellation shaders pass outputs to the next shader using LDS.
317 * LS outputs = TCS inputs
318 * TCS outputs = TES inputs
321 * - TCS inputs for patch 0
322 * - TCS inputs for patch 1
323 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
325 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
326 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
327 * - TCS outputs for patch 1
328 * - Per-patch TCS outputs for patch 1
329 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
330 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
333 * All three shaders VS(LS), TCS, TES share the same LDS space.
336 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
338 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
339 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
340 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
342 input_patch_size
/= 4;
343 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
347 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
349 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
350 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
351 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
352 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
353 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
354 output_patch_size
/= 4;
355 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
359 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
361 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
362 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
363 output_vertex_size
/= 4;
364 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
368 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
370 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
371 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
372 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
373 uint32_t output_patch0_offset
= input_patch_size
;
374 unsigned num_patches
= ctx
->tcs_num_patches
;
376 output_patch0_offset
*= num_patches
;
377 output_patch0_offset
/= 4;
378 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
382 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
384 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
385 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
386 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
387 uint32_t output_patch0_offset
= input_patch_size
;
389 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
390 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
391 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
392 unsigned num_patches
= ctx
->tcs_num_patches
;
394 output_patch0_offset
*= num_patches
;
395 output_patch0_offset
+= pervertex_output_patch_size
;
396 output_patch0_offset
/= 4;
397 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
401 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
403 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
404 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
406 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
410 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
412 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
413 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
414 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
416 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
421 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
423 LLVMValueRef patch0_patch_data_offset
=
424 get_tcs_out_patch0_patch_data_offset(ctx
);
425 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
426 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
428 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
429 patch0_patch_data_offset
);
434 LLVMTypeRef types
[MAX_ARGS
];
435 LLVMValueRef
*assign
[MAX_ARGS
];
438 uint8_t num_sgprs_used
;
439 uint8_t num_vgprs_used
;
442 enum ac_arg_regfile
{
448 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
449 LLVMValueRef
*param_ptr
)
451 assert(info
->count
< MAX_ARGS
);
453 info
->assign
[info
->count
] = param_ptr
;
454 info
->types
[info
->count
] = type
;
457 if (regfile
== ARG_SGPR
) {
458 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
461 assert(regfile
== ARG_VGPR
);
462 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
466 static void assign_arguments(LLVMValueRef main_function
,
467 struct arg_info
*info
)
470 for (i
= 0; i
< info
->count
; i
++) {
472 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
477 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
478 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
479 unsigned num_return_elems
,
480 struct arg_info
*args
,
481 unsigned max_workgroup_size
,
482 const struct radv_nir_compiler_options
*options
)
484 LLVMTypeRef main_function_type
, ret_type
;
485 LLVMBasicBlockRef main_function_body
;
487 if (num_return_elems
)
488 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
489 num_return_elems
, true);
491 ret_type
= LLVMVoidTypeInContext(ctx
);
493 /* Setup the function */
495 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
496 LLVMValueRef main_function
=
497 LLVMAddFunction(module
, "main", main_function_type
);
499 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
500 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
502 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
503 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
504 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
506 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
508 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
509 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
510 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
514 if (options
->address32_hi
) {
515 ac_llvm_add_target_dep_function_attr(main_function
,
516 "amdgpu-32bit-address-high-bits",
517 options
->address32_hi
);
520 if (max_workgroup_size
) {
521 ac_llvm_add_target_dep_function_attr(main_function
,
522 "amdgpu-max-work-group-size",
525 if (options
->unsafe_math
) {
526 /* These were copied from some LLVM test. */
527 LLVMAddTargetDependentFunctionAttr(main_function
,
528 "less-precise-fpmad",
530 LLVMAddTargetDependentFunctionAttr(main_function
,
533 LLVMAddTargetDependentFunctionAttr(main_function
,
536 LLVMAddTargetDependentFunctionAttr(main_function
,
539 LLVMAddTargetDependentFunctionAttr(main_function
,
540 "no-signed-zeros-fp-math",
543 return main_function
;
548 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
,
551 ud_info
->sgpr_idx
= *sgpr_idx
;
552 ud_info
->num_sgprs
= num_sgprs
;
553 *sgpr_idx
+= num_sgprs
;
557 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
560 struct radv_userdata_info
*ud_info
=
561 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
564 set_loc(ud_info
, sgpr_idx
, num_sgprs
);
568 set_loc_shader_ptr(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
570 bool use_32bit_pointers
= idx
!= AC_UD_SCRATCH_RING_OFFSETS
;
572 set_loc_shader(ctx
, idx
, sgpr_idx
, use_32bit_pointers
? 1 : 2);
576 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
578 struct radv_userdata_locations
*locs
=
579 &ctx
->shader_info
->user_sgprs_locs
;
580 struct radv_userdata_info
*ud_info
= &locs
->descriptor_sets
[idx
];
583 set_loc(ud_info
, sgpr_idx
, 1);
585 locs
->descriptor_sets_enabled
|= 1 << idx
;
588 struct user_sgpr_info
{
589 bool need_ring_offsets
;
590 bool indirect_all_descriptor_sets
;
591 uint8_t remaining_sgprs
;
594 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
595 gl_shader_stage stage
)
598 case MESA_SHADER_VERTEX
:
599 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
600 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
603 case MESA_SHADER_TESS_EVAL
:
604 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
607 case MESA_SHADER_GEOMETRY
:
608 case MESA_SHADER_TESS_CTRL
:
609 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
619 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
623 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
625 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
630 static void allocate_inline_push_consts(struct radv_shader_context
*ctx
,
631 struct user_sgpr_info
*user_sgpr_info
)
633 uint8_t remaining_sgprs
= user_sgpr_info
->remaining_sgprs
;
635 /* Only supported if shaders use push constants. */
636 if (ctx
->shader_info
->info
.min_push_constant_used
== UINT8_MAX
)
639 /* Only supported if shaders don't have indirect push constants. */
640 if (ctx
->shader_info
->info
.has_indirect_push_constants
)
643 /* Only supported for 32-bit push constants. */
644 if (!ctx
->shader_info
->info
.has_only_32bit_push_constants
)
647 uint8_t num_push_consts
=
648 (ctx
->shader_info
->info
.max_push_constant_used
-
649 ctx
->shader_info
->info
.min_push_constant_used
) / 4;
651 /* Check if the number of user SGPRs is large enough. */
652 if (num_push_consts
< remaining_sgprs
) {
653 ctx
->shader_info
->info
.num_inline_push_consts
= num_push_consts
;
655 ctx
->shader_info
->info
.num_inline_push_consts
= remaining_sgprs
;
658 /* Clamp to the maximum number of allowed inlined push constants. */
659 if (ctx
->shader_info
->info
.num_inline_push_consts
> AC_MAX_INLINE_PUSH_CONSTS
)
660 ctx
->shader_info
->info
.num_inline_push_consts
= AC_MAX_INLINE_PUSH_CONSTS
;
662 if (ctx
->shader_info
->info
.num_inline_push_consts
== num_push_consts
&&
663 !ctx
->shader_info
->info
.loads_dynamic_offsets
) {
664 /* Disable the default push constants path if all constants are
665 * inlined and if shaders don't use dynamic descriptors.
667 ctx
->shader_info
->info
.loads_push_constants
= false;
670 ctx
->shader_info
->info
.base_inline_push_consts
=
671 ctx
->shader_info
->info
.min_push_constant_used
/ 4;
674 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
675 gl_shader_stage stage
,
676 bool has_previous_stage
,
677 gl_shader_stage previous_stage
,
678 bool needs_view_index
,
679 struct user_sgpr_info
*user_sgpr_info
)
681 uint8_t user_sgpr_count
= 0;
683 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
685 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
686 if (stage
== MESA_SHADER_GEOMETRY
||
687 stage
== MESA_SHADER_VERTEX
||
688 stage
== MESA_SHADER_TESS_CTRL
||
689 stage
== MESA_SHADER_TESS_EVAL
||
690 ctx
->is_gs_copy_shader
)
691 user_sgpr_info
->need_ring_offsets
= true;
693 if (stage
== MESA_SHADER_FRAGMENT
&&
694 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
695 user_sgpr_info
->need_ring_offsets
= true;
697 /* 2 user sgprs will nearly always be allocated for scratch/rings */
698 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
699 user_sgpr_count
+= 2;
703 case MESA_SHADER_COMPUTE
:
704 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
705 user_sgpr_count
+= 3;
707 case MESA_SHADER_FRAGMENT
:
708 user_sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
710 case MESA_SHADER_VERTEX
:
711 if (!ctx
->is_gs_copy_shader
)
712 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
714 case MESA_SHADER_TESS_CTRL
:
715 if (has_previous_stage
) {
716 if (previous_stage
== MESA_SHADER_VERTEX
)
717 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
720 case MESA_SHADER_TESS_EVAL
:
722 case MESA_SHADER_GEOMETRY
:
723 if (has_previous_stage
) {
724 if (previous_stage
== MESA_SHADER_VERTEX
) {
725 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
733 if (needs_view_index
)
736 if (ctx
->shader_info
->info
.loads_push_constants
)
739 if (ctx
->streamout_buffers
)
742 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
&& stage
!= MESA_SHADER_COMPUTE
? 32 : 16;
743 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_count
;
744 uint32_t num_desc_set
=
745 util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
);
747 if (remaining_sgprs
< num_desc_set
) {
748 user_sgpr_info
->indirect_all_descriptor_sets
= true;
749 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- 1;
751 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- num_desc_set
;
754 allocate_inline_push_consts(ctx
, user_sgpr_info
);
758 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
759 const struct user_sgpr_info
*user_sgpr_info
,
760 struct arg_info
*args
,
761 LLVMValueRef
*desc_sets
)
763 LLVMTypeRef type
= ac_array_in_const32_addr_space(ctx
->ac
.i8
);
765 /* 1 for each descriptor set */
766 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
767 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
770 int i
= u_bit_scan(&mask
);
772 add_arg(args
, ARG_SGPR
, type
, &ctx
->descriptor_sets
[i
]);
775 add_arg(args
, ARG_SGPR
, ac_array_in_const32_addr_space(type
),
779 if (ctx
->shader_info
->info
.loads_push_constants
) {
780 /* 1 for push constants and dynamic descriptors */
781 add_arg(args
, ARG_SGPR
, type
, &ctx
->abi
.push_constants
);
784 for (unsigned i
= 0; i
< ctx
->shader_info
->info
.num_inline_push_consts
; i
++) {
785 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
,
786 &ctx
->abi
.inline_push_consts
[i
]);
788 ctx
->abi
.num_inline_push_consts
= ctx
->shader_info
->info
.num_inline_push_consts
;
789 ctx
->abi
.base_inline_push_consts
= ctx
->shader_info
->info
.base_inline_push_consts
;
791 if (ctx
->shader_info
->info
.so
.num_outputs
) {
792 add_arg(args
, ARG_SGPR
,
793 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
794 &ctx
->streamout_buffers
);
799 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
800 gl_shader_stage stage
,
801 bool has_previous_stage
,
802 gl_shader_stage previous_stage
,
803 struct arg_info
*args
)
805 if (!ctx
->is_gs_copy_shader
&&
806 (stage
== MESA_SHADER_VERTEX
||
807 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
808 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
809 add_arg(args
, ARG_SGPR
,
810 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
811 &ctx
->vertex_buffers
);
813 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
814 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
815 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
816 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
822 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
824 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
825 if (!ctx
->is_gs_copy_shader
) {
826 if (ctx
->options
->key
.vs
.as_ls
) {
827 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
828 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
830 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
831 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
833 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
838 declare_streamout_sgprs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
839 struct arg_info
*args
)
843 /* Streamout SGPRs. */
844 if (ctx
->shader_info
->info
.so
.num_outputs
) {
845 assert(stage
== MESA_SHADER_VERTEX
||
846 stage
== MESA_SHADER_TESS_EVAL
);
848 if (stage
!= MESA_SHADER_TESS_EVAL
) {
849 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_config
);
851 args
->assign
[args
->count
- 1] = &ctx
->streamout_config
;
852 args
->types
[args
->count
- 1] = ctx
->ac
.i32
;
855 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_write_idx
);
858 /* A streamout buffer offset is loaded if the stride is non-zero. */
859 for (i
= 0; i
< 4; i
++) {
860 if (!ctx
->shader_info
->info
.so
.strides
[i
])
863 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_offset
[i
]);
868 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
870 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
871 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
872 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
873 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
877 set_global_input_locs(struct radv_shader_context
*ctx
,
878 const struct user_sgpr_info
*user_sgpr_info
,
879 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
881 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
883 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
885 int i
= u_bit_scan(&mask
);
887 set_loc_desc(ctx
, i
, user_sgpr_idx
);
890 set_loc_shader_ptr(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
894 int i
= u_bit_scan(&mask
);
896 ctx
->descriptor_sets
[i
] =
897 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
898 LLVMConstInt(ctx
->ac
.i32
, i
, false));
902 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
905 if (ctx
->shader_info
->info
.loads_push_constants
) {
906 set_loc_shader_ptr(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
);
909 if (ctx
->shader_info
->info
.num_inline_push_consts
) {
910 set_loc_shader(ctx
, AC_UD_INLINE_PUSH_CONSTANTS
, user_sgpr_idx
,
911 ctx
->shader_info
->info
.num_inline_push_consts
);
914 if (ctx
->streamout_buffers
) {
915 set_loc_shader_ptr(ctx
, AC_UD_STREAMOUT_BUFFERS
,
921 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
922 gl_shader_stage stage
, bool has_previous_stage
,
923 gl_shader_stage previous_stage
,
924 uint8_t *user_sgpr_idx
)
926 if (!ctx
->is_gs_copy_shader
&&
927 (stage
== MESA_SHADER_VERTEX
||
928 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
929 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
930 set_loc_shader_ptr(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
935 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
938 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
939 user_sgpr_idx
, vs_num
);
943 static void set_llvm_calling_convention(LLVMValueRef func
,
944 gl_shader_stage stage
)
946 enum radeon_llvm_calling_convention calling_conv
;
949 case MESA_SHADER_VERTEX
:
950 case MESA_SHADER_TESS_EVAL
:
951 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
953 case MESA_SHADER_GEOMETRY
:
954 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
956 case MESA_SHADER_TESS_CTRL
:
957 calling_conv
= RADEON_LLVM_AMDGPU_HS
;
959 case MESA_SHADER_FRAGMENT
:
960 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
962 case MESA_SHADER_COMPUTE
:
963 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
966 unreachable("Unhandle shader type");
969 LLVMSetFunctionCallConv(func
, calling_conv
);
972 static void create_function(struct radv_shader_context
*ctx
,
973 gl_shader_stage stage
,
974 bool has_previous_stage
,
975 gl_shader_stage previous_stage
)
977 uint8_t user_sgpr_idx
;
978 struct user_sgpr_info user_sgpr_info
;
979 struct arg_info args
= {};
980 LLVMValueRef desc_sets
;
981 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
982 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
983 previous_stage
, needs_view_index
, &user_sgpr_info
);
985 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
986 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
991 case MESA_SHADER_COMPUTE
:
992 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
995 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
996 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
997 &ctx
->abi
.num_work_groups
);
1000 for (int i
= 0; i
< 3; i
++) {
1001 ctx
->abi
.workgroup_ids
[i
] = NULL
;
1002 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
1003 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1004 &ctx
->abi
.workgroup_ids
[i
]);
1008 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
1009 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
1010 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
1011 &ctx
->abi
.local_invocation_ids
);
1013 case MESA_SHADER_VERTEX
:
1014 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1017 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
1018 previous_stage
, &args
);
1020 if (needs_view_index
)
1021 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1022 &ctx
->abi
.view_index
);
1023 if (ctx
->options
->key
.vs
.as_es
) {
1024 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1025 &ctx
->es2gs_offset
);
1026 } else if (ctx
->options
->key
.vs
.as_ls
) {
1027 /* no extra parameters */
1029 declare_streamout_sgprs(ctx
, stage
, &args
);
1032 declare_vs_input_vgprs(ctx
, &args
);
1034 case MESA_SHADER_TESS_CTRL
:
1035 if (has_previous_stage
) {
1036 // First 6 system regs
1037 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1038 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1039 &ctx
->merged_wave_info
);
1040 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1041 &ctx
->tess_factor_offset
);
1043 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1044 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1045 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1047 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1050 declare_vs_specific_input_sgprs(ctx
, stage
,
1052 previous_stage
, &args
);
1054 if (needs_view_index
)
1055 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1056 &ctx
->abi
.view_index
);
1058 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1059 &ctx
->abi
.tcs_patch_id
);
1060 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1061 &ctx
->abi
.tcs_rel_ids
);
1063 declare_vs_input_vgprs(ctx
, &args
);
1065 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1068 if (needs_view_index
)
1069 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1070 &ctx
->abi
.view_index
);
1072 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1073 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1074 &ctx
->tess_factor_offset
);
1075 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1076 &ctx
->abi
.tcs_patch_id
);
1077 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1078 &ctx
->abi
.tcs_rel_ids
);
1081 case MESA_SHADER_TESS_EVAL
:
1082 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1085 if (needs_view_index
)
1086 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1087 &ctx
->abi
.view_index
);
1089 if (ctx
->options
->key
.tes
.as_es
) {
1090 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1091 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1092 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1093 &ctx
->es2gs_offset
);
1095 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1096 declare_streamout_sgprs(ctx
, stage
, &args
);
1097 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1099 declare_tes_input_vgprs(ctx
, &args
);
1101 case MESA_SHADER_GEOMETRY
:
1102 if (has_previous_stage
) {
1103 // First 6 system regs
1104 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1105 &ctx
->gs2vs_offset
);
1106 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1107 &ctx
->merged_wave_info
);
1108 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1110 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1111 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1112 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1114 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1117 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
1118 declare_vs_specific_input_sgprs(ctx
, stage
,
1124 if (needs_view_index
)
1125 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1126 &ctx
->abi
.view_index
);
1128 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1129 &ctx
->gs_vtx_offset
[0]);
1130 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1131 &ctx
->gs_vtx_offset
[2]);
1132 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1133 &ctx
->abi
.gs_prim_id
);
1134 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1135 &ctx
->abi
.gs_invocation_id
);
1136 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1137 &ctx
->gs_vtx_offset
[4]);
1139 if (previous_stage
== MESA_SHADER_VERTEX
) {
1140 declare_vs_input_vgprs(ctx
, &args
);
1142 declare_tes_input_vgprs(ctx
, &args
);
1145 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1148 if (needs_view_index
)
1149 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1150 &ctx
->abi
.view_index
);
1152 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1153 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1154 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1155 &ctx
->gs_vtx_offset
[0]);
1156 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1157 &ctx
->gs_vtx_offset
[1]);
1158 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1159 &ctx
->abi
.gs_prim_id
);
1160 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1161 &ctx
->gs_vtx_offset
[2]);
1162 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1163 &ctx
->gs_vtx_offset
[3]);
1164 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1165 &ctx
->gs_vtx_offset
[4]);
1166 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1167 &ctx
->gs_vtx_offset
[5]);
1168 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1169 &ctx
->abi
.gs_invocation_id
);
1172 case MESA_SHADER_FRAGMENT
:
1173 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1176 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1177 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1178 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1179 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1180 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1181 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1182 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1183 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1184 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1185 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1186 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1187 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1188 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1189 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1190 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1191 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1192 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1195 unreachable("Shader stage not implemented");
1198 ctx
->main_function
= create_llvm_function(
1199 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1200 ctx
->max_workgroup_size
, ctx
->options
);
1201 set_llvm_calling_convention(ctx
->main_function
, stage
);
1204 ctx
->shader_info
->num_input_vgprs
= 0;
1205 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1207 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1209 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1210 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1212 assign_arguments(ctx
->main_function
, &args
);
1216 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1217 set_loc_shader_ptr(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1219 if (ctx
->options
->supports_spill
) {
1220 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1221 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
1222 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1223 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1224 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1228 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1229 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1230 if (has_previous_stage
)
1233 set_global_input_locs(ctx
, &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1236 case MESA_SHADER_COMPUTE
:
1237 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1238 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1242 case MESA_SHADER_VERTEX
:
1243 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1244 previous_stage
, &user_sgpr_idx
);
1245 if (ctx
->abi
.view_index
)
1246 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1248 case MESA_SHADER_TESS_CTRL
:
1249 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1250 previous_stage
, &user_sgpr_idx
);
1251 if (ctx
->abi
.view_index
)
1252 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1254 case MESA_SHADER_TESS_EVAL
:
1255 if (ctx
->abi
.view_index
)
1256 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1258 case MESA_SHADER_GEOMETRY
:
1259 if (has_previous_stage
) {
1260 if (previous_stage
== MESA_SHADER_VERTEX
)
1261 set_vs_specific_input_locs(ctx
, stage
,
1266 if (ctx
->abi
.view_index
)
1267 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1269 case MESA_SHADER_FRAGMENT
:
1272 unreachable("Shader stage not implemented");
1275 if (stage
== MESA_SHADER_TESS_CTRL
||
1276 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_ls
) ||
1277 /* GFX9 has the ESGS ring buffer in LDS. */
1278 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1279 ac_declare_lds_as_pointer(&ctx
->ac
);
1282 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1287 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1288 unsigned desc_set
, unsigned binding
)
1290 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1291 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1292 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
1293 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1294 unsigned base_offset
= layout
->binding
[binding
].offset
;
1295 LLVMValueRef offset
, stride
;
1297 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1298 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1299 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1300 layout
->binding
[binding
].dynamic_offset_offset
;
1301 desc_ptr
= ctx
->abi
.push_constants
;
1302 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1303 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1305 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1307 offset
= ac_build_imad(&ctx
->ac
, index
, stride
,
1308 LLVMConstInt(ctx
->ac
.i32
, base_offset
, false));
1310 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
1311 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1312 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1318 /* The offchip buffer layout for TCS->TES is
1320 * - attribute 0 of patch 0 vertex 0
1321 * - attribute 0 of patch 0 vertex 1
1322 * - attribute 0 of patch 0 vertex 2
1324 * - attribute 0 of patch 1 vertex 0
1325 * - attribute 0 of patch 1 vertex 1
1327 * - attribute 1 of patch 0 vertex 0
1328 * - attribute 1 of patch 0 vertex 1
1330 * - per patch attribute 0 of patch 0
1331 * - per patch attribute 0 of patch 1
1334 * Note that every attribute has 4 components.
1336 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1338 uint32_t num_patches
= ctx
->tcs_num_patches
;
1339 uint32_t num_tcs_outputs
;
1340 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1341 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
1343 num_tcs_outputs
= ctx
->options
->key
.tes
.tcs_num_outputs
;
1345 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1346 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
1348 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1351 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1352 LLVMValueRef vertex_index
)
1354 LLVMValueRef param_stride
;
1356 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
* ctx
->tcs_num_patches
, false);
1358 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1359 return param_stride
;
1362 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1363 LLVMValueRef vertex_index
,
1364 LLVMValueRef param_index
)
1366 LLVMValueRef base_addr
;
1367 LLVMValueRef param_stride
, constant16
;
1368 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1369 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
1370 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1371 param_stride
= calc_param_stride(ctx
, vertex_index
);
1373 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
1374 vertices_per_patch
, vertex_index
);
1376 base_addr
= rel_patch_id
;
1379 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1380 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1381 param_stride
, ""), "");
1383 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1385 if (!vertex_index
) {
1386 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1388 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1389 patch_data_offset
, "");
1394 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1396 unsigned const_index
,
1398 LLVMValueRef vertex_index
,
1399 LLVMValueRef indir_index
)
1401 LLVMValueRef param_index
;
1404 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1407 if (const_index
&& !is_compact
)
1408 param
+= const_index
;
1409 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1411 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1415 get_dw_address(struct radv_shader_context
*ctx
,
1416 LLVMValueRef dw_addr
,
1418 unsigned const_index
,
1419 bool compact_const_index
,
1420 LLVMValueRef vertex_index
,
1421 LLVMValueRef stride
,
1422 LLVMValueRef indir_index
)
1427 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1428 LLVMBuildMul(ctx
->ac
.builder
,
1434 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1435 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1436 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1437 else if (const_index
&& !compact_const_index
)
1438 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1439 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1441 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1442 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1444 if (const_index
&& compact_const_index
)
1445 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1446 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1451 load_tcs_varyings(struct ac_shader_abi
*abi
,
1453 LLVMValueRef vertex_index
,
1454 LLVMValueRef indir_index
,
1455 unsigned const_index
,
1457 unsigned driver_location
,
1459 unsigned num_components
,
1464 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1465 LLVMValueRef dw_addr
, stride
;
1466 LLVMValueRef value
[4], result
;
1467 unsigned param
= shader_io_get_unique_index(location
);
1470 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1471 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1472 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1475 stride
= get_tcs_out_vertex_stride(ctx
);
1476 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1478 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1483 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1486 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1487 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1488 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1491 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1496 store_tcs_output(struct ac_shader_abi
*abi
,
1497 const nir_variable
*var
,
1498 LLVMValueRef vertex_index
,
1499 LLVMValueRef param_index
,
1500 unsigned const_index
,
1504 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1505 const unsigned location
= var
->data
.location
;
1506 const unsigned component
= var
->data
.location_frac
;
1507 const bool is_patch
= var
->data
.patch
;
1508 const bool is_compact
= var
->data
.compact
;
1509 LLVMValueRef dw_addr
;
1510 LLVMValueRef stride
= NULL
;
1511 LLVMValueRef buf_addr
= NULL
;
1513 bool store_lds
= true;
1516 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1519 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
1523 param
= shader_io_get_unique_index(location
);
1524 if (location
== VARYING_SLOT_CLIP_DIST0
&&
1525 is_compact
&& const_index
> 3) {
1531 stride
= get_tcs_out_vertex_stride(ctx
);
1532 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1534 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1537 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1539 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1540 vertex_index
, param_index
);
1542 bool is_tess_factor
= false;
1543 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1544 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1545 is_tess_factor
= true;
1547 unsigned base
= is_compact
? const_index
: 0;
1548 for (unsigned chan
= 0; chan
< 8; chan
++) {
1549 if (!(writemask
& (1 << chan
)))
1551 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1552 value
= ac_to_integer(&ctx
->ac
, value
);
1553 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
1555 if (store_lds
|| is_tess_factor
) {
1556 LLVMValueRef dw_addr_chan
=
1557 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1558 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1559 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1562 if (!is_tess_factor
&& writemask
!= 0xF)
1563 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1564 buf_addr
, ctx
->oc_lds
,
1565 4 * (base
+ chan
), 1, 0, true, false);
1568 if (writemask
== 0xF) {
1569 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1570 buf_addr
, ctx
->oc_lds
,
1571 (base
* 4), 1, 0, true, false);
1576 load_tes_input(struct ac_shader_abi
*abi
,
1578 LLVMValueRef vertex_index
,
1579 LLVMValueRef param_index
,
1580 unsigned const_index
,
1582 unsigned driver_location
,
1584 unsigned num_components
,
1589 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1590 LLVMValueRef buf_addr
;
1591 LLVMValueRef result
;
1592 unsigned param
= shader_io_get_unique_index(location
);
1594 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
1599 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1600 is_compact
, vertex_index
, param_index
);
1602 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1603 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1605 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1606 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
1607 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1612 load_gs_input(struct ac_shader_abi
*abi
,
1614 unsigned driver_location
,
1616 unsigned num_components
,
1617 unsigned vertex_index
,
1618 unsigned const_index
,
1621 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1622 LLVMValueRef vtx_offset
;
1623 unsigned param
, vtx_offset_param
;
1624 LLVMValueRef value
[4], result
;
1626 vtx_offset_param
= vertex_index
;
1627 assert(vtx_offset_param
< 6);
1628 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1629 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1631 param
= shader_io_get_unique_index(location
);
1633 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1634 if (ctx
->ac
.chip_class
>= GFX9
) {
1635 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1636 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1637 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1638 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1640 LLVMValueRef soffset
=
1641 LLVMConstInt(ctx
->ac
.i32
,
1642 (param
* 4 + i
+ const_index
) * 256,
1645 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1648 vtx_offset
, soffset
,
1649 0, 1, 0, true, false);
1652 if (ac_get_type_size(type
) == 2) {
1653 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
1654 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
1656 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
1658 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1659 result
= ac_to_integer(&ctx
->ac
, result
);
1664 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1666 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1667 ac_build_kill_if_false(&ctx
->ac
, visible
);
1670 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
1671 enum glsl_interp_mode interp
, unsigned location
)
1673 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1676 case INTERP_MODE_FLAT
:
1679 case INTERP_MODE_SMOOTH
:
1680 case INTERP_MODE_NONE
:
1681 if (location
== INTERP_CENTER
)
1682 return ctx
->persp_center
;
1683 else if (location
== INTERP_CENTROID
)
1684 return ctx
->persp_centroid
;
1685 else if (location
== INTERP_SAMPLE
)
1686 return ctx
->persp_sample
;
1688 case INTERP_MODE_NOPERSPECTIVE
:
1689 if (location
== INTERP_CENTER
)
1690 return ctx
->linear_center
;
1691 else if (location
== INTERP_CENTROID
)
1692 return ctx
->linear_centroid
;
1693 else if (location
== INTERP_SAMPLE
)
1694 return ctx
->linear_sample
;
1701 radv_get_sample_pos_offset(uint32_t num_samples
)
1703 uint32_t sample_pos_offset
= 0;
1705 switch (num_samples
) {
1707 sample_pos_offset
= 1;
1710 sample_pos_offset
= 3;
1713 sample_pos_offset
= 7;
1718 return sample_pos_offset
;
1721 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1722 LLVMValueRef sample_id
)
1724 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1726 LLVMValueRef result
;
1727 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
1729 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1730 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1732 uint32_t sample_pos_offset
=
1733 radv_get_sample_pos_offset(ctx
->options
->key
.fs
.num_samples
);
1736 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
1737 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
1738 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1744 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1746 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1747 uint8_t log2_ps_iter_samples
;
1749 if (ctx
->shader_info
->info
.ps
.force_persample
) {
1750 log2_ps_iter_samples
=
1751 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
1753 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
1756 /* The bit pattern matches that used by fixed function fragment
1758 static const uint16_t ps_iter_masks
[] = {
1759 0xffff, /* not used */
1765 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1767 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1769 LLVMValueRef result
, sample_id
;
1770 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
1771 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1772 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
1778 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1780 LLVMValueRef gs_next_vertex
;
1781 LLVMValueRef can_emit
;
1782 unsigned offset
= 0;
1783 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1785 /* Write vertex attribute values to GSVS ring */
1786 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1787 ctx
->gs_next_vertex
[stream
],
1790 /* If this thread has already emitted the declared maximum number of
1791 * vertices, kill it: excessive vertex emissions are not supposed to
1792 * have any effect, and GS threads have no externally observable
1793 * effects other than emitting vertices.
1795 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1796 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
1797 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1799 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1800 unsigned output_usage_mask
=
1801 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
1802 uint8_t output_stream
=
1803 ctx
->shader_info
->info
.gs
.output_streams
[i
];
1804 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1805 int length
= util_last_bit(output_usage_mask
);
1807 if (!(ctx
->output_mask
& (1ull << i
)) ||
1808 output_stream
!= stream
)
1811 for (unsigned j
= 0; j
< length
; j
++) {
1812 if (!(output_usage_mask
& (1 << j
)))
1815 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1817 LLVMValueRef voffset
=
1818 LLVMConstInt(ctx
->ac
.i32
, offset
*
1819 ctx
->gs_max_out_vertices
, false);
1823 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1824 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1826 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1827 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1829 ac_build_buffer_store_dword(&ctx
->ac
,
1830 ctx
->gsvs_ring
[stream
],
1832 voffset
, ctx
->gs2vs_offset
, 0,
1837 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1839 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1841 ac_build_sendmsg(&ctx
->ac
,
1842 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1847 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1849 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1850 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1854 load_tess_coord(struct ac_shader_abi
*abi
)
1856 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1858 LLVMValueRef coord
[4] = {
1865 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
1866 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1867 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1869 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1873 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1875 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1876 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
1880 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1882 return abi
->base_vertex
;
1885 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1886 LLVMValueRef buffer_ptr
, bool write
)
1888 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1889 LLVMValueRef result
;
1891 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1893 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1894 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1899 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1901 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1902 LLVMValueRef result
;
1904 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1906 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1907 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1912 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1913 unsigned descriptor_set
,
1914 unsigned base_index
,
1915 unsigned constant_index
,
1917 enum ac_descriptor_type desc_type
,
1918 bool image
, bool write
,
1921 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1922 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1923 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
1924 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1925 unsigned offset
= binding
->offset
;
1926 unsigned stride
= binding
->size
;
1928 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1931 assert(base_index
< layout
->binding_count
);
1933 switch (desc_type
) {
1935 type
= ctx
->ac
.v8i32
;
1939 type
= ctx
->ac
.v8i32
;
1943 case AC_DESC_SAMPLER
:
1944 type
= ctx
->ac
.v4i32
;
1945 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1950 case AC_DESC_BUFFER
:
1951 type
= ctx
->ac
.v4i32
;
1955 unreachable("invalid desc_type\n");
1958 offset
+= constant_index
* stride
;
1960 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
1961 (!index
|| binding
->immutable_samplers_equal
)) {
1962 if (binding
->immutable_samplers_equal
)
1965 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
1967 LLVMValueRef constants
[] = {
1968 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
1969 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
1970 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
1971 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
1973 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
1976 assert(stride
% type_size
== 0);
1979 index
= ctx
->ac
.i32_0
;
1981 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
1983 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
1984 list
= LLVMBuildPointerCast(builder
, list
,
1985 ac_array_in_const32_addr_space(type
), "");
1987 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
1990 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1991 * so we may need to fix it up. */
1993 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
1994 unsigned adjustment
,
1997 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
2000 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
2002 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
2003 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2005 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
2007 /* For the integer-like cases, do a natural sign extension.
2009 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2010 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2013 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
2014 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
2015 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
2016 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
2018 /* Convert back to the right type. */
2019 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
2021 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
2022 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2023 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
2024 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
2025 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
2026 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2033 get_num_channels_from_data_format(unsigned data_format
)
2035 switch (data_format
) {
2036 case V_008F0C_BUF_DATA_FORMAT_8
:
2037 case V_008F0C_BUF_DATA_FORMAT_16
:
2038 case V_008F0C_BUF_DATA_FORMAT_32
:
2040 case V_008F0C_BUF_DATA_FORMAT_8_8
:
2041 case V_008F0C_BUF_DATA_FORMAT_16_16
:
2042 case V_008F0C_BUF_DATA_FORMAT_32_32
:
2044 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
2045 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
2046 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
2048 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
2049 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
2050 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
2051 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
2052 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
2062 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
2064 unsigned num_channels
,
2067 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
2068 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
2069 LLVMValueRef chan
[4];
2071 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
2072 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
2074 if (num_channels
== 4 && num_channels
== vec_size
)
2077 num_channels
= MIN2(num_channels
, vec_size
);
2079 for (unsigned i
= 0; i
< num_channels
; i
++)
2080 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
2083 assert(num_channels
== 1);
2088 for (unsigned i
= num_channels
; i
< 4; i
++) {
2089 chan
[i
] = i
== 3 ? one
: zero
;
2090 chan
[i
] = ac_to_float(&ctx
->ac
, chan
[i
]);
2093 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
2097 handle_vs_input_decl(struct radv_shader_context
*ctx
,
2098 struct nir_variable
*variable
)
2100 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
2101 LLVMValueRef t_offset
;
2102 LLVMValueRef t_list
;
2104 LLVMValueRef buffer_index
;
2105 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
2106 uint8_t input_usage_mask
=
2107 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
2108 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
2110 variable
->data
.driver_location
= variable
->data
.location
* 4;
2112 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
2113 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
2114 LLVMValueRef output
[4];
2115 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
2116 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
2117 unsigned data_format
= attrib_format
& 0x0f;
2118 unsigned num_format
= (attrib_format
>> 4) & 0x07;
2119 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
2120 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
2122 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
2123 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
2126 buffer_index
= ctx
->abi
.instance_id
;
2129 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
2130 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
2133 if (ctx
->options
->key
.vs
.as_ls
) {
2134 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
2135 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
2137 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
2138 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
2141 buffer_index
= ctx
->ac
.i32_0
;
2144 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.start_instance
, buffer_index
, "");
2146 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
2147 ctx
->abi
.base_vertex
, "");
2148 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_index
, false);
2150 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
2152 /* Adjust the number of channels to load based on the vertex
2155 unsigned num_format_channels
= get_num_channels_from_data_format(data_format
);
2156 unsigned num_channels
= MIN2(num_input_channels
, num_format_channels
);
2158 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
2161 num_channels
, false, true);
2163 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
2166 for (unsigned chan
= 0; chan
< 4; chan
++) {
2167 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2168 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
2169 if (type
== GLSL_TYPE_FLOAT16
) {
2170 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
2171 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
2175 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
2176 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
2178 for (unsigned chan
= 0; chan
< 4; chan
++) {
2179 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
2180 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
2181 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
2183 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
2188 static void interp_fs_input(struct radv_shader_context
*ctx
,
2190 LLVMValueRef interp_param
,
2191 LLVMValueRef prim_mask
,
2192 LLVMValueRef result
[4])
2194 LLVMValueRef attr_number
;
2197 bool interp
= !LLVMIsUndef(interp_param
);
2199 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
2201 /* fs.constant returns the param from the middle vertex, so it's not
2202 * really useful for flat shading. It's meant to be used for custom
2203 * interpolation (but the intrinsic can't fetch from the other two
2206 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2207 * to do the right thing. The only reason we use fs.constant is that
2208 * fs.interp cannot be used on integers, because they can be equal
2212 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
2215 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
2217 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
2221 for (chan
= 0; chan
< 4; chan
++) {
2222 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2225 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
2230 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
2231 LLVMConstInt(ctx
->ac
.i32
, 2, false),
2235 result
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, result
[chan
], ctx
->ac
.i32
, "");
2236 result
[chan
] = LLVMBuildTruncOrBitCast(ctx
->ac
.builder
, result
[chan
], LLVMTypeOf(interp_param
), "");
2242 handle_fs_input_decl(struct radv_shader_context
*ctx
,
2243 struct nir_variable
*variable
)
2245 int idx
= variable
->data
.location
;
2246 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2247 LLVMValueRef interp
= NULL
;
2250 variable
->data
.driver_location
= idx
* 4;
2251 mask
= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
2253 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
2254 unsigned interp_type
;
2255 if (variable
->data
.sample
)
2256 interp_type
= INTERP_SAMPLE
;
2257 else if (variable
->data
.centroid
)
2258 interp_type
= INTERP_CENTROID
;
2260 interp_type
= INTERP_CENTER
;
2262 interp
= lookup_interp_param(&ctx
->abi
, variable
->data
.interpolation
, interp_type
);
2264 bool is_16bit
= glsl_type_is_16bit(glsl_without_array(variable
->type
));
2265 LLVMTypeRef type
= is_16bit
? ctx
->ac
.i16
: ctx
->ac
.i32
;
2267 interp
= LLVMGetUndef(type
);
2269 for (unsigned i
= 0; i
< attrib_count
; ++i
)
2270 ctx
->inputs
[ac_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
2272 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2273 /* Do not account for the number of components inside the array
2274 * of clip/cull distances because this might wrongly set other
2275 * bits like primitive ID or layer.
2277 mask
= 1ull << VARYING_SLOT_CLIP_DIST0
;
2280 ctx
->input_mask
|= mask
;
2284 handle_vs_inputs(struct radv_shader_context
*ctx
,
2285 struct nir_shader
*nir
) {
2286 nir_foreach_variable(variable
, &nir
->inputs
)
2287 handle_vs_input_decl(ctx
, variable
);
2291 prepare_interp_optimize(struct radv_shader_context
*ctx
,
2292 struct nir_shader
*nir
)
2294 bool uses_center
= false;
2295 bool uses_centroid
= false;
2296 nir_foreach_variable(variable
, &nir
->inputs
) {
2297 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
2298 variable
->data
.sample
)
2301 if (variable
->data
.centroid
)
2302 uses_centroid
= true;
2307 if (uses_center
&& uses_centroid
) {
2308 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
2309 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
2310 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
2315 handle_fs_inputs(struct radv_shader_context
*ctx
,
2316 struct nir_shader
*nir
)
2318 prepare_interp_optimize(ctx
, nir
);
2320 nir_foreach_variable(variable
, &nir
->inputs
)
2321 handle_fs_input_decl(ctx
, variable
);
2325 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
2326 ctx
->shader_info
->info
.needs_multiview_view_index
) {
2327 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
2328 ctx
->inputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)] = LLVMGetUndef(ctx
->ac
.i32
);
2331 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
2332 LLVMValueRef interp_param
;
2333 LLVMValueRef
*inputs
= ctx
->inputs
+ac_llvm_reg_index_soa(i
, 0);
2335 if (!(ctx
->input_mask
& (1ull << i
)))
2338 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
2339 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
2340 interp_param
= *inputs
;
2341 interp_fs_input(ctx
, index
, interp_param
, ctx
->abi
.prim_mask
,
2344 if (LLVMIsUndef(interp_param
))
2345 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
2346 if (i
>= VARYING_SLOT_VAR0
)
2347 ctx
->abi
.fs_input_attr_indices
[i
- VARYING_SLOT_VAR0
] = index
;
2349 } else if (i
== VARYING_SLOT_CLIP_DIST0
) {
2350 int length
= ctx
->shader_info
->info
.ps
.num_input_clips_culls
;
2352 for (unsigned j
= 0; j
< length
; j
+= 4) {
2353 inputs
= ctx
->inputs
+ ac_llvm_reg_index_soa(i
, j
);
2355 interp_param
= *inputs
;
2356 interp_fs_input(ctx
, index
, interp_param
,
2357 ctx
->abi
.prim_mask
, inputs
);
2360 } else if (i
== VARYING_SLOT_POS
) {
2361 for(int i
= 0; i
< 3; ++i
)
2362 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
2364 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
2365 ctx
->abi
.frag_pos
[3]);
2368 ctx
->shader_info
->fs
.num_interp
= index
;
2369 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
2371 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
2372 ctx
->abi
.view_index
= ctx
->inputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2376 scan_shader_output_decl(struct radv_shader_context
*ctx
,
2377 struct nir_variable
*variable
,
2378 struct nir_shader
*shader
,
2379 gl_shader_stage stage
)
2381 int idx
= variable
->data
.location
+ variable
->data
.index
;
2382 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2383 uint64_t mask_attribs
;
2385 variable
->data
.driver_location
= idx
* 4;
2387 /* tess ctrl has it's own load/store paths for outputs */
2388 if (stage
== MESA_SHADER_TESS_CTRL
)
2391 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2392 if (stage
== MESA_SHADER_VERTEX
||
2393 stage
== MESA_SHADER_TESS_EVAL
||
2394 stage
== MESA_SHADER_GEOMETRY
) {
2395 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2396 if (stage
== MESA_SHADER_VERTEX
) {
2397 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2398 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2399 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2401 if (stage
== MESA_SHADER_TESS_EVAL
) {
2402 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2403 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2404 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2407 mask_attribs
= 1ull << idx
;
2411 ctx
->output_mask
|= mask_attribs
;
2415 /* Initialize arguments for the shader export intrinsic */
2417 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2418 LLVMValueRef
*values
,
2419 unsigned enabled_channels
,
2421 struct ac_export_args
*args
)
2423 /* Specify the channels that are enabled. */
2424 args
->enabled_channels
= enabled_channels
;
2426 /* Specify whether the EXEC mask represents the valid mask */
2427 args
->valid_mask
= 0;
2429 /* Specify whether this is the last export */
2432 /* Specify the target we are exporting */
2433 args
->target
= target
;
2435 args
->compr
= false;
2436 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2437 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2438 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2439 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2444 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
2445 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2446 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2447 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2448 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2449 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2452 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2453 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2454 unsigned bits
, bool hi
) = NULL
;
2456 switch(col_format
) {
2457 case V_028714_SPI_SHADER_ZERO
:
2458 args
->enabled_channels
= 0; /* writemask */
2459 args
->target
= V_008DFC_SQ_EXP_NULL
;
2462 case V_028714_SPI_SHADER_32_R
:
2463 args
->enabled_channels
= 1;
2464 args
->out
[0] = values
[0];
2467 case V_028714_SPI_SHADER_32_GR
:
2468 args
->enabled_channels
= 0x3;
2469 args
->out
[0] = values
[0];
2470 args
->out
[1] = values
[1];
2473 case V_028714_SPI_SHADER_32_AR
:
2474 args
->enabled_channels
= 0x9;
2475 args
->out
[0] = values
[0];
2476 args
->out
[3] = values
[3];
2479 case V_028714_SPI_SHADER_FP16_ABGR
:
2480 args
->enabled_channels
= 0x5;
2481 packf
= ac_build_cvt_pkrtz_f16
;
2483 for (unsigned chan
= 0; chan
< 4; chan
++)
2484 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
2490 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2491 args
->enabled_channels
= 0x5;
2492 packf
= ac_build_cvt_pknorm_u16
;
2495 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2496 args
->enabled_channels
= 0x5;
2497 packf
= ac_build_cvt_pknorm_i16
;
2500 case V_028714_SPI_SHADER_UINT16_ABGR
:
2501 args
->enabled_channels
= 0x5;
2502 packi
= ac_build_cvt_pk_u16
;
2504 for (unsigned chan
= 0; chan
< 4; chan
++)
2505 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
2506 ac_to_integer(&ctx
->ac
, values
[chan
]),
2511 case V_028714_SPI_SHADER_SINT16_ABGR
:
2512 args
->enabled_channels
= 0x5;
2513 packi
= ac_build_cvt_pk_i16
;
2515 for (unsigned chan
= 0; chan
< 4; chan
++)
2516 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
2517 ac_to_integer(&ctx
->ac
, values
[chan
]),
2523 case V_028714_SPI_SHADER_32_ABGR
:
2524 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2528 /* Pack f16 or norm_i16/u16. */
2530 for (chan
= 0; chan
< 2; chan
++) {
2531 LLVMValueRef pack_args
[2] = {
2533 values
[2 * chan
+ 1]
2535 LLVMValueRef packed
;
2537 packed
= packf(&ctx
->ac
, pack_args
);
2538 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2540 args
->compr
= 1; /* COMPR flag */
2545 for (chan
= 0; chan
< 2; chan
++) {
2546 LLVMValueRef pack_args
[2] = {
2547 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2548 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2550 LLVMValueRef packed
;
2552 packed
= packi(&ctx
->ac
, pack_args
,
2553 is_int8
? 8 : is_int10
? 10 : 16,
2555 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2557 args
->compr
= 1; /* COMPR flag */
2563 for (unsigned chan
= 0; chan
< 4; chan
++) {
2564 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
2565 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
2568 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2570 for (unsigned i
= 0; i
< 4; ++i
)
2571 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2575 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2576 LLVMValueRef
*values
, unsigned enabled_channels
)
2578 struct ac_export_args args
;
2580 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2581 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2582 ac_build_export(&ctx
->ac
, &args
);
2586 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2588 LLVMValueRef output
=
2589 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2591 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2595 radv_emit_stream_output(struct radv_shader_context
*ctx
,
2596 LLVMValueRef
const *so_buffers
,
2597 LLVMValueRef
const *so_write_offsets
,
2598 const struct radv_stream_output
*output
)
2600 unsigned num_comps
= util_bitcount(output
->component_mask
);
2601 unsigned loc
= output
->location
;
2602 unsigned buf
= output
->buffer
;
2603 unsigned offset
= output
->offset
;
2605 LLVMValueRef out
[4];
2607 assert(num_comps
&& num_comps
<= 4);
2608 if (!num_comps
|| num_comps
> 4)
2611 /* Get the first component. */
2612 start
= ffs(output
->component_mask
) - 1;
2614 /* Load the output as int. */
2615 for (int i
= 0; i
< num_comps
; i
++) {
2616 out
[i
] = ac_to_integer(&ctx
->ac
,
2617 radv_load_output(ctx
, loc
, start
+ i
));
2620 /* Pack the output. */
2621 LLVMValueRef vdata
= NULL
;
2623 switch (num_comps
) {
2624 case 1: /* as i32 */
2627 case 2: /* as v2i32 */
2628 case 3: /* as v4i32 (aligned to 4) */
2629 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
2631 case 4: /* as v4i32 */
2632 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
2633 util_next_power_of_two(num_comps
));
2637 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
2638 vdata
, num_comps
, so_write_offsets
[buf
],
2639 ctx
->ac
.i32_0
, offset
,
2644 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
2646 struct ac_build_if_state if_ctx
;
2649 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2650 assert(ctx
->streamout_config
);
2651 LLVMValueRef so_vtx_count
=
2652 ac_build_bfe(&ctx
->ac
, ctx
->streamout_config
,
2653 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2654 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
2656 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2658 /* can_emit = tid < so_vtx_count; */
2659 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
2660 tid
, so_vtx_count
, "");
2662 /* Emit the streamout code conditionally. This actually avoids
2663 * out-of-bounds buffer access. The hw tells us via the SGPR
2664 * (so_vtx_count) which threads are allowed to emit streamout data.
2666 ac_nir_build_if(&if_ctx
, ctx
, can_emit
);
2668 /* The buffer offset is computed as follows:
2669 * ByteOffset = streamout_offset[buffer_id]*4 +
2670 * (streamout_write_index + thread_id)*stride[buffer_id] +
2673 LLVMValueRef so_write_index
= ctx
->streamout_write_idx
;
2675 /* Compute (streamout_write_index + thread_id). */
2677 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
2679 /* Load the descriptor and compute the write offset for each
2682 LLVMValueRef so_write_offset
[4] = {};
2683 LLVMValueRef so_buffers
[4] = {};
2684 LLVMValueRef buf_ptr
= ctx
->streamout_buffers
;
2686 for (i
= 0; i
< 4; i
++) {
2687 uint16_t stride
= ctx
->shader_info
->info
.so
.strides
[i
];
2692 LLVMValueRef offset
=
2693 LLVMConstInt(ctx
->ac
.i32
, i
, false);
2695 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
2698 LLVMValueRef so_offset
= ctx
->streamout_offset
[i
];
2700 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
2701 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2703 so_write_offset
[i
] =
2704 ac_build_imad(&ctx
->ac
, so_write_index
,
2705 LLVMConstInt(ctx
->ac
.i32
,
2710 /* Write streamout data. */
2711 for (i
= 0; i
< ctx
->shader_info
->info
.so
.num_outputs
; i
++) {
2712 struct radv_stream_output
*output
=
2713 &ctx
->shader_info
->info
.so
.outputs
[i
];
2715 if (stream
!= output
->stream
)
2718 radv_emit_stream_output(ctx
, so_buffers
,
2719 so_write_offset
, output
);
2722 ac_nir_build_endif(&if_ctx
);
2726 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2727 bool export_prim_id
, bool export_layer_id
,
2728 struct radv_vs_output_info
*outinfo
)
2730 uint32_t param_count
= 0;
2732 unsigned pos_idx
, num_pos_exports
= 0;
2733 struct ac_export_args args
, pos_args
[4] = {};
2734 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2737 if (ctx
->options
->key
.has_multiview_view_index
) {
2738 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2740 for(unsigned i
= 0; i
< 4; ++i
)
2741 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2742 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2745 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
2746 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2749 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2750 sizeof(outinfo
->vs_output_param_offset
));
2752 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
2753 unsigned output_usage_mask
, length
;
2754 LLVMValueRef slots
[8];
2757 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2758 !ctx
->is_gs_copy_shader
) {
2760 ctx
->shader_info
->info
.vs
.output_usage_mask
[VARYING_SLOT_CLIP_DIST0
];
2761 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2763 ctx
->shader_info
->info
.tes
.output_usage_mask
[VARYING_SLOT_CLIP_DIST0
];
2765 assert(ctx
->is_gs_copy_shader
);
2767 ctx
->shader_info
->info
.gs
.output_usage_mask
[VARYING_SLOT_CLIP_DIST0
];
2770 length
= util_last_bit(output_usage_mask
);
2772 i
= VARYING_SLOT_CLIP_DIST0
;
2773 for (j
= 0; j
< length
; j
++)
2774 slots
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2776 for (i
= length
; i
< 8; i
++)
2777 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
2780 target
= V_008DFC_SQ_EXP_POS
+ 3;
2781 si_llvm_init_export_args(ctx
, &slots
[4], 0xf, target
, &args
);
2782 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2783 &args
, sizeof(args
));
2786 target
= V_008DFC_SQ_EXP_POS
+ 2;
2787 si_llvm_init_export_args(ctx
, &slots
[0], 0xf, target
, &args
);
2788 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2789 &args
, sizeof(args
));
2791 /* Export the clip/cull distances values to the next stage. */
2792 radv_export_param(ctx
, param_count
, &slots
[0], 0xf);
2793 outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
] = param_count
++;
2795 radv_export_param(ctx
, param_count
, &slots
[4], 0xf);
2796 outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
] = param_count
++;
2800 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
2801 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
2802 for (unsigned j
= 0; j
< 4; j
++)
2803 pos_values
[j
] = radv_load_output(ctx
, VARYING_SLOT_POS
, j
);
2805 si_llvm_init_export_args(ctx
, pos_values
, 0xf, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2807 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
2808 outinfo
->writes_pointsize
= true;
2809 psize_value
= radv_load_output(ctx
, VARYING_SLOT_PSIZ
, 0);
2812 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
2813 outinfo
->writes_layer
= true;
2814 layer_value
= radv_load_output(ctx
, VARYING_SLOT_LAYER
, 0);
2817 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
2818 outinfo
->writes_viewport_index
= true;
2819 viewport_index_value
= radv_load_output(ctx
, VARYING_SLOT_VIEWPORT
, 0);
2822 if (ctx
->shader_info
->info
.so
.num_outputs
&&
2823 !ctx
->is_gs_copy_shader
) {
2824 /* The GS copy shader emission already emits streamout. */
2825 radv_emit_streamout(ctx
, 0);
2828 if (outinfo
->writes_pointsize
||
2829 outinfo
->writes_layer
||
2830 outinfo
->writes_viewport_index
) {
2831 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2832 (outinfo
->writes_layer
== true ? 4 : 0));
2833 pos_args
[1].valid_mask
= 0;
2834 pos_args
[1].done
= 0;
2835 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2836 pos_args
[1].compr
= 0;
2837 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2838 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2839 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2840 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2842 if (outinfo
->writes_pointsize
== true)
2843 pos_args
[1].out
[0] = psize_value
;
2844 if (outinfo
->writes_layer
== true)
2845 pos_args
[1].out
[2] = layer_value
;
2846 if (outinfo
->writes_viewport_index
== true) {
2847 if (ctx
->options
->chip_class
>= GFX9
) {
2848 /* GFX9 has the layer in out.z[10:0] and the viewport
2849 * index in out.z[19:16].
2851 LLVMValueRef v
= viewport_index_value
;
2852 v
= ac_to_integer(&ctx
->ac
, v
);
2853 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2854 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2856 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2857 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2859 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2860 pos_args
[1].enabled_channels
|= 1 << 2;
2862 pos_args
[1].out
[3] = viewport_index_value
;
2863 pos_args
[1].enabled_channels
|= 1 << 3;
2867 for (i
= 0; i
< 4; i
++) {
2868 if (pos_args
[i
].out
[0])
2873 for (i
= 0; i
< 4; i
++) {
2874 if (!pos_args
[i
].out
[0])
2877 /* Specify the target we are exporting */
2878 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2879 if (pos_idx
== num_pos_exports
)
2880 pos_args
[i
].done
= 1;
2881 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2884 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2885 LLVMValueRef values
[4];
2886 if (!(ctx
->output_mask
& (1ull << i
)))
2889 if (i
!= VARYING_SLOT_LAYER
&&
2890 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
2891 i
< VARYING_SLOT_VAR0
)
2894 for (unsigned j
= 0; j
< 4; j
++)
2895 values
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2897 unsigned output_usage_mask
;
2899 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2900 !ctx
->is_gs_copy_shader
) {
2902 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2903 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2905 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2907 assert(ctx
->is_gs_copy_shader
);
2909 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
2912 radv_export_param(ctx
, param_count
, values
, output_usage_mask
);
2914 outinfo
->vs_output_param_offset
[i
] = param_count
++;
2917 if (export_prim_id
) {
2918 LLVMValueRef values
[4];
2920 values
[0] = ctx
->vs_prim_id
;
2921 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
2922 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
2923 for (unsigned j
= 1; j
< 4; j
++)
2924 values
[j
] = ctx
->ac
.f32_0
;
2926 radv_export_param(ctx
, param_count
, values
, 0x1);
2928 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
2929 outinfo
->export_prim_id
= true;
2932 if (export_layer_id
&& layer_value
) {
2933 LLVMValueRef values
[4];
2935 values
[0] = layer_value
;
2936 for (unsigned j
= 1; j
< 4; j
++)
2937 values
[j
] = ctx
->ac
.f32_0
;
2939 radv_export_param(ctx
, param_count
, values
, 0x1);
2941 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
++;
2944 outinfo
->pos_exports
= num_pos_exports
;
2945 outinfo
->param_exports
= param_count
;
2949 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2950 struct radv_es_output_info
*outinfo
)
2953 uint64_t max_output_written
= 0;
2954 LLVMValueRef lds_base
= NULL
;
2956 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2957 unsigned output_usage_mask
;
2961 if (!(ctx
->output_mask
& (1ull << i
)))
2964 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2966 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2968 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2970 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2973 if (i
== VARYING_SLOT_CLIP_DIST0
)
2974 length
= util_last_bit(output_usage_mask
);
2976 param_index
= shader_io_get_unique_index(i
);
2978 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
2981 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
2983 if (ctx
->ac
.chip_class
>= GFX9
) {
2984 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2985 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2986 LLVMValueRef wave_idx
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
2987 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2988 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2989 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
2990 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2991 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2994 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2995 LLVMValueRef dw_addr
= NULL
;
2996 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2997 unsigned output_usage_mask
;
3001 if (!(ctx
->output_mask
& (1ull << i
)))
3004 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3006 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
3008 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3010 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
3013 if (i
== VARYING_SLOT_CLIP_DIST0
)
3014 length
= util_last_bit(output_usage_mask
);
3016 param_index
= shader_io_get_unique_index(i
);
3019 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3020 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
3024 for (j
= 0; j
< length
; j
++) {
3025 if (!(output_usage_mask
& (1 << j
)))
3028 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
3029 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3030 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3032 if (ctx
->ac
.chip_class
>= GFX9
) {
3033 LLVMValueRef dw_addr_offset
=
3034 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3035 LLVMConstInt(ctx
->ac
.i32
,
3038 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
3040 ac_build_buffer_store_dword(&ctx
->ac
,
3043 NULL
, ctx
->es2gs_offset
,
3044 (4 * param_index
+ j
) * 4,
3052 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
3054 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
3055 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->shader_info
->info
.vs
.ls_outputs_written
);
3056 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
3057 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
3058 vertex_dw_stride
, "");
3060 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3061 unsigned output_usage_mask
=
3062 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
3063 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
3066 if (!(ctx
->output_mask
& (1ull << i
)))
3069 if (i
== VARYING_SLOT_CLIP_DIST0
)
3070 length
= util_last_bit(output_usage_mask
);
3072 int param
= shader_io_get_unique_index(i
);
3073 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
3074 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
3076 for (unsigned j
= 0; j
< length
; j
++) {
3077 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
3078 value
= ac_to_integer(&ctx
->ac
, value
);
3079 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
3080 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
3081 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
3087 write_tess_factors(struct radv_shader_context
*ctx
)
3089 unsigned stride
, outer_comps
, inner_comps
;
3090 struct ac_build_if_state if_ctx
, inner_if_ctx
;
3091 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3092 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
3093 unsigned tess_inner_index
= 0, tess_outer_index
;
3094 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3095 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3097 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3099 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
3119 ac_nir_build_if(&if_ctx
, ctx
,
3120 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3121 invocation_id
, ctx
->ac
.i32_0
, ""));
3123 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3126 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3127 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3128 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3131 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3132 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3133 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3135 for (i
= 0; i
< 4; i
++) {
3136 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3137 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3141 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3142 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3143 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3145 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3147 for (i
= 0; i
< outer_comps
; i
++) {
3149 ac_lds_load(&ctx
->ac
, lds_outer
);
3150 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3153 for (i
= 0; i
< inner_comps
; i
++) {
3154 inner
[i
] = out
[outer_comps
+i
] =
3155 ac_lds_load(&ctx
->ac
, lds_inner
);
3156 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3161 /* Convert the outputs to vectors for stores. */
3162 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3166 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3169 buffer
= ctx
->hs_ring_tess_factor
;
3170 tf_base
= ctx
->tess_factor_offset
;
3171 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3172 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3173 unsigned tf_offset
= 0;
3175 if (ctx
->options
->chip_class
<= VI
) {
3176 ac_nir_build_if(&inner_if_ctx
, ctx
,
3177 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3178 rel_patch_id
, ctx
->ac
.i32_0
, ""));
3180 /* Store the dynamic HS control word. */
3181 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3182 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3183 1, ctx
->ac
.i32_0
, tf_base
,
3184 0, 1, 0, true, false);
3187 ac_nir_build_endif(&inner_if_ctx
);
3190 /* Store the tessellation factors. */
3191 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3192 MIN2(stride
, 4), byteoffset
, tf_base
,
3193 tf_offset
, 1, 0, true, false);
3195 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3196 stride
- 4, byteoffset
, tf_base
,
3197 16 + tf_offset
, 1, 0, true, false);
3199 //store to offchip for TES to read - only if TES reads them
3200 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
3201 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3202 LLVMValueRef tf_inner_offset
;
3203 unsigned param_outer
, param_inner
;
3205 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3206 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3207 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3209 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3210 util_next_power_of_two(outer_comps
));
3212 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3213 outer_comps
, tf_outer_offset
,
3214 ctx
->oc_lds
, 0, 1, 0, true, false);
3216 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3217 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3218 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3220 inner_vec
= inner_comps
== 1 ? inner
[0] :
3221 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3222 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3223 inner_comps
, tf_inner_offset
,
3224 ctx
->oc_lds
, 0, 1, 0, true, false);
3227 ac_nir_build_endif(&if_ctx
);
3231 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3233 write_tess_factors(ctx
);
3237 si_export_mrt_color(struct radv_shader_context
*ctx
,
3238 LLVMValueRef
*color
, unsigned index
,
3239 struct ac_export_args
*args
)
3242 si_llvm_init_export_args(ctx
, color
, 0xf,
3243 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3244 if (!args
->enabled_channels
)
3245 return false; /* unnecessary NULL export */
3251 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3252 LLVMValueRef depth
, LLVMValueRef stencil
,
3253 LLVMValueRef samplemask
)
3255 struct ac_export_args args
;
3257 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3259 ac_build_export(&ctx
->ac
, &args
);
3263 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3266 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3267 struct ac_export_args color_args
[8];
3269 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3270 LLVMValueRef values
[4];
3272 if (!(ctx
->output_mask
& (1ull << i
)))
3275 if (i
< FRAG_RESULT_DATA0
)
3278 for (unsigned j
= 0; j
< 4; j
++)
3279 values
[j
] = ac_to_float(&ctx
->ac
,
3280 radv_load_output(ctx
, i
, j
));
3282 bool ret
= si_export_mrt_color(ctx
, values
,
3283 i
- FRAG_RESULT_DATA0
,
3284 &color_args
[index
]);
3289 /* Process depth, stencil, samplemask. */
3290 if (ctx
->shader_info
->info
.ps
.writes_z
) {
3291 depth
= ac_to_float(&ctx
->ac
,
3292 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3294 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
3295 stencil
= ac_to_float(&ctx
->ac
,
3296 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
3298 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3299 samplemask
= ac_to_float(&ctx
->ac
,
3300 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
3303 /* Set the DONE bit on last non-null color export only if Z isn't
3307 !ctx
->shader_info
->info
.ps
.writes_z
&&
3308 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
3309 !ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3310 unsigned last
= index
- 1;
3312 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
3313 color_args
[last
].done
= 1; /* DONE bit */
3316 /* Export PS outputs. */
3317 for (unsigned i
= 0; i
< index
; i
++)
3318 ac_build_export(&ctx
->ac
, &color_args
[i
]);
3320 if (depth
|| stencil
|| samplemask
)
3321 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
3323 ac_build_export_null(&ctx
->ac
);
3327 emit_gs_epilogue(struct radv_shader_context
*ctx
)
3329 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
3333 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
3334 LLVMValueRef
*addrs
)
3336 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3338 switch (ctx
->stage
) {
3339 case MESA_SHADER_VERTEX
:
3340 if (ctx
->options
->key
.vs
.as_ls
)
3341 handle_ls_outputs_post(ctx
);
3342 else if (ctx
->options
->key
.vs
.as_es
)
3343 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
3345 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
3346 ctx
->options
->key
.vs
.export_layer_id
,
3347 &ctx
->shader_info
->vs
.outinfo
);
3349 case MESA_SHADER_FRAGMENT
:
3350 handle_fs_outputs_post(ctx
);
3352 case MESA_SHADER_GEOMETRY
:
3353 emit_gs_epilogue(ctx
);
3355 case MESA_SHADER_TESS_CTRL
:
3356 handle_tcs_outputs_post(ctx
);
3358 case MESA_SHADER_TESS_EVAL
:
3359 if (ctx
->options
->key
.tes
.as_es
)
3360 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
3362 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
3363 ctx
->options
->key
.tes
.export_layer_id
,
3364 &ctx
->shader_info
->tes
.outinfo
);
3371 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
3372 LLVMPassManagerRef passmgr
,
3373 const struct radv_nir_compiler_options
*options
)
3375 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
3376 LLVMDisposeBuilder(ctx
->ac
.builder
);
3378 ac_llvm_context_dispose(&ctx
->ac
);
3382 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
3384 struct radv_vs_output_info
*outinfo
;
3386 switch (ctx
->stage
) {
3387 case MESA_SHADER_FRAGMENT
:
3388 case MESA_SHADER_COMPUTE
:
3389 case MESA_SHADER_TESS_CTRL
:
3390 case MESA_SHADER_GEOMETRY
:
3392 case MESA_SHADER_VERTEX
:
3393 if (ctx
->options
->key
.vs
.as_ls
||
3394 ctx
->options
->key
.vs
.as_es
)
3396 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
3398 case MESA_SHADER_TESS_EVAL
:
3399 if (ctx
->options
->key
.vs
.as_es
)
3401 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
3404 unreachable("Unhandled shader type");
3407 ac_optimize_vs_outputs(&ctx
->ac
,
3409 outinfo
->vs_output_param_offset
,
3411 &outinfo
->param_exports
);
3415 ac_setup_rings(struct radv_shader_context
*ctx
)
3417 if (ctx
->options
->chip_class
<= VI
&&
3418 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
3419 ctx
->options
->key
.vs
.as_es
|| ctx
->options
->key
.tes
.as_es
)) {
3420 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
3422 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
3424 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
3429 if (ctx
->is_gs_copy_shader
) {
3431 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3432 LLVMConstInt(ctx
->ac
.i32
,
3433 RING_GSVS_VS
, false));
3436 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3437 /* The conceptual layout of the GSVS ring is
3438 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3439 * but the real memory layout is swizzled across
3441 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3443 * Override the buffer descriptor accordingly.
3445 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
3446 uint64_t stream_offset
= 0;
3447 unsigned num_records
= 64;
3448 LLVMValueRef base_ring
;
3451 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3452 LLVMConstInt(ctx
->ac
.i32
,
3453 RING_GSVS_GS
, false));
3455 for (unsigned stream
= 0; stream
< 4; stream
++) {
3456 unsigned num_components
, stride
;
3457 LLVMValueRef ring
, tmp
;
3460 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
3462 if (!num_components
)
3465 stride
= 4 * num_components
* ctx
->gs_max_out_vertices
;
3467 /* Limit on the stride field for <= CIK. */
3468 assert(stride
< (1 << 14));
3470 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
3471 base_ring
, v2i64
, "");
3472 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3473 ring
, ctx
->ac
.i32_0
, "");
3474 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
3475 LLVMConstInt(ctx
->ac
.i64
,
3476 stream_offset
, 0), "");
3477 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
3478 ring
, tmp
, ctx
->ac
.i32_0
, "");
3480 stream_offset
+= stride
* 64;
3482 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
3485 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
3487 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
3488 LLVMConstInt(ctx
->ac
.i32
,
3489 S_008F04_STRIDE(stride
), false), "");
3490 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
3493 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
3494 LLVMConstInt(ctx
->ac
.i32
,
3495 num_records
, false),
3496 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3498 ctx
->gsvs_ring
[stream
] = ring
;
3502 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3503 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3504 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
3505 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
3510 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
3511 const struct nir_shader
*nir
)
3513 switch (nir
->info
.stage
) {
3514 case MESA_SHADER_TESS_CTRL
:
3515 return chip_class
>= CIK
? 128 : 64;
3516 case MESA_SHADER_GEOMETRY
:
3517 return chip_class
>= GFX9
? 128 : 64;
3518 case MESA_SHADER_COMPUTE
:
3524 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
3525 nir
->info
.cs
.local_size
[1] *
3526 nir
->info
.cs
.local_size
[2];
3527 return max_workgroup_size
;
3530 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3531 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
3533 LLVMValueRef count
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
3534 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
3536 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
3537 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
3538 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
3541 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
3543 for(int i
= 5; i
>= 0; --i
) {
3544 ctx
->gs_vtx_offset
[i
] = ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
3548 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 16, 8);
3553 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
3554 struct nir_shader
*const *shaders
,
3556 struct radv_shader_variant_info
*shader_info
,
3557 const struct radv_nir_compiler_options
*options
)
3559 struct radv_shader_context ctx
= {0};
3561 ctx
.options
= options
;
3562 ctx
.shader_info
= shader_info
;
3564 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
3565 ctx
.context
= ctx
.ac
.context
;
3566 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
3568 enum ac_float_mode float_mode
=
3569 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
3570 AC_FLOAT_MODE_DEFAULT
;
3572 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
3574 memset(shader_info
, 0, sizeof(*shader_info
));
3576 radv_nir_shader_info_init(&shader_info
->info
);
3578 for(int i
= 0; i
< shader_count
; ++i
)
3579 radv_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
3581 for (i
= 0; i
< RADV_UD_MAX_SETS
; i
++)
3582 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
3583 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
3584 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
3586 ctx
.max_workgroup_size
= 0;
3587 for (int i
= 0; i
< shader_count
; ++i
) {
3588 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
3589 radv_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
3593 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
3594 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
3596 ctx
.abi
.inputs
= &ctx
.inputs
[0];
3597 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
3598 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
3599 ctx
.abi
.load_ubo
= radv_load_ubo
;
3600 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
3601 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
3602 ctx
.abi
.load_resource
= radv_load_resource
;
3603 ctx
.abi
.clamp_shadow_reference
= false;
3604 ctx
.abi
.gfx9_stride_size_workaround
= ctx
.ac
.chip_class
== GFX9
&& HAVE_LLVM
< 0x800;
3606 if (shader_count
>= 2)
3607 ac_init_exec_full_mask(&ctx
.ac
);
3609 if (ctx
.ac
.chip_class
== GFX9
&&
3610 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
3611 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
3613 for(int i
= 0; i
< shader_count
; ++i
) {
3614 ctx
.stage
= shaders
[i
]->info
.stage
;
3615 ctx
.output_mask
= 0;
3617 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3618 for (int i
= 0; i
< 4; i
++) {
3619 ctx
.gs_next_vertex
[i
] =
3620 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
3622 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
3623 ctx
.abi
.load_inputs
= load_gs_input
;
3624 ctx
.abi
.emit_primitive
= visit_end_primitive
;
3625 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3626 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
3627 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
3628 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
3629 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3630 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
3631 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3632 if (shader_count
== 1)
3633 ctx
.tcs_num_inputs
= ctx
.options
->key
.tcs
.num_inputs
;
3635 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->info
.vs
.ls_outputs_written
);
3636 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
3637 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
3638 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
3639 ctx
.abi
.load_tess_varyings
= load_tes_input
;
3640 ctx
.abi
.load_tess_coord
= load_tess_coord
;
3641 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3642 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3643 ctx
.tcs_num_patches
= ctx
.options
->key
.tes
.num_patches
;
3644 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
3645 if (shader_info
->info
.vs
.needs_instance_id
) {
3646 if (ctx
.options
->key
.vs
.as_ls
) {
3647 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
3648 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
3650 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
3651 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
3654 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
3655 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
3656 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
3657 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
3658 ctx
.abi
.load_sample_position
= load_sample_position
;
3659 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
3660 ctx
.abi
.emit_kill
= radv_emit_kill
;
3664 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
3666 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
3667 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
3669 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3670 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
3671 shaders
[i
]->info
.cull_distance_array_size
> 4;
3672 ctx
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
3673 ctx
.max_gsvs_emit_size
= ctx
.gsvs_vertex_size
*
3674 shaders
[i
]->info
.gs
.vertices_out
;
3677 ac_setup_rings(&ctx
);
3679 LLVMBasicBlockRef merge_block
;
3680 if (shader_count
>= 2) {
3681 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
3682 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3683 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3685 LLVMValueRef count
= ac_unpack_param(&ctx
.ac
, ctx
.merged_wave_info
, 8 * i
, 8);
3686 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
3687 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
3688 thread_id
, count
, "");
3689 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
3691 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
3694 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
3695 handle_fs_inputs(&ctx
, shaders
[i
]);
3696 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
3697 handle_vs_inputs(&ctx
, shaders
[i
]);
3698 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
3699 prepare_gs_input_vgprs(&ctx
);
3701 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
3703 if (shader_count
>= 2) {
3704 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
3705 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
3708 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3709 shader_info
->gs
.gsvs_vertex_size
= ctx
.gsvs_vertex_size
;
3710 shader_info
->gs
.max_gsvs_emit_size
= ctx
.max_gsvs_emit_size
;
3711 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3712 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
3713 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
3717 LLVMBuildRetVoid(ctx
.ac
.builder
);
3719 if (options
->dump_preoptir
)
3720 ac_dump_module(ctx
.ac
.module
);
3722 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
3724 if (shader_count
== 1)
3725 ac_nir_eliminate_const_vs_outputs(&ctx
);
3727 if (options
->dump_shader
) {
3728 ctx
.shader_info
->private_mem_vgprs
=
3729 ac_count_scratch_private_memory(ctx
.main_function
);
3732 return ctx
.ac
.module
;
3735 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
3737 unsigned *retval
= (unsigned *)context
;
3738 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
3739 char *description
= LLVMGetDiagInfoDescription(di
);
3741 if (severity
== LLVMDSError
) {
3743 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
3747 LLVMDisposeMessage(description
);
3750 static unsigned ac_llvm_compile(LLVMModuleRef M
,
3751 struct ac_shader_binary
*binary
,
3752 struct ac_llvm_compiler
*ac_llvm
)
3754 unsigned retval
= 0;
3755 LLVMContextRef llvm_ctx
;
3757 /* Setup Diagnostic Handler*/
3758 llvm_ctx
= LLVMGetModuleContext(M
);
3760 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
3764 if (!radv_compile_to_binary(ac_llvm
, M
, binary
))
3769 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
3770 LLVMModuleRef llvm_module
,
3771 struct ac_shader_binary
*binary
,
3772 struct ac_shader_config
*config
,
3773 struct radv_shader_variant_info
*shader_info
,
3774 gl_shader_stage stage
,
3775 const struct radv_nir_compiler_options
*options
)
3777 if (options
->dump_shader
)
3778 ac_dump_module(llvm_module
);
3780 memset(binary
, 0, sizeof(*binary
));
3782 if (options
->record_llvm_ir
) {
3783 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
3784 binary
->llvm_ir_string
= strdup(llvm_ir
);
3785 LLVMDisposeMessage(llvm_ir
);
3788 int v
= ac_llvm_compile(llvm_module
, binary
, ac_llvm
);
3790 fprintf(stderr
, "compile failed\n");
3793 if (options
->dump_shader
)
3794 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
3796 ac_shader_binary_read_config(binary
, config
, 0, options
->supports_spill
);
3798 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
3799 LLVMDisposeModule(llvm_module
);
3800 LLVMContextDispose(ctx
);
3802 if (stage
== MESA_SHADER_FRAGMENT
) {
3803 shader_info
->num_input_vgprs
= 0;
3804 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
3805 shader_info
->num_input_vgprs
+= 2;
3806 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
3807 shader_info
->num_input_vgprs
+= 2;
3808 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
3809 shader_info
->num_input_vgprs
+= 2;
3810 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
3811 shader_info
->num_input_vgprs
+= 3;
3812 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
3813 shader_info
->num_input_vgprs
+= 2;
3814 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
3815 shader_info
->num_input_vgprs
+= 2;
3816 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
3817 shader_info
->num_input_vgprs
+= 2;
3818 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
3819 shader_info
->num_input_vgprs
+= 1;
3820 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
3821 shader_info
->num_input_vgprs
+= 1;
3822 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
3823 shader_info
->num_input_vgprs
+= 1;
3824 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
3825 shader_info
->num_input_vgprs
+= 1;
3826 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
3827 shader_info
->num_input_vgprs
+= 1;
3828 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
3829 shader_info
->num_input_vgprs
+= 1;
3830 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
3831 shader_info
->num_input_vgprs
+= 1;
3832 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
3833 shader_info
->num_input_vgprs
+= 1;
3834 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
3835 shader_info
->num_input_vgprs
+= 1;
3837 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
3839 /* +3 for scratch wave offset and VCC */
3840 config
->num_sgprs
= MAX2(config
->num_sgprs
,
3841 shader_info
->num_input_sgprs
+ 3);
3843 /* Enable 64-bit and 16-bit denormals, because there is no performance
3846 * If denormals are enabled, all floating-point output modifiers are
3849 * Don't enable denormals for 32-bit floats, because:
3850 * - Floating-point output modifiers would be ignored by the hw.
3851 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3852 * have to stop using those.
3853 * - SI & CI would be very slow.
3855 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
3859 ac_fill_shader_info(struct radv_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct radv_nir_compiler_options
*options
)
3861 switch (nir
->info
.stage
) {
3862 case MESA_SHADER_COMPUTE
:
3863 for (int i
= 0; i
< 3; ++i
)
3864 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
3866 case MESA_SHADER_FRAGMENT
:
3867 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
3869 case MESA_SHADER_GEOMETRY
:
3870 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
3871 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
3872 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
3873 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
3875 case MESA_SHADER_TESS_EVAL
:
3876 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
3877 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
3878 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
3879 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
3880 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
3882 case MESA_SHADER_TESS_CTRL
:
3883 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
3885 case MESA_SHADER_VERTEX
:
3886 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
3887 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
3888 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3889 if (options
->key
.vs
.as_ls
)
3890 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
3898 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
3899 struct ac_shader_binary
*binary
,
3900 struct ac_shader_config
*config
,
3901 struct radv_shader_variant_info
*shader_info
,
3902 struct nir_shader
*const *nir
,
3904 const struct radv_nir_compiler_options
*options
)
3907 LLVMModuleRef llvm_module
;
3909 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, shader_info
,
3912 ac_compile_llvm_module(ac_llvm
, llvm_module
, binary
, config
, shader_info
,
3913 nir
[0]->info
.stage
, options
);
3915 for (int i
= 0; i
< nir_count
; ++i
)
3916 ac_fill_shader_info(shader_info
, nir
[i
], options
);
3918 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3919 if (options
->chip_class
== GFX9
) {
3920 if (nir_count
== 2 &&
3921 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3922 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
3928 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
3930 LLVMValueRef vtx_offset
=
3931 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
3932 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3933 LLVMValueRef stream_id
;
3935 /* Fetch the vertex stream ID. */
3936 if (ctx
->shader_info
->info
.so
.num_outputs
) {
3938 ac_unpack_param(&ctx
->ac
, ctx
->streamout_config
, 24, 2);
3940 stream_id
= ctx
->ac
.i32_0
;
3943 LLVMBasicBlockRef end_bb
;
3944 LLVMValueRef switch_inst
;
3946 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
3947 ctx
->main_function
, "end");
3948 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
3950 for (unsigned stream
= 0; stream
< 4; stream
++) {
3951 unsigned num_components
=
3952 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
3953 LLVMBasicBlockRef bb
;
3956 if (!num_components
)
3959 if (stream
> 0 && !ctx
->shader_info
->info
.so
.num_outputs
)
3962 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
3963 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
3964 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
3967 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3968 unsigned output_usage_mask
=
3969 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
3970 unsigned output_stream
=
3971 ctx
->shader_info
->info
.gs
.output_streams
[i
];
3972 int length
= util_last_bit(output_usage_mask
);
3974 if (!(ctx
->output_mask
& (1ull << i
)) ||
3975 output_stream
!= stream
)
3978 for (unsigned j
= 0; j
< length
; j
++) {
3979 LLVMValueRef value
, soffset
;
3981 if (!(output_usage_mask
& (1 << j
)))
3984 soffset
= LLVMConstInt(ctx
->ac
.i32
,
3986 ctx
->gs_max_out_vertices
* 16 * 4, false);
3990 value
= ac_build_buffer_load(&ctx
->ac
,
3993 vtx_offset
, soffset
,
3994 0, 1, 1, true, false);
3996 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3997 if (ac_get_type_size(type
) == 2) {
3998 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
3999 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
4002 LLVMBuildStore(ctx
->ac
.builder
,
4003 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4007 if (ctx
->shader_info
->info
.so
.num_outputs
)
4008 radv_emit_streamout(ctx
, stream
);
4011 handle_vs_outputs_post(ctx
, false, false,
4012 &ctx
->shader_info
->vs
.outinfo
);
4015 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
4018 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
4022 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
4023 struct nir_shader
*geom_shader
,
4024 struct ac_shader_binary
*binary
,
4025 struct ac_shader_config
*config
,
4026 struct radv_shader_variant_info
*shader_info
,
4027 const struct radv_nir_compiler_options
*options
)
4029 struct radv_shader_context ctx
= {0};
4030 ctx
.options
= options
;
4031 ctx
.shader_info
= shader_info
;
4033 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
4034 ctx
.context
= ctx
.ac
.context
;
4035 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
4037 ctx
.is_gs_copy_shader
= true;
4039 enum ac_float_mode float_mode
=
4040 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
4041 AC_FLOAT_MODE_DEFAULT
;
4043 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
4044 ctx
.stage
= MESA_SHADER_VERTEX
;
4046 radv_nir_shader_info_pass(geom_shader
, options
, &shader_info
->info
);
4048 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
4050 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
4051 ac_setup_rings(&ctx
);
4053 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
4054 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
4055 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
4056 variable
, MESA_SHADER_VERTEX
);
4059 ac_gs_copy_shader_emit(&ctx
);
4061 LLVMBuildRetVoid(ctx
.ac
.builder
);
4063 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
4065 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, binary
, config
, shader_info
,
4066 MESA_SHADER_VERTEX
, options
);