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radv/gfx10: adjust the GS NGG scratch size for streamout
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "nir/nir.h"
32
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
37
38 #include "sid.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_llvm_build.h"
42 #include "ac_shader_abi.h"
43 #include "ac_shader_util.h"
44 #include "ac_exp_param.h"
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct radv_shader_context {
49 struct ac_llvm_context ac;
50 const struct radv_nir_compiler_options *options;
51 struct radv_shader_info *shader_info;
52 const struct nir_shader *shader;
53 struct ac_shader_abi abi;
54
55 unsigned max_workgroup_size;
56 LLVMContextRef context;
57 LLVMValueRef main_function;
58
59 LLVMValueRef descriptor_sets[MAX_SETS];
60 LLVMValueRef ring_offsets;
61
62 LLVMValueRef vertex_buffers;
63 LLVMValueRef rel_auto_id;
64 LLVMValueRef vs_prim_id;
65 LLVMValueRef es2gs_offset;
66
67 LLVMValueRef oc_lds;
68 LLVMValueRef merged_wave_info;
69 LLVMValueRef tess_factor_offset;
70 LLVMValueRef tes_rel_patch_id;
71 LLVMValueRef tes_u;
72 LLVMValueRef tes_v;
73
74 /* HW GS */
75 /* On gfx10:
76 * - bits 0..10: ordered_wave_id
77 * - bits 12..20: number of vertices in group
78 * - bits 22..30: number of primitives in group
79 */
80 LLVMValueRef gs_tg_info;
81 LLVMValueRef gs2vs_offset;
82 LLVMValueRef gs_wave_id;
83 LLVMValueRef gs_vtx_offset[6];
84
85 LLVMValueRef esgs_ring;
86 LLVMValueRef gsvs_ring[4];
87 LLVMValueRef hs_ring_tess_offchip;
88 LLVMValueRef hs_ring_tess_factor;
89
90 /* Streamout */
91 LLVMValueRef streamout_buffers;
92 LLVMValueRef streamout_write_idx;
93 LLVMValueRef streamout_config;
94 LLVMValueRef streamout_offset[4];
95
96 gl_shader_stage stage;
97
98 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
99
100 uint64_t output_mask;
101
102 bool is_gs_copy_shader;
103 LLVMValueRef gs_next_vertex[4];
104 LLVMValueRef gs_curprim_verts[4];
105 LLVMValueRef gs_generated_prims[4];
106 LLVMValueRef gs_ngg_emit;
107 LLVMValueRef gs_ngg_scratch;
108
109 uint32_t tcs_num_inputs;
110 uint32_t tcs_num_patches;
111
112 LLVMValueRef vertexptr; /* GFX10 only */
113 };
114
115 struct radv_shader_output_values {
116 LLVMValueRef values[4];
117 unsigned slot_name;
118 unsigned slot_index;
119 unsigned usage_mask;
120 };
121
122 enum radeon_llvm_calling_convention {
123 RADEON_LLVM_AMDGPU_VS = 87,
124 RADEON_LLVM_AMDGPU_GS = 88,
125 RADEON_LLVM_AMDGPU_PS = 89,
126 RADEON_LLVM_AMDGPU_CS = 90,
127 RADEON_LLVM_AMDGPU_HS = 93,
128 };
129
130 static inline struct radv_shader_context *
131 radv_shader_context_from_abi(struct ac_shader_abi *abi)
132 {
133 struct radv_shader_context *ctx = NULL;
134 return container_of(abi, ctx, abi);
135 }
136
137 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
138 {
139 switch (ctx->stage) {
140 case MESA_SHADER_TESS_CTRL:
141 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
142 case MESA_SHADER_TESS_EVAL:
143 return ctx->tes_rel_patch_id;
144 break;
145 default:
146 unreachable("Illegal stage");
147 }
148 }
149
150 static unsigned
151 get_tcs_num_patches(struct radv_shader_context *ctx)
152 {
153 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
154 unsigned num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
155 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
156 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
157 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
158 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->tcs.patch_outputs_written);
159 uint32_t output_vertex_size = num_tcs_outputs * 16;
160 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
161 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
162 unsigned num_patches;
163 unsigned hardware_lds_size;
164
165 /* Ensure that we only need one wave per SIMD so we don't need to check
166 * resource usage. Also ensures that the number of tcs in and out
167 * vertices per threadgroup are at most 256.
168 */
169 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
170 /* Make sure that the data fits in LDS. This assumes the shaders only
171 * use LDS for the inputs and outputs.
172 */
173 hardware_lds_size = 32768;
174
175 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
176 * threadgroup, even though there is more than 32 KiB LDS.
177 *
178 * Test: dEQP-VK.tessellation.shader_input_output.barrier
179 */
180 if (ctx->options->chip_class >= GFX7 && ctx->options->family != CHIP_STONEY)
181 hardware_lds_size = 65536;
182
183 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
184 /* Make sure the output data fits in the offchip buffer */
185 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
186 /* Not necessary for correctness, but improves performance. The
187 * specific value is taken from the proprietary driver.
188 */
189 num_patches = MIN2(num_patches, 40);
190
191 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
192 if (ctx->options->chip_class == GFX6) {
193 unsigned one_wave = ctx->options->wave_size / MAX2(num_tcs_input_cp, num_tcs_output_cp);
194 num_patches = MIN2(num_patches, one_wave);
195 }
196 return num_patches;
197 }
198
199 static unsigned
200 calculate_tess_lds_size(struct radv_shader_context *ctx)
201 {
202 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
203 unsigned num_tcs_output_cp;
204 unsigned num_tcs_outputs, num_tcs_patch_outputs;
205 unsigned input_vertex_size, output_vertex_size;
206 unsigned input_patch_size, output_patch_size;
207 unsigned pervertex_output_patch_size;
208 unsigned output_patch0_offset;
209 unsigned num_patches;
210 unsigned lds_size;
211
212 num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
213 num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
214 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->tcs.patch_outputs_written);
215
216 input_vertex_size = ctx->tcs_num_inputs * 16;
217 output_vertex_size = num_tcs_outputs * 16;
218
219 input_patch_size = num_tcs_input_cp * input_vertex_size;
220
221 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
222 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
223
224 num_patches = ctx->tcs_num_patches;
225 output_patch0_offset = input_patch_size * num_patches;
226
227 lds_size = output_patch0_offset + output_patch_size * num_patches;
228 return lds_size;
229 }
230
231 /* Tessellation shaders pass outputs to the next shader using LDS.
232 *
233 * LS outputs = TCS inputs
234 * TCS outputs = TES inputs
235 *
236 * The LDS layout is:
237 * - TCS inputs for patch 0
238 * - TCS inputs for patch 1
239 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
240 * - ...
241 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
242 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
243 * - TCS outputs for patch 1
244 * - Per-patch TCS outputs for patch 1
245 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
246 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
247 * - ...
248 *
249 * All three shaders VS(LS), TCS, TES share the same LDS space.
250 */
251 static LLVMValueRef
252 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
253 {
254 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
255 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
256 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
257
258 input_patch_size /= 4;
259 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
260 }
261
262 static LLVMValueRef
263 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
264 {
265 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
266 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->tcs.patch_outputs_written);
267 uint32_t output_vertex_size = num_tcs_outputs * 16;
268 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
269 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
270 output_patch_size /= 4;
271 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
272 }
273
274 static LLVMValueRef
275 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
276 {
277 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
278 uint32_t output_vertex_size = num_tcs_outputs * 16;
279 output_vertex_size /= 4;
280 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
281 }
282
283 static LLVMValueRef
284 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
285 {
286 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
287 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
288 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
289 uint32_t output_patch0_offset = input_patch_size;
290 unsigned num_patches = ctx->tcs_num_patches;
291
292 output_patch0_offset *= num_patches;
293 output_patch0_offset /= 4;
294 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
295 }
296
297 static LLVMValueRef
298 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
299 {
300 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
301 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
302 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
303 uint32_t output_patch0_offset = input_patch_size;
304
305 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
306 uint32_t output_vertex_size = num_tcs_outputs * 16;
307 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
308 unsigned num_patches = ctx->tcs_num_patches;
309
310 output_patch0_offset *= num_patches;
311 output_patch0_offset += pervertex_output_patch_size;
312 output_patch0_offset /= 4;
313 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
314 }
315
316 static LLVMValueRef
317 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
318 {
319 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
320 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
321
322 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
323 }
324
325 static LLVMValueRef
326 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
327 {
328 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
329 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
330 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
331
332 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
333 patch0_offset);
334 }
335
336 static LLVMValueRef
337 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
338 {
339 LLVMValueRef patch0_patch_data_offset =
340 get_tcs_out_patch0_patch_data_offset(ctx);
341 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
342 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
343
344 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
345 patch0_patch_data_offset);
346 }
347
348 #define MAX_ARGS 64
349 struct arg_info {
350 LLVMTypeRef types[MAX_ARGS];
351 LLVMValueRef *assign[MAX_ARGS];
352 uint8_t count;
353 uint8_t sgpr_count;
354 uint8_t num_sgprs_used;
355 uint8_t num_vgprs_used;
356 };
357
358 enum ac_arg_regfile {
359 ARG_SGPR,
360 ARG_VGPR,
361 };
362
363 static void
364 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
365 LLVMValueRef *param_ptr)
366 {
367 assert(info->count < MAX_ARGS);
368
369 info->assign[info->count] = param_ptr;
370 info->types[info->count] = type;
371 info->count++;
372
373 if (regfile == ARG_SGPR) {
374 info->num_sgprs_used += ac_get_type_size(type) / 4;
375 info->sgpr_count++;
376 } else {
377 assert(regfile == ARG_VGPR);
378 info->num_vgprs_used += ac_get_type_size(type) / 4;
379 }
380 }
381
382 static void assign_arguments(LLVMValueRef main_function,
383 struct arg_info *info)
384 {
385 unsigned i;
386 for (i = 0; i < info->count; i++) {
387 if (info->assign[i])
388 *info->assign[i] = LLVMGetParam(main_function, i);
389 }
390 }
391
392 static LLVMValueRef
393 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
394 LLVMBuilderRef builder, LLVMTypeRef *return_types,
395 unsigned num_return_elems,
396 struct arg_info *args,
397 unsigned max_workgroup_size,
398 const struct radv_nir_compiler_options *options)
399 {
400 LLVMTypeRef main_function_type, ret_type;
401 LLVMBasicBlockRef main_function_body;
402
403 if (num_return_elems)
404 ret_type = LLVMStructTypeInContext(ctx, return_types,
405 num_return_elems, true);
406 else
407 ret_type = LLVMVoidTypeInContext(ctx);
408
409 /* Setup the function */
410 main_function_type =
411 LLVMFunctionType(ret_type, args->types, args->count, 0);
412 LLVMValueRef main_function =
413 LLVMAddFunction(module, "main", main_function_type);
414 main_function_body =
415 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
416 LLVMPositionBuilderAtEnd(builder, main_function_body);
417
418 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
419 for (unsigned i = 0; i < args->sgpr_count; ++i) {
420 LLVMValueRef P = LLVMGetParam(main_function, i);
421
422 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
423
424 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
425 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
426 ac_add_attr_dereferenceable(P, UINT64_MAX);
427 }
428 }
429
430 if (options->address32_hi) {
431 ac_llvm_add_target_dep_function_attr(main_function,
432 "amdgpu-32bit-address-high-bits",
433 options->address32_hi);
434 }
435
436 ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
437
438 if (options->unsafe_math) {
439 /* These were copied from some LLVM test. */
440 LLVMAddTargetDependentFunctionAttr(main_function,
441 "less-precise-fpmad",
442 "true");
443 LLVMAddTargetDependentFunctionAttr(main_function,
444 "no-infs-fp-math",
445 "true");
446 LLVMAddTargetDependentFunctionAttr(main_function,
447 "no-nans-fp-math",
448 "true");
449 LLVMAddTargetDependentFunctionAttr(main_function,
450 "unsafe-fp-math",
451 "true");
452 LLVMAddTargetDependentFunctionAttr(main_function,
453 "no-signed-zeros-fp-math",
454 "true");
455 }
456 return main_function;
457 }
458
459
460 static void
461 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx,
462 uint8_t num_sgprs)
463 {
464 ud_info->sgpr_idx = *sgpr_idx;
465 ud_info->num_sgprs = num_sgprs;
466 *sgpr_idx += num_sgprs;
467 }
468
469 static void
470 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
471 uint8_t num_sgprs)
472 {
473 struct radv_userdata_info *ud_info =
474 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
475 assert(ud_info);
476
477 set_loc(ud_info, sgpr_idx, num_sgprs);
478 }
479
480 static void
481 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
482 {
483 bool use_32bit_pointers = idx != AC_UD_SCRATCH_RING_OFFSETS;
484
485 set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
486 }
487
488 static void
489 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
490 {
491 struct radv_userdata_locations *locs =
492 &ctx->shader_info->user_sgprs_locs;
493 struct radv_userdata_info *ud_info = &locs->descriptor_sets[idx];
494 assert(ud_info);
495
496 set_loc(ud_info, sgpr_idx, 1);
497
498 locs->descriptor_sets_enabled |= 1 << idx;
499 }
500
501 struct user_sgpr_info {
502 bool need_ring_offsets;
503 bool indirect_all_descriptor_sets;
504 uint8_t remaining_sgprs;
505 };
506
507 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
508 gl_shader_stage stage)
509 {
510 switch (stage) {
511 case MESA_SHADER_VERTEX:
512 if (ctx->shader_info->needs_multiview_view_index ||
513 (!ctx->options->key.vs_common_out.as_es && !ctx->options->key.vs_common_out.as_ls && ctx->options->key.has_multiview_view_index))
514 return true;
515 break;
516 case MESA_SHADER_TESS_EVAL:
517 if (ctx->shader_info->needs_multiview_view_index || (!ctx->options->key.vs_common_out.as_es && ctx->options->key.has_multiview_view_index))
518 return true;
519 break;
520 case MESA_SHADER_GEOMETRY:
521 case MESA_SHADER_TESS_CTRL:
522 if (ctx->shader_info->needs_multiview_view_index)
523 return true;
524 break;
525 default:
526 break;
527 }
528 return false;
529 }
530
531 static uint8_t
532 count_vs_user_sgprs(struct radv_shader_context *ctx)
533 {
534 uint8_t count = 0;
535
536 if (ctx->shader_info->vs.has_vertex_buffers)
537 count++;
538 count += ctx->shader_info->vs.needs_draw_id ? 3 : 2;
539
540 return count;
541 }
542
543 static void allocate_inline_push_consts(struct radv_shader_context *ctx,
544 struct user_sgpr_info *user_sgpr_info)
545 {
546 uint8_t remaining_sgprs = user_sgpr_info->remaining_sgprs;
547
548 /* Only supported if shaders use push constants. */
549 if (ctx->shader_info->min_push_constant_used == UINT8_MAX)
550 return;
551
552 /* Only supported if shaders don't have indirect push constants. */
553 if (ctx->shader_info->has_indirect_push_constants)
554 return;
555
556 /* Only supported for 32-bit push constants. */
557 if (!ctx->shader_info->has_only_32bit_push_constants)
558 return;
559
560 uint8_t num_push_consts =
561 (ctx->shader_info->max_push_constant_used -
562 ctx->shader_info->min_push_constant_used) / 4;
563
564 /* Check if the number of user SGPRs is large enough. */
565 if (num_push_consts < remaining_sgprs) {
566 ctx->shader_info->num_inline_push_consts = num_push_consts;
567 } else {
568 ctx->shader_info->num_inline_push_consts = remaining_sgprs;
569 }
570
571 /* Clamp to the maximum number of allowed inlined push constants. */
572 if (ctx->shader_info->num_inline_push_consts > AC_MAX_INLINE_PUSH_CONSTS)
573 ctx->shader_info->num_inline_push_consts = AC_MAX_INLINE_PUSH_CONSTS;
574
575 if (ctx->shader_info->num_inline_push_consts == num_push_consts &&
576 !ctx->shader_info->loads_dynamic_offsets) {
577 /* Disable the default push constants path if all constants are
578 * inlined and if shaders don't use dynamic descriptors.
579 */
580 ctx->shader_info->loads_push_constants = false;
581 }
582
583 ctx->shader_info->base_inline_push_consts =
584 ctx->shader_info->min_push_constant_used / 4;
585 }
586
587 static void allocate_user_sgprs(struct radv_shader_context *ctx,
588 gl_shader_stage stage,
589 bool has_previous_stage,
590 gl_shader_stage previous_stage,
591 bool needs_view_index,
592 struct user_sgpr_info *user_sgpr_info)
593 {
594 uint8_t user_sgpr_count = 0;
595
596 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
597
598 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
599 if (stage == MESA_SHADER_GEOMETRY ||
600 stage == MESA_SHADER_VERTEX ||
601 stage == MESA_SHADER_TESS_CTRL ||
602 stage == MESA_SHADER_TESS_EVAL ||
603 ctx->is_gs_copy_shader)
604 user_sgpr_info->need_ring_offsets = true;
605
606 if (stage == MESA_SHADER_FRAGMENT &&
607 ctx->shader_info->ps.needs_sample_positions)
608 user_sgpr_info->need_ring_offsets = true;
609
610 /* 2 user sgprs will nearly always be allocated for scratch/rings */
611 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
612 user_sgpr_count += 2;
613 }
614
615 switch (stage) {
616 case MESA_SHADER_COMPUTE:
617 if (ctx->shader_info->cs.uses_grid_size)
618 user_sgpr_count += 3;
619 break;
620 case MESA_SHADER_FRAGMENT:
621 user_sgpr_count += ctx->shader_info->ps.needs_sample_positions;
622 break;
623 case MESA_SHADER_VERTEX:
624 if (!ctx->is_gs_copy_shader)
625 user_sgpr_count += count_vs_user_sgprs(ctx);
626 break;
627 case MESA_SHADER_TESS_CTRL:
628 if (has_previous_stage) {
629 if (previous_stage == MESA_SHADER_VERTEX)
630 user_sgpr_count += count_vs_user_sgprs(ctx);
631 }
632 break;
633 case MESA_SHADER_TESS_EVAL:
634 break;
635 case MESA_SHADER_GEOMETRY:
636 if (has_previous_stage) {
637 if (previous_stage == MESA_SHADER_VERTEX) {
638 user_sgpr_count += count_vs_user_sgprs(ctx);
639 }
640 }
641 break;
642 default:
643 break;
644 }
645
646 if (needs_view_index)
647 user_sgpr_count++;
648
649 if (ctx->shader_info->loads_push_constants)
650 user_sgpr_count++;
651
652 if (ctx->shader_info->so.num_outputs)
653 user_sgpr_count++;
654
655 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
656 uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
657 uint32_t num_desc_set =
658 util_bitcount(ctx->shader_info->desc_set_used_mask);
659
660 if (remaining_sgprs < num_desc_set) {
661 user_sgpr_info->indirect_all_descriptor_sets = true;
662 user_sgpr_info->remaining_sgprs = remaining_sgprs - 1;
663 } else {
664 user_sgpr_info->remaining_sgprs = remaining_sgprs - num_desc_set;
665 }
666
667 allocate_inline_push_consts(ctx, user_sgpr_info);
668 }
669
670 static void
671 declare_global_input_sgprs(struct radv_shader_context *ctx,
672 const struct user_sgpr_info *user_sgpr_info,
673 struct arg_info *args,
674 LLVMValueRef *desc_sets)
675 {
676 LLVMTypeRef type = ac_array_in_const32_addr_space(ctx->ac.i8);
677
678 /* 1 for each descriptor set */
679 if (!user_sgpr_info->indirect_all_descriptor_sets) {
680 uint32_t mask = ctx->shader_info->desc_set_used_mask;
681
682 while (mask) {
683 int i = u_bit_scan(&mask);
684
685 add_arg(args, ARG_SGPR, type, &ctx->descriptor_sets[i]);
686 }
687 } else {
688 add_arg(args, ARG_SGPR, ac_array_in_const32_addr_space(type),
689 desc_sets);
690 }
691
692 if (ctx->shader_info->loads_push_constants) {
693 /* 1 for push constants and dynamic descriptors */
694 add_arg(args, ARG_SGPR, type, &ctx->abi.push_constants);
695 }
696
697 for (unsigned i = 0; i < ctx->shader_info->num_inline_push_consts; i++) {
698 add_arg(args, ARG_SGPR, ctx->ac.i32,
699 &ctx->abi.inline_push_consts[i]);
700 }
701 ctx->abi.num_inline_push_consts = ctx->shader_info->num_inline_push_consts;
702 ctx->abi.base_inline_push_consts = ctx->shader_info->base_inline_push_consts;
703
704 if (ctx->shader_info->so.num_outputs) {
705 add_arg(args, ARG_SGPR,
706 ac_array_in_const32_addr_space(ctx->ac.v4i32),
707 &ctx->streamout_buffers);
708 }
709 }
710
711 static void
712 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
713 gl_shader_stage stage,
714 bool has_previous_stage,
715 gl_shader_stage previous_stage,
716 struct arg_info *args)
717 {
718 if (!ctx->is_gs_copy_shader &&
719 (stage == MESA_SHADER_VERTEX ||
720 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
721 if (ctx->shader_info->vs.has_vertex_buffers) {
722 add_arg(args, ARG_SGPR,
723 ac_array_in_const32_addr_space(ctx->ac.v4i32),
724 &ctx->vertex_buffers);
725 }
726 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
727 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
728 if (ctx->shader_info->vs.needs_draw_id) {
729 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
730 }
731 }
732 }
733
734 static void
735 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
736 {
737 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
738 if (!ctx->is_gs_copy_shader) {
739 if (ctx->options->key.vs_common_out.as_ls) {
740 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
741 if (ctx->ac.chip_class >= GFX10) {
742 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
743 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
744 } else {
745 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
746 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
747 }
748 } else {
749 if (ctx->ac.chip_class >= GFX10) {
750 if (ctx->options->key.vs_common_out.as_ngg) {
751 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
752 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
753 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
754 } else {
755 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
756 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
757 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
758 }
759 } else {
760 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
761 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
762 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
763 }
764 }
765 }
766 }
767
768 static void
769 declare_streamout_sgprs(struct radv_shader_context *ctx, gl_shader_stage stage,
770 struct arg_info *args)
771 {
772 int i;
773
774 if (ctx->options->use_ngg_streamout)
775 return;
776
777 /* Streamout SGPRs. */
778 if (ctx->shader_info->so.num_outputs) {
779 assert(stage == MESA_SHADER_VERTEX ||
780 stage == MESA_SHADER_TESS_EVAL);
781
782 if (stage != MESA_SHADER_TESS_EVAL) {
783 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_config);
784 } else {
785 args->assign[args->count - 1] = &ctx->streamout_config;
786 args->types[args->count - 1] = ctx->ac.i32;
787 }
788
789 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_write_idx);
790 }
791
792 /* A streamout buffer offset is loaded if the stride is non-zero. */
793 for (i = 0; i < 4; i++) {
794 if (!ctx->shader_info->so.strides[i])
795 continue;
796
797 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_offset[i]);
798 }
799 }
800
801 static void
802 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
803 {
804 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
805 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
806 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
807 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
808 }
809
810 static void
811 set_global_input_locs(struct radv_shader_context *ctx,
812 const struct user_sgpr_info *user_sgpr_info,
813 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
814 {
815 uint32_t mask = ctx->shader_info->desc_set_used_mask;
816
817 if (!user_sgpr_info->indirect_all_descriptor_sets) {
818 while (mask) {
819 int i = u_bit_scan(&mask);
820
821 set_loc_desc(ctx, i, user_sgpr_idx);
822 }
823 } else {
824 set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
825 user_sgpr_idx);
826
827 while (mask) {
828 int i = u_bit_scan(&mask);
829
830 ctx->descriptor_sets[i] =
831 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
832 LLVMConstInt(ctx->ac.i32, i, false));
833
834 }
835
836 ctx->shader_info->need_indirect_descriptor_sets = true;
837 }
838
839 if (ctx->shader_info->loads_push_constants) {
840 set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
841 }
842
843 if (ctx->shader_info->num_inline_push_consts) {
844 set_loc_shader(ctx, AC_UD_INLINE_PUSH_CONSTANTS, user_sgpr_idx,
845 ctx->shader_info->num_inline_push_consts);
846 }
847
848 if (ctx->streamout_buffers) {
849 set_loc_shader_ptr(ctx, AC_UD_STREAMOUT_BUFFERS,
850 user_sgpr_idx);
851 }
852 }
853
854 static void
855 set_vs_specific_input_locs(struct radv_shader_context *ctx,
856 gl_shader_stage stage, bool has_previous_stage,
857 gl_shader_stage previous_stage,
858 uint8_t *user_sgpr_idx)
859 {
860 if (!ctx->is_gs_copy_shader &&
861 (stage == MESA_SHADER_VERTEX ||
862 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
863 if (ctx->shader_info->vs.has_vertex_buffers) {
864 set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
865 user_sgpr_idx);
866 }
867
868 unsigned vs_num = 2;
869 if (ctx->shader_info->vs.needs_draw_id)
870 vs_num++;
871
872 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
873 user_sgpr_idx, vs_num);
874 }
875 }
876
877 static void set_llvm_calling_convention(LLVMValueRef func,
878 gl_shader_stage stage)
879 {
880 enum radeon_llvm_calling_convention calling_conv;
881
882 switch (stage) {
883 case MESA_SHADER_VERTEX:
884 case MESA_SHADER_TESS_EVAL:
885 calling_conv = RADEON_LLVM_AMDGPU_VS;
886 break;
887 case MESA_SHADER_GEOMETRY:
888 calling_conv = RADEON_LLVM_AMDGPU_GS;
889 break;
890 case MESA_SHADER_TESS_CTRL:
891 calling_conv = RADEON_LLVM_AMDGPU_HS;
892 break;
893 case MESA_SHADER_FRAGMENT:
894 calling_conv = RADEON_LLVM_AMDGPU_PS;
895 break;
896 case MESA_SHADER_COMPUTE:
897 calling_conv = RADEON_LLVM_AMDGPU_CS;
898 break;
899 default:
900 unreachable("Unhandle shader type");
901 }
902
903 LLVMSetFunctionCallConv(func, calling_conv);
904 }
905
906 /* Returns whether the stage is a stage that can be directly before the GS */
907 static bool is_pre_gs_stage(gl_shader_stage stage)
908 {
909 return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
910 }
911
912 static void create_function(struct radv_shader_context *ctx,
913 gl_shader_stage stage,
914 bool has_previous_stage,
915 gl_shader_stage previous_stage)
916 {
917 uint8_t user_sgpr_idx;
918 struct user_sgpr_info user_sgpr_info;
919 struct arg_info args = {};
920 LLVMValueRef desc_sets;
921 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
922
923 if (ctx->ac.chip_class >= GFX10) {
924 if (is_pre_gs_stage(stage) && ctx->options->key.vs_common_out.as_ngg) {
925 /* On GFX10, VS is merged into GS for NGG. */
926 previous_stage = stage;
927 stage = MESA_SHADER_GEOMETRY;
928 has_previous_stage = true;
929 }
930 }
931
932 allocate_user_sgprs(ctx, stage, has_previous_stage,
933 previous_stage, needs_view_index, &user_sgpr_info);
934
935 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
936 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
937 &ctx->ring_offsets);
938 }
939
940 switch (stage) {
941 case MESA_SHADER_COMPUTE:
942 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
943 &desc_sets);
944
945 if (ctx->shader_info->cs.uses_grid_size) {
946 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
947 &ctx->abi.num_work_groups);
948 }
949
950 for (int i = 0; i < 3; i++) {
951 ctx->abi.workgroup_ids[i] = NULL;
952 if (ctx->shader_info->cs.uses_block_id[i]) {
953 add_arg(&args, ARG_SGPR, ctx->ac.i32,
954 &ctx->abi.workgroup_ids[i]);
955 }
956 }
957
958 if (ctx->shader_info->cs.uses_local_invocation_idx)
959 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
960 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
961 &ctx->abi.local_invocation_ids);
962 break;
963 case MESA_SHADER_VERTEX:
964 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
965 &desc_sets);
966
967 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
968 previous_stage, &args);
969
970 if (needs_view_index)
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->abi.view_index);
973 if (ctx->options->key.vs_common_out.as_es) {
974 add_arg(&args, ARG_SGPR, ctx->ac.i32,
975 &ctx->es2gs_offset);
976 } else if (ctx->options->key.vs_common_out.as_ls) {
977 /* no extra parameters */
978 } else {
979 declare_streamout_sgprs(ctx, stage, &args);
980 }
981
982 declare_vs_input_vgprs(ctx, &args);
983 break;
984 case MESA_SHADER_TESS_CTRL:
985 if (has_previous_stage) {
986 // First 6 system regs
987 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
988 add_arg(&args, ARG_SGPR, ctx->ac.i32,
989 &ctx->merged_wave_info);
990 add_arg(&args, ARG_SGPR, ctx->ac.i32,
991 &ctx->tess_factor_offset);
992
993 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
994 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
995 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
996
997 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
998 &desc_sets);
999
1000 declare_vs_specific_input_sgprs(ctx, stage,
1001 has_previous_stage,
1002 previous_stage, &args);
1003
1004 if (needs_view_index)
1005 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1006 &ctx->abi.view_index);
1007
1008 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1009 &ctx->abi.tcs_patch_id);
1010 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1011 &ctx->abi.tcs_rel_ids);
1012
1013 declare_vs_input_vgprs(ctx, &args);
1014 } else {
1015 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1016 &desc_sets);
1017
1018 if (needs_view_index)
1019 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1020 &ctx->abi.view_index);
1021
1022 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1023 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1024 &ctx->tess_factor_offset);
1025 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1026 &ctx->abi.tcs_patch_id);
1027 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1028 &ctx->abi.tcs_rel_ids);
1029 }
1030 break;
1031 case MESA_SHADER_TESS_EVAL:
1032 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1033 &desc_sets);
1034
1035 if (needs_view_index)
1036 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1037 &ctx->abi.view_index);
1038
1039 if (ctx->options->key.vs_common_out.as_es) {
1040 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1041 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1042 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1043 &ctx->es2gs_offset);
1044 } else {
1045 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1046 declare_streamout_sgprs(ctx, stage, &args);
1047 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1048 }
1049 declare_tes_input_vgprs(ctx, &args);
1050 break;
1051 case MESA_SHADER_GEOMETRY:
1052 if (has_previous_stage) {
1053 // First 6 system regs
1054 if (ctx->options->key.vs_common_out.as_ngg) {
1055 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1056 &ctx->gs_tg_info);
1057 } else {
1058 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1059 &ctx->gs2vs_offset);
1060 }
1061
1062 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1063 &ctx->merged_wave_info);
1064 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1065
1066 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1067 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1068 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1069
1070 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1071 &desc_sets);
1072
1073 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1074 declare_vs_specific_input_sgprs(ctx, stage,
1075 has_previous_stage,
1076 previous_stage,
1077 &args);
1078 }
1079
1080 if (needs_view_index)
1081 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1082 &ctx->abi.view_index);
1083
1084 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1085 &ctx->gs_vtx_offset[0]);
1086 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1087 &ctx->gs_vtx_offset[2]);
1088 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1089 &ctx->abi.gs_prim_id);
1090 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1091 &ctx->abi.gs_invocation_id);
1092 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1093 &ctx->gs_vtx_offset[4]);
1094
1095 if (previous_stage == MESA_SHADER_VERTEX) {
1096 declare_vs_input_vgprs(ctx, &args);
1097 } else {
1098 declare_tes_input_vgprs(ctx, &args);
1099 }
1100 } else {
1101 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1102 &desc_sets);
1103
1104 if (needs_view_index)
1105 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1106 &ctx->abi.view_index);
1107
1108 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1109 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1110 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1111 &ctx->gs_vtx_offset[0]);
1112 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1113 &ctx->gs_vtx_offset[1]);
1114 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1115 &ctx->abi.gs_prim_id);
1116 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1117 &ctx->gs_vtx_offset[2]);
1118 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1119 &ctx->gs_vtx_offset[3]);
1120 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1121 &ctx->gs_vtx_offset[4]);
1122 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1123 &ctx->gs_vtx_offset[5]);
1124 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1125 &ctx->abi.gs_invocation_id);
1126 }
1127 break;
1128 case MESA_SHADER_FRAGMENT:
1129 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1130 &desc_sets);
1131
1132 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1133 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.persp_sample);
1134 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.persp_center);
1135 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.persp_centroid);
1136 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1137 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.linear_sample);
1138 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.linear_center);
1139 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.linear_centroid);
1140 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1141 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1142 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1143 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1144 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1145 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1146 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1147 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1148 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1149 break;
1150 default:
1151 unreachable("Shader stage not implemented");
1152 }
1153
1154 ctx->main_function = create_llvm_function(
1155 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1156 ctx->max_workgroup_size, ctx->options);
1157 set_llvm_calling_convention(ctx->main_function, stage);
1158
1159
1160 ctx->shader_info->num_input_vgprs = 0;
1161 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1162
1163 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1164
1165 if (ctx->stage != MESA_SHADER_FRAGMENT)
1166 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1167
1168 assign_arguments(ctx->main_function, &args);
1169
1170 user_sgpr_idx = 0;
1171
1172 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1173 set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1174 &user_sgpr_idx);
1175 if (ctx->options->supports_spill) {
1176 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1177 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
1178 NULL, 0, AC_FUNC_ATTR_READNONE);
1179 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1180 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1181 }
1182 }
1183
1184 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1185 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1186 if (has_previous_stage)
1187 user_sgpr_idx = 0;
1188
1189 set_global_input_locs(ctx, &user_sgpr_info, desc_sets, &user_sgpr_idx);
1190
1191 switch (stage) {
1192 case MESA_SHADER_COMPUTE:
1193 if (ctx->shader_info->cs.uses_grid_size) {
1194 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1195 &user_sgpr_idx, 3);
1196 }
1197 break;
1198 case MESA_SHADER_VERTEX:
1199 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1200 previous_stage, &user_sgpr_idx);
1201 if (ctx->abi.view_index)
1202 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1203 break;
1204 case MESA_SHADER_TESS_CTRL:
1205 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1206 previous_stage, &user_sgpr_idx);
1207 if (ctx->abi.view_index)
1208 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1209 break;
1210 case MESA_SHADER_TESS_EVAL:
1211 if (ctx->abi.view_index)
1212 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1213 break;
1214 case MESA_SHADER_GEOMETRY:
1215 if (has_previous_stage) {
1216 if (previous_stage == MESA_SHADER_VERTEX)
1217 set_vs_specific_input_locs(ctx, stage,
1218 has_previous_stage,
1219 previous_stage,
1220 &user_sgpr_idx);
1221 }
1222 if (ctx->abi.view_index)
1223 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1224 break;
1225 case MESA_SHADER_FRAGMENT:
1226 break;
1227 default:
1228 unreachable("Shader stage not implemented");
1229 }
1230
1231 if (stage == MESA_SHADER_TESS_CTRL ||
1232 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs_common_out.as_ls) ||
1233 /* GFX9 has the ESGS ring buffer in LDS. */
1234 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1235 ac_declare_lds_as_pointer(&ctx->ac);
1236 }
1237
1238 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1239 }
1240
1241
1242 static LLVMValueRef
1243 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1244 unsigned desc_set, unsigned binding)
1245 {
1246 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1247 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1248 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1249 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1250 unsigned base_offset = layout->binding[binding].offset;
1251 LLVMValueRef offset, stride;
1252
1253 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1254 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1255 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1256 layout->binding[binding].dynamic_offset_offset;
1257 desc_ptr = ctx->abi.push_constants;
1258 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1259 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1260 } else
1261 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1262
1263 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1264
1265 if (layout->binding[binding].type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
1266 offset = ac_build_imad(&ctx->ac, index, stride, offset);
1267 }
1268
1269 desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
1270 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1271 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1272
1273 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
1274 uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1275 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1276 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1277 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1278
1279 if (ctx->ac.chip_class >= GFX10) {
1280 desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1281 S_008F0C_OOB_SELECT(3) |
1282 S_008F0C_RESOURCE_LEVEL(1);
1283 } else {
1284 desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1285 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1286 }
1287
1288 LLVMValueRef desc_components[4] = {
1289 LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
1290 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi), false),
1291 /* High limit to support variable sizes. */
1292 LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
1293 LLVMConstInt(ctx->ac.i32, desc_type, false),
1294 };
1295
1296 return ac_build_gather_values(&ctx->ac, desc_components, 4);
1297 }
1298
1299 return desc_ptr;
1300 }
1301
1302
1303 /* The offchip buffer layout for TCS->TES is
1304 *
1305 * - attribute 0 of patch 0 vertex 0
1306 * - attribute 0 of patch 0 vertex 1
1307 * - attribute 0 of patch 0 vertex 2
1308 * ...
1309 * - attribute 0 of patch 1 vertex 0
1310 * - attribute 0 of patch 1 vertex 1
1311 * ...
1312 * - attribute 1 of patch 0 vertex 0
1313 * - attribute 1 of patch 0 vertex 1
1314 * ...
1315 * - per patch attribute 0 of patch 0
1316 * - per patch attribute 0 of patch 1
1317 * ...
1318 *
1319 * Note that every attribute has 4 components.
1320 */
1321 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1322 {
1323 uint32_t num_patches = ctx->tcs_num_patches;
1324 uint32_t num_tcs_outputs;
1325 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1326 num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
1327 else
1328 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1329
1330 uint32_t output_vertex_size = num_tcs_outputs * 16;
1331 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
1332
1333 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1334 }
1335
1336 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1337 LLVMValueRef vertex_index)
1338 {
1339 LLVMValueRef param_stride;
1340 if (vertex_index)
1341 param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
1342 else
1343 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1344 return param_stride;
1345 }
1346
1347 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1348 LLVMValueRef vertex_index,
1349 LLVMValueRef param_index)
1350 {
1351 LLVMValueRef base_addr;
1352 LLVMValueRef param_stride, constant16;
1353 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1354 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
1355 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1356 param_stride = calc_param_stride(ctx, vertex_index);
1357 if (vertex_index) {
1358 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
1359 vertices_per_patch, vertex_index);
1360 } else {
1361 base_addr = rel_patch_id;
1362 }
1363
1364 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1365 LLVMBuildMul(ctx->ac.builder, param_index,
1366 param_stride, ""), "");
1367
1368 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1369
1370 if (!vertex_index) {
1371 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1372
1373 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1374 patch_data_offset, "");
1375 }
1376 return base_addr;
1377 }
1378
1379 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1380 unsigned param,
1381 unsigned const_index,
1382 bool is_compact,
1383 LLVMValueRef vertex_index,
1384 LLVMValueRef indir_index)
1385 {
1386 LLVMValueRef param_index;
1387
1388 if (indir_index)
1389 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1390 indir_index, "");
1391 else {
1392 if (const_index && !is_compact)
1393 param += const_index;
1394 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1395 }
1396 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1397 }
1398
1399 static LLVMValueRef
1400 get_dw_address(struct radv_shader_context *ctx,
1401 LLVMValueRef dw_addr,
1402 unsigned param,
1403 unsigned const_index,
1404 bool compact_const_index,
1405 LLVMValueRef vertex_index,
1406 LLVMValueRef stride,
1407 LLVMValueRef indir_index)
1408
1409 {
1410
1411 if (vertex_index) {
1412 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1413 LLVMBuildMul(ctx->ac.builder,
1414 vertex_index,
1415 stride, ""), "");
1416 }
1417
1418 if (indir_index)
1419 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1420 LLVMBuildMul(ctx->ac.builder, indir_index,
1421 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1422 else if (const_index && !compact_const_index)
1423 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1424 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1425
1426 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1427 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1428
1429 if (const_index && compact_const_index)
1430 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1431 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1432 return dw_addr;
1433 }
1434
1435 static LLVMValueRef
1436 load_tcs_varyings(struct ac_shader_abi *abi,
1437 LLVMTypeRef type,
1438 LLVMValueRef vertex_index,
1439 LLVMValueRef indir_index,
1440 unsigned const_index,
1441 unsigned location,
1442 unsigned driver_location,
1443 unsigned component,
1444 unsigned num_components,
1445 bool is_patch,
1446 bool is_compact,
1447 bool load_input)
1448 {
1449 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1450 LLVMValueRef dw_addr, stride;
1451 LLVMValueRef value[4], result;
1452 unsigned param = shader_io_get_unique_index(location);
1453
1454 if (load_input) {
1455 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1456 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1457 dw_addr = get_tcs_in_current_patch_offset(ctx);
1458 } else {
1459 if (!is_patch) {
1460 stride = get_tcs_out_vertex_stride(ctx);
1461 dw_addr = get_tcs_out_current_patch_offset(ctx);
1462 } else {
1463 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1464 stride = NULL;
1465 }
1466 }
1467
1468 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1469 indir_index);
1470
1471 for (unsigned i = 0; i < num_components + component; i++) {
1472 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1473 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1474 ctx->ac.i32_1, "");
1475 }
1476 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1477 return result;
1478 }
1479
1480 static void
1481 store_tcs_output(struct ac_shader_abi *abi,
1482 const nir_variable *var,
1483 LLVMValueRef vertex_index,
1484 LLVMValueRef param_index,
1485 unsigned const_index,
1486 LLVMValueRef src,
1487 unsigned writemask)
1488 {
1489 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1490 const unsigned location = var->data.location;
1491 unsigned component = var->data.location_frac;
1492 const bool is_patch = var->data.patch;
1493 const bool is_compact = var->data.compact;
1494 LLVMValueRef dw_addr;
1495 LLVMValueRef stride = NULL;
1496 LLVMValueRef buf_addr = NULL;
1497 unsigned param;
1498 bool store_lds = true;
1499
1500 if (is_patch) {
1501 if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1502 store_lds = false;
1503 } else {
1504 if (!(ctx->shader->info.outputs_read & (1ULL << location)))
1505 store_lds = false;
1506 }
1507
1508 param = shader_io_get_unique_index(location);
1509 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
1510 const_index += component;
1511 component = 0;
1512
1513 if (const_index >= 4) {
1514 const_index -= 4;
1515 param++;
1516 }
1517 }
1518
1519 if (!is_patch) {
1520 stride = get_tcs_out_vertex_stride(ctx);
1521 dw_addr = get_tcs_out_current_patch_offset(ctx);
1522 } else {
1523 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1524 }
1525
1526 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1527 param_index);
1528 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1529 vertex_index, param_index);
1530
1531 bool is_tess_factor = false;
1532 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1533 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1534 is_tess_factor = true;
1535
1536 unsigned base = is_compact ? const_index : 0;
1537 for (unsigned chan = 0; chan < 8; chan++) {
1538 if (!(writemask & (1 << chan)))
1539 continue;
1540 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1541 value = ac_to_integer(&ctx->ac, value);
1542 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
1543
1544 if (store_lds || is_tess_factor) {
1545 LLVMValueRef dw_addr_chan =
1546 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1547 LLVMConstInt(ctx->ac.i32, chan, false), "");
1548 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1549 }
1550
1551 if (!is_tess_factor && writemask != 0xF)
1552 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1553 buf_addr, ctx->oc_lds,
1554 4 * (base + chan), ac_glc, false);
1555 }
1556
1557 if (writemask == 0xF) {
1558 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1559 buf_addr, ctx->oc_lds,
1560 (base * 4), ac_glc, false);
1561 }
1562 }
1563
1564 static LLVMValueRef
1565 load_tes_input(struct ac_shader_abi *abi,
1566 LLVMTypeRef type,
1567 LLVMValueRef vertex_index,
1568 LLVMValueRef param_index,
1569 unsigned const_index,
1570 unsigned location,
1571 unsigned driver_location,
1572 unsigned component,
1573 unsigned num_components,
1574 bool is_patch,
1575 bool is_compact,
1576 bool load_input)
1577 {
1578 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1579 LLVMValueRef buf_addr;
1580 LLVMValueRef result;
1581 unsigned param = shader_io_get_unique_index(location);
1582
1583 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
1584 const_index += component;
1585 component = 0;
1586 if (const_index >= 4) {
1587 const_index -= 4;
1588 param++;
1589 }
1590 }
1591
1592 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1593 is_compact, vertex_index, param_index);
1594
1595 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1596 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1597
1598 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1599 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
1600 result = ac_trim_vector(&ctx->ac, result, num_components);
1601 return result;
1602 }
1603
1604 static LLVMValueRef
1605 load_gs_input(struct ac_shader_abi *abi,
1606 unsigned location,
1607 unsigned driver_location,
1608 unsigned component,
1609 unsigned num_components,
1610 unsigned vertex_index,
1611 unsigned const_index,
1612 LLVMTypeRef type)
1613 {
1614 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1615 LLVMValueRef vtx_offset;
1616 unsigned param, vtx_offset_param;
1617 LLVMValueRef value[4], result;
1618
1619 vtx_offset_param = vertex_index;
1620 assert(vtx_offset_param < 6);
1621 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1622 LLVMConstInt(ctx->ac.i32, 4, false), "");
1623
1624 param = shader_io_get_unique_index(location);
1625
1626 for (unsigned i = component; i < num_components + component; i++) {
1627 if (ctx->ac.chip_class >= GFX9) {
1628 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1629 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1630 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1631 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1632 } else {
1633 LLVMValueRef soffset =
1634 LLVMConstInt(ctx->ac.i32,
1635 (param * 4 + i + const_index) * 256,
1636 false);
1637
1638 value[i] = ac_build_buffer_load(&ctx->ac,
1639 ctx->esgs_ring, 1,
1640 ctx->ac.i32_0,
1641 vtx_offset, soffset,
1642 0, ac_glc, true, false);
1643 }
1644
1645 if (ac_get_type_size(type) == 2) {
1646 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
1647 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
1648 }
1649 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
1650 }
1651 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1652 result = ac_to_integer(&ctx->ac, result);
1653 return result;
1654 }
1655
1656
1657 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1658 {
1659 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1660 ac_build_kill_if_false(&ctx->ac, visible);
1661 }
1662
1663 static uint32_t
1664 radv_get_sample_pos_offset(uint32_t num_samples)
1665 {
1666 uint32_t sample_pos_offset = 0;
1667
1668 switch (num_samples) {
1669 case 2:
1670 sample_pos_offset = 1;
1671 break;
1672 case 4:
1673 sample_pos_offset = 3;
1674 break;
1675 case 8:
1676 sample_pos_offset = 7;
1677 break;
1678 default:
1679 break;
1680 }
1681 return sample_pos_offset;
1682 }
1683
1684 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1685 LLVMValueRef sample_id)
1686 {
1687 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1688
1689 LLVMValueRef result;
1690 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false);
1691 LLVMValueRef ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ring_offsets, &index, 1, "");
1692
1693 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1694 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1695
1696 uint32_t sample_pos_offset =
1697 radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
1698
1699 sample_id =
1700 LLVMBuildAdd(ctx->ac.builder, sample_id,
1701 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
1702 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1703
1704 return result;
1705 }
1706
1707
1708 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1709 {
1710 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1711 uint8_t log2_ps_iter_samples;
1712
1713 if (ctx->shader_info->ps.force_persample) {
1714 log2_ps_iter_samples =
1715 util_logbase2(ctx->options->key.fs.num_samples);
1716 } else {
1717 log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
1718 }
1719
1720 /* The bit pattern matches that used by fixed function fragment
1721 * processing. */
1722 static const uint16_t ps_iter_masks[] = {
1723 0xffff, /* not used */
1724 0x5555,
1725 0x1111,
1726 0x0101,
1727 0x0001,
1728 };
1729 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1730
1731 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1732
1733 LLVMValueRef result, sample_id;
1734 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1735 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1736 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1737 return result;
1738 }
1739
1740
1741 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
1742 unsigned stream,
1743 LLVMValueRef *addrs);
1744
1745 static void
1746 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1747 {
1748 LLVMValueRef gs_next_vertex;
1749 LLVMValueRef can_emit;
1750 unsigned offset = 0;
1751 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1752
1753 if (ctx->options->key.vs_common_out.as_ngg) {
1754 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
1755 return;
1756 }
1757
1758 /* Write vertex attribute values to GSVS ring */
1759 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1760 ctx->gs_next_vertex[stream],
1761 "");
1762
1763 /* If this thread has already emitted the declared maximum number of
1764 * vertices, kill it: excessive vertex emissions are not supposed to
1765 * have any effect, and GS threads have no externally observable
1766 * effects other than emitting vertices.
1767 */
1768 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1769 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
1770 ac_build_kill_if_false(&ctx->ac, can_emit);
1771
1772 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1773 unsigned output_usage_mask =
1774 ctx->shader_info->gs.output_usage_mask[i];
1775 uint8_t output_stream =
1776 ctx->shader_info->gs.output_streams[i];
1777 LLVMValueRef *out_ptr = &addrs[i * 4];
1778 int length = util_last_bit(output_usage_mask);
1779
1780 if (!(ctx->output_mask & (1ull << i)) ||
1781 output_stream != stream)
1782 continue;
1783
1784 for (unsigned j = 0; j < length; j++) {
1785 if (!(output_usage_mask & (1 << j)))
1786 continue;
1787
1788 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1789 out_ptr[j], "");
1790 LLVMValueRef voffset =
1791 LLVMConstInt(ctx->ac.i32, offset *
1792 ctx->shader->info.gs.vertices_out, false);
1793
1794 offset++;
1795
1796 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1797 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1798
1799 out_val = ac_to_integer(&ctx->ac, out_val);
1800 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1801
1802 ac_build_buffer_store_dword(&ctx->ac,
1803 ctx->gsvs_ring[stream],
1804 out_val, 1,
1805 voffset, ctx->gs2vs_offset, 0,
1806 ac_glc | ac_slc, true);
1807 }
1808 }
1809
1810 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1811 ctx->ac.i32_1, "");
1812 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
1813
1814 ac_build_sendmsg(&ctx->ac,
1815 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
1816 ctx->gs_wave_id);
1817 }
1818
1819 static void
1820 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1821 {
1822 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1823
1824 if (ctx->options->key.vs_common_out.as_ngg) {
1825 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
1826 return;
1827 }
1828
1829 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1830 }
1831
1832 static LLVMValueRef
1833 load_tess_coord(struct ac_shader_abi *abi)
1834 {
1835 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1836
1837 LLVMValueRef coord[4] = {
1838 ctx->tes_u,
1839 ctx->tes_v,
1840 ctx->ac.f32_0,
1841 ctx->ac.f32_0,
1842 };
1843
1844 if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
1845 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1846 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1847
1848 return ac_build_gather_values(&ctx->ac, coord, 3);
1849 }
1850
1851 static LLVMValueRef
1852 load_patch_vertices_in(struct ac_shader_abi *abi)
1853 {
1854 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1855 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1856 }
1857
1858
1859 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1860 {
1861 return abi->base_vertex;
1862 }
1863
1864 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1865 LLVMValueRef buffer_ptr, bool write)
1866 {
1867 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1868 LLVMValueRef result;
1869
1870 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1871
1872 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1873 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1874
1875 return result;
1876 }
1877
1878 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1879 {
1880 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1881 LLVMValueRef result;
1882
1883 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr)) != LLVMPointerTypeKind) {
1884 /* Do not load the descriptor for inlined uniform blocks. */
1885 return buffer_ptr;
1886 }
1887
1888 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1889
1890 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1891 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1892
1893 return result;
1894 }
1895
1896 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1897 unsigned descriptor_set,
1898 unsigned base_index,
1899 unsigned constant_index,
1900 LLVMValueRef index,
1901 enum ac_descriptor_type desc_type,
1902 bool image, bool write,
1903 bool bindless)
1904 {
1905 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1906 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1907 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1908 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1909 unsigned offset = binding->offset;
1910 unsigned stride = binding->size;
1911 unsigned type_size;
1912 LLVMBuilderRef builder = ctx->ac.builder;
1913 LLVMTypeRef type;
1914
1915 assert(base_index < layout->binding_count);
1916
1917 switch (desc_type) {
1918 case AC_DESC_IMAGE:
1919 type = ctx->ac.v8i32;
1920 type_size = 32;
1921 break;
1922 case AC_DESC_FMASK:
1923 type = ctx->ac.v8i32;
1924 offset += 32;
1925 type_size = 32;
1926 break;
1927 case AC_DESC_SAMPLER:
1928 type = ctx->ac.v4i32;
1929 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
1930 offset += radv_combined_image_descriptor_sampler_offset(binding);
1931 }
1932
1933 type_size = 16;
1934 break;
1935 case AC_DESC_BUFFER:
1936 type = ctx->ac.v4i32;
1937 type_size = 16;
1938 break;
1939 case AC_DESC_PLANE_0:
1940 case AC_DESC_PLANE_1:
1941 case AC_DESC_PLANE_2:
1942 type = ctx->ac.v8i32;
1943 type_size = 32;
1944 offset += 32 * (desc_type - AC_DESC_PLANE_0);
1945 break;
1946 default:
1947 unreachable("invalid desc_type\n");
1948 }
1949
1950 offset += constant_index * stride;
1951
1952 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1953 (!index || binding->immutable_samplers_equal)) {
1954 if (binding->immutable_samplers_equal)
1955 constant_index = 0;
1956
1957 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1958
1959 LLVMValueRef constants[] = {
1960 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1961 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1962 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1963 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1964 };
1965 return ac_build_gather_values(&ctx->ac, constants, 4);
1966 }
1967
1968 assert(stride % type_size == 0);
1969
1970 LLVMValueRef adjusted_index = index;
1971 if (!adjusted_index)
1972 adjusted_index = ctx->ac.i32_0;
1973
1974 adjusted_index = LLVMBuildMul(builder, adjusted_index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1975
1976 LLVMValueRef val_offset = LLVMConstInt(ctx->ac.i32, offset, 0);
1977 list = LLVMBuildGEP(builder, list, &val_offset, 1, "");
1978 list = LLVMBuildPointerCast(builder, list,
1979 ac_array_in_const32_addr_space(type), "");
1980
1981 LLVMValueRef descriptor = ac_build_load_to_sgpr(&ctx->ac, list, adjusted_index);
1982
1983 /* 3 plane formats always have same size and format for plane 1 & 2, so
1984 * use the tail from plane 1 so that we can store only the first 16 bytes
1985 * of the last plane. */
1986 if (desc_type == AC_DESC_PLANE_2) {
1987 LLVMValueRef descriptor2 = radv_get_sampler_desc(abi, descriptor_set, base_index, constant_index, index, AC_DESC_PLANE_1,image, write, bindless);
1988
1989 LLVMValueRef components[8];
1990 for (unsigned i = 0; i < 4; ++i)
1991 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor, i);
1992
1993 for (unsigned i = 4; i < 8; ++i)
1994 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor2, i);
1995 descriptor = ac_build_gather_values(&ctx->ac, components, 8);
1996 }
1997
1998 return descriptor;
1999 }
2000
2001 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
2002 * so we may need to fix it up. */
2003 static LLVMValueRef
2004 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
2005 unsigned adjustment,
2006 LLVMValueRef alpha)
2007 {
2008 if (adjustment == RADV_ALPHA_ADJUST_NONE)
2009 return alpha;
2010
2011 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
2012
2013 alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
2014
2015 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
2016 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
2017 else
2018 alpha = ac_to_integer(&ctx->ac, alpha);
2019
2020 /* For the integer-like cases, do a natural sign extension.
2021 *
2022 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2023 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2024 * exponent.
2025 */
2026 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
2027 adjustment == RADV_ALPHA_ADJUST_SNORM ?
2028 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
2029 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
2030
2031 /* Convert back to the right type. */
2032 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
2033 LLVMValueRef clamp;
2034 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
2035 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
2036 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
2037 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
2038 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
2039 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
2040 }
2041
2042 return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
2043 }
2044
2045 static unsigned
2046 get_num_channels_from_data_format(unsigned data_format)
2047 {
2048 switch (data_format) {
2049 case V_008F0C_BUF_DATA_FORMAT_8:
2050 case V_008F0C_BUF_DATA_FORMAT_16:
2051 case V_008F0C_BUF_DATA_FORMAT_32:
2052 return 1;
2053 case V_008F0C_BUF_DATA_FORMAT_8_8:
2054 case V_008F0C_BUF_DATA_FORMAT_16_16:
2055 case V_008F0C_BUF_DATA_FORMAT_32_32:
2056 return 2;
2057 case V_008F0C_BUF_DATA_FORMAT_10_11_11:
2058 case V_008F0C_BUF_DATA_FORMAT_11_11_10:
2059 case V_008F0C_BUF_DATA_FORMAT_32_32_32:
2060 return 3;
2061 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8:
2062 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2:
2063 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10:
2064 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16:
2065 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32:
2066 return 4;
2067 default:
2068 break;
2069 }
2070
2071 return 4;
2072 }
2073
2074 static LLVMValueRef
2075 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
2076 LLVMValueRef value,
2077 unsigned num_channels,
2078 bool is_float)
2079 {
2080 LLVMValueRef zero = is_float ? ctx->ac.f32_0 : ctx->ac.i32_0;
2081 LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
2082 LLVMValueRef chan[4];
2083
2084 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
2085 unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
2086
2087 if (num_channels == 4 && num_channels == vec_size)
2088 return value;
2089
2090 num_channels = MIN2(num_channels, vec_size);
2091
2092 for (unsigned i = 0; i < num_channels; i++)
2093 chan[i] = ac_llvm_extract_elem(&ctx->ac, value, i);
2094 } else {
2095 if (num_channels) {
2096 assert(num_channels == 1);
2097 chan[0] = value;
2098 }
2099 }
2100
2101 for (unsigned i = num_channels; i < 4; i++) {
2102 chan[i] = i == 3 ? one : zero;
2103 chan[i] = ac_to_integer(&ctx->ac, chan[i]);
2104 }
2105
2106 return ac_build_gather_values(&ctx->ac, chan, 4);
2107 }
2108
2109 static void
2110 handle_vs_input_decl(struct radv_shader_context *ctx,
2111 struct nir_variable *variable)
2112 {
2113 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
2114 LLVMValueRef t_offset;
2115 LLVMValueRef t_list;
2116 LLVMValueRef input;
2117 LLVMValueRef buffer_index;
2118 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
2119 uint8_t input_usage_mask =
2120 ctx->shader_info->vs.input_usage_mask[variable->data.location];
2121 unsigned num_input_channels = util_last_bit(input_usage_mask);
2122
2123 variable->data.driver_location = variable->data.location * 4;
2124
2125 enum glsl_base_type type = glsl_get_base_type(variable->type);
2126 for (unsigned i = 0; i < attrib_count; ++i) {
2127 LLVMValueRef output[4];
2128 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
2129 unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[attrib_index];
2130 unsigned data_format = attrib_format & 0x0f;
2131 unsigned num_format = (attrib_format >> 4) & 0x07;
2132 bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
2133 num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
2134
2135 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
2136 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
2137
2138 if (divisor) {
2139 buffer_index = ctx->abi.instance_id;
2140
2141 if (divisor != 1) {
2142 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
2143 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
2144 }
2145 } else {
2146 buffer_index = ctx->ac.i32_0;
2147 }
2148
2149 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index, "");
2150 } else
2151 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
2152 ctx->abi.base_vertex, "");
2153
2154 /* Adjust the number of channels to load based on the vertex
2155 * attribute format.
2156 */
2157 unsigned num_format_channels = get_num_channels_from_data_format(data_format);
2158 unsigned num_channels = MIN2(num_input_channels, num_format_channels);
2159 unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[attrib_index];
2160 unsigned attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[attrib_index];
2161 unsigned attrib_stride = ctx->options->key.vs.vertex_attribute_strides[attrib_index];
2162
2163 if (ctx->options->key.vs.post_shuffle & (1 << attrib_index)) {
2164 /* Always load, at least, 3 channels for formats that
2165 * need to be shuffled because X<->Z.
2166 */
2167 num_channels = MAX2(num_channels, 3);
2168 }
2169
2170 if (attrib_stride != 0 && attrib_offset > attrib_stride) {
2171 LLVMValueRef buffer_offset =
2172 LLVMConstInt(ctx->ac.i32,
2173 attrib_offset / attrib_stride, false);
2174
2175 buffer_index = LLVMBuildAdd(ctx->ac.builder,
2176 buffer_index,
2177 buffer_offset, "");
2178
2179 attrib_offset = attrib_offset % attrib_stride;
2180 }
2181
2182 t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false);
2183 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
2184
2185 input = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
2186 buffer_index,
2187 LLVMConstInt(ctx->ac.i32, attrib_offset, false),
2188 ctx->ac.i32_0, ctx->ac.i32_0,
2189 num_channels,
2190 data_format, num_format, 0, true);
2191
2192 if (ctx->options->key.vs.post_shuffle & (1 << attrib_index)) {
2193 LLVMValueRef c[4];
2194 c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
2195 c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
2196 c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
2197 c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
2198
2199 input = ac_build_gather_values(&ctx->ac, c, 4);
2200 }
2201
2202 input = radv_fixup_vertex_input_fetches(ctx, input, num_channels,
2203 is_float);
2204
2205 for (unsigned chan = 0; chan < 4; chan++) {
2206 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2207 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
2208 if (type == GLSL_TYPE_FLOAT16) {
2209 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
2210 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
2211 }
2212 }
2213
2214 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
2215 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
2216
2217 for (unsigned chan = 0; chan < 4; chan++) {
2218 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
2219 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
2220 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
2221
2222 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
2223 }
2224 }
2225 }
2226
2227 static void
2228 handle_vs_inputs(struct radv_shader_context *ctx,
2229 struct nir_shader *nir) {
2230 nir_foreach_variable(variable, &nir->inputs)
2231 handle_vs_input_decl(ctx, variable);
2232 }
2233
2234 static void
2235 prepare_interp_optimize(struct radv_shader_context *ctx,
2236 struct nir_shader *nir)
2237 {
2238 bool uses_center = false;
2239 bool uses_centroid = false;
2240 nir_foreach_variable(variable, &nir->inputs) {
2241 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2242 variable->data.sample)
2243 continue;
2244
2245 if (variable->data.centroid)
2246 uses_centroid = true;
2247 else
2248 uses_center = true;
2249 }
2250
2251 if (uses_center && uses_centroid) {
2252 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2253 ctx->abi.persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->abi.persp_center, ctx->abi.persp_centroid, "");
2254 ctx->abi.linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->abi.linear_center, ctx->abi.linear_centroid, "");
2255 }
2256 }
2257
2258 static void
2259 scan_shader_output_decl(struct radv_shader_context *ctx,
2260 struct nir_variable *variable,
2261 struct nir_shader *shader,
2262 gl_shader_stage stage)
2263 {
2264 int idx = variable->data.location + variable->data.index;
2265 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2266 uint64_t mask_attribs;
2267
2268 variable->data.driver_location = idx * 4;
2269
2270 /* tess ctrl has it's own load/store paths for outputs */
2271 if (stage == MESA_SHADER_TESS_CTRL)
2272 return;
2273
2274 if (variable->data.compact) {
2275 unsigned component_count = variable->data.location_frac +
2276 glsl_get_length(variable->type);
2277 attrib_count = (component_count + 3) / 4;
2278 }
2279
2280 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2281
2282 ctx->output_mask |= mask_attribs;
2283 }
2284
2285
2286 /* Initialize arguments for the shader export intrinsic */
2287 static void
2288 si_llvm_init_export_args(struct radv_shader_context *ctx,
2289 LLVMValueRef *values,
2290 unsigned enabled_channels,
2291 unsigned target,
2292 struct ac_export_args *args)
2293 {
2294 /* Specify the channels that are enabled. */
2295 args->enabled_channels = enabled_channels;
2296
2297 /* Specify whether the EXEC mask represents the valid mask */
2298 args->valid_mask = 0;
2299
2300 /* Specify whether this is the last export */
2301 args->done = 0;
2302
2303 /* Specify the target we are exporting */
2304 args->target = target;
2305
2306 args->compr = false;
2307 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2308 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2309 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2310 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2311
2312 if (!values)
2313 return;
2314
2315 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
2316 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2317 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2318 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2319 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2320 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2321 unsigned chan;
2322
2323 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2324 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2325 unsigned bits, bool hi) = NULL;
2326
2327 switch(col_format) {
2328 case V_028714_SPI_SHADER_ZERO:
2329 args->enabled_channels = 0; /* writemask */
2330 args->target = V_008DFC_SQ_EXP_NULL;
2331 break;
2332
2333 case V_028714_SPI_SHADER_32_R:
2334 args->enabled_channels = 1;
2335 args->out[0] = values[0];
2336 break;
2337
2338 case V_028714_SPI_SHADER_32_GR:
2339 args->enabled_channels = 0x3;
2340 args->out[0] = values[0];
2341 args->out[1] = values[1];
2342 break;
2343
2344 case V_028714_SPI_SHADER_32_AR:
2345 if (ctx->ac.chip_class >= GFX10) {
2346 args->enabled_channels = 0x3;
2347 args->out[0] = values[0];
2348 args->out[1] = values[3];
2349 } else {
2350 args->enabled_channels = 0x9;
2351 args->out[0] = values[0];
2352 args->out[3] = values[3];
2353 }
2354 break;
2355
2356 case V_028714_SPI_SHADER_FP16_ABGR:
2357 args->enabled_channels = 0x5;
2358 packf = ac_build_cvt_pkrtz_f16;
2359 if (is_16bit) {
2360 for (unsigned chan = 0; chan < 4; chan++)
2361 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
2362 values[chan],
2363 ctx->ac.f32, "");
2364 }
2365 break;
2366
2367 case V_028714_SPI_SHADER_UNORM16_ABGR:
2368 args->enabled_channels = 0x5;
2369 packf = ac_build_cvt_pknorm_u16;
2370 break;
2371
2372 case V_028714_SPI_SHADER_SNORM16_ABGR:
2373 args->enabled_channels = 0x5;
2374 packf = ac_build_cvt_pknorm_i16;
2375 break;
2376
2377 case V_028714_SPI_SHADER_UINT16_ABGR:
2378 args->enabled_channels = 0x5;
2379 packi = ac_build_cvt_pk_u16;
2380 if (is_16bit) {
2381 for (unsigned chan = 0; chan < 4; chan++)
2382 values[chan] = LLVMBuildZExt(ctx->ac.builder,
2383 ac_to_integer(&ctx->ac, values[chan]),
2384 ctx->ac.i32, "");
2385 }
2386 break;
2387
2388 case V_028714_SPI_SHADER_SINT16_ABGR:
2389 args->enabled_channels = 0x5;
2390 packi = ac_build_cvt_pk_i16;
2391 if (is_16bit) {
2392 for (unsigned chan = 0; chan < 4; chan++)
2393 values[chan] = LLVMBuildSExt(ctx->ac.builder,
2394 ac_to_integer(&ctx->ac, values[chan]),
2395 ctx->ac.i32, "");
2396 }
2397 break;
2398
2399 default:
2400 case V_028714_SPI_SHADER_32_ABGR:
2401 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2402 break;
2403 }
2404
2405 /* Pack f16 or norm_i16/u16. */
2406 if (packf) {
2407 for (chan = 0; chan < 2; chan++) {
2408 LLVMValueRef pack_args[2] = {
2409 values[2 * chan],
2410 values[2 * chan + 1]
2411 };
2412 LLVMValueRef packed;
2413
2414 packed = packf(&ctx->ac, pack_args);
2415 args->out[chan] = ac_to_float(&ctx->ac, packed);
2416 }
2417 args->compr = 1; /* COMPR flag */
2418 }
2419
2420 /* Pack i16/u16. */
2421 if (packi) {
2422 for (chan = 0; chan < 2; chan++) {
2423 LLVMValueRef pack_args[2] = {
2424 ac_to_integer(&ctx->ac, values[2 * chan]),
2425 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2426 };
2427 LLVMValueRef packed;
2428
2429 packed = packi(&ctx->ac, pack_args,
2430 is_int8 ? 8 : is_int10 ? 10 : 16,
2431 chan == 1);
2432 args->out[chan] = ac_to_float(&ctx->ac, packed);
2433 }
2434 args->compr = 1; /* COMPR flag */
2435 }
2436 return;
2437 }
2438
2439 if (is_16bit) {
2440 for (unsigned chan = 0; chan < 4; chan++) {
2441 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
2442 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
2443 }
2444 } else
2445 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2446
2447 for (unsigned i = 0; i < 4; ++i)
2448 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2449 }
2450
2451 static void
2452 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2453 LLVMValueRef *values, unsigned enabled_channels)
2454 {
2455 struct ac_export_args args;
2456
2457 si_llvm_init_export_args(ctx, values, enabled_channels,
2458 V_008DFC_SQ_EXP_PARAM + index, &args);
2459 ac_build_export(&ctx->ac, &args);
2460 }
2461
2462 static LLVMValueRef
2463 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2464 {
2465 LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2466 return LLVMBuildLoad(ctx->ac.builder, output, "");
2467 }
2468
2469 static void
2470 radv_emit_stream_output(struct radv_shader_context *ctx,
2471 LLVMValueRef const *so_buffers,
2472 LLVMValueRef const *so_write_offsets,
2473 const struct radv_stream_output *output,
2474 struct radv_shader_output_values *shader_out)
2475 {
2476 unsigned num_comps = util_bitcount(output->component_mask);
2477 unsigned buf = output->buffer;
2478 unsigned offset = output->offset;
2479 unsigned start;
2480 LLVMValueRef out[4];
2481
2482 assert(num_comps && num_comps <= 4);
2483 if (!num_comps || num_comps > 4)
2484 return;
2485
2486 /* Get the first component. */
2487 start = ffs(output->component_mask) - 1;
2488
2489 /* Load the output as int. */
2490 for (int i = 0; i < num_comps; i++) {
2491 out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
2492 }
2493
2494 /* Pack the output. */
2495 LLVMValueRef vdata = NULL;
2496
2497 switch (num_comps) {
2498 case 1: /* as i32 */
2499 vdata = out[0];
2500 break;
2501 case 2: /* as v2i32 */
2502 case 3: /* as v4i32 (aligned to 4) */
2503 out[3] = LLVMGetUndef(ctx->ac.i32);
2504 /* fall through */
2505 case 4: /* as v4i32 */
2506 vdata = ac_build_gather_values(&ctx->ac, out,
2507 !ac_has_vec3_support(ctx->ac.chip_class, false) ?
2508 util_next_power_of_two(num_comps) :
2509 num_comps);
2510 break;
2511 }
2512
2513 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
2514 vdata, num_comps, so_write_offsets[buf],
2515 ctx->ac.i32_0, offset,
2516 ac_glc | ac_slc, false);
2517 }
2518
2519 static void
2520 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
2521 {
2522 int i;
2523
2524 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2525 assert(ctx->streamout_config);
2526 LLVMValueRef so_vtx_count =
2527 ac_build_bfe(&ctx->ac, ctx->streamout_config,
2528 LLVMConstInt(ctx->ac.i32, 16, false),
2529 LLVMConstInt(ctx->ac.i32, 7, false), false);
2530
2531 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2532
2533 /* can_emit = tid < so_vtx_count; */
2534 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
2535 tid, so_vtx_count, "");
2536
2537 /* Emit the streamout code conditionally. This actually avoids
2538 * out-of-bounds buffer access. The hw tells us via the SGPR
2539 * (so_vtx_count) which threads are allowed to emit streamout data.
2540 */
2541 ac_build_ifcc(&ctx->ac, can_emit, 6501);
2542 {
2543 /* The buffer offset is computed as follows:
2544 * ByteOffset = streamout_offset[buffer_id]*4 +
2545 * (streamout_write_index + thread_id)*stride[buffer_id] +
2546 * attrib_offset
2547 */
2548 LLVMValueRef so_write_index = ctx->streamout_write_idx;
2549
2550 /* Compute (streamout_write_index + thread_id). */
2551 so_write_index =
2552 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
2553
2554 /* Load the descriptor and compute the write offset for each
2555 * enabled buffer.
2556 */
2557 LLVMValueRef so_write_offset[4] = {};
2558 LLVMValueRef so_buffers[4] = {};
2559 LLVMValueRef buf_ptr = ctx->streamout_buffers;
2560
2561 for (i = 0; i < 4; i++) {
2562 uint16_t stride = ctx->shader_info->so.strides[i];
2563
2564 if (!stride)
2565 continue;
2566
2567 LLVMValueRef offset =
2568 LLVMConstInt(ctx->ac.i32, i, false);
2569
2570 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
2571 buf_ptr, offset);
2572
2573 LLVMValueRef so_offset = ctx->streamout_offset[i];
2574
2575 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
2576 LLVMConstInt(ctx->ac.i32, 4, false), "");
2577
2578 so_write_offset[i] =
2579 ac_build_imad(&ctx->ac, so_write_index,
2580 LLVMConstInt(ctx->ac.i32,
2581 stride * 4, false),
2582 so_offset);
2583 }
2584
2585 /* Write streamout data. */
2586 for (i = 0; i < ctx->shader_info->so.num_outputs; i++) {
2587 struct radv_shader_output_values shader_out = {};
2588 struct radv_stream_output *output =
2589 &ctx->shader_info->so.outputs[i];
2590
2591 if (stream != output->stream)
2592 continue;
2593
2594 for (int j = 0; j < 4; j++) {
2595 shader_out.values[j] =
2596 radv_load_output(ctx, output->location, j);
2597 }
2598
2599 radv_emit_stream_output(ctx, so_buffers,so_write_offset,
2600 output, &shader_out);
2601 }
2602 }
2603 ac_build_endif(&ctx->ac, 6501);
2604 }
2605
2606 static void
2607 radv_build_param_exports(struct radv_shader_context *ctx,
2608 struct radv_shader_output_values *outputs,
2609 unsigned noutput,
2610 struct radv_vs_output_info *outinfo,
2611 bool export_clip_dists)
2612 {
2613 unsigned param_count = 0;
2614
2615 for (unsigned i = 0; i < noutput; i++) {
2616 unsigned slot_name = outputs[i].slot_name;
2617 unsigned usage_mask = outputs[i].usage_mask;
2618
2619 if (slot_name != VARYING_SLOT_LAYER &&
2620 slot_name != VARYING_SLOT_PRIMITIVE_ID &&
2621 slot_name != VARYING_SLOT_CLIP_DIST0 &&
2622 slot_name != VARYING_SLOT_CLIP_DIST1 &&
2623 slot_name < VARYING_SLOT_VAR0)
2624 continue;
2625
2626 if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
2627 slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
2628 continue;
2629
2630 radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
2631
2632 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
2633 outinfo->vs_output_param_offset[slot_name] = param_count++;
2634 }
2635
2636 outinfo->param_exports = param_count;
2637 }
2638
2639 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2640 * (position and parameter data only).
2641 */
2642 static void
2643 radv_llvm_export_vs(struct radv_shader_context *ctx,
2644 struct radv_shader_output_values *outputs,
2645 unsigned noutput,
2646 struct radv_vs_output_info *outinfo,
2647 bool export_clip_dists)
2648 {
2649 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
2650 struct ac_export_args pos_args[4] = {};
2651 unsigned pos_idx, index;
2652 int i;
2653
2654 /* Build position exports */
2655 for (i = 0; i < noutput; i++) {
2656 switch (outputs[i].slot_name) {
2657 case VARYING_SLOT_POS:
2658 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
2659 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2660 break;
2661 case VARYING_SLOT_PSIZ:
2662 psize_value = outputs[i].values[0];
2663 break;
2664 case VARYING_SLOT_LAYER:
2665 layer_value = outputs[i].values[0];
2666 break;
2667 case VARYING_SLOT_VIEWPORT:
2668 viewport_value = outputs[i].values[0];
2669 break;
2670 case VARYING_SLOT_CLIP_DIST0:
2671 case VARYING_SLOT_CLIP_DIST1:
2672 index = 2 + outputs[i].slot_index;
2673 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
2674 V_008DFC_SQ_EXP_POS + index,
2675 &pos_args[index]);
2676 break;
2677 default:
2678 break;
2679 }
2680 }
2681
2682 /* We need to add the position output manually if it's missing. */
2683 if (!pos_args[0].out[0]) {
2684 pos_args[0].enabled_channels = 0xf; /* writemask */
2685 pos_args[0].valid_mask = 0; /* EXEC mask */
2686 pos_args[0].done = 0; /* last export? */
2687 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2688 pos_args[0].compr = 0; /* COMPR flag */
2689 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2690 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2691 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2692 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2693 }
2694
2695 if (outinfo->writes_pointsize ||
2696 outinfo->writes_layer ||
2697 outinfo->writes_viewport_index) {
2698 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2699 (outinfo->writes_layer == true ? 4 : 0));
2700 pos_args[1].valid_mask = 0;
2701 pos_args[1].done = 0;
2702 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2703 pos_args[1].compr = 0;
2704 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2705 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2706 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2707 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2708
2709 if (outinfo->writes_pointsize == true)
2710 pos_args[1].out[0] = psize_value;
2711 if (outinfo->writes_layer == true)
2712 pos_args[1].out[2] = layer_value;
2713 if (outinfo->writes_viewport_index == true) {
2714 if (ctx->options->chip_class >= GFX9) {
2715 /* GFX9 has the layer in out.z[10:0] and the viewport
2716 * index in out.z[19:16].
2717 */
2718 LLVMValueRef v = viewport_value;
2719 v = ac_to_integer(&ctx->ac, v);
2720 v = LLVMBuildShl(ctx->ac.builder, v,
2721 LLVMConstInt(ctx->ac.i32, 16, false),
2722 "");
2723 v = LLVMBuildOr(ctx->ac.builder, v,
2724 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2725
2726 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2727 pos_args[1].enabled_channels |= 1 << 2;
2728 } else {
2729 pos_args[1].out[3] = viewport_value;
2730 pos_args[1].enabled_channels |= 1 << 3;
2731 }
2732 }
2733 }
2734
2735 for (i = 0; i < 4; i++) {
2736 if (pos_args[i].out[0])
2737 outinfo->pos_exports++;
2738 }
2739
2740 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2741 * Setting valid_mask=1 prevents it and has no other effect.
2742 */
2743 if (ctx->ac.family == CHIP_NAVI10 ||
2744 ctx->ac.family == CHIP_NAVI12 ||
2745 ctx->ac.family == CHIP_NAVI14)
2746 pos_args[0].valid_mask = 1;
2747
2748 pos_idx = 0;
2749 for (i = 0; i < 4; i++) {
2750 if (!pos_args[i].out[0])
2751 continue;
2752
2753 /* Specify the target we are exporting */
2754 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2755
2756 if (pos_idx == outinfo->pos_exports)
2757 /* Specify that this is the last export */
2758 pos_args[i].done = 1;
2759
2760 ac_build_export(&ctx->ac, &pos_args[i]);
2761 }
2762
2763 /* Build parameter exports */
2764 radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
2765 }
2766
2767 static void
2768 handle_vs_outputs_post(struct radv_shader_context *ctx,
2769 bool export_prim_id,
2770 bool export_clip_dists,
2771 struct radv_vs_output_info *outinfo)
2772 {
2773 struct radv_shader_output_values *outputs;
2774 unsigned noutput = 0;
2775
2776 if (ctx->options->key.has_multiview_view_index) {
2777 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2778 if(!*tmp_out) {
2779 for(unsigned i = 0; i < 4; ++i)
2780 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2781 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2782 }
2783
2784 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2785 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2786 }
2787
2788 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2789 sizeof(outinfo->vs_output_param_offset));
2790 outinfo->pos_exports = 0;
2791
2792 if (!ctx->options->use_ngg_streamout &&
2793 ctx->shader_info->so.num_outputs &&
2794 !ctx->is_gs_copy_shader) {
2795 /* The GS copy shader emission already emits streamout. */
2796 radv_emit_streamout(ctx, 0);
2797 }
2798
2799 /* Allocate a temporary array for the output values. */
2800 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
2801 outputs = malloc(num_outputs * sizeof(outputs[0]));
2802
2803 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2804 if (!(ctx->output_mask & (1ull << i)))
2805 continue;
2806
2807 outputs[noutput].slot_name = i;
2808 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2809
2810 if (ctx->stage == MESA_SHADER_VERTEX &&
2811 !ctx->is_gs_copy_shader) {
2812 outputs[noutput].usage_mask =
2813 ctx->shader_info->vs.output_usage_mask[i];
2814 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2815 outputs[noutput].usage_mask =
2816 ctx->shader_info->tes.output_usage_mask[i];
2817 } else {
2818 assert(ctx->is_gs_copy_shader);
2819 outputs[noutput].usage_mask =
2820 ctx->shader_info->gs.output_usage_mask[i];
2821 }
2822
2823 for (unsigned j = 0; j < 4; j++) {
2824 outputs[noutput].values[j] =
2825 ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2826 }
2827
2828 noutput++;
2829 }
2830
2831 /* Export PrimitiveID. */
2832 if (export_prim_id) {
2833 outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
2834 outputs[noutput].slot_index = 0;
2835 outputs[noutput].usage_mask = 0x1;
2836 outputs[noutput].values[0] = ctx->vs_prim_id;
2837 for (unsigned j = 1; j < 4; j++)
2838 outputs[noutput].values[j] = ctx->ac.f32_0;
2839 noutput++;
2840 }
2841
2842 radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
2843
2844 free(outputs);
2845 }
2846
2847 static void
2848 handle_es_outputs_post(struct radv_shader_context *ctx,
2849 struct radv_es_output_info *outinfo)
2850 {
2851 int j;
2852 LLVMValueRef lds_base = NULL;
2853
2854 if (ctx->ac.chip_class >= GFX9) {
2855 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2856 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2857 LLVMValueRef wave_idx = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
2858 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2859 LLVMBuildMul(ctx->ac.builder, wave_idx,
2860 LLVMConstInt(ctx->ac.i32,
2861 ctx->ac.wave_size, false), ""), "");
2862 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2863 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2864 }
2865
2866 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2867 LLVMValueRef dw_addr = NULL;
2868 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2869 unsigned output_usage_mask;
2870 int param_index;
2871
2872 if (!(ctx->output_mask & (1ull << i)))
2873 continue;
2874
2875 if (ctx->stage == MESA_SHADER_VERTEX) {
2876 output_usage_mask =
2877 ctx->shader_info->vs.output_usage_mask[i];
2878 } else {
2879 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2880 output_usage_mask =
2881 ctx->shader_info->tes.output_usage_mask[i];
2882 }
2883
2884 param_index = shader_io_get_unique_index(i);
2885
2886 if (lds_base) {
2887 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2888 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2889 "");
2890 }
2891
2892 for (j = 0; j < 4; j++) {
2893 if (!(output_usage_mask & (1 << j)))
2894 continue;
2895
2896 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2897 out_val = ac_to_integer(&ctx->ac, out_val);
2898 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2899
2900 if (ctx->ac.chip_class >= GFX9) {
2901 LLVMValueRef dw_addr_offset =
2902 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2903 LLVMConstInt(ctx->ac.i32,
2904 j, false), "");
2905
2906 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2907 } else {
2908 ac_build_buffer_store_dword(&ctx->ac,
2909 ctx->esgs_ring,
2910 out_val, 1,
2911 NULL, ctx->es2gs_offset,
2912 (4 * param_index + j) * 4,
2913 ac_glc | ac_slc, true);
2914 }
2915 }
2916 }
2917 }
2918
2919 static void
2920 handle_ls_outputs_post(struct radv_shader_context *ctx)
2921 {
2922 LLVMValueRef vertex_id = ctx->rel_auto_id;
2923 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->vs.ls_outputs_written);
2924 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2925 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2926 vertex_dw_stride, "");
2927
2928 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2929 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2930
2931 if (!(ctx->output_mask & (1ull << i)))
2932 continue;
2933
2934 int param = shader_io_get_unique_index(i);
2935 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2936 LLVMConstInt(ctx->ac.i32, param * 4, false),
2937 "");
2938 for (unsigned j = 0; j < 4; j++) {
2939 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2940 value = ac_to_integer(&ctx->ac, value);
2941 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2942 ac_lds_store(&ctx->ac, dw_addr, value);
2943 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2944 }
2945 }
2946 }
2947
2948 static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
2949 {
2950 return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
2951 }
2952
2953 static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
2954 {
2955 return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 28, 4);
2956 }
2957
2958 static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
2959 {
2960 LLVMBuilderRef builder = ctx->ac.builder;
2961 LLVMValueRef tmp;
2962 tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
2963 LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
2964 return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
2965 }
2966
2967 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
2968 {
2969 return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
2970 LLVMConstInt(ctx->ac.i32, 12, false),
2971 LLVMConstInt(ctx->ac.i32, 9, false),
2972 false);
2973 }
2974
2975 static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
2976 {
2977 return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
2978 LLVMConstInt(ctx->ac.i32, 22, false),
2979 LLVMConstInt(ctx->ac.i32, 9, false),
2980 false);
2981 }
2982
2983 static LLVMValueRef
2984 ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
2985 {
2986 unsigned num_outputs = util_bitcount64(ctx->output_mask);
2987
2988 if (ctx->options->key.has_multiview_view_index)
2989 num_outputs++;
2990
2991 LLVMTypeRef elements[2] = {
2992 LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
2993 LLVMArrayType(ctx->ac.i8, 4),
2994 };
2995 LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
2996 type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
2997 return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
2998 }
2999
3000 /**
3001 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
3002 * is in emit order; that is:
3003 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
3004 * - during vertex emit, i.e. while the API GS shader invocation is running,
3005 * N = threadidx * gs_max_out_vertices + emitidx
3006 *
3007 * Goals of the LDS memory layout:
3008 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
3009 * in uniform control flow
3010 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
3011 * culling
3012 * 3. Agnostic to the number of waves (since we don't know it before compiling)
3013 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
3014 * 5. Avoid wasting memory.
3015 *
3016 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
3017 * layout, elimination of bank conflicts requires that each vertex occupy an
3018 * odd number of dwords. We use the additional dword to store the output stream
3019 * index as well as a flag to indicate whether this vertex ends a primitive
3020 * for rasterization.
3021 *
3022 * Swizzling is required to satisfy points 1 and 2 simultaneously.
3023 *
3024 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
3025 * Indices are swizzled in groups of 32, which ensures point 1 without
3026 * disturbing point 2.
3027 *
3028 * \return an LDS pointer to type {[N x i32], [4 x i8]}
3029 */
3030 static LLVMValueRef
3031 ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
3032 {
3033 LLVMBuilderRef builder = ctx->ac.builder;
3034 LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
3035
3036 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
3037 unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
3038 if (write_stride_2exp) {
3039 LLVMValueRef row =
3040 LLVMBuildLShr(builder, vertexidx,
3041 LLVMConstInt(ctx->ac.i32, 5, false), "");
3042 LLVMValueRef swizzle =
3043 LLVMBuildAnd(builder, row,
3044 LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
3045 false), "");
3046 vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
3047 }
3048
3049 return ac_build_gep0(&ctx->ac, storage, vertexidx);
3050 }
3051
3052 static LLVMValueRef
3053 ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
3054 LLVMValueRef emitidx)
3055 {
3056 LLVMBuilderRef builder = ctx->ac.builder;
3057 LLVMValueRef tmp;
3058
3059 tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
3060 tmp = LLVMBuildMul(builder, tmp, gsthread, "");
3061 const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
3062 return ngg_gs_vertex_ptr(ctx, vertexidx);
3063 }
3064
3065 /* Send GS Alloc Req message from the first wave of the group to SPI.
3066 * Message payload is:
3067 * - bits 0..10: vertices in group
3068 * - bits 12..22: primitives in group
3069 */
3070 static void build_sendmsg_gs_alloc_req(struct radv_shader_context *ctx,
3071 LLVMValueRef vtx_cnt,
3072 LLVMValueRef prim_cnt)
3073 {
3074 LLVMBuilderRef builder = ctx->ac.builder;
3075 LLVMValueRef tmp;
3076
3077 tmp = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
3078 ac_build_ifcc(&ctx->ac, tmp, 5020);
3079
3080 tmp = LLVMBuildShl(builder, prim_cnt, LLVMConstInt(ctx->ac.i32, 12, false),"");
3081 tmp = LLVMBuildOr(builder, tmp, vtx_cnt, "");
3082 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_ALLOC_REQ, tmp);
3083
3084 ac_build_endif(&ctx->ac, 5020);
3085 }
3086
3087 struct ngg_prim {
3088 unsigned num_vertices;
3089 LLVMValueRef isnull;
3090 LLVMValueRef index[3];
3091 LLVMValueRef edgeflag[3];
3092 };
3093
3094 static void build_export_prim(struct radv_shader_context *ctx,
3095 const struct ngg_prim *prim)
3096 {
3097 LLVMBuilderRef builder = ctx->ac.builder;
3098 struct ac_export_args args;
3099 LLVMValueRef tmp;
3100
3101 tmp = LLVMBuildZExt(builder, prim->isnull, ctx->ac.i32, "");
3102 args.out[0] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 31, false), "");
3103
3104 for (unsigned i = 0; i < prim->num_vertices; ++i) {
3105 tmp = LLVMBuildShl(builder, prim->index[i],
3106 LLVMConstInt(ctx->ac.i32, 10 * i, false), "");
3107 args.out[0] = LLVMBuildOr(builder, args.out[0], tmp, "");
3108 tmp = LLVMBuildZExt(builder, prim->edgeflag[i], ctx->ac.i32, "");
3109 tmp = LLVMBuildShl(builder, tmp,
3110 LLVMConstInt(ctx->ac.i32, 10 * i + 9, false), "");
3111 args.out[0] = LLVMBuildOr(builder, args.out[0], tmp, "");
3112 }
3113
3114 args.out[0] = LLVMBuildBitCast(builder, args.out[0], ctx->ac.f32, "");
3115 args.out[1] = LLVMGetUndef(ctx->ac.f32);
3116 args.out[2] = LLVMGetUndef(ctx->ac.f32);
3117 args.out[3] = LLVMGetUndef(ctx->ac.f32);
3118
3119 args.target = V_008DFC_SQ_EXP_PRIM;
3120 args.enabled_channels = 1;
3121 args.done = true;
3122 args.valid_mask = false;
3123 args.compr = false;
3124
3125 ac_build_export(&ctx->ac, &args);
3126 }
3127
3128 static void
3129 handle_ngg_outputs_post(struct radv_shader_context *ctx)
3130 {
3131 LLVMBuilderRef builder = ctx->ac.builder;
3132 LLVMValueRef tmp;
3133
3134 assert((ctx->stage == MESA_SHADER_VERTEX ||
3135 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->is_gs_copy_shader);
3136
3137 LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
3138 LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 0, 8);
3139 LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
3140 ac_get_thread_id(&ctx->ac), prims_in_wave, "");
3141 LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
3142 ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
3143 LLVMValueRef vtxindex[] = {
3144 ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[0], 0, 16),
3145 ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[0], 16, 16),
3146 ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[2], 0, 16),
3147 };
3148
3149 /* Determine the number of vertices per primitive. */
3150 unsigned num_vertices;
3151
3152 if (ctx->stage == MESA_SHADER_VERTEX) {
3153 num_vertices = 3; /* TODO: optimize for points & lines */
3154 } else {
3155 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
3156
3157 if (ctx->shader->info.tess.point_mode)
3158 num_vertices = 1;
3159 else if (ctx->shader->info.tess.primitive_mode == GL_ISOLINES)
3160 num_vertices = 2;
3161 else
3162 num_vertices = 3;
3163 }
3164
3165 /* TODO: streamout */
3166
3167 /* Copy Primitive IDs from GS threads to the LDS address corresponding
3168 * to the ES thread of the provoking vertex.
3169 */
3170 if (ctx->stage == MESA_SHADER_VERTEX &&
3171 ctx->options->key.vs_common_out.export_prim_id) {
3172 /* TODO: streamout */
3173
3174 ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
3175 /* Extract the PROVOKING_VTX_INDEX field. */
3176 LLVMValueRef provoking_vtx_in_prim =
3177 LLVMConstInt(ctx->ac.i32, 0, false);
3178
3179 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
3180 LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
3181 LLVMValueRef provoking_vtx_index =
3182 LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
3183
3184 LLVMBuildStore(builder, ctx->abi.gs_prim_id,
3185 ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
3186 ac_build_endif(&ctx->ac, 5400);
3187 }
3188
3189 /* TODO: primitive culling */
3190
3191 build_sendmsg_gs_alloc_req(ctx, ngg_get_vtx_cnt(ctx), ngg_get_prim_cnt(ctx));
3192
3193 /* TODO: streamout queries */
3194 /* Export primitive data to the index buffer. Format is:
3195 * - bits 0..8: index 0
3196 * - bit 9: edge flag 0
3197 * - bits 10..18: index 1
3198 * - bit 19: edge flag 1
3199 * - bits 20..28: index 2
3200 * - bit 29: edge flag 2
3201 * - bit 31: null primitive (skip)
3202 *
3203 * For the first version, we will always build up all three indices
3204 * independent of the primitive type. The additional garbage data
3205 * shouldn't hurt.
3206 *
3207 * TODO: culling depends on the primitive type, so can have some
3208 * interaction here.
3209 */
3210 ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
3211 {
3212 struct ngg_prim prim = {};
3213
3214 prim.num_vertices = num_vertices;
3215 prim.isnull = ctx->ac.i1false;
3216 memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
3217
3218 for (unsigned i = 0; i < num_vertices; ++i) {
3219 tmp = LLVMBuildLShr(builder, ctx->abi.gs_invocation_id,
3220 LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
3221 prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3222 }
3223
3224 build_export_prim(ctx, &prim);
3225 }
3226 ac_build_endif(&ctx->ac, 6001);
3227
3228 /* Export per-vertex data (positions and parameters). */
3229 ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
3230 {
3231 struct radv_vs_output_info *outinfo =
3232 ctx->stage == MESA_SHADER_TESS_EVAL ? &ctx->shader_info->tes.outinfo : &ctx->shader_info->vs.outinfo;
3233
3234 /* Exporting the primitive ID is handled below. */
3235 /* TODO: use the new VS export path */
3236 handle_vs_outputs_post(ctx, false,
3237 ctx->options->key.vs_common_out.export_clip_dists,
3238 outinfo);
3239
3240 if (ctx->options->key.vs_common_out.export_prim_id) {
3241 unsigned param_count = outinfo->param_exports;
3242 LLVMValueRef values[4];
3243
3244 if (ctx->stage == MESA_SHADER_VERTEX) {
3245 /* Wait for GS stores to finish. */
3246 ac_build_s_barrier(&ctx->ac);
3247
3248 tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
3249 get_thread_id_in_tg(ctx));
3250 values[0] = LLVMBuildLoad(builder, tmp, "");
3251 } else {
3252 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
3253 values[0] = ctx->abi.tes_patch_id;
3254 }
3255
3256 values[0] = ac_to_float(&ctx->ac, values[0]);
3257 for (unsigned j = 1; j < 4; j++)
3258 values[j] = ctx->ac.f32_0;
3259
3260 radv_export_param(ctx, param_count, values, 0x1);
3261
3262 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
3263 outinfo->param_exports = param_count;
3264 }
3265 }
3266 ac_build_endif(&ctx->ac, 6002);
3267 }
3268
3269 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
3270 {
3271 /* Zero out the part of LDS scratch that is used to accumulate the
3272 * per-stream generated primitive count.
3273 */
3274 LLVMBuilderRef builder = ctx->ac.builder;
3275 LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
3276 LLVMValueRef tid = get_thread_id_in_tg(ctx);
3277 LLVMBasicBlockRef merge_block;
3278 LLVMValueRef cond;
3279
3280 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
3281 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3282 merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3283
3284 cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
3285 LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
3286 LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
3287
3288 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
3289 LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
3290
3291 LLVMBuildBr(ctx->ac.builder, merge_block);
3292 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
3293
3294 ac_build_s_barrier(&ctx->ac);
3295 }
3296
3297 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
3298 {
3299 LLVMBuilderRef builder = ctx->ac.builder;
3300 LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
3301 LLVMValueRef tmp;
3302
3303 /* Zero out remaining (non-emitted) primitive flags.
3304 *
3305 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3306 * the emit threads via LDS. This is likely worse in the expected
3307 * typical case where each GS thread emits the full set of
3308 * vertices.
3309 */
3310 for (unsigned stream = 0; stream < 4; ++stream) {
3311 unsigned num_components;
3312
3313 num_components =
3314 ctx->shader_info->gs.num_stream_output_components[stream];
3315 if (!num_components)
3316 continue;
3317
3318 const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
3319
3320 ac_build_bgnloop(&ctx->ac, 5100);
3321
3322 const LLVMValueRef vertexidx =
3323 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3324 tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
3325 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3326 ac_build_ifcc(&ctx->ac, tmp, 5101);
3327 ac_build_break(&ctx->ac);
3328 ac_build_endif(&ctx->ac, 5101);
3329
3330 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3331 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3332
3333 tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
3334 LLVMValueRef gep_idx[3] = {
3335 ctx->ac.i32_0, /* implied C-style array */
3336 ctx->ac.i32_1, /* second entry of struct */
3337 LLVMConstInt(ctx->ac.i32, stream, false),
3338 };
3339 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3340 LLVMBuildStore(builder, i8_0, tmp);
3341
3342 ac_build_endloop(&ctx->ac, 5100);
3343 }
3344 }
3345
3346 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
3347 {
3348 const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
3349 LLVMBuilderRef builder = ctx->ac.builder;
3350 LLVMValueRef tmp, tmp2;
3351
3352 ac_build_s_barrier(&ctx->ac);
3353
3354 const LLVMValueRef tid = get_thread_id_in_tg(ctx);
3355 LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
3356
3357 /* TODO: streamout */
3358
3359 /* TODO: culling */
3360
3361 /* Determine vertex liveness. */
3362 LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
3363
3364 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3365 ac_build_ifcc(&ctx->ac, tmp, 5120);
3366 {
3367 for (unsigned i = 0; i < verts_per_prim; ++i) {
3368 const LLVMValueRef primidx =
3369 LLVMBuildAdd(builder, tid,
3370 LLVMConstInt(ctx->ac.i32, i, false), "");
3371
3372 if (i > 0) {
3373 tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
3374 ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
3375 }
3376
3377 /* Load primitive liveness */
3378 tmp = ngg_gs_vertex_ptr(ctx, primidx);
3379 LLVMValueRef gep_idx[3] = {
3380 ctx->ac.i32_0, /* implicit C-style array */
3381 ctx->ac.i32_1, /* second value of struct */
3382 ctx->ac.i32_0, /* stream 0 */
3383 };
3384 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3385 tmp = LLVMBuildLoad(builder, tmp, "");
3386 const LLVMValueRef primlive =
3387 LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3388
3389 tmp = LLVMBuildLoad(builder, vertliveptr, "");
3390 tmp = LLVMBuildOr(builder, tmp, primlive, ""),
3391 LLVMBuildStore(builder, tmp, vertliveptr);
3392
3393 if (i > 0)
3394 ac_build_endif(&ctx->ac, 5121 + i);
3395 }
3396 }
3397 ac_build_endif(&ctx->ac, 5120);
3398
3399 /* Inclusive scan addition across the current wave. */
3400 LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
3401 struct ac_wg_scan vertlive_scan = {};
3402 vertlive_scan.op = nir_op_iadd;
3403 vertlive_scan.enable_reduce = true;
3404 vertlive_scan.enable_exclusive = true;
3405 vertlive_scan.src = vertlive;
3406 vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
3407 vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
3408 vertlive_scan.numwaves = get_tgsize(ctx);
3409 vertlive_scan.maxwaves = 8;
3410
3411 ac_build_wg_scan(&ctx->ac, &vertlive_scan);
3412
3413 /* Skip all exports (including index exports) when possible. At least on
3414 * early gfx10 revisions this is also to avoid hangs.
3415 */
3416 LLVMValueRef have_exports =
3417 LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
3418 num_emit_threads =
3419 LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
3420
3421 /* Allocate export space. Send this message as early as possible, to
3422 * hide the latency of the SQ <-> SPI roundtrip.
3423 *
3424 * Note: We could consider compacting primitives for export as well.
3425 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3426 * prim data per clock and skips null primitives at no additional
3427 * cost. So compacting primitives can only be beneficial when
3428 * there are 4 or more contiguous null primitives in the export
3429 * (in the common case of single-dword prim exports).
3430 */
3431 build_sendmsg_gs_alloc_req(ctx, vertlive_scan.result_reduce, num_emit_threads);
3432
3433 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3434 * of the primitive liveness flags, relying on the fact that each
3435 * threadgroup can have at most 256 threads. */
3436 ac_build_ifcc(&ctx->ac, vertlive, 5130);
3437 {
3438 tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
3439 LLVMValueRef gep_idx[3] = {
3440 ctx->ac.i32_0, /* implicit C-style array */
3441 ctx->ac.i32_1, /* second value of struct */
3442 ctx->ac.i32_1, /* stream 1 */
3443 };
3444 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3445 tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
3446 LLVMBuildStore(builder, tmp2, tmp);
3447 }
3448 ac_build_endif(&ctx->ac, 5130);
3449
3450 ac_build_s_barrier(&ctx->ac);
3451
3452 /* Export primitive data */
3453 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3454 ac_build_ifcc(&ctx->ac, tmp, 5140);
3455 {
3456 struct ngg_prim prim = {};
3457 prim.num_vertices = verts_per_prim;
3458
3459 tmp = ngg_gs_vertex_ptr(ctx, tid);
3460 LLVMValueRef gep_idx[3] = {
3461 ctx->ac.i32_0, /* implicit C-style array */
3462 ctx->ac.i32_1, /* second value of struct */
3463 ctx->ac.i32_0, /* primflag */
3464 };
3465 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3466 tmp = LLVMBuildLoad(builder, tmp, "");
3467 prim.isnull = LLVMBuildICmp(builder, LLVMIntEQ, tmp,
3468 LLVMConstInt(ctx->ac.i8, 0, false), "");
3469
3470 for (unsigned i = 0; i < verts_per_prim; ++i) {
3471 prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
3472 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3473 prim.edgeflag[i] = ctx->ac.i1false;
3474 }
3475
3476 build_export_prim(ctx, &prim);
3477 }
3478 ac_build_endif(&ctx->ac, 5140);
3479
3480 /* Export position and parameter data */
3481 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
3482 ac_build_ifcc(&ctx->ac, tmp, 5145);
3483 {
3484 struct radv_vs_output_info *outinfo = &ctx->shader_info->vs.outinfo;
3485 bool export_view_index = ctx->options->key.has_multiview_view_index;
3486 struct radv_shader_output_values *outputs;
3487 unsigned noutput = 0;
3488
3489 /* Allocate a temporary array for the output values. */
3490 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
3491 outputs = calloc(num_outputs, sizeof(outputs[0]));
3492
3493 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
3494 sizeof(outinfo->vs_output_param_offset));
3495 outinfo->pos_exports = 0;
3496
3497 tmp = ngg_gs_vertex_ptr(ctx, tid);
3498 LLVMValueRef gep_idx[3] = {
3499 ctx->ac.i32_0, /* implicit C-style array */
3500 ctx->ac.i32_1, /* second value of struct */
3501 ctx->ac.i32_1, /* stream 1: source data index */
3502 };
3503 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3504 tmp = LLVMBuildLoad(builder, tmp, "");
3505 tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
3506 const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
3507
3508 unsigned out_idx = 0;
3509 gep_idx[1] = ctx->ac.i32_0;
3510 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3511 unsigned output_usage_mask =
3512 ctx->shader_info->gs.output_usage_mask[i];
3513 int length = util_last_bit(output_usage_mask);
3514
3515 if (!(ctx->output_mask & (1ull << i)))
3516 continue;
3517
3518 outputs[noutput].slot_name = i;
3519 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
3520 outputs[noutput].usage_mask = output_usage_mask;
3521
3522 for (unsigned j = 0; j < length; j++, out_idx++) {
3523 if (!(output_usage_mask & (1 << j)))
3524 continue;
3525
3526 gep_idx[2] = LLVMConstInt(ctx->ac.i32, out_idx, false);
3527 tmp = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
3528 tmp = LLVMBuildLoad(builder, tmp, "");
3529
3530 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3531 if (ac_get_type_size(type) == 2) {
3532 tmp = ac_to_integer(&ctx->ac, tmp);
3533 tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
3534 }
3535
3536 outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
3537 }
3538
3539 for (unsigned j = length; j < 4; j++)
3540 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
3541
3542 noutput++;
3543 }
3544
3545 /* Export ViewIndex. */
3546 if (export_view_index) {
3547 outputs[noutput].slot_name = VARYING_SLOT_LAYER;
3548 outputs[noutput].slot_index = 0;
3549 outputs[noutput].usage_mask = 0x1;
3550 outputs[noutput].values[0] = ac_to_float(&ctx->ac, ctx->abi.view_index);
3551 for (unsigned j = 1; j < 4; j++)
3552 outputs[noutput].values[j] = ctx->ac.f32_0;
3553 noutput++;
3554 }
3555
3556 radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
3557 ctx->options->key.vs_common_out.export_clip_dists);
3558 FREE(outputs);
3559 }
3560 ac_build_endif(&ctx->ac, 5145);
3561 }
3562
3563 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
3564 unsigned stream,
3565 LLVMValueRef *addrs)
3566 {
3567 LLVMBuilderRef builder = ctx->ac.builder;
3568 LLVMValueRef tmp;
3569 const LLVMValueRef vertexidx =
3570 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3571
3572 /* If this thread has already emitted the declared maximum number of
3573 * vertices, skip the write: excessive vertex emissions are not
3574 * supposed to have any effect.
3575 */
3576 const LLVMValueRef can_emit =
3577 LLVMBuildICmp(builder, LLVMIntULT, vertexidx,
3578 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3579 ac_build_kill_if_false(&ctx->ac, can_emit);
3580
3581 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3582 tmp = LLVMBuildSelect(builder, can_emit, tmp, vertexidx, "");
3583 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3584
3585 const LLVMValueRef vertexptr =
3586 ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
3587 unsigned out_idx = 0;
3588 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3589 unsigned output_usage_mask =
3590 ctx->shader_info->gs.output_usage_mask[i];
3591 uint8_t output_stream =
3592 ctx->shader_info->gs.output_streams[i];
3593 LLVMValueRef *out_ptr = &addrs[i * 4];
3594 int length = util_last_bit(output_usage_mask);
3595
3596 if (!(ctx->output_mask & (1ull << i)) ||
3597 output_stream != stream)
3598 continue;
3599
3600 for (unsigned j = 0; j < length; j++, out_idx++) {
3601 if (!(output_usage_mask & (1 << j)))
3602 continue;
3603
3604 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
3605 out_ptr[j], "");
3606 LLVMValueRef gep_idx[3] = {
3607 ctx->ac.i32_0, /* implied C-style array */
3608 ctx->ac.i32_0, /* first entry of struct */
3609 LLVMConstInt(ctx->ac.i32, out_idx, false),
3610 };
3611 LLVMValueRef ptr = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
3612
3613 out_val = ac_to_integer(&ctx->ac, out_val);
3614 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
3615
3616 LLVMBuildStore(builder, out_val, ptr);
3617 }
3618 }
3619 assert(out_idx * 4 <= ctx->shader_info->gs.gsvs_vertex_size);
3620
3621 /* Determine and store whether this vertex completed a primitive. */
3622 const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
3623
3624 tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
3625 const LLVMValueRef iscompleteprim =
3626 LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
3627
3628 tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
3629 LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
3630
3631 LLVMValueRef gep_idx[3] = {
3632 ctx->ac.i32_0, /* implied C-style array */
3633 ctx->ac.i32_1, /* second struct entry */
3634 LLVMConstInt(ctx->ac.i32, stream, false),
3635 };
3636 const LLVMValueRef primflagptr =
3637 LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
3638
3639 tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
3640 LLVMBuildStore(builder, tmp, primflagptr);
3641
3642 tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3643 tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
3644 LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
3645 }
3646
3647 static void
3648 write_tess_factors(struct radv_shader_context *ctx)
3649 {
3650 unsigned stride, outer_comps, inner_comps;
3651 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
3652 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
3653 unsigned tess_inner_index = 0, tess_outer_index;
3654 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
3655 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3656 int i;
3657 ac_emit_barrier(&ctx->ac, ctx->stage);
3658
3659 switch (ctx->options->key.tcs.primitive_mode) {
3660 case GL_ISOLINES:
3661 stride = 2;
3662 outer_comps = 2;
3663 inner_comps = 0;
3664 break;
3665 case GL_TRIANGLES:
3666 stride = 4;
3667 outer_comps = 3;
3668 inner_comps = 1;
3669 break;
3670 case GL_QUADS:
3671 stride = 6;
3672 outer_comps = 4;
3673 inner_comps = 2;
3674 break;
3675 default:
3676 return;
3677 }
3678
3679 ac_build_ifcc(&ctx->ac,
3680 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3681 invocation_id, ctx->ac.i32_0, ""), 6503);
3682
3683 lds_base = get_tcs_out_current_patch_data_offset(ctx);
3684
3685 if (inner_comps) {
3686 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3687 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3688 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3689 }
3690
3691 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3692 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3693 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3694
3695 for (i = 0; i < 4; i++) {
3696 inner[i] = LLVMGetUndef(ctx->ac.i32);
3697 outer[i] = LLVMGetUndef(ctx->ac.i32);
3698 }
3699
3700 // LINES reversal
3701 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
3702 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3703 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3704 ctx->ac.i32_1, "");
3705 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3706 } else {
3707 for (i = 0; i < outer_comps; i++) {
3708 outer[i] = out[i] =
3709 ac_lds_load(&ctx->ac, lds_outer);
3710 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3711 ctx->ac.i32_1, "");
3712 }
3713 for (i = 0; i < inner_comps; i++) {
3714 inner[i] = out[outer_comps+i] =
3715 ac_lds_load(&ctx->ac, lds_inner);
3716 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3717 ctx->ac.i32_1, "");
3718 }
3719 }
3720
3721 /* Convert the outputs to vectors for stores. */
3722 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3723 vec1 = NULL;
3724
3725 if (stride > 4)
3726 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3727
3728
3729 buffer = ctx->hs_ring_tess_factor;
3730 tf_base = ctx->tess_factor_offset;
3731 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3732 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3733 unsigned tf_offset = 0;
3734
3735 if (ctx->options->chip_class <= GFX8) {
3736 ac_build_ifcc(&ctx->ac,
3737 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3738 rel_patch_id, ctx->ac.i32_0, ""), 6504);
3739
3740 /* Store the dynamic HS control word. */
3741 ac_build_buffer_store_dword(&ctx->ac, buffer,
3742 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3743 1, ctx->ac.i32_0, tf_base,
3744 0, ac_glc, false);
3745 tf_offset += 4;
3746
3747 ac_build_endif(&ctx->ac, 6504);
3748 }
3749
3750 /* Store the tessellation factors. */
3751 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3752 MIN2(stride, 4), byteoffset, tf_base,
3753 tf_offset, ac_glc, false);
3754 if (vec1)
3755 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3756 stride - 4, byteoffset, tf_base,
3757 16 + tf_offset, ac_glc, false);
3758
3759 //store to offchip for TES to read - only if TES reads them
3760 if (ctx->options->key.tcs.tes_reads_tess_factors) {
3761 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3762 LLVMValueRef tf_inner_offset;
3763 unsigned param_outer, param_inner;
3764
3765 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3766 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3767 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3768
3769 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3770 util_next_power_of_two(outer_comps));
3771
3772 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3773 outer_comps, tf_outer_offset,
3774 ctx->oc_lds, 0, ac_glc, false);
3775 if (inner_comps) {
3776 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3777 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3778 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3779
3780 inner_vec = inner_comps == 1 ? inner[0] :
3781 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3782 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3783 inner_comps, tf_inner_offset,
3784 ctx->oc_lds, 0, ac_glc, false);
3785 }
3786 }
3787
3788 ac_build_endif(&ctx->ac, 6503);
3789 }
3790
3791 static void
3792 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3793 {
3794 write_tess_factors(ctx);
3795 }
3796
3797 static bool
3798 si_export_mrt_color(struct radv_shader_context *ctx,
3799 LLVMValueRef *color, unsigned index,
3800 struct ac_export_args *args)
3801 {
3802 /* Export */
3803 si_llvm_init_export_args(ctx, color, 0xf,
3804 V_008DFC_SQ_EXP_MRT + index, args);
3805 if (!args->enabled_channels)
3806 return false; /* unnecessary NULL export */
3807
3808 return true;
3809 }
3810
3811 static void
3812 radv_export_mrt_z(struct radv_shader_context *ctx,
3813 LLVMValueRef depth, LLVMValueRef stencil,
3814 LLVMValueRef samplemask)
3815 {
3816 struct ac_export_args args;
3817
3818 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3819
3820 ac_build_export(&ctx->ac, &args);
3821 }
3822
3823 static void
3824 handle_fs_outputs_post(struct radv_shader_context *ctx)
3825 {
3826 unsigned index = 0;
3827 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3828 struct ac_export_args color_args[8];
3829
3830 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3831 LLVMValueRef values[4];
3832
3833 if (!(ctx->output_mask & (1ull << i)))
3834 continue;
3835
3836 if (i < FRAG_RESULT_DATA0)
3837 continue;
3838
3839 for (unsigned j = 0; j < 4; j++)
3840 values[j] = ac_to_float(&ctx->ac,
3841 radv_load_output(ctx, i, j));
3842
3843 bool ret = si_export_mrt_color(ctx, values,
3844 i - FRAG_RESULT_DATA0,
3845 &color_args[index]);
3846 if (ret)
3847 index++;
3848 }
3849
3850 /* Process depth, stencil, samplemask. */
3851 if (ctx->shader_info->ps.writes_z) {
3852 depth = ac_to_float(&ctx->ac,
3853 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3854 }
3855 if (ctx->shader_info->ps.writes_stencil) {
3856 stencil = ac_to_float(&ctx->ac,
3857 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3858 }
3859 if (ctx->shader_info->ps.writes_sample_mask) {
3860 samplemask = ac_to_float(&ctx->ac,
3861 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3862 }
3863
3864 /* Set the DONE bit on last non-null color export only if Z isn't
3865 * exported.
3866 */
3867 if (index > 0 &&
3868 !ctx->shader_info->ps.writes_z &&
3869 !ctx->shader_info->ps.writes_stencil &&
3870 !ctx->shader_info->ps.writes_sample_mask) {
3871 unsigned last = index - 1;
3872
3873 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3874 color_args[last].done = 1; /* DONE bit */
3875 }
3876
3877 /* Export PS outputs. */
3878 for (unsigned i = 0; i < index; i++)
3879 ac_build_export(&ctx->ac, &color_args[i]);
3880
3881 if (depth || stencil || samplemask)
3882 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3883 else if (!index)
3884 ac_build_export_null(&ctx->ac);
3885 }
3886
3887 static void
3888 emit_gs_epilogue(struct radv_shader_context *ctx)
3889 {
3890 if (ctx->options->key.vs_common_out.as_ngg) {
3891 gfx10_ngg_gs_emit_epilogue_1(ctx);
3892 return;
3893 }
3894
3895 if (ctx->ac.chip_class >= GFX10)
3896 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3897
3898 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3899 }
3900
3901 static void
3902 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3903 LLVMValueRef *addrs)
3904 {
3905 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3906
3907 switch (ctx->stage) {
3908 case MESA_SHADER_VERTEX:
3909 if (ctx->options->key.vs_common_out.as_ls)
3910 handle_ls_outputs_post(ctx);
3911 else if (ctx->options->key.vs_common_out.as_es)
3912 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
3913 else if (ctx->options->key.vs_common_out.as_ngg)
3914 break; /* handled outside of the shader body */
3915 else
3916 handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
3917 ctx->options->key.vs_common_out.export_clip_dists,
3918 &ctx->shader_info->vs.outinfo);
3919 break;
3920 case MESA_SHADER_FRAGMENT:
3921 handle_fs_outputs_post(ctx);
3922 break;
3923 case MESA_SHADER_GEOMETRY:
3924 emit_gs_epilogue(ctx);
3925 break;
3926 case MESA_SHADER_TESS_CTRL:
3927 handle_tcs_outputs_post(ctx);
3928 break;
3929 case MESA_SHADER_TESS_EVAL:
3930 if (ctx->options->key.vs_common_out.as_es)
3931 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
3932 else if (ctx->options->key.vs_common_out.as_ngg)
3933 break; /* handled outside of the shader body */
3934 else
3935 handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
3936 ctx->options->key.vs_common_out.export_clip_dists,
3937 &ctx->shader_info->tes.outinfo);
3938 break;
3939 default:
3940 break;
3941 }
3942 }
3943
3944 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3945 LLVMPassManagerRef passmgr,
3946 const struct radv_nir_compiler_options *options)
3947 {
3948 LLVMRunPassManager(passmgr, ctx->ac.module);
3949 LLVMDisposeBuilder(ctx->ac.builder);
3950
3951 ac_llvm_context_dispose(&ctx->ac);
3952 }
3953
3954 static void
3955 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3956 {
3957 struct radv_vs_output_info *outinfo;
3958
3959 switch (ctx->stage) {
3960 case MESA_SHADER_FRAGMENT:
3961 case MESA_SHADER_COMPUTE:
3962 case MESA_SHADER_TESS_CTRL:
3963 case MESA_SHADER_GEOMETRY:
3964 return;
3965 case MESA_SHADER_VERTEX:
3966 if (ctx->options->key.vs_common_out.as_ls ||
3967 ctx->options->key.vs_common_out.as_es)
3968 return;
3969 outinfo = &ctx->shader_info->vs.outinfo;
3970 break;
3971 case MESA_SHADER_TESS_EVAL:
3972 if (ctx->options->key.vs_common_out.as_es)
3973 return;
3974 outinfo = &ctx->shader_info->tes.outinfo;
3975 break;
3976 default:
3977 unreachable("Unhandled shader type");
3978 }
3979
3980 ac_optimize_vs_outputs(&ctx->ac,
3981 ctx->main_function,
3982 outinfo->vs_output_param_offset,
3983 VARYING_SLOT_MAX,
3984 &outinfo->param_exports);
3985 }
3986
3987 static void
3988 ac_setup_rings(struct radv_shader_context *ctx)
3989 {
3990 if (ctx->options->chip_class <= GFX8 &&
3991 (ctx->stage == MESA_SHADER_GEOMETRY ||
3992 ctx->options->key.vs_common_out.as_es || ctx->options->key.vs_common_out.as_es)) {
3993 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3994 : RING_ESGS_VS;
3995 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3996
3997 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3998 ctx->ring_offsets,
3999 offset);
4000 }
4001
4002 if (ctx->is_gs_copy_shader) {
4003 ctx->gsvs_ring[0] =
4004 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
4005 LLVMConstInt(ctx->ac.i32,
4006 RING_GSVS_VS, false));
4007 }
4008
4009 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4010 /* The conceptual layout of the GSVS ring is
4011 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4012 * but the real memory layout is swizzled across
4013 * threads:
4014 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4015 * t16v0c0 ..
4016 * Override the buffer descriptor accordingly.
4017 */
4018 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
4019 uint64_t stream_offset = 0;
4020 unsigned num_records = ctx->ac.wave_size;
4021 LLVMValueRef base_ring;
4022
4023 base_ring =
4024 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
4025 LLVMConstInt(ctx->ac.i32,
4026 RING_GSVS_GS, false));
4027
4028 for (unsigned stream = 0; stream < 4; stream++) {
4029 unsigned num_components, stride;
4030 LLVMValueRef ring, tmp;
4031
4032 num_components =
4033 ctx->shader_info->gs.num_stream_output_components[stream];
4034
4035 if (!num_components)
4036 continue;
4037
4038 stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
4039
4040 /* Limit on the stride field for <= GFX7. */
4041 assert(stride < (1 << 14));
4042
4043 ring = LLVMBuildBitCast(ctx->ac.builder,
4044 base_ring, v2i64, "");
4045 tmp = LLVMBuildExtractElement(ctx->ac.builder,
4046 ring, ctx->ac.i32_0, "");
4047 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
4048 LLVMConstInt(ctx->ac.i64,
4049 stream_offset, 0), "");
4050 ring = LLVMBuildInsertElement(ctx->ac.builder,
4051 ring, tmp, ctx->ac.i32_0, "");
4052
4053 stream_offset += stride * ctx->ac.wave_size;
4054
4055 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
4056 ctx->ac.v4i32, "");
4057
4058 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
4059 ctx->ac.i32_1, "");
4060 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
4061 LLVMConstInt(ctx->ac.i32,
4062 S_008F04_STRIDE(stride), false), "");
4063 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
4064 ctx->ac.i32_1, "");
4065
4066 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
4067 LLVMConstInt(ctx->ac.i32,
4068 num_records, false),
4069 LLVMConstInt(ctx->ac.i32, 2, false), "");
4070
4071 ctx->gsvs_ring[stream] = ring;
4072 }
4073 }
4074
4075 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
4076 ctx->stage == MESA_SHADER_TESS_EVAL) {
4077 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
4078 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
4079 }
4080 }
4081
4082 unsigned
4083 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
4084 gl_shader_stage stage,
4085 const struct nir_shader *nir)
4086 {
4087 const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
4088 return radv_get_max_workgroup_size(chip_class, stage, nir ? nir->info.cs.local_size : backup_sizes);
4089 }
4090
4091 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
4092 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
4093 {
4094 LLVMValueRef count = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
4095 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
4096 ctx->ac.i32_0, "");
4097 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
4098 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
4099 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
4100 }
4101
4102 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
4103 {
4104 for(int i = 5; i >= 0; --i) {
4105 ctx->gs_vtx_offset[i] = ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
4106 (i & 1) * 16, 16);
4107 }
4108
4109 ctx->gs_wave_id = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 16, 8);
4110 }
4111
4112 /* Ensure that the esgs ring is declared.
4113 *
4114 * We declare it with 64KB alignment as a hint that the
4115 * pointer value will always be 0.
4116 */
4117 static void declare_esgs_ring(struct radv_shader_context *ctx)
4118 {
4119 if (ctx->esgs_ring)
4120 return;
4121
4122 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
4123
4124 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
4125 ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
4126 "esgs_ring",
4127 AC_ADDR_SPACE_LDS);
4128 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
4129 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
4130 }
4131
4132 static
4133 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
4134 struct nir_shader *const *shaders,
4135 int shader_count,
4136 struct radv_shader_info *shader_info,
4137 const struct radv_nir_compiler_options *options)
4138 {
4139 struct radv_shader_context ctx = {0};
4140 unsigned i;
4141 ctx.options = options;
4142 ctx.shader_info = shader_info;
4143
4144 enum ac_float_mode float_mode =
4145 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
4146 AC_FLOAT_MODE_DEFAULT;
4147
4148 ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class,
4149 options->family, float_mode, options->wave_size, 64);
4150 ctx.context = ctx.ac.context;
4151
4152 for (i = 0; i < MAX_SETS; i++)
4153 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4154 for (i = 0; i < AC_UD_MAX_UD; i++)
4155 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4156
4157 ctx.max_workgroup_size = 0;
4158 for (int i = 0; i < shader_count; ++i) {
4159 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
4160 radv_nir_get_max_workgroup_size(ctx.options->chip_class,
4161 shaders[i]->info.stage,
4162 shaders[i]));
4163 }
4164
4165 if (ctx.ac.chip_class >= GFX10) {
4166 if (is_pre_gs_stage(shaders[0]->info.stage) &&
4167 options->key.vs_common_out.as_ngg) {
4168 ctx.max_workgroup_size = 128;
4169 }
4170 }
4171
4172 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
4173 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
4174
4175 ctx.abi.inputs = &ctx.inputs[0];
4176 ctx.abi.emit_outputs = handle_shader_outputs_post;
4177 ctx.abi.emit_vertex = visit_emit_vertex;
4178 ctx.abi.load_ubo = radv_load_ubo;
4179 ctx.abi.load_ssbo = radv_load_ssbo;
4180 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
4181 ctx.abi.load_resource = radv_load_resource;
4182 ctx.abi.clamp_shadow_reference = false;
4183 ctx.abi.robust_buffer_access = options->robust_buffer_access;
4184
4185 bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && ctx.options->key.vs_common_out.as_ngg;
4186 if (shader_count >= 2 || is_ngg)
4187 ac_init_exec_full_mask(&ctx.ac);
4188
4189 if (options->has_ls_vgpr_init_bug &&
4190 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
4191 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
4192
4193 for(int i = 0; i < shader_count; ++i) {
4194 ctx.stage = shaders[i]->info.stage;
4195 ctx.shader = shaders[i];
4196 ctx.output_mask = 0;
4197
4198 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
4199 for (int i = 0; i < 4; i++) {
4200 ctx.gs_next_vertex[i] =
4201 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4202 }
4203 if (ctx.options->key.vs_common_out.as_ngg) {
4204 for (unsigned i = 0; i < 4; ++i) {
4205 ctx.gs_curprim_verts[i] =
4206 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4207 ctx.gs_generated_prims[i] =
4208 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4209 }
4210
4211 unsigned scratch_size = 8;
4212 if (ctx.shader_info->so.num_outputs)
4213 scratch_size = 44;
4214
4215 LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, scratch_size);
4216 ctx.gs_ngg_scratch =
4217 LLVMAddGlobalInAddressSpace(ctx.ac.module,
4218 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4219 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
4220 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4221
4222 ctx.gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4223 LLVMArrayType(ctx.ac.i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
4224 LLVMSetLinkage(ctx.gs_ngg_emit, LLVMExternalLinkage);
4225 LLVMSetAlignment(ctx.gs_ngg_emit, 4);
4226 }
4227
4228 ctx.abi.load_inputs = load_gs_input;
4229 ctx.abi.emit_primitive = visit_end_primitive;
4230 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4231 ctx.abi.load_tess_varyings = load_tcs_varyings;
4232 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4233 ctx.abi.store_tcs_outputs = store_tcs_output;
4234 if (shader_count == 1)
4235 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
4236 else
4237 ctx.tcs_num_inputs = util_last_bit64(shader_info->vs.ls_outputs_written);
4238 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
4239 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
4240 ctx.abi.load_tess_varyings = load_tes_input;
4241 ctx.abi.load_tess_coord = load_tess_coord;
4242 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4243 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
4244 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
4245 ctx.abi.load_base_vertex = radv_load_base_vertex;
4246 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
4247 ctx.abi.load_sample_position = load_sample_position;
4248 ctx.abi.load_sample_mask_in = load_sample_mask_in;
4249 ctx.abi.emit_kill = radv_emit_kill;
4250 }
4251
4252 if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
4253 ctx.options->key.vs_common_out.as_ngg &&
4254 ctx.options->key.vs_common_out.export_prim_id) {
4255 declare_esgs_ring(&ctx);
4256 }
4257
4258 bool nested_barrier = false;
4259
4260 if (i) {
4261 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4262 ctx.options->key.vs_common_out.as_ngg) {
4263 gfx10_ngg_gs_emit_prologue(&ctx);
4264 nested_barrier = false;
4265 } else {
4266 nested_barrier = true;
4267 }
4268 }
4269
4270 if (nested_barrier) {
4271 /* Execute a barrier before the second shader in
4272 * a merged shader.
4273 *
4274 * Execute the barrier inside the conditional block,
4275 * so that empty waves can jump directly to s_endpgm,
4276 * which will also signal the barrier.
4277 *
4278 * This is possible in gfx9, because an empty wave
4279 * for the second shader does not participate in
4280 * the epilogue. With NGG, empty waves may still
4281 * be required to export data (e.g. GS output vertices),
4282 * so we cannot let them exit early.
4283 *
4284 * If the shader is TCS and the TCS epilog is present
4285 * and contains a barrier, it will wait there and then
4286 * reach s_endpgm.
4287 */
4288 ac_emit_barrier(&ctx.ac, ctx.stage);
4289 }
4290
4291 nir_foreach_variable(variable, &shaders[i]->outputs)
4292 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
4293
4294 ac_setup_rings(&ctx);
4295
4296 LLVMBasicBlockRef merge_block;
4297 if (shader_count >= 2 || is_ngg) {
4298 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
4299 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4300 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4301
4302 LLVMValueRef count = ac_unpack_param(&ctx.ac, ctx.merged_wave_info, 8 * i, 8);
4303 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
4304 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
4305 thread_id, count, "");
4306 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
4307
4308 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
4309 }
4310
4311 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
4312 prepare_interp_optimize(&ctx, shaders[i]);
4313 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
4314 handle_vs_inputs(&ctx, shaders[i]);
4315 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
4316 prepare_gs_input_vgprs(&ctx);
4317
4318 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
4319
4320 if (shader_count >= 2 || is_ngg) {
4321 LLVMBuildBr(ctx.ac.builder, merge_block);
4322 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
4323 }
4324
4325 /* This needs to be outside the if wrapping the shader body, as sometimes
4326 * the HW generates waves with 0 es/vs threads. */
4327 if (is_pre_gs_stage(shaders[i]->info.stage) &&
4328 ctx.options->key.vs_common_out.as_ngg &&
4329 i == shader_count - 1) {
4330 handle_ngg_outputs_post(&ctx);
4331 } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4332 ctx.options->key.vs_common_out.as_ngg) {
4333 gfx10_ngg_gs_emit_epilogue_2(&ctx);
4334 }
4335
4336 if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4337 shader_info->tcs.num_patches = ctx.tcs_num_patches;
4338 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
4339 }
4340 }
4341
4342 LLVMBuildRetVoid(ctx.ac.builder);
4343
4344 if (options->dump_preoptir) {
4345 fprintf(stderr, "%s LLVM IR:\n\n",
4346 radv_get_shader_name(shader_info,
4347 shaders[shader_count - 1]->info.stage));
4348 ac_dump_module(ctx.ac.module);
4349 fprintf(stderr, "\n");
4350 }
4351
4352 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
4353
4354 if (shader_count == 1)
4355 ac_nir_eliminate_const_vs_outputs(&ctx);
4356
4357 if (options->dump_shader) {
4358 ctx.shader_info->private_mem_vgprs =
4359 ac_count_scratch_private_memory(ctx.main_function);
4360 }
4361
4362 return ctx.ac.module;
4363 }
4364
4365 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4366 {
4367 unsigned *retval = (unsigned *)context;
4368 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4369 char *description = LLVMGetDiagInfoDescription(di);
4370
4371 if (severity == LLVMDSError) {
4372 *retval = 1;
4373 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4374 description);
4375 }
4376
4377 LLVMDisposeMessage(description);
4378 }
4379
4380 static unsigned radv_llvm_compile(LLVMModuleRef M,
4381 char **pelf_buffer, size_t *pelf_size,
4382 struct ac_llvm_compiler *ac_llvm)
4383 {
4384 unsigned retval = 0;
4385 LLVMContextRef llvm_ctx;
4386
4387 /* Setup Diagnostic Handler*/
4388 llvm_ctx = LLVMGetModuleContext(M);
4389
4390 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4391 &retval);
4392
4393 /* Compile IR*/
4394 if (!radv_compile_to_elf(ac_llvm, M, pelf_buffer, pelf_size))
4395 retval = 1;
4396 return retval;
4397 }
4398
4399 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
4400 LLVMModuleRef llvm_module,
4401 struct radv_shader_binary **rbinary,
4402 gl_shader_stage stage,
4403 const char *name,
4404 const struct radv_nir_compiler_options *options)
4405 {
4406 char *elf_buffer = NULL;
4407 size_t elf_size = 0;
4408 char *llvm_ir_string = NULL;
4409
4410 if (options->dump_shader) {
4411 fprintf(stderr, "%s LLVM IR:\n\n", name);
4412 ac_dump_module(llvm_module);
4413 fprintf(stderr, "\n");
4414 }
4415
4416 if (options->record_llvm_ir) {
4417 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
4418 llvm_ir_string = strdup(llvm_ir);
4419 LLVMDisposeMessage(llvm_ir);
4420 }
4421
4422 int v = radv_llvm_compile(llvm_module, &elf_buffer, &elf_size, ac_llvm);
4423 if (v) {
4424 fprintf(stderr, "compile failed\n");
4425 }
4426
4427 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4428 LLVMDisposeModule(llvm_module);
4429 LLVMContextDispose(ctx);
4430
4431 size_t llvm_ir_size = llvm_ir_string ? strlen(llvm_ir_string) : 0;
4432 size_t alloc_size = sizeof(struct radv_shader_binary_rtld) + elf_size + llvm_ir_size + 1;
4433 struct radv_shader_binary_rtld *rbin = calloc(1, alloc_size);
4434 memcpy(rbin->data, elf_buffer, elf_size);
4435 if (llvm_ir_string)
4436 memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
4437
4438 rbin->base.type = RADV_BINARY_TYPE_RTLD;
4439 rbin->base.stage = stage;
4440 rbin->base.total_size = alloc_size;
4441 rbin->elf_size = elf_size;
4442 rbin->llvm_ir_size = llvm_ir_size;
4443 *rbinary = &rbin->base;
4444
4445 free(llvm_ir_string);
4446 free(elf_buffer);
4447 }
4448
4449 void
4450 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
4451 struct radv_shader_binary **rbinary,
4452 struct radv_shader_info *shader_info,
4453 struct nir_shader *const *nir,
4454 int nir_count,
4455 const struct radv_nir_compiler_options *options)
4456 {
4457
4458 LLVMModuleRef llvm_module;
4459
4460 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, shader_info,
4461 options);
4462
4463 ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
4464 nir[nir_count - 1]->info.stage,
4465 radv_get_shader_name(shader_info,
4466 nir[nir_count - 1]->info.stage),
4467 options);
4468
4469 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4470 if (options->chip_class >= GFX9) {
4471 if (nir_count == 2 &&
4472 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
4473 shader_info->gs.es_type = nir[0]->info.stage;
4474 }
4475 }
4476 shader_info->wave_size = options->wave_size;
4477 }
4478
4479 static void
4480 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
4481 {
4482 LLVMValueRef vtx_offset =
4483 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
4484 LLVMConstInt(ctx->ac.i32, 4, false), "");
4485 LLVMValueRef stream_id;
4486
4487 /* Fetch the vertex stream ID. */
4488 if (!ctx->options->use_ngg_streamout &&
4489 ctx->shader_info->so.num_outputs) {
4490 stream_id =
4491 ac_unpack_param(&ctx->ac, ctx->streamout_config, 24, 2);
4492 } else {
4493 stream_id = ctx->ac.i32_0;
4494 }
4495
4496 LLVMBasicBlockRef end_bb;
4497 LLVMValueRef switch_inst;
4498
4499 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
4500 ctx->main_function, "end");
4501 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
4502
4503 for (unsigned stream = 0; stream < 4; stream++) {
4504 unsigned num_components =
4505 ctx->shader_info->gs.num_stream_output_components[stream];
4506 LLVMBasicBlockRef bb;
4507 unsigned offset;
4508
4509 if (!num_components)
4510 continue;
4511
4512 if (stream > 0 && !ctx->shader_info->so.num_outputs)
4513 continue;
4514
4515 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
4516 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
4517 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
4518
4519 offset = 0;
4520 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4521 unsigned output_usage_mask =
4522 ctx->shader_info->gs.output_usage_mask[i];
4523 unsigned output_stream =
4524 ctx->shader_info->gs.output_streams[i];
4525 int length = util_last_bit(output_usage_mask);
4526
4527 if (!(ctx->output_mask & (1ull << i)) ||
4528 output_stream != stream)
4529 continue;
4530
4531 for (unsigned j = 0; j < length; j++) {
4532 LLVMValueRef value, soffset;
4533
4534 if (!(output_usage_mask & (1 << j)))
4535 continue;
4536
4537 soffset = LLVMConstInt(ctx->ac.i32,
4538 offset *
4539 ctx->shader->info.gs.vertices_out * 16 * 4, false);
4540
4541 offset++;
4542
4543 value = ac_build_buffer_load(&ctx->ac,
4544 ctx->gsvs_ring[0],
4545 1, ctx->ac.i32_0,
4546 vtx_offset, soffset,
4547 0, ac_glc | ac_slc, true, false);
4548
4549 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4550 if (ac_get_type_size(type) == 2) {
4551 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
4552 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
4553 }
4554
4555 LLVMBuildStore(ctx->ac.builder,
4556 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4557 }
4558 }
4559
4560 if (!ctx->options->use_ngg_streamout &&
4561 ctx->shader_info->so.num_outputs)
4562 radv_emit_streamout(ctx, stream);
4563
4564 if (stream == 0) {
4565 handle_vs_outputs_post(ctx, false, true,
4566 &ctx->shader_info->vs.outinfo);
4567 }
4568
4569 LLVMBuildBr(ctx->ac.builder, end_bb);
4570 }
4571
4572 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
4573 }
4574
4575 void
4576 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
4577 struct nir_shader *geom_shader,
4578 struct radv_shader_binary **rbinary,
4579 struct radv_shader_info *shader_info,
4580 const struct radv_nir_compiler_options *options)
4581 {
4582 struct radv_shader_context ctx = {0};
4583 ctx.options = options;
4584 ctx.shader_info = shader_info;
4585
4586 enum ac_float_mode float_mode =
4587 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
4588 AC_FLOAT_MODE_DEFAULT;
4589
4590 ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class,
4591 options->family, float_mode, 64, 64);
4592 ctx.context = ctx.ac.context;
4593
4594 ctx.is_gs_copy_shader = true;
4595 ctx.stage = MESA_SHADER_VERTEX;
4596 ctx.shader = geom_shader;
4597
4598 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
4599
4600 ac_setup_rings(&ctx);
4601
4602 nir_foreach_variable(variable, &geom_shader->outputs) {
4603 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
4604 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
4605 variable, MESA_SHADER_VERTEX);
4606 }
4607
4608 ac_gs_copy_shader_emit(&ctx);
4609
4610 LLVMBuildRetVoid(ctx.ac.builder);
4611
4612 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
4613
4614 ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
4615 MESA_SHADER_VERTEX, "GS Copy Shader", options);
4616 (*rbinary)->is_gs_copy_shader = true;
4617
4618 }