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amd: join emit_kill() from radv and radeonsi in ac_nir_to_llvm
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
32 #include "nir/nir.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36 #include <llvm-c/Transforms/Scalar.h>
37 #include <llvm-c/Transforms/Utils.h>
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct radv_shader_context {
50 struct ac_llvm_context ac;
51 const struct nir_shader *shader;
52 struct ac_shader_abi abi;
53 const struct radv_shader_args *args;
54
55 gl_shader_stage stage;
56
57 unsigned max_workgroup_size;
58 LLVMContextRef context;
59 LLVMValueRef main_function;
60
61 LLVMValueRef descriptor_sets[MAX_SETS];
62
63 LLVMValueRef ring_offsets;
64
65 LLVMValueRef rel_auto_id;
66
67 LLVMValueRef gs_wave_id;
68 LLVMValueRef gs_vtx_offset[6];
69
70 LLVMValueRef esgs_ring;
71 LLVMValueRef gsvs_ring[4];
72 LLVMValueRef hs_ring_tess_offchip;
73 LLVMValueRef hs_ring_tess_factor;
74
75 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
76
77 uint64_t output_mask;
78
79 LLVMValueRef gs_next_vertex[4];
80 LLVMValueRef gs_curprim_verts[4];
81 LLVMValueRef gs_generated_prims[4];
82 LLVMValueRef gs_ngg_emit;
83 LLVMValueRef gs_ngg_scratch;
84
85 uint32_t tcs_num_inputs;
86 uint32_t tcs_num_patches;
87
88 LLVMValueRef vertexptr; /* GFX10 only */
89 };
90
91 struct radv_shader_output_values {
92 LLVMValueRef values[4];
93 unsigned slot_name;
94 unsigned slot_index;
95 unsigned usage_mask;
96 };
97
98 static inline struct radv_shader_context *
99 radv_shader_context_from_abi(struct ac_shader_abi *abi)
100 {
101 struct radv_shader_context *ctx = NULL;
102 return container_of(abi, ctx, abi);
103 }
104
105 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
106 {
107 switch (ctx->stage) {
108 case MESA_SHADER_TESS_CTRL:
109 return ac_unpack_param(&ctx->ac,
110 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
111 0, 8);
112 case MESA_SHADER_TESS_EVAL:
113 return ac_get_arg(&ctx->ac, ctx->args->tes_rel_patch_id);
114 break;
115 default:
116 unreachable("Illegal stage");
117 }
118 }
119
120 static unsigned
121 get_tcs_num_patches(struct radv_shader_context *ctx)
122 {
123 unsigned num_tcs_input_cp = ctx->args->options->key.tcs.input_vertices;
124 unsigned num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
125 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
126 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
127 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
128 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
129 uint32_t output_vertex_size = num_tcs_outputs * 16;
130 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
131 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
132 unsigned num_patches;
133 unsigned hardware_lds_size;
134
135 /* Ensure that we only need one wave per SIMD so we don't need to check
136 * resource usage. Also ensures that the number of tcs in and out
137 * vertices per threadgroup are at most 256.
138 */
139 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
140 /* Make sure that the data fits in LDS. This assumes the shaders only
141 * use LDS for the inputs and outputs.
142 */
143 hardware_lds_size = 32768;
144
145 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
146 * threadgroup, even though there is more than 32 KiB LDS.
147 *
148 * Test: dEQP-VK.tessellation.shader_input_output.barrier
149 */
150 if (ctx->args->options->chip_class >= GFX7 && ctx->args->options->family != CHIP_STONEY)
151 hardware_lds_size = 65536;
152
153 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
154 /* Make sure the output data fits in the offchip buffer */
155 num_patches = MIN2(num_patches, (ctx->args->options->tess_offchip_block_dw_size * 4) / output_patch_size);
156 /* Not necessary for correctness, but improves performance. The
157 * specific value is taken from the proprietary driver.
158 */
159 num_patches = MIN2(num_patches, 40);
160
161 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
162 if (ctx->args->options->chip_class == GFX6) {
163 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
164 num_patches = MIN2(num_patches, one_wave);
165 }
166 return num_patches;
167 }
168
169 static unsigned
170 calculate_tess_lds_size(struct radv_shader_context *ctx)
171 {
172 unsigned num_tcs_input_cp = ctx->args->options->key.tcs.input_vertices;
173 unsigned num_tcs_output_cp;
174 unsigned num_tcs_outputs, num_tcs_patch_outputs;
175 unsigned input_vertex_size, output_vertex_size;
176 unsigned input_patch_size, output_patch_size;
177 unsigned pervertex_output_patch_size;
178 unsigned output_patch0_offset;
179 unsigned num_patches;
180 unsigned lds_size;
181
182 num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
183 num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
184 num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
185
186 input_vertex_size = ctx->tcs_num_inputs * 16;
187 output_vertex_size = num_tcs_outputs * 16;
188
189 input_patch_size = num_tcs_input_cp * input_vertex_size;
190
191 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
192 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
193
194 num_patches = ctx->tcs_num_patches;
195 output_patch0_offset = input_patch_size * num_patches;
196
197 lds_size = output_patch0_offset + output_patch_size * num_patches;
198 return lds_size;
199 }
200
201 /* Tessellation shaders pass outputs to the next shader using LDS.
202 *
203 * LS outputs = TCS inputs
204 * TCS outputs = TES inputs
205 *
206 * The LDS layout is:
207 * - TCS inputs for patch 0
208 * - TCS inputs for patch 1
209 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
210 * - ...
211 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
212 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
213 * - TCS outputs for patch 1
214 * - Per-patch TCS outputs for patch 1
215 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
216 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
217 * - ...
218 *
219 * All three shaders VS(LS), TCS, TES share the same LDS space.
220 */
221 static LLVMValueRef
222 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
223 {
224 assert(ctx->stage == MESA_SHADER_TESS_CTRL);
225 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
226 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
227
228 input_patch_size /= 4;
229 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
230 }
231
232 static LLVMValueRef
233 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
234 {
235 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
236 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
237 uint32_t output_vertex_size = num_tcs_outputs * 16;
238 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
239 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
240 output_patch_size /= 4;
241 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
242 }
243
244 static LLVMValueRef
245 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
246 {
247 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
248 uint32_t output_vertex_size = num_tcs_outputs * 16;
249 output_vertex_size /= 4;
250 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
251 }
252
253 static LLVMValueRef
254 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
255 {
256 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
257 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
258 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
259 uint32_t output_patch0_offset = input_patch_size;
260 unsigned num_patches = ctx->tcs_num_patches;
261
262 output_patch0_offset *= num_patches;
263 output_patch0_offset /= 4;
264 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
265 }
266
267 static LLVMValueRef
268 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
269 {
270 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
271 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
272 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
273 uint32_t output_patch0_offset = input_patch_size;
274
275 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
276 uint32_t output_vertex_size = num_tcs_outputs * 16;
277 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
278 unsigned num_patches = ctx->tcs_num_patches;
279
280 output_patch0_offset *= num_patches;
281 output_patch0_offset += pervertex_output_patch_size;
282 output_patch0_offset /= 4;
283 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
284 }
285
286 static LLVMValueRef
287 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
288 {
289 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
290 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
291
292 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
293 }
294
295 static LLVMValueRef
296 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
297 {
298 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
299 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
300 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
301
302 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
303 patch0_offset);
304 }
305
306 static LLVMValueRef
307 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
308 {
309 LLVMValueRef patch0_patch_data_offset =
310 get_tcs_out_patch0_patch_data_offset(ctx);
311 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
312 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
313
314 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
315 patch0_patch_data_offset);
316 }
317
318 static LLVMValueRef
319 create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module,
320 LLVMBuilderRef builder,
321 const struct ac_shader_args *args,
322 enum ac_llvm_calling_convention convention,
323 unsigned max_workgroup_size,
324 const struct radv_nir_compiler_options *options)
325 {
326 LLVMValueRef main_function =
327 ac_build_main(args, ctx, convention, "main", ctx->voidt, module);
328
329 if (options->address32_hi) {
330 ac_llvm_add_target_dep_function_attr(main_function,
331 "amdgpu-32bit-address-high-bits",
332 options->address32_hi);
333 }
334
335 ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
336
337 return main_function;
338 }
339
340 static void
341 load_descriptor_sets(struct radv_shader_context *ctx)
342 {
343 uint32_t mask = ctx->args->shader_info->desc_set_used_mask;
344 if (ctx->args->shader_info->need_indirect_descriptor_sets) {
345 LLVMValueRef desc_sets =
346 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[0]);
347 while (mask) {
348 int i = u_bit_scan(&mask);
349
350 ctx->descriptor_sets[i] =
351 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
352 LLVMConstInt(ctx->ac.i32, i, false));
353
354 }
355 } else {
356 while (mask) {
357 int i = u_bit_scan(&mask);
358
359 ctx->descriptor_sets[i] =
360 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[i]);
361 }
362 }
363 }
364
365 static enum ac_llvm_calling_convention
366 get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage)
367 {
368 switch (stage) {
369 case MESA_SHADER_VERTEX:
370 case MESA_SHADER_TESS_EVAL:
371 return AC_LLVM_AMDGPU_VS;
372 break;
373 case MESA_SHADER_GEOMETRY:
374 return AC_LLVM_AMDGPU_GS;
375 break;
376 case MESA_SHADER_TESS_CTRL:
377 return AC_LLVM_AMDGPU_HS;
378 break;
379 case MESA_SHADER_FRAGMENT:
380 return AC_LLVM_AMDGPU_PS;
381 break;
382 case MESA_SHADER_COMPUTE:
383 return AC_LLVM_AMDGPU_CS;
384 break;
385 default:
386 unreachable("Unhandle shader type");
387 }
388 }
389
390 /* Returns whether the stage is a stage that can be directly before the GS */
391 static bool is_pre_gs_stage(gl_shader_stage stage)
392 {
393 return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
394 }
395
396 static void create_function(struct radv_shader_context *ctx,
397 gl_shader_stage stage,
398 bool has_previous_stage)
399 {
400 if (ctx->ac.chip_class >= GFX10) {
401 if (is_pre_gs_stage(stage) && ctx->args->options->key.vs_common_out.as_ngg) {
402 /* On GFX10, VS is merged into GS for NGG. */
403 stage = MESA_SHADER_GEOMETRY;
404 has_previous_stage = true;
405 }
406 }
407
408 ctx->main_function = create_llvm_function(
409 &ctx->ac, ctx->ac.module, ctx->ac.builder, &ctx->args->ac,
410 get_llvm_calling_convention(ctx->main_function, stage),
411 ctx->max_workgroup_size,
412 ctx->args->options);
413
414 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
415 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
416 NULL, 0, AC_FUNC_ATTR_READNONE);
417 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
418 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
419
420 load_descriptor_sets(ctx);
421
422 if (stage == MESA_SHADER_TESS_CTRL ||
423 (stage == MESA_SHADER_VERTEX && ctx->args->options->key.vs_common_out.as_ls) ||
424 /* GFX9 has the ESGS ring buffer in LDS. */
425 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
426 ac_declare_lds_as_pointer(&ctx->ac);
427 }
428
429 }
430
431
432 static LLVMValueRef
433 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
434 unsigned desc_set, unsigned binding)
435 {
436 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
437 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
438 struct radv_pipeline_layout *pipeline_layout = ctx->args->options->layout;
439 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
440 unsigned base_offset = layout->binding[binding].offset;
441 LLVMValueRef offset, stride;
442
443 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
444 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
445 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
446 layout->binding[binding].dynamic_offset_offset;
447 desc_ptr = ac_get_arg(&ctx->ac, ctx->args->ac.push_constants);
448 base_offset = pipeline_layout->push_constant_size + 16 * idx;
449 stride = LLVMConstInt(ctx->ac.i32, 16, false);
450 } else
451 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
452
453 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
454
455 if (layout->binding[binding].type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
456 offset = ac_build_imad(&ctx->ac, index, stride, offset);
457 }
458
459 desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
460 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
461 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
462
463 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
464 uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
465 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
466 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
467 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
468
469 if (ctx->ac.chip_class >= GFX10) {
470 desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
471 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
472 S_008F0C_RESOURCE_LEVEL(1);
473 } else {
474 desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
475 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
476 }
477
478 LLVMValueRef desc_components[4] = {
479 LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
480 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->args->options->address32_hi), false),
481 /* High limit to support variable sizes. */
482 LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
483 LLVMConstInt(ctx->ac.i32, desc_type, false),
484 };
485
486 return ac_build_gather_values(&ctx->ac, desc_components, 4);
487 }
488
489 return desc_ptr;
490 }
491
492
493 /* The offchip buffer layout for TCS->TES is
494 *
495 * - attribute 0 of patch 0 vertex 0
496 * - attribute 0 of patch 0 vertex 1
497 * - attribute 0 of patch 0 vertex 2
498 * ...
499 * - attribute 0 of patch 1 vertex 0
500 * - attribute 0 of patch 1 vertex 1
501 * ...
502 * - attribute 1 of patch 0 vertex 0
503 * - attribute 1 of patch 0 vertex 1
504 * ...
505 * - per patch attribute 0 of patch 0
506 * - per patch attribute 0 of patch 1
507 * ...
508 *
509 * Note that every attribute has 4 components.
510 */
511 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
512 {
513 uint32_t num_patches = ctx->tcs_num_patches;
514 uint32_t num_tcs_outputs;
515 if (ctx->stage == MESA_SHADER_TESS_CTRL)
516 num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
517 else
518 num_tcs_outputs = ctx->args->options->key.tes.tcs_num_outputs;
519
520 uint32_t output_vertex_size = num_tcs_outputs * 16;
521 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
522
523 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
524 }
525
526 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
527 LLVMValueRef vertex_index)
528 {
529 LLVMValueRef param_stride;
530 if (vertex_index)
531 param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
532 else
533 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
534 return param_stride;
535 }
536
537 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
538 LLVMValueRef vertex_index,
539 LLVMValueRef param_index)
540 {
541 LLVMValueRef base_addr;
542 LLVMValueRef param_stride, constant16;
543 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
544 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
545 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
546 param_stride = calc_param_stride(ctx, vertex_index);
547 if (vertex_index) {
548 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
549 vertices_per_patch, vertex_index);
550 } else {
551 base_addr = rel_patch_id;
552 }
553
554 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
555 LLVMBuildMul(ctx->ac.builder, param_index,
556 param_stride, ""), "");
557
558 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
559
560 if (!vertex_index) {
561 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
562
563 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
564 patch_data_offset, "");
565 }
566 return base_addr;
567 }
568
569 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
570 unsigned param,
571 unsigned const_index,
572 bool is_compact,
573 LLVMValueRef vertex_index,
574 LLVMValueRef indir_index)
575 {
576 LLVMValueRef param_index;
577
578 if (indir_index)
579 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
580 indir_index, "");
581 else {
582 if (const_index && !is_compact)
583 param += const_index;
584 param_index = LLVMConstInt(ctx->ac.i32, param, false);
585 }
586 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
587 }
588
589 static LLVMValueRef
590 get_dw_address(struct radv_shader_context *ctx,
591 LLVMValueRef dw_addr,
592 unsigned param,
593 unsigned const_index,
594 bool compact_const_index,
595 LLVMValueRef vertex_index,
596 LLVMValueRef stride,
597 LLVMValueRef indir_index)
598
599 {
600
601 if (vertex_index) {
602 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
603 LLVMBuildMul(ctx->ac.builder,
604 vertex_index,
605 stride, ""), "");
606 }
607
608 if (indir_index)
609 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
610 LLVMBuildMul(ctx->ac.builder, indir_index,
611 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
612 else if (const_index && !compact_const_index)
613 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
614 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
615
616 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
617 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
618
619 if (const_index && compact_const_index)
620 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
621 LLVMConstInt(ctx->ac.i32, const_index, false), "");
622 return dw_addr;
623 }
624
625 static LLVMValueRef
626 load_tcs_varyings(struct ac_shader_abi *abi,
627 LLVMTypeRef type,
628 LLVMValueRef vertex_index,
629 LLVMValueRef indir_index,
630 unsigned const_index,
631 unsigned location,
632 unsigned driver_location,
633 unsigned component,
634 unsigned num_components,
635 bool is_patch,
636 bool is_compact,
637 bool load_input)
638 {
639 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
640 LLVMValueRef dw_addr, stride;
641 LLVMValueRef value[4], result;
642 unsigned param = shader_io_get_unique_index(location);
643
644 if (load_input) {
645 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
646 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
647 dw_addr = get_tcs_in_current_patch_offset(ctx);
648 } else {
649 if (!is_patch) {
650 stride = get_tcs_out_vertex_stride(ctx);
651 dw_addr = get_tcs_out_current_patch_offset(ctx);
652 } else {
653 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
654 stride = NULL;
655 }
656 }
657
658 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
659 indir_index);
660
661 for (unsigned i = 0; i < num_components + component; i++) {
662 value[i] = ac_lds_load(&ctx->ac, dw_addr);
663 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
664 ctx->ac.i32_1, "");
665 }
666 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
667 return result;
668 }
669
670 static void
671 store_tcs_output(struct ac_shader_abi *abi,
672 const nir_variable *var,
673 LLVMValueRef vertex_index,
674 LLVMValueRef param_index,
675 unsigned const_index,
676 LLVMValueRef src,
677 unsigned writemask)
678 {
679 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
680 const unsigned location = var->data.location;
681 unsigned component = var->data.location_frac;
682 const bool is_patch = var->data.patch;
683 const bool is_compact = var->data.compact;
684 LLVMValueRef dw_addr;
685 LLVMValueRef stride = NULL;
686 LLVMValueRef buf_addr = NULL;
687 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
688 unsigned param;
689 bool store_lds = true;
690
691 if (is_patch) {
692 if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
693 store_lds = false;
694 } else {
695 if (!(ctx->shader->info.outputs_read & (1ULL << location)))
696 store_lds = false;
697 }
698
699 param = shader_io_get_unique_index(location);
700 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
701 const_index += component;
702 component = 0;
703
704 if (const_index >= 4) {
705 const_index -= 4;
706 param++;
707 }
708 }
709
710 if (!is_patch) {
711 stride = get_tcs_out_vertex_stride(ctx);
712 dw_addr = get_tcs_out_current_patch_offset(ctx);
713 } else {
714 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
715 }
716
717 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
718 param_index);
719 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
720 vertex_index, param_index);
721
722 bool is_tess_factor = false;
723 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
724 location == VARYING_SLOT_TESS_LEVEL_OUTER)
725 is_tess_factor = true;
726
727 unsigned base = is_compact ? const_index : 0;
728 for (unsigned chan = 0; chan < 8; chan++) {
729 if (!(writemask & (1 << chan)))
730 continue;
731 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
732 value = ac_to_integer(&ctx->ac, value);
733 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
734
735 if (store_lds || is_tess_factor) {
736 LLVMValueRef dw_addr_chan =
737 LLVMBuildAdd(ctx->ac.builder, dw_addr,
738 LLVMConstInt(ctx->ac.i32, chan, false), "");
739 ac_lds_store(&ctx->ac, dw_addr_chan, value);
740 }
741
742 if (!is_tess_factor && writemask != 0xF)
743 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
744 buf_addr, oc_lds,
745 4 * (base + chan), ac_glc);
746 }
747
748 if (writemask == 0xF) {
749 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
750 buf_addr, oc_lds,
751 (base * 4), ac_glc);
752 }
753 }
754
755 static LLVMValueRef
756 load_tes_input(struct ac_shader_abi *abi,
757 LLVMTypeRef type,
758 LLVMValueRef vertex_index,
759 LLVMValueRef param_index,
760 unsigned const_index,
761 unsigned location,
762 unsigned driver_location,
763 unsigned component,
764 unsigned num_components,
765 bool is_patch,
766 bool is_compact,
767 bool load_input)
768 {
769 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
770 LLVMValueRef buf_addr;
771 LLVMValueRef result;
772 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
773 unsigned param = shader_io_get_unique_index(location);
774
775 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
776 const_index += component;
777 component = 0;
778 if (const_index >= 4) {
779 const_index -= 4;
780 param++;
781 }
782 }
783
784 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
785 is_compact, vertex_index, param_index);
786
787 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
788 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
789
790 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
791 buf_addr, oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
792 result = ac_trim_vector(&ctx->ac, result, num_components);
793 return result;
794 }
795
796 static LLVMValueRef
797 radv_emit_fetch_64bit(struct radv_shader_context *ctx,
798 LLVMTypeRef type, LLVMValueRef a, LLVMValueRef b)
799 {
800 LLVMValueRef values[2] = {
801 ac_to_integer(&ctx->ac, a),
802 ac_to_integer(&ctx->ac, b),
803 };
804 LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
805 return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
806 }
807
808 static LLVMValueRef
809 load_gs_input(struct ac_shader_abi *abi,
810 unsigned location,
811 unsigned driver_location,
812 unsigned component,
813 unsigned num_components,
814 unsigned vertex_index,
815 unsigned const_index,
816 LLVMTypeRef type)
817 {
818 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
819 LLVMValueRef vtx_offset;
820 unsigned param, vtx_offset_param;
821 LLVMValueRef value[4], result;
822
823 vtx_offset_param = vertex_index;
824 assert(vtx_offset_param < 6);
825 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
826 LLVMConstInt(ctx->ac.i32, 4, false), "");
827
828 param = shader_io_get_unique_index(location);
829
830 for (unsigned i = component; i < num_components + component; i++) {
831 if (ctx->ac.chip_class >= GFX9) {
832 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
833 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
834 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
835 value[i] = ac_lds_load(&ctx->ac, dw_addr);
836
837 if (ac_get_type_size(type) == 8) {
838 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
839 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index + 1, 0), "");
840 LLVMValueRef tmp = ac_lds_load(&ctx->ac, dw_addr);
841
842 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
843 }
844 } else {
845 LLVMValueRef soffset =
846 LLVMConstInt(ctx->ac.i32,
847 (param * 4 + i + const_index) * 256,
848 false);
849
850 value[i] = ac_build_buffer_load(&ctx->ac,
851 ctx->esgs_ring, 1,
852 ctx->ac.i32_0,
853 vtx_offset, soffset,
854 0, ac_glc, true, false);
855
856 if (ac_get_type_size(type) == 8) {
857 soffset = LLVMConstInt(ctx->ac.i32,
858 (param * 4 + i + const_index + 1) * 256,
859 false);
860
861 LLVMValueRef tmp =
862 ac_build_buffer_load(&ctx->ac,
863 ctx->esgs_ring, 1,
864 ctx->ac.i32_0,
865 vtx_offset, soffset,
866 0, ac_glc, true, false);
867
868 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
869 }
870 }
871
872 if (ac_get_type_size(type) == 2) {
873 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
874 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
875 }
876 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
877 }
878 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
879 result = ac_to_integer(&ctx->ac, result);
880 return result;
881 }
882
883 static uint32_t
884 radv_get_sample_pos_offset(uint32_t num_samples)
885 {
886 uint32_t sample_pos_offset = 0;
887
888 switch (num_samples) {
889 case 2:
890 sample_pos_offset = 1;
891 break;
892 case 4:
893 sample_pos_offset = 3;
894 break;
895 case 8:
896 sample_pos_offset = 7;
897 break;
898 default:
899 break;
900 }
901 return sample_pos_offset;
902 }
903
904 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
905 LLVMValueRef sample_id)
906 {
907 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
908
909 LLVMValueRef result;
910 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false);
911 LLVMValueRef ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ring_offsets, &index, 1, "");
912
913 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
914 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
915
916 uint32_t sample_pos_offset =
917 radv_get_sample_pos_offset(ctx->args->options->key.fs.num_samples);
918
919 sample_id =
920 LLVMBuildAdd(ctx->ac.builder, sample_id,
921 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
922 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
923
924 return result;
925 }
926
927
928 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
929 {
930 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
931 uint8_t log2_ps_iter_samples;
932
933 if (ctx->args->shader_info->ps.force_persample) {
934 log2_ps_iter_samples =
935 util_logbase2(ctx->args->options->key.fs.num_samples);
936 } else {
937 log2_ps_iter_samples = ctx->args->options->key.fs.log2_ps_iter_samples;
938 }
939
940 /* The bit pattern matches that used by fixed function fragment
941 * processing. */
942 static const uint16_t ps_iter_masks[] = {
943 0xffff, /* not used */
944 0x5555,
945 0x1111,
946 0x0101,
947 0x0001,
948 };
949 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
950
951 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
952
953 LLVMValueRef result, sample_id;
954 sample_id = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.ancillary), 8, 4);
955 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
956 result = LLVMBuildAnd(ctx->ac.builder, sample_id,
957 ac_get_arg(&ctx->ac, ctx->args->ac.sample_coverage), "");
958 return result;
959 }
960
961
962 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
963 unsigned stream,
964 LLVMValueRef *addrs);
965
966 static void
967 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
968 {
969 LLVMValueRef gs_next_vertex;
970 LLVMValueRef can_emit;
971 unsigned offset = 0;
972 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
973
974 if (ctx->args->options->key.vs_common_out.as_ngg) {
975 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
976 return;
977 }
978
979 /* Write vertex attribute values to GSVS ring */
980 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
981 ctx->gs_next_vertex[stream],
982 "");
983
984 /* If this thread has already emitted the declared maximum number of
985 * vertices, don't emit any more: excessive vertex emissions are not
986 * supposed to have any effect.
987 */
988 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
989 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
990
991 bool use_kill = !ctx->args->shader_info->gs.writes_memory;
992 if (use_kill)
993 ac_build_kill_if_false(&ctx->ac, can_emit);
994 else
995 ac_build_ifcc(&ctx->ac, can_emit, 6505);
996
997 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
998 unsigned output_usage_mask =
999 ctx->args->shader_info->gs.output_usage_mask[i];
1000 uint8_t output_stream =
1001 ctx->args->shader_info->gs.output_streams[i];
1002 LLVMValueRef *out_ptr = &addrs[i * 4];
1003 int length = util_last_bit(output_usage_mask);
1004
1005 if (!(ctx->output_mask & (1ull << i)) ||
1006 output_stream != stream)
1007 continue;
1008
1009 for (unsigned j = 0; j < length; j++) {
1010 if (!(output_usage_mask & (1 << j)))
1011 continue;
1012
1013 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1014 out_ptr[j], "");
1015 LLVMValueRef voffset =
1016 LLVMConstInt(ctx->ac.i32, offset *
1017 ctx->shader->info.gs.vertices_out, false);
1018
1019 offset++;
1020
1021 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1022 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1023
1024 out_val = ac_to_integer(&ctx->ac, out_val);
1025 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1026
1027 ac_build_buffer_store_dword(&ctx->ac,
1028 ctx->gsvs_ring[stream],
1029 out_val, 1,
1030 voffset,
1031 ac_get_arg(&ctx->ac,
1032 ctx->args->gs2vs_offset),
1033 0, ac_glc | ac_slc | ac_swizzled);
1034 }
1035 }
1036
1037 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1038 ctx->ac.i32_1, "");
1039 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
1040
1041 ac_build_sendmsg(&ctx->ac,
1042 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
1043 ctx->gs_wave_id);
1044
1045 if (!use_kill)
1046 ac_build_endif(&ctx->ac, 6505);
1047 }
1048
1049 static void
1050 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1051 {
1052 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1053
1054 if (ctx->args->options->key.vs_common_out.as_ngg) {
1055 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
1056 return;
1057 }
1058
1059 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1060 }
1061
1062 static LLVMValueRef
1063 load_tess_coord(struct ac_shader_abi *abi)
1064 {
1065 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1066
1067 LLVMValueRef coord[4] = {
1068 ac_get_arg(&ctx->ac, ctx->args->tes_u),
1069 ac_get_arg(&ctx->ac, ctx->args->tes_v),
1070 ctx->ac.f32_0,
1071 ctx->ac.f32_0,
1072 };
1073
1074 if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
1075 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1076 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1077
1078 return ac_build_gather_values(&ctx->ac, coord, 3);
1079 }
1080
1081 static LLVMValueRef
1082 load_patch_vertices_in(struct ac_shader_abi *abi)
1083 {
1084 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1085 return LLVMConstInt(ctx->ac.i32, ctx->args->options->key.tcs.input_vertices, false);
1086 }
1087
1088
1089 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1090 {
1091 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1092 return ac_get_arg(&ctx->ac, ctx->args->ac.base_vertex);
1093 }
1094
1095 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1096 LLVMValueRef buffer_ptr, bool write)
1097 {
1098 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1099 LLVMValueRef result;
1100
1101 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1102
1103 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1104 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1105
1106 return result;
1107 }
1108
1109 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1110 {
1111 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1112 LLVMValueRef result;
1113
1114 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr)) != LLVMPointerTypeKind) {
1115 /* Do not load the descriptor for inlined uniform blocks. */
1116 return buffer_ptr;
1117 }
1118
1119 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1120
1121 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1122 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1123
1124 return result;
1125 }
1126
1127 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1128 unsigned descriptor_set,
1129 unsigned base_index,
1130 unsigned constant_index,
1131 LLVMValueRef index,
1132 enum ac_descriptor_type desc_type,
1133 bool image, bool write,
1134 bool bindless)
1135 {
1136 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1137 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1138 struct radv_descriptor_set_layout *layout = ctx->args->options->layout->set[descriptor_set].layout;
1139 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1140 unsigned offset = binding->offset;
1141 unsigned stride = binding->size;
1142 unsigned type_size;
1143 LLVMBuilderRef builder = ctx->ac.builder;
1144 LLVMTypeRef type;
1145
1146 assert(base_index < layout->binding_count);
1147
1148 switch (desc_type) {
1149 case AC_DESC_IMAGE:
1150 type = ctx->ac.v8i32;
1151 type_size = 32;
1152 break;
1153 case AC_DESC_FMASK:
1154 type = ctx->ac.v8i32;
1155 offset += 32;
1156 type_size = 32;
1157 break;
1158 case AC_DESC_SAMPLER:
1159 type = ctx->ac.v4i32;
1160 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
1161 offset += radv_combined_image_descriptor_sampler_offset(binding);
1162 }
1163
1164 type_size = 16;
1165 break;
1166 case AC_DESC_BUFFER:
1167 type = ctx->ac.v4i32;
1168 type_size = 16;
1169 break;
1170 case AC_DESC_PLANE_0:
1171 case AC_DESC_PLANE_1:
1172 case AC_DESC_PLANE_2:
1173 type = ctx->ac.v8i32;
1174 type_size = 32;
1175 offset += 32 * (desc_type - AC_DESC_PLANE_0);
1176 break;
1177 default:
1178 unreachable("invalid desc_type\n");
1179 }
1180
1181 offset += constant_index * stride;
1182
1183 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1184 (!index || binding->immutable_samplers_equal)) {
1185 if (binding->immutable_samplers_equal)
1186 constant_index = 0;
1187
1188 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1189
1190 LLVMValueRef constants[] = {
1191 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1192 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1193 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1194 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1195 };
1196 return ac_build_gather_values(&ctx->ac, constants, 4);
1197 }
1198
1199 assert(stride % type_size == 0);
1200
1201 LLVMValueRef adjusted_index = index;
1202 if (!adjusted_index)
1203 adjusted_index = ctx->ac.i32_0;
1204
1205 adjusted_index = LLVMBuildMul(builder, adjusted_index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1206
1207 LLVMValueRef val_offset = LLVMConstInt(ctx->ac.i32, offset, 0);
1208 list = LLVMBuildGEP(builder, list, &val_offset, 1, "");
1209 list = LLVMBuildPointerCast(builder, list,
1210 ac_array_in_const32_addr_space(type), "");
1211
1212 LLVMValueRef descriptor = ac_build_load_to_sgpr(&ctx->ac, list, adjusted_index);
1213
1214 /* 3 plane formats always have same size and format for plane 1 & 2, so
1215 * use the tail from plane 1 so that we can store only the first 16 bytes
1216 * of the last plane. */
1217 if (desc_type == AC_DESC_PLANE_2) {
1218 LLVMValueRef descriptor2 = radv_get_sampler_desc(abi, descriptor_set, base_index, constant_index, index, AC_DESC_PLANE_1,image, write, bindless);
1219
1220 LLVMValueRef components[8];
1221 for (unsigned i = 0; i < 4; ++i)
1222 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor, i);
1223
1224 for (unsigned i = 4; i < 8; ++i)
1225 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor2, i);
1226 descriptor = ac_build_gather_values(&ctx->ac, components, 8);
1227 }
1228
1229 return descriptor;
1230 }
1231
1232 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1233 * so we may need to fix it up. */
1234 static LLVMValueRef
1235 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1236 unsigned adjustment,
1237 LLVMValueRef alpha)
1238 {
1239 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1240 return alpha;
1241
1242 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1243
1244 alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
1245
1246 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1247 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1248 else
1249 alpha = ac_to_integer(&ctx->ac, alpha);
1250
1251 /* For the integer-like cases, do a natural sign extension.
1252 *
1253 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1254 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1255 * exponent.
1256 */
1257 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1258 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1259 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1260 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1261
1262 /* Convert back to the right type. */
1263 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1264 LLVMValueRef clamp;
1265 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1266 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1267 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1268 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1269 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1270 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1271 }
1272
1273 return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
1274 }
1275
1276 static LLVMValueRef
1277 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
1278 LLVMValueRef value,
1279 unsigned num_channels,
1280 bool is_float)
1281 {
1282 LLVMValueRef zero = is_float ? ctx->ac.f32_0 : ctx->ac.i32_0;
1283 LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
1284 LLVMValueRef chan[4];
1285
1286 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
1287 unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
1288
1289 if (num_channels == 4 && num_channels == vec_size)
1290 return value;
1291
1292 num_channels = MIN2(num_channels, vec_size);
1293
1294 for (unsigned i = 0; i < num_channels; i++)
1295 chan[i] = ac_llvm_extract_elem(&ctx->ac, value, i);
1296 } else {
1297 assert(num_channels == 1);
1298 chan[0] = value;
1299 }
1300
1301 for (unsigned i = num_channels; i < 4; i++) {
1302 chan[i] = i == 3 ? one : zero;
1303 chan[i] = ac_to_integer(&ctx->ac, chan[i]);
1304 }
1305
1306 return ac_build_gather_values(&ctx->ac, chan, 4);
1307 }
1308
1309 static void
1310 handle_vs_input_decl(struct radv_shader_context *ctx,
1311 struct nir_variable *variable)
1312 {
1313 LLVMValueRef t_list_ptr = ac_get_arg(&ctx->ac, ctx->args->vertex_buffers);
1314 LLVMValueRef t_offset;
1315 LLVMValueRef t_list;
1316 LLVMValueRef input;
1317 LLVMValueRef buffer_index;
1318 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1319 uint8_t input_usage_mask =
1320 ctx->args->shader_info->vs.input_usage_mask[variable->data.location];
1321 unsigned num_input_channels = util_last_bit(input_usage_mask);
1322
1323 variable->data.driver_location = variable->data.location * 4;
1324
1325 enum glsl_base_type type = glsl_get_base_type(variable->type);
1326 for (unsigned i = 0; i < attrib_count; ++i) {
1327 LLVMValueRef output[4];
1328 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1329 unsigned attrib_format = ctx->args->options->key.vs.vertex_attribute_formats[attrib_index];
1330 unsigned data_format = attrib_format & 0x0f;
1331 unsigned num_format = (attrib_format >> 4) & 0x07;
1332 bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
1333 num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
1334
1335 if (ctx->args->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1336 uint32_t divisor = ctx->args->options->key.vs.instance_rate_divisors[attrib_index];
1337
1338 if (divisor) {
1339 buffer_index = ctx->abi.instance_id;
1340
1341 if (divisor != 1) {
1342 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1343 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1344 }
1345 } else {
1346 buffer_index = ctx->ac.i32_0;
1347 }
1348
1349 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1350 ac_get_arg(&ctx->ac,
1351 ctx->args->ac.start_instance),\
1352 buffer_index, "");
1353 } else {
1354 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1355 ctx->abi.vertex_id,
1356 ac_get_arg(&ctx->ac,
1357 ctx->args->ac.base_vertex), "");
1358 }
1359
1360 const struct ac_data_format_info *vtx_info = ac_get_data_format_info(data_format);
1361
1362 /* Adjust the number of channels to load based on the vertex
1363 * attribute format.
1364 */
1365 unsigned num_channels = MIN2(num_input_channels, vtx_info->num_channels);
1366 unsigned attrib_binding = ctx->args->options->key.vs.vertex_attribute_bindings[attrib_index];
1367 unsigned attrib_offset = ctx->args->options->key.vs.vertex_attribute_offsets[attrib_index];
1368 unsigned attrib_stride = ctx->args->options->key.vs.vertex_attribute_strides[attrib_index];
1369
1370 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1371 /* Always load, at least, 3 channels for formats that
1372 * need to be shuffled because X<->Z.
1373 */
1374 num_channels = MAX2(num_channels, 3);
1375 }
1376
1377 t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false);
1378 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1379
1380 /* Perform per-channel vertex fetch operations if unaligned
1381 * access are detected. Only GFX6 and GFX10 are affected.
1382 */
1383 bool unaligned_vertex_fetches = false;
1384 if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class == GFX10) &&
1385 vtx_info->chan_format != data_format &&
1386 ((attrib_offset % vtx_info->element_size) ||
1387 (attrib_stride % vtx_info->element_size)))
1388 unaligned_vertex_fetches = true;
1389
1390 if (unaligned_vertex_fetches) {
1391 unsigned chan_format = vtx_info->chan_format;
1392 LLVMValueRef values[4];
1393
1394 assert(ctx->ac.chip_class == GFX6 ||
1395 ctx->ac.chip_class == GFX10);
1396
1397 for (unsigned chan = 0; chan < num_channels; chan++) {
1398 unsigned chan_offset = attrib_offset + chan * vtx_info->chan_byte_size;
1399 LLVMValueRef chan_index = buffer_index;
1400
1401 if (attrib_stride != 0 && chan_offset > attrib_stride) {
1402 LLVMValueRef buffer_offset =
1403 LLVMConstInt(ctx->ac.i32,
1404 chan_offset / attrib_stride, false);
1405
1406 chan_index = LLVMBuildAdd(ctx->ac.builder,
1407 buffer_index,
1408 buffer_offset, "");
1409
1410 chan_offset = chan_offset % attrib_stride;
1411 }
1412
1413 values[chan] = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1414 chan_index,
1415 LLVMConstInt(ctx->ac.i32, chan_offset, false),
1416 ctx->ac.i32_0, ctx->ac.i32_0, 1,
1417 chan_format, num_format, 0, true);
1418 }
1419
1420 input = ac_build_gather_values(&ctx->ac, values, num_channels);
1421 } else {
1422 if (attrib_stride != 0 && attrib_offset > attrib_stride) {
1423 LLVMValueRef buffer_offset =
1424 LLVMConstInt(ctx->ac.i32,
1425 attrib_offset / attrib_stride, false);
1426
1427 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1428 buffer_index,
1429 buffer_offset, "");
1430
1431 attrib_offset = attrib_offset % attrib_stride;
1432 }
1433
1434 input = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1435 buffer_index,
1436 LLVMConstInt(ctx->ac.i32, attrib_offset, false),
1437 ctx->ac.i32_0, ctx->ac.i32_0,
1438 num_channels,
1439 data_format, num_format, 0, true);
1440 }
1441
1442 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1443 LLVMValueRef c[4];
1444 c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
1445 c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
1446 c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
1447 c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
1448
1449 input = ac_build_gather_values(&ctx->ac, c, 4);
1450 }
1451
1452 input = radv_fixup_vertex_input_fetches(ctx, input, num_channels,
1453 is_float);
1454
1455 for (unsigned chan = 0; chan < 4; chan++) {
1456 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1457 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1458 if (type == GLSL_TYPE_FLOAT16) {
1459 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
1460 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
1461 }
1462 }
1463
1464 unsigned alpha_adjust = (ctx->args->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
1465 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
1466
1467 for (unsigned chan = 0; chan < 4; chan++) {
1468 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
1469 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
1470 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
1471
1472 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
1473 }
1474 }
1475 }
1476
1477 static void
1478 handle_vs_inputs(struct radv_shader_context *ctx,
1479 struct nir_shader *nir) {
1480 nir_foreach_variable(variable, &nir->inputs)
1481 handle_vs_input_decl(ctx, variable);
1482 }
1483
1484 static void
1485 prepare_interp_optimize(struct radv_shader_context *ctx,
1486 struct nir_shader *nir)
1487 {
1488 bool uses_center = false;
1489 bool uses_centroid = false;
1490 nir_foreach_variable(variable, &nir->inputs) {
1491 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1492 variable->data.sample)
1493 continue;
1494
1495 if (variable->data.centroid)
1496 uses_centroid = true;
1497 else
1498 uses_center = true;
1499 }
1500
1501 ctx->abi.persp_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.persp_centroid);
1502 ctx->abi.linear_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.linear_centroid);
1503
1504 if (uses_center && uses_centroid) {
1505 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT,
1506 ac_get_arg(&ctx->ac, ctx->args->ac.prim_mask),
1507 ctx->ac.i32_0, "");
1508 ctx->abi.persp_centroid =
1509 LLVMBuildSelect(ctx->ac.builder, sel,
1510 ac_get_arg(&ctx->ac, ctx->args->ac.persp_center),
1511 ctx->abi.persp_centroid, "");
1512 ctx->abi.linear_centroid =
1513 LLVMBuildSelect(ctx->ac.builder, sel,
1514 ac_get_arg(&ctx->ac, ctx->args->ac.linear_center),
1515 ctx->abi.linear_centroid, "");
1516 }
1517 }
1518
1519 static void
1520 scan_shader_output_decl(struct radv_shader_context *ctx,
1521 struct nir_variable *variable,
1522 struct nir_shader *shader,
1523 gl_shader_stage stage)
1524 {
1525 int idx = variable->data.location + variable->data.index;
1526 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1527 uint64_t mask_attribs;
1528
1529 variable->data.driver_location = idx * 4;
1530
1531 /* tess ctrl has it's own load/store paths for outputs */
1532 if (stage == MESA_SHADER_TESS_CTRL)
1533 return;
1534
1535 if (variable->data.compact) {
1536 unsigned component_count = variable->data.location_frac +
1537 glsl_get_length(variable->type);
1538 attrib_count = (component_count + 3) / 4;
1539 }
1540
1541 mask_attribs = ((1ull << attrib_count) - 1) << idx;
1542
1543 ctx->output_mask |= mask_attribs;
1544 }
1545
1546
1547 /* Initialize arguments for the shader export intrinsic */
1548 static void
1549 si_llvm_init_export_args(struct radv_shader_context *ctx,
1550 LLVMValueRef *values,
1551 unsigned enabled_channels,
1552 unsigned target,
1553 struct ac_export_args *args)
1554 {
1555 /* Specify the channels that are enabled. */
1556 args->enabled_channels = enabled_channels;
1557
1558 /* Specify whether the EXEC mask represents the valid mask */
1559 args->valid_mask = 0;
1560
1561 /* Specify whether this is the last export */
1562 args->done = 0;
1563
1564 /* Specify the target we are exporting */
1565 args->target = target;
1566
1567 args->compr = false;
1568 args->out[0] = LLVMGetUndef(ctx->ac.f32);
1569 args->out[1] = LLVMGetUndef(ctx->ac.f32);
1570 args->out[2] = LLVMGetUndef(ctx->ac.f32);
1571 args->out[3] = LLVMGetUndef(ctx->ac.f32);
1572
1573 if (!values)
1574 return;
1575
1576 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
1577 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1578 unsigned index = target - V_008DFC_SQ_EXP_MRT;
1579 unsigned col_format = (ctx->args->options->key.fs.col_format >> (4 * index)) & 0xf;
1580 bool is_int8 = (ctx->args->options->key.fs.is_int8 >> index) & 1;
1581 bool is_int10 = (ctx->args->options->key.fs.is_int10 >> index) & 1;
1582 unsigned chan;
1583
1584 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
1585 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
1586 unsigned bits, bool hi) = NULL;
1587
1588 switch(col_format) {
1589 case V_028714_SPI_SHADER_ZERO:
1590 args->enabled_channels = 0; /* writemask */
1591 args->target = V_008DFC_SQ_EXP_NULL;
1592 break;
1593
1594 case V_028714_SPI_SHADER_32_R:
1595 args->enabled_channels = 1;
1596 args->out[0] = values[0];
1597 break;
1598
1599 case V_028714_SPI_SHADER_32_GR:
1600 args->enabled_channels = 0x3;
1601 args->out[0] = values[0];
1602 args->out[1] = values[1];
1603 break;
1604
1605 case V_028714_SPI_SHADER_32_AR:
1606 if (ctx->ac.chip_class >= GFX10) {
1607 args->enabled_channels = 0x3;
1608 args->out[0] = values[0];
1609 args->out[1] = values[3];
1610 } else {
1611 args->enabled_channels = 0x9;
1612 args->out[0] = values[0];
1613 args->out[3] = values[3];
1614 }
1615 break;
1616
1617 case V_028714_SPI_SHADER_FP16_ABGR:
1618 args->enabled_channels = 0x5;
1619 packf = ac_build_cvt_pkrtz_f16;
1620 if (is_16bit) {
1621 for (unsigned chan = 0; chan < 4; chan++)
1622 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
1623 values[chan],
1624 ctx->ac.f32, "");
1625 }
1626 break;
1627
1628 case V_028714_SPI_SHADER_UNORM16_ABGR:
1629 args->enabled_channels = 0x5;
1630 packf = ac_build_cvt_pknorm_u16;
1631 break;
1632
1633 case V_028714_SPI_SHADER_SNORM16_ABGR:
1634 args->enabled_channels = 0x5;
1635 packf = ac_build_cvt_pknorm_i16;
1636 break;
1637
1638 case V_028714_SPI_SHADER_UINT16_ABGR:
1639 args->enabled_channels = 0x5;
1640 packi = ac_build_cvt_pk_u16;
1641 if (is_16bit) {
1642 for (unsigned chan = 0; chan < 4; chan++)
1643 values[chan] = LLVMBuildZExt(ctx->ac.builder,
1644 ac_to_integer(&ctx->ac, values[chan]),
1645 ctx->ac.i32, "");
1646 }
1647 break;
1648
1649 case V_028714_SPI_SHADER_SINT16_ABGR:
1650 args->enabled_channels = 0x5;
1651 packi = ac_build_cvt_pk_i16;
1652 if (is_16bit) {
1653 for (unsigned chan = 0; chan < 4; chan++)
1654 values[chan] = LLVMBuildSExt(ctx->ac.builder,
1655 ac_to_integer(&ctx->ac, values[chan]),
1656 ctx->ac.i32, "");
1657 }
1658 break;
1659
1660 default:
1661 case V_028714_SPI_SHADER_32_ABGR:
1662 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1663 break;
1664 }
1665
1666 /* Pack f16 or norm_i16/u16. */
1667 if (packf) {
1668 for (chan = 0; chan < 2; chan++) {
1669 LLVMValueRef pack_args[2] = {
1670 values[2 * chan],
1671 values[2 * chan + 1]
1672 };
1673 LLVMValueRef packed;
1674
1675 packed = packf(&ctx->ac, pack_args);
1676 args->out[chan] = ac_to_float(&ctx->ac, packed);
1677 }
1678 args->compr = 1; /* COMPR flag */
1679 }
1680
1681 /* Pack i16/u16. */
1682 if (packi) {
1683 for (chan = 0; chan < 2; chan++) {
1684 LLVMValueRef pack_args[2] = {
1685 ac_to_integer(&ctx->ac, values[2 * chan]),
1686 ac_to_integer(&ctx->ac, values[2 * chan + 1])
1687 };
1688 LLVMValueRef packed;
1689
1690 packed = packi(&ctx->ac, pack_args,
1691 is_int8 ? 8 : is_int10 ? 10 : 16,
1692 chan == 1);
1693 args->out[chan] = ac_to_float(&ctx->ac, packed);
1694 }
1695 args->compr = 1; /* COMPR flag */
1696 }
1697 return;
1698 }
1699
1700 if (is_16bit) {
1701 for (unsigned chan = 0; chan < 4; chan++) {
1702 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
1703 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
1704 }
1705 } else
1706 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1707
1708 for (unsigned i = 0; i < 4; ++i)
1709 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
1710 }
1711
1712 static void
1713 radv_export_param(struct radv_shader_context *ctx, unsigned index,
1714 LLVMValueRef *values, unsigned enabled_channels)
1715 {
1716 struct ac_export_args args;
1717
1718 si_llvm_init_export_args(ctx, values, enabled_channels,
1719 V_008DFC_SQ_EXP_PARAM + index, &args);
1720 ac_build_export(&ctx->ac, &args);
1721 }
1722
1723 static LLVMValueRef
1724 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
1725 {
1726 LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
1727 return LLVMBuildLoad(ctx->ac.builder, output, "");
1728 }
1729
1730 static void
1731 radv_emit_stream_output(struct radv_shader_context *ctx,
1732 LLVMValueRef const *so_buffers,
1733 LLVMValueRef const *so_write_offsets,
1734 const struct radv_stream_output *output,
1735 struct radv_shader_output_values *shader_out)
1736 {
1737 unsigned num_comps = util_bitcount(output->component_mask);
1738 unsigned buf = output->buffer;
1739 unsigned offset = output->offset;
1740 unsigned start;
1741 LLVMValueRef out[4];
1742
1743 assert(num_comps && num_comps <= 4);
1744 if (!num_comps || num_comps > 4)
1745 return;
1746
1747 /* Get the first component. */
1748 start = ffs(output->component_mask) - 1;
1749
1750 /* Load the output as int. */
1751 for (int i = 0; i < num_comps; i++) {
1752 out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
1753 }
1754
1755 /* Pack the output. */
1756 LLVMValueRef vdata = NULL;
1757
1758 switch (num_comps) {
1759 case 1: /* as i32 */
1760 vdata = out[0];
1761 break;
1762 case 2: /* as v2i32 */
1763 case 3: /* as v4i32 (aligned to 4) */
1764 out[3] = LLVMGetUndef(ctx->ac.i32);
1765 /* fall through */
1766 case 4: /* as v4i32 */
1767 vdata = ac_build_gather_values(&ctx->ac, out,
1768 !ac_has_vec3_support(ctx->ac.chip_class, false) ?
1769 util_next_power_of_two(num_comps) :
1770 num_comps);
1771 break;
1772 }
1773
1774 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
1775 vdata, num_comps, so_write_offsets[buf],
1776 ctx->ac.i32_0, offset,
1777 ac_glc | ac_slc);
1778 }
1779
1780 static void
1781 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
1782 {
1783 int i;
1784
1785 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1786 assert(ctx->args->streamout_config.used);
1787 LLVMValueRef so_vtx_count =
1788 ac_build_bfe(&ctx->ac,
1789 ac_get_arg(&ctx->ac, ctx->args->streamout_config),
1790 LLVMConstInt(ctx->ac.i32, 16, false),
1791 LLVMConstInt(ctx->ac.i32, 7, false), false);
1792
1793 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
1794
1795 /* can_emit = tid < so_vtx_count; */
1796 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
1797 tid, so_vtx_count, "");
1798
1799 /* Emit the streamout code conditionally. This actually avoids
1800 * out-of-bounds buffer access. The hw tells us via the SGPR
1801 * (so_vtx_count) which threads are allowed to emit streamout data.
1802 */
1803 ac_build_ifcc(&ctx->ac, can_emit, 6501);
1804 {
1805 /* The buffer offset is computed as follows:
1806 * ByteOffset = streamout_offset[buffer_id]*4 +
1807 * (streamout_write_index + thread_id)*stride[buffer_id] +
1808 * attrib_offset
1809 */
1810 LLVMValueRef so_write_index =
1811 ac_get_arg(&ctx->ac, ctx->args->streamout_write_idx);
1812
1813 /* Compute (streamout_write_index + thread_id). */
1814 so_write_index =
1815 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
1816
1817 /* Load the descriptor and compute the write offset for each
1818 * enabled buffer.
1819 */
1820 LLVMValueRef so_write_offset[4] = {};
1821 LLVMValueRef so_buffers[4] = {};
1822 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
1823
1824 for (i = 0; i < 4; i++) {
1825 uint16_t stride = ctx->args->shader_info->so.strides[i];
1826
1827 if (!stride)
1828 continue;
1829
1830 LLVMValueRef offset =
1831 LLVMConstInt(ctx->ac.i32, i, false);
1832
1833 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
1834 buf_ptr, offset);
1835
1836 LLVMValueRef so_offset =
1837 ac_get_arg(&ctx->ac, ctx->args->streamout_offset[i]);
1838
1839 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
1840 LLVMConstInt(ctx->ac.i32, 4, false), "");
1841
1842 so_write_offset[i] =
1843 ac_build_imad(&ctx->ac, so_write_index,
1844 LLVMConstInt(ctx->ac.i32,
1845 stride * 4, false),
1846 so_offset);
1847 }
1848
1849 /* Write streamout data. */
1850 for (i = 0; i < ctx->args->shader_info->so.num_outputs; i++) {
1851 struct radv_shader_output_values shader_out = {};
1852 struct radv_stream_output *output =
1853 &ctx->args->shader_info->so.outputs[i];
1854
1855 if (stream != output->stream)
1856 continue;
1857
1858 for (int j = 0; j < 4; j++) {
1859 shader_out.values[j] =
1860 radv_load_output(ctx, output->location, j);
1861 }
1862
1863 radv_emit_stream_output(ctx, so_buffers,so_write_offset,
1864 output, &shader_out);
1865 }
1866 }
1867 ac_build_endif(&ctx->ac, 6501);
1868 }
1869
1870 static void
1871 radv_build_param_exports(struct radv_shader_context *ctx,
1872 struct radv_shader_output_values *outputs,
1873 unsigned noutput,
1874 struct radv_vs_output_info *outinfo,
1875 bool export_clip_dists)
1876 {
1877 unsigned param_count = 0;
1878
1879 for (unsigned i = 0; i < noutput; i++) {
1880 unsigned slot_name = outputs[i].slot_name;
1881 unsigned usage_mask = outputs[i].usage_mask;
1882
1883 if (slot_name != VARYING_SLOT_LAYER &&
1884 slot_name != VARYING_SLOT_PRIMITIVE_ID &&
1885 slot_name != VARYING_SLOT_CLIP_DIST0 &&
1886 slot_name != VARYING_SLOT_CLIP_DIST1 &&
1887 slot_name < VARYING_SLOT_VAR0)
1888 continue;
1889
1890 if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
1891 slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
1892 continue;
1893
1894 radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
1895
1896 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
1897 outinfo->vs_output_param_offset[slot_name] = param_count++;
1898 }
1899
1900 outinfo->param_exports = param_count;
1901 }
1902
1903 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1904 * (position and parameter data only).
1905 */
1906 static void
1907 radv_llvm_export_vs(struct radv_shader_context *ctx,
1908 struct radv_shader_output_values *outputs,
1909 unsigned noutput,
1910 struct radv_vs_output_info *outinfo,
1911 bool export_clip_dists)
1912 {
1913 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
1914 struct ac_export_args pos_args[4] = {};
1915 unsigned pos_idx, index;
1916 int i;
1917
1918 /* Build position exports */
1919 for (i = 0; i < noutput; i++) {
1920 switch (outputs[i].slot_name) {
1921 case VARYING_SLOT_POS:
1922 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1923 V_008DFC_SQ_EXP_POS, &pos_args[0]);
1924 break;
1925 case VARYING_SLOT_PSIZ:
1926 psize_value = outputs[i].values[0];
1927 break;
1928 case VARYING_SLOT_LAYER:
1929 layer_value = outputs[i].values[0];
1930 break;
1931 case VARYING_SLOT_VIEWPORT:
1932 viewport_value = outputs[i].values[0];
1933 break;
1934 case VARYING_SLOT_CLIP_DIST0:
1935 case VARYING_SLOT_CLIP_DIST1:
1936 index = 2 + outputs[i].slot_index;
1937 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1938 V_008DFC_SQ_EXP_POS + index,
1939 &pos_args[index]);
1940 break;
1941 default:
1942 break;
1943 }
1944 }
1945
1946 /* We need to add the position output manually if it's missing. */
1947 if (!pos_args[0].out[0]) {
1948 pos_args[0].enabled_channels = 0xf; /* writemask */
1949 pos_args[0].valid_mask = 0; /* EXEC mask */
1950 pos_args[0].done = 0; /* last export? */
1951 pos_args[0].target = V_008DFC_SQ_EXP_POS;
1952 pos_args[0].compr = 0; /* COMPR flag */
1953 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
1954 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
1955 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
1956 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
1957 }
1958
1959 if (outinfo->writes_pointsize ||
1960 outinfo->writes_layer ||
1961 outinfo->writes_viewport_index) {
1962 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
1963 (outinfo->writes_layer == true ? 4 : 0));
1964 pos_args[1].valid_mask = 0;
1965 pos_args[1].done = 0;
1966 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
1967 pos_args[1].compr = 0;
1968 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
1969 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
1970 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
1971 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
1972
1973 if (outinfo->writes_pointsize == true)
1974 pos_args[1].out[0] = psize_value;
1975 if (outinfo->writes_layer == true)
1976 pos_args[1].out[2] = layer_value;
1977 if (outinfo->writes_viewport_index == true) {
1978 if (ctx->args->options->chip_class >= GFX9) {
1979 /* GFX9 has the layer in out.z[10:0] and the viewport
1980 * index in out.z[19:16].
1981 */
1982 LLVMValueRef v = viewport_value;
1983 v = ac_to_integer(&ctx->ac, v);
1984 v = LLVMBuildShl(ctx->ac.builder, v,
1985 LLVMConstInt(ctx->ac.i32, 16, false),
1986 "");
1987 v = LLVMBuildOr(ctx->ac.builder, v,
1988 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
1989
1990 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
1991 pos_args[1].enabled_channels |= 1 << 2;
1992 } else {
1993 pos_args[1].out[3] = viewport_value;
1994 pos_args[1].enabled_channels |= 1 << 3;
1995 }
1996 }
1997 }
1998
1999 for (i = 0; i < 4; i++) {
2000 if (pos_args[i].out[0])
2001 outinfo->pos_exports++;
2002 }
2003
2004 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2005 * Setting valid_mask=1 prevents it and has no other effect.
2006 */
2007 if (ctx->ac.family == CHIP_NAVI10 ||
2008 ctx->ac.family == CHIP_NAVI12 ||
2009 ctx->ac.family == CHIP_NAVI14)
2010 pos_args[0].valid_mask = 1;
2011
2012 pos_idx = 0;
2013 for (i = 0; i < 4; i++) {
2014 if (!pos_args[i].out[0])
2015 continue;
2016
2017 /* Specify the target we are exporting */
2018 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2019
2020 if (pos_idx == outinfo->pos_exports)
2021 /* Specify that this is the last export */
2022 pos_args[i].done = 1;
2023
2024 ac_build_export(&ctx->ac, &pos_args[i]);
2025 }
2026
2027 /* Build parameter exports */
2028 radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
2029 }
2030
2031 static void
2032 handle_vs_outputs_post(struct radv_shader_context *ctx,
2033 bool export_prim_id,
2034 bool export_clip_dists,
2035 struct radv_vs_output_info *outinfo)
2036 {
2037 struct radv_shader_output_values *outputs;
2038 unsigned noutput = 0;
2039
2040 if (ctx->args->options->key.has_multiview_view_index) {
2041 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2042 if(!*tmp_out) {
2043 for(unsigned i = 0; i < 4; ++i)
2044 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2045 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2046 }
2047
2048 LLVMValueRef view_index = ac_get_arg(&ctx->ac, ctx->args->ac.view_index);
2049 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, view_index), *tmp_out);
2050 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2051 }
2052
2053 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2054 sizeof(outinfo->vs_output_param_offset));
2055 outinfo->pos_exports = 0;
2056
2057 if (!ctx->args->options->use_ngg_streamout &&
2058 ctx->args->shader_info->so.num_outputs &&
2059 !ctx->args->is_gs_copy_shader) {
2060 /* The GS copy shader emission already emits streamout. */
2061 radv_emit_streamout(ctx, 0);
2062 }
2063
2064 /* Allocate a temporary array for the output values. */
2065 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
2066 outputs = malloc(num_outputs * sizeof(outputs[0]));
2067
2068 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2069 if (!(ctx->output_mask & (1ull << i)))
2070 continue;
2071
2072 outputs[noutput].slot_name = i;
2073 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2074
2075 if (ctx->stage == MESA_SHADER_VERTEX &&
2076 !ctx->args->is_gs_copy_shader) {
2077 outputs[noutput].usage_mask =
2078 ctx->args->shader_info->vs.output_usage_mask[i];
2079 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2080 outputs[noutput].usage_mask =
2081 ctx->args->shader_info->tes.output_usage_mask[i];
2082 } else {
2083 assert(ctx->args->is_gs_copy_shader);
2084 outputs[noutput].usage_mask =
2085 ctx->args->shader_info->gs.output_usage_mask[i];
2086 }
2087
2088 for (unsigned j = 0; j < 4; j++) {
2089 outputs[noutput].values[j] =
2090 ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2091 }
2092
2093 noutput++;
2094 }
2095
2096 /* Export PrimitiveID. */
2097 if (export_prim_id) {
2098 outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
2099 outputs[noutput].slot_index = 0;
2100 outputs[noutput].usage_mask = 0x1;
2101 outputs[noutput].values[0] =
2102 ac_get_arg(&ctx->ac, ctx->args->vs_prim_id);
2103 for (unsigned j = 1; j < 4; j++)
2104 outputs[noutput].values[j] = ctx->ac.f32_0;
2105 noutput++;
2106 }
2107
2108 radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
2109
2110 free(outputs);
2111 }
2112
2113 static void
2114 handle_es_outputs_post(struct radv_shader_context *ctx,
2115 struct radv_es_output_info *outinfo)
2116 {
2117 int j;
2118 LLVMValueRef lds_base = NULL;
2119
2120 if (ctx->ac.chip_class >= GFX9) {
2121 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2122 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2123 LLVMValueRef wave_idx =
2124 ac_unpack_param(&ctx->ac,
2125 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2126 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2127 LLVMBuildMul(ctx->ac.builder, wave_idx,
2128 LLVMConstInt(ctx->ac.i32,
2129 ctx->ac.wave_size, false), ""), "");
2130 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2131 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2132 }
2133
2134 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2135 LLVMValueRef dw_addr = NULL;
2136 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2137 unsigned output_usage_mask;
2138 int param_index;
2139
2140 if (!(ctx->output_mask & (1ull << i)))
2141 continue;
2142
2143 if (ctx->stage == MESA_SHADER_VERTEX) {
2144 output_usage_mask =
2145 ctx->args->shader_info->vs.output_usage_mask[i];
2146 } else {
2147 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2148 output_usage_mask =
2149 ctx->args->shader_info->tes.output_usage_mask[i];
2150 }
2151
2152 param_index = shader_io_get_unique_index(i);
2153
2154 if (lds_base) {
2155 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2156 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2157 "");
2158 }
2159
2160 for (j = 0; j < 4; j++) {
2161 if (!(output_usage_mask & (1 << j)))
2162 continue;
2163
2164 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2165 out_val = ac_to_integer(&ctx->ac, out_val);
2166 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2167
2168 if (ctx->ac.chip_class >= GFX9) {
2169 LLVMValueRef dw_addr_offset =
2170 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2171 LLVMConstInt(ctx->ac.i32,
2172 j, false), "");
2173
2174 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2175 } else {
2176 ac_build_buffer_store_dword(&ctx->ac,
2177 ctx->esgs_ring,
2178 out_val, 1,
2179 NULL,
2180 ac_get_arg(&ctx->ac, ctx->args->es2gs_offset),
2181 (4 * param_index + j) * 4,
2182 ac_glc | ac_slc | ac_swizzled);
2183 }
2184 }
2185 }
2186 }
2187
2188 static void
2189 handle_ls_outputs_post(struct radv_shader_context *ctx)
2190 {
2191 LLVMValueRef vertex_id = ctx->rel_auto_id;
2192 uint32_t num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
2193 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2194 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2195 vertex_dw_stride, "");
2196
2197 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2198 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2199
2200 if (!(ctx->output_mask & (1ull << i)))
2201 continue;
2202
2203 int param = shader_io_get_unique_index(i);
2204 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2205 LLVMConstInt(ctx->ac.i32, param * 4, false),
2206 "");
2207 for (unsigned j = 0; j < 4; j++) {
2208 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2209 value = ac_to_integer(&ctx->ac, value);
2210 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2211 ac_lds_store(&ctx->ac, dw_addr, value);
2212 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2213 }
2214 }
2215 }
2216
2217 static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
2218 {
2219 return ac_unpack_param(&ctx->ac,
2220 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2221 }
2222
2223 static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
2224 {
2225 return ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 28, 4);
2226 }
2227
2228 static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
2229 {
2230 LLVMBuilderRef builder = ctx->ac.builder;
2231 LLVMValueRef tmp;
2232 tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
2233 LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
2234 return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
2235 }
2236
2237 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
2238 {
2239 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2240 LLVMConstInt(ctx->ac.i32, 12, false),
2241 LLVMConstInt(ctx->ac.i32, 9, false),
2242 false);
2243 }
2244
2245 static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
2246 {
2247 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2248 LLVMConstInt(ctx->ac.i32, 22, false),
2249 LLVMConstInt(ctx->ac.i32, 9, false),
2250 false);
2251 }
2252
2253 static LLVMValueRef ngg_get_ordered_id(struct radv_shader_context *ctx)
2254 {
2255 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2256 ctx->ac.i32_0,
2257 LLVMConstInt(ctx->ac.i32, 12, false),
2258 false);
2259 }
2260
2261 static LLVMValueRef
2262 ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
2263 {
2264 unsigned num_outputs = util_bitcount64(ctx->output_mask);
2265
2266 if (ctx->args->options->key.has_multiview_view_index)
2267 num_outputs++;
2268
2269 LLVMTypeRef elements[2] = {
2270 LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
2271 LLVMArrayType(ctx->ac.i8, 4),
2272 };
2273 LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
2274 type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
2275 return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
2276 }
2277
2278 /**
2279 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2280 * is in emit order; that is:
2281 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2282 * - during vertex emit, i.e. while the API GS shader invocation is running,
2283 * N = threadidx * gs_max_out_vertices + emitidx
2284 *
2285 * Goals of the LDS memory layout:
2286 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2287 * in uniform control flow
2288 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2289 * culling
2290 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2291 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2292 * 5. Avoid wasting memory.
2293 *
2294 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2295 * layout, elimination of bank conflicts requires that each vertex occupy an
2296 * odd number of dwords. We use the additional dword to store the output stream
2297 * index as well as a flag to indicate whether this vertex ends a primitive
2298 * for rasterization.
2299 *
2300 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2301 *
2302 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2303 * Indices are swizzled in groups of 32, which ensures point 1 without
2304 * disturbing point 2.
2305 *
2306 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2307 */
2308 static LLVMValueRef
2309 ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
2310 {
2311 LLVMBuilderRef builder = ctx->ac.builder;
2312 LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
2313
2314 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2315 unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
2316 if (write_stride_2exp) {
2317 LLVMValueRef row =
2318 LLVMBuildLShr(builder, vertexidx,
2319 LLVMConstInt(ctx->ac.i32, 5, false), "");
2320 LLVMValueRef swizzle =
2321 LLVMBuildAnd(builder, row,
2322 LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
2323 false), "");
2324 vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
2325 }
2326
2327 return ac_build_gep0(&ctx->ac, storage, vertexidx);
2328 }
2329
2330 static LLVMValueRef
2331 ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
2332 LLVMValueRef emitidx)
2333 {
2334 LLVMBuilderRef builder = ctx->ac.builder;
2335 LLVMValueRef tmp;
2336
2337 tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
2338 tmp = LLVMBuildMul(builder, tmp, gsthread, "");
2339 const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
2340 return ngg_gs_vertex_ptr(ctx, vertexidx);
2341 }
2342
2343 static LLVMValueRef
2344 ngg_gs_get_emit_output_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2345 unsigned out_idx)
2346 {
2347 LLVMValueRef gep_idx[3] = {
2348 ctx->ac.i32_0, /* implied C-style array */
2349 ctx->ac.i32_0, /* first struct entry */
2350 LLVMConstInt(ctx->ac.i32, out_idx, false),
2351 };
2352 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2353 }
2354
2355 static LLVMValueRef
2356 ngg_gs_get_emit_primflag_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2357 unsigned stream)
2358 {
2359 LLVMValueRef gep_idx[3] = {
2360 ctx->ac.i32_0, /* implied C-style array */
2361 ctx->ac.i32_1, /* second struct entry */
2362 LLVMConstInt(ctx->ac.i32, stream, false),
2363 };
2364 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2365 }
2366
2367 static struct radv_stream_output *
2368 radv_get_stream_output_by_loc(struct radv_streamout_info *so, unsigned location)
2369 {
2370 for (unsigned i = 0; i < so->num_outputs; ++i) {
2371 if (so->outputs[i].location == location)
2372 return &so->outputs[i];
2373 }
2374
2375 return NULL;
2376 }
2377
2378 static void build_streamout_vertex(struct radv_shader_context *ctx,
2379 LLVMValueRef *so_buffer, LLVMValueRef *wg_offset_dw,
2380 unsigned stream, LLVMValueRef offset_vtx,
2381 LLVMValueRef vertexptr)
2382 {
2383 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2384 LLVMBuilderRef builder = ctx->ac.builder;
2385 LLVMValueRef offset[4] = {};
2386 LLVMValueRef tmp;
2387
2388 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2389 if (!wg_offset_dw[buffer])
2390 continue;
2391
2392 tmp = LLVMBuildMul(builder, offset_vtx,
2393 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false), "");
2394 tmp = LLVMBuildAdd(builder, wg_offset_dw[buffer], tmp, "");
2395 offset[buffer] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
2396 }
2397
2398 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2399 struct radv_shader_output_values outputs[AC_LLVM_MAX_OUTPUTS];
2400 unsigned noutput = 0;
2401 unsigned out_idx = 0;
2402
2403 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2404 unsigned output_usage_mask =
2405 ctx->args->shader_info->gs.output_usage_mask[i];
2406 uint8_t output_stream =
2407 output_stream = ctx->args->shader_info->gs.output_streams[i];
2408
2409 if (!(ctx->output_mask & (1ull << i)) ||
2410 output_stream != stream)
2411 continue;
2412
2413 outputs[noutput].slot_name = i;
2414 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2415 outputs[noutput].usage_mask = output_usage_mask;
2416
2417 int length = util_last_bit(output_usage_mask);
2418
2419 for (unsigned j = 0; j < length; j++, out_idx++) {
2420 if (!(output_usage_mask & (1 << j)))
2421 continue;
2422
2423 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2424 LLVMConstInt(ctx->ac.i32, out_idx, false));
2425 outputs[noutput].values[j] = LLVMBuildLoad(builder, tmp, "");
2426 }
2427
2428 for (unsigned j = length; j < 4; j++)
2429 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
2430
2431 noutput++;
2432 }
2433
2434 for (unsigned i = 0; i < noutput; i++) {
2435 struct radv_stream_output *output =
2436 radv_get_stream_output_by_loc(so, outputs[i].slot_name);
2437
2438 if (!output ||
2439 output->stream != stream)
2440 continue;
2441
2442 struct radv_shader_output_values out = {};
2443
2444 for (unsigned j = 0; j < 4; j++) {
2445 out.values[j] = outputs[i].values[j];
2446 }
2447
2448 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2449 }
2450 } else {
2451 for (unsigned i = 0; i < so->num_outputs; ++i) {
2452 struct radv_stream_output *output =
2453 &ctx->args->shader_info->so.outputs[i];
2454
2455 if (stream != output->stream)
2456 continue;
2457
2458 struct radv_shader_output_values out = {};
2459
2460 for (unsigned comp = 0; comp < 4; comp++) {
2461 if (!(output->component_mask & (1 << comp)))
2462 continue;
2463
2464 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2465 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2466 out.values[comp] = LLVMBuildLoad(builder, tmp, "");
2467 }
2468
2469 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2470 }
2471 }
2472 }
2473
2474 struct ngg_streamout {
2475 LLVMValueRef num_vertices;
2476
2477 /* per-thread data */
2478 LLVMValueRef prim_enable[4]; /* i1 per stream */
2479 LLVMValueRef vertices[3]; /* [N x i32] addrspace(LDS)* */
2480
2481 /* Output */
2482 LLVMValueRef emit[4]; /* per-stream emitted primitives (only valid for used streams) */
2483 };
2484
2485 /**
2486 * Build streamout logic.
2487 *
2488 * Implies a barrier.
2489 *
2490 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2491 *
2492 * Clobbers gs_ngg_scratch[8:].
2493 */
2494 static void build_streamout(struct radv_shader_context *ctx,
2495 struct ngg_streamout *nggso)
2496 {
2497 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2498 LLVMBuilderRef builder = ctx->ac.builder;
2499 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
2500 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2501 LLVMValueRef cond, tmp, tmp2;
2502 LLVMValueRef i32_2 = LLVMConstInt(ctx->ac.i32, 2, false);
2503 LLVMValueRef i32_4 = LLVMConstInt(ctx->ac.i32, 4, false);
2504 LLVMValueRef i32_8 = LLVMConstInt(ctx->ac.i32, 8, false);
2505 LLVMValueRef so_buffer[4] = {};
2506 unsigned max_num_vertices = 1 + (nggso->vertices[1] ? 1 : 0) +
2507 (nggso->vertices[2] ? 1 : 0);
2508 LLVMValueRef prim_stride_dw[4] = {};
2509 LLVMValueRef prim_stride_dw_vgpr = LLVMGetUndef(ctx->ac.i32);
2510 int stream_for_buffer[4] = { -1, -1, -1, -1 };
2511 unsigned bufmask_for_stream[4] = {};
2512 bool isgs = ctx->stage == MESA_SHADER_GEOMETRY;
2513 unsigned scratch_emit_base = isgs ? 4 : 0;
2514 LLVMValueRef scratch_emit_basev = isgs ? i32_4 : ctx->ac.i32_0;
2515 unsigned scratch_offset_base = isgs ? 8 : 4;
2516 LLVMValueRef scratch_offset_basev = isgs ? i32_8 : i32_4;
2517
2518 ac_llvm_add_target_dep_function_attr(ctx->main_function,
2519 "amdgpu-gds-size", 256);
2520
2521 /* Determine the mapping of streamout buffers to vertex streams. */
2522 for (unsigned i = 0; i < so->num_outputs; ++i) {
2523 unsigned buf = so->outputs[i].buffer;
2524 unsigned stream = so->outputs[i].stream;
2525 assert(stream_for_buffer[buf] < 0 || stream_for_buffer[buf] == stream);
2526 stream_for_buffer[buf] = stream;
2527 bufmask_for_stream[stream] |= 1 << buf;
2528 }
2529
2530 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2531 if (stream_for_buffer[buffer] == -1)
2532 continue;
2533
2534 assert(so->strides[buffer]);
2535
2536 LLVMValueRef stride_for_buffer =
2537 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false);
2538 prim_stride_dw[buffer] =
2539 LLVMBuildMul(builder, stride_for_buffer,
2540 nggso->num_vertices, "");
2541 prim_stride_dw_vgpr = ac_build_writelane(
2542 &ctx->ac, prim_stride_dw_vgpr, prim_stride_dw[buffer],
2543 LLVMConstInt(ctx->ac.i32, buffer, false));
2544
2545 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, buffer, false);
2546 so_buffer[buffer] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr,
2547 offset);
2548 }
2549
2550 cond = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
2551 ac_build_ifcc(&ctx->ac, cond, 5200);
2552 {
2553 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
2554 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
2555
2556 /* Advance the streamout offsets in GDS. */
2557 LLVMValueRef offsets_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2558 LLVMValueRef generated_by_stream_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2559
2560 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2561 ac_build_ifcc(&ctx->ac, cond, 5210);
2562 {
2563 /* Fetch the number of generated primitives and store
2564 * it in GDS for later use.
2565 */
2566 if (isgs) {
2567 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid);
2568 tmp = LLVMBuildLoad(builder, tmp, "");
2569 } else {
2570 tmp = ac_build_writelane(&ctx->ac, ctx->ac.i32_0,
2571 ngg_get_prim_cnt(ctx), ctx->ac.i32_0);
2572 }
2573 LLVMBuildStore(builder, tmp, generated_by_stream_vgpr);
2574
2575 unsigned swizzle[4];
2576 int unused_stream = -1;
2577 for (unsigned stream = 0; stream < 4; ++stream) {
2578 if (!ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2579 unused_stream = stream;
2580 break;
2581 }
2582 }
2583 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2584 if (stream_for_buffer[buffer] >= 0) {
2585 swizzle[buffer] = stream_for_buffer[buffer];
2586 } else {
2587 assert(unused_stream >= 0);
2588 swizzle[buffer] = unused_stream;
2589 }
2590 }
2591
2592 tmp = ac_build_quad_swizzle(&ctx->ac, tmp,
2593 swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2594 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2595
2596 LLVMValueRef args[] = {
2597 LLVMBuildIntToPtr(builder, ngg_get_ordered_id(ctx), gdsptr, ""),
2598 tmp,
2599 ctx->ac.i32_0, // ordering
2600 ctx->ac.i32_0, // scope
2601 ctx->ac.i1false, // isVolatile
2602 LLVMConstInt(ctx->ac.i32, 4 << 24, false), // OA index
2603 ctx->ac.i1true, // wave release
2604 ctx->ac.i1true, // wave done
2605 };
2606
2607 tmp = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.ordered.add",
2608 ctx->ac.i32, args, ARRAY_SIZE(args), 0);
2609
2610 /* Keep offsets in a VGPR for quick retrieval via readlane by
2611 * the first wave for bounds checking, and also store in LDS
2612 * for retrieval by all waves later. */
2613 LLVMBuildStore(builder, tmp, offsets_vgpr);
2614
2615 tmp2 = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2616 scratch_offset_basev, "");
2617 tmp2 = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp2);
2618 LLVMBuildStore(builder, tmp, tmp2);
2619 }
2620 ac_build_endif(&ctx->ac, 5210);
2621
2622 /* Determine the max emit per buffer. This is done via the SALU, in part
2623 * because LLVM can't generate divide-by-multiply if we try to do this
2624 * via VALU with one lane per buffer.
2625 */
2626 LLVMValueRef max_emit[4] = {};
2627 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2628 if (stream_for_buffer[buffer] == -1)
2629 continue;
2630
2631 /* Compute the streamout buffer size in DWORD. */
2632 LLVMValueRef bufsize_dw =
2633 LLVMBuildLShr(builder,
2634 LLVMBuildExtractElement(builder, so_buffer[buffer], i32_2, ""),
2635 i32_2, "");
2636
2637 /* Load the streamout buffer offset from GDS. */
2638 tmp = LLVMBuildLoad(builder, offsets_vgpr, "");
2639 LLVMValueRef offset_dw =
2640 ac_build_readlane(&ctx->ac, tmp,
2641 LLVMConstInt(ctx->ac.i32, buffer, false));
2642
2643 /* Compute the remaining size to emit. */
2644 LLVMValueRef remaining_dw =
2645 LLVMBuildSub(builder, bufsize_dw, offset_dw, "");
2646 tmp = LLVMBuildUDiv(builder, remaining_dw,
2647 prim_stride_dw[buffer], "");
2648
2649 cond = LLVMBuildICmp(builder, LLVMIntULT,
2650 bufsize_dw, offset_dw, "");
2651 max_emit[buffer] = LLVMBuildSelect(builder, cond,
2652 ctx->ac.i32_0, tmp, "");
2653 }
2654
2655 /* Determine the number of emitted primitives per stream and fixup the
2656 * GDS counter if necessary.
2657 *
2658 * This is complicated by the fact that a single stream can emit to
2659 * multiple buffers (but luckily not vice versa).
2660 */
2661 LLVMValueRef emit_vgpr = ctx->ac.i32_0;
2662
2663 for (unsigned stream = 0; stream < 4; ++stream) {
2664 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2665 continue;
2666
2667 /* Load the number of generated primitives from GDS and
2668 * determine that number for the given stream.
2669 */
2670 tmp = LLVMBuildLoad(builder, generated_by_stream_vgpr, "");
2671 LLVMValueRef generated =
2672 ac_build_readlane(&ctx->ac, tmp,
2673 LLVMConstInt(ctx->ac.i32, stream, false));
2674
2675
2676 /* Compute the number of emitted primitives. */
2677 LLVMValueRef emit = generated;
2678 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2679 if (stream_for_buffer[buffer] == stream)
2680 emit = ac_build_umin(&ctx->ac, emit, max_emit[buffer]);
2681 }
2682
2683 /* Store the number of emitted primitives for that
2684 * stream.
2685 */
2686 emit_vgpr = ac_build_writelane(&ctx->ac, emit_vgpr, emit,
2687 LLVMConstInt(ctx->ac.i32, stream, false));
2688
2689 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2690 cond = LLVMBuildICmp(builder, LLVMIntULT, emit, generated, "");
2691 ac_build_ifcc(&ctx->ac, cond, 5221); /* scalar branch */
2692 tmp = LLVMBuildLShr(builder,
2693 LLVMConstInt(ctx->ac.i32, bufmask_for_stream[stream], false),
2694 ac_get_thread_id(&ctx->ac), "");
2695 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2696 ac_build_ifcc(&ctx->ac, tmp, 5222);
2697 {
2698 tmp = LLVMBuildSub(builder, generated, emit, "");
2699 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2700 tmp2 = LLVMBuildGEP(builder, gdsbase, &tid, 1, "");
2701 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpSub, tmp2, tmp,
2702 LLVMAtomicOrderingMonotonic, false);
2703 }
2704 ac_build_endif(&ctx->ac, 5222);
2705 ac_build_endif(&ctx->ac, 5221);
2706 }
2707
2708 /* Store the number of emitted primitives to LDS for later use. */
2709 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2710 ac_build_ifcc(&ctx->ac, cond, 5225);
2711 {
2712 tmp = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2713 scratch_emit_basev, "");
2714 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp);
2715 LLVMBuildStore(builder, emit_vgpr, tmp);
2716 }
2717 ac_build_endif(&ctx->ac, 5225);
2718 }
2719 ac_build_endif(&ctx->ac, 5200);
2720
2721 /* Determine the workgroup-relative per-thread / primitive offset into
2722 * the streamout buffers */
2723 struct ac_wg_scan primemit_scan[4] = {};
2724
2725 if (isgs) {
2726 for (unsigned stream = 0; stream < 4; ++stream) {
2727 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2728 continue;
2729
2730 primemit_scan[stream].enable_exclusive = true;
2731 primemit_scan[stream].op = nir_op_iadd;
2732 primemit_scan[stream].src = nggso->prim_enable[stream];
2733 primemit_scan[stream].scratch =
2734 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
2735 LLVMConstInt(ctx->ac.i32, 12 + 8 * stream, false));
2736 primemit_scan[stream].waveidx = get_wave_id_in_tg(ctx);
2737 primemit_scan[stream].numwaves = get_tgsize(ctx);
2738 primemit_scan[stream].maxwaves = 8;
2739 ac_build_wg_scan_top(&ctx->ac, &primemit_scan[stream]);
2740 }
2741 }
2742
2743 ac_build_s_barrier(&ctx->ac);
2744
2745 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2746 LLVMValueRef wgoffset_dw[4] = {};
2747
2748 {
2749 LLVMValueRef scratch_vgpr;
2750
2751 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ac_get_thread_id(&ctx->ac));
2752 scratch_vgpr = LLVMBuildLoad(builder, tmp, "");
2753
2754 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2755 if (stream_for_buffer[buffer] >= 0) {
2756 wgoffset_dw[buffer] = ac_build_readlane(
2757 &ctx->ac, scratch_vgpr,
2758 LLVMConstInt(ctx->ac.i32, scratch_offset_base + buffer, false));
2759 }
2760 }
2761
2762 for (unsigned stream = 0; stream < 4; ++stream) {
2763 if (ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2764 nggso->emit[stream] = ac_build_readlane(
2765 &ctx->ac, scratch_vgpr,
2766 LLVMConstInt(ctx->ac.i32, scratch_emit_base + stream, false));
2767 }
2768 }
2769 }
2770
2771 /* Write out primitive data */
2772 for (unsigned stream = 0; stream < 4; ++stream) {
2773 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2774 continue;
2775
2776 if (isgs) {
2777 ac_build_wg_scan_bottom(&ctx->ac, &primemit_scan[stream]);
2778 } else {
2779 primemit_scan[stream].result_exclusive = tid;
2780 }
2781
2782 cond = LLVMBuildICmp(builder, LLVMIntULT,
2783 primemit_scan[stream].result_exclusive,
2784 nggso->emit[stream], "");
2785 cond = LLVMBuildAnd(builder, cond, nggso->prim_enable[stream], "");
2786 ac_build_ifcc(&ctx->ac, cond, 5240);
2787 {
2788 LLVMValueRef offset_vtx =
2789 LLVMBuildMul(builder, primemit_scan[stream].result_exclusive,
2790 nggso->num_vertices, "");
2791
2792 for (unsigned i = 0; i < max_num_vertices; ++i) {
2793 cond = LLVMBuildICmp(builder, LLVMIntULT,
2794 LLVMConstInt(ctx->ac.i32, i, false),
2795 nggso->num_vertices, "");
2796 ac_build_ifcc(&ctx->ac, cond, 5241);
2797 build_streamout_vertex(ctx, so_buffer, wgoffset_dw,
2798 stream, offset_vtx, nggso->vertices[i]);
2799 ac_build_endif(&ctx->ac, 5241);
2800 offset_vtx = LLVMBuildAdd(builder, offset_vtx, ctx->ac.i32_1, "");
2801 }
2802 }
2803 ac_build_endif(&ctx->ac, 5240);
2804 }
2805 }
2806
2807 static unsigned ngg_nogs_vertex_size(struct radv_shader_context *ctx)
2808 {
2809 unsigned lds_vertex_size = 0;
2810
2811 if (ctx->args->shader_info->so.num_outputs)
2812 lds_vertex_size = 4 * ctx->args->shader_info->so.num_outputs + 1;
2813
2814 return lds_vertex_size;
2815 }
2816
2817 /**
2818 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2819 * for the vertex outputs.
2820 */
2821 static LLVMValueRef ngg_nogs_vertex_ptr(struct radv_shader_context *ctx,
2822 LLVMValueRef vtxid)
2823 {
2824 /* The extra dword is used to avoid LDS bank conflicts. */
2825 unsigned vertex_size = ngg_nogs_vertex_size(ctx);
2826 LLVMTypeRef ai32 = LLVMArrayType(ctx->ac.i32, vertex_size);
2827 LLVMTypeRef pai32 = LLVMPointerType(ai32, AC_ADDR_SPACE_LDS);
2828 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, ctx->esgs_ring, pai32, "");
2829 return LLVMBuildGEP(ctx->ac.builder, tmp, &vtxid, 1, "");
2830 }
2831
2832 static void
2833 handle_ngg_outputs_post_1(struct radv_shader_context *ctx)
2834 {
2835 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2836 LLVMBuilderRef builder = ctx->ac.builder;
2837 LLVMValueRef vertex_ptr = NULL;
2838 LLVMValueRef tmp, tmp2;
2839
2840 assert((ctx->stage == MESA_SHADER_VERTEX ||
2841 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2842
2843 if (!ctx->args->shader_info->so.num_outputs)
2844 return;
2845
2846 vertex_ptr = ngg_nogs_vertex_ptr(ctx, get_thread_id_in_tg(ctx));
2847
2848 for (unsigned i = 0; i < so->num_outputs; ++i) {
2849 struct radv_stream_output *output =
2850 &ctx->args->shader_info->so.outputs[i];
2851
2852 unsigned loc = output->location;
2853
2854 for (unsigned comp = 0; comp < 4; comp++) {
2855 if (!(output->component_mask & (1 << comp)))
2856 continue;
2857
2858 tmp = ac_build_gep0(&ctx->ac, vertex_ptr,
2859 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2860 tmp2 = LLVMBuildLoad(builder,
2861 ctx->abi.outputs[4 * loc + comp], "");
2862 tmp2 = ac_to_integer(&ctx->ac, tmp2);
2863 LLVMBuildStore(builder, tmp2, tmp);
2864 }
2865 }
2866 }
2867
2868 static void
2869 handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
2870 {
2871 LLVMBuilderRef builder = ctx->ac.builder;
2872 LLVMValueRef tmp;
2873
2874 assert((ctx->stage == MESA_SHADER_VERTEX ||
2875 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2876
2877 LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac,
2878 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
2879 LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac,
2880 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 0, 8);
2881 LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
2882 ac_get_thread_id(&ctx->ac), prims_in_wave, "");
2883 LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
2884 ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
2885 LLVMValueRef vtxindex[] = {
2886 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 0, 16),
2887 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 16, 16),
2888 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[2]), 0, 16),
2889 };
2890
2891 /* Determine the number of vertices per primitive. */
2892 unsigned num_vertices;
2893 LLVMValueRef num_vertices_val;
2894
2895 if (ctx->stage == MESA_SHADER_VERTEX) {
2896 LLVMValueRef outprim_val =
2897 LLVMConstInt(ctx->ac.i32,
2898 ctx->args->options->key.vs.outprim, false);
2899 num_vertices_val = LLVMBuildAdd(builder, outprim_val,
2900 ctx->ac.i32_1, "");
2901 num_vertices = 3; /* TODO: optimize for points & lines */
2902 } else {
2903 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2904
2905 if (ctx->shader->info.tess.point_mode)
2906 num_vertices = 1;
2907 else if (ctx->shader->info.tess.primitive_mode == GL_ISOLINES)
2908 num_vertices = 2;
2909 else
2910 num_vertices = 3;
2911
2912 num_vertices_val = LLVMConstInt(ctx->ac.i32, num_vertices, false);
2913 }
2914
2915 /* Streamout */
2916 if (ctx->args->shader_info->so.num_outputs) {
2917 struct ngg_streamout nggso = {};
2918
2919 nggso.num_vertices = num_vertices_val;
2920 nggso.prim_enable[0] = is_gs_thread;
2921
2922 for (unsigned i = 0; i < num_vertices; ++i)
2923 nggso.vertices[i] = ngg_nogs_vertex_ptr(ctx, vtxindex[i]);
2924
2925 build_streamout(ctx, &nggso);
2926 }
2927
2928 /* Copy Primitive IDs from GS threads to the LDS address corresponding
2929 * to the ES thread of the provoking vertex.
2930 */
2931 if (ctx->stage == MESA_SHADER_VERTEX &&
2932 ctx->args->options->key.vs_common_out.export_prim_id) {
2933 if (ctx->args->shader_info->so.num_outputs)
2934 ac_build_s_barrier(&ctx->ac);
2935
2936 ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
2937 /* Extract the PROVOKING_VTX_INDEX field. */
2938 LLVMValueRef provoking_vtx_in_prim =
2939 LLVMConstInt(ctx->ac.i32, 0, false);
2940
2941 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
2942 LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
2943 LLVMValueRef provoking_vtx_index =
2944 LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
2945
2946 LLVMBuildStore(builder, ac_get_arg(&ctx->ac, ctx->args->ac.gs_prim_id),
2947 ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
2948 ac_build_endif(&ctx->ac, 5400);
2949 }
2950
2951 /* TODO: primitive culling */
2952
2953 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
2954 ngg_get_vtx_cnt(ctx), ngg_get_prim_cnt(ctx));
2955
2956 /* TODO: streamout queries */
2957 /* Export primitive data to the index buffer.
2958 *
2959 * For the first version, we will always build up all three indices
2960 * independent of the primitive type. The additional garbage data
2961 * shouldn't hurt.
2962 *
2963 * TODO: culling depends on the primitive type, so can have some
2964 * interaction here.
2965 */
2966 ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
2967 {
2968 struct ac_ngg_prim prim = {};
2969
2970 if (ctx->args->options->key.vs_common_out.as_ngg_passthrough) {
2971 prim.passthrough = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]);
2972 } else {
2973 prim.num_vertices = num_vertices;
2974 prim.isnull = ctx->ac.i1false;
2975 memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
2976
2977 for (unsigned i = 0; i < num_vertices; ++i) {
2978 tmp = LLVMBuildLShr(builder,
2979 ac_get_arg(&ctx->ac, ctx->args->ac.gs_invocation_id),
2980 LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
2981 prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2982 }
2983 }
2984
2985 ac_build_export_prim(&ctx->ac, &prim);
2986 }
2987 ac_build_endif(&ctx->ac, 6001);
2988
2989 /* Export per-vertex data (positions and parameters). */
2990 ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
2991 {
2992 struct radv_vs_output_info *outinfo =
2993 ctx->stage == MESA_SHADER_TESS_EVAL ?
2994 &ctx->args->shader_info->tes.outinfo : &ctx->args->shader_info->vs.outinfo;
2995
2996 /* Exporting the primitive ID is handled below. */
2997 /* TODO: use the new VS export path */
2998 handle_vs_outputs_post(ctx, false,
2999 ctx->args->options->key.vs_common_out.export_clip_dists,
3000 outinfo);
3001
3002 if (ctx->args->options->key.vs_common_out.export_prim_id) {
3003 unsigned param_count = outinfo->param_exports;
3004 LLVMValueRef values[4];
3005
3006 if (ctx->stage == MESA_SHADER_VERTEX) {
3007 /* Wait for GS stores to finish. */
3008 ac_build_s_barrier(&ctx->ac);
3009
3010 tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
3011 get_thread_id_in_tg(ctx));
3012 values[0] = LLVMBuildLoad(builder, tmp, "");
3013 } else {
3014 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
3015 values[0] = ac_get_arg(&ctx->ac, ctx->args->ac.tes_patch_id);
3016 }
3017
3018 values[0] = ac_to_float(&ctx->ac, values[0]);
3019 for (unsigned j = 1; j < 4; j++)
3020 values[j] = ctx->ac.f32_0;
3021
3022 radv_export_param(ctx, param_count, values, 0x1);
3023
3024 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
3025 outinfo->param_exports = param_count;
3026 }
3027 }
3028 ac_build_endif(&ctx->ac, 6002);
3029 }
3030
3031 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
3032 {
3033 /* Zero out the part of LDS scratch that is used to accumulate the
3034 * per-stream generated primitive count.
3035 */
3036 LLVMBuilderRef builder = ctx->ac.builder;
3037 LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
3038 LLVMValueRef tid = get_thread_id_in_tg(ctx);
3039 LLVMBasicBlockRef merge_block;
3040 LLVMValueRef cond;
3041
3042 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
3043 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3044 merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3045
3046 cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
3047 LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
3048 LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
3049
3050 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
3051 LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
3052
3053 LLVMBuildBr(ctx->ac.builder, merge_block);
3054 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
3055
3056 ac_build_s_barrier(&ctx->ac);
3057 }
3058
3059 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
3060 {
3061 LLVMBuilderRef builder = ctx->ac.builder;
3062 LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
3063 LLVMValueRef tmp;
3064
3065 /* Zero out remaining (non-emitted) primitive flags.
3066 *
3067 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3068 * the emit threads via LDS. This is likely worse in the expected
3069 * typical case where each GS thread emits the full set of
3070 * vertices.
3071 */
3072 for (unsigned stream = 0; stream < 4; ++stream) {
3073 unsigned num_components;
3074
3075 num_components =
3076 ctx->args->shader_info->gs.num_stream_output_components[stream];
3077 if (!num_components)
3078 continue;
3079
3080 const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
3081
3082 ac_build_bgnloop(&ctx->ac, 5100);
3083
3084 const LLVMValueRef vertexidx =
3085 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3086 tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
3087 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3088 ac_build_ifcc(&ctx->ac, tmp, 5101);
3089 ac_build_break(&ctx->ac);
3090 ac_build_endif(&ctx->ac, 5101);
3091
3092 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3093 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3094
3095 tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
3096 LLVMBuildStore(builder, i8_0,
3097 ngg_gs_get_emit_primflag_ptr(ctx, tmp, stream));
3098
3099 ac_build_endloop(&ctx->ac, 5100);
3100 }
3101
3102 /* Accumulate generated primitives counts across the entire threadgroup. */
3103 for (unsigned stream = 0; stream < 4; ++stream) {
3104 unsigned num_components;
3105
3106 num_components =
3107 ctx->args->shader_info->gs.num_stream_output_components[stream];
3108 if (!num_components)
3109 continue;
3110
3111 LLVMValueRef numprims =
3112 LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3113 numprims = ac_build_reduce(&ctx->ac, numprims, nir_op_iadd, ctx->ac.wave_size);
3114
3115 tmp = LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(&ctx->ac), ctx->ac.i32_0, "");
3116 ac_build_ifcc(&ctx->ac, tmp, 5105);
3117 {
3118 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
3119 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
3120 LLVMConstInt(ctx->ac.i32, stream, false)),
3121 numprims, LLVMAtomicOrderingMonotonic, false);
3122 }
3123 ac_build_endif(&ctx->ac, 5105);
3124 }
3125 }
3126
3127 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
3128 {
3129 const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
3130 LLVMBuilderRef builder = ctx->ac.builder;
3131 LLVMValueRef tmp, tmp2;
3132
3133 ac_build_s_barrier(&ctx->ac);
3134
3135 const LLVMValueRef tid = get_thread_id_in_tg(ctx);
3136 LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
3137
3138 /* Streamout */
3139 if (ctx->args->shader_info->so.num_outputs) {
3140 struct ngg_streamout nggso = {};
3141
3142 nggso.num_vertices = LLVMConstInt(ctx->ac.i32, verts_per_prim, false);
3143
3144 LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tid);
3145 for (unsigned stream = 0; stream < 4; ++stream) {
3146 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
3147 continue;
3148
3149 tmp = LLVMBuildLoad(builder,
3150 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream), "");
3151 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3152 tmp2 = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3153 nggso.prim_enable[stream] = LLVMBuildAnd(builder, tmp, tmp2, "");
3154 }
3155
3156 for (unsigned i = 0; i < verts_per_prim; ++i) {
3157 tmp = LLVMBuildSub(builder, tid,
3158 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3159 tmp = ngg_gs_vertex_ptr(ctx, tmp);
3160 nggso.vertices[i] = ac_build_gep0(&ctx->ac, tmp, ctx->ac.i32_0);
3161 }
3162
3163 build_streamout(ctx, &nggso);
3164 }
3165
3166 /* Write shader query data. */
3167 tmp = ac_get_arg(&ctx->ac, ctx->args->ngg_gs_state);
3168 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3169 ac_build_ifcc(&ctx->ac, tmp, 5109);
3170 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid,
3171 LLVMConstInt(ctx->ac.i32, 4, false), "");
3172 ac_build_ifcc(&ctx->ac, tmp, 5110);
3173 {
3174 tmp = LLVMBuildLoad(builder, ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid), "");
3175
3176 ac_llvm_add_target_dep_function_attr(ctx->main_function,
3177 "amdgpu-gds-size", 256);
3178
3179 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
3180 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
3181
3182 const char *sync_scope = LLVM_VERSION_MAJOR >= 9 ? "workgroup-one-as" : "workgroup";
3183
3184 /* Use a plain GDS atomic to accumulate the number of generated
3185 * primitives.
3186 */
3187 ac_build_atomic_rmw(&ctx->ac, LLVMAtomicRMWBinOpAdd, gdsbase,
3188 tmp, sync_scope);
3189 }
3190 ac_build_endif(&ctx->ac, 5110);
3191 ac_build_endif(&ctx->ac, 5109);
3192
3193 /* TODO: culling */
3194
3195 /* Determine vertex liveness. */
3196 LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
3197
3198 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3199 ac_build_ifcc(&ctx->ac, tmp, 5120);
3200 {
3201 for (unsigned i = 0; i < verts_per_prim; ++i) {
3202 const LLVMValueRef primidx =
3203 LLVMBuildAdd(builder, tid,
3204 LLVMConstInt(ctx->ac.i32, i, false), "");
3205
3206 if (i > 0) {
3207 tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
3208 ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
3209 }
3210
3211 /* Load primitive liveness */
3212 tmp = ngg_gs_vertex_ptr(ctx, primidx);
3213 tmp = LLVMBuildLoad(builder,
3214 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3215 const LLVMValueRef primlive =
3216 LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3217
3218 tmp = LLVMBuildLoad(builder, vertliveptr, "");
3219 tmp = LLVMBuildOr(builder, tmp, primlive, ""),
3220 LLVMBuildStore(builder, tmp, vertliveptr);
3221
3222 if (i > 0)
3223 ac_build_endif(&ctx->ac, 5121 + i);
3224 }
3225 }
3226 ac_build_endif(&ctx->ac, 5120);
3227
3228 /* Inclusive scan addition across the current wave. */
3229 LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
3230 struct ac_wg_scan vertlive_scan = {};
3231 vertlive_scan.op = nir_op_iadd;
3232 vertlive_scan.enable_reduce = true;
3233 vertlive_scan.enable_exclusive = true;
3234 vertlive_scan.src = vertlive;
3235 vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
3236 vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
3237 vertlive_scan.numwaves = get_tgsize(ctx);
3238 vertlive_scan.maxwaves = 8;
3239
3240 ac_build_wg_scan(&ctx->ac, &vertlive_scan);
3241
3242 /* Skip all exports (including index exports) when possible. At least on
3243 * early gfx10 revisions this is also to avoid hangs.
3244 */
3245 LLVMValueRef have_exports =
3246 LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
3247 num_emit_threads =
3248 LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
3249
3250 /* Allocate export space. Send this message as early as possible, to
3251 * hide the latency of the SQ <-> SPI roundtrip.
3252 *
3253 * Note: We could consider compacting primitives for export as well.
3254 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3255 * prim data per clock and skips null primitives at no additional
3256 * cost. So compacting primitives can only be beneficial when
3257 * there are 4 or more contiguous null primitives in the export
3258 * (in the common case of single-dword prim exports).
3259 */
3260 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
3261 vertlive_scan.result_reduce, num_emit_threads);
3262
3263 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3264 * of the primitive liveness flags, relying on the fact that each
3265 * threadgroup can have at most 256 threads. */
3266 ac_build_ifcc(&ctx->ac, vertlive, 5130);
3267 {
3268 tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
3269 tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
3270 LLVMBuildStore(builder, tmp2,
3271 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1));
3272 }
3273 ac_build_endif(&ctx->ac, 5130);
3274
3275 ac_build_s_barrier(&ctx->ac);
3276
3277 /* Export primitive data */
3278 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3279 ac_build_ifcc(&ctx->ac, tmp, 5140);
3280 {
3281 LLVMValueRef flags;
3282 struct ac_ngg_prim prim = {};
3283 prim.num_vertices = verts_per_prim;
3284
3285 tmp = ngg_gs_vertex_ptr(ctx, tid);
3286 flags = LLVMBuildLoad(builder,
3287 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3288 prim.isnull = LLVMBuildNot(builder, LLVMBuildTrunc(builder, flags, ctx->ac.i1, ""), "");
3289
3290 for (unsigned i = 0; i < verts_per_prim; ++i) {
3291 prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
3292 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3293 prim.edgeflag[i] = ctx->ac.i1false;
3294 }
3295
3296 /* Geometry shaders output triangle strips, but NGG expects
3297 * triangles. We need to change the vertex order for odd
3298 * triangles to get correct front/back facing by swapping 2
3299 * vertex indices, but we also have to keep the provoking
3300 * vertex in the same place.
3301 */
3302 if (verts_per_prim == 3) {
3303 LLVMValueRef is_odd = LLVMBuildLShr(builder, flags, ctx->ac.i8_1, "");
3304 is_odd = LLVMBuildTrunc(builder, is_odd, ctx->ac.i1, "");
3305
3306 struct ac_ngg_prim in = prim;
3307 prim.index[0] = in.index[0];
3308 prim.index[1] = LLVMBuildSelect(builder, is_odd,
3309 in.index[2], in.index[1], "");
3310 prim.index[2] = LLVMBuildSelect(builder, is_odd,
3311 in.index[1], in.index[2], "");
3312 }
3313
3314 ac_build_export_prim(&ctx->ac, &prim);
3315 }
3316 ac_build_endif(&ctx->ac, 5140);
3317
3318 /* Export position and parameter data */
3319 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
3320 ac_build_ifcc(&ctx->ac, tmp, 5145);
3321 {
3322 struct radv_vs_output_info *outinfo = &ctx->args->shader_info->vs.outinfo;
3323 bool export_view_index = ctx->args->options->key.has_multiview_view_index;
3324 struct radv_shader_output_values *outputs;
3325 unsigned noutput = 0;
3326
3327 /* Allocate a temporary array for the output values. */
3328 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
3329 outputs = calloc(num_outputs, sizeof(outputs[0]));
3330
3331 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
3332 sizeof(outinfo->vs_output_param_offset));
3333 outinfo->pos_exports = 0;
3334
3335 tmp = ngg_gs_vertex_ptr(ctx, tid);
3336 tmp = LLVMBuildLoad(builder,
3337 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1), "");
3338 tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
3339 const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
3340
3341 unsigned out_idx = 0;
3342 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3343 unsigned output_usage_mask =
3344 ctx->args->shader_info->gs.output_usage_mask[i];
3345 int length = util_last_bit(output_usage_mask);
3346
3347 if (!(ctx->output_mask & (1ull << i)))
3348 continue;
3349
3350 outputs[noutput].slot_name = i;
3351 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
3352 outputs[noutput].usage_mask = output_usage_mask;
3353
3354 for (unsigned j = 0; j < length; j++, out_idx++) {
3355 if (!(output_usage_mask & (1 << j)))
3356 continue;
3357
3358 tmp = ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx);
3359 tmp = LLVMBuildLoad(builder, tmp, "");
3360
3361 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3362 if (ac_get_type_size(type) == 2) {
3363 tmp = ac_to_integer(&ctx->ac, tmp);
3364 tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
3365 }
3366
3367 outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
3368 }
3369
3370 for (unsigned j = length; j < 4; j++)
3371 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
3372
3373 noutput++;
3374 }
3375
3376 /* Export ViewIndex. */
3377 if (export_view_index) {
3378 outputs[noutput].slot_name = VARYING_SLOT_LAYER;
3379 outputs[noutput].slot_index = 0;
3380 outputs[noutput].usage_mask = 0x1;
3381 outputs[noutput].values[0] =
3382 ac_to_float(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.view_index));
3383 for (unsigned j = 1; j < 4; j++)
3384 outputs[noutput].values[j] = ctx->ac.f32_0;
3385 noutput++;
3386 }
3387
3388 radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
3389 ctx->args->options->key.vs_common_out.export_clip_dists);
3390 FREE(outputs);
3391 }
3392 ac_build_endif(&ctx->ac, 5145);
3393 }
3394
3395 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
3396 unsigned stream,
3397 LLVMValueRef *addrs)
3398 {
3399 LLVMBuilderRef builder = ctx->ac.builder;
3400 LLVMValueRef tmp;
3401 const LLVMValueRef vertexidx =
3402 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3403
3404 /* If this thread has already emitted the declared maximum number of
3405 * vertices, skip the write: excessive vertex emissions are not
3406 * supposed to have any effect.
3407 */
3408 const LLVMValueRef can_emit =
3409 LLVMBuildICmp(builder, LLVMIntULT, vertexidx,
3410 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3411 ac_build_ifcc(&ctx->ac, can_emit, 9001);
3412
3413 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3414 tmp = LLVMBuildSelect(builder, can_emit, tmp, vertexidx, "");
3415 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3416
3417 const LLVMValueRef vertexptr =
3418 ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
3419 unsigned out_idx = 0;
3420 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3421 unsigned output_usage_mask =
3422 ctx->args->shader_info->gs.output_usage_mask[i];
3423 uint8_t output_stream =
3424 ctx->args->shader_info->gs.output_streams[i];
3425 LLVMValueRef *out_ptr = &addrs[i * 4];
3426 int length = util_last_bit(output_usage_mask);
3427
3428 if (!(ctx->output_mask & (1ull << i)) ||
3429 output_stream != stream)
3430 continue;
3431
3432 for (unsigned j = 0; j < length; j++, out_idx++) {
3433 if (!(output_usage_mask & (1 << j)))
3434 continue;
3435
3436 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
3437 out_ptr[j], "");
3438 out_val = ac_to_integer(&ctx->ac, out_val);
3439 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
3440
3441 LLVMBuildStore(builder, out_val,
3442 ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx));
3443 }
3444 }
3445 assert(out_idx * 4 <= ctx->args->shader_info->gs.gsvs_vertex_size);
3446
3447 /* Determine and store whether this vertex completed a primitive. */
3448 const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
3449
3450 tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
3451 const LLVMValueRef iscompleteprim =
3452 LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
3453
3454 /* Since the geometry shader emits triangle strips, we need to
3455 * track which primitive is odd and swap vertex indices to get
3456 * the correct vertex order.
3457 */
3458 LLVMValueRef is_odd = ctx->ac.i1false;
3459 if (stream == 0 &&
3460 si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) == 3) {
3461 tmp = LLVMBuildAnd(builder, curverts, ctx->ac.i32_1, "");
3462 is_odd = LLVMBuildICmp(builder, LLVMIntEQ, tmp, ctx->ac.i32_1, "");
3463 }
3464
3465 tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
3466 LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
3467
3468 /* The per-vertex primitive flag encoding:
3469 * bit 0: whether this vertex finishes a primitive
3470 * bit 1: whether the primitive is odd (if we are emitting triangle strips)
3471 */
3472 tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
3473 tmp = LLVMBuildOr(builder, tmp,
3474 LLVMBuildShl(builder,
3475 LLVMBuildZExt(builder, is_odd, ctx->ac.i8, ""),
3476 ctx->ac.i8_1, ""), "");
3477 LLVMBuildStore(builder, tmp,
3478 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream));
3479
3480 tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3481 tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
3482 LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
3483
3484 ac_build_endif(&ctx->ac, 9001);
3485 }
3486
3487 static void
3488 write_tess_factors(struct radv_shader_context *ctx)
3489 {
3490 unsigned stride, outer_comps, inner_comps;
3491 LLVMValueRef tcs_rel_ids = ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids);
3492 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 8, 5);
3493 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 0, 8);
3494 unsigned tess_inner_index = 0, tess_outer_index;
3495 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
3496 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3497 int i;
3498 ac_emit_barrier(&ctx->ac, ctx->stage);
3499
3500 switch (ctx->args->options->key.tcs.primitive_mode) {
3501 case GL_ISOLINES:
3502 stride = 2;
3503 outer_comps = 2;
3504 inner_comps = 0;
3505 break;
3506 case GL_TRIANGLES:
3507 stride = 4;
3508 outer_comps = 3;
3509 inner_comps = 1;
3510 break;
3511 case GL_QUADS:
3512 stride = 6;
3513 outer_comps = 4;
3514 inner_comps = 2;
3515 break;
3516 default:
3517 return;
3518 }
3519
3520 ac_build_ifcc(&ctx->ac,
3521 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3522 invocation_id, ctx->ac.i32_0, ""), 6503);
3523
3524 lds_base = get_tcs_out_current_patch_data_offset(ctx);
3525
3526 if (inner_comps) {
3527 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3528 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3529 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3530 }
3531
3532 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3533 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3534 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3535
3536 for (i = 0; i < 4; i++) {
3537 inner[i] = LLVMGetUndef(ctx->ac.i32);
3538 outer[i] = LLVMGetUndef(ctx->ac.i32);
3539 }
3540
3541 // LINES reversal
3542 if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
3543 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3544 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3545 ctx->ac.i32_1, "");
3546 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3547 } else {
3548 for (i = 0; i < outer_comps; i++) {
3549 outer[i] = out[i] =
3550 ac_lds_load(&ctx->ac, lds_outer);
3551 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3552 ctx->ac.i32_1, "");
3553 }
3554 for (i = 0; i < inner_comps; i++) {
3555 inner[i] = out[outer_comps+i] =
3556 ac_lds_load(&ctx->ac, lds_inner);
3557 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3558 ctx->ac.i32_1, "");
3559 }
3560 }
3561
3562 /* Convert the outputs to vectors for stores. */
3563 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3564 vec1 = NULL;
3565
3566 if (stride > 4)
3567 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3568
3569
3570 buffer = ctx->hs_ring_tess_factor;
3571 tf_base = ac_get_arg(&ctx->ac, ctx->args->tess_factor_offset);
3572 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3573 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3574 unsigned tf_offset = 0;
3575
3576 if (ctx->ac.chip_class <= GFX8) {
3577 ac_build_ifcc(&ctx->ac,
3578 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3579 rel_patch_id, ctx->ac.i32_0, ""), 6504);
3580
3581 /* Store the dynamic HS control word. */
3582 ac_build_buffer_store_dword(&ctx->ac, buffer,
3583 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3584 1, ctx->ac.i32_0, tf_base,
3585 0, ac_glc);
3586 tf_offset += 4;
3587
3588 ac_build_endif(&ctx->ac, 6504);
3589 }
3590
3591 /* Store the tessellation factors. */
3592 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3593 MIN2(stride, 4), byteoffset, tf_base,
3594 tf_offset, ac_glc);
3595 if (vec1)
3596 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3597 stride - 4, byteoffset, tf_base,
3598 16 + tf_offset, ac_glc);
3599
3600 //store to offchip for TES to read - only if TES reads them
3601 if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
3602 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3603 LLVMValueRef tf_inner_offset;
3604 unsigned param_outer, param_inner;
3605
3606 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3607 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3608 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3609
3610 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3611 util_next_power_of_two(outer_comps));
3612
3613 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3614 outer_comps, tf_outer_offset,
3615 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3616 0, ac_glc);
3617 if (inner_comps) {
3618 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3619 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3620 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3621
3622 inner_vec = inner_comps == 1 ? inner[0] :
3623 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3624 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3625 inner_comps, tf_inner_offset,
3626 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3627 0, ac_glc);
3628 }
3629 }
3630
3631 ac_build_endif(&ctx->ac, 6503);
3632 }
3633
3634 static void
3635 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3636 {
3637 write_tess_factors(ctx);
3638 }
3639
3640 static bool
3641 si_export_mrt_color(struct radv_shader_context *ctx,
3642 LLVMValueRef *color, unsigned index,
3643 struct ac_export_args *args)
3644 {
3645 /* Export */
3646 si_llvm_init_export_args(ctx, color, 0xf,
3647 V_008DFC_SQ_EXP_MRT + index, args);
3648 if (!args->enabled_channels)
3649 return false; /* unnecessary NULL export */
3650
3651 return true;
3652 }
3653
3654 static void
3655 radv_export_mrt_z(struct radv_shader_context *ctx,
3656 LLVMValueRef depth, LLVMValueRef stencil,
3657 LLVMValueRef samplemask)
3658 {
3659 struct ac_export_args args;
3660
3661 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3662
3663 ac_build_export(&ctx->ac, &args);
3664 }
3665
3666 static void
3667 handle_fs_outputs_post(struct radv_shader_context *ctx)
3668 {
3669 unsigned index = 0;
3670 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3671 struct ac_export_args color_args[8];
3672
3673 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3674 LLVMValueRef values[4];
3675
3676 if (!(ctx->output_mask & (1ull << i)))
3677 continue;
3678
3679 if (i < FRAG_RESULT_DATA0)
3680 continue;
3681
3682 for (unsigned j = 0; j < 4; j++)
3683 values[j] = ac_to_float(&ctx->ac,
3684 radv_load_output(ctx, i, j));
3685
3686 bool ret = si_export_mrt_color(ctx, values,
3687 i - FRAG_RESULT_DATA0,
3688 &color_args[index]);
3689 if (ret)
3690 index++;
3691 }
3692
3693 /* Process depth, stencil, samplemask. */
3694 if (ctx->args->shader_info->ps.writes_z) {
3695 depth = ac_to_float(&ctx->ac,
3696 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3697 }
3698 if (ctx->args->shader_info->ps.writes_stencil) {
3699 stencil = ac_to_float(&ctx->ac,
3700 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3701 }
3702 if (ctx->args->shader_info->ps.writes_sample_mask) {
3703 samplemask = ac_to_float(&ctx->ac,
3704 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3705 }
3706
3707 /* Set the DONE bit on last non-null color export only if Z isn't
3708 * exported.
3709 */
3710 if (index > 0 &&
3711 !ctx->args->shader_info->ps.writes_z &&
3712 !ctx->args->shader_info->ps.writes_stencil &&
3713 !ctx->args->shader_info->ps.writes_sample_mask) {
3714 unsigned last = index - 1;
3715
3716 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3717 color_args[last].done = 1; /* DONE bit */
3718 }
3719
3720 /* Export PS outputs. */
3721 for (unsigned i = 0; i < index; i++)
3722 ac_build_export(&ctx->ac, &color_args[i]);
3723
3724 if (depth || stencil || samplemask)
3725 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3726 else if (!index)
3727 ac_build_export_null(&ctx->ac);
3728 }
3729
3730 static void
3731 emit_gs_epilogue(struct radv_shader_context *ctx)
3732 {
3733 if (ctx->args->options->key.vs_common_out.as_ngg) {
3734 gfx10_ngg_gs_emit_epilogue_1(ctx);
3735 return;
3736 }
3737
3738 if (ctx->ac.chip_class >= GFX10)
3739 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3740
3741 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3742 }
3743
3744 static void
3745 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3746 LLVMValueRef *addrs)
3747 {
3748 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3749
3750 switch (ctx->stage) {
3751 case MESA_SHADER_VERTEX:
3752 if (ctx->args->options->key.vs_common_out.as_ls)
3753 handle_ls_outputs_post(ctx);
3754 else if (ctx->args->options->key.vs_common_out.as_es)
3755 handle_es_outputs_post(ctx, &ctx->args->shader_info->vs.es_info);
3756 else if (ctx->args->options->key.vs_common_out.as_ngg)
3757 handle_ngg_outputs_post_1(ctx);
3758 else
3759 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3760 ctx->args->options->key.vs_common_out.export_clip_dists,
3761 &ctx->args->shader_info->vs.outinfo);
3762 break;
3763 case MESA_SHADER_FRAGMENT:
3764 handle_fs_outputs_post(ctx);
3765 break;
3766 case MESA_SHADER_GEOMETRY:
3767 emit_gs_epilogue(ctx);
3768 break;
3769 case MESA_SHADER_TESS_CTRL:
3770 handle_tcs_outputs_post(ctx);
3771 break;
3772 case MESA_SHADER_TESS_EVAL:
3773 if (ctx->args->options->key.vs_common_out.as_es)
3774 handle_es_outputs_post(ctx, &ctx->args->shader_info->tes.es_info);
3775 else if (ctx->args->options->key.vs_common_out.as_ngg)
3776 handle_ngg_outputs_post_1(ctx);
3777 else
3778 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3779 ctx->args->options->key.vs_common_out.export_clip_dists,
3780 &ctx->args->shader_info->tes.outinfo);
3781 break;
3782 default:
3783 break;
3784 }
3785 }
3786
3787 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3788 LLVMPassManagerRef passmgr,
3789 const struct radv_nir_compiler_options *options)
3790 {
3791 LLVMRunPassManager(passmgr, ctx->ac.module);
3792 LLVMDisposeBuilder(ctx->ac.builder);
3793
3794 ac_llvm_context_dispose(&ctx->ac);
3795 }
3796
3797 static void
3798 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3799 {
3800 struct radv_vs_output_info *outinfo;
3801
3802 switch (ctx->stage) {
3803 case MESA_SHADER_FRAGMENT:
3804 case MESA_SHADER_COMPUTE:
3805 case MESA_SHADER_TESS_CTRL:
3806 case MESA_SHADER_GEOMETRY:
3807 return;
3808 case MESA_SHADER_VERTEX:
3809 if (ctx->args->options->key.vs_common_out.as_ls ||
3810 ctx->args->options->key.vs_common_out.as_es)
3811 return;
3812 outinfo = &ctx->args->shader_info->vs.outinfo;
3813 break;
3814 case MESA_SHADER_TESS_EVAL:
3815 if (ctx->args->options->key.vs_common_out.as_es)
3816 return;
3817 outinfo = &ctx->args->shader_info->tes.outinfo;
3818 break;
3819 default:
3820 unreachable("Unhandled shader type");
3821 }
3822
3823 ac_optimize_vs_outputs(&ctx->ac,
3824 ctx->main_function,
3825 outinfo->vs_output_param_offset,
3826 VARYING_SLOT_MAX,
3827 &outinfo->param_exports);
3828 }
3829
3830 static void
3831 ac_setup_rings(struct radv_shader_context *ctx)
3832 {
3833 if (ctx->args->options->chip_class <= GFX8 &&
3834 (ctx->stage == MESA_SHADER_GEOMETRY ||
3835 ctx->args->options->key.vs_common_out.as_es || ctx->args->options->key.vs_common_out.as_es)) {
3836 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3837 : RING_ESGS_VS;
3838 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3839
3840 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3841 ctx->ring_offsets,
3842 offset);
3843 }
3844
3845 if (ctx->args->is_gs_copy_shader) {
3846 ctx->gsvs_ring[0] =
3847 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3848 LLVMConstInt(ctx->ac.i32,
3849 RING_GSVS_VS, false));
3850 }
3851
3852 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3853 /* The conceptual layout of the GSVS ring is
3854 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3855 * but the real memory layout is swizzled across
3856 * threads:
3857 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3858 * t16v0c0 ..
3859 * Override the buffer descriptor accordingly.
3860 */
3861 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3862 uint64_t stream_offset = 0;
3863 unsigned num_records = ctx->ac.wave_size;
3864 LLVMValueRef base_ring;
3865
3866 base_ring =
3867 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3868 LLVMConstInt(ctx->ac.i32,
3869 RING_GSVS_GS, false));
3870
3871 for (unsigned stream = 0; stream < 4; stream++) {
3872 unsigned num_components, stride;
3873 LLVMValueRef ring, tmp;
3874
3875 num_components =
3876 ctx->args->shader_info->gs.num_stream_output_components[stream];
3877
3878 if (!num_components)
3879 continue;
3880
3881 stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
3882
3883 /* Limit on the stride field for <= GFX7. */
3884 assert(stride < (1 << 14));
3885
3886 ring = LLVMBuildBitCast(ctx->ac.builder,
3887 base_ring, v2i64, "");
3888 tmp = LLVMBuildExtractElement(ctx->ac.builder,
3889 ring, ctx->ac.i32_0, "");
3890 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
3891 LLVMConstInt(ctx->ac.i64,
3892 stream_offset, 0), "");
3893 ring = LLVMBuildInsertElement(ctx->ac.builder,
3894 ring, tmp, ctx->ac.i32_0, "");
3895
3896 stream_offset += stride * ctx->ac.wave_size;
3897
3898 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
3899 ctx->ac.v4i32, "");
3900
3901 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3902 ctx->ac.i32_1, "");
3903 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3904 LLVMConstInt(ctx->ac.i32,
3905 S_008F04_STRIDE(stride), false), "");
3906 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3907 ctx->ac.i32_1, "");
3908
3909 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3910 LLVMConstInt(ctx->ac.i32,
3911 num_records, false),
3912 LLVMConstInt(ctx->ac.i32, 2, false), "");
3913
3914 ctx->gsvs_ring[stream] = ring;
3915 }
3916 }
3917
3918 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3919 ctx->stage == MESA_SHADER_TESS_EVAL) {
3920 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3921 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3922 }
3923 }
3924
3925 unsigned
3926 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
3927 gl_shader_stage stage,
3928 const struct nir_shader *nir)
3929 {
3930 const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
3931 unsigned sizes[3];
3932 for (unsigned i = 0; i < 3; i++)
3933 sizes[i] = nir ? nir->info.cs.local_size[i] : backup_sizes[i];
3934 return radv_get_max_workgroup_size(chip_class, stage, sizes);
3935 }
3936
3937 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3938 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3939 {
3940 LLVMValueRef count =
3941 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
3942 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3943 ctx->ac.i32_0, "");
3944 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3945 ac_get_arg(&ctx->ac, ctx->args->rel_auto_id),
3946 ctx->abi.instance_id, "");
3947 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3948 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
3949 ctx->rel_auto_id,
3950 "");
3951 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3952 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_patch_id),
3953 ctx->abi.vertex_id, "");
3954 }
3955
3956 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx, bool merged)
3957 {
3958 if (merged) {
3959 for(int i = 5; i >= 0; --i) {
3960 ctx->gs_vtx_offset[i] =
3961 ac_unpack_param(&ctx->ac,
3962 ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i & ~1]),
3963 (i & 1) * 16, 16);
3964 }
3965
3966 ctx->gs_wave_id = ac_unpack_param(&ctx->ac,
3967 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info),
3968 16, 8);
3969 } else {
3970 for (int i = 0; i < 6; i++)
3971 ctx->gs_vtx_offset[i] = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i]);
3972 ctx->gs_wave_id = ac_get_arg(&ctx->ac, ctx->args->gs_wave_id);
3973 }
3974 }
3975
3976 /* Ensure that the esgs ring is declared.
3977 *
3978 * We declare it with 64KB alignment as a hint that the
3979 * pointer value will always be 0.
3980 */
3981 static void declare_esgs_ring(struct radv_shader_context *ctx)
3982 {
3983 if (ctx->esgs_ring)
3984 return;
3985
3986 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
3987
3988 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
3989 ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
3990 "esgs_ring",
3991 AC_ADDR_SPACE_LDS);
3992 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
3993 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
3994 }
3995
3996 static
3997 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
3998 struct nir_shader *const *shaders,
3999 int shader_count,
4000 const struct radv_shader_args *args)
4001 {
4002 struct radv_shader_context ctx = {0};
4003 ctx.args = args;
4004
4005 enum ac_float_mode float_mode = AC_FLOAT_MODE_DEFAULT;
4006
4007 if (args->shader_info->float_controls_mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32) {
4008 float_mode = AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO;
4009 }
4010
4011 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
4012 args->options->family, float_mode,
4013 args->shader_info->wave_size, 64);
4014 ctx.context = ctx.ac.context;
4015
4016 ctx.max_workgroup_size = 0;
4017 for (int i = 0; i < shader_count; ++i) {
4018 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
4019 radv_nir_get_max_workgroup_size(args->options->chip_class,
4020 shaders[i]->info.stage,
4021 shaders[i]));
4022 }
4023
4024 if (ctx.ac.chip_class >= GFX10) {
4025 if (is_pre_gs_stage(shaders[0]->info.stage) &&
4026 args->options->key.vs_common_out.as_ngg) {
4027 ctx.max_workgroup_size = 128;
4028 }
4029 }
4030
4031 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2);
4032
4033 ctx.abi.inputs = &ctx.inputs[0];
4034 ctx.abi.emit_outputs = handle_shader_outputs_post;
4035 ctx.abi.emit_vertex = visit_emit_vertex;
4036 ctx.abi.load_ubo = radv_load_ubo;
4037 ctx.abi.load_ssbo = radv_load_ssbo;
4038 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
4039 ctx.abi.load_resource = radv_load_resource;
4040 ctx.abi.clamp_shadow_reference = false;
4041 ctx.abi.robust_buffer_access = args->options->robust_buffer_access;
4042
4043 bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && args->options->key.vs_common_out.as_ngg;
4044 if (shader_count >= 2 || is_ngg)
4045 ac_init_exec_full_mask(&ctx.ac);
4046
4047 if (args->ac.vertex_id.used)
4048 ctx.abi.vertex_id = ac_get_arg(&ctx.ac, args->ac.vertex_id);
4049 if (args->rel_auto_id.used)
4050 ctx.rel_auto_id = ac_get_arg(&ctx.ac, args->rel_auto_id);
4051 if (args->ac.instance_id.used)
4052 ctx.abi.instance_id = ac_get_arg(&ctx.ac, args->ac.instance_id);
4053
4054 if (args->options->has_ls_vgpr_init_bug &&
4055 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
4056 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
4057
4058 if (is_ngg) {
4059 /* Declare scratch space base for streamout and vertex
4060 * compaction. Whether space is actually allocated is
4061 * determined during linking / PM4 creation.
4062 *
4063 * Add an extra dword per vertex to ensure an odd stride, which
4064 * avoids bank conflicts for SoA accesses.
4065 */
4066 if (!args->options->key.vs_common_out.as_ngg_passthrough)
4067 declare_esgs_ring(&ctx);
4068
4069 /* This is really only needed when streamout and / or vertex
4070 * compaction is enabled.
4071 */
4072 if (args->shader_info->so.num_outputs) {
4073 LLVMTypeRef asi32 = LLVMArrayType(ctx.ac.i32, 8);
4074 ctx.gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4075 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4076 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(asi32));
4077 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4078 }
4079 }
4080
4081 for(int i = 0; i < shader_count; ++i) {
4082 ctx.stage = shaders[i]->info.stage;
4083 ctx.shader = shaders[i];
4084 ctx.output_mask = 0;
4085
4086 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
4087 for (int i = 0; i < 4; i++) {
4088 ctx.gs_next_vertex[i] =
4089 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4090 }
4091 if (args->options->key.vs_common_out.as_ngg) {
4092 for (unsigned i = 0; i < 4; ++i) {
4093 ctx.gs_curprim_verts[i] =
4094 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4095 ctx.gs_generated_prims[i] =
4096 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4097 }
4098
4099 unsigned scratch_size = 8;
4100 if (args->shader_info->so.num_outputs)
4101 scratch_size = 44;
4102
4103 LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, scratch_size);
4104 ctx.gs_ngg_scratch =
4105 LLVMAddGlobalInAddressSpace(ctx.ac.module,
4106 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4107 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
4108 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4109
4110 ctx.gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4111 LLVMArrayType(ctx.ac.i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
4112 LLVMSetLinkage(ctx.gs_ngg_emit, LLVMExternalLinkage);
4113 LLVMSetAlignment(ctx.gs_ngg_emit, 4);
4114 }
4115
4116 ctx.abi.load_inputs = load_gs_input;
4117 ctx.abi.emit_primitive = visit_end_primitive;
4118 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4119 ctx.abi.load_tess_varyings = load_tcs_varyings;
4120 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4121 ctx.abi.store_tcs_outputs = store_tcs_output;
4122 if (shader_count == 1)
4123 ctx.tcs_num_inputs = args->options->key.tcs.num_inputs;
4124 else
4125 ctx.tcs_num_inputs = util_last_bit64(args->shader_info->vs.ls_outputs_written);
4126 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
4127 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
4128 ctx.abi.load_tess_varyings = load_tes_input;
4129 ctx.abi.load_tess_coord = load_tess_coord;
4130 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4131 ctx.tcs_num_patches = args->options->key.tes.num_patches;
4132 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
4133 ctx.abi.load_base_vertex = radv_load_base_vertex;
4134 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
4135 ctx.abi.load_sample_position = load_sample_position;
4136 ctx.abi.load_sample_mask_in = load_sample_mask_in;
4137 }
4138
4139 if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
4140 args->options->key.vs_common_out.as_ngg &&
4141 args->options->key.vs_common_out.export_prim_id) {
4142 declare_esgs_ring(&ctx);
4143 }
4144
4145 bool nested_barrier = false;
4146
4147 if (i) {
4148 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4149 args->options->key.vs_common_out.as_ngg) {
4150 gfx10_ngg_gs_emit_prologue(&ctx);
4151 nested_barrier = false;
4152 } else {
4153 nested_barrier = true;
4154 }
4155 }
4156
4157 if (nested_barrier) {
4158 /* Execute a barrier before the second shader in
4159 * a merged shader.
4160 *
4161 * Execute the barrier inside the conditional block,
4162 * so that empty waves can jump directly to s_endpgm,
4163 * which will also signal the barrier.
4164 *
4165 * This is possible in gfx9, because an empty wave
4166 * for the second shader does not participate in
4167 * the epilogue. With NGG, empty waves may still
4168 * be required to export data (e.g. GS output vertices),
4169 * so we cannot let them exit early.
4170 *
4171 * If the shader is TCS and the TCS epilog is present
4172 * and contains a barrier, it will wait there and then
4173 * reach s_endpgm.
4174 */
4175 ac_emit_barrier(&ctx.ac, ctx.stage);
4176 }
4177
4178 nir_foreach_variable(variable, &shaders[i]->outputs)
4179 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
4180
4181 ac_setup_rings(&ctx);
4182
4183 LLVMBasicBlockRef merge_block = NULL;
4184 if (shader_count >= 2 || is_ngg) {
4185 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
4186 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4187 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4188
4189 LLVMValueRef count =
4190 ac_unpack_param(&ctx.ac,
4191 ac_get_arg(&ctx.ac, args->merged_wave_info),
4192 8 * i, 8);
4193 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
4194 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
4195 thread_id, count, "");
4196 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
4197
4198 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
4199 }
4200
4201 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
4202 prepare_interp_optimize(&ctx, shaders[i]);
4203 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
4204 handle_vs_inputs(&ctx, shaders[i]);
4205 else if(shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
4206 prepare_gs_input_vgprs(&ctx, shader_count >= 2);
4207
4208 ac_nir_translate(&ctx.ac, &ctx.abi, &args->ac, shaders[i]);
4209
4210 if (shader_count >= 2 || is_ngg) {
4211 LLVMBuildBr(ctx.ac.builder, merge_block);
4212 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
4213 }
4214
4215 /* This needs to be outside the if wrapping the shader body, as sometimes
4216 * the HW generates waves with 0 es/vs threads. */
4217 if (is_pre_gs_stage(shaders[i]->info.stage) &&
4218 args->options->key.vs_common_out.as_ngg &&
4219 i == shader_count - 1) {
4220 handle_ngg_outputs_post_2(&ctx);
4221 } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4222 args->options->key.vs_common_out.as_ngg) {
4223 gfx10_ngg_gs_emit_epilogue_2(&ctx);
4224 }
4225
4226 if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4227 args->shader_info->tcs.num_patches = ctx.tcs_num_patches;
4228 args->shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
4229 }
4230 }
4231
4232 LLVMBuildRetVoid(ctx.ac.builder);
4233
4234 if (args->options->dump_preoptir) {
4235 fprintf(stderr, "%s LLVM IR:\n\n",
4236 radv_get_shader_name(args->shader_info,
4237 shaders[shader_count - 1]->info.stage));
4238 ac_dump_module(ctx.ac.module);
4239 fprintf(stderr, "\n");
4240 }
4241
4242 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4243
4244 if (shader_count == 1)
4245 ac_nir_eliminate_const_vs_outputs(&ctx);
4246
4247 if (args->options->dump_shader) {
4248 args->shader_info->private_mem_vgprs =
4249 ac_count_scratch_private_memory(ctx.main_function);
4250 }
4251
4252 return ctx.ac.module;
4253 }
4254
4255 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4256 {
4257 unsigned *retval = (unsigned *)context;
4258 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4259 char *description = LLVMGetDiagInfoDescription(di);
4260
4261 if (severity == LLVMDSError) {
4262 *retval = 1;
4263 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4264 description);
4265 }
4266
4267 LLVMDisposeMessage(description);
4268 }
4269
4270 static unsigned radv_llvm_compile(LLVMModuleRef M,
4271 char **pelf_buffer, size_t *pelf_size,
4272 struct ac_llvm_compiler *ac_llvm)
4273 {
4274 unsigned retval = 0;
4275 LLVMContextRef llvm_ctx;
4276
4277 /* Setup Diagnostic Handler*/
4278 llvm_ctx = LLVMGetModuleContext(M);
4279
4280 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4281 &retval);
4282
4283 /* Compile IR*/
4284 if (!radv_compile_to_elf(ac_llvm, M, pelf_buffer, pelf_size))
4285 retval = 1;
4286 return retval;
4287 }
4288
4289 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
4290 LLVMModuleRef llvm_module,
4291 struct radv_shader_binary **rbinary,
4292 gl_shader_stage stage,
4293 const char *name,
4294 const struct radv_nir_compiler_options *options)
4295 {
4296 char *elf_buffer = NULL;
4297 size_t elf_size = 0;
4298 char *llvm_ir_string = NULL;
4299
4300 if (options->dump_shader) {
4301 fprintf(stderr, "%s LLVM IR:\n\n", name);
4302 ac_dump_module(llvm_module);
4303 fprintf(stderr, "\n");
4304 }
4305
4306 if (options->record_ir) {
4307 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
4308 llvm_ir_string = strdup(llvm_ir);
4309 LLVMDisposeMessage(llvm_ir);
4310 }
4311
4312 int v = radv_llvm_compile(llvm_module, &elf_buffer, &elf_size, ac_llvm);
4313 if (v) {
4314 fprintf(stderr, "compile failed\n");
4315 }
4316
4317 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4318 LLVMDisposeModule(llvm_module);
4319 LLVMContextDispose(ctx);
4320
4321 size_t llvm_ir_size = llvm_ir_string ? strlen(llvm_ir_string) : 0;
4322 size_t alloc_size = sizeof(struct radv_shader_binary_rtld) + elf_size + llvm_ir_size + 1;
4323 struct radv_shader_binary_rtld *rbin = calloc(1, alloc_size);
4324 memcpy(rbin->data, elf_buffer, elf_size);
4325 if (llvm_ir_string)
4326 memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
4327
4328 rbin->base.type = RADV_BINARY_TYPE_RTLD;
4329 rbin->base.stage = stage;
4330 rbin->base.total_size = alloc_size;
4331 rbin->elf_size = elf_size;
4332 rbin->llvm_ir_size = llvm_ir_size;
4333 *rbinary = &rbin->base;
4334
4335 free(llvm_ir_string);
4336 free(elf_buffer);
4337 }
4338
4339 void
4340 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
4341 struct radv_shader_binary **rbinary,
4342 const struct radv_shader_args *args,
4343 struct nir_shader *const *nir,
4344 int nir_count)
4345 {
4346
4347 LLVMModuleRef llvm_module;
4348
4349 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, args);
4350
4351 ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
4352 nir[nir_count - 1]->info.stage,
4353 radv_get_shader_name(args->shader_info,
4354 nir[nir_count - 1]->info.stage),
4355 args->options);
4356
4357 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4358 if (args->options->chip_class >= GFX9) {
4359 if (nir_count == 2 &&
4360 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
4361 args->shader_info->gs.es_type = nir[0]->info.stage;
4362 }
4363 }
4364 }
4365
4366 static void
4367 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
4368 {
4369 LLVMValueRef vtx_offset =
4370 LLVMBuildMul(ctx->ac.builder, ac_get_arg(&ctx->ac, ctx->args->ac.vertex_id),
4371 LLVMConstInt(ctx->ac.i32, 4, false), "");
4372 LLVMValueRef stream_id;
4373
4374 /* Fetch the vertex stream ID. */
4375 if (!ctx->args->options->use_ngg_streamout &&
4376 ctx->args->shader_info->so.num_outputs) {
4377 stream_id =
4378 ac_unpack_param(&ctx->ac,
4379 ac_get_arg(&ctx->ac,
4380 ctx->args->streamout_config),
4381 24, 2);
4382 } else {
4383 stream_id = ctx->ac.i32_0;
4384 }
4385
4386 LLVMBasicBlockRef end_bb;
4387 LLVMValueRef switch_inst;
4388
4389 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
4390 ctx->main_function, "end");
4391 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
4392
4393 for (unsigned stream = 0; stream < 4; stream++) {
4394 unsigned num_components =
4395 ctx->args->shader_info->gs.num_stream_output_components[stream];
4396 LLVMBasicBlockRef bb;
4397 unsigned offset;
4398
4399 if (stream > 0 && !num_components)
4400 continue;
4401
4402 if (stream > 0 && !ctx->args->shader_info->so.num_outputs)
4403 continue;
4404
4405 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
4406 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
4407 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
4408
4409 offset = 0;
4410 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4411 unsigned output_usage_mask =
4412 ctx->args->shader_info->gs.output_usage_mask[i];
4413 unsigned output_stream =
4414 ctx->args->shader_info->gs.output_streams[i];
4415 int length = util_last_bit(output_usage_mask);
4416
4417 if (!(ctx->output_mask & (1ull << i)) ||
4418 output_stream != stream)
4419 continue;
4420
4421 for (unsigned j = 0; j < length; j++) {
4422 LLVMValueRef value, soffset;
4423
4424 if (!(output_usage_mask & (1 << j)))
4425 continue;
4426
4427 soffset = LLVMConstInt(ctx->ac.i32,
4428 offset *
4429 ctx->shader->info.gs.vertices_out * 16 * 4, false);
4430
4431 offset++;
4432
4433 value = ac_build_buffer_load(&ctx->ac,
4434 ctx->gsvs_ring[0],
4435 1, ctx->ac.i32_0,
4436 vtx_offset, soffset,
4437 0, ac_glc | ac_slc, true, false);
4438
4439 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4440 if (ac_get_type_size(type) == 2) {
4441 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
4442 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
4443 }
4444
4445 LLVMBuildStore(ctx->ac.builder,
4446 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4447 }
4448 }
4449
4450 if (!ctx->args->options->use_ngg_streamout &&
4451 ctx->args->shader_info->so.num_outputs)
4452 radv_emit_streamout(ctx, stream);
4453
4454 if (stream == 0) {
4455 handle_vs_outputs_post(ctx, false, true,
4456 &ctx->args->shader_info->vs.outinfo);
4457 }
4458
4459 LLVMBuildBr(ctx->ac.builder, end_bb);
4460 }
4461
4462 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
4463 }
4464
4465 void
4466 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
4467 struct nir_shader *geom_shader,
4468 struct radv_shader_binary **rbinary,
4469 const struct radv_shader_args *args)
4470 {
4471 struct radv_shader_context ctx = {0};
4472 ctx.args = args;
4473
4474 assert(args->is_gs_copy_shader);
4475
4476 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
4477 args->options->family, AC_FLOAT_MODE_DEFAULT, 64, 64);
4478 ctx.context = ctx.ac.context;
4479
4480 ctx.stage = MESA_SHADER_VERTEX;
4481 ctx.shader = geom_shader;
4482
4483 create_function(&ctx, MESA_SHADER_VERTEX, false);
4484
4485 ac_setup_rings(&ctx);
4486
4487 nir_foreach_variable(variable, &geom_shader->outputs) {
4488 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
4489 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
4490 variable, MESA_SHADER_VERTEX);
4491 }
4492
4493 ac_gs_copy_shader_emit(&ctx);
4494
4495 LLVMBuildRetVoid(ctx.ac.builder);
4496
4497 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4498
4499 ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
4500 MESA_SHADER_VERTEX, "GS Copy Shader", args->options);
4501 (*rbinary)->is_gs_copy_shader = true;
4502
4503 }