2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35 #if HAVE_LLVM >= 0x0700
36 #include <llvm-c/Transforms/Utils.h>
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_llvm_build.h"
44 #include "ac_shader_abi.h"
45 #include "ac_shader_util.h"
46 #include "ac_exp_param.h"
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 struct radv_shader_context
{
51 struct ac_llvm_context ac
;
52 const struct radv_nir_compiler_options
*options
;
53 struct radv_shader_variant_info
*shader_info
;
54 struct ac_shader_abi abi
;
56 unsigned max_workgroup_size
;
57 LLVMContextRef context
;
58 LLVMValueRef main_function
;
60 LLVMValueRef descriptor_sets
[RADV_UD_MAX_SETS
];
61 LLVMValueRef ring_offsets
;
63 LLVMValueRef vertex_buffers
;
64 LLVMValueRef rel_auto_id
;
65 LLVMValueRef vs_prim_id
;
66 LLVMValueRef es2gs_offset
;
69 LLVMValueRef merged_wave_info
;
70 LLVMValueRef tess_factor_offset
;
71 LLVMValueRef tes_rel_patch_id
;
75 LLVMValueRef gs2vs_offset
;
76 LLVMValueRef gs_wave_id
;
77 LLVMValueRef gs_vtx_offset
[6];
79 LLVMValueRef esgs_ring
;
80 LLVMValueRef gsvs_ring
;
81 LLVMValueRef hs_ring_tess_offchip
;
82 LLVMValueRef hs_ring_tess_factor
;
84 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
85 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
87 gl_shader_stage stage
;
89 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
93 uint8_t num_output_clips
;
94 uint8_t num_output_culls
;
96 bool is_gs_copy_shader
;
97 LLVMValueRef gs_next_vertex
;
98 unsigned gs_max_out_vertices
;
100 unsigned tes_primitive_mode
;
102 uint32_t tcs_patch_outputs_read
;
103 uint64_t tcs_outputs_read
;
104 uint32_t tcs_vertices_per_patch
;
105 uint32_t tcs_num_inputs
;
106 uint32_t tcs_num_patches
;
107 uint32_t max_gsvs_emit_size
;
108 uint32_t gsvs_vertex_size
;
111 enum radeon_llvm_calling_convention
{
112 RADEON_LLVM_AMDGPU_VS
= 87,
113 RADEON_LLVM_AMDGPU_GS
= 88,
114 RADEON_LLVM_AMDGPU_PS
= 89,
115 RADEON_LLVM_AMDGPU_CS
= 90,
116 RADEON_LLVM_AMDGPU_HS
= 93,
119 static inline struct radv_shader_context
*
120 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
122 struct radv_shader_context
*ctx
= NULL
;
123 return container_of(abi
, ctx
, abi
);
126 struct ac_build_if_state
128 struct radv_shader_context
*ctx
;
129 LLVMValueRef condition
;
130 LLVMBasicBlockRef entry_block
;
131 LLVMBasicBlockRef true_block
;
132 LLVMBasicBlockRef false_block
;
133 LLVMBasicBlockRef merge_block
;
136 static LLVMBasicBlockRef
137 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
139 LLVMBasicBlockRef current_block
;
140 LLVMBasicBlockRef next_block
;
141 LLVMBasicBlockRef new_block
;
143 /* get current basic block */
144 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
146 /* chqeck if there's another block after this one */
147 next_block
= LLVMGetNextBasicBlock(current_block
);
149 /* insert the new block before the next block */
150 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
153 /* append new block after current block */
154 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
155 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
161 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
162 struct radv_shader_context
*ctx
,
163 LLVMValueRef condition
)
165 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
167 memset(ifthen
, 0, sizeof *ifthen
);
169 ifthen
->condition
= condition
;
170 ifthen
->entry_block
= block
;
172 /* create endif/merge basic block for the phi functions */
173 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
175 /* create/insert true_block before merge_block */
177 LLVMInsertBasicBlockInContext(ctx
->context
,
181 /* successive code goes into the true block */
182 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
189 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
191 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
193 /* Insert branch to the merge block from current block */
194 LLVMBuildBr(builder
, ifthen
->merge_block
);
197 * Now patch in the various branch instructions.
200 /* Insert the conditional branch instruction at the end of entry_block */
201 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
202 if (ifthen
->false_block
) {
203 /* we have an else clause */
204 LLVMBuildCondBr(builder
, ifthen
->condition
,
205 ifthen
->true_block
, ifthen
->false_block
);
209 LLVMBuildCondBr(builder
, ifthen
->condition
,
210 ifthen
->true_block
, ifthen
->merge_block
);
213 /* Resume building code at end of the ifthen->merge_block */
214 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
218 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
220 switch (ctx
->stage
) {
221 case MESA_SHADER_TESS_CTRL
:
222 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
223 case MESA_SHADER_TESS_EVAL
:
224 return ctx
->tes_rel_patch_id
;
227 unreachable("Illegal stage");
232 get_tcs_num_patches(struct radv_shader_context
*ctx
)
234 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
235 unsigned num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
236 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
237 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
238 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
239 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
240 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
241 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
242 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
243 unsigned num_patches
;
244 unsigned hardware_lds_size
;
246 /* Ensure that we only need one wave per SIMD so we don't need to check
247 * resource usage. Also ensures that the number of tcs in and out
248 * vertices per threadgroup are at most 256.
250 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
251 /* Make sure that the data fits in LDS. This assumes the shaders only
252 * use LDS for the inputs and outputs.
254 hardware_lds_size
= ctx
->options
->chip_class
>= CIK
? 65536 : 32768;
255 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
256 /* Make sure the output data fits in the offchip buffer */
257 num_patches
= MIN2(num_patches
, (ctx
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
258 /* Not necessary for correctness, but improves performance. The
259 * specific value is taken from the proprietary driver.
261 num_patches
= MIN2(num_patches
, 40);
263 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
264 if (ctx
->options
->chip_class
== SI
) {
265 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
266 num_patches
= MIN2(num_patches
, one_wave
);
272 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
274 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
275 unsigned num_tcs_output_cp
;
276 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
277 unsigned input_vertex_size
, output_vertex_size
;
278 unsigned input_patch_size
, output_patch_size
;
279 unsigned pervertex_output_patch_size
;
280 unsigned output_patch0_offset
;
281 unsigned num_patches
;
284 num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
285 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
286 num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
288 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
289 output_vertex_size
= num_tcs_outputs
* 16;
291 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
293 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
294 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
296 num_patches
= ctx
->tcs_num_patches
;
297 output_patch0_offset
= input_patch_size
* num_patches
;
299 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
303 /* Tessellation shaders pass outputs to the next shader using LDS.
305 * LS outputs = TCS inputs
306 * TCS outputs = TES inputs
309 * - TCS inputs for patch 0
310 * - TCS inputs for patch 1
311 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
313 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
314 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
315 * - TCS outputs for patch 1
316 * - Per-patch TCS outputs for patch 1
317 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
318 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
321 * All three shaders VS(LS), TCS, TES share the same LDS space.
324 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
326 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
327 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
328 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
330 input_patch_size
/= 4;
331 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
335 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
337 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
338 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
339 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
340 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
341 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
342 output_patch_size
/= 4;
343 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
347 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
349 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
350 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
351 output_vertex_size
/= 4;
352 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
356 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
358 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
359 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
360 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
361 uint32_t output_patch0_offset
= input_patch_size
;
362 unsigned num_patches
= ctx
->tcs_num_patches
;
364 output_patch0_offset
*= num_patches
;
365 output_patch0_offset
/= 4;
366 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
370 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
372 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
373 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
374 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
375 uint32_t output_patch0_offset
= input_patch_size
;
377 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
378 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
379 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
380 unsigned num_patches
= ctx
->tcs_num_patches
;
382 output_patch0_offset
*= num_patches
;
383 output_patch0_offset
+= pervertex_output_patch_size
;
384 output_patch0_offset
/= 4;
385 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
389 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
391 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
392 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
394 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
398 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
400 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
401 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
402 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
404 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_offset
,
405 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
411 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
413 LLVMValueRef patch0_patch_data_offset
=
414 get_tcs_out_patch0_patch_data_offset(ctx
);
415 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
416 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
418 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_patch_data_offset
,
419 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
426 LLVMTypeRef types
[MAX_ARGS
];
427 LLVMValueRef
*assign
[MAX_ARGS
];
428 unsigned array_params_mask
;
431 uint8_t num_sgprs_used
;
432 uint8_t num_vgprs_used
;
435 enum ac_arg_regfile
{
441 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
442 LLVMValueRef
*param_ptr
)
444 assert(info
->count
< MAX_ARGS
);
446 info
->assign
[info
->count
] = param_ptr
;
447 info
->types
[info
->count
] = type
;
450 if (regfile
== ARG_SGPR
) {
451 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
454 assert(regfile
== ARG_VGPR
);
455 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
460 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
462 info
->array_params_mask
|= (1 << info
->count
);
463 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
466 static void assign_arguments(LLVMValueRef main_function
,
467 struct arg_info
*info
)
470 for (i
= 0; i
< info
->count
; i
++) {
472 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
477 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
478 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
479 unsigned num_return_elems
,
480 struct arg_info
*args
,
481 unsigned max_workgroup_size
,
482 const struct radv_nir_compiler_options
*options
)
484 LLVMTypeRef main_function_type
, ret_type
;
485 LLVMBasicBlockRef main_function_body
;
487 if (num_return_elems
)
488 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
489 num_return_elems
, true);
491 ret_type
= LLVMVoidTypeInContext(ctx
);
493 /* Setup the function */
495 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
496 LLVMValueRef main_function
=
497 LLVMAddFunction(module
, "main", main_function_type
);
499 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
500 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
502 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
503 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
504 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
506 if (args
->array_params_mask
& (1 << i
)) {
507 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
508 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
509 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
513 if (options
->address32_hi
) {
514 ac_llvm_add_target_dep_function_attr(main_function
,
515 "amdgpu-32bit-address-high-bits",
516 options
->address32_hi
);
519 if (max_workgroup_size
) {
520 ac_llvm_add_target_dep_function_attr(main_function
,
521 "amdgpu-max-work-group-size",
524 if (options
->unsafe_math
) {
525 /* These were copied from some LLVM test. */
526 LLVMAddTargetDependentFunctionAttr(main_function
,
527 "less-precise-fpmad",
529 LLVMAddTargetDependentFunctionAttr(main_function
,
532 LLVMAddTargetDependentFunctionAttr(main_function
,
535 LLVMAddTargetDependentFunctionAttr(main_function
,
538 LLVMAddTargetDependentFunctionAttr(main_function
,
539 "no-signed-zeros-fp-math",
542 return main_function
;
547 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
,
548 uint32_t indirect_offset
)
550 ud_info
->sgpr_idx
= *sgpr_idx
;
551 ud_info
->num_sgprs
= num_sgprs
;
552 ud_info
->indirect
= indirect_offset
> 0;
553 ud_info
->indirect_offset
= indirect_offset
;
554 *sgpr_idx
+= num_sgprs
;
558 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
561 struct radv_userdata_info
*ud_info
=
562 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
565 set_loc(ud_info
, sgpr_idx
, num_sgprs
, 0);
569 set_loc_shader_ptr(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
571 bool use_32bit_pointers
= HAVE_32BIT_POINTERS
&&
572 idx
!= AC_UD_SCRATCH_RING_OFFSETS
;
574 set_loc_shader(ctx
, idx
, sgpr_idx
, use_32bit_pointers
? 1 : 2);
578 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
579 uint32_t indirect_offset
)
581 struct radv_userdata_info
*ud_info
=
582 &ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[idx
];
585 set_loc(ud_info
, sgpr_idx
, HAVE_32BIT_POINTERS
? 1 : 2, indirect_offset
);
588 struct user_sgpr_info
{
589 bool need_ring_offsets
;
590 bool indirect_all_descriptor_sets
;
593 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
594 gl_shader_stage stage
)
597 case MESA_SHADER_VERTEX
:
598 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
599 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
602 case MESA_SHADER_TESS_EVAL
:
603 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
606 case MESA_SHADER_GEOMETRY
:
607 case MESA_SHADER_TESS_CTRL
:
608 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
618 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
622 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
623 count
+= HAVE_32BIT_POINTERS
? 1 : 2;
624 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
629 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
630 gl_shader_stage stage
,
631 bool has_previous_stage
,
632 gl_shader_stage previous_stage
,
633 bool needs_view_index
,
634 struct user_sgpr_info
*user_sgpr_info
)
636 uint8_t user_sgpr_count
= 0;
638 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
640 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
641 if (stage
== MESA_SHADER_GEOMETRY
||
642 stage
== MESA_SHADER_VERTEX
||
643 stage
== MESA_SHADER_TESS_CTRL
||
644 stage
== MESA_SHADER_TESS_EVAL
||
645 ctx
->is_gs_copy_shader
)
646 user_sgpr_info
->need_ring_offsets
= true;
648 if (stage
== MESA_SHADER_FRAGMENT
&&
649 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
650 user_sgpr_info
->need_ring_offsets
= true;
652 /* 2 user sgprs will nearly always be allocated for scratch/rings */
653 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
654 user_sgpr_count
+= 2;
658 case MESA_SHADER_COMPUTE
:
659 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
660 user_sgpr_count
+= 3;
662 case MESA_SHADER_FRAGMENT
:
663 user_sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
665 case MESA_SHADER_VERTEX
:
666 if (!ctx
->is_gs_copy_shader
)
667 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
669 case MESA_SHADER_TESS_CTRL
:
670 if (has_previous_stage
) {
671 if (previous_stage
== MESA_SHADER_VERTEX
)
672 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
675 case MESA_SHADER_TESS_EVAL
:
677 case MESA_SHADER_GEOMETRY
:
678 if (has_previous_stage
) {
679 if (previous_stage
== MESA_SHADER_VERTEX
) {
680 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
688 if (needs_view_index
)
691 if (ctx
->shader_info
->info
.loads_push_constants
)
692 user_sgpr_count
+= HAVE_32BIT_POINTERS
? 1 : 2;
694 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
? 32 : 16;
695 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_count
;
696 uint32_t num_desc_set
=
697 util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
);
699 if (remaining_sgprs
/ (HAVE_32BIT_POINTERS
? 1 : 2) < num_desc_set
) {
700 user_sgpr_info
->indirect_all_descriptor_sets
= true;
705 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
706 gl_shader_stage stage
,
707 bool has_previous_stage
,
708 gl_shader_stage previous_stage
,
709 const struct user_sgpr_info
*user_sgpr_info
,
710 struct arg_info
*args
,
711 LLVMValueRef
*desc_sets
)
713 LLVMTypeRef type
= ac_array_in_const32_addr_space(ctx
->ac
.i8
);
714 unsigned num_sets
= ctx
->options
->layout
?
715 ctx
->options
->layout
->num_sets
: 0;
716 unsigned stage_mask
= 1 << stage
;
718 if (has_previous_stage
)
719 stage_mask
|= 1 << previous_stage
;
721 /* 1 for each descriptor set */
722 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
723 for (unsigned i
= 0; i
< num_sets
; ++i
) {
724 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
725 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
726 add_array_arg(args
, type
,
727 &ctx
->descriptor_sets
[i
]);
731 add_array_arg(args
, ac_array_in_const32_addr_space(type
), desc_sets
);
734 if (ctx
->shader_info
->info
.loads_push_constants
) {
735 /* 1 for push constants and dynamic descriptors */
736 add_array_arg(args
, type
, &ctx
->abi
.push_constants
);
741 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
742 gl_shader_stage stage
,
743 bool has_previous_stage
,
744 gl_shader_stage previous_stage
,
745 struct arg_info
*args
)
747 if (!ctx
->is_gs_copy_shader
&&
748 (stage
== MESA_SHADER_VERTEX
||
749 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
750 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
751 add_arg(args
, ARG_SGPR
,
752 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
753 &ctx
->vertex_buffers
);
755 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
756 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
757 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
758 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
764 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
766 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
767 if (!ctx
->is_gs_copy_shader
) {
768 if (ctx
->options
->key
.vs
.as_ls
) {
769 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
770 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
772 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
773 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
775 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
780 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
782 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
783 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
784 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
785 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
789 set_global_input_locs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
790 bool has_previous_stage
, gl_shader_stage previous_stage
,
791 const struct user_sgpr_info
*user_sgpr_info
,
792 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
794 unsigned num_sets
= ctx
->options
->layout
?
795 ctx
->options
->layout
->num_sets
: 0;
796 unsigned stage_mask
= 1 << stage
;
798 if (has_previous_stage
)
799 stage_mask
|= 1 << previous_stage
;
801 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
802 for (unsigned i
= 0; i
< num_sets
; ++i
) {
803 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
804 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
805 set_loc_desc(ctx
, i
, user_sgpr_idx
, 0);
807 ctx
->descriptor_sets
[i
] = NULL
;
810 set_loc_shader_ptr(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
813 for (unsigned i
= 0; i
< num_sets
; ++i
) {
814 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
815 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
816 set_loc_desc(ctx
, i
, user_sgpr_idx
, i
* 8);
817 ctx
->descriptor_sets
[i
] =
818 ac_build_load_to_sgpr(&ctx
->ac
,
820 LLVMConstInt(ctx
->ac
.i32
, i
, false));
823 ctx
->descriptor_sets
[i
] = NULL
;
825 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
828 if (ctx
->shader_info
->info
.loads_push_constants
) {
829 set_loc_shader_ptr(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
);
834 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
835 gl_shader_stage stage
, bool has_previous_stage
,
836 gl_shader_stage previous_stage
,
837 uint8_t *user_sgpr_idx
)
839 if (!ctx
->is_gs_copy_shader
&&
840 (stage
== MESA_SHADER_VERTEX
||
841 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
842 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
843 set_loc_shader_ptr(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
848 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
851 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
852 user_sgpr_idx
, vs_num
);
856 static void set_llvm_calling_convention(LLVMValueRef func
,
857 gl_shader_stage stage
)
859 enum radeon_llvm_calling_convention calling_conv
;
862 case MESA_SHADER_VERTEX
:
863 case MESA_SHADER_TESS_EVAL
:
864 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
866 case MESA_SHADER_GEOMETRY
:
867 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
869 case MESA_SHADER_TESS_CTRL
:
870 calling_conv
= RADEON_LLVM_AMDGPU_HS
;
872 case MESA_SHADER_FRAGMENT
:
873 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
875 case MESA_SHADER_COMPUTE
:
876 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
879 unreachable("Unhandle shader type");
882 LLVMSetFunctionCallConv(func
, calling_conv
);
885 static void create_function(struct radv_shader_context
*ctx
,
886 gl_shader_stage stage
,
887 bool has_previous_stage
,
888 gl_shader_stage previous_stage
)
890 uint8_t user_sgpr_idx
;
891 struct user_sgpr_info user_sgpr_info
;
892 struct arg_info args
= {};
893 LLVMValueRef desc_sets
;
894 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
895 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
896 previous_stage
, needs_view_index
, &user_sgpr_info
);
898 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
899 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
904 case MESA_SHADER_COMPUTE
:
905 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
906 previous_stage
, &user_sgpr_info
,
909 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
910 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
911 &ctx
->abi
.num_work_groups
);
914 for (int i
= 0; i
< 3; i
++) {
915 ctx
->abi
.workgroup_ids
[i
] = NULL
;
916 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
917 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
918 &ctx
->abi
.workgroup_ids
[i
]);
922 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
923 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
924 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
925 &ctx
->abi
.local_invocation_ids
);
927 case MESA_SHADER_VERTEX
:
928 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
929 previous_stage
, &user_sgpr_info
,
931 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
932 previous_stage
, &args
);
934 if (needs_view_index
)
935 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
936 &ctx
->abi
.view_index
);
937 if (ctx
->options
->key
.vs
.as_es
)
938 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
941 declare_vs_input_vgprs(ctx
, &args
);
943 case MESA_SHADER_TESS_CTRL
:
944 if (has_previous_stage
) {
945 // First 6 system regs
946 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
947 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
948 &ctx
->merged_wave_info
);
949 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
950 &ctx
->tess_factor_offset
);
952 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
953 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
954 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
956 declare_global_input_sgprs(ctx
, stage
,
959 &user_sgpr_info
, &args
,
961 declare_vs_specific_input_sgprs(ctx
, stage
,
963 previous_stage
, &args
);
965 if (needs_view_index
)
966 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
967 &ctx
->abi
.view_index
);
969 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
970 &ctx
->abi
.tcs_patch_id
);
971 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
972 &ctx
->abi
.tcs_rel_ids
);
974 declare_vs_input_vgprs(ctx
, &args
);
976 declare_global_input_sgprs(ctx
, stage
,
979 &user_sgpr_info
, &args
,
982 if (needs_view_index
)
983 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
984 &ctx
->abi
.view_index
);
986 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
987 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
988 &ctx
->tess_factor_offset
);
989 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
990 &ctx
->abi
.tcs_patch_id
);
991 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
992 &ctx
->abi
.tcs_rel_ids
);
995 case MESA_SHADER_TESS_EVAL
:
996 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
997 previous_stage
, &user_sgpr_info
,
1000 if (needs_view_index
)
1001 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1002 &ctx
->abi
.view_index
);
1004 if (ctx
->options
->key
.tes
.as_es
) {
1005 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1006 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1007 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1008 &ctx
->es2gs_offset
);
1010 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1011 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1013 declare_tes_input_vgprs(ctx
, &args
);
1015 case MESA_SHADER_GEOMETRY
:
1016 if (has_previous_stage
) {
1017 // First 6 system regs
1018 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1019 &ctx
->gs2vs_offset
);
1020 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1021 &ctx
->merged_wave_info
);
1022 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1024 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1025 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1026 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1028 declare_global_input_sgprs(ctx
, stage
,
1031 &user_sgpr_info
, &args
,
1034 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
1035 declare_vs_specific_input_sgprs(ctx
, stage
,
1041 if (needs_view_index
)
1042 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1043 &ctx
->abi
.view_index
);
1045 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1046 &ctx
->gs_vtx_offset
[0]);
1047 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1048 &ctx
->gs_vtx_offset
[2]);
1049 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1050 &ctx
->abi
.gs_prim_id
);
1051 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1052 &ctx
->abi
.gs_invocation_id
);
1053 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1054 &ctx
->gs_vtx_offset
[4]);
1056 if (previous_stage
== MESA_SHADER_VERTEX
) {
1057 declare_vs_input_vgprs(ctx
, &args
);
1059 declare_tes_input_vgprs(ctx
, &args
);
1062 declare_global_input_sgprs(ctx
, stage
,
1065 &user_sgpr_info
, &args
,
1068 if (needs_view_index
)
1069 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1070 &ctx
->abi
.view_index
);
1072 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1073 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1074 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1075 &ctx
->gs_vtx_offset
[0]);
1076 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1077 &ctx
->gs_vtx_offset
[1]);
1078 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1079 &ctx
->abi
.gs_prim_id
);
1080 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1081 &ctx
->gs_vtx_offset
[2]);
1082 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1083 &ctx
->gs_vtx_offset
[3]);
1084 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1085 &ctx
->gs_vtx_offset
[4]);
1086 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1087 &ctx
->gs_vtx_offset
[5]);
1088 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1089 &ctx
->abi
.gs_invocation_id
);
1092 case MESA_SHADER_FRAGMENT
:
1093 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
1094 previous_stage
, &user_sgpr_info
,
1097 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1098 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1099 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1100 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1101 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1102 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1103 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1104 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1105 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1106 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1107 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1108 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1109 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1110 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1111 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1112 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1113 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1116 unreachable("Shader stage not implemented");
1119 ctx
->main_function
= create_llvm_function(
1120 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1121 ctx
->max_workgroup_size
, ctx
->options
);
1122 set_llvm_calling_convention(ctx
->main_function
, stage
);
1125 ctx
->shader_info
->num_input_vgprs
= 0;
1126 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1128 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1130 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1131 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1133 assign_arguments(ctx
->main_function
, &args
);
1137 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1138 set_loc_shader_ptr(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1140 if (ctx
->options
->supports_spill
) {
1141 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1142 LLVMPointerType(ctx
->ac
.i8
, AC_CONST_ADDR_SPACE
),
1143 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1144 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1145 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1149 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1150 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1151 if (has_previous_stage
)
1154 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1155 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1158 case MESA_SHADER_COMPUTE
:
1159 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1160 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1164 case MESA_SHADER_VERTEX
:
1165 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1166 previous_stage
, &user_sgpr_idx
);
1167 if (ctx
->abi
.view_index
)
1168 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1170 case MESA_SHADER_TESS_CTRL
:
1171 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1172 previous_stage
, &user_sgpr_idx
);
1173 if (ctx
->abi
.view_index
)
1174 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1176 case MESA_SHADER_TESS_EVAL
:
1177 if (ctx
->abi
.view_index
)
1178 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1180 case MESA_SHADER_GEOMETRY
:
1181 if (has_previous_stage
) {
1182 if (previous_stage
== MESA_SHADER_VERTEX
)
1183 set_vs_specific_input_locs(ctx
, stage
,
1188 if (ctx
->abi
.view_index
)
1189 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1191 case MESA_SHADER_FRAGMENT
:
1194 unreachable("Shader stage not implemented");
1197 if (stage
== MESA_SHADER_TESS_CTRL
||
1198 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_ls
) ||
1199 /* GFX9 has the ESGS ring buffer in LDS. */
1200 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1201 ac_declare_lds_as_pointer(&ctx
->ac
);
1204 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1209 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1210 unsigned desc_set
, unsigned binding
)
1212 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1213 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1214 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
1215 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1216 unsigned base_offset
= layout
->binding
[binding
].offset
;
1217 LLVMValueRef offset
, stride
;
1219 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1220 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1221 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1222 layout
->binding
[binding
].dynamic_offset_offset
;
1223 desc_ptr
= ctx
->abi
.push_constants
;
1224 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1225 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1227 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1229 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
1230 index
= LLVMBuildMul(ctx
->ac
.builder
, index
, stride
, "");
1231 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, index
, "");
1233 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
1234 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1235 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1241 /* The offchip buffer layout for TCS->TES is
1243 * - attribute 0 of patch 0 vertex 0
1244 * - attribute 0 of patch 0 vertex 1
1245 * - attribute 0 of patch 0 vertex 2
1247 * - attribute 0 of patch 1 vertex 0
1248 * - attribute 0 of patch 1 vertex 1
1250 * - attribute 1 of patch 0 vertex 0
1251 * - attribute 1 of patch 0 vertex 1
1253 * - per patch attribute 0 of patch 0
1254 * - per patch attribute 0 of patch 1
1257 * Note that every attribute has 4 components.
1259 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1261 uint32_t num_patches
= ctx
->tcs_num_patches
;
1262 uint32_t num_tcs_outputs
;
1263 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1264 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
1266 num_tcs_outputs
= ctx
->options
->key
.tes
.tcs_num_outputs
;
1268 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1269 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
1271 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1274 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1275 LLVMValueRef vertex_index
)
1277 LLVMValueRef param_stride
;
1279 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
* ctx
->tcs_num_patches
, false);
1281 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1282 return param_stride
;
1285 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1286 LLVMValueRef vertex_index
,
1287 LLVMValueRef param_index
)
1289 LLVMValueRef base_addr
;
1290 LLVMValueRef param_stride
, constant16
;
1291 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1292 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
1293 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1294 param_stride
= calc_param_stride(ctx
, vertex_index
);
1296 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
1297 vertices_per_patch
, "");
1299 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1302 base_addr
= rel_patch_id
;
1305 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1306 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1307 param_stride
, ""), "");
1309 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1311 if (!vertex_index
) {
1312 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1314 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1315 patch_data_offset
, "");
1320 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1322 unsigned const_index
,
1324 LLVMValueRef vertex_index
,
1325 LLVMValueRef indir_index
)
1327 LLVMValueRef param_index
;
1330 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1333 if (const_index
&& !is_compact
)
1334 param
+= const_index
;
1335 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1337 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1341 get_dw_address(struct radv_shader_context
*ctx
,
1342 LLVMValueRef dw_addr
,
1344 unsigned const_index
,
1345 bool compact_const_index
,
1346 LLVMValueRef vertex_index
,
1347 LLVMValueRef stride
,
1348 LLVMValueRef indir_index
)
1353 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1354 LLVMBuildMul(ctx
->ac
.builder
,
1360 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1361 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1362 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1363 else if (const_index
&& !compact_const_index
)
1364 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1365 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1367 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1368 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1370 if (const_index
&& compact_const_index
)
1371 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1372 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1377 load_tcs_varyings(struct ac_shader_abi
*abi
,
1379 LLVMValueRef vertex_index
,
1380 LLVMValueRef indir_index
,
1381 unsigned const_index
,
1383 unsigned driver_location
,
1385 unsigned num_components
,
1390 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1391 LLVMValueRef dw_addr
, stride
;
1392 LLVMValueRef value
[4], result
;
1393 unsigned param
= shader_io_get_unique_index(location
);
1396 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1397 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1398 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1401 stride
= get_tcs_out_vertex_stride(ctx
);
1402 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1404 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1409 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1412 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1413 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1414 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1417 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1422 store_tcs_output(struct ac_shader_abi
*abi
,
1423 const nir_variable
*var
,
1424 LLVMValueRef vertex_index
,
1425 LLVMValueRef param_index
,
1426 unsigned const_index
,
1430 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1431 const unsigned location
= var
->data
.location
;
1432 const unsigned component
= var
->data
.location_frac
;
1433 const bool is_patch
= var
->data
.patch
;
1434 const bool is_compact
= var
->data
.compact
;
1435 LLVMValueRef dw_addr
;
1436 LLVMValueRef stride
= NULL
;
1437 LLVMValueRef buf_addr
= NULL
;
1439 bool store_lds
= true;
1442 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1445 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
1449 param
= shader_io_get_unique_index(location
);
1450 if (location
== VARYING_SLOT_CLIP_DIST0
&&
1451 is_compact
&& const_index
> 3) {
1457 stride
= get_tcs_out_vertex_stride(ctx
);
1458 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1460 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1463 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1465 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1466 vertex_index
, param_index
);
1468 bool is_tess_factor
= false;
1469 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1470 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1471 is_tess_factor
= true;
1473 unsigned base
= is_compact
? const_index
: 0;
1474 for (unsigned chan
= 0; chan
< 8; chan
++) {
1475 if (!(writemask
& (1 << chan
)))
1477 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1479 if (store_lds
|| is_tess_factor
) {
1480 LLVMValueRef dw_addr_chan
=
1481 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1482 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1483 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1486 if (!is_tess_factor
&& writemask
!= 0xF)
1487 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1488 buf_addr
, ctx
->oc_lds
,
1489 4 * (base
+ chan
), 1, 0, true, false);
1492 if (writemask
== 0xF) {
1493 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1494 buf_addr
, ctx
->oc_lds
,
1495 (base
* 4), 1, 0, true, false);
1500 load_tes_input(struct ac_shader_abi
*abi
,
1502 LLVMValueRef vertex_index
,
1503 LLVMValueRef param_index
,
1504 unsigned const_index
,
1506 unsigned driver_location
,
1508 unsigned num_components
,
1513 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1514 LLVMValueRef buf_addr
;
1515 LLVMValueRef result
;
1516 unsigned param
= shader_io_get_unique_index(location
);
1518 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
1523 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1524 is_compact
, vertex_index
, param_index
);
1526 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1527 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1529 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1530 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
1531 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1536 load_gs_input(struct ac_shader_abi
*abi
,
1538 unsigned driver_location
,
1540 unsigned num_components
,
1541 unsigned vertex_index
,
1542 unsigned const_index
,
1545 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1546 LLVMValueRef vtx_offset
;
1547 unsigned param
, vtx_offset_param
;
1548 LLVMValueRef value
[4], result
;
1550 vtx_offset_param
= vertex_index
;
1551 assert(vtx_offset_param
< 6);
1552 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1553 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1555 param
= shader_io_get_unique_index(location
);
1557 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1558 if (ctx
->ac
.chip_class
>= GFX9
) {
1559 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1560 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1561 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1562 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1564 LLVMValueRef soffset
=
1565 LLVMConstInt(ctx
->ac
.i32
,
1566 (param
* 4 + i
+ const_index
) * 256,
1569 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1572 vtx_offset
, soffset
,
1573 0, 1, 0, true, false);
1575 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
],
1579 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1580 result
= ac_to_integer(&ctx
->ac
, result
);
1585 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1587 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1588 ac_build_kill_if_false(&ctx
->ac
, visible
);
1591 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
1592 enum glsl_interp_mode interp
, unsigned location
)
1594 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1597 case INTERP_MODE_FLAT
:
1600 case INTERP_MODE_SMOOTH
:
1601 case INTERP_MODE_NONE
:
1602 if (location
== INTERP_CENTER
)
1603 return ctx
->persp_center
;
1604 else if (location
== INTERP_CENTROID
)
1605 return ctx
->persp_centroid
;
1606 else if (location
== INTERP_SAMPLE
)
1607 return ctx
->persp_sample
;
1609 case INTERP_MODE_NOPERSPECTIVE
:
1610 if (location
== INTERP_CENTER
)
1611 return ctx
->linear_center
;
1612 else if (location
== INTERP_CENTROID
)
1613 return ctx
->linear_centroid
;
1614 else if (location
== INTERP_SAMPLE
)
1615 return ctx
->linear_sample
;
1622 radv_get_sample_pos_offset(uint32_t num_samples
)
1624 uint32_t sample_pos_offset
= 0;
1626 switch (num_samples
) {
1628 sample_pos_offset
= 1;
1631 sample_pos_offset
= 3;
1634 sample_pos_offset
= 7;
1637 sample_pos_offset
= 15;
1642 return sample_pos_offset
;
1645 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1646 LLVMValueRef sample_id
)
1648 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1650 LLVMValueRef result
;
1651 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
1653 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1654 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1656 uint32_t sample_pos_offset
=
1657 radv_get_sample_pos_offset(ctx
->options
->key
.fs
.num_samples
);
1660 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
1661 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
1662 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1668 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1670 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1671 uint8_t log2_ps_iter_samples
;
1673 if (ctx
->shader_info
->info
.ps
.force_persample
) {
1674 log2_ps_iter_samples
=
1675 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
1677 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
1680 /* The bit pattern matches that used by fixed function fragment
1682 static const uint16_t ps_iter_masks
[] = {
1683 0xffff, /* not used */
1689 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1691 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1693 LLVMValueRef result
, sample_id
;
1694 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
1695 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1696 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
1702 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1704 LLVMValueRef gs_next_vertex
;
1705 LLVMValueRef can_emit
;
1707 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1709 assert(stream
== 0);
1711 /* Write vertex attribute values to GSVS ring */
1712 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1713 ctx
->gs_next_vertex
,
1716 /* If this thread has already emitted the declared maximum number of
1717 * vertices, kill it: excessive vertex emissions are not supposed to
1718 * have any effect, and GS threads have no externally observable
1719 * effects other than emitting vertices.
1721 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1722 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
1723 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1725 /* loop num outputs */
1727 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1728 unsigned output_usage_mask
=
1729 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
1730 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1735 if (!(ctx
->output_mask
& (1ull << i
)))
1738 if (i
== VARYING_SLOT_CLIP_DIST0
) {
1739 /* pack clip and cull into a single set of slots */
1740 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
1743 output_usage_mask
= (1 << length
) - 1;
1746 for (unsigned j
= 0; j
< length
; j
++) {
1747 if (!(output_usage_mask
& (1 << j
)))
1750 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1752 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
1753 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1754 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1756 out_val
= LLVMBuildBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1758 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
1760 voffset
, ctx
->gs2vs_offset
, 0,
1766 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1768 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
1770 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
1774 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1776 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1777 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1781 load_tess_coord(struct ac_shader_abi
*abi
)
1783 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1785 LLVMValueRef coord
[4] = {
1792 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
1793 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1794 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1796 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1800 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1802 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1803 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
1807 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1809 return abi
->base_vertex
;
1812 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1813 LLVMValueRef buffer_ptr
, bool write
)
1815 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1816 LLVMValueRef result
;
1818 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1820 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1821 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1826 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1828 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1829 LLVMValueRef result
;
1831 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1833 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1834 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1839 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1840 unsigned descriptor_set
,
1841 unsigned base_index
,
1842 unsigned constant_index
,
1844 enum ac_descriptor_type desc_type
,
1845 bool image
, bool write
,
1848 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1849 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1850 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
1851 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1852 unsigned offset
= binding
->offset
;
1853 unsigned stride
= binding
->size
;
1855 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1858 assert(base_index
< layout
->binding_count
);
1860 switch (desc_type
) {
1862 type
= ctx
->ac
.v8i32
;
1866 type
= ctx
->ac
.v8i32
;
1870 case AC_DESC_SAMPLER
:
1871 type
= ctx
->ac
.v4i32
;
1872 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1877 case AC_DESC_BUFFER
:
1878 type
= ctx
->ac
.v4i32
;
1882 unreachable("invalid desc_type\n");
1885 offset
+= constant_index
* stride
;
1887 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
1888 (!index
|| binding
->immutable_samplers_equal
)) {
1889 if (binding
->immutable_samplers_equal
)
1892 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
1894 LLVMValueRef constants
[] = {
1895 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
1896 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
1897 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
1898 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
1900 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
1903 assert(stride
% type_size
== 0);
1906 index
= ctx
->ac
.i32_0
;
1908 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
1910 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
1911 list
= LLVMBuildPointerCast(builder
, list
,
1912 ac_array_in_const32_addr_space(type
), "");
1914 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
1917 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1918 * so we may need to fix it up. */
1920 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
1921 unsigned adjustment
,
1924 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
1927 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
1929 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
1930 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1932 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
1934 /* For the integer-like cases, do a natural sign extension.
1936 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1937 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1940 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
1941 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
1942 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
1943 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
1945 /* Convert back to the right type. */
1946 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
1948 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
1949 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1950 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
1951 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
1952 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
1953 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1960 handle_vs_input_decl(struct radv_shader_context
*ctx
,
1961 struct nir_variable
*variable
)
1963 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
1964 LLVMValueRef t_offset
;
1965 LLVMValueRef t_list
;
1967 LLVMValueRef buffer_index
;
1968 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
1969 uint8_t input_usage_mask
=
1970 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
1971 unsigned num_channels
= util_last_bit(input_usage_mask
);
1973 variable
->data
.driver_location
= variable
->data
.location
* 4;
1975 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
1976 LLVMValueRef output
[4];
1977 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
1979 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
1980 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
1983 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.instance_id
,
1984 ctx
->abi
.start_instance
, "");
1987 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
1988 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
1991 if (ctx
->options
->key
.vs
.as_ls
) {
1992 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
1993 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
1995 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
1996 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
1999 buffer_index
= ctx
->ac
.i32_0
;
2002 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
2003 ctx
->abi
.base_vertex
, "");
2004 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_index
, false);
2006 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
2008 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
2011 num_channels
, false, true);
2013 input
= ac_build_expand_to_vec4(&ctx
->ac
, input
, num_channels
);
2015 for (unsigned chan
= 0; chan
< 4; chan
++) {
2016 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2017 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
2020 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
2021 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
2023 for (unsigned chan
= 0; chan
< 4; chan
++) {
2024 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] =
2025 ac_to_integer(&ctx
->ac
, output
[chan
]);
2030 static void interp_fs_input(struct radv_shader_context
*ctx
,
2032 LLVMValueRef interp_param
,
2033 LLVMValueRef prim_mask
,
2034 LLVMValueRef result
[4])
2036 LLVMValueRef attr_number
;
2039 bool interp
= interp_param
!= NULL
;
2041 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
2043 /* fs.constant returns the param from the middle vertex, so it's not
2044 * really useful for flat shading. It's meant to be used for custom
2045 * interpolation (but the intrinsic can't fetch from the other two
2048 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2049 * to do the right thing. The only reason we use fs.constant is that
2050 * fs.interp cannot be used on integers, because they can be equal
2054 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
2057 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
2059 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
2063 for (chan
= 0; chan
< 4; chan
++) {
2064 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2067 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
2072 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
2073 LLVMConstInt(ctx
->ac
.i32
, 2, false),
2082 handle_fs_input_decl(struct radv_shader_context
*ctx
,
2083 struct nir_variable
*variable
)
2085 int idx
= variable
->data
.location
;
2086 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2087 LLVMValueRef interp
;
2089 variable
->data
.driver_location
= idx
* 4;
2090 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
2092 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
2093 unsigned interp_type
;
2094 if (variable
->data
.sample
)
2095 interp_type
= INTERP_SAMPLE
;
2096 else if (variable
->data
.centroid
)
2097 interp_type
= INTERP_CENTROID
;
2099 interp_type
= INTERP_CENTER
;
2101 interp
= lookup_interp_param(&ctx
->abi
, variable
->data
.interpolation
, interp_type
);
2105 for (unsigned i
= 0; i
< attrib_count
; ++i
)
2106 ctx
->inputs
[ac_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
2111 handle_vs_inputs(struct radv_shader_context
*ctx
,
2112 struct nir_shader
*nir
) {
2113 nir_foreach_variable(variable
, &nir
->inputs
)
2114 handle_vs_input_decl(ctx
, variable
);
2118 prepare_interp_optimize(struct radv_shader_context
*ctx
,
2119 struct nir_shader
*nir
)
2121 bool uses_center
= false;
2122 bool uses_centroid
= false;
2123 nir_foreach_variable(variable
, &nir
->inputs
) {
2124 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
2125 variable
->data
.sample
)
2128 if (variable
->data
.centroid
)
2129 uses_centroid
= true;
2134 if (uses_center
&& uses_centroid
) {
2135 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
2136 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
2137 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
2142 handle_fs_inputs(struct radv_shader_context
*ctx
,
2143 struct nir_shader
*nir
)
2145 prepare_interp_optimize(ctx
, nir
);
2147 nir_foreach_variable(variable
, &nir
->inputs
)
2148 handle_fs_input_decl(ctx
, variable
);
2152 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
2153 ctx
->shader_info
->info
.needs_multiview_view_index
)
2154 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
2156 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
2157 LLVMValueRef interp_param
;
2158 LLVMValueRef
*inputs
= ctx
->inputs
+ac_llvm_reg_index_soa(i
, 0);
2160 if (!(ctx
->input_mask
& (1ull << i
)))
2163 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
2164 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
2165 interp_param
= *inputs
;
2166 interp_fs_input(ctx
, index
, interp_param
, ctx
->abi
.prim_mask
,
2170 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
2172 } else if (i
== VARYING_SLOT_POS
) {
2173 for(int i
= 0; i
< 3; ++i
)
2174 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
2176 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
2177 ctx
->abi
.frag_pos
[3]);
2180 ctx
->shader_info
->fs
.num_interp
= index
;
2181 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
2183 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
2184 ctx
->abi
.view_index
= ctx
->inputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2188 scan_shader_output_decl(struct radv_shader_context
*ctx
,
2189 struct nir_variable
*variable
,
2190 struct nir_shader
*shader
,
2191 gl_shader_stage stage
)
2193 int idx
= variable
->data
.location
+ variable
->data
.index
;
2194 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2195 uint64_t mask_attribs
;
2197 variable
->data
.driver_location
= idx
* 4;
2199 /* tess ctrl has it's own load/store paths for outputs */
2200 if (stage
== MESA_SHADER_TESS_CTRL
)
2203 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2204 if (stage
== MESA_SHADER_VERTEX
||
2205 stage
== MESA_SHADER_TESS_EVAL
||
2206 stage
== MESA_SHADER_GEOMETRY
) {
2207 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2208 int length
= shader
->info
.clip_distance_array_size
+
2209 shader
->info
.cull_distance_array_size
;
2210 if (stage
== MESA_SHADER_VERTEX
) {
2211 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2212 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2214 if (stage
== MESA_SHADER_TESS_EVAL
) {
2215 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2216 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2223 mask_attribs
= 1ull << idx
;
2227 ctx
->output_mask
|= mask_attribs
;
2231 /* Initialize arguments for the shader export intrinsic */
2233 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2234 LLVMValueRef
*values
,
2235 unsigned enabled_channels
,
2237 struct ac_export_args
*args
)
2239 /* Specify the channels that are enabled. */
2240 args
->enabled_channels
= enabled_channels
;
2242 /* Specify whether the EXEC mask represents the valid mask */
2243 args
->valid_mask
= 0;
2245 /* Specify whether this is the last export */
2248 /* Specify the target we are exporting */
2249 args
->target
= target
;
2251 args
->compr
= false;
2252 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2253 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2254 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2255 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2257 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
2258 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2259 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2260 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2261 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2264 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2265 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2266 unsigned bits
, bool hi
) = NULL
;
2268 switch(col_format
) {
2269 case V_028714_SPI_SHADER_ZERO
:
2270 args
->enabled_channels
= 0; /* writemask */
2271 args
->target
= V_008DFC_SQ_EXP_NULL
;
2274 case V_028714_SPI_SHADER_32_R
:
2275 args
->enabled_channels
= 1;
2276 args
->out
[0] = values
[0];
2279 case V_028714_SPI_SHADER_32_GR
:
2280 args
->enabled_channels
= 0x3;
2281 args
->out
[0] = values
[0];
2282 args
->out
[1] = values
[1];
2285 case V_028714_SPI_SHADER_32_AR
:
2286 args
->enabled_channels
= 0x9;
2287 args
->out
[0] = values
[0];
2288 args
->out
[3] = values
[3];
2291 case V_028714_SPI_SHADER_FP16_ABGR
:
2292 args
->enabled_channels
= 0x5;
2293 packf
= ac_build_cvt_pkrtz_f16
;
2296 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2297 args
->enabled_channels
= 0x5;
2298 packf
= ac_build_cvt_pknorm_u16
;
2301 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2302 args
->enabled_channels
= 0x5;
2303 packf
= ac_build_cvt_pknorm_i16
;
2306 case V_028714_SPI_SHADER_UINT16_ABGR
:
2307 args
->enabled_channels
= 0x5;
2308 packi
= ac_build_cvt_pk_u16
;
2311 case V_028714_SPI_SHADER_SINT16_ABGR
:
2312 args
->enabled_channels
= 0x5;
2313 packi
= ac_build_cvt_pk_i16
;
2317 case V_028714_SPI_SHADER_32_ABGR
:
2318 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2322 /* Pack f16 or norm_i16/u16. */
2324 for (chan
= 0; chan
< 2; chan
++) {
2325 LLVMValueRef pack_args
[2] = {
2327 values
[2 * chan
+ 1]
2329 LLVMValueRef packed
;
2331 packed
= packf(&ctx
->ac
, pack_args
);
2332 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2334 args
->compr
= 1; /* COMPR flag */
2339 for (chan
= 0; chan
< 2; chan
++) {
2340 LLVMValueRef pack_args
[2] = {
2341 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2342 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2344 LLVMValueRef packed
;
2346 packed
= packi(&ctx
->ac
, pack_args
,
2347 is_int8
? 8 : is_int10
? 10 : 16,
2349 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2351 args
->compr
= 1; /* COMPR flag */
2356 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2358 for (unsigned i
= 0; i
< 4; ++i
) {
2359 if (!(args
->enabled_channels
& (1 << i
)))
2362 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2367 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2368 LLVMValueRef
*values
, unsigned enabled_channels
)
2370 struct ac_export_args args
;
2372 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2373 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2374 ac_build_export(&ctx
->ac
, &args
);
2378 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2380 LLVMValueRef output
=
2381 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2383 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2387 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2388 bool export_prim_id
, bool export_layer_id
,
2389 struct radv_vs_output_info
*outinfo
)
2391 uint32_t param_count
= 0;
2393 unsigned pos_idx
, num_pos_exports
= 0;
2394 struct ac_export_args args
, pos_args
[4] = {};
2395 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2398 if (ctx
->options
->key
.has_multiview_view_index
) {
2399 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2401 for(unsigned i
= 0; i
< 4; ++i
)
2402 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2403 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2406 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
2407 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2410 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2411 sizeof(outinfo
->vs_output_param_offset
));
2413 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
2414 LLVMValueRef slots
[8];
2417 if (outinfo
->cull_dist_mask
)
2418 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
2420 i
= VARYING_SLOT_CLIP_DIST0
;
2421 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
2422 slots
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2424 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
2425 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
2427 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
2428 target
= V_008DFC_SQ_EXP_POS
+ 3;
2429 si_llvm_init_export_args(ctx
, &slots
[4], 0xf, target
, &args
);
2430 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2431 &args
, sizeof(args
));
2434 target
= V_008DFC_SQ_EXP_POS
+ 2;
2435 si_llvm_init_export_args(ctx
, &slots
[0], 0xf, target
, &args
);
2436 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2437 &args
, sizeof(args
));
2441 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
2442 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
2443 for (unsigned j
= 0; j
< 4; j
++)
2444 pos_values
[j
] = radv_load_output(ctx
, VARYING_SLOT_POS
, j
);
2446 si_llvm_init_export_args(ctx
, pos_values
, 0xf, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2448 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
2449 outinfo
->writes_pointsize
= true;
2450 psize_value
= radv_load_output(ctx
, VARYING_SLOT_PSIZ
, 0);
2453 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
2454 outinfo
->writes_layer
= true;
2455 layer_value
= radv_load_output(ctx
, VARYING_SLOT_LAYER
, 0);
2458 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
2459 outinfo
->writes_viewport_index
= true;
2460 viewport_index_value
= radv_load_output(ctx
, VARYING_SLOT_VIEWPORT
, 0);
2463 if (outinfo
->writes_pointsize
||
2464 outinfo
->writes_layer
||
2465 outinfo
->writes_viewport_index
) {
2466 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2467 (outinfo
->writes_layer
== true ? 4 : 0));
2468 pos_args
[1].valid_mask
= 0;
2469 pos_args
[1].done
= 0;
2470 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2471 pos_args
[1].compr
= 0;
2472 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2473 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2474 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2475 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2477 if (outinfo
->writes_pointsize
== true)
2478 pos_args
[1].out
[0] = psize_value
;
2479 if (outinfo
->writes_layer
== true)
2480 pos_args
[1].out
[2] = layer_value
;
2481 if (outinfo
->writes_viewport_index
== true) {
2482 if (ctx
->options
->chip_class
>= GFX9
) {
2483 /* GFX9 has the layer in out.z[10:0] and the viewport
2484 * index in out.z[19:16].
2486 LLVMValueRef v
= viewport_index_value
;
2487 v
= ac_to_integer(&ctx
->ac
, v
);
2488 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2489 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2491 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2492 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2494 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2495 pos_args
[1].enabled_channels
|= 1 << 2;
2497 pos_args
[1].out
[3] = viewport_index_value
;
2498 pos_args
[1].enabled_channels
|= 1 << 3;
2502 for (i
= 0; i
< 4; i
++) {
2503 if (pos_args
[i
].out
[0])
2508 for (i
= 0; i
< 4; i
++) {
2509 if (!pos_args
[i
].out
[0])
2512 /* Specify the target we are exporting */
2513 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2514 if (pos_idx
== num_pos_exports
)
2515 pos_args
[i
].done
= 1;
2516 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2519 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2520 LLVMValueRef values
[4];
2521 if (!(ctx
->output_mask
& (1ull << i
)))
2524 if (i
!= VARYING_SLOT_LAYER
&&
2525 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
2526 i
< VARYING_SLOT_VAR0
)
2529 for (unsigned j
= 0; j
< 4; j
++)
2530 values
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2532 unsigned output_usage_mask
;
2534 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2535 !ctx
->is_gs_copy_shader
) {
2537 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2538 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2540 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2542 assert(ctx
->is_gs_copy_shader
);
2544 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
2547 radv_export_param(ctx
, param_count
, values
, output_usage_mask
);
2549 outinfo
->vs_output_param_offset
[i
] = param_count
++;
2552 if (export_prim_id
) {
2553 LLVMValueRef values
[4];
2555 values
[0] = ctx
->vs_prim_id
;
2556 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
2557 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
2558 for (unsigned j
= 1; j
< 4; j
++)
2559 values
[j
] = ctx
->ac
.f32_0
;
2561 radv_export_param(ctx
, param_count
, values
, 0x1);
2563 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
2564 outinfo
->export_prim_id
= true;
2567 if (export_layer_id
&& layer_value
) {
2568 LLVMValueRef values
[4];
2570 values
[0] = layer_value
;
2571 for (unsigned j
= 1; j
< 4; j
++)
2572 values
[j
] = ctx
->ac
.f32_0
;
2574 radv_export_param(ctx
, param_count
, values
, 0x1);
2576 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
++;
2579 outinfo
->pos_exports
= num_pos_exports
;
2580 outinfo
->param_exports
= param_count
;
2584 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2585 struct radv_es_output_info
*outinfo
)
2588 uint64_t max_output_written
= 0;
2589 LLVMValueRef lds_base
= NULL
;
2591 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2595 if (!(ctx
->output_mask
& (1ull << i
)))
2598 if (i
== VARYING_SLOT_CLIP_DIST0
)
2599 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
2601 param_index
= shader_io_get_unique_index(i
);
2603 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
2606 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
2608 if (ctx
->ac
.chip_class
>= GFX9
) {
2609 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2610 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2611 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
2612 LLVMConstInt(ctx
->ac
.i32
, 24, false),
2613 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
2614 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2615 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2616 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
2617 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2618 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2621 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2622 LLVMValueRef dw_addr
= NULL
;
2623 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2624 unsigned output_usage_mask
;
2628 if (!(ctx
->output_mask
& (1ull << i
)))
2631 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2633 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2635 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2637 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2640 if (i
== VARYING_SLOT_CLIP_DIST0
) {
2641 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
2642 output_usage_mask
= (1 << length
) - 1;
2645 param_index
= shader_io_get_unique_index(i
);
2648 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2649 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
2653 for (j
= 0; j
< length
; j
++) {
2654 if (!(output_usage_mask
& (1 << j
)))
2657 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2658 out_val
= LLVMBuildBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
2660 if (ctx
->ac
.chip_class
>= GFX9
) {
2661 LLVMValueRef dw_addr_offset
=
2662 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2663 LLVMConstInt(ctx
->ac
.i32
,
2666 ac_lds_store(&ctx
->ac
, dw_addr_offset
,
2667 LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], ""));
2669 ac_build_buffer_store_dword(&ctx
->ac
,
2672 NULL
, ctx
->es2gs_offset
,
2673 (4 * param_index
+ j
) * 4,
2681 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
2683 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
2684 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->shader_info
->info
.vs
.ls_outputs_written
);
2685 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
2686 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
2687 vertex_dw_stride
, "");
2689 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2690 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2693 if (!(ctx
->output_mask
& (1ull << i
)))
2696 if (i
== VARYING_SLOT_CLIP_DIST0
)
2697 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
2698 int param
= shader_io_get_unique_index(i
);
2699 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
2700 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
2702 for (unsigned j
= 0; j
< length
; j
++) {
2703 ac_lds_store(&ctx
->ac
, dw_addr
,
2704 LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], ""));
2705 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
2711 write_tess_factors(struct radv_shader_context
*ctx
)
2713 unsigned stride
, outer_comps
, inner_comps
;
2714 struct ac_build_if_state if_ctx
, inner_if_ctx
;
2715 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
2716 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
2717 unsigned tess_inner_index
= 0, tess_outer_index
;
2718 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
2719 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
2721 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
2723 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
2743 ac_nir_build_if(&if_ctx
, ctx
,
2744 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
2745 invocation_id
, ctx
->ac
.i32_0
, ""));
2747 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
2750 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
2751 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2752 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
2755 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
2756 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2757 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
2759 for (i
= 0; i
< 4; i
++) {
2760 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
2761 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
2765 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
2766 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
2767 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
2769 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
2771 for (i
= 0; i
< outer_comps
; i
++) {
2773 ac_lds_load(&ctx
->ac
, lds_outer
);
2774 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
2777 for (i
= 0; i
< inner_comps
; i
++) {
2778 inner
[i
] = out
[outer_comps
+i
] =
2779 ac_lds_load(&ctx
->ac
, lds_inner
);
2780 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
2785 /* Convert the outputs to vectors for stores. */
2786 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
2790 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
2793 buffer
= ctx
->hs_ring_tess_factor
;
2794 tf_base
= ctx
->tess_factor_offset
;
2795 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
2796 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
2797 unsigned tf_offset
= 0;
2799 if (ctx
->options
->chip_class
<= VI
) {
2800 ac_nir_build_if(&inner_if_ctx
, ctx
,
2801 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
2802 rel_patch_id
, ctx
->ac
.i32_0
, ""));
2804 /* Store the dynamic HS control word. */
2805 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
2806 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
2807 1, ctx
->ac
.i32_0
, tf_base
,
2808 0, 1, 0, true, false);
2811 ac_nir_build_endif(&inner_if_ctx
);
2814 /* Store the tessellation factors. */
2815 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
2816 MIN2(stride
, 4), byteoffset
, tf_base
,
2817 tf_offset
, 1, 0, true, false);
2819 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
2820 stride
- 4, byteoffset
, tf_base
,
2821 16 + tf_offset
, 1, 0, true, false);
2823 //store to offchip for TES to read - only if TES reads them
2824 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
2825 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
2826 LLVMValueRef tf_inner_offset
;
2827 unsigned param_outer
, param_inner
;
2829 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
2830 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
2831 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
2833 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
2834 util_next_power_of_two(outer_comps
));
2836 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
2837 outer_comps
, tf_outer_offset
,
2838 ctx
->oc_lds
, 0, 1, 0, true, false);
2840 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
2841 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
2842 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
2844 inner_vec
= inner_comps
== 1 ? inner
[0] :
2845 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
2846 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
2847 inner_comps
, tf_inner_offset
,
2848 ctx
->oc_lds
, 0, 1, 0, true, false);
2851 ac_nir_build_endif(&if_ctx
);
2855 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
2857 write_tess_factors(ctx
);
2861 si_export_mrt_color(struct radv_shader_context
*ctx
,
2862 LLVMValueRef
*color
, unsigned index
,
2863 struct ac_export_args
*args
)
2866 si_llvm_init_export_args(ctx
, color
, 0xf,
2867 V_008DFC_SQ_EXP_MRT
+ index
, args
);
2868 if (!args
->enabled_channels
)
2869 return false; /* unnecessary NULL export */
2875 radv_export_mrt_z(struct radv_shader_context
*ctx
,
2876 LLVMValueRef depth
, LLVMValueRef stencil
,
2877 LLVMValueRef samplemask
)
2879 struct ac_export_args args
;
2881 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
2883 ac_build_export(&ctx
->ac
, &args
);
2887 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
2890 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
2891 struct ac_export_args color_args
[8];
2893 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2894 LLVMValueRef values
[4];
2896 if (!(ctx
->output_mask
& (1ull << i
)))
2899 if (i
< FRAG_RESULT_DATA0
)
2902 for (unsigned j
= 0; j
< 4; j
++)
2903 values
[j
] = ac_to_float(&ctx
->ac
,
2904 radv_load_output(ctx
, i
, j
));
2906 bool ret
= si_export_mrt_color(ctx
, values
,
2907 i
- FRAG_RESULT_DATA0
,
2908 &color_args
[index
]);
2913 /* Process depth, stencil, samplemask. */
2914 if (ctx
->shader_info
->info
.ps
.writes_z
) {
2915 depth
= ac_to_float(&ctx
->ac
,
2916 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
2918 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
2919 stencil
= ac_to_float(&ctx
->ac
,
2920 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
2922 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
2923 samplemask
= ac_to_float(&ctx
->ac
,
2924 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
2927 /* Set the DONE bit on last non-null color export only if Z isn't
2931 !ctx
->shader_info
->info
.ps
.writes_z
&&
2932 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
2933 !ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
2934 unsigned last
= index
- 1;
2936 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
2937 color_args
[last
].done
= 1; /* DONE bit */
2940 /* Export PS outputs. */
2941 for (unsigned i
= 0; i
< index
; i
++)
2942 ac_build_export(&ctx
->ac
, &color_args
[i
]);
2944 if (depth
|| stencil
|| samplemask
)
2945 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
2947 ac_build_export_null(&ctx
->ac
);
2951 emit_gs_epilogue(struct radv_shader_context
*ctx
)
2953 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
2957 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
2958 LLVMValueRef
*addrs
)
2960 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2962 switch (ctx
->stage
) {
2963 case MESA_SHADER_VERTEX
:
2964 if (ctx
->options
->key
.vs
.as_ls
)
2965 handle_ls_outputs_post(ctx
);
2966 else if (ctx
->options
->key
.vs
.as_es
)
2967 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
2969 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
2970 ctx
->options
->key
.vs
.export_layer_id
,
2971 &ctx
->shader_info
->vs
.outinfo
);
2973 case MESA_SHADER_FRAGMENT
:
2974 handle_fs_outputs_post(ctx
);
2976 case MESA_SHADER_GEOMETRY
:
2977 emit_gs_epilogue(ctx
);
2979 case MESA_SHADER_TESS_CTRL
:
2980 handle_tcs_outputs_post(ctx
);
2982 case MESA_SHADER_TESS_EVAL
:
2983 if (ctx
->options
->key
.tes
.as_es
)
2984 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
2986 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
2987 ctx
->options
->key
.tes
.export_layer_id
,
2988 &ctx
->shader_info
->tes
.outinfo
);
2995 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
2996 const struct radv_nir_compiler_options
*options
)
2998 LLVMPassManagerRef passmgr
;
2999 /* Create the pass manager */
3000 passmgr
= LLVMCreateFunctionPassManagerForModule(
3003 if (options
->check_ir
)
3004 LLVMAddVerifierPass(passmgr
);
3006 /* This pass should eliminate all the load and store instructions */
3007 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
3009 /* Add some optimization passes */
3010 LLVMAddScalarReplAggregatesPass(passmgr
);
3011 LLVMAddLICMPass(passmgr
);
3012 LLVMAddAggressiveDCEPass(passmgr
);
3013 LLVMAddCFGSimplificationPass(passmgr
);
3014 /* This is recommended by the instruction combining pass. */
3015 LLVMAddEarlyCSEMemSSAPass(passmgr
);
3016 LLVMAddInstructionCombiningPass(passmgr
);
3019 LLVMInitializeFunctionPassManager(passmgr
);
3020 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
3021 LLVMFinalizeFunctionPassManager(passmgr
);
3023 LLVMDisposeBuilder(ctx
->ac
.builder
);
3024 LLVMDisposePassManager(passmgr
);
3026 ac_llvm_context_dispose(&ctx
->ac
);
3030 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
3032 struct radv_vs_output_info
*outinfo
;
3034 switch (ctx
->stage
) {
3035 case MESA_SHADER_FRAGMENT
:
3036 case MESA_SHADER_COMPUTE
:
3037 case MESA_SHADER_TESS_CTRL
:
3038 case MESA_SHADER_GEOMETRY
:
3040 case MESA_SHADER_VERTEX
:
3041 if (ctx
->options
->key
.vs
.as_ls
||
3042 ctx
->options
->key
.vs
.as_es
)
3044 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
3046 case MESA_SHADER_TESS_EVAL
:
3047 if (ctx
->options
->key
.vs
.as_es
)
3049 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
3052 unreachable("Unhandled shader type");
3055 ac_optimize_vs_outputs(&ctx
->ac
,
3057 outinfo
->vs_output_param_offset
,
3059 &outinfo
->param_exports
);
3063 ac_setup_rings(struct radv_shader_context
*ctx
)
3065 if (ctx
->options
->chip_class
<= VI
&&
3066 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
3067 ctx
->options
->key
.vs
.as_es
|| ctx
->options
->key
.tes
.as_es
)) {
3068 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
3070 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
3072 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
3077 if (ctx
->is_gs_copy_shader
) {
3078 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
3080 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3082 uint32_t num_entries
= 64;
3083 LLVMValueRef gsvs_ring_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->max_gsvs_emit_size
, false);
3084 LLVMValueRef gsvs_ring_desc
= LLVMConstInt(ctx
->ac
.i32
, ctx
->max_gsvs_emit_size
<< 16, false);
3085 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
3087 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
3089 tmp
= LLVMConstInt(ctx
->ac
.i32
, num_entries
, false);
3090 if (ctx
->options
->chip_class
>= VI
)
3091 tmp
= LLVMBuildMul(ctx
->ac
.builder
, gsvs_ring_stride
, tmp
, "");
3092 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3093 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
3094 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
, gsvs_ring_desc
, "");
3095 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
3098 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3099 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3100 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
3101 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
3106 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
3107 const struct nir_shader
*nir
)
3109 switch (nir
->info
.stage
) {
3110 case MESA_SHADER_TESS_CTRL
:
3111 return chip_class
>= CIK
? 128 : 64;
3112 case MESA_SHADER_GEOMETRY
:
3113 return chip_class
>= GFX9
? 128 : 64;
3114 case MESA_SHADER_COMPUTE
:
3120 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
3121 nir
->info
.cs
.local_size
[1] *
3122 nir
->info
.cs
.local_size
[2];
3123 return max_workgroup_size
;
3126 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3127 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
3129 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
3130 LLVMConstInt(ctx
->ac
.i32
, 8, false),
3131 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
3132 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
3134 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
3135 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
3136 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
3139 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
3141 for(int i
= 5; i
>= 0; --i
) {
3142 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
3143 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
3144 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
3147 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
3148 LLVMConstInt(ctx
->ac
.i32
, 16, false),
3149 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
3154 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
3155 struct nir_shader
*const *shaders
,
3157 struct radv_shader_variant_info
*shader_info
,
3158 const struct radv_nir_compiler_options
*options
)
3160 struct radv_shader_context ctx
= {0};
3162 ctx
.options
= options
;
3163 ctx
.shader_info
= shader_info
;
3164 ctx
.context
= LLVMContextCreate();
3166 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
3168 ctx
.ac
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
3169 LLVMSetTarget(ctx
.ac
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
3171 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
3172 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
3173 LLVMSetDataLayout(ctx
.ac
.module
, data_layout_str
);
3174 LLVMDisposeTargetData(data_layout
);
3175 LLVMDisposeMessage(data_layout_str
);
3177 enum ac_float_mode float_mode
=
3178 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
3179 AC_FLOAT_MODE_DEFAULT
;
3181 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
3183 memset(shader_info
, 0, sizeof(*shader_info
));
3185 for(int i
= 0; i
< shader_count
; ++i
)
3186 radv_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
3188 for (i
= 0; i
< RADV_UD_MAX_SETS
; i
++)
3189 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
3190 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
3191 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
3193 ctx
.max_workgroup_size
= 0;
3194 for (int i
= 0; i
< shader_count
; ++i
) {
3195 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
3196 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
3200 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
3201 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
3203 ctx
.abi
.inputs
= &ctx
.inputs
[0];
3204 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
3205 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
3206 ctx
.abi
.load_ubo
= radv_load_ubo
;
3207 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
3208 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
3209 ctx
.abi
.load_resource
= radv_load_resource
;
3210 ctx
.abi
.clamp_shadow_reference
= false;
3211 ctx
.abi
.gfx9_stride_size_workaround
= ctx
.ac
.chip_class
== GFX9
;
3213 if (shader_count
>= 2)
3214 ac_init_exec_full_mask(&ctx
.ac
);
3216 if (ctx
.ac
.chip_class
== GFX9
&&
3217 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
3218 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
3220 for(int i
= 0; i
< shader_count
; ++i
) {
3221 ctx
.stage
= shaders
[i
]->info
.stage
;
3222 ctx
.output_mask
= 0;
3223 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
3224 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
3226 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3227 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
3228 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
3229 ctx
.abi
.load_inputs
= load_gs_input
;
3230 ctx
.abi
.emit_primitive
= visit_end_primitive
;
3231 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3232 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
3233 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
3234 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
3235 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3236 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
3237 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3238 if (shader_count
== 1)
3239 ctx
.tcs_num_inputs
= ctx
.options
->key
.tcs
.num_inputs
;
3241 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->info
.vs
.ls_outputs_written
);
3242 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
3243 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
3244 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
3245 ctx
.abi
.load_tess_varyings
= load_tes_input
;
3246 ctx
.abi
.load_tess_coord
= load_tess_coord
;
3247 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3248 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3249 ctx
.tcs_num_patches
= ctx
.options
->key
.tes
.num_patches
;
3250 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
3251 if (shader_info
->info
.vs
.needs_instance_id
) {
3252 if (ctx
.options
->key
.vs
.as_ls
) {
3253 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
3254 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
3256 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
3257 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
3260 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
3261 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
3262 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
3263 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
3264 ctx
.abi
.load_sample_position
= load_sample_position
;
3265 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
3266 ctx
.abi
.emit_kill
= radv_emit_kill
;
3270 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
3272 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
3273 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
3275 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3276 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
3277 shaders
[i
]->info
.cull_distance_array_size
> 4;
3278 ctx
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
3279 ctx
.max_gsvs_emit_size
= ctx
.gsvs_vertex_size
*
3280 shaders
[i
]->info
.gs
.vertices_out
;
3283 ac_setup_rings(&ctx
);
3285 LLVMBasicBlockRef merge_block
;
3286 if (shader_count
>= 2) {
3287 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
3288 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3289 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3291 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
3292 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
3293 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
3294 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
3295 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
3296 thread_id
, count
, "");
3297 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
3299 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
3302 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
3303 handle_fs_inputs(&ctx
, shaders
[i
]);
3304 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
3305 handle_vs_inputs(&ctx
, shaders
[i
]);
3306 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
3307 prepare_gs_input_vgprs(&ctx
);
3309 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
3311 if (shader_count
>= 2) {
3312 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
3313 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
3316 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3317 shader_info
->gs
.gsvs_vertex_size
= ctx
.gsvs_vertex_size
;
3318 shader_info
->gs
.max_gsvs_emit_size
= ctx
.max_gsvs_emit_size
;
3319 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3320 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
3321 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
3325 LLVMBuildRetVoid(ctx
.ac
.builder
);
3327 if (options
->dump_preoptir
)
3328 ac_dump_module(ctx
.ac
.module
);
3330 ac_llvm_finalize_module(&ctx
, options
);
3332 if (shader_count
== 1)
3333 ac_nir_eliminate_const_vs_outputs(&ctx
);
3335 if (options
->dump_shader
) {
3336 ctx
.shader_info
->private_mem_vgprs
=
3337 ac_count_scratch_private_memory(ctx
.main_function
);
3340 return ctx
.ac
.module
;
3343 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
3345 unsigned *retval
= (unsigned *)context
;
3346 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
3347 char *description
= LLVMGetDiagInfoDescription(di
);
3349 if (severity
== LLVMDSError
) {
3351 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
3355 LLVMDisposeMessage(description
);
3358 static unsigned ac_llvm_compile(LLVMModuleRef M
,
3359 struct ac_shader_binary
*binary
,
3360 LLVMTargetMachineRef tm
)
3362 unsigned retval
= 0;
3364 LLVMContextRef llvm_ctx
;
3365 LLVMMemoryBufferRef out_buffer
;
3366 unsigned buffer_size
;
3367 const char *buffer_data
;
3370 /* Setup Diagnostic Handler*/
3371 llvm_ctx
= LLVMGetModuleContext(M
);
3373 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
3377 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
3380 /* Process Errors/Warnings */
3382 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
3388 /* Extract Shader Code*/
3389 buffer_size
= LLVMGetBufferSize(out_buffer
);
3390 buffer_data
= LLVMGetBufferStart(out_buffer
);
3392 ac_elf_read(buffer_data
, buffer_size
, binary
);
3395 LLVMDisposeMemoryBuffer(out_buffer
);
3401 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
3402 LLVMModuleRef llvm_module
,
3403 struct ac_shader_binary
*binary
,
3404 struct ac_shader_config
*config
,
3405 struct radv_shader_variant_info
*shader_info
,
3406 gl_shader_stage stage
,
3407 const struct radv_nir_compiler_options
*options
)
3409 if (options
->dump_shader
)
3410 ac_dump_module(llvm_module
);
3412 memset(binary
, 0, sizeof(*binary
));
3414 if (options
->record_llvm_ir
) {
3415 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
3416 binary
->llvm_ir_string
= strdup(llvm_ir
);
3417 LLVMDisposeMessage(llvm_ir
);
3420 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
3422 fprintf(stderr
, "compile failed\n");
3425 if (options
->dump_shader
)
3426 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
3428 ac_shader_binary_read_config(binary
, config
, 0, options
->supports_spill
);
3430 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
3431 LLVMDisposeModule(llvm_module
);
3432 LLVMContextDispose(ctx
);
3434 if (stage
== MESA_SHADER_FRAGMENT
) {
3435 shader_info
->num_input_vgprs
= 0;
3436 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
3437 shader_info
->num_input_vgprs
+= 2;
3438 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
3439 shader_info
->num_input_vgprs
+= 2;
3440 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
3441 shader_info
->num_input_vgprs
+= 2;
3442 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
3443 shader_info
->num_input_vgprs
+= 3;
3444 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
3445 shader_info
->num_input_vgprs
+= 2;
3446 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
3447 shader_info
->num_input_vgprs
+= 2;
3448 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
3449 shader_info
->num_input_vgprs
+= 2;
3450 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
3451 shader_info
->num_input_vgprs
+= 1;
3452 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
3453 shader_info
->num_input_vgprs
+= 1;
3454 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
3455 shader_info
->num_input_vgprs
+= 1;
3456 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
3457 shader_info
->num_input_vgprs
+= 1;
3458 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
3459 shader_info
->num_input_vgprs
+= 1;
3460 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
3461 shader_info
->num_input_vgprs
+= 1;
3462 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
3463 shader_info
->num_input_vgprs
+= 1;
3464 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
3465 shader_info
->num_input_vgprs
+= 1;
3466 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
3467 shader_info
->num_input_vgprs
+= 1;
3469 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
3471 /* +3 for scratch wave offset and VCC */
3472 config
->num_sgprs
= MAX2(config
->num_sgprs
,
3473 shader_info
->num_input_sgprs
+ 3);
3475 /* Enable 64-bit and 16-bit denormals, because there is no performance
3478 * If denormals are enabled, all floating-point output modifiers are
3481 * Don't enable denormals for 32-bit floats, because:
3482 * - Floating-point output modifiers would be ignored by the hw.
3483 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3484 * have to stop using those.
3485 * - SI & CI would be very slow.
3487 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
3491 ac_fill_shader_info(struct radv_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct radv_nir_compiler_options
*options
)
3493 switch (nir
->info
.stage
) {
3494 case MESA_SHADER_COMPUTE
:
3495 for (int i
= 0; i
< 3; ++i
)
3496 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
3498 case MESA_SHADER_FRAGMENT
:
3499 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
3501 case MESA_SHADER_GEOMETRY
:
3502 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
3503 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
3504 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
3505 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
3507 case MESA_SHADER_TESS_EVAL
:
3508 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
3509 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
3510 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
3511 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
3512 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
3514 case MESA_SHADER_TESS_CTRL
:
3515 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
3517 case MESA_SHADER_VERTEX
:
3518 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
3519 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
3520 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3521 if (options
->key
.vs
.as_ls
)
3522 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
3530 radv_compile_nir_shader(LLVMTargetMachineRef tm
,
3531 struct ac_shader_binary
*binary
,
3532 struct ac_shader_config
*config
,
3533 struct radv_shader_variant_info
*shader_info
,
3534 struct nir_shader
*const *nir
,
3536 const struct radv_nir_compiler_options
*options
)
3539 LLVMModuleRef llvm_module
;
3541 llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
3544 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
,
3545 nir
[0]->info
.stage
, options
);
3547 for (int i
= 0; i
< nir_count
; ++i
)
3548 ac_fill_shader_info(shader_info
, nir
[i
], options
);
3550 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3551 if (options
->chip_class
== GFX9
) {
3552 if (nir_count
== 2 &&
3553 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3554 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
3560 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
3562 LLVMValueRef vtx_offset
=
3563 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
3564 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3567 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3571 if (!(ctx
->output_mask
& (1ull << i
)))
3574 if (i
== VARYING_SLOT_CLIP_DIST0
) {
3575 /* unpack clip and cull from a single set of slots */
3576 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
3581 for (unsigned j
= 0; j
< length
; j
++) {
3582 LLVMValueRef value
, soffset
;
3584 soffset
= LLVMConstInt(ctx
->ac
.i32
,
3586 ctx
->gs_max_out_vertices
* 16 * 4, false);
3588 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->gsvs_ring
,
3590 vtx_offset
, soffset
,
3591 0, 1, 1, true, false);
3593 LLVMBuildStore(ctx
->ac
.builder
,
3594 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3598 handle_vs_outputs_post(ctx
, false, false, &ctx
->shader_info
->vs
.outinfo
);
3602 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm
,
3603 struct nir_shader
*geom_shader
,
3604 struct ac_shader_binary
*binary
,
3605 struct ac_shader_config
*config
,
3606 struct radv_shader_variant_info
*shader_info
,
3607 const struct radv_nir_compiler_options
*options
)
3609 struct radv_shader_context ctx
= {0};
3610 ctx
.context
= LLVMContextCreate();
3611 ctx
.options
= options
;
3612 ctx
.shader_info
= shader_info
;
3614 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
3616 ctx
.ac
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
3618 ctx
.is_gs_copy_shader
= true;
3619 LLVMSetTarget(ctx
.ac
.module
, "amdgcn--");
3621 enum ac_float_mode float_mode
=
3622 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
3623 AC_FLOAT_MODE_DEFAULT
;
3625 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
3626 ctx
.stage
= MESA_SHADER_VERTEX
;
3628 radv_nir_shader_info_pass(geom_shader
, options
, &shader_info
->info
);
3630 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
3632 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
3633 ac_setup_rings(&ctx
);
3635 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
3636 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
3638 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
3639 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
3640 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
3641 variable
, MESA_SHADER_VERTEX
);
3644 ac_gs_copy_shader_emit(&ctx
);
3646 LLVMBuildRetVoid(ctx
.ac
.builder
);
3648 ac_llvm_finalize_module(&ctx
, options
);
3650 ac_compile_llvm_module(tm
, ctx
.ac
.module
, binary
, config
, shader_info
,
3651 MESA_SHADER_VERTEX
, options
);