projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: fix centroid interpolation
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "nir/nir.h"
31
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35 #if HAVE_LLVM >= 0x0700
36 #include <llvm-c/Transforms/Utils.h>
37 #endif
38
39 #include "sid.h"
40 #include "gfx9d.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_llvm_build.h"
44 #include "ac_shader_abi.h"
45 #include "ac_shader_util.h"
46 #include "ac_exp_param.h"
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct radv_shader_context {
51 struct ac_llvm_context ac;
52 const struct radv_nir_compiler_options *options;
53 struct radv_shader_variant_info *shader_info;
54 struct ac_shader_abi abi;
55
56 unsigned max_workgroup_size;
57 LLVMContextRef context;
58 LLVMValueRef main_function;
59
60 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
61 LLVMValueRef ring_offsets;
62
63 LLVMValueRef vertex_buffers;
64 LLVMValueRef rel_auto_id;
65 LLVMValueRef vs_prim_id;
66 LLVMValueRef es2gs_offset;
67
68 LLVMValueRef oc_lds;
69 LLVMValueRef merged_wave_info;
70 LLVMValueRef tess_factor_offset;
71 LLVMValueRef tes_rel_patch_id;
72 LLVMValueRef tes_u;
73 LLVMValueRef tes_v;
74
75 LLVMValueRef gs2vs_offset;
76 LLVMValueRef gs_wave_id;
77 LLVMValueRef gs_vtx_offset[6];
78
79 LLVMValueRef esgs_ring;
80 LLVMValueRef gsvs_ring;
81 LLVMValueRef hs_ring_tess_offchip;
82 LLVMValueRef hs_ring_tess_factor;
83
84 LLVMValueRef sample_pos_offset;
85 LLVMValueRef persp_sample, persp_center, persp_centroid;
86 LLVMValueRef linear_sample, linear_center, linear_centroid;
87
88 gl_shader_stage stage;
89
90 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
91
92 uint64_t input_mask;
93 uint64_t output_mask;
94 uint8_t num_output_clips;
95 uint8_t num_output_culls;
96
97 bool is_gs_copy_shader;
98 LLVMValueRef gs_next_vertex;
99 unsigned gs_max_out_vertices;
100
101 unsigned tes_primitive_mode;
102
103 uint32_t tcs_patch_outputs_read;
104 uint64_t tcs_outputs_read;
105 uint32_t tcs_vertices_per_patch;
106 uint32_t tcs_num_inputs;
107 uint32_t tcs_num_patches;
108 uint32_t max_gsvs_emit_size;
109 uint32_t gsvs_vertex_size;
110 };
111
112 enum radeon_llvm_calling_convention {
113 RADEON_LLVM_AMDGPU_VS = 87,
114 RADEON_LLVM_AMDGPU_GS = 88,
115 RADEON_LLVM_AMDGPU_PS = 89,
116 RADEON_LLVM_AMDGPU_CS = 90,
117 RADEON_LLVM_AMDGPU_HS = 93,
118 };
119
120 static inline struct radv_shader_context *
121 radv_shader_context_from_abi(struct ac_shader_abi *abi)
122 {
123 struct radv_shader_context *ctx = NULL;
124 return container_of(abi, ctx, abi);
125 }
126
127 struct ac_build_if_state
128 {
129 struct radv_shader_context *ctx;
130 LLVMValueRef condition;
131 LLVMBasicBlockRef entry_block;
132 LLVMBasicBlockRef true_block;
133 LLVMBasicBlockRef false_block;
134 LLVMBasicBlockRef merge_block;
135 };
136
137 static LLVMBasicBlockRef
138 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
139 {
140 LLVMBasicBlockRef current_block;
141 LLVMBasicBlockRef next_block;
142 LLVMBasicBlockRef new_block;
143
144 /* get current basic block */
145 current_block = LLVMGetInsertBlock(ctx->ac.builder);
146
147 /* chqeck if there's another block after this one */
148 next_block = LLVMGetNextBasicBlock(current_block);
149 if (next_block) {
150 /* insert the new block before the next block */
151 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
152 }
153 else {
154 /* append new block after current block */
155 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
156 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
157 }
158 return new_block;
159 }
160
161 static void
162 ac_nir_build_if(struct ac_build_if_state *ifthen,
163 struct radv_shader_context *ctx,
164 LLVMValueRef condition)
165 {
166 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
167
168 memset(ifthen, 0, sizeof *ifthen);
169 ifthen->ctx = ctx;
170 ifthen->condition = condition;
171 ifthen->entry_block = block;
172
173 /* create endif/merge basic block for the phi functions */
174 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
175
176 /* create/insert true_block before merge_block */
177 ifthen->true_block =
178 LLVMInsertBasicBlockInContext(ctx->context,
179 ifthen->merge_block,
180 "if-true-block");
181
182 /* successive code goes into the true block */
183 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
184 }
185
186 /**
187 * End a conditional.
188 */
189 static void
190 ac_nir_build_endif(struct ac_build_if_state *ifthen)
191 {
192 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
193
194 /* Insert branch to the merge block from current block */
195 LLVMBuildBr(builder, ifthen->merge_block);
196
197 /*
198 * Now patch in the various branch instructions.
199 */
200
201 /* Insert the conditional branch instruction at the end of entry_block */
202 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
203 if (ifthen->false_block) {
204 /* we have an else clause */
205 LLVMBuildCondBr(builder, ifthen->condition,
206 ifthen->true_block, ifthen->false_block);
207 }
208 else {
209 /* no else clause */
210 LLVMBuildCondBr(builder, ifthen->condition,
211 ifthen->true_block, ifthen->merge_block);
212 }
213
214 /* Resume building code at end of the ifthen->merge_block */
215 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
216 }
217
218
219 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
220 {
221 switch (ctx->stage) {
222 case MESA_SHADER_TESS_CTRL:
223 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
224 case MESA_SHADER_TESS_EVAL:
225 return ctx->tes_rel_patch_id;
226 break;
227 default:
228 unreachable("Illegal stage");
229 }
230 }
231
232 static unsigned
233 get_tcs_num_patches(struct radv_shader_context *ctx)
234 {
235 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
236 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
237 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
238 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
239 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
240 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
241 uint32_t output_vertex_size = num_tcs_outputs * 16;
242 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
243 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
244 unsigned num_patches;
245 unsigned hardware_lds_size;
246
247 /* Ensure that we only need one wave per SIMD so we don't need to check
248 * resource usage. Also ensures that the number of tcs in and out
249 * vertices per threadgroup are at most 256.
250 */
251 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
252 /* Make sure that the data fits in LDS. This assumes the shaders only
253 * use LDS for the inputs and outputs.
254 */
255 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
256 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
257 /* Make sure the output data fits in the offchip buffer */
258 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
259 /* Not necessary for correctness, but improves performance. The
260 * specific value is taken from the proprietary driver.
261 */
262 num_patches = MIN2(num_patches, 40);
263
264 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
265 if (ctx->options->chip_class == SI) {
266 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
267 num_patches = MIN2(num_patches, one_wave);
268 }
269 return num_patches;
270 }
271
272 static unsigned
273 calculate_tess_lds_size(struct radv_shader_context *ctx)
274 {
275 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
276 unsigned num_tcs_output_cp;
277 unsigned num_tcs_outputs, num_tcs_patch_outputs;
278 unsigned input_vertex_size, output_vertex_size;
279 unsigned input_patch_size, output_patch_size;
280 unsigned pervertex_output_patch_size;
281 unsigned output_patch0_offset;
282 unsigned num_patches;
283 unsigned lds_size;
284
285 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
286 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
287 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
288
289 input_vertex_size = ctx->tcs_num_inputs * 16;
290 output_vertex_size = num_tcs_outputs * 16;
291
292 input_patch_size = num_tcs_input_cp * input_vertex_size;
293
294 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
295 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
296
297 num_patches = ctx->tcs_num_patches;
298 output_patch0_offset = input_patch_size * num_patches;
299
300 lds_size = output_patch0_offset + output_patch_size * num_patches;
301 return lds_size;
302 }
303
304 /* Tessellation shaders pass outputs to the next shader using LDS.
305 *
306 * LS outputs = TCS inputs
307 * TCS outputs = TES inputs
308 *
309 * The LDS layout is:
310 * - TCS inputs for patch 0
311 * - TCS inputs for patch 1
312 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
313 * - ...
314 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
315 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
316 * - TCS outputs for patch 1
317 * - Per-patch TCS outputs for patch 1
318 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
319 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
320 * - ...
321 *
322 * All three shaders VS(LS), TCS, TES share the same LDS space.
323 */
324 static LLVMValueRef
325 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
326 {
327 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
328 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
329 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
330
331 input_patch_size /= 4;
332 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
333 }
334
335 static LLVMValueRef
336 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
337 {
338 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
339 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
340 uint32_t output_vertex_size = num_tcs_outputs * 16;
341 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
342 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
343 output_patch_size /= 4;
344 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
345 }
346
347 static LLVMValueRef
348 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
349 {
350 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
351 uint32_t output_vertex_size = num_tcs_outputs * 16;
352 output_vertex_size /= 4;
353 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
354 }
355
356 static LLVMValueRef
357 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
358 {
359 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
360 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
361 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
362 uint32_t output_patch0_offset = input_patch_size;
363 unsigned num_patches = ctx->tcs_num_patches;
364
365 output_patch0_offset *= num_patches;
366 output_patch0_offset /= 4;
367 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
368 }
369
370 static LLVMValueRef
371 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
372 {
373 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
374 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
375 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
376 uint32_t output_patch0_offset = input_patch_size;
377
378 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
379 uint32_t output_vertex_size = num_tcs_outputs * 16;
380 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
381 unsigned num_patches = ctx->tcs_num_patches;
382
383 output_patch0_offset *= num_patches;
384 output_patch0_offset += pervertex_output_patch_size;
385 output_patch0_offset /= 4;
386 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
387 }
388
389 static LLVMValueRef
390 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
391 {
392 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
393 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
394
395 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
396 }
397
398 static LLVMValueRef
399 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
400 {
401 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
402 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
403 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
404
405 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
406 LLVMBuildMul(ctx->ac.builder, patch_stride,
407 rel_patch_id, ""),
408 "");
409 }
410
411 static LLVMValueRef
412 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
413 {
414 LLVMValueRef patch0_patch_data_offset =
415 get_tcs_out_patch0_patch_data_offset(ctx);
416 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
417 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
418
419 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
420 LLVMBuildMul(ctx->ac.builder, patch_stride,
421 rel_patch_id, ""),
422 "");
423 }
424
425 #define MAX_ARGS 23
426 struct arg_info {
427 LLVMTypeRef types[MAX_ARGS];
428 LLVMValueRef *assign[MAX_ARGS];
429 unsigned array_params_mask;
430 uint8_t count;
431 uint8_t sgpr_count;
432 uint8_t num_sgprs_used;
433 uint8_t num_vgprs_used;
434 };
435
436 enum ac_arg_regfile {
437 ARG_SGPR,
438 ARG_VGPR,
439 };
440
441 static void
442 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
443 LLVMValueRef *param_ptr)
444 {
445 assert(info->count < MAX_ARGS);
446
447 info->assign[info->count] = param_ptr;
448 info->types[info->count] = type;
449 info->count++;
450
451 if (regfile == ARG_SGPR) {
452 info->num_sgprs_used += ac_get_type_size(type) / 4;
453 info->sgpr_count++;
454 } else {
455 assert(regfile == ARG_VGPR);
456 info->num_vgprs_used += ac_get_type_size(type) / 4;
457 }
458 }
459
460 static inline void
461 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
462 {
463 info->array_params_mask |= (1 << info->count);
464 add_arg(info, ARG_SGPR, type, param_ptr);
465 }
466
467 static void assign_arguments(LLVMValueRef main_function,
468 struct arg_info *info)
469 {
470 unsigned i;
471 for (i = 0; i < info->count; i++) {
472 if (info->assign[i])
473 *info->assign[i] = LLVMGetParam(main_function, i);
474 }
475 }
476
477 static LLVMValueRef
478 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
479 LLVMBuilderRef builder, LLVMTypeRef *return_types,
480 unsigned num_return_elems,
481 struct arg_info *args,
482 unsigned max_workgroup_size,
483 const struct radv_nir_compiler_options *options)
484 {
485 LLVMTypeRef main_function_type, ret_type;
486 LLVMBasicBlockRef main_function_body;
487
488 if (num_return_elems)
489 ret_type = LLVMStructTypeInContext(ctx, return_types,
490 num_return_elems, true);
491 else
492 ret_type = LLVMVoidTypeInContext(ctx);
493
494 /* Setup the function */
495 main_function_type =
496 LLVMFunctionType(ret_type, args->types, args->count, 0);
497 LLVMValueRef main_function =
498 LLVMAddFunction(module, "main", main_function_type);
499 main_function_body =
500 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
501 LLVMPositionBuilderAtEnd(builder, main_function_body);
502
503 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
504 for (unsigned i = 0; i < args->sgpr_count; ++i) {
505 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
506
507 if (args->array_params_mask & (1 << i)) {
508 LLVMValueRef P = LLVMGetParam(main_function, i);
509 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
510 ac_add_attr_dereferenceable(P, UINT64_MAX);
511 }
512 }
513
514 if (max_workgroup_size) {
515 ac_llvm_add_target_dep_function_attr(main_function,
516 "amdgpu-max-work-group-size",
517 max_workgroup_size);
518 }
519 if (options->unsafe_math) {
520 /* These were copied from some LLVM test. */
521 LLVMAddTargetDependentFunctionAttr(main_function,
522 "less-precise-fpmad",
523 "true");
524 LLVMAddTargetDependentFunctionAttr(main_function,
525 "no-infs-fp-math",
526 "true");
527 LLVMAddTargetDependentFunctionAttr(main_function,
528 "no-nans-fp-math",
529 "true");
530 LLVMAddTargetDependentFunctionAttr(main_function,
531 "unsafe-fp-math",
532 "true");
533 LLVMAddTargetDependentFunctionAttr(main_function,
534 "no-signed-zeros-fp-math",
535 "true");
536 }
537 return main_function;
538 }
539
540
541 static void
542 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
543 uint32_t indirect_offset)
544 {
545 ud_info->sgpr_idx = *sgpr_idx;
546 ud_info->num_sgprs = num_sgprs;
547 ud_info->indirect = indirect_offset > 0;
548 ud_info->indirect_offset = indirect_offset;
549 *sgpr_idx += num_sgprs;
550 }
551
552 static void
553 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
554 uint8_t num_sgprs)
555 {
556 struct radv_userdata_info *ud_info =
557 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
558 assert(ud_info);
559
560 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
561 }
562
563 static void
564 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
565 uint32_t indirect_offset)
566 {
567 struct radv_userdata_info *ud_info =
568 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
569 assert(ud_info);
570
571 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
572 }
573
574 struct user_sgpr_info {
575 bool need_ring_offsets;
576 uint8_t sgpr_count;
577 bool indirect_all_descriptor_sets;
578 };
579
580 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
581 gl_shader_stage stage)
582 {
583 switch (stage) {
584 case MESA_SHADER_VERTEX:
585 if (ctx->shader_info->info.needs_multiview_view_index ||
586 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
587 return true;
588 break;
589 case MESA_SHADER_TESS_EVAL:
590 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
591 return true;
592 break;
593 case MESA_SHADER_GEOMETRY:
594 case MESA_SHADER_TESS_CTRL:
595 if (ctx->shader_info->info.needs_multiview_view_index)
596 return true;
597 break;
598 default:
599 break;
600 }
601 return false;
602 }
603
604 static uint8_t
605 count_vs_user_sgprs(struct radv_shader_context *ctx)
606 {
607 uint8_t count = 0;
608
609 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
610 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
611
612 return count;
613 }
614
615 static void allocate_user_sgprs(struct radv_shader_context *ctx,
616 gl_shader_stage stage,
617 bool has_previous_stage,
618 gl_shader_stage previous_stage,
619 bool needs_view_index,
620 struct user_sgpr_info *user_sgpr_info)
621 {
622 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
623
624 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
625 if (stage == MESA_SHADER_GEOMETRY ||
626 stage == MESA_SHADER_VERTEX ||
627 stage == MESA_SHADER_TESS_CTRL ||
628 stage == MESA_SHADER_TESS_EVAL ||
629 ctx->is_gs_copy_shader)
630 user_sgpr_info->need_ring_offsets = true;
631
632 if (stage == MESA_SHADER_FRAGMENT &&
633 ctx->shader_info->info.ps.needs_sample_positions)
634 user_sgpr_info->need_ring_offsets = true;
635
636 /* 2 user sgprs will nearly always be allocated for scratch/rings */
637 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
638 user_sgpr_info->sgpr_count += 2;
639 }
640
641 switch (stage) {
642 case MESA_SHADER_COMPUTE:
643 if (ctx->shader_info->info.cs.uses_grid_size)
644 user_sgpr_info->sgpr_count += 3;
645 break;
646 case MESA_SHADER_FRAGMENT:
647 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
648 break;
649 case MESA_SHADER_VERTEX:
650 if (!ctx->is_gs_copy_shader)
651 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
652 break;
653 case MESA_SHADER_TESS_CTRL:
654 if (has_previous_stage) {
655 if (previous_stage == MESA_SHADER_VERTEX)
656 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
657 }
658 break;
659 case MESA_SHADER_TESS_EVAL:
660 break;
661 case MESA_SHADER_GEOMETRY:
662 if (has_previous_stage) {
663 if (previous_stage == MESA_SHADER_VERTEX) {
664 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
665 }
666 }
667 break;
668 default:
669 break;
670 }
671
672 if (needs_view_index)
673 user_sgpr_info->sgpr_count++;
674
675 if (ctx->shader_info->info.loads_push_constants)
676 user_sgpr_info->sgpr_count += 2;
677
678 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
679 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
680
681 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
682 user_sgpr_info->sgpr_count += 2;
683 user_sgpr_info->indirect_all_descriptor_sets = true;
684 } else {
685 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
686 }
687 }
688
689 static void
690 declare_global_input_sgprs(struct radv_shader_context *ctx,
691 gl_shader_stage stage,
692 bool has_previous_stage,
693 gl_shader_stage previous_stage,
694 const struct user_sgpr_info *user_sgpr_info,
695 struct arg_info *args,
696 LLVMValueRef *desc_sets)
697 {
698 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
699 unsigned num_sets = ctx->options->layout ?
700 ctx->options->layout->num_sets : 0;
701 unsigned stage_mask = 1 << stage;
702
703 if (has_previous_stage)
704 stage_mask |= 1 << previous_stage;
705
706 /* 1 for each descriptor set */
707 if (!user_sgpr_info->indirect_all_descriptor_sets) {
708 for (unsigned i = 0; i < num_sets; ++i) {
709 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
710 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
711 add_array_arg(args, type,
712 &ctx->descriptor_sets[i]);
713 }
714 }
715 } else {
716 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
717 }
718
719 if (ctx->shader_info->info.loads_push_constants) {
720 /* 1 for push constants and dynamic descriptors */
721 add_array_arg(args, type, &ctx->abi.push_constants);
722 }
723 }
724
725 static void
726 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
727 gl_shader_stage stage,
728 bool has_previous_stage,
729 gl_shader_stage previous_stage,
730 struct arg_info *args)
731 {
732 if (!ctx->is_gs_copy_shader &&
733 (stage == MESA_SHADER_VERTEX ||
734 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
735 if (ctx->shader_info->info.vs.has_vertex_buffers) {
736 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
737 &ctx->vertex_buffers);
738 }
739 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
740 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
741 if (ctx->shader_info->info.vs.needs_draw_id) {
742 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
743 }
744 }
745 }
746
747 static void
748 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
749 {
750 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
751 if (!ctx->is_gs_copy_shader) {
752 if (ctx->options->key.vs.as_ls) {
753 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
754 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
755 } else {
756 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
757 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
758 }
759 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
760 }
761 }
762
763 static void
764 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
765 {
766 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
767 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
768 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
769 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
770 }
771
772 static void
773 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
774 bool has_previous_stage, gl_shader_stage previous_stage,
775 const struct user_sgpr_info *user_sgpr_info,
776 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
777 {
778 unsigned num_sets = ctx->options->layout ?
779 ctx->options->layout->num_sets : 0;
780 unsigned stage_mask = 1 << stage;
781
782 if (has_previous_stage)
783 stage_mask |= 1 << previous_stage;
784
785 if (!user_sgpr_info->indirect_all_descriptor_sets) {
786 for (unsigned i = 0; i < num_sets; ++i) {
787 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
788 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
789 set_loc_desc(ctx, i, user_sgpr_idx, 0);
790 } else
791 ctx->descriptor_sets[i] = NULL;
792 }
793 } else {
794 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
795 user_sgpr_idx, 2);
796
797 for (unsigned i = 0; i < num_sets; ++i) {
798 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
799 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
800 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
801 ctx->descriptor_sets[i] =
802 ac_build_load_to_sgpr(&ctx->ac,
803 desc_sets,
804 LLVMConstInt(ctx->ac.i32, i, false));
805
806 } else
807 ctx->descriptor_sets[i] = NULL;
808 }
809 ctx->shader_info->need_indirect_descriptor_sets = true;
810 }
811
812 if (ctx->shader_info->info.loads_push_constants) {
813 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
814 }
815 }
816
817 static void
818 set_vs_specific_input_locs(struct radv_shader_context *ctx,
819 gl_shader_stage stage, bool has_previous_stage,
820 gl_shader_stage previous_stage,
821 uint8_t *user_sgpr_idx)
822 {
823 if (!ctx->is_gs_copy_shader &&
824 (stage == MESA_SHADER_VERTEX ||
825 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
826 if (ctx->shader_info->info.vs.has_vertex_buffers) {
827 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
828 user_sgpr_idx, 2);
829 }
830
831 unsigned vs_num = 2;
832 if (ctx->shader_info->info.vs.needs_draw_id)
833 vs_num++;
834
835 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
836 user_sgpr_idx, vs_num);
837 }
838 }
839
840 static void set_llvm_calling_convention(LLVMValueRef func,
841 gl_shader_stage stage)
842 {
843 enum radeon_llvm_calling_convention calling_conv;
844
845 switch (stage) {
846 case MESA_SHADER_VERTEX:
847 case MESA_SHADER_TESS_EVAL:
848 calling_conv = RADEON_LLVM_AMDGPU_VS;
849 break;
850 case MESA_SHADER_GEOMETRY:
851 calling_conv = RADEON_LLVM_AMDGPU_GS;
852 break;
853 case MESA_SHADER_TESS_CTRL:
854 calling_conv = RADEON_LLVM_AMDGPU_HS;
855 break;
856 case MESA_SHADER_FRAGMENT:
857 calling_conv = RADEON_LLVM_AMDGPU_PS;
858 break;
859 case MESA_SHADER_COMPUTE:
860 calling_conv = RADEON_LLVM_AMDGPU_CS;
861 break;
862 default:
863 unreachable("Unhandle shader type");
864 }
865
866 LLVMSetFunctionCallConv(func, calling_conv);
867 }
868
869 static void create_function(struct radv_shader_context *ctx,
870 gl_shader_stage stage,
871 bool has_previous_stage,
872 gl_shader_stage previous_stage)
873 {
874 uint8_t user_sgpr_idx;
875 struct user_sgpr_info user_sgpr_info;
876 struct arg_info args = {};
877 LLVMValueRef desc_sets;
878 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
879 allocate_user_sgprs(ctx, stage, has_previous_stage,
880 previous_stage, needs_view_index, &user_sgpr_info);
881
882 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
883 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
884 &ctx->ring_offsets);
885 }
886
887 switch (stage) {
888 case MESA_SHADER_COMPUTE:
889 declare_global_input_sgprs(ctx, stage, has_previous_stage,
890 previous_stage, &user_sgpr_info,
891 &args, &desc_sets);
892
893 if (ctx->shader_info->info.cs.uses_grid_size) {
894 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
895 &ctx->abi.num_work_groups);
896 }
897
898 for (int i = 0; i < 3; i++) {
899 ctx->abi.workgroup_ids[i] = NULL;
900 if (ctx->shader_info->info.cs.uses_block_id[i]) {
901 add_arg(&args, ARG_SGPR, ctx->ac.i32,
902 &ctx->abi.workgroup_ids[i]);
903 }
904 }
905
906 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
907 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
908 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
909 &ctx->abi.local_invocation_ids);
910 break;
911 case MESA_SHADER_VERTEX:
912 declare_global_input_sgprs(ctx, stage, has_previous_stage,
913 previous_stage, &user_sgpr_info,
914 &args, &desc_sets);
915 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
916 previous_stage, &args);
917
918 if (needs_view_index)
919 add_arg(&args, ARG_SGPR, ctx->ac.i32,
920 &ctx->abi.view_index);
921 if (ctx->options->key.vs.as_es)
922 add_arg(&args, ARG_SGPR, ctx->ac.i32,
923 &ctx->es2gs_offset);
924
925 declare_vs_input_vgprs(ctx, &args);
926 break;
927 case MESA_SHADER_TESS_CTRL:
928 if (has_previous_stage) {
929 // First 6 system regs
930 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
931 add_arg(&args, ARG_SGPR, ctx->ac.i32,
932 &ctx->merged_wave_info);
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->tess_factor_offset);
935
936 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
937 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
938 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
939
940 declare_global_input_sgprs(ctx, stage,
941 has_previous_stage,
942 previous_stage,
943 &user_sgpr_info, &args,
944 &desc_sets);
945 declare_vs_specific_input_sgprs(ctx, stage,
946 has_previous_stage,
947 previous_stage, &args);
948
949 if (needs_view_index)
950 add_arg(&args, ARG_SGPR, ctx->ac.i32,
951 &ctx->abi.view_index);
952
953 add_arg(&args, ARG_VGPR, ctx->ac.i32,
954 &ctx->abi.tcs_patch_id);
955 add_arg(&args, ARG_VGPR, ctx->ac.i32,
956 &ctx->abi.tcs_rel_ids);
957
958 declare_vs_input_vgprs(ctx, &args);
959 } else {
960 declare_global_input_sgprs(ctx, stage,
961 has_previous_stage,
962 previous_stage,
963 &user_sgpr_info, &args,
964 &desc_sets);
965
966 if (needs_view_index)
967 add_arg(&args, ARG_SGPR, ctx->ac.i32,
968 &ctx->abi.view_index);
969
970 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->tess_factor_offset);
973 add_arg(&args, ARG_VGPR, ctx->ac.i32,
974 &ctx->abi.tcs_patch_id);
975 add_arg(&args, ARG_VGPR, ctx->ac.i32,
976 &ctx->abi.tcs_rel_ids);
977 }
978 break;
979 case MESA_SHADER_TESS_EVAL:
980 declare_global_input_sgprs(ctx, stage, has_previous_stage,
981 previous_stage, &user_sgpr_info,
982 &args, &desc_sets);
983
984 if (needs_view_index)
985 add_arg(&args, ARG_SGPR, ctx->ac.i32,
986 &ctx->abi.view_index);
987
988 if (ctx->options->key.tes.as_es) {
989 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
990 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
991 add_arg(&args, ARG_SGPR, ctx->ac.i32,
992 &ctx->es2gs_offset);
993 } else {
994 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
995 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
996 }
997 declare_tes_input_vgprs(ctx, &args);
998 break;
999 case MESA_SHADER_GEOMETRY:
1000 if (has_previous_stage) {
1001 // First 6 system regs
1002 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1003 &ctx->gs2vs_offset);
1004 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1005 &ctx->merged_wave_info);
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1007
1008 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1009 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1010 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1011
1012 declare_global_input_sgprs(ctx, stage,
1013 has_previous_stage,
1014 previous_stage,
1015 &user_sgpr_info, &args,
1016 &desc_sets);
1017
1018 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1019 declare_vs_specific_input_sgprs(ctx, stage,
1020 has_previous_stage,
1021 previous_stage,
1022 &args);
1023 }
1024
1025 if (needs_view_index)
1026 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1027 &ctx->abi.view_index);
1028
1029 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1030 &ctx->gs_vtx_offset[0]);
1031 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1032 &ctx->gs_vtx_offset[2]);
1033 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1034 &ctx->abi.gs_prim_id);
1035 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1036 &ctx->abi.gs_invocation_id);
1037 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1038 &ctx->gs_vtx_offset[4]);
1039
1040 if (previous_stage == MESA_SHADER_VERTEX) {
1041 declare_vs_input_vgprs(ctx, &args);
1042 } else {
1043 declare_tes_input_vgprs(ctx, &args);
1044 }
1045 } else {
1046 declare_global_input_sgprs(ctx, stage,
1047 has_previous_stage,
1048 previous_stage,
1049 &user_sgpr_info, &args,
1050 &desc_sets);
1051
1052 if (needs_view_index)
1053 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1054 &ctx->abi.view_index);
1055
1056 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1057 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1058 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1059 &ctx->gs_vtx_offset[0]);
1060 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1061 &ctx->gs_vtx_offset[1]);
1062 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1063 &ctx->abi.gs_prim_id);
1064 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1065 &ctx->gs_vtx_offset[2]);
1066 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1067 &ctx->gs_vtx_offset[3]);
1068 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1069 &ctx->gs_vtx_offset[4]);
1070 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1071 &ctx->gs_vtx_offset[5]);
1072 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1073 &ctx->abi.gs_invocation_id);
1074 }
1075 break;
1076 case MESA_SHADER_FRAGMENT:
1077 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1078 previous_stage, &user_sgpr_info,
1079 &args, &desc_sets);
1080
1081 if (ctx->shader_info->info.ps.needs_sample_positions)
1082 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1083 &ctx->sample_pos_offset);
1084
1085 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1086 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1087 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1088 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1089 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1090 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1091 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1092 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1093 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1094 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1095 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1096 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1097 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1098 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1099 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1100 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1101 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1102 break;
1103 default:
1104 unreachable("Shader stage not implemented");
1105 }
1106
1107 ctx->main_function = create_llvm_function(
1108 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1109 ctx->max_workgroup_size, ctx->options);
1110 set_llvm_calling_convention(ctx->main_function, stage);
1111
1112
1113 ctx->shader_info->num_input_vgprs = 0;
1114 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1115
1116 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1117
1118 if (ctx->stage != MESA_SHADER_FRAGMENT)
1119 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1120
1121 assign_arguments(ctx->main_function, &args);
1122
1123 user_sgpr_idx = 0;
1124
1125 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1126 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1127 &user_sgpr_idx, 2);
1128 if (ctx->options->supports_spill) {
1129 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1130 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1131 NULL, 0, AC_FUNC_ATTR_READNONE);
1132 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1133 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1134 }
1135 }
1136
1137 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1138 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1139 if (has_previous_stage)
1140 user_sgpr_idx = 0;
1141
1142 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1143 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1144
1145 switch (stage) {
1146 case MESA_SHADER_COMPUTE:
1147 if (ctx->shader_info->info.cs.uses_grid_size) {
1148 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1149 &user_sgpr_idx, 3);
1150 }
1151 break;
1152 case MESA_SHADER_VERTEX:
1153 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1154 previous_stage, &user_sgpr_idx);
1155 if (ctx->abi.view_index)
1156 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1157 break;
1158 case MESA_SHADER_TESS_CTRL:
1159 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1160 previous_stage, &user_sgpr_idx);
1161 if (ctx->abi.view_index)
1162 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1163 break;
1164 case MESA_SHADER_TESS_EVAL:
1165 if (ctx->abi.view_index)
1166 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1167 break;
1168 case MESA_SHADER_GEOMETRY:
1169 if (has_previous_stage) {
1170 if (previous_stage == MESA_SHADER_VERTEX)
1171 set_vs_specific_input_locs(ctx, stage,
1172 has_previous_stage,
1173 previous_stage,
1174 &user_sgpr_idx);
1175 }
1176 if (ctx->abi.view_index)
1177 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1178 break;
1179 case MESA_SHADER_FRAGMENT:
1180 if (ctx->shader_info->info.ps.needs_sample_positions) {
1181 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1182 &user_sgpr_idx, 1);
1183 }
1184 break;
1185 default:
1186 unreachable("Shader stage not implemented");
1187 }
1188
1189 if (stage == MESA_SHADER_TESS_CTRL ||
1190 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1191 /* GFX9 has the ESGS ring buffer in LDS. */
1192 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1193 ac_declare_lds_as_pointer(&ctx->ac);
1194 }
1195
1196 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1197 }
1198
1199
1200 static LLVMValueRef
1201 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1202 unsigned desc_set, unsigned binding)
1203 {
1204 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1205 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1206 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1207 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1208 unsigned base_offset = layout->binding[binding].offset;
1209 LLVMValueRef offset, stride;
1210
1211 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1212 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1213 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1214 layout->binding[binding].dynamic_offset_offset;
1215 desc_ptr = ctx->abi.push_constants;
1216 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1217 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1218 } else
1219 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1220
1221 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1222 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
1223 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
1224
1225 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1226 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1227 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1228
1229 return desc_ptr;
1230 }
1231
1232
1233 /* The offchip buffer layout for TCS->TES is
1234 *
1235 * - attribute 0 of patch 0 vertex 0
1236 * - attribute 0 of patch 0 vertex 1
1237 * - attribute 0 of patch 0 vertex 2
1238 * ...
1239 * - attribute 0 of patch 1 vertex 0
1240 * - attribute 0 of patch 1 vertex 1
1241 * ...
1242 * - attribute 1 of patch 0 vertex 0
1243 * - attribute 1 of patch 0 vertex 1
1244 * ...
1245 * - per patch attribute 0 of patch 0
1246 * - per patch attribute 0 of patch 1
1247 * ...
1248 *
1249 * Note that every attribute has 4 components.
1250 */
1251 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1252 {
1253 uint32_t num_patches = ctx->tcs_num_patches;
1254 uint32_t num_tcs_outputs;
1255 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1256 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1257 else
1258 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1259
1260 uint32_t output_vertex_size = num_tcs_outputs * 16;
1261 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1262
1263 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1264 }
1265
1266 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1267 LLVMValueRef vertex_index)
1268 {
1269 LLVMValueRef param_stride;
1270 if (vertex_index)
1271 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1272 else
1273 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1274 return param_stride;
1275 }
1276
1277 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1278 LLVMValueRef vertex_index,
1279 LLVMValueRef param_index)
1280 {
1281 LLVMValueRef base_addr;
1282 LLVMValueRef param_stride, constant16;
1283 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1284 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1285 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1286 param_stride = calc_param_stride(ctx, vertex_index);
1287 if (vertex_index) {
1288 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
1289 vertices_per_patch, "");
1290
1291 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1292 vertex_index, "");
1293 } else {
1294 base_addr = rel_patch_id;
1295 }
1296
1297 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1298 LLVMBuildMul(ctx->ac.builder, param_index,
1299 param_stride, ""), "");
1300
1301 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1302
1303 if (!vertex_index) {
1304 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1305
1306 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1307 patch_data_offset, "");
1308 }
1309 return base_addr;
1310 }
1311
1312 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1313 unsigned param,
1314 unsigned const_index,
1315 bool is_compact,
1316 LLVMValueRef vertex_index,
1317 LLVMValueRef indir_index)
1318 {
1319 LLVMValueRef param_index;
1320
1321 if (indir_index)
1322 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1323 indir_index, "");
1324 else {
1325 if (const_index && !is_compact)
1326 param += const_index;
1327 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1328 }
1329 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1330 }
1331
1332 static LLVMValueRef
1333 get_dw_address(struct radv_shader_context *ctx,
1334 LLVMValueRef dw_addr,
1335 unsigned param,
1336 unsigned const_index,
1337 bool compact_const_index,
1338 LLVMValueRef vertex_index,
1339 LLVMValueRef stride,
1340 LLVMValueRef indir_index)
1341
1342 {
1343
1344 if (vertex_index) {
1345 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1346 LLVMBuildMul(ctx->ac.builder,
1347 vertex_index,
1348 stride, ""), "");
1349 }
1350
1351 if (indir_index)
1352 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1353 LLVMBuildMul(ctx->ac.builder, indir_index,
1354 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1355 else if (const_index && !compact_const_index)
1356 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1357 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1358
1359 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1360 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1361
1362 if (const_index && compact_const_index)
1363 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1364 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1365 return dw_addr;
1366 }
1367
1368 static LLVMValueRef
1369 load_tcs_varyings(struct ac_shader_abi *abi,
1370 LLVMTypeRef type,
1371 LLVMValueRef vertex_index,
1372 LLVMValueRef indir_index,
1373 unsigned const_index,
1374 unsigned location,
1375 unsigned driver_location,
1376 unsigned component,
1377 unsigned num_components,
1378 bool is_patch,
1379 bool is_compact,
1380 bool load_input)
1381 {
1382 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1383 LLVMValueRef dw_addr, stride;
1384 LLVMValueRef value[4], result;
1385 unsigned param = shader_io_get_unique_index(location);
1386
1387 if (load_input) {
1388 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1389 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1390 dw_addr = get_tcs_in_current_patch_offset(ctx);
1391 } else {
1392 if (!is_patch) {
1393 stride = get_tcs_out_vertex_stride(ctx);
1394 dw_addr = get_tcs_out_current_patch_offset(ctx);
1395 } else {
1396 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1397 stride = NULL;
1398 }
1399 }
1400
1401 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1402 indir_index);
1403
1404 for (unsigned i = 0; i < num_components + component; i++) {
1405 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1406 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1407 ctx->ac.i32_1, "");
1408 }
1409 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1410 return result;
1411 }
1412
1413 static void
1414 store_tcs_output(struct ac_shader_abi *abi,
1415 const nir_variable *var,
1416 LLVMValueRef vertex_index,
1417 LLVMValueRef param_index,
1418 unsigned const_index,
1419 LLVMValueRef src,
1420 unsigned writemask)
1421 {
1422 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1423 const unsigned location = var->data.location;
1424 const unsigned component = var->data.location_frac;
1425 const bool is_patch = var->data.patch;
1426 const bool is_compact = var->data.compact;
1427 LLVMValueRef dw_addr;
1428 LLVMValueRef stride = NULL;
1429 LLVMValueRef buf_addr = NULL;
1430 unsigned param;
1431 bool store_lds = true;
1432
1433 if (is_patch) {
1434 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1435 store_lds = false;
1436 } else {
1437 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1438 store_lds = false;
1439 }
1440
1441 param = shader_io_get_unique_index(location);
1442 if (location == VARYING_SLOT_CLIP_DIST0 &&
1443 is_compact && const_index > 3) {
1444 const_index -= 3;
1445 param++;
1446 }
1447
1448 if (!is_patch) {
1449 stride = get_tcs_out_vertex_stride(ctx);
1450 dw_addr = get_tcs_out_current_patch_offset(ctx);
1451 } else {
1452 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1453 }
1454
1455 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1456 param_index);
1457 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1458 vertex_index, param_index);
1459
1460 bool is_tess_factor = false;
1461 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1462 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1463 is_tess_factor = true;
1464
1465 unsigned base = is_compact ? const_index : 0;
1466 for (unsigned chan = 0; chan < 8; chan++) {
1467 if (!(writemask & (1 << chan)))
1468 continue;
1469 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1470
1471 if (store_lds || is_tess_factor) {
1472 LLVMValueRef dw_addr_chan =
1473 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1474 LLVMConstInt(ctx->ac.i32, chan, false), "");
1475 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1476 }
1477
1478 if (!is_tess_factor && writemask != 0xF)
1479 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1480 buf_addr, ctx->oc_lds,
1481 4 * (base + chan), 1, 0, true, false);
1482 }
1483
1484 if (writemask == 0xF) {
1485 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1486 buf_addr, ctx->oc_lds,
1487 (base * 4), 1, 0, true, false);
1488 }
1489 }
1490
1491 static LLVMValueRef
1492 load_tes_input(struct ac_shader_abi *abi,
1493 LLVMTypeRef type,
1494 LLVMValueRef vertex_index,
1495 LLVMValueRef param_index,
1496 unsigned const_index,
1497 unsigned location,
1498 unsigned driver_location,
1499 unsigned component,
1500 unsigned num_components,
1501 bool is_patch,
1502 bool is_compact,
1503 bool load_input)
1504 {
1505 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1506 LLVMValueRef buf_addr;
1507 LLVMValueRef result;
1508 unsigned param = shader_io_get_unique_index(location);
1509
1510 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1511 const_index -= 3;
1512 param++;
1513 }
1514
1515 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1516 is_compact, vertex_index, param_index);
1517
1518 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1519 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1520
1521 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1522 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1523 result = ac_trim_vector(&ctx->ac, result, num_components);
1524 return result;
1525 }
1526
1527 static LLVMValueRef
1528 load_gs_input(struct ac_shader_abi *abi,
1529 unsigned location,
1530 unsigned driver_location,
1531 unsigned component,
1532 unsigned num_components,
1533 unsigned vertex_index,
1534 unsigned const_index,
1535 LLVMTypeRef type)
1536 {
1537 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1538 LLVMValueRef vtx_offset;
1539 unsigned param, vtx_offset_param;
1540 LLVMValueRef value[4], result;
1541
1542 vtx_offset_param = vertex_index;
1543 assert(vtx_offset_param < 6);
1544 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1545 LLVMConstInt(ctx->ac.i32, 4, false), "");
1546
1547 param = shader_io_get_unique_index(location);
1548
1549 for (unsigned i = component; i < num_components + component; i++) {
1550 if (ctx->ac.chip_class >= GFX9) {
1551 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1552 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1553 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1554 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1555 } else {
1556 LLVMValueRef soffset =
1557 LLVMConstInt(ctx->ac.i32,
1558 (param * 4 + i + const_index) * 256,
1559 false);
1560
1561 value[i] = ac_build_buffer_load(&ctx->ac,
1562 ctx->esgs_ring, 1,
1563 ctx->ac.i32_0,
1564 vtx_offset, soffset,
1565 0, 1, 0, true, false);
1566
1567 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
1568 type, "");
1569 }
1570 }
1571 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1572 result = ac_to_integer(&ctx->ac, result);
1573 return result;
1574 }
1575
1576
1577 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1578 {
1579 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1580 ac_build_kill_if_false(&ctx->ac, visible);
1581 }
1582
1583 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1584 enum glsl_interp_mode interp, unsigned location)
1585 {
1586 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1587
1588 switch (interp) {
1589 case INTERP_MODE_FLAT:
1590 default:
1591 return NULL;
1592 case INTERP_MODE_SMOOTH:
1593 case INTERP_MODE_NONE:
1594 if (location == INTERP_CENTER)
1595 return ctx->persp_center;
1596 else if (location == INTERP_CENTROID)
1597 return ctx->persp_centroid;
1598 else if (location == INTERP_SAMPLE)
1599 return ctx->persp_sample;
1600 break;
1601 case INTERP_MODE_NOPERSPECTIVE:
1602 if (location == INTERP_CENTER)
1603 return ctx->linear_center;
1604 else if (location == INTERP_CENTROID)
1605 return ctx->linear_centroid;
1606 else if (location == INTERP_SAMPLE)
1607 return ctx->linear_sample;
1608 break;
1609 }
1610 return NULL;
1611 }
1612
1613 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1614 LLVMValueRef sample_id)
1615 {
1616 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1617
1618 LLVMValueRef result;
1619 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1620
1621 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1622 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1623
1624 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
1625 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1626
1627 return result;
1628 }
1629
1630
1631 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1632 {
1633 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1634 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
1635 ctx->options->key.fs.log2_num_samples :
1636 ctx->options->key.fs.log2_ps_iter_samples;
1637
1638 /* The bit pattern matches that used by fixed function fragment
1639 * processing. */
1640 static const uint16_t ps_iter_masks[] = {
1641 0xffff, /* not used */
1642 0x5555,
1643 0x1111,
1644 0x0101,
1645 0x0001,
1646 };
1647 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1648
1649 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1650
1651 LLVMValueRef result, sample_id;
1652 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1653 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1654 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1655 return result;
1656 }
1657
1658
1659 static void
1660 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1661 {
1662 LLVMValueRef gs_next_vertex;
1663 LLVMValueRef can_emit;
1664 int idx;
1665 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1666
1667 assert(stream == 0);
1668
1669 /* Write vertex attribute values to GSVS ring */
1670 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1671 ctx->gs_next_vertex,
1672 "");
1673
1674 /* If this thread has already emitted the declared maximum number of
1675 * vertices, kill it: excessive vertex emissions are not supposed to
1676 * have any effect, and GS threads have no externally observable
1677 * effects other than emitting vertices.
1678 */
1679 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1680 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1681 ac_build_kill_if_false(&ctx->ac, can_emit);
1682
1683 /* loop num outputs */
1684 idx = 0;
1685 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1686 unsigned output_usage_mask =
1687 ctx->shader_info->info.gs.output_usage_mask[i];
1688 LLVMValueRef *out_ptr = &addrs[i * 4];
1689 int length = 4;
1690 int slot = idx;
1691 int slot_inc = 1;
1692
1693 if (!(ctx->output_mask & (1ull << i)))
1694 continue;
1695
1696 if (i == VARYING_SLOT_CLIP_DIST0) {
1697 /* pack clip and cull into a single set of slots */
1698 length = ctx->num_output_clips + ctx->num_output_culls;
1699 if (length > 4)
1700 slot_inc = 2;
1701 output_usage_mask = (1 << length) - 1;
1702 }
1703
1704 for (unsigned j = 0; j < length; j++) {
1705 if (!(output_usage_mask & (1 << j)))
1706 continue;
1707
1708 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1709 out_ptr[j], "");
1710 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1711 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1712 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1713
1714 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1715
1716 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1717 out_val, 1,
1718 voffset, ctx->gs2vs_offset, 0,
1719 1, 1, true, true);
1720 }
1721 idx += slot_inc;
1722 }
1723
1724 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1725 ctx->ac.i32_1, "");
1726 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1727
1728 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1729 }
1730
1731 static void
1732 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1733 {
1734 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1735 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1736 }
1737
1738 static LLVMValueRef
1739 load_tess_coord(struct ac_shader_abi *abi)
1740 {
1741 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1742
1743 LLVMValueRef coord[4] = {
1744 ctx->tes_u,
1745 ctx->tes_v,
1746 ctx->ac.f32_0,
1747 ctx->ac.f32_0,
1748 };
1749
1750 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1751 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1752 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1753
1754 return ac_build_gather_values(&ctx->ac, coord, 3);
1755 }
1756
1757 static LLVMValueRef
1758 load_patch_vertices_in(struct ac_shader_abi *abi)
1759 {
1760 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1761 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1762 }
1763
1764
1765 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1766 {
1767 return abi->base_vertex;
1768 }
1769
1770 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1771 LLVMValueRef buffer_ptr, bool write)
1772 {
1773 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1774 LLVMValueRef result;
1775
1776 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1777
1778 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1779 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1780
1781 return result;
1782 }
1783
1784 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1785 {
1786 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1787 LLVMValueRef result;
1788
1789 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1790
1791 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1792 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1793
1794 return result;
1795 }
1796
1797 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1798 unsigned descriptor_set,
1799 unsigned base_index,
1800 unsigned constant_index,
1801 LLVMValueRef index,
1802 enum ac_descriptor_type desc_type,
1803 bool image, bool write,
1804 bool bindless)
1805 {
1806 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1807 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1808 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1809 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1810 unsigned offset = binding->offset;
1811 unsigned stride = binding->size;
1812 unsigned type_size;
1813 LLVMBuilderRef builder = ctx->ac.builder;
1814 LLVMTypeRef type;
1815
1816 assert(base_index < layout->binding_count);
1817
1818 switch (desc_type) {
1819 case AC_DESC_IMAGE:
1820 type = ctx->ac.v8i32;
1821 type_size = 32;
1822 break;
1823 case AC_DESC_FMASK:
1824 type = ctx->ac.v8i32;
1825 offset += 32;
1826 type_size = 32;
1827 break;
1828 case AC_DESC_SAMPLER:
1829 type = ctx->ac.v4i32;
1830 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1831 offset += 64;
1832
1833 type_size = 16;
1834 break;
1835 case AC_DESC_BUFFER:
1836 type = ctx->ac.v4i32;
1837 type_size = 16;
1838 break;
1839 default:
1840 unreachable("invalid desc_type\n");
1841 }
1842
1843 offset += constant_index * stride;
1844
1845 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1846 (!index || binding->immutable_samplers_equal)) {
1847 if (binding->immutable_samplers_equal)
1848 constant_index = 0;
1849
1850 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1851
1852 LLVMValueRef constants[] = {
1853 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1854 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1855 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1856 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1857 };
1858 return ac_build_gather_values(&ctx->ac, constants, 4);
1859 }
1860
1861 assert(stride % type_size == 0);
1862
1863 if (!index)
1864 index = ctx->ac.i32_0;
1865
1866 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1867
1868 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1869 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
1870
1871 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1872 }
1873
1874 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1875 * so we may need to fix it up. */
1876 static LLVMValueRef
1877 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1878 unsigned adjustment,
1879 LLVMValueRef alpha)
1880 {
1881 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1882 return alpha;
1883
1884 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1885
1886 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1887 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1888 else
1889 alpha = ac_to_integer(&ctx->ac, alpha);
1890
1891 /* For the integer-like cases, do a natural sign extension.
1892 *
1893 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1894 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1895 * exponent.
1896 */
1897 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1898 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1899 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1900 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1901
1902 /* Convert back to the right type. */
1903 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1904 LLVMValueRef clamp;
1905 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1906 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1907 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1908 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1909 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1910 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1911 }
1912
1913 return alpha;
1914 }
1915
1916 static void
1917 handle_vs_input_decl(struct radv_shader_context *ctx,
1918 struct nir_variable *variable)
1919 {
1920 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1921 LLVMValueRef t_offset;
1922 LLVMValueRef t_list;
1923 LLVMValueRef input;
1924 LLVMValueRef buffer_index;
1925 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1926 uint8_t input_usage_mask =
1927 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1928 unsigned num_channels = util_last_bit(input_usage_mask);
1929
1930 variable->data.driver_location = variable->data.location * 4;
1931
1932 for (unsigned i = 0; i < attrib_count; ++i) {
1933 LLVMValueRef output[4];
1934 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1935
1936 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1937 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
1938
1939 if (divisor) {
1940 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
1941 ctx->abi.start_instance, "");
1942
1943 if (divisor != 1) {
1944 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1945 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1946 }
1947
1948 if (ctx->options->key.vs.as_ls) {
1949 ctx->shader_info->vs.vgpr_comp_cnt =
1950 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1951 } else {
1952 ctx->shader_info->vs.vgpr_comp_cnt =
1953 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1954 }
1955 } else {
1956 buffer_index = ctx->ac.i32_0;
1957 }
1958 } else
1959 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
1960 ctx->abi.base_vertex, "");
1961 t_offset = LLVMConstInt(ctx->ac.i32, attrib_index, false);
1962
1963 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1964
1965 input = ac_build_buffer_load_format(&ctx->ac, t_list,
1966 buffer_index,
1967 ctx->ac.i32_0,
1968 num_channels, false, true);
1969
1970 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
1971
1972 for (unsigned chan = 0; chan < 4; chan++) {
1973 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1974 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1975 }
1976
1977 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
1978 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
1979
1980 for (unsigned chan = 0; chan < 4; chan++) {
1981 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] =
1982 ac_to_integer(&ctx->ac, output[chan]);
1983 }
1984 }
1985 }
1986
1987 static void interp_fs_input(struct radv_shader_context *ctx,
1988 unsigned attr,
1989 LLVMValueRef interp_param,
1990 LLVMValueRef prim_mask,
1991 LLVMValueRef result[4])
1992 {
1993 LLVMValueRef attr_number;
1994 unsigned chan;
1995 LLVMValueRef i, j;
1996 bool interp = interp_param != NULL;
1997
1998 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
1999
2000 /* fs.constant returns the param from the middle vertex, so it's not
2001 * really useful for flat shading. It's meant to be used for custom
2002 * interpolation (but the intrinsic can't fetch from the other two
2003 * vertices).
2004 *
2005 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2006 * to do the right thing. The only reason we use fs.constant is that
2007 * fs.interp cannot be used on integers, because they can be equal
2008 * to NaN.
2009 */
2010 if (interp) {
2011 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
2012 ctx->ac.v2f32, "");
2013
2014 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2015 ctx->ac.i32_0, "");
2016 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2017 ctx->ac.i32_1, "");
2018 }
2019
2020 for (chan = 0; chan < 4; chan++) {
2021 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2022
2023 if (interp) {
2024 result[chan] = ac_build_fs_interp(&ctx->ac,
2025 llvm_chan,
2026 attr_number,
2027 prim_mask, i, j);
2028 } else {
2029 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2030 LLVMConstInt(ctx->ac.i32, 2, false),
2031 llvm_chan,
2032 attr_number,
2033 prim_mask);
2034 }
2035 }
2036 }
2037
2038 static void
2039 handle_fs_input_decl(struct radv_shader_context *ctx,
2040 struct nir_variable *variable)
2041 {
2042 int idx = variable->data.location;
2043 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2044 LLVMValueRef interp;
2045
2046 variable->data.driver_location = idx * 4;
2047 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
2048
2049 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
2050 unsigned interp_type;
2051 if (variable->data.sample)
2052 interp_type = INTERP_SAMPLE;
2053 else if (variable->data.centroid)
2054 interp_type = INTERP_CENTROID;
2055 else
2056 interp_type = INTERP_CENTER;
2057
2058 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
2059 } else
2060 interp = NULL;
2061
2062 for (unsigned i = 0; i < attrib_count; ++i)
2063 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
2064
2065 }
2066
2067 static void
2068 handle_vs_inputs(struct radv_shader_context *ctx,
2069 struct nir_shader *nir) {
2070 nir_foreach_variable(variable, &nir->inputs)
2071 handle_vs_input_decl(ctx, variable);
2072 }
2073
2074 static void
2075 prepare_interp_optimize(struct radv_shader_context *ctx,
2076 struct nir_shader *nir)
2077 {
2078 bool uses_center = false;
2079 bool uses_centroid = false;
2080 nir_foreach_variable(variable, &nir->inputs) {
2081 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2082 variable->data.sample)
2083 continue;
2084
2085 if (variable->data.centroid)
2086 uses_centroid = true;
2087 else
2088 uses_center = true;
2089 }
2090
2091 if (uses_center && uses_centroid) {
2092 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2093 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
2094 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
2095 }
2096 }
2097
2098 static void
2099 handle_fs_inputs(struct radv_shader_context *ctx,
2100 struct nir_shader *nir)
2101 {
2102 prepare_interp_optimize(ctx, nir);
2103
2104 nir_foreach_variable(variable, &nir->inputs)
2105 handle_fs_input_decl(ctx, variable);
2106
2107 unsigned index = 0;
2108
2109 if (ctx->shader_info->info.ps.uses_input_attachments ||
2110 ctx->shader_info->info.needs_multiview_view_index)
2111 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
2112
2113 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
2114 LLVMValueRef interp_param;
2115 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
2116
2117 if (!(ctx->input_mask & (1ull << i)))
2118 continue;
2119
2120 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
2121 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
2122 interp_param = *inputs;
2123 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
2124 inputs);
2125
2126 if (!interp_param)
2127 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
2128 ++index;
2129 } else if (i == VARYING_SLOT_POS) {
2130 for(int i = 0; i < 3; ++i)
2131 inputs[i] = ctx->abi.frag_pos[i];
2132
2133 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2134 ctx->abi.frag_pos[3]);
2135 }
2136 }
2137 ctx->shader_info->fs.num_interp = index;
2138 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
2139
2140 if (ctx->shader_info->info.needs_multiview_view_index)
2141 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2142 }
2143
2144 static void
2145 scan_shader_output_decl(struct radv_shader_context *ctx,
2146 struct nir_variable *variable,
2147 struct nir_shader *shader,
2148 gl_shader_stage stage)
2149 {
2150 int idx = variable->data.location + variable->data.index;
2151 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2152 uint64_t mask_attribs;
2153
2154 variable->data.driver_location = idx * 4;
2155
2156 /* tess ctrl has it's own load/store paths for outputs */
2157 if (stage == MESA_SHADER_TESS_CTRL)
2158 return;
2159
2160 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2161 if (stage == MESA_SHADER_VERTEX ||
2162 stage == MESA_SHADER_TESS_EVAL ||
2163 stage == MESA_SHADER_GEOMETRY) {
2164 if (idx == VARYING_SLOT_CLIP_DIST0) {
2165 int length = shader->info.clip_distance_array_size +
2166 shader->info.cull_distance_array_size;
2167 if (stage == MESA_SHADER_VERTEX) {
2168 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2169 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2170 }
2171 if (stage == MESA_SHADER_TESS_EVAL) {
2172 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2173 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2174 }
2175
2176 if (length > 4)
2177 attrib_count = 2;
2178 else
2179 attrib_count = 1;
2180 mask_attribs = 1ull << idx;
2181 }
2182 }
2183
2184 ctx->output_mask |= mask_attribs;
2185 }
2186
2187
2188 /* Initialize arguments for the shader export intrinsic */
2189 static void
2190 si_llvm_init_export_args(struct radv_shader_context *ctx,
2191 LLVMValueRef *values,
2192 unsigned enabled_channels,
2193 unsigned target,
2194 struct ac_export_args *args)
2195 {
2196 /* Specify the channels that are enabled. */
2197 args->enabled_channels = enabled_channels;
2198
2199 /* Specify whether the EXEC mask represents the valid mask */
2200 args->valid_mask = 0;
2201
2202 /* Specify whether this is the last export */
2203 args->done = 0;
2204
2205 /* Specify the target we are exporting */
2206 args->target = target;
2207
2208 args->compr = false;
2209 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2210 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2211 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2212 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2213
2214 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2215 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2216 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2217 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2218 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2219 unsigned chan;
2220
2221 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2222 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2223 unsigned bits, bool hi) = NULL;
2224
2225 switch(col_format) {
2226 case V_028714_SPI_SHADER_ZERO:
2227 args->enabled_channels = 0; /* writemask */
2228 args->target = V_008DFC_SQ_EXP_NULL;
2229 break;
2230
2231 case V_028714_SPI_SHADER_32_R:
2232 args->enabled_channels = 1;
2233 args->out[0] = values[0];
2234 break;
2235
2236 case V_028714_SPI_SHADER_32_GR:
2237 args->enabled_channels = 0x3;
2238 args->out[0] = values[0];
2239 args->out[1] = values[1];
2240 break;
2241
2242 case V_028714_SPI_SHADER_32_AR:
2243 args->enabled_channels = 0x9;
2244 args->out[0] = values[0];
2245 args->out[3] = values[3];
2246 break;
2247
2248 case V_028714_SPI_SHADER_FP16_ABGR:
2249 args->enabled_channels = 0x5;
2250 packf = ac_build_cvt_pkrtz_f16;
2251 break;
2252
2253 case V_028714_SPI_SHADER_UNORM16_ABGR:
2254 args->enabled_channels = 0x5;
2255 packf = ac_build_cvt_pknorm_u16;
2256 break;
2257
2258 case V_028714_SPI_SHADER_SNORM16_ABGR:
2259 args->enabled_channels = 0x5;
2260 packf = ac_build_cvt_pknorm_i16;
2261 break;
2262
2263 case V_028714_SPI_SHADER_UINT16_ABGR:
2264 args->enabled_channels = 0x5;
2265 packi = ac_build_cvt_pk_u16;
2266 break;
2267
2268 case V_028714_SPI_SHADER_SINT16_ABGR:
2269 args->enabled_channels = 0x5;
2270 packi = ac_build_cvt_pk_i16;
2271 break;
2272
2273 default:
2274 case V_028714_SPI_SHADER_32_ABGR:
2275 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2276 break;
2277 }
2278
2279 /* Pack f16 or norm_i16/u16. */
2280 if (packf) {
2281 for (chan = 0; chan < 2; chan++) {
2282 LLVMValueRef pack_args[2] = {
2283 values[2 * chan],
2284 values[2 * chan + 1]
2285 };
2286 LLVMValueRef packed;
2287
2288 packed = packf(&ctx->ac, pack_args);
2289 args->out[chan] = ac_to_float(&ctx->ac, packed);
2290 }
2291 args->compr = 1; /* COMPR flag */
2292 }
2293
2294 /* Pack i16/u16. */
2295 if (packi) {
2296 for (chan = 0; chan < 2; chan++) {
2297 LLVMValueRef pack_args[2] = {
2298 ac_to_integer(&ctx->ac, values[2 * chan]),
2299 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2300 };
2301 LLVMValueRef packed;
2302
2303 packed = packi(&ctx->ac, pack_args,
2304 is_int8 ? 8 : is_int10 ? 10 : 16,
2305 chan == 1);
2306 args->out[chan] = ac_to_float(&ctx->ac, packed);
2307 }
2308 args->compr = 1; /* COMPR flag */
2309 }
2310 return;
2311 }
2312
2313 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2314
2315 for (unsigned i = 0; i < 4; ++i) {
2316 if (!(args->enabled_channels & (1 << i)))
2317 continue;
2318
2319 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2320 }
2321 }
2322
2323 static void
2324 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2325 LLVMValueRef *values, unsigned enabled_channels)
2326 {
2327 struct ac_export_args args;
2328
2329 si_llvm_init_export_args(ctx, values, enabled_channels,
2330 V_008DFC_SQ_EXP_PARAM + index, &args);
2331 ac_build_export(&ctx->ac, &args);
2332 }
2333
2334 static LLVMValueRef
2335 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2336 {
2337 LLVMValueRef output =
2338 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2339
2340 return LLVMBuildLoad(ctx->ac.builder, output, "");
2341 }
2342
2343 static void
2344 handle_vs_outputs_post(struct radv_shader_context *ctx,
2345 bool export_prim_id, bool export_layer_id,
2346 struct radv_vs_output_info *outinfo)
2347 {
2348 uint32_t param_count = 0;
2349 unsigned target;
2350 unsigned pos_idx, num_pos_exports = 0;
2351 struct ac_export_args args, pos_args[4] = {};
2352 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2353 int i;
2354
2355 if (ctx->options->key.has_multiview_view_index) {
2356 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2357 if(!*tmp_out) {
2358 for(unsigned i = 0; i < 4; ++i)
2359 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2360 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2361 }
2362
2363 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2364 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2365 }
2366
2367 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2368 sizeof(outinfo->vs_output_param_offset));
2369
2370 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2371 LLVMValueRef slots[8];
2372 unsigned j;
2373
2374 if (outinfo->cull_dist_mask)
2375 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2376
2377 i = VARYING_SLOT_CLIP_DIST0;
2378 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
2379 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2380
2381 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
2382 slots[i] = LLVMGetUndef(ctx->ac.f32);
2383
2384 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
2385 target = V_008DFC_SQ_EXP_POS + 3;
2386 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2387 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2388 &args, sizeof(args));
2389 }
2390
2391 target = V_008DFC_SQ_EXP_POS + 2;
2392 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2393 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2394 &args, sizeof(args));
2395
2396 }
2397
2398 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2399 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2400 for (unsigned j = 0; j < 4; j++)
2401 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2402 }
2403 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2404
2405 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2406 outinfo->writes_pointsize = true;
2407 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2408 }
2409
2410 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2411 outinfo->writes_layer = true;
2412 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2413 }
2414
2415 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2416 outinfo->writes_viewport_index = true;
2417 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2418 }
2419
2420 if (outinfo->writes_pointsize ||
2421 outinfo->writes_layer ||
2422 outinfo->writes_viewport_index) {
2423 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2424 (outinfo->writes_layer == true ? 4 : 0));
2425 pos_args[1].valid_mask = 0;
2426 pos_args[1].done = 0;
2427 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2428 pos_args[1].compr = 0;
2429 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2430 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2431 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2432 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2433
2434 if (outinfo->writes_pointsize == true)
2435 pos_args[1].out[0] = psize_value;
2436 if (outinfo->writes_layer == true)
2437 pos_args[1].out[2] = layer_value;
2438 if (outinfo->writes_viewport_index == true) {
2439 if (ctx->options->chip_class >= GFX9) {
2440 /* GFX9 has the layer in out.z[10:0] and the viewport
2441 * index in out.z[19:16].
2442 */
2443 LLVMValueRef v = viewport_index_value;
2444 v = ac_to_integer(&ctx->ac, v);
2445 v = LLVMBuildShl(ctx->ac.builder, v,
2446 LLVMConstInt(ctx->ac.i32, 16, false),
2447 "");
2448 v = LLVMBuildOr(ctx->ac.builder, v,
2449 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2450
2451 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2452 pos_args[1].enabled_channels |= 1 << 2;
2453 } else {
2454 pos_args[1].out[3] = viewport_index_value;
2455 pos_args[1].enabled_channels |= 1 << 3;
2456 }
2457 }
2458 }
2459 for (i = 0; i < 4; i++) {
2460 if (pos_args[i].out[0])
2461 num_pos_exports++;
2462 }
2463
2464 pos_idx = 0;
2465 for (i = 0; i < 4; i++) {
2466 if (!pos_args[i].out[0])
2467 continue;
2468
2469 /* Specify the target we are exporting */
2470 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2471 if (pos_idx == num_pos_exports)
2472 pos_args[i].done = 1;
2473 ac_build_export(&ctx->ac, &pos_args[i]);
2474 }
2475
2476 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2477 LLVMValueRef values[4];
2478 if (!(ctx->output_mask & (1ull << i)))
2479 continue;
2480
2481 if (i != VARYING_SLOT_LAYER &&
2482 i != VARYING_SLOT_PRIMITIVE_ID &&
2483 i < VARYING_SLOT_VAR0)
2484 continue;
2485
2486 for (unsigned j = 0; j < 4; j++)
2487 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2488
2489 unsigned output_usage_mask;
2490
2491 if (ctx->stage == MESA_SHADER_VERTEX &&
2492 !ctx->is_gs_copy_shader) {
2493 output_usage_mask =
2494 ctx->shader_info->info.vs.output_usage_mask[i];
2495 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2496 output_usage_mask =
2497 ctx->shader_info->info.tes.output_usage_mask[i];
2498 } else {
2499 assert(ctx->is_gs_copy_shader);
2500 output_usage_mask =
2501 ctx->shader_info->info.gs.output_usage_mask[i];
2502 }
2503
2504 radv_export_param(ctx, param_count, values, output_usage_mask);
2505
2506 outinfo->vs_output_param_offset[i] = param_count++;
2507 }
2508
2509 if (export_prim_id) {
2510 LLVMValueRef values[4];
2511
2512 values[0] = ctx->vs_prim_id;
2513 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2514 ctx->shader_info->vs.vgpr_comp_cnt);
2515 for (unsigned j = 1; j < 4; j++)
2516 values[j] = ctx->ac.f32_0;
2517
2518 radv_export_param(ctx, param_count, values, 0x1);
2519
2520 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2521 outinfo->export_prim_id = true;
2522 }
2523
2524 if (export_layer_id && layer_value) {
2525 LLVMValueRef values[4];
2526
2527 values[0] = layer_value;
2528 for (unsigned j = 1; j < 4; j++)
2529 values[j] = ctx->ac.f32_0;
2530
2531 radv_export_param(ctx, param_count, values, 0x1);
2532
2533 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2534 }
2535
2536 outinfo->pos_exports = num_pos_exports;
2537 outinfo->param_exports = param_count;
2538 }
2539
2540 static void
2541 handle_es_outputs_post(struct radv_shader_context *ctx,
2542 struct radv_es_output_info *outinfo)
2543 {
2544 int j;
2545 uint64_t max_output_written = 0;
2546 LLVMValueRef lds_base = NULL;
2547
2548 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2549 int param_index;
2550 int length = 4;
2551
2552 if (!(ctx->output_mask & (1ull << i)))
2553 continue;
2554
2555 if (i == VARYING_SLOT_CLIP_DIST0)
2556 length = ctx->num_output_clips + ctx->num_output_culls;
2557
2558 param_index = shader_io_get_unique_index(i);
2559
2560 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2561 }
2562
2563 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2564
2565 if (ctx->ac.chip_class >= GFX9) {
2566 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2567 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2568 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2569 LLVMConstInt(ctx->ac.i32, 24, false),
2570 LLVMConstInt(ctx->ac.i32, 4, false), false);
2571 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2572 LLVMBuildMul(ctx->ac.builder, wave_idx,
2573 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2574 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2575 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2576 }
2577
2578 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2579 LLVMValueRef dw_addr = NULL;
2580 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2581 unsigned output_usage_mask;
2582 int param_index;
2583 int length = 4;
2584
2585 if (!(ctx->output_mask & (1ull << i)))
2586 continue;
2587
2588 if (ctx->stage == MESA_SHADER_VERTEX) {
2589 output_usage_mask =
2590 ctx->shader_info->info.vs.output_usage_mask[i];
2591 } else {
2592 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2593 output_usage_mask =
2594 ctx->shader_info->info.tes.output_usage_mask[i];
2595 }
2596
2597 if (i == VARYING_SLOT_CLIP_DIST0) {
2598 length = ctx->num_output_clips + ctx->num_output_culls;
2599 output_usage_mask = (1 << length) - 1;
2600 }
2601
2602 param_index = shader_io_get_unique_index(i);
2603
2604 if (lds_base) {
2605 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2606 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2607 "");
2608 }
2609
2610 for (j = 0; j < length; j++) {
2611 if (!(output_usage_mask & (1 << j)))
2612 continue;
2613
2614 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2615 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2616
2617 if (ctx->ac.chip_class >= GFX9) {
2618 LLVMValueRef dw_addr_offset =
2619 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2620 LLVMConstInt(ctx->ac.i32,
2621 j, false), "");
2622
2623 ac_lds_store(&ctx->ac, dw_addr_offset,
2624 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2625 } else {
2626 ac_build_buffer_store_dword(&ctx->ac,
2627 ctx->esgs_ring,
2628 out_val, 1,
2629 NULL, ctx->es2gs_offset,
2630 (4 * param_index + j) * 4,
2631 1, 1, true, true);
2632 }
2633 }
2634 }
2635 }
2636
2637 static void
2638 handle_ls_outputs_post(struct radv_shader_context *ctx)
2639 {
2640 LLVMValueRef vertex_id = ctx->rel_auto_id;
2641 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2642 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2643 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2644 vertex_dw_stride, "");
2645
2646 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2647 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2648 int length = 4;
2649
2650 if (!(ctx->output_mask & (1ull << i)))
2651 continue;
2652
2653 if (i == VARYING_SLOT_CLIP_DIST0)
2654 length = ctx->num_output_clips + ctx->num_output_culls;
2655 int param = shader_io_get_unique_index(i);
2656 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2657 LLVMConstInt(ctx->ac.i32, param * 4, false),
2658 "");
2659 for (unsigned j = 0; j < length; j++) {
2660 ac_lds_store(&ctx->ac, dw_addr,
2661 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2662 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2663 }
2664 }
2665 }
2666
2667 static void
2668 write_tess_factors(struct radv_shader_context *ctx)
2669 {
2670 unsigned stride, outer_comps, inner_comps;
2671 struct ac_build_if_state if_ctx, inner_if_ctx;
2672 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2673 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2674 unsigned tess_inner_index = 0, tess_outer_index;
2675 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2676 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2677 int i;
2678 ac_emit_barrier(&ctx->ac, ctx->stage);
2679
2680 switch (ctx->options->key.tcs.primitive_mode) {
2681 case GL_ISOLINES:
2682 stride = 2;
2683 outer_comps = 2;
2684 inner_comps = 0;
2685 break;
2686 case GL_TRIANGLES:
2687 stride = 4;
2688 outer_comps = 3;
2689 inner_comps = 1;
2690 break;
2691 case GL_QUADS:
2692 stride = 6;
2693 outer_comps = 4;
2694 inner_comps = 2;
2695 break;
2696 default:
2697 return;
2698 }
2699
2700 ac_nir_build_if(&if_ctx, ctx,
2701 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2702 invocation_id, ctx->ac.i32_0, ""));
2703
2704 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2705
2706 if (inner_comps) {
2707 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2708 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2709 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2710 }
2711
2712 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2713 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2714 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2715
2716 for (i = 0; i < 4; i++) {
2717 inner[i] = LLVMGetUndef(ctx->ac.i32);
2718 outer[i] = LLVMGetUndef(ctx->ac.i32);
2719 }
2720
2721 // LINES reversal
2722 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2723 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2724 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2725 ctx->ac.i32_1, "");
2726 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2727 } else {
2728 for (i = 0; i < outer_comps; i++) {
2729 outer[i] = out[i] =
2730 ac_lds_load(&ctx->ac, lds_outer);
2731 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2732 ctx->ac.i32_1, "");
2733 }
2734 for (i = 0; i < inner_comps; i++) {
2735 inner[i] = out[outer_comps+i] =
2736 ac_lds_load(&ctx->ac, lds_inner);
2737 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2738 ctx->ac.i32_1, "");
2739 }
2740 }
2741
2742 /* Convert the outputs to vectors for stores. */
2743 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2744 vec1 = NULL;
2745
2746 if (stride > 4)
2747 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2748
2749
2750 buffer = ctx->hs_ring_tess_factor;
2751 tf_base = ctx->tess_factor_offset;
2752 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2753 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2754 unsigned tf_offset = 0;
2755
2756 if (ctx->options->chip_class <= VI) {
2757 ac_nir_build_if(&inner_if_ctx, ctx,
2758 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2759 rel_patch_id, ctx->ac.i32_0, ""));
2760
2761 /* Store the dynamic HS control word. */
2762 ac_build_buffer_store_dword(&ctx->ac, buffer,
2763 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2764 1, ctx->ac.i32_0, tf_base,
2765 0, 1, 0, true, false);
2766 tf_offset += 4;
2767
2768 ac_nir_build_endif(&inner_if_ctx);
2769 }
2770
2771 /* Store the tessellation factors. */
2772 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2773 MIN2(stride, 4), byteoffset, tf_base,
2774 tf_offset, 1, 0, true, false);
2775 if (vec1)
2776 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2777 stride - 4, byteoffset, tf_base,
2778 16 + tf_offset, 1, 0, true, false);
2779
2780 //store to offchip for TES to read - only if TES reads them
2781 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2782 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2783 LLVMValueRef tf_inner_offset;
2784 unsigned param_outer, param_inner;
2785
2786 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2787 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2788 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2789
2790 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2791 util_next_power_of_two(outer_comps));
2792
2793 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2794 outer_comps, tf_outer_offset,
2795 ctx->oc_lds, 0, 1, 0, true, false);
2796 if (inner_comps) {
2797 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2798 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2799 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2800
2801 inner_vec = inner_comps == 1 ? inner[0] :
2802 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2803 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2804 inner_comps, tf_inner_offset,
2805 ctx->oc_lds, 0, 1, 0, true, false);
2806 }
2807 }
2808 ac_nir_build_endif(&if_ctx);
2809 }
2810
2811 static void
2812 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2813 {
2814 write_tess_factors(ctx);
2815 }
2816
2817 static bool
2818 si_export_mrt_color(struct radv_shader_context *ctx,
2819 LLVMValueRef *color, unsigned index,
2820 struct ac_export_args *args)
2821 {
2822 /* Export */
2823 si_llvm_init_export_args(ctx, color, 0xf,
2824 V_008DFC_SQ_EXP_MRT + index, args);
2825 if (!args->enabled_channels)
2826 return false; /* unnecessary NULL export */
2827
2828 return true;
2829 }
2830
2831 static void
2832 radv_export_mrt_z(struct radv_shader_context *ctx,
2833 LLVMValueRef depth, LLVMValueRef stencil,
2834 LLVMValueRef samplemask)
2835 {
2836 struct ac_export_args args;
2837
2838 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2839
2840 ac_build_export(&ctx->ac, &args);
2841 }
2842
2843 static void
2844 handle_fs_outputs_post(struct radv_shader_context *ctx)
2845 {
2846 unsigned index = 0;
2847 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2848 struct ac_export_args color_args[8];
2849
2850 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2851 LLVMValueRef values[4];
2852
2853 if (!(ctx->output_mask & (1ull << i)))
2854 continue;
2855
2856 if (i < FRAG_RESULT_DATA0)
2857 continue;
2858
2859 for (unsigned j = 0; j < 4; j++)
2860 values[j] = ac_to_float(&ctx->ac,
2861 radv_load_output(ctx, i, j));
2862
2863 bool ret = si_export_mrt_color(ctx, values,
2864 i - FRAG_RESULT_DATA0,
2865 &color_args[index]);
2866 if (ret)
2867 index++;
2868 }
2869
2870 /* Process depth, stencil, samplemask. */
2871 if (ctx->shader_info->info.ps.writes_z) {
2872 depth = ac_to_float(&ctx->ac,
2873 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
2874 }
2875 if (ctx->shader_info->info.ps.writes_stencil) {
2876 stencil = ac_to_float(&ctx->ac,
2877 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
2878 }
2879 if (ctx->shader_info->info.ps.writes_sample_mask) {
2880 samplemask = ac_to_float(&ctx->ac,
2881 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
2882 }
2883
2884 /* Set the DONE bit on last non-null color export only if Z isn't
2885 * exported.
2886 */
2887 if (index > 0 &&
2888 !ctx->shader_info->info.ps.writes_z &&
2889 !ctx->shader_info->info.ps.writes_stencil &&
2890 !ctx->shader_info->info.ps.writes_sample_mask) {
2891 unsigned last = index - 1;
2892
2893 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
2894 color_args[last].done = 1; /* DONE bit */
2895 }
2896
2897 /* Export PS outputs. */
2898 for (unsigned i = 0; i < index; i++)
2899 ac_build_export(&ctx->ac, &color_args[i]);
2900
2901 if (depth || stencil || samplemask)
2902 radv_export_mrt_z(ctx, depth, stencil, samplemask);
2903 else if (!index)
2904 ac_build_export_null(&ctx->ac);
2905 }
2906
2907 static void
2908 emit_gs_epilogue(struct radv_shader_context *ctx)
2909 {
2910 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
2911 }
2912
2913 static void
2914 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
2915 LLVMValueRef *addrs)
2916 {
2917 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2918
2919 switch (ctx->stage) {
2920 case MESA_SHADER_VERTEX:
2921 if (ctx->options->key.vs.as_ls)
2922 handle_ls_outputs_post(ctx);
2923 else if (ctx->options->key.vs.as_es)
2924 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
2925 else
2926 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
2927 ctx->options->key.vs.export_layer_id,
2928 &ctx->shader_info->vs.outinfo);
2929 break;
2930 case MESA_SHADER_FRAGMENT:
2931 handle_fs_outputs_post(ctx);
2932 break;
2933 case MESA_SHADER_GEOMETRY:
2934 emit_gs_epilogue(ctx);
2935 break;
2936 case MESA_SHADER_TESS_CTRL:
2937 handle_tcs_outputs_post(ctx);
2938 break;
2939 case MESA_SHADER_TESS_EVAL:
2940 if (ctx->options->key.tes.as_es)
2941 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
2942 else
2943 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
2944 ctx->options->key.tes.export_layer_id,
2945 &ctx->shader_info->tes.outinfo);
2946 break;
2947 default:
2948 break;
2949 }
2950 }
2951
2952 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
2953 {
2954 LLVMPassManagerRef passmgr;
2955 /* Create the pass manager */
2956 passmgr = LLVMCreateFunctionPassManagerForModule(
2957 ctx->ac.module);
2958
2959 /* This pass should eliminate all the load and store instructions */
2960 LLVMAddPromoteMemoryToRegisterPass(passmgr);
2961
2962 /* Add some optimization passes */
2963 LLVMAddScalarReplAggregatesPass(passmgr);
2964 LLVMAddLICMPass(passmgr);
2965 LLVMAddAggressiveDCEPass(passmgr);
2966 LLVMAddCFGSimplificationPass(passmgr);
2967 LLVMAddInstructionCombiningPass(passmgr);
2968
2969 /* Run the pass */
2970 LLVMInitializeFunctionPassManager(passmgr);
2971 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
2972 LLVMFinalizeFunctionPassManager(passmgr);
2973
2974 LLVMDisposeBuilder(ctx->ac.builder);
2975 LLVMDisposePassManager(passmgr);
2976
2977 ac_llvm_context_dispose(&ctx->ac);
2978 }
2979
2980 static void
2981 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
2982 {
2983 struct radv_vs_output_info *outinfo;
2984
2985 switch (ctx->stage) {
2986 case MESA_SHADER_FRAGMENT:
2987 case MESA_SHADER_COMPUTE:
2988 case MESA_SHADER_TESS_CTRL:
2989 case MESA_SHADER_GEOMETRY:
2990 return;
2991 case MESA_SHADER_VERTEX:
2992 if (ctx->options->key.vs.as_ls ||
2993 ctx->options->key.vs.as_es)
2994 return;
2995 outinfo = &ctx->shader_info->vs.outinfo;
2996 break;
2997 case MESA_SHADER_TESS_EVAL:
2998 if (ctx->options->key.vs.as_es)
2999 return;
3000 outinfo = &ctx->shader_info->tes.outinfo;
3001 break;
3002 default:
3003 unreachable("Unhandled shader type");
3004 }
3005
3006 ac_optimize_vs_outputs(&ctx->ac,
3007 ctx->main_function,
3008 outinfo->vs_output_param_offset,
3009 VARYING_SLOT_MAX,
3010 &outinfo->param_exports);
3011 }
3012
3013 static void
3014 ac_setup_rings(struct radv_shader_context *ctx)
3015 {
3016 if (ctx->options->chip_class <= VI &&
3017 (ctx->stage == MESA_SHADER_GEOMETRY ||
3018 ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
3019 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3020 : RING_ESGS_VS;
3021 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3022
3023 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3024 ctx->ring_offsets,
3025 offset);
3026 }
3027
3028 if (ctx->is_gs_copy_shader) {
3029 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
3030 }
3031 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3032 LLVMValueRef tmp;
3033 uint32_t num_entries = 64;
3034 LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size, false);
3035 LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size << 16, false);
3036 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
3037
3038 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
3039
3040 tmp = LLVMConstInt(ctx->ac.i32, num_entries, false);
3041 if (ctx->options->chip_class >= VI)
3042 tmp = LLVMBuildMul(ctx->ac.builder, gsvs_ring_stride, tmp, "");
3043 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
3044 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
3045 tmp = LLVMBuildOr(ctx->ac.builder, tmp, gsvs_ring_desc, "");
3046 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
3047 }
3048
3049 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3050 ctx->stage == MESA_SHADER_TESS_EVAL) {
3051 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3052 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3053 }
3054 }
3055
3056 static unsigned
3057 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
3058 const struct nir_shader *nir)
3059 {
3060 switch (nir->info.stage) {
3061 case MESA_SHADER_TESS_CTRL:
3062 return chip_class >= CIK ? 128 : 64;
3063 case MESA_SHADER_GEOMETRY:
3064 return chip_class >= GFX9 ? 128 : 64;
3065 case MESA_SHADER_COMPUTE:
3066 break;
3067 default:
3068 return 0;
3069 }
3070
3071 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
3072 nir->info.cs.local_size[1] *
3073 nir->info.cs.local_size[2];
3074 return max_workgroup_size;
3075 }
3076
3077 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3078 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3079 {
3080 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3081 LLVMConstInt(ctx->ac.i32, 8, false),
3082 LLVMConstInt(ctx->ac.i32, 8, false), false);
3083 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3084 ctx->ac.i32_0, "");
3085 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
3086 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
3087 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
3088 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3089 }
3090
3091 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3092 {
3093 for(int i = 5; i >= 0; --i) {
3094 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3095 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
3096 LLVMConstInt(ctx->ac.i32, 16, false), false);
3097 }
3098
3099 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3100 LLVMConstInt(ctx->ac.i32, 16, false),
3101 LLVMConstInt(ctx->ac.i32, 8, false), false);
3102 }
3103
3104
3105 static
3106 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
3107 struct nir_shader *const *shaders,
3108 int shader_count,
3109 struct radv_shader_variant_info *shader_info,
3110 const struct radv_nir_compiler_options *options)
3111 {
3112 struct radv_shader_context ctx = {0};
3113 unsigned i;
3114 ctx.options = options;
3115 ctx.shader_info = shader_info;
3116 ctx.context = LLVMContextCreate();
3117
3118 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3119 options->family);
3120 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3121 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
3122
3123 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
3124 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
3125 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
3126 LLVMDisposeTargetData(data_layout);
3127 LLVMDisposeMessage(data_layout_str);
3128
3129 enum ac_float_mode float_mode =
3130 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3131 AC_FLOAT_MODE_DEFAULT;
3132
3133 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3134
3135 memset(shader_info, 0, sizeof(*shader_info));
3136
3137 for(int i = 0; i < shader_count; ++i)
3138 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3139
3140 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3141 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3142 for (i = 0; i < AC_UD_MAX_UD; i++)
3143 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3144
3145 ctx.max_workgroup_size = 0;
3146 for (int i = 0; i < shader_count; ++i) {
3147 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3148 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3149 shaders[i]));
3150 }
3151
3152 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3153 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3154
3155 ctx.abi.inputs = &ctx.inputs[0];
3156 ctx.abi.emit_outputs = handle_shader_outputs_post;
3157 ctx.abi.emit_vertex = visit_emit_vertex;
3158 ctx.abi.load_ubo = radv_load_ubo;
3159 ctx.abi.load_ssbo = radv_load_ssbo;
3160 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3161 ctx.abi.load_resource = radv_load_resource;
3162 ctx.abi.clamp_shadow_reference = false;
3163 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9;
3164
3165 if (shader_count >= 2)
3166 ac_init_exec_full_mask(&ctx.ac);
3167
3168 if (ctx.ac.chip_class == GFX9 &&
3169 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3170 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3171
3172 for(int i = 0; i < shader_count; ++i) {
3173 ctx.stage = shaders[i]->info.stage;
3174 ctx.output_mask = 0;
3175 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3176 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3177
3178 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3179 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3180 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3181 ctx.abi.load_inputs = load_gs_input;
3182 ctx.abi.emit_primitive = visit_end_primitive;
3183 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3184 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3185 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3186 ctx.abi.load_tess_varyings = load_tcs_varyings;
3187 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3188 ctx.abi.store_tcs_outputs = store_tcs_output;
3189 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3190 if (shader_count == 1)
3191 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3192 else
3193 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3194 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3195 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3196 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3197 ctx.abi.load_tess_varyings = load_tes_input;
3198 ctx.abi.load_tess_coord = load_tess_coord;
3199 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3200 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3201 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3202 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3203 if (shader_info->info.vs.needs_instance_id) {
3204 if (ctx.options->key.vs.as_ls) {
3205 ctx.shader_info->vs.vgpr_comp_cnt =
3206 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3207 } else {
3208 ctx.shader_info->vs.vgpr_comp_cnt =
3209 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3210 }
3211 }
3212 ctx.abi.load_base_vertex = radv_load_base_vertex;
3213 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3214 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3215 ctx.abi.lookup_interp_param = lookup_interp_param;
3216 ctx.abi.load_sample_position = load_sample_position;
3217 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3218 ctx.abi.emit_kill = radv_emit_kill;
3219 }
3220
3221 if (i)
3222 ac_emit_barrier(&ctx.ac, ctx.stage);
3223
3224 nir_foreach_variable(variable, &shaders[i]->outputs)
3225 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3226
3227 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3228 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3229 shaders[i]->info.cull_distance_array_size > 4;
3230 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3231 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3232 shaders[i]->info.gs.vertices_out;
3233 }
3234
3235 ac_setup_rings(&ctx);
3236
3237 LLVMBasicBlockRef merge_block;
3238 if (shader_count >= 2) {
3239 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3240 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3241 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3242
3243 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3244 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3245 LLVMConstInt(ctx.ac.i32, 8, false), false);
3246 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3247 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3248 thread_id, count, "");
3249 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3250
3251 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3252 }
3253
3254 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3255 handle_fs_inputs(&ctx, shaders[i]);
3256 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3257 handle_vs_inputs(&ctx, shaders[i]);
3258 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3259 prepare_gs_input_vgprs(&ctx);
3260
3261 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3262
3263 if (shader_count >= 2) {
3264 LLVMBuildBr(ctx.ac.builder, merge_block);
3265 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3266 }
3267
3268 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3269 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3270 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3271 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3272 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3273 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3274 }
3275 }
3276
3277 LLVMBuildRetVoid(ctx.ac.builder);
3278
3279 if (options->dump_preoptir)
3280 ac_dump_module(ctx.ac.module);
3281
3282 ac_llvm_finalize_module(&ctx);
3283
3284 if (shader_count == 1)
3285 ac_nir_eliminate_const_vs_outputs(&ctx);
3286
3287 if (options->dump_shader) {
3288 ctx.shader_info->private_mem_vgprs =
3289 ac_count_scratch_private_memory(ctx.main_function);
3290 }
3291
3292 return ctx.ac.module;
3293 }
3294
3295 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3296 {
3297 unsigned *retval = (unsigned *)context;
3298 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3299 char *description = LLVMGetDiagInfoDescription(di);
3300
3301 if (severity == LLVMDSError) {
3302 *retval = 1;
3303 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3304 description);
3305 }
3306
3307 LLVMDisposeMessage(description);
3308 }
3309
3310 static unsigned ac_llvm_compile(LLVMModuleRef M,
3311 struct ac_shader_binary *binary,
3312 LLVMTargetMachineRef tm)
3313 {
3314 unsigned retval = 0;
3315 char *err;
3316 LLVMContextRef llvm_ctx;
3317 LLVMMemoryBufferRef out_buffer;
3318 unsigned buffer_size;
3319 const char *buffer_data;
3320 LLVMBool mem_err;
3321
3322 /* Setup Diagnostic Handler*/
3323 llvm_ctx = LLVMGetModuleContext(M);
3324
3325 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3326 &retval);
3327
3328 /* Compile IR*/
3329 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
3330 &err, &out_buffer);
3331
3332 /* Process Errors/Warnings */
3333 if (mem_err) {
3334 fprintf(stderr, "%s: %s", __FUNCTION__, err);
3335 free(err);
3336 retval = 1;
3337 goto out;
3338 }
3339
3340 /* Extract Shader Code*/
3341 buffer_size = LLVMGetBufferSize(out_buffer);
3342 buffer_data = LLVMGetBufferStart(out_buffer);
3343
3344 ac_elf_read(buffer_data, buffer_size, binary);
3345
3346 /* Clean up */
3347 LLVMDisposeMemoryBuffer(out_buffer);
3348
3349 out:
3350 return retval;
3351 }
3352
3353 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
3354 LLVMModuleRef llvm_module,
3355 struct ac_shader_binary *binary,
3356 struct ac_shader_config *config,
3357 struct radv_shader_variant_info *shader_info,
3358 gl_shader_stage stage,
3359 const struct radv_nir_compiler_options *options)
3360 {
3361 if (options->dump_shader)
3362 ac_dump_module(llvm_module);
3363
3364 memset(binary, 0, sizeof(*binary));
3365
3366 if (options->record_llvm_ir) {
3367 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3368 binary->llvm_ir_string = strdup(llvm_ir);
3369 LLVMDisposeMessage(llvm_ir);
3370 }
3371
3372 int v = ac_llvm_compile(llvm_module, binary, tm);
3373 if (v) {
3374 fprintf(stderr, "compile failed\n");
3375 }
3376
3377 if (options->dump_shader)
3378 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3379
3380 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3381
3382 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3383 LLVMDisposeModule(llvm_module);
3384 LLVMContextDispose(ctx);
3385
3386 if (stage == MESA_SHADER_FRAGMENT) {
3387 shader_info->num_input_vgprs = 0;
3388 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3389 shader_info->num_input_vgprs += 2;
3390 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3391 shader_info->num_input_vgprs += 2;
3392 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3393 shader_info->num_input_vgprs += 2;
3394 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3395 shader_info->num_input_vgprs += 3;
3396 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3397 shader_info->num_input_vgprs += 2;
3398 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3399 shader_info->num_input_vgprs += 2;
3400 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3401 shader_info->num_input_vgprs += 2;
3402 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3403 shader_info->num_input_vgprs += 1;
3404 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3405 shader_info->num_input_vgprs += 1;
3406 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3407 shader_info->num_input_vgprs += 1;
3408 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3409 shader_info->num_input_vgprs += 1;
3410 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3411 shader_info->num_input_vgprs += 1;
3412 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3413 shader_info->num_input_vgprs += 1;
3414 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3415 shader_info->num_input_vgprs += 1;
3416 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3417 shader_info->num_input_vgprs += 1;
3418 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3419 shader_info->num_input_vgprs += 1;
3420 }
3421 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3422
3423 /* +3 for scratch wave offset and VCC */
3424 config->num_sgprs = MAX2(config->num_sgprs,
3425 shader_info->num_input_sgprs + 3);
3426
3427 /* Enable 64-bit and 16-bit denormals, because there is no performance
3428 * cost.
3429 *
3430 * If denormals are enabled, all floating-point output modifiers are
3431 * ignored.
3432 *
3433 * Don't enable denormals for 32-bit floats, because:
3434 * - Floating-point output modifiers would be ignored by the hw.
3435 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3436 * have to stop using those.
3437 * - SI & CI would be very slow.
3438 */
3439 config->float_mode |= V_00B028_FP_64_DENORMS;
3440 }
3441
3442 static void
3443 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3444 {
3445 switch (nir->info.stage) {
3446 case MESA_SHADER_COMPUTE:
3447 for (int i = 0; i < 3; ++i)
3448 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3449 break;
3450 case MESA_SHADER_FRAGMENT:
3451 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3452 break;
3453 case MESA_SHADER_GEOMETRY:
3454 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3455 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3456 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3457 shader_info->gs.invocations = nir->info.gs.invocations;
3458 break;
3459 case MESA_SHADER_TESS_EVAL:
3460 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3461 shader_info->tes.spacing = nir->info.tess.spacing;
3462 shader_info->tes.ccw = nir->info.tess.ccw;
3463 shader_info->tes.point_mode = nir->info.tess.point_mode;
3464 shader_info->tes.as_es = options->key.tes.as_es;
3465 break;
3466 case MESA_SHADER_TESS_CTRL:
3467 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3468 break;
3469 case MESA_SHADER_VERTEX:
3470 shader_info->vs.as_es = options->key.vs.as_es;
3471 shader_info->vs.as_ls = options->key.vs.as_ls;
3472 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3473 if (options->key.vs.as_ls)
3474 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3475 break;
3476 default:
3477 break;
3478 }
3479 }
3480
3481 void
3482 radv_compile_nir_shader(LLVMTargetMachineRef tm,
3483 struct ac_shader_binary *binary,
3484 struct ac_shader_config *config,
3485 struct radv_shader_variant_info *shader_info,
3486 struct nir_shader *const *nir,
3487 int nir_count,
3488 const struct radv_nir_compiler_options *options)
3489 {
3490
3491 LLVMModuleRef llvm_module;
3492
3493 llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
3494 options);
3495
3496 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
3497 nir[0]->info.stage, options);
3498
3499 for (int i = 0; i < nir_count; ++i)
3500 ac_fill_shader_info(shader_info, nir[i], options);
3501
3502 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3503 if (options->chip_class == GFX9) {
3504 if (nir_count == 2 &&
3505 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3506 shader_info->gs.es_type = nir[0]->info.stage;
3507 }
3508 }
3509 }
3510
3511 static void
3512 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3513 {
3514 LLVMValueRef vtx_offset =
3515 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3516 LLVMConstInt(ctx->ac.i32, 4, false), "");
3517 int idx = 0;
3518
3519 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3520 int length = 4;
3521 int slot = idx;
3522 int slot_inc = 1;
3523 if (!(ctx->output_mask & (1ull << i)))
3524 continue;
3525
3526 if (i == VARYING_SLOT_CLIP_DIST0) {
3527 /* unpack clip and cull from a single set of slots */
3528 length = ctx->num_output_clips + ctx->num_output_culls;
3529 if (length > 4)
3530 slot_inc = 2;
3531 }
3532
3533 for (unsigned j = 0; j < length; j++) {
3534 LLVMValueRef value, soffset;
3535
3536 soffset = LLVMConstInt(ctx->ac.i32,
3537 (slot * 4 + j) *
3538 ctx->gs_max_out_vertices * 16 * 4, false);
3539
3540 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3541 1, ctx->ac.i32_0,
3542 vtx_offset, soffset,
3543 0, 1, 1, true, false);
3544
3545 LLVMBuildStore(ctx->ac.builder,
3546 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3547 }
3548 idx += slot_inc;
3549 }
3550 handle_vs_outputs_post(ctx, false, false, &ctx->shader_info->vs.outinfo);
3551 }
3552
3553 void
3554 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
3555 struct nir_shader *geom_shader,
3556 struct ac_shader_binary *binary,
3557 struct ac_shader_config *config,
3558 struct radv_shader_variant_info *shader_info,
3559 const struct radv_nir_compiler_options *options)
3560 {
3561 struct radv_shader_context ctx = {0};
3562 ctx.context = LLVMContextCreate();
3563 ctx.options = options;
3564 ctx.shader_info = shader_info;
3565
3566 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3567 options->family);
3568 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3569
3570 ctx.is_gs_copy_shader = true;
3571 LLVMSetTarget(ctx.ac.module, "amdgcn--");
3572
3573 enum ac_float_mode float_mode =
3574 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3575 AC_FLOAT_MODE_DEFAULT;
3576
3577 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3578 ctx.stage = MESA_SHADER_VERTEX;
3579
3580 radv_nir_shader_info_pass(geom_shader, options, &shader_info->info);
3581
3582 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3583
3584 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3585 ac_setup_rings(&ctx);
3586
3587 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3588 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3589
3590 nir_foreach_variable(variable, &geom_shader->outputs) {
3591 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3592 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3593 variable, MESA_SHADER_VERTEX);
3594 }
3595
3596 ac_gs_copy_shader_emit(&ctx);
3597
3598 LLVMBuildRetVoid(ctx.ac.builder);
3599
3600 ac_llvm_finalize_module(&ctx);
3601
3602 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
3603 MESA_SHADER_VERTEX, options);
3604 }