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ac/nir: Fix include for LLVMAddPromoteMemoryToRegisterPass
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "nir/nir.h"
31
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35 #if HAVE_LLVM >= 0x0700
36 #include <llvm-c/Transforms/Utils.h>
37 #endif
38
39 #include "sid.h"
40 #include "gfx9d.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_llvm_build.h"
44 #include "ac_shader_abi.h"
45 #include "ac_shader_util.h"
46 #include "ac_exp_param.h"
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct radv_shader_context {
51 struct ac_llvm_context ac;
52 const struct radv_nir_compiler_options *options;
53 struct radv_shader_variant_info *shader_info;
54 struct ac_shader_abi abi;
55
56 unsigned max_workgroup_size;
57 LLVMContextRef context;
58 LLVMValueRef main_function;
59
60 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
61 LLVMValueRef ring_offsets;
62
63 LLVMValueRef vertex_buffers;
64 LLVMValueRef rel_auto_id;
65 LLVMValueRef vs_prim_id;
66 LLVMValueRef es2gs_offset;
67
68 LLVMValueRef oc_lds;
69 LLVMValueRef merged_wave_info;
70 LLVMValueRef tess_factor_offset;
71 LLVMValueRef tes_rel_patch_id;
72 LLVMValueRef tes_u;
73 LLVMValueRef tes_v;
74
75 LLVMValueRef gs2vs_offset;
76 LLVMValueRef gs_wave_id;
77 LLVMValueRef gs_vtx_offset[6];
78
79 LLVMValueRef esgs_ring;
80 LLVMValueRef gsvs_ring;
81 LLVMValueRef hs_ring_tess_offchip;
82 LLVMValueRef hs_ring_tess_factor;
83
84 LLVMValueRef sample_pos_offset;
85 LLVMValueRef persp_sample, persp_center, persp_centroid;
86 LLVMValueRef linear_sample, linear_center, linear_centroid;
87
88 gl_shader_stage stage;
89
90 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
91
92 uint64_t input_mask;
93 uint64_t output_mask;
94 uint8_t num_output_clips;
95 uint8_t num_output_culls;
96
97 bool is_gs_copy_shader;
98 LLVMValueRef gs_next_vertex;
99 unsigned gs_max_out_vertices;
100
101 unsigned tes_primitive_mode;
102
103 uint32_t tcs_patch_outputs_read;
104 uint64_t tcs_outputs_read;
105 uint32_t tcs_vertices_per_patch;
106 uint32_t tcs_num_inputs;
107 uint32_t tcs_num_patches;
108 uint32_t max_gsvs_emit_size;
109 uint32_t gsvs_vertex_size;
110 };
111
112 enum radeon_llvm_calling_convention {
113 RADEON_LLVM_AMDGPU_VS = 87,
114 RADEON_LLVM_AMDGPU_GS = 88,
115 RADEON_LLVM_AMDGPU_PS = 89,
116 RADEON_LLVM_AMDGPU_CS = 90,
117 RADEON_LLVM_AMDGPU_HS = 93,
118 };
119
120 static inline struct radv_shader_context *
121 radv_shader_context_from_abi(struct ac_shader_abi *abi)
122 {
123 struct radv_shader_context *ctx = NULL;
124 return container_of(abi, ctx, abi);
125 }
126
127 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
128 {
129 switch (ctx->stage) {
130 case MESA_SHADER_TESS_CTRL:
131 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
132 case MESA_SHADER_TESS_EVAL:
133 return ctx->tes_rel_patch_id;
134 break;
135 default:
136 unreachable("Illegal stage");
137 }
138 }
139
140 static unsigned
141 get_tcs_num_patches(struct radv_shader_context *ctx)
142 {
143 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
144 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
145 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
146 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
147 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
148 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
149 uint32_t output_vertex_size = num_tcs_outputs * 16;
150 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
151 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
152 unsigned num_patches;
153 unsigned hardware_lds_size;
154
155 /* Ensure that we only need one wave per SIMD so we don't need to check
156 * resource usage. Also ensures that the number of tcs in and out
157 * vertices per threadgroup are at most 256.
158 */
159 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
160 /* Make sure that the data fits in LDS. This assumes the shaders only
161 * use LDS for the inputs and outputs.
162 */
163 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
164 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
165 /* Make sure the output data fits in the offchip buffer */
166 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
167 /* Not necessary for correctness, but improves performance. The
168 * specific value is taken from the proprietary driver.
169 */
170 num_patches = MIN2(num_patches, 40);
171
172 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
173 if (ctx->options->chip_class == SI) {
174 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
175 num_patches = MIN2(num_patches, one_wave);
176 }
177 return num_patches;
178 }
179
180 static unsigned
181 calculate_tess_lds_size(struct radv_shader_context *ctx)
182 {
183 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
184 unsigned num_tcs_output_cp;
185 unsigned num_tcs_outputs, num_tcs_patch_outputs;
186 unsigned input_vertex_size, output_vertex_size;
187 unsigned input_patch_size, output_patch_size;
188 unsigned pervertex_output_patch_size;
189 unsigned output_patch0_offset;
190 unsigned num_patches;
191 unsigned lds_size;
192
193 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
194 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
195 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
196
197 input_vertex_size = ctx->tcs_num_inputs * 16;
198 output_vertex_size = num_tcs_outputs * 16;
199
200 input_patch_size = num_tcs_input_cp * input_vertex_size;
201
202 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
203 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
204
205 num_patches = ctx->tcs_num_patches;
206 output_patch0_offset = input_patch_size * num_patches;
207
208 lds_size = output_patch0_offset + output_patch_size * num_patches;
209 return lds_size;
210 }
211
212 /* Tessellation shaders pass outputs to the next shader using LDS.
213 *
214 * LS outputs = TCS inputs
215 * TCS outputs = TES inputs
216 *
217 * The LDS layout is:
218 * - TCS inputs for patch 0
219 * - TCS inputs for patch 1
220 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
221 * - ...
222 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
223 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
224 * - TCS outputs for patch 1
225 * - Per-patch TCS outputs for patch 1
226 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
227 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
228 * - ...
229 *
230 * All three shaders VS(LS), TCS, TES share the same LDS space.
231 */
232 static LLVMValueRef
233 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
234 {
235 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
236 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
237 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
238
239 input_patch_size /= 4;
240 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
241 }
242
243 static LLVMValueRef
244 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
245 {
246 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
247 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
248 uint32_t output_vertex_size = num_tcs_outputs * 16;
249 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
250 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
251 output_patch_size /= 4;
252 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
253 }
254
255 static LLVMValueRef
256 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
257 {
258 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
259 uint32_t output_vertex_size = num_tcs_outputs * 16;
260 output_vertex_size /= 4;
261 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
262 }
263
264 static LLVMValueRef
265 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
266 {
267 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
268 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
269 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
270 uint32_t output_patch0_offset = input_patch_size;
271 unsigned num_patches = ctx->tcs_num_patches;
272
273 output_patch0_offset *= num_patches;
274 output_patch0_offset /= 4;
275 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
276 }
277
278 static LLVMValueRef
279 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
280 {
281 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
282 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
283 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
284 uint32_t output_patch0_offset = input_patch_size;
285
286 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
287 uint32_t output_vertex_size = num_tcs_outputs * 16;
288 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
289 unsigned num_patches = ctx->tcs_num_patches;
290
291 output_patch0_offset *= num_patches;
292 output_patch0_offset += pervertex_output_patch_size;
293 output_patch0_offset /= 4;
294 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
295 }
296
297 static LLVMValueRef
298 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
299 {
300 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
301 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
302
303 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
304 }
305
306 static LLVMValueRef
307 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
308 {
309 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
310 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
311 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
312
313 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
314 LLVMBuildMul(ctx->ac.builder, patch_stride,
315 rel_patch_id, ""),
316 "");
317 }
318
319 static LLVMValueRef
320 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
321 {
322 LLVMValueRef patch0_patch_data_offset =
323 get_tcs_out_patch0_patch_data_offset(ctx);
324 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
325 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
326
327 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
328 LLVMBuildMul(ctx->ac.builder, patch_stride,
329 rel_patch_id, ""),
330 "");
331 }
332
333 #define MAX_ARGS 23
334 struct arg_info {
335 LLVMTypeRef types[MAX_ARGS];
336 LLVMValueRef *assign[MAX_ARGS];
337 unsigned array_params_mask;
338 uint8_t count;
339 uint8_t sgpr_count;
340 uint8_t num_sgprs_used;
341 uint8_t num_vgprs_used;
342 };
343
344 enum ac_arg_regfile {
345 ARG_SGPR,
346 ARG_VGPR,
347 };
348
349 static void
350 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
351 LLVMValueRef *param_ptr)
352 {
353 assert(info->count < MAX_ARGS);
354
355 info->assign[info->count] = param_ptr;
356 info->types[info->count] = type;
357 info->count++;
358
359 if (regfile == ARG_SGPR) {
360 info->num_sgprs_used += ac_get_type_size(type) / 4;
361 info->sgpr_count++;
362 } else {
363 assert(regfile == ARG_VGPR);
364 info->num_vgprs_used += ac_get_type_size(type) / 4;
365 }
366 }
367
368 static inline void
369 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
370 {
371 info->array_params_mask |= (1 << info->count);
372 add_arg(info, ARG_SGPR, type, param_ptr);
373 }
374
375 static void assign_arguments(LLVMValueRef main_function,
376 struct arg_info *info)
377 {
378 unsigned i;
379 for (i = 0; i < info->count; i++) {
380 if (info->assign[i])
381 *info->assign[i] = LLVMGetParam(main_function, i);
382 }
383 }
384
385 static LLVMValueRef
386 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
387 LLVMBuilderRef builder, LLVMTypeRef *return_types,
388 unsigned num_return_elems,
389 struct arg_info *args,
390 unsigned max_workgroup_size,
391 bool unsafe_math)
392 {
393 LLVMTypeRef main_function_type, ret_type;
394 LLVMBasicBlockRef main_function_body;
395
396 if (num_return_elems)
397 ret_type = LLVMStructTypeInContext(ctx, return_types,
398 num_return_elems, true);
399 else
400 ret_type = LLVMVoidTypeInContext(ctx);
401
402 /* Setup the function */
403 main_function_type =
404 LLVMFunctionType(ret_type, args->types, args->count, 0);
405 LLVMValueRef main_function =
406 LLVMAddFunction(module, "main", main_function_type);
407 main_function_body =
408 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
409 LLVMPositionBuilderAtEnd(builder, main_function_body);
410
411 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
412 for (unsigned i = 0; i < args->sgpr_count; ++i) {
413 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
414
415 if (args->array_params_mask & (1 << i)) {
416 LLVMValueRef P = LLVMGetParam(main_function, i);
417 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
418 ac_add_attr_dereferenceable(P, UINT64_MAX);
419 }
420 }
421
422 if (max_workgroup_size) {
423 ac_llvm_add_target_dep_function_attr(main_function,
424 "amdgpu-max-work-group-size",
425 max_workgroup_size);
426 }
427 if (unsafe_math) {
428 /* These were copied from some LLVM test. */
429 LLVMAddTargetDependentFunctionAttr(main_function,
430 "less-precise-fpmad",
431 "true");
432 LLVMAddTargetDependentFunctionAttr(main_function,
433 "no-infs-fp-math",
434 "true");
435 LLVMAddTargetDependentFunctionAttr(main_function,
436 "no-nans-fp-math",
437 "true");
438 LLVMAddTargetDependentFunctionAttr(main_function,
439 "unsafe-fp-math",
440 "true");
441 LLVMAddTargetDependentFunctionAttr(main_function,
442 "no-signed-zeros-fp-math",
443 "true");
444 }
445 return main_function;
446 }
447
448
449 static void
450 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
451 uint32_t indirect_offset)
452 {
453 ud_info->sgpr_idx = *sgpr_idx;
454 ud_info->num_sgprs = num_sgprs;
455 ud_info->indirect = indirect_offset > 0;
456 ud_info->indirect_offset = indirect_offset;
457 *sgpr_idx += num_sgprs;
458 }
459
460 static void
461 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
462 uint8_t num_sgprs)
463 {
464 struct radv_userdata_info *ud_info =
465 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
466 assert(ud_info);
467
468 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
469 }
470
471 static void
472 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
473 uint32_t indirect_offset)
474 {
475 struct radv_userdata_info *ud_info =
476 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
477 assert(ud_info);
478
479 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
480 }
481
482 struct user_sgpr_info {
483 bool need_ring_offsets;
484 uint8_t sgpr_count;
485 bool indirect_all_descriptor_sets;
486 };
487
488 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
489 gl_shader_stage stage)
490 {
491 switch (stage) {
492 case MESA_SHADER_VERTEX:
493 if (ctx->shader_info->info.needs_multiview_view_index ||
494 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
495 return true;
496 break;
497 case MESA_SHADER_TESS_EVAL:
498 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
499 return true;
500 break;
501 case MESA_SHADER_GEOMETRY:
502 case MESA_SHADER_TESS_CTRL:
503 if (ctx->shader_info->info.needs_multiview_view_index)
504 return true;
505 break;
506 default:
507 break;
508 }
509 return false;
510 }
511
512 static uint8_t
513 count_vs_user_sgprs(struct radv_shader_context *ctx)
514 {
515 uint8_t count = 0;
516
517 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
518 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
519
520 return count;
521 }
522
523 static void allocate_user_sgprs(struct radv_shader_context *ctx,
524 gl_shader_stage stage,
525 bool has_previous_stage,
526 gl_shader_stage previous_stage,
527 bool needs_view_index,
528 struct user_sgpr_info *user_sgpr_info)
529 {
530 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
531
532 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
533 if (stage == MESA_SHADER_GEOMETRY ||
534 stage == MESA_SHADER_VERTEX ||
535 stage == MESA_SHADER_TESS_CTRL ||
536 stage == MESA_SHADER_TESS_EVAL ||
537 ctx->is_gs_copy_shader)
538 user_sgpr_info->need_ring_offsets = true;
539
540 if (stage == MESA_SHADER_FRAGMENT &&
541 ctx->shader_info->info.ps.needs_sample_positions)
542 user_sgpr_info->need_ring_offsets = true;
543
544 /* 2 user sgprs will nearly always be allocated for scratch/rings */
545 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
546 user_sgpr_info->sgpr_count += 2;
547 }
548
549 switch (stage) {
550 case MESA_SHADER_COMPUTE:
551 if (ctx->shader_info->info.cs.uses_grid_size)
552 user_sgpr_info->sgpr_count += 3;
553 break;
554 case MESA_SHADER_FRAGMENT:
555 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
556 break;
557 case MESA_SHADER_VERTEX:
558 if (!ctx->is_gs_copy_shader)
559 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
560 break;
561 case MESA_SHADER_TESS_CTRL:
562 if (has_previous_stage) {
563 if (previous_stage == MESA_SHADER_VERTEX)
564 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
565 }
566 break;
567 case MESA_SHADER_TESS_EVAL:
568 break;
569 case MESA_SHADER_GEOMETRY:
570 if (has_previous_stage) {
571 if (previous_stage == MESA_SHADER_VERTEX) {
572 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
573 }
574 }
575 break;
576 default:
577 break;
578 }
579
580 if (needs_view_index)
581 user_sgpr_info->sgpr_count++;
582
583 if (ctx->shader_info->info.loads_push_constants)
584 user_sgpr_info->sgpr_count += 2;
585
586 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
587 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
588
589 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
590 user_sgpr_info->sgpr_count += 2;
591 user_sgpr_info->indirect_all_descriptor_sets = true;
592 } else {
593 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
594 }
595 }
596
597 static void
598 declare_global_input_sgprs(struct radv_shader_context *ctx,
599 gl_shader_stage stage,
600 bool has_previous_stage,
601 gl_shader_stage previous_stage,
602 const struct user_sgpr_info *user_sgpr_info,
603 struct arg_info *args,
604 LLVMValueRef *desc_sets)
605 {
606 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
607 unsigned num_sets = ctx->options->layout ?
608 ctx->options->layout->num_sets : 0;
609 unsigned stage_mask = 1 << stage;
610
611 if (has_previous_stage)
612 stage_mask |= 1 << previous_stage;
613
614 /* 1 for each descriptor set */
615 if (!user_sgpr_info->indirect_all_descriptor_sets) {
616 for (unsigned i = 0; i < num_sets; ++i) {
617 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
618 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
619 add_array_arg(args, type,
620 &ctx->descriptor_sets[i]);
621 }
622 }
623 } else {
624 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
625 }
626
627 if (ctx->shader_info->info.loads_push_constants) {
628 /* 1 for push constants and dynamic descriptors */
629 add_array_arg(args, type, &ctx->abi.push_constants);
630 }
631 }
632
633 static void
634 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
635 gl_shader_stage stage,
636 bool has_previous_stage,
637 gl_shader_stage previous_stage,
638 struct arg_info *args)
639 {
640 if (!ctx->is_gs_copy_shader &&
641 (stage == MESA_SHADER_VERTEX ||
642 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
643 if (ctx->shader_info->info.vs.has_vertex_buffers) {
644 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
645 &ctx->vertex_buffers);
646 }
647 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
648 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
649 if (ctx->shader_info->info.vs.needs_draw_id) {
650 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
651 }
652 }
653 }
654
655 static void
656 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
657 {
658 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
659 if (!ctx->is_gs_copy_shader) {
660 if (ctx->options->key.vs.as_ls) {
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
662 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
663 } else {
664 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
665 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
666 }
667 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
668 }
669 }
670
671 static void
672 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
673 {
674 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
675 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
676 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
678 }
679
680 static void
681 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
682 bool has_previous_stage, gl_shader_stage previous_stage,
683 const struct user_sgpr_info *user_sgpr_info,
684 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
685 {
686 unsigned num_sets = ctx->options->layout ?
687 ctx->options->layout->num_sets : 0;
688 unsigned stage_mask = 1 << stage;
689
690 if (has_previous_stage)
691 stage_mask |= 1 << previous_stage;
692
693 if (!user_sgpr_info->indirect_all_descriptor_sets) {
694 for (unsigned i = 0; i < num_sets; ++i) {
695 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
696 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
697 set_loc_desc(ctx, i, user_sgpr_idx, 0);
698 } else
699 ctx->descriptor_sets[i] = NULL;
700 }
701 } else {
702 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
703 user_sgpr_idx, 2);
704
705 for (unsigned i = 0; i < num_sets; ++i) {
706 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
707 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
708 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
709 ctx->descriptor_sets[i] =
710 ac_build_load_to_sgpr(&ctx->ac,
711 desc_sets,
712 LLVMConstInt(ctx->ac.i32, i, false));
713
714 } else
715 ctx->descriptor_sets[i] = NULL;
716 }
717 ctx->shader_info->need_indirect_descriptor_sets = true;
718 }
719
720 if (ctx->shader_info->info.loads_push_constants) {
721 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
722 }
723 }
724
725 static void
726 set_vs_specific_input_locs(struct radv_shader_context *ctx,
727 gl_shader_stage stage, bool has_previous_stage,
728 gl_shader_stage previous_stage,
729 uint8_t *user_sgpr_idx)
730 {
731 if (!ctx->is_gs_copy_shader &&
732 (stage == MESA_SHADER_VERTEX ||
733 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
734 if (ctx->shader_info->info.vs.has_vertex_buffers) {
735 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
736 user_sgpr_idx, 2);
737 }
738
739 unsigned vs_num = 2;
740 if (ctx->shader_info->info.vs.needs_draw_id)
741 vs_num++;
742
743 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
744 user_sgpr_idx, vs_num);
745 }
746 }
747
748 static void set_llvm_calling_convention(LLVMValueRef func,
749 gl_shader_stage stage)
750 {
751 enum radeon_llvm_calling_convention calling_conv;
752
753 switch (stage) {
754 case MESA_SHADER_VERTEX:
755 case MESA_SHADER_TESS_EVAL:
756 calling_conv = RADEON_LLVM_AMDGPU_VS;
757 break;
758 case MESA_SHADER_GEOMETRY:
759 calling_conv = RADEON_LLVM_AMDGPU_GS;
760 break;
761 case MESA_SHADER_TESS_CTRL:
762 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
763 break;
764 case MESA_SHADER_FRAGMENT:
765 calling_conv = RADEON_LLVM_AMDGPU_PS;
766 break;
767 case MESA_SHADER_COMPUTE:
768 calling_conv = RADEON_LLVM_AMDGPU_CS;
769 break;
770 default:
771 unreachable("Unhandle shader type");
772 }
773
774 LLVMSetFunctionCallConv(func, calling_conv);
775 }
776
777 static void create_function(struct radv_shader_context *ctx,
778 gl_shader_stage stage,
779 bool has_previous_stage,
780 gl_shader_stage previous_stage)
781 {
782 uint8_t user_sgpr_idx;
783 struct user_sgpr_info user_sgpr_info;
784 struct arg_info args = {};
785 LLVMValueRef desc_sets;
786 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
787 allocate_user_sgprs(ctx, stage, has_previous_stage,
788 previous_stage, needs_view_index, &user_sgpr_info);
789
790 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
791 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
792 &ctx->ring_offsets);
793 }
794
795 switch (stage) {
796 case MESA_SHADER_COMPUTE:
797 declare_global_input_sgprs(ctx, stage, has_previous_stage,
798 previous_stage, &user_sgpr_info,
799 &args, &desc_sets);
800
801 if (ctx->shader_info->info.cs.uses_grid_size) {
802 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
803 &ctx->abi.num_work_groups);
804 }
805
806 for (int i = 0; i < 3; i++) {
807 ctx->abi.workgroup_ids[i] = NULL;
808 if (ctx->shader_info->info.cs.uses_block_id[i]) {
809 add_arg(&args, ARG_SGPR, ctx->ac.i32,
810 &ctx->abi.workgroup_ids[i]);
811 }
812 }
813
814 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
816 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
817 &ctx->abi.local_invocation_ids);
818 break;
819 case MESA_SHADER_VERTEX:
820 declare_global_input_sgprs(ctx, stage, has_previous_stage,
821 previous_stage, &user_sgpr_info,
822 &args, &desc_sets);
823 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
824 previous_stage, &args);
825
826 if (needs_view_index)
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->abi.view_index);
829 if (ctx->options->key.vs.as_es)
830 add_arg(&args, ARG_SGPR, ctx->ac.i32,
831 &ctx->es2gs_offset);
832
833 declare_vs_input_vgprs(ctx, &args);
834 break;
835 case MESA_SHADER_TESS_CTRL:
836 if (has_previous_stage) {
837 // First 6 system regs
838 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->merged_wave_info);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tess_factor_offset);
843
844 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
845 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
846 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
847
848 declare_global_input_sgprs(ctx, stage,
849 has_previous_stage,
850 previous_stage,
851 &user_sgpr_info, &args,
852 &desc_sets);
853 declare_vs_specific_input_sgprs(ctx, stage,
854 has_previous_stage,
855 previous_stage, &args);
856
857 if (needs_view_index)
858 add_arg(&args, ARG_SGPR, ctx->ac.i32,
859 &ctx->abi.view_index);
860
861 add_arg(&args, ARG_VGPR, ctx->ac.i32,
862 &ctx->abi.tcs_patch_id);
863 add_arg(&args, ARG_VGPR, ctx->ac.i32,
864 &ctx->abi.tcs_rel_ids);
865
866 declare_vs_input_vgprs(ctx, &args);
867 } else {
868 declare_global_input_sgprs(ctx, stage,
869 has_previous_stage,
870 previous_stage,
871 &user_sgpr_info, &args,
872 &desc_sets);
873
874 if (needs_view_index)
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->abi.view_index);
877
878 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
879 add_arg(&args, ARG_SGPR, ctx->ac.i32,
880 &ctx->tess_factor_offset);
881 add_arg(&args, ARG_VGPR, ctx->ac.i32,
882 &ctx->abi.tcs_patch_id);
883 add_arg(&args, ARG_VGPR, ctx->ac.i32,
884 &ctx->abi.tcs_rel_ids);
885 }
886 break;
887 case MESA_SHADER_TESS_EVAL:
888 declare_global_input_sgprs(ctx, stage, has_previous_stage,
889 previous_stage, &user_sgpr_info,
890 &args, &desc_sets);
891
892 if (needs_view_index)
893 add_arg(&args, ARG_SGPR, ctx->ac.i32,
894 &ctx->abi.view_index);
895
896 if (ctx->options->key.tes.as_es) {
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
898 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
899 add_arg(&args, ARG_SGPR, ctx->ac.i32,
900 &ctx->es2gs_offset);
901 } else {
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
903 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
904 }
905 declare_tes_input_vgprs(ctx, &args);
906 break;
907 case MESA_SHADER_GEOMETRY:
908 if (has_previous_stage) {
909 // First 6 system regs
910 add_arg(&args, ARG_SGPR, ctx->ac.i32,
911 &ctx->gs2vs_offset);
912 add_arg(&args, ARG_SGPR, ctx->ac.i32,
913 &ctx->merged_wave_info);
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
915
916 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
917 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
918 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
919
920 declare_global_input_sgprs(ctx, stage,
921 has_previous_stage,
922 previous_stage,
923 &user_sgpr_info, &args,
924 &desc_sets);
925
926 if (previous_stage != MESA_SHADER_TESS_EVAL) {
927 declare_vs_specific_input_sgprs(ctx, stage,
928 has_previous_stage,
929 previous_stage,
930 &args);
931 }
932
933 if (needs_view_index)
934 add_arg(&args, ARG_SGPR, ctx->ac.i32,
935 &ctx->abi.view_index);
936
937 add_arg(&args, ARG_VGPR, ctx->ac.i32,
938 &ctx->gs_vtx_offset[0]);
939 add_arg(&args, ARG_VGPR, ctx->ac.i32,
940 &ctx->gs_vtx_offset[2]);
941 add_arg(&args, ARG_VGPR, ctx->ac.i32,
942 &ctx->abi.gs_prim_id);
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->abi.gs_invocation_id);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->gs_vtx_offset[4]);
947
948 if (previous_stage == MESA_SHADER_VERTEX) {
949 declare_vs_input_vgprs(ctx, &args);
950 } else {
951 declare_tes_input_vgprs(ctx, &args);
952 }
953 } else {
954 declare_global_input_sgprs(ctx, stage,
955 has_previous_stage,
956 previous_stage,
957 &user_sgpr_info, &args,
958 &desc_sets);
959
960 if (needs_view_index)
961 add_arg(&args, ARG_SGPR, ctx->ac.i32,
962 &ctx->abi.view_index);
963
964 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
965 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
966 add_arg(&args, ARG_VGPR, ctx->ac.i32,
967 &ctx->gs_vtx_offset[0]);
968 add_arg(&args, ARG_VGPR, ctx->ac.i32,
969 &ctx->gs_vtx_offset[1]);
970 add_arg(&args, ARG_VGPR, ctx->ac.i32,
971 &ctx->abi.gs_prim_id);
972 add_arg(&args, ARG_VGPR, ctx->ac.i32,
973 &ctx->gs_vtx_offset[2]);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[3]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[4]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->gs_vtx_offset[5]);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->abi.gs_invocation_id);
982 }
983 break;
984 case MESA_SHADER_FRAGMENT:
985 declare_global_input_sgprs(ctx, stage, has_previous_stage,
986 previous_stage, &user_sgpr_info,
987 &args, &desc_sets);
988
989 if (ctx->shader_info->info.ps.needs_sample_positions)
990 add_arg(&args, ARG_SGPR, ctx->ac.i32,
991 &ctx->sample_pos_offset);
992
993 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
994 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
995 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
996 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
997 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
998 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
999 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1000 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1001 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1002 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1003 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1004 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1005 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1006 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1007 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1008 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1009 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1010 break;
1011 default:
1012 unreachable("Shader stage not implemented");
1013 }
1014
1015 ctx->main_function = create_llvm_function(
1016 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1017 ctx->max_workgroup_size,
1018 ctx->options->unsafe_math);
1019 set_llvm_calling_convention(ctx->main_function, stage);
1020
1021
1022 ctx->shader_info->num_input_vgprs = 0;
1023 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1024
1025 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1026
1027 if (ctx->stage != MESA_SHADER_FRAGMENT)
1028 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1029
1030 assign_arguments(ctx->main_function, &args);
1031
1032 user_sgpr_idx = 0;
1033
1034 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1035 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1036 &user_sgpr_idx, 2);
1037 if (ctx->options->supports_spill) {
1038 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1039 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1040 NULL, 0, AC_FUNC_ATTR_READNONE);
1041 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1042 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1043 }
1044 }
1045
1046 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1047 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1048 if (has_previous_stage)
1049 user_sgpr_idx = 0;
1050
1051 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1052 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1053
1054 switch (stage) {
1055 case MESA_SHADER_COMPUTE:
1056 if (ctx->shader_info->info.cs.uses_grid_size) {
1057 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1058 &user_sgpr_idx, 3);
1059 }
1060 break;
1061 case MESA_SHADER_VERTEX:
1062 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1063 previous_stage, &user_sgpr_idx);
1064 if (ctx->abi.view_index)
1065 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1066 break;
1067 case MESA_SHADER_TESS_CTRL:
1068 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1069 previous_stage, &user_sgpr_idx);
1070 if (ctx->abi.view_index)
1071 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1072 break;
1073 case MESA_SHADER_TESS_EVAL:
1074 if (ctx->abi.view_index)
1075 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1076 break;
1077 case MESA_SHADER_GEOMETRY:
1078 if (has_previous_stage) {
1079 if (previous_stage == MESA_SHADER_VERTEX)
1080 set_vs_specific_input_locs(ctx, stage,
1081 has_previous_stage,
1082 previous_stage,
1083 &user_sgpr_idx);
1084 }
1085 if (ctx->abi.view_index)
1086 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1087 break;
1088 case MESA_SHADER_FRAGMENT:
1089 if (ctx->shader_info->info.ps.needs_sample_positions) {
1090 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1091 &user_sgpr_idx, 1);
1092 }
1093 break;
1094 default:
1095 unreachable("Shader stage not implemented");
1096 }
1097
1098 if (stage == MESA_SHADER_TESS_CTRL ||
1099 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1100 /* GFX9 has the ESGS ring buffer in LDS. */
1101 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1102 ac_declare_lds_as_pointer(&ctx->ac);
1103 }
1104
1105 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1106 }
1107
1108
1109 static LLVMValueRef
1110 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1111 unsigned desc_set, unsigned binding)
1112 {
1113 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1114 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1115 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1116 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1117 unsigned base_offset = layout->binding[binding].offset;
1118 LLVMValueRef offset, stride;
1119
1120 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1121 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1122 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1123 layout->binding[binding].dynamic_offset_offset;
1124 desc_ptr = ctx->abi.push_constants;
1125 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1126 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1127 } else
1128 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1129
1130 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1131 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
1132 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
1133
1134 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1135 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1136 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1137
1138 return desc_ptr;
1139 }
1140
1141
1142 /* The offchip buffer layout for TCS->TES is
1143 *
1144 * - attribute 0 of patch 0 vertex 0
1145 * - attribute 0 of patch 0 vertex 1
1146 * - attribute 0 of patch 0 vertex 2
1147 * ...
1148 * - attribute 0 of patch 1 vertex 0
1149 * - attribute 0 of patch 1 vertex 1
1150 * ...
1151 * - attribute 1 of patch 0 vertex 0
1152 * - attribute 1 of patch 0 vertex 1
1153 * ...
1154 * - per patch attribute 0 of patch 0
1155 * - per patch attribute 0 of patch 1
1156 * ...
1157 *
1158 * Note that every attribute has 4 components.
1159 */
1160 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1161 {
1162 uint32_t num_patches = ctx->tcs_num_patches;
1163 uint32_t num_tcs_outputs;
1164 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1165 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1166 else
1167 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1168
1169 uint32_t output_vertex_size = num_tcs_outputs * 16;
1170 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1171
1172 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1173 }
1174
1175 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1176 LLVMValueRef vertex_index)
1177 {
1178 LLVMValueRef param_stride;
1179 if (vertex_index)
1180 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1181 else
1182 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1183 return param_stride;
1184 }
1185
1186 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1187 LLVMValueRef vertex_index,
1188 LLVMValueRef param_index)
1189 {
1190 LLVMValueRef base_addr;
1191 LLVMValueRef param_stride, constant16;
1192 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1193 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1194 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1195 param_stride = calc_param_stride(ctx, vertex_index);
1196 if (vertex_index) {
1197 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
1198 vertices_per_patch, "");
1199
1200 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1201 vertex_index, "");
1202 } else {
1203 base_addr = rel_patch_id;
1204 }
1205
1206 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1207 LLVMBuildMul(ctx->ac.builder, param_index,
1208 param_stride, ""), "");
1209
1210 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1211
1212 if (!vertex_index) {
1213 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1214
1215 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1216 patch_data_offset, "");
1217 }
1218 return base_addr;
1219 }
1220
1221 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1222 unsigned param,
1223 unsigned const_index,
1224 bool is_compact,
1225 LLVMValueRef vertex_index,
1226 LLVMValueRef indir_index)
1227 {
1228 LLVMValueRef param_index;
1229
1230 if (indir_index)
1231 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1232 indir_index, "");
1233 else {
1234 if (const_index && !is_compact)
1235 param += const_index;
1236 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1237 }
1238 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1239 }
1240
1241 static LLVMValueRef
1242 get_dw_address(struct radv_shader_context *ctx,
1243 LLVMValueRef dw_addr,
1244 unsigned param,
1245 unsigned const_index,
1246 bool compact_const_index,
1247 LLVMValueRef vertex_index,
1248 LLVMValueRef stride,
1249 LLVMValueRef indir_index)
1250
1251 {
1252
1253 if (vertex_index) {
1254 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1255 LLVMBuildMul(ctx->ac.builder,
1256 vertex_index,
1257 stride, ""), "");
1258 }
1259
1260 if (indir_index)
1261 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1262 LLVMBuildMul(ctx->ac.builder, indir_index,
1263 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1264 else if (const_index && !compact_const_index)
1265 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1266 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1267
1268 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1269 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1270
1271 if (const_index && compact_const_index)
1272 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1273 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1274 return dw_addr;
1275 }
1276
1277 static LLVMValueRef
1278 load_tcs_varyings(struct ac_shader_abi *abi,
1279 LLVMTypeRef type,
1280 LLVMValueRef vertex_index,
1281 LLVMValueRef indir_index,
1282 unsigned const_index,
1283 unsigned location,
1284 unsigned driver_location,
1285 unsigned component,
1286 unsigned num_components,
1287 bool is_patch,
1288 bool is_compact,
1289 bool load_input)
1290 {
1291 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1292 LLVMValueRef dw_addr, stride;
1293 LLVMValueRef value[4], result;
1294 unsigned param = shader_io_get_unique_index(location);
1295
1296 if (load_input) {
1297 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1298 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1299 dw_addr = get_tcs_in_current_patch_offset(ctx);
1300 } else {
1301 if (!is_patch) {
1302 stride = get_tcs_out_vertex_stride(ctx);
1303 dw_addr = get_tcs_out_current_patch_offset(ctx);
1304 } else {
1305 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1306 stride = NULL;
1307 }
1308 }
1309
1310 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1311 indir_index);
1312
1313 for (unsigned i = 0; i < num_components + component; i++) {
1314 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1315 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1316 ctx->ac.i32_1, "");
1317 }
1318 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1319 return result;
1320 }
1321
1322 static void
1323 store_tcs_output(struct ac_shader_abi *abi,
1324 const nir_variable *var,
1325 LLVMValueRef vertex_index,
1326 LLVMValueRef param_index,
1327 unsigned const_index,
1328 LLVMValueRef src,
1329 unsigned writemask)
1330 {
1331 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1332 const unsigned location = var->data.location;
1333 const unsigned component = var->data.location_frac;
1334 const bool is_patch = var->data.patch;
1335 const bool is_compact = var->data.compact;
1336 LLVMValueRef dw_addr;
1337 LLVMValueRef stride = NULL;
1338 LLVMValueRef buf_addr = NULL;
1339 unsigned param;
1340 bool store_lds = true;
1341
1342 if (is_patch) {
1343 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1344 store_lds = false;
1345 } else {
1346 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1347 store_lds = false;
1348 }
1349
1350 param = shader_io_get_unique_index(location);
1351 if (location == VARYING_SLOT_CLIP_DIST0 &&
1352 is_compact && const_index > 3) {
1353 const_index -= 3;
1354 param++;
1355 }
1356
1357 if (!is_patch) {
1358 stride = get_tcs_out_vertex_stride(ctx);
1359 dw_addr = get_tcs_out_current_patch_offset(ctx);
1360 } else {
1361 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1362 }
1363
1364 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1365 param_index);
1366 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1367 vertex_index, param_index);
1368
1369 bool is_tess_factor = false;
1370 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1371 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1372 is_tess_factor = true;
1373
1374 unsigned base = is_compact ? const_index : 0;
1375 for (unsigned chan = 0; chan < 8; chan++) {
1376 if (!(writemask & (1 << chan)))
1377 continue;
1378 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1379
1380 if (store_lds || is_tess_factor) {
1381 LLVMValueRef dw_addr_chan =
1382 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1383 LLVMConstInt(ctx->ac.i32, chan, false), "");
1384 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1385 }
1386
1387 if (!is_tess_factor && writemask != 0xF)
1388 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1389 buf_addr, ctx->oc_lds,
1390 4 * (base + chan), 1, 0, true, false);
1391 }
1392
1393 if (writemask == 0xF) {
1394 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1395 buf_addr, ctx->oc_lds,
1396 (base * 4), 1, 0, true, false);
1397 }
1398 }
1399
1400 static LLVMValueRef
1401 load_tes_input(struct ac_shader_abi *abi,
1402 LLVMTypeRef type,
1403 LLVMValueRef vertex_index,
1404 LLVMValueRef param_index,
1405 unsigned const_index,
1406 unsigned location,
1407 unsigned driver_location,
1408 unsigned component,
1409 unsigned num_components,
1410 bool is_patch,
1411 bool is_compact,
1412 bool load_input)
1413 {
1414 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1415 LLVMValueRef buf_addr;
1416 LLVMValueRef result;
1417 unsigned param = shader_io_get_unique_index(location);
1418
1419 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1420 const_index -= 3;
1421 param++;
1422 }
1423
1424 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1425 is_compact, vertex_index, param_index);
1426
1427 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1428 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1429
1430 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1431 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1432 result = ac_trim_vector(&ctx->ac, result, num_components);
1433 return result;
1434 }
1435
1436 static LLVMValueRef
1437 load_gs_input(struct ac_shader_abi *abi,
1438 unsigned location,
1439 unsigned driver_location,
1440 unsigned component,
1441 unsigned num_components,
1442 unsigned vertex_index,
1443 unsigned const_index,
1444 LLVMTypeRef type)
1445 {
1446 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1447 LLVMValueRef vtx_offset;
1448 unsigned param, vtx_offset_param;
1449 LLVMValueRef value[4], result;
1450
1451 vtx_offset_param = vertex_index;
1452 assert(vtx_offset_param < 6);
1453 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1454 LLVMConstInt(ctx->ac.i32, 4, false), "");
1455
1456 param = shader_io_get_unique_index(location);
1457
1458 for (unsigned i = component; i < num_components + component; i++) {
1459 if (ctx->ac.chip_class >= GFX9) {
1460 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1461 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1462 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1463 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1464 } else {
1465 LLVMValueRef soffset =
1466 LLVMConstInt(ctx->ac.i32,
1467 (param * 4 + i + const_index) * 256,
1468 false);
1469
1470 value[i] = ac_build_buffer_load(&ctx->ac,
1471 ctx->esgs_ring, 1,
1472 ctx->ac.i32_0,
1473 vtx_offset, soffset,
1474 0, 1, 0, true, false);
1475
1476 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
1477 type, "");
1478 }
1479 }
1480 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1481 result = ac_to_integer(&ctx->ac, result);
1482 return result;
1483 }
1484
1485
1486 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1487 {
1488 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1489 ac_build_kill_if_false(&ctx->ac, visible);
1490 }
1491
1492 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1493 enum glsl_interp_mode interp, unsigned location)
1494 {
1495 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1496
1497 switch (interp) {
1498 case INTERP_MODE_FLAT:
1499 default:
1500 return NULL;
1501 case INTERP_MODE_SMOOTH:
1502 case INTERP_MODE_NONE:
1503 if (location == INTERP_CENTER)
1504 return ctx->persp_center;
1505 else if (location == INTERP_CENTROID)
1506 return ctx->persp_centroid;
1507 else if (location == INTERP_SAMPLE)
1508 return ctx->persp_sample;
1509 break;
1510 case INTERP_MODE_NOPERSPECTIVE:
1511 if (location == INTERP_CENTER)
1512 return ctx->linear_center;
1513 else if (location == INTERP_CENTROID)
1514 return ctx->linear_centroid;
1515 else if (location == INTERP_SAMPLE)
1516 return ctx->linear_sample;
1517 break;
1518 }
1519 return NULL;
1520 }
1521
1522 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1523 LLVMValueRef sample_id)
1524 {
1525 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1526
1527 LLVMValueRef result;
1528 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1529
1530 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1531 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1532
1533 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
1534 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1535
1536 return result;
1537 }
1538
1539
1540 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1541 {
1542 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1543 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
1544 ctx->options->key.fs.log2_num_samples :
1545 ctx->options->key.fs.log2_ps_iter_samples;
1546
1547 /* The bit pattern matches that used by fixed function fragment
1548 * processing. */
1549 static const uint16_t ps_iter_masks[] = {
1550 0xffff, /* not used */
1551 0x5555,
1552 0x1111,
1553 0x0101,
1554 0x0001,
1555 };
1556 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1557
1558 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1559
1560 LLVMValueRef result, sample_id;
1561 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1562 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1563 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1564 return result;
1565 }
1566
1567
1568 static void
1569 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1570 {
1571 LLVMValueRef gs_next_vertex;
1572 LLVMValueRef can_emit;
1573 int idx;
1574 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1575
1576 assert(stream == 0);
1577
1578 /* Write vertex attribute values to GSVS ring */
1579 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1580 ctx->gs_next_vertex,
1581 "");
1582
1583 /* If this thread has already emitted the declared maximum number of
1584 * vertices, kill it: excessive vertex emissions are not supposed to
1585 * have any effect, and GS threads have no externally observable
1586 * effects other than emitting vertices.
1587 */
1588 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1589 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1590 ac_build_kill_if_false(&ctx->ac, can_emit);
1591
1592 /* loop num outputs */
1593 idx = 0;
1594 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1595 LLVMValueRef *out_ptr = &addrs[i * 4];
1596 int length = 4;
1597 int slot = idx;
1598 int slot_inc = 1;
1599
1600 if (!(ctx->output_mask & (1ull << i)))
1601 continue;
1602
1603 if (i == VARYING_SLOT_CLIP_DIST0) {
1604 /* pack clip and cull into a single set of slots */
1605 length = ctx->num_output_clips + ctx->num_output_culls;
1606 if (length > 4)
1607 slot_inc = 2;
1608 }
1609 for (unsigned j = 0; j < length; j++) {
1610 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1611 out_ptr[j], "");
1612 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1613 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1614 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1615
1616 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1617
1618 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1619 out_val, 1,
1620 voffset, ctx->gs2vs_offset, 0,
1621 1, 1, true, true);
1622 }
1623 idx += slot_inc;
1624 }
1625
1626 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1627 ctx->ac.i32_1, "");
1628 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1629
1630 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1631 }
1632
1633 static void
1634 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1635 {
1636 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1637 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1638 }
1639
1640 static LLVMValueRef
1641 load_tess_coord(struct ac_shader_abi *abi)
1642 {
1643 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1644
1645 LLVMValueRef coord[4] = {
1646 ctx->tes_u,
1647 ctx->tes_v,
1648 ctx->ac.f32_0,
1649 ctx->ac.f32_0,
1650 };
1651
1652 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1653 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1654 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1655
1656 return ac_build_gather_values(&ctx->ac, coord, 3);
1657 }
1658
1659 static LLVMValueRef
1660 load_patch_vertices_in(struct ac_shader_abi *abi)
1661 {
1662 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1663 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1664 }
1665
1666
1667 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1668 {
1669 return abi->base_vertex;
1670 }
1671
1672 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1673 LLVMValueRef buffer_ptr, bool write)
1674 {
1675 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1676 LLVMValueRef result;
1677
1678 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1679
1680 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1681 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1682
1683 return result;
1684 }
1685
1686 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1687 {
1688 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1689 LLVMValueRef result;
1690
1691 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1692
1693 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1694 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1695
1696 return result;
1697 }
1698
1699 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1700 unsigned descriptor_set,
1701 unsigned base_index,
1702 unsigned constant_index,
1703 LLVMValueRef index,
1704 enum ac_descriptor_type desc_type,
1705 bool image, bool write,
1706 bool bindless)
1707 {
1708 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1709 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1710 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1711 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1712 unsigned offset = binding->offset;
1713 unsigned stride = binding->size;
1714 unsigned type_size;
1715 LLVMBuilderRef builder = ctx->ac.builder;
1716 LLVMTypeRef type;
1717
1718 assert(base_index < layout->binding_count);
1719
1720 switch (desc_type) {
1721 case AC_DESC_IMAGE:
1722 type = ctx->ac.v8i32;
1723 type_size = 32;
1724 break;
1725 case AC_DESC_FMASK:
1726 type = ctx->ac.v8i32;
1727 offset += 32;
1728 type_size = 32;
1729 break;
1730 case AC_DESC_SAMPLER:
1731 type = ctx->ac.v4i32;
1732 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1733 offset += 64;
1734
1735 type_size = 16;
1736 break;
1737 case AC_DESC_BUFFER:
1738 type = ctx->ac.v4i32;
1739 type_size = 16;
1740 break;
1741 default:
1742 unreachable("invalid desc_type\n");
1743 }
1744
1745 offset += constant_index * stride;
1746
1747 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1748 (!index || binding->immutable_samplers_equal)) {
1749 if (binding->immutable_samplers_equal)
1750 constant_index = 0;
1751
1752 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1753
1754 LLVMValueRef constants[] = {
1755 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1756 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1757 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1758 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1759 };
1760 return ac_build_gather_values(&ctx->ac, constants, 4);
1761 }
1762
1763 assert(stride % type_size == 0);
1764
1765 if (!index)
1766 index = ctx->ac.i32_0;
1767
1768 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1769
1770 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1771 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
1772
1773 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1774 }
1775
1776
1777 static void
1778 handle_vs_input_decl(struct radv_shader_context *ctx,
1779 struct nir_variable *variable)
1780 {
1781 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1782 LLVMValueRef t_offset;
1783 LLVMValueRef t_list;
1784 LLVMValueRef input;
1785 LLVMValueRef buffer_index;
1786 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
1787 int idx = variable->data.location;
1788 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1789 uint8_t input_usage_mask =
1790 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1791 unsigned num_channels = util_last_bit(input_usage_mask);
1792
1793 variable->data.driver_location = idx * 4;
1794
1795 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
1796 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
1797 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
1798 ctx->abi.start_instance, "");
1799 if (ctx->options->key.vs.as_ls) {
1800 ctx->shader_info->vs.vgpr_comp_cnt =
1801 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1802 } else {
1803 ctx->shader_info->vs.vgpr_comp_cnt =
1804 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1805 }
1806 } else
1807 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
1808 ctx->abi.base_vertex, "");
1809 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
1810
1811 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1812
1813 input = ac_build_buffer_load_format(&ctx->ac, t_list,
1814 buffer_index,
1815 ctx->ac.i32_0,
1816 num_channels, false, true);
1817
1818 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
1819
1820 for (unsigned chan = 0; chan < 4; chan++) {
1821 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1822 ctx->inputs[ac_llvm_reg_index_soa(idx, chan)] =
1823 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
1824 input, llvm_chan, ""));
1825 }
1826 }
1827 }
1828
1829 static void interp_fs_input(struct radv_shader_context *ctx,
1830 unsigned attr,
1831 LLVMValueRef interp_param,
1832 LLVMValueRef prim_mask,
1833 LLVMValueRef result[4])
1834 {
1835 LLVMValueRef attr_number;
1836 unsigned chan;
1837 LLVMValueRef i, j;
1838 bool interp = interp_param != NULL;
1839
1840 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
1841
1842 /* fs.constant returns the param from the middle vertex, so it's not
1843 * really useful for flat shading. It's meant to be used for custom
1844 * interpolation (but the intrinsic can't fetch from the other two
1845 * vertices).
1846 *
1847 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1848 * to do the right thing. The only reason we use fs.constant is that
1849 * fs.interp cannot be used on integers, because they can be equal
1850 * to NaN.
1851 */
1852 if (interp) {
1853 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1854 ctx->ac.v2f32, "");
1855
1856 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1857 ctx->ac.i32_0, "");
1858 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1859 ctx->ac.i32_1, "");
1860 }
1861
1862 for (chan = 0; chan < 4; chan++) {
1863 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1864
1865 if (interp) {
1866 result[chan] = ac_build_fs_interp(&ctx->ac,
1867 llvm_chan,
1868 attr_number,
1869 prim_mask, i, j);
1870 } else {
1871 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1872 LLVMConstInt(ctx->ac.i32, 2, false),
1873 llvm_chan,
1874 attr_number,
1875 prim_mask);
1876 }
1877 }
1878 }
1879
1880 static void
1881 handle_fs_input_decl(struct radv_shader_context *ctx,
1882 struct nir_variable *variable)
1883 {
1884 int idx = variable->data.location;
1885 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1886 LLVMValueRef interp;
1887
1888 variable->data.driver_location = idx * 4;
1889 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
1890
1891 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
1892 unsigned interp_type;
1893 if (variable->data.sample)
1894 interp_type = INTERP_SAMPLE;
1895 else if (variable->data.centroid)
1896 interp_type = INTERP_CENTROID;
1897 else
1898 interp_type = INTERP_CENTER;
1899
1900 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
1901 } else
1902 interp = NULL;
1903
1904 for (unsigned i = 0; i < attrib_count; ++i)
1905 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
1906
1907 }
1908
1909 static void
1910 handle_vs_inputs(struct radv_shader_context *ctx,
1911 struct nir_shader *nir) {
1912 nir_foreach_variable(variable, &nir->inputs)
1913 handle_vs_input_decl(ctx, variable);
1914 }
1915
1916 static void
1917 prepare_interp_optimize(struct radv_shader_context *ctx,
1918 struct nir_shader *nir)
1919 {
1920 if (!ctx->options->key.fs.multisample)
1921 return;
1922
1923 bool uses_center = false;
1924 bool uses_centroid = false;
1925 nir_foreach_variable(variable, &nir->inputs) {
1926 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1927 variable->data.sample)
1928 continue;
1929
1930 if (variable->data.centroid)
1931 uses_centroid = true;
1932 else
1933 uses_center = true;
1934 }
1935
1936 if (uses_center && uses_centroid) {
1937 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
1938 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
1939 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
1940 }
1941 }
1942
1943 static void
1944 handle_fs_inputs(struct radv_shader_context *ctx,
1945 struct nir_shader *nir)
1946 {
1947 prepare_interp_optimize(ctx, nir);
1948
1949 nir_foreach_variable(variable, &nir->inputs)
1950 handle_fs_input_decl(ctx, variable);
1951
1952 unsigned index = 0;
1953
1954 if (ctx->shader_info->info.ps.uses_input_attachments ||
1955 ctx->shader_info->info.needs_multiview_view_index)
1956 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
1957
1958 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
1959 LLVMValueRef interp_param;
1960 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
1961
1962 if (!(ctx->input_mask & (1ull << i)))
1963 continue;
1964
1965 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
1966 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
1967 interp_param = *inputs;
1968 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
1969 inputs);
1970
1971 if (!interp_param)
1972 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
1973 ++index;
1974 } else if (i == VARYING_SLOT_POS) {
1975 for(int i = 0; i < 3; ++i)
1976 inputs[i] = ctx->abi.frag_pos[i];
1977
1978 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
1979 ctx->abi.frag_pos[3]);
1980 }
1981 }
1982 ctx->shader_info->fs.num_interp = index;
1983 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
1984
1985 if (ctx->shader_info->info.needs_multiview_view_index)
1986 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
1987 }
1988
1989 static void
1990 scan_shader_output_decl(struct radv_shader_context *ctx,
1991 struct nir_variable *variable,
1992 struct nir_shader *shader,
1993 gl_shader_stage stage)
1994 {
1995 int idx = variable->data.location + variable->data.index;
1996 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1997 uint64_t mask_attribs;
1998
1999 variable->data.driver_location = idx * 4;
2000
2001 /* tess ctrl has it's own load/store paths for outputs */
2002 if (stage == MESA_SHADER_TESS_CTRL)
2003 return;
2004
2005 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2006 if (stage == MESA_SHADER_VERTEX ||
2007 stage == MESA_SHADER_TESS_EVAL ||
2008 stage == MESA_SHADER_GEOMETRY) {
2009 if (idx == VARYING_SLOT_CLIP_DIST0) {
2010 int length = shader->info.clip_distance_array_size +
2011 shader->info.cull_distance_array_size;
2012 if (stage == MESA_SHADER_VERTEX) {
2013 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2014 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2015 }
2016 if (stage == MESA_SHADER_TESS_EVAL) {
2017 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2018 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2019 }
2020
2021 if (length > 4)
2022 attrib_count = 2;
2023 else
2024 attrib_count = 1;
2025 mask_attribs = 1ull << idx;
2026 }
2027 }
2028
2029 ctx->output_mask |= mask_attribs;
2030 }
2031
2032
2033 /* Initialize arguments for the shader export intrinsic */
2034 static void
2035 si_llvm_init_export_args(struct radv_shader_context *ctx,
2036 LLVMValueRef *values,
2037 unsigned enabled_channels,
2038 unsigned target,
2039 struct ac_export_args *args)
2040 {
2041 /* Specify the channels that are enabled. */
2042 args->enabled_channels = enabled_channels;
2043
2044 /* Specify whether the EXEC mask represents the valid mask */
2045 args->valid_mask = 0;
2046
2047 /* Specify whether this is the last export */
2048 args->done = 0;
2049
2050 /* Specify the target we are exporting */
2051 args->target = target;
2052
2053 args->compr = false;
2054 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2055 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2056 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2057 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2058
2059 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2060 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2061 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2062 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2063 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2064 unsigned chan;
2065
2066 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2067 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2068 unsigned bits, bool hi) = NULL;
2069
2070 switch(col_format) {
2071 case V_028714_SPI_SHADER_ZERO:
2072 args->enabled_channels = 0; /* writemask */
2073 args->target = V_008DFC_SQ_EXP_NULL;
2074 break;
2075
2076 case V_028714_SPI_SHADER_32_R:
2077 args->enabled_channels = 1;
2078 args->out[0] = values[0];
2079 break;
2080
2081 case V_028714_SPI_SHADER_32_GR:
2082 args->enabled_channels = 0x3;
2083 args->out[0] = values[0];
2084 args->out[1] = values[1];
2085 break;
2086
2087 case V_028714_SPI_SHADER_32_AR:
2088 args->enabled_channels = 0x9;
2089 args->out[0] = values[0];
2090 args->out[3] = values[3];
2091 break;
2092
2093 case V_028714_SPI_SHADER_FP16_ABGR:
2094 args->enabled_channels = 0x5;
2095 packf = ac_build_cvt_pkrtz_f16;
2096 break;
2097
2098 case V_028714_SPI_SHADER_UNORM16_ABGR:
2099 args->enabled_channels = 0x5;
2100 packf = ac_build_cvt_pknorm_u16;
2101 break;
2102
2103 case V_028714_SPI_SHADER_SNORM16_ABGR:
2104 args->enabled_channels = 0x5;
2105 packf = ac_build_cvt_pknorm_i16;
2106 break;
2107
2108 case V_028714_SPI_SHADER_UINT16_ABGR:
2109 args->enabled_channels = 0x5;
2110 packi = ac_build_cvt_pk_u16;
2111 break;
2112
2113 case V_028714_SPI_SHADER_SINT16_ABGR:
2114 args->enabled_channels = 0x5;
2115 packi = ac_build_cvt_pk_i16;
2116 break;
2117
2118 default:
2119 case V_028714_SPI_SHADER_32_ABGR:
2120 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2121 break;
2122 }
2123
2124 /* Pack f16 or norm_i16/u16. */
2125 if (packf) {
2126 for (chan = 0; chan < 2; chan++) {
2127 LLVMValueRef pack_args[2] = {
2128 values[2 * chan],
2129 values[2 * chan + 1]
2130 };
2131 LLVMValueRef packed;
2132
2133 packed = packf(&ctx->ac, pack_args);
2134 args->out[chan] = ac_to_float(&ctx->ac, packed);
2135 }
2136 args->compr = 1; /* COMPR flag */
2137 }
2138
2139 /* Pack i16/u16. */
2140 if (packi) {
2141 for (chan = 0; chan < 2; chan++) {
2142 LLVMValueRef pack_args[2] = {
2143 ac_to_integer(&ctx->ac, values[2 * chan]),
2144 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2145 };
2146 LLVMValueRef packed;
2147
2148 packed = packi(&ctx->ac, pack_args,
2149 is_int8 ? 8 : is_int10 ? 10 : 16,
2150 chan == 1);
2151 args->out[chan] = ac_to_float(&ctx->ac, packed);
2152 }
2153 args->compr = 1; /* COMPR flag */
2154 }
2155 return;
2156 }
2157
2158 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2159
2160 for (unsigned i = 0; i < 4; ++i) {
2161 if (!(args->enabled_channels & (1 << i)))
2162 continue;
2163
2164 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2165 }
2166 }
2167
2168 static void
2169 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2170 LLVMValueRef *values, unsigned enabled_channels)
2171 {
2172 struct ac_export_args args;
2173
2174 si_llvm_init_export_args(ctx, values, enabled_channels,
2175 V_008DFC_SQ_EXP_PARAM + index, &args);
2176 ac_build_export(&ctx->ac, &args);
2177 }
2178
2179 static LLVMValueRef
2180 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2181 {
2182 LLVMValueRef output =
2183 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2184
2185 return LLVMBuildLoad(ctx->ac.builder, output, "");
2186 }
2187
2188 static void
2189 handle_vs_outputs_post(struct radv_shader_context *ctx,
2190 bool export_prim_id, bool export_layer_id,
2191 struct radv_vs_output_info *outinfo)
2192 {
2193 uint32_t param_count = 0;
2194 unsigned target;
2195 unsigned pos_idx, num_pos_exports = 0;
2196 struct ac_export_args args, pos_args[4] = {};
2197 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2198 int i;
2199
2200 if (ctx->options->key.has_multiview_view_index) {
2201 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2202 if(!*tmp_out) {
2203 for(unsigned i = 0; i < 4; ++i)
2204 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2205 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2206 }
2207
2208 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2209 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2210 }
2211
2212 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2213 sizeof(outinfo->vs_output_param_offset));
2214
2215 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2216 LLVMValueRef slots[8];
2217 unsigned j;
2218
2219 if (outinfo->cull_dist_mask)
2220 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2221
2222 i = VARYING_SLOT_CLIP_DIST0;
2223 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
2224 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2225
2226 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
2227 slots[i] = LLVMGetUndef(ctx->ac.f32);
2228
2229 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
2230 target = V_008DFC_SQ_EXP_POS + 3;
2231 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2232 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2233 &args, sizeof(args));
2234 }
2235
2236 target = V_008DFC_SQ_EXP_POS + 2;
2237 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2238 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2239 &args, sizeof(args));
2240
2241 }
2242
2243 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2244 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2245 for (unsigned j = 0; j < 4; j++)
2246 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2247 }
2248 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2249
2250 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2251 outinfo->writes_pointsize = true;
2252 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2253 }
2254
2255 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2256 outinfo->writes_layer = true;
2257 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2258 }
2259
2260 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2261 outinfo->writes_viewport_index = true;
2262 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2263 }
2264
2265 if (outinfo->writes_pointsize ||
2266 outinfo->writes_layer ||
2267 outinfo->writes_viewport_index) {
2268 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2269 (outinfo->writes_layer == true ? 4 : 0));
2270 pos_args[1].valid_mask = 0;
2271 pos_args[1].done = 0;
2272 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2273 pos_args[1].compr = 0;
2274 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2275 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2276 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2277 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2278
2279 if (outinfo->writes_pointsize == true)
2280 pos_args[1].out[0] = psize_value;
2281 if (outinfo->writes_layer == true)
2282 pos_args[1].out[2] = layer_value;
2283 if (outinfo->writes_viewport_index == true) {
2284 if (ctx->options->chip_class >= GFX9) {
2285 /* GFX9 has the layer in out.z[10:0] and the viewport
2286 * index in out.z[19:16].
2287 */
2288 LLVMValueRef v = viewport_index_value;
2289 v = ac_to_integer(&ctx->ac, v);
2290 v = LLVMBuildShl(ctx->ac.builder, v,
2291 LLVMConstInt(ctx->ac.i32, 16, false),
2292 "");
2293 v = LLVMBuildOr(ctx->ac.builder, v,
2294 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2295
2296 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2297 pos_args[1].enabled_channels |= 1 << 2;
2298 } else {
2299 pos_args[1].out[3] = viewport_index_value;
2300 pos_args[1].enabled_channels |= 1 << 3;
2301 }
2302 }
2303 }
2304 for (i = 0; i < 4; i++) {
2305 if (pos_args[i].out[0])
2306 num_pos_exports++;
2307 }
2308
2309 pos_idx = 0;
2310 for (i = 0; i < 4; i++) {
2311 if (!pos_args[i].out[0])
2312 continue;
2313
2314 /* Specify the target we are exporting */
2315 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2316 if (pos_idx == num_pos_exports)
2317 pos_args[i].done = 1;
2318 ac_build_export(&ctx->ac, &pos_args[i]);
2319 }
2320
2321 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2322 LLVMValueRef values[4];
2323 if (!(ctx->output_mask & (1ull << i)))
2324 continue;
2325
2326 if (i != VARYING_SLOT_LAYER &&
2327 i != VARYING_SLOT_PRIMITIVE_ID &&
2328 i < VARYING_SLOT_VAR0)
2329 continue;
2330
2331 for (unsigned j = 0; j < 4; j++)
2332 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2333
2334 unsigned output_usage_mask;
2335
2336 if (ctx->stage == MESA_SHADER_VERTEX &&
2337 !ctx->is_gs_copy_shader) {
2338 output_usage_mask =
2339 ctx->shader_info->info.vs.output_usage_mask[i];
2340 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2341 output_usage_mask =
2342 ctx->shader_info->info.tes.output_usage_mask[i];
2343 } else {
2344 /* Enable all channels for the GS copy shader because
2345 * we don't know the output usage mask currently.
2346 */
2347 output_usage_mask = 0xf;
2348 }
2349
2350 radv_export_param(ctx, param_count, values, output_usage_mask);
2351
2352 outinfo->vs_output_param_offset[i] = param_count++;
2353 }
2354
2355 if (export_prim_id) {
2356 LLVMValueRef values[4];
2357
2358 values[0] = ctx->vs_prim_id;
2359 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2360 ctx->shader_info->vs.vgpr_comp_cnt);
2361 for (unsigned j = 1; j < 4; j++)
2362 values[j] = ctx->ac.f32_0;
2363
2364 radv_export_param(ctx, param_count, values, 0x1);
2365
2366 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2367 outinfo->export_prim_id = true;
2368 }
2369
2370 if (export_layer_id && layer_value) {
2371 LLVMValueRef values[4];
2372
2373 values[0] = layer_value;
2374 for (unsigned j = 1; j < 4; j++)
2375 values[j] = ctx->ac.f32_0;
2376
2377 radv_export_param(ctx, param_count, values, 0x1);
2378
2379 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2380 }
2381
2382 outinfo->pos_exports = num_pos_exports;
2383 outinfo->param_exports = param_count;
2384 }
2385
2386 static void
2387 handle_es_outputs_post(struct radv_shader_context *ctx,
2388 struct radv_es_output_info *outinfo)
2389 {
2390 int j;
2391 uint64_t max_output_written = 0;
2392 LLVMValueRef lds_base = NULL;
2393
2394 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2395 int param_index;
2396 int length = 4;
2397
2398 if (!(ctx->output_mask & (1ull << i)))
2399 continue;
2400
2401 if (i == VARYING_SLOT_CLIP_DIST0)
2402 length = ctx->num_output_clips + ctx->num_output_culls;
2403
2404 param_index = shader_io_get_unique_index(i);
2405
2406 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2407 }
2408
2409 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2410
2411 if (ctx->ac.chip_class >= GFX9) {
2412 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2413 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2414 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2415 LLVMConstInt(ctx->ac.i32, 24, false),
2416 LLVMConstInt(ctx->ac.i32, 4, false), false);
2417 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2418 LLVMBuildMul(ctx->ac.builder, wave_idx,
2419 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2420 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2421 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2422 }
2423
2424 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2425 LLVMValueRef dw_addr = NULL;
2426 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2427 int param_index;
2428 int length = 4;
2429
2430 if (!(ctx->output_mask & (1ull << i)))
2431 continue;
2432
2433 if (i == VARYING_SLOT_CLIP_DIST0)
2434 length = ctx->num_output_clips + ctx->num_output_culls;
2435
2436 param_index = shader_io_get_unique_index(i);
2437
2438 if (lds_base) {
2439 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2440 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2441 "");
2442 }
2443 for (j = 0; j < length; j++) {
2444 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2445 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2446
2447 if (ctx->ac.chip_class >= GFX9) {
2448 ac_lds_store(&ctx->ac, dw_addr,
2449 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2450 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2451 } else {
2452 ac_build_buffer_store_dword(&ctx->ac,
2453 ctx->esgs_ring,
2454 out_val, 1,
2455 NULL, ctx->es2gs_offset,
2456 (4 * param_index + j) * 4,
2457 1, 1, true, true);
2458 }
2459 }
2460 }
2461 }
2462
2463 static void
2464 handle_ls_outputs_post(struct radv_shader_context *ctx)
2465 {
2466 LLVMValueRef vertex_id = ctx->rel_auto_id;
2467 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2468 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2469 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2470 vertex_dw_stride, "");
2471
2472 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2473 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2474 int length = 4;
2475
2476 if (!(ctx->output_mask & (1ull << i)))
2477 continue;
2478
2479 if (i == VARYING_SLOT_CLIP_DIST0)
2480 length = ctx->num_output_clips + ctx->num_output_culls;
2481 int param = shader_io_get_unique_index(i);
2482 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2483 LLVMConstInt(ctx->ac.i32, param * 4, false),
2484 "");
2485 for (unsigned j = 0; j < length; j++) {
2486 ac_lds_store(&ctx->ac, dw_addr,
2487 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2488 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2489 }
2490 }
2491 }
2492
2493 struct ac_build_if_state
2494 {
2495 struct radv_shader_context *ctx;
2496 LLVMValueRef condition;
2497 LLVMBasicBlockRef entry_block;
2498 LLVMBasicBlockRef true_block;
2499 LLVMBasicBlockRef false_block;
2500 LLVMBasicBlockRef merge_block;
2501 };
2502
2503 static LLVMBasicBlockRef
2504 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
2505 {
2506 LLVMBasicBlockRef current_block;
2507 LLVMBasicBlockRef next_block;
2508 LLVMBasicBlockRef new_block;
2509
2510 /* get current basic block */
2511 current_block = LLVMGetInsertBlock(ctx->ac.builder);
2512
2513 /* chqeck if there's another block after this one */
2514 next_block = LLVMGetNextBasicBlock(current_block);
2515 if (next_block) {
2516 /* insert the new block before the next block */
2517 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
2518 }
2519 else {
2520 /* append new block after current block */
2521 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
2522 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
2523 }
2524 return new_block;
2525 }
2526
2527 static void
2528 ac_nir_build_if(struct ac_build_if_state *ifthen,
2529 struct radv_shader_context *ctx,
2530 LLVMValueRef condition)
2531 {
2532 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
2533
2534 memset(ifthen, 0, sizeof *ifthen);
2535 ifthen->ctx = ctx;
2536 ifthen->condition = condition;
2537 ifthen->entry_block = block;
2538
2539 /* create endif/merge basic block for the phi functions */
2540 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
2541
2542 /* create/insert true_block before merge_block */
2543 ifthen->true_block =
2544 LLVMInsertBasicBlockInContext(ctx->context,
2545 ifthen->merge_block,
2546 "if-true-block");
2547
2548 /* successive code goes into the true block */
2549 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
2550 }
2551
2552 /**
2553 * End a conditional.
2554 */
2555 static void
2556 ac_nir_build_endif(struct ac_build_if_state *ifthen)
2557 {
2558 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
2559
2560 /* Insert branch to the merge block from current block */
2561 LLVMBuildBr(builder, ifthen->merge_block);
2562
2563 /*
2564 * Now patch in the various branch instructions.
2565 */
2566
2567 /* Insert the conditional branch instruction at the end of entry_block */
2568 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
2569 if (ifthen->false_block) {
2570 /* we have an else clause */
2571 LLVMBuildCondBr(builder, ifthen->condition,
2572 ifthen->true_block, ifthen->false_block);
2573 }
2574 else {
2575 /* no else clause */
2576 LLVMBuildCondBr(builder, ifthen->condition,
2577 ifthen->true_block, ifthen->merge_block);
2578 }
2579
2580 /* Resume building code at end of the ifthen->merge_block */
2581 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
2582 }
2583
2584 static void
2585 write_tess_factors(struct radv_shader_context *ctx)
2586 {
2587 unsigned stride, outer_comps, inner_comps;
2588 struct ac_build_if_state if_ctx, inner_if_ctx;
2589 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2590 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2591 unsigned tess_inner_index = 0, tess_outer_index;
2592 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2593 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2594 int i;
2595 ac_emit_barrier(&ctx->ac, ctx->stage);
2596
2597 switch (ctx->options->key.tcs.primitive_mode) {
2598 case GL_ISOLINES:
2599 stride = 2;
2600 outer_comps = 2;
2601 inner_comps = 0;
2602 break;
2603 case GL_TRIANGLES:
2604 stride = 4;
2605 outer_comps = 3;
2606 inner_comps = 1;
2607 break;
2608 case GL_QUADS:
2609 stride = 6;
2610 outer_comps = 4;
2611 inner_comps = 2;
2612 break;
2613 default:
2614 return;
2615 }
2616
2617 ac_nir_build_if(&if_ctx, ctx,
2618 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2619 invocation_id, ctx->ac.i32_0, ""));
2620
2621 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2622
2623 if (inner_comps) {
2624 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2625 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2626 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2627 }
2628
2629 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2630 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2631 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2632
2633 for (i = 0; i < 4; i++) {
2634 inner[i] = LLVMGetUndef(ctx->ac.i32);
2635 outer[i] = LLVMGetUndef(ctx->ac.i32);
2636 }
2637
2638 // LINES reverseal
2639 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2640 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2641 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2642 ctx->ac.i32_1, "");
2643 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2644 } else {
2645 for (i = 0; i < outer_comps; i++) {
2646 outer[i] = out[i] =
2647 ac_lds_load(&ctx->ac, lds_outer);
2648 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2649 ctx->ac.i32_1, "");
2650 }
2651 for (i = 0; i < inner_comps; i++) {
2652 inner[i] = out[outer_comps+i] =
2653 ac_lds_load(&ctx->ac, lds_inner);
2654 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2655 ctx->ac.i32_1, "");
2656 }
2657 }
2658
2659 /* Convert the outputs to vectors for stores. */
2660 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2661 vec1 = NULL;
2662
2663 if (stride > 4)
2664 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2665
2666
2667 buffer = ctx->hs_ring_tess_factor;
2668 tf_base = ctx->tess_factor_offset;
2669 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2670 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2671 unsigned tf_offset = 0;
2672
2673 if (ctx->options->chip_class <= VI) {
2674 ac_nir_build_if(&inner_if_ctx, ctx,
2675 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2676 rel_patch_id, ctx->ac.i32_0, ""));
2677
2678 /* Store the dynamic HS control word. */
2679 ac_build_buffer_store_dword(&ctx->ac, buffer,
2680 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2681 1, ctx->ac.i32_0, tf_base,
2682 0, 1, 0, true, false);
2683 tf_offset += 4;
2684
2685 ac_nir_build_endif(&inner_if_ctx);
2686 }
2687
2688 /* Store the tessellation factors. */
2689 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2690 MIN2(stride, 4), byteoffset, tf_base,
2691 tf_offset, 1, 0, true, false);
2692 if (vec1)
2693 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2694 stride - 4, byteoffset, tf_base,
2695 16 + tf_offset, 1, 0, true, false);
2696
2697 //store to offchip for TES to read - only if TES reads them
2698 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2699 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2700 LLVMValueRef tf_inner_offset;
2701 unsigned param_outer, param_inner;
2702
2703 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2704 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2705 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2706
2707 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2708 util_next_power_of_two(outer_comps));
2709
2710 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2711 outer_comps, tf_outer_offset,
2712 ctx->oc_lds, 0, 1, 0, true, false);
2713 if (inner_comps) {
2714 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2715 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2716 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2717
2718 inner_vec = inner_comps == 1 ? inner[0] :
2719 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2720 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2721 inner_comps, tf_inner_offset,
2722 ctx->oc_lds, 0, 1, 0, true, false);
2723 }
2724 }
2725 ac_nir_build_endif(&if_ctx);
2726 }
2727
2728 static void
2729 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2730 {
2731 write_tess_factors(ctx);
2732 }
2733
2734 static bool
2735 si_export_mrt_color(struct radv_shader_context *ctx,
2736 LLVMValueRef *color, unsigned index,
2737 struct ac_export_args *args)
2738 {
2739 /* Export */
2740 si_llvm_init_export_args(ctx, color, 0xf,
2741 V_008DFC_SQ_EXP_MRT + index, args);
2742 if (!args->enabled_channels)
2743 return false; /* unnecessary NULL export */
2744
2745 return true;
2746 }
2747
2748 static void
2749 radv_export_mrt_z(struct radv_shader_context *ctx,
2750 LLVMValueRef depth, LLVMValueRef stencil,
2751 LLVMValueRef samplemask)
2752 {
2753 struct ac_export_args args;
2754
2755 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2756
2757 ac_build_export(&ctx->ac, &args);
2758 }
2759
2760 static void
2761 handle_fs_outputs_post(struct radv_shader_context *ctx)
2762 {
2763 unsigned index = 0;
2764 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2765 struct ac_export_args color_args[8];
2766
2767 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2768 LLVMValueRef values[4];
2769
2770 if (!(ctx->output_mask & (1ull << i)))
2771 continue;
2772
2773 if (i < FRAG_RESULT_DATA0)
2774 continue;
2775
2776 for (unsigned j = 0; j < 4; j++)
2777 values[j] = ac_to_float(&ctx->ac,
2778 radv_load_output(ctx, i, j));
2779
2780 bool ret = si_export_mrt_color(ctx, values,
2781 i - FRAG_RESULT_DATA0,
2782 &color_args[index]);
2783 if (ret)
2784 index++;
2785 }
2786
2787 /* Process depth, stencil, samplemask. */
2788 if (ctx->shader_info->info.ps.writes_z) {
2789 depth = ac_to_float(&ctx->ac,
2790 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
2791 }
2792 if (ctx->shader_info->info.ps.writes_stencil) {
2793 stencil = ac_to_float(&ctx->ac,
2794 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
2795 }
2796 if (ctx->shader_info->info.ps.writes_sample_mask) {
2797 samplemask = ac_to_float(&ctx->ac,
2798 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
2799 }
2800
2801 /* Set the DONE bit on last non-null color export only if Z isn't
2802 * exported.
2803 */
2804 if (index > 0 &&
2805 !ctx->shader_info->info.ps.writes_z &&
2806 !ctx->shader_info->info.ps.writes_stencil &&
2807 !ctx->shader_info->info.ps.writes_sample_mask) {
2808 unsigned last = index - 1;
2809
2810 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
2811 color_args[last].done = 1; /* DONE bit */
2812 }
2813
2814 /* Export PS outputs. */
2815 for (unsigned i = 0; i < index; i++)
2816 ac_build_export(&ctx->ac, &color_args[i]);
2817
2818 if (depth || stencil || samplemask)
2819 radv_export_mrt_z(ctx, depth, stencil, samplemask);
2820 else if (!index)
2821 ac_build_export_null(&ctx->ac);
2822 }
2823
2824 static void
2825 emit_gs_epilogue(struct radv_shader_context *ctx)
2826 {
2827 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
2828 }
2829
2830 static void
2831 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
2832 LLVMValueRef *addrs)
2833 {
2834 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2835
2836 switch (ctx->stage) {
2837 case MESA_SHADER_VERTEX:
2838 if (ctx->options->key.vs.as_ls)
2839 handle_ls_outputs_post(ctx);
2840 else if (ctx->options->key.vs.as_es)
2841 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
2842 else
2843 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
2844 ctx->options->key.vs.export_layer_id,
2845 &ctx->shader_info->vs.outinfo);
2846 break;
2847 case MESA_SHADER_FRAGMENT:
2848 handle_fs_outputs_post(ctx);
2849 break;
2850 case MESA_SHADER_GEOMETRY:
2851 emit_gs_epilogue(ctx);
2852 break;
2853 case MESA_SHADER_TESS_CTRL:
2854 handle_tcs_outputs_post(ctx);
2855 break;
2856 case MESA_SHADER_TESS_EVAL:
2857 if (ctx->options->key.tes.as_es)
2858 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
2859 else
2860 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
2861 ctx->options->key.tes.export_layer_id,
2862 &ctx->shader_info->tes.outinfo);
2863 break;
2864 default:
2865 break;
2866 }
2867 }
2868
2869 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
2870 {
2871 LLVMPassManagerRef passmgr;
2872 /* Create the pass manager */
2873 passmgr = LLVMCreateFunctionPassManagerForModule(
2874 ctx->ac.module);
2875
2876 /* This pass should eliminate all the load and store instructions */
2877 LLVMAddPromoteMemoryToRegisterPass(passmgr);
2878
2879 /* Add some optimization passes */
2880 LLVMAddScalarReplAggregatesPass(passmgr);
2881 LLVMAddLICMPass(passmgr);
2882 LLVMAddAggressiveDCEPass(passmgr);
2883 LLVMAddCFGSimplificationPass(passmgr);
2884 LLVMAddInstructionCombiningPass(passmgr);
2885
2886 /* Run the pass */
2887 LLVMInitializeFunctionPassManager(passmgr);
2888 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
2889 LLVMFinalizeFunctionPassManager(passmgr);
2890
2891 LLVMDisposeBuilder(ctx->ac.builder);
2892 LLVMDisposePassManager(passmgr);
2893
2894 ac_llvm_context_dispose(&ctx->ac);
2895 }
2896
2897 static void
2898 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
2899 {
2900 struct radv_vs_output_info *outinfo;
2901
2902 switch (ctx->stage) {
2903 case MESA_SHADER_FRAGMENT:
2904 case MESA_SHADER_COMPUTE:
2905 case MESA_SHADER_TESS_CTRL:
2906 case MESA_SHADER_GEOMETRY:
2907 return;
2908 case MESA_SHADER_VERTEX:
2909 if (ctx->options->key.vs.as_ls ||
2910 ctx->options->key.vs.as_es)
2911 return;
2912 outinfo = &ctx->shader_info->vs.outinfo;
2913 break;
2914 case MESA_SHADER_TESS_EVAL:
2915 if (ctx->options->key.vs.as_es)
2916 return;
2917 outinfo = &ctx->shader_info->tes.outinfo;
2918 break;
2919 default:
2920 unreachable("Unhandled shader type");
2921 }
2922
2923 ac_optimize_vs_outputs(&ctx->ac,
2924 ctx->main_function,
2925 outinfo->vs_output_param_offset,
2926 VARYING_SLOT_MAX,
2927 &outinfo->param_exports);
2928 }
2929
2930 static void
2931 ac_setup_rings(struct radv_shader_context *ctx)
2932 {
2933 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
2934 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
2935 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
2936 }
2937
2938 if (ctx->is_gs_copy_shader) {
2939 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
2940 }
2941 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2942 LLVMValueRef tmp;
2943 uint32_t num_entries = 64;
2944 LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size, false);
2945 LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size << 16, false);
2946 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
2947 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
2948
2949 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
2950
2951 tmp = LLVMConstInt(ctx->ac.i32, num_entries, false);
2952 if (ctx->options->chip_class >= VI)
2953 tmp = LLVMBuildMul(ctx->ac.builder, gsvs_ring_stride, tmp, "");
2954 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
2955 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
2956 tmp = LLVMBuildOr(ctx->ac.builder, tmp, gsvs_ring_desc, "");
2957 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
2958 }
2959
2960 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
2961 ctx->stage == MESA_SHADER_TESS_EVAL) {
2962 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
2963 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
2964 }
2965 }
2966
2967 static unsigned
2968 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
2969 const struct nir_shader *nir)
2970 {
2971 switch (nir->info.stage) {
2972 case MESA_SHADER_TESS_CTRL:
2973 return chip_class >= CIK ? 128 : 64;
2974 case MESA_SHADER_GEOMETRY:
2975 return chip_class >= GFX9 ? 128 : 64;
2976 case MESA_SHADER_COMPUTE:
2977 break;
2978 default:
2979 return 0;
2980 }
2981
2982 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
2983 nir->info.cs.local_size[1] *
2984 nir->info.cs.local_size[2];
2985 return max_workgroup_size;
2986 }
2987
2988 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
2989 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
2990 {
2991 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2992 LLVMConstInt(ctx->ac.i32, 8, false),
2993 LLVMConstInt(ctx->ac.i32, 8, false), false);
2994 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
2995 ctx->ac.i32_0, "");
2996 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
2997 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
2998 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
2999 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3000 }
3001
3002 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3003 {
3004 for(int i = 5; i >= 0; --i) {
3005 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3006 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
3007 LLVMConstInt(ctx->ac.i32, 16, false), false);
3008 }
3009
3010 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3011 LLVMConstInt(ctx->ac.i32, 16, false),
3012 LLVMConstInt(ctx->ac.i32, 8, false), false);
3013 }
3014
3015
3016 static
3017 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
3018 struct nir_shader *const *shaders,
3019 int shader_count,
3020 struct radv_shader_variant_info *shader_info,
3021 const struct radv_nir_compiler_options *options)
3022 {
3023 struct radv_shader_context ctx = {0};
3024 unsigned i;
3025 ctx.options = options;
3026 ctx.shader_info = shader_info;
3027 ctx.context = LLVMContextCreate();
3028
3029 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3030 options->family);
3031 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3032 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
3033
3034 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
3035 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
3036 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
3037 LLVMDisposeTargetData(data_layout);
3038 LLVMDisposeMessage(data_layout_str);
3039
3040 enum ac_float_mode float_mode =
3041 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3042 AC_FLOAT_MODE_DEFAULT;
3043
3044 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3045
3046 memset(shader_info, 0, sizeof(*shader_info));
3047
3048 for(int i = 0; i < shader_count; ++i)
3049 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3050
3051 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3052 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3053 for (i = 0; i < AC_UD_MAX_UD; i++)
3054 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3055
3056 ctx.max_workgroup_size = 0;
3057 for (int i = 0; i < shader_count; ++i) {
3058 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3059 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3060 shaders[i]));
3061 }
3062
3063 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3064 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3065
3066 ctx.abi.inputs = &ctx.inputs[0];
3067 ctx.abi.emit_outputs = handle_shader_outputs_post;
3068 ctx.abi.emit_vertex = visit_emit_vertex;
3069 ctx.abi.load_ubo = radv_load_ubo;
3070 ctx.abi.load_ssbo = radv_load_ssbo;
3071 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3072 ctx.abi.load_resource = radv_load_resource;
3073 ctx.abi.clamp_shadow_reference = false;
3074 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9;
3075
3076 if (shader_count >= 2)
3077 ac_init_exec_full_mask(&ctx.ac);
3078
3079 if (ctx.ac.chip_class == GFX9 &&
3080 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3081 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3082
3083 for(int i = 0; i < shader_count; ++i) {
3084 ctx.stage = shaders[i]->info.stage;
3085 ctx.output_mask = 0;
3086 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3087 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3088
3089 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3090 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3091 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3092 ctx.abi.load_inputs = load_gs_input;
3093 ctx.abi.emit_primitive = visit_end_primitive;
3094 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3095 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3096 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3097 ctx.abi.load_tess_varyings = load_tcs_varyings;
3098 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3099 ctx.abi.store_tcs_outputs = store_tcs_output;
3100 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3101 if (shader_count == 1)
3102 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3103 else
3104 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3105 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3106 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3107 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3108 ctx.abi.load_tess_varyings = load_tes_input;
3109 ctx.abi.load_tess_coord = load_tess_coord;
3110 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3111 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3112 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3113 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3114 if (shader_info->info.vs.needs_instance_id) {
3115 if (ctx.options->key.vs.as_ls) {
3116 ctx.shader_info->vs.vgpr_comp_cnt =
3117 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3118 } else {
3119 ctx.shader_info->vs.vgpr_comp_cnt =
3120 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3121 }
3122 }
3123 ctx.abi.load_base_vertex = radv_load_base_vertex;
3124 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3125 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3126 ctx.abi.lookup_interp_param = lookup_interp_param;
3127 ctx.abi.load_sample_position = load_sample_position;
3128 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3129 ctx.abi.emit_kill = radv_emit_kill;
3130 }
3131
3132 if (i)
3133 ac_emit_barrier(&ctx.ac, ctx.stage);
3134
3135 nir_foreach_variable(variable, &shaders[i]->outputs)
3136 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3137
3138 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3139 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3140 shaders[i]->info.cull_distance_array_size > 4;
3141 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3142 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3143 shaders[i]->info.gs.vertices_out;
3144 }
3145
3146 ac_setup_rings(&ctx);
3147
3148 LLVMBasicBlockRef merge_block;
3149 if (shader_count >= 2) {
3150 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3151 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3152 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3153
3154 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3155 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3156 LLVMConstInt(ctx.ac.i32, 8, false), false);
3157 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3158 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3159 thread_id, count, "");
3160 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3161
3162 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3163 }
3164
3165 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3166 handle_fs_inputs(&ctx, shaders[i]);
3167 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3168 handle_vs_inputs(&ctx, shaders[i]);
3169 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3170 prepare_gs_input_vgprs(&ctx);
3171
3172 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3173
3174 if (shader_count >= 2) {
3175 LLVMBuildBr(ctx.ac.builder, merge_block);
3176 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3177 }
3178
3179 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3180 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3181 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3182 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3183 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3184 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3185 }
3186 }
3187
3188 LLVMBuildRetVoid(ctx.ac.builder);
3189
3190 if (options->dump_preoptir)
3191 ac_dump_module(ctx.ac.module);
3192
3193 ac_llvm_finalize_module(&ctx);
3194
3195 if (shader_count == 1)
3196 ac_nir_eliminate_const_vs_outputs(&ctx);
3197
3198 if (options->dump_shader) {
3199 ctx.shader_info->private_mem_vgprs =
3200 ac_count_scratch_private_memory(ctx.main_function);
3201 }
3202
3203 return ctx.ac.module;
3204 }
3205
3206 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3207 {
3208 unsigned *retval = (unsigned *)context;
3209 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3210 char *description = LLVMGetDiagInfoDescription(di);
3211
3212 if (severity == LLVMDSError) {
3213 *retval = 1;
3214 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3215 description);
3216 }
3217
3218 LLVMDisposeMessage(description);
3219 }
3220
3221 static unsigned ac_llvm_compile(LLVMModuleRef M,
3222 struct ac_shader_binary *binary,
3223 LLVMTargetMachineRef tm)
3224 {
3225 unsigned retval = 0;
3226 char *err;
3227 LLVMContextRef llvm_ctx;
3228 LLVMMemoryBufferRef out_buffer;
3229 unsigned buffer_size;
3230 const char *buffer_data;
3231 LLVMBool mem_err;
3232
3233 /* Setup Diagnostic Handler*/
3234 llvm_ctx = LLVMGetModuleContext(M);
3235
3236 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3237 &retval);
3238
3239 /* Compile IR*/
3240 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
3241 &err, &out_buffer);
3242
3243 /* Process Errors/Warnings */
3244 if (mem_err) {
3245 fprintf(stderr, "%s: %s", __FUNCTION__, err);
3246 free(err);
3247 retval = 1;
3248 goto out;
3249 }
3250
3251 /* Extract Shader Code*/
3252 buffer_size = LLVMGetBufferSize(out_buffer);
3253 buffer_data = LLVMGetBufferStart(out_buffer);
3254
3255 ac_elf_read(buffer_data, buffer_size, binary);
3256
3257 /* Clean up */
3258 LLVMDisposeMemoryBuffer(out_buffer);
3259
3260 out:
3261 return retval;
3262 }
3263
3264 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
3265 LLVMModuleRef llvm_module,
3266 struct ac_shader_binary *binary,
3267 struct ac_shader_config *config,
3268 struct radv_shader_variant_info *shader_info,
3269 gl_shader_stage stage,
3270 const struct radv_nir_compiler_options *options)
3271 {
3272 if (options->dump_shader)
3273 ac_dump_module(llvm_module);
3274
3275 memset(binary, 0, sizeof(*binary));
3276
3277 if (options->record_llvm_ir) {
3278 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3279 binary->llvm_ir_string = strdup(llvm_ir);
3280 LLVMDisposeMessage(llvm_ir);
3281 }
3282
3283 int v = ac_llvm_compile(llvm_module, binary, tm);
3284 if (v) {
3285 fprintf(stderr, "compile failed\n");
3286 }
3287
3288 if (options->dump_shader)
3289 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3290
3291 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3292
3293 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3294 LLVMDisposeModule(llvm_module);
3295 LLVMContextDispose(ctx);
3296
3297 if (stage == MESA_SHADER_FRAGMENT) {
3298 shader_info->num_input_vgprs = 0;
3299 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3300 shader_info->num_input_vgprs += 2;
3301 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3302 shader_info->num_input_vgprs += 2;
3303 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3304 shader_info->num_input_vgprs += 2;
3305 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3306 shader_info->num_input_vgprs += 3;
3307 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3308 shader_info->num_input_vgprs += 2;
3309 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3310 shader_info->num_input_vgprs += 2;
3311 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3312 shader_info->num_input_vgprs += 2;
3313 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3314 shader_info->num_input_vgprs += 1;
3315 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3316 shader_info->num_input_vgprs += 1;
3317 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3318 shader_info->num_input_vgprs += 1;
3319 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3320 shader_info->num_input_vgprs += 1;
3321 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3322 shader_info->num_input_vgprs += 1;
3323 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3324 shader_info->num_input_vgprs += 1;
3325 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3326 shader_info->num_input_vgprs += 1;
3327 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3328 shader_info->num_input_vgprs += 1;
3329 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3330 shader_info->num_input_vgprs += 1;
3331 }
3332 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3333
3334 /* +3 for scratch wave offset and VCC */
3335 config->num_sgprs = MAX2(config->num_sgprs,
3336 shader_info->num_input_sgprs + 3);
3337
3338 /* Enable 64-bit and 16-bit denormals, because there is no performance
3339 * cost.
3340 *
3341 * If denormals are enabled, all floating-point output modifiers are
3342 * ignored.
3343 *
3344 * Don't enable denormals for 32-bit floats, because:
3345 * - Floating-point output modifiers would be ignored by the hw.
3346 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3347 * have to stop using those.
3348 * - SI & CI would be very slow.
3349 */
3350 config->float_mode |= V_00B028_FP_64_DENORMS;
3351 }
3352
3353 static void
3354 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3355 {
3356 switch (nir->info.stage) {
3357 case MESA_SHADER_COMPUTE:
3358 for (int i = 0; i < 3; ++i)
3359 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3360 break;
3361 case MESA_SHADER_FRAGMENT:
3362 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3363 break;
3364 case MESA_SHADER_GEOMETRY:
3365 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3366 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3367 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3368 shader_info->gs.invocations = nir->info.gs.invocations;
3369 break;
3370 case MESA_SHADER_TESS_EVAL:
3371 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3372 shader_info->tes.spacing = nir->info.tess.spacing;
3373 shader_info->tes.ccw = nir->info.tess.ccw;
3374 shader_info->tes.point_mode = nir->info.tess.point_mode;
3375 shader_info->tes.as_es = options->key.tes.as_es;
3376 break;
3377 case MESA_SHADER_TESS_CTRL:
3378 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3379 break;
3380 case MESA_SHADER_VERTEX:
3381 shader_info->vs.as_es = options->key.vs.as_es;
3382 shader_info->vs.as_ls = options->key.vs.as_ls;
3383 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3384 if (options->key.vs.as_ls)
3385 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3386 break;
3387 default:
3388 break;
3389 }
3390 }
3391
3392 void
3393 radv_compile_nir_shader(LLVMTargetMachineRef tm,
3394 struct ac_shader_binary *binary,
3395 struct ac_shader_config *config,
3396 struct radv_shader_variant_info *shader_info,
3397 struct nir_shader *const *nir,
3398 int nir_count,
3399 const struct radv_nir_compiler_options *options)
3400 {
3401
3402 LLVMModuleRef llvm_module;
3403
3404 llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
3405 options);
3406
3407 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
3408 nir[0]->info.stage, options);
3409
3410 for (int i = 0; i < nir_count; ++i)
3411 ac_fill_shader_info(shader_info, nir[i], options);
3412
3413 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3414 if (options->chip_class == GFX9) {
3415 if (nir_count == 2 &&
3416 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3417 shader_info->gs.es_type = nir[0]->info.stage;
3418 }
3419 }
3420 }
3421
3422 static void
3423 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3424 {
3425 LLVMValueRef vtx_offset =
3426 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3427 LLVMConstInt(ctx->ac.i32, 4, false), "");
3428 int idx = 0;
3429
3430 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3431 int length = 4;
3432 int slot = idx;
3433 int slot_inc = 1;
3434 if (!(ctx->output_mask & (1ull << i)))
3435 continue;
3436
3437 if (i == VARYING_SLOT_CLIP_DIST0) {
3438 /* unpack clip and cull from a single set of slots */
3439 length = ctx->num_output_clips + ctx->num_output_culls;
3440 if (length > 4)
3441 slot_inc = 2;
3442 }
3443
3444 for (unsigned j = 0; j < length; j++) {
3445 LLVMValueRef value, soffset;
3446
3447 soffset = LLVMConstInt(ctx->ac.i32,
3448 (slot * 4 + j) *
3449 ctx->gs_max_out_vertices * 16 * 4, false);
3450
3451 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3452 1, ctx->ac.i32_0,
3453 vtx_offset, soffset,
3454 0, 1, 1, true, false);
3455
3456 LLVMBuildStore(ctx->ac.builder,
3457 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3458 }
3459 idx += slot_inc;
3460 }
3461 handle_vs_outputs_post(ctx, false, false, &ctx->shader_info->vs.outinfo);
3462 }
3463
3464 void
3465 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
3466 struct nir_shader *geom_shader,
3467 struct ac_shader_binary *binary,
3468 struct ac_shader_config *config,
3469 struct radv_shader_variant_info *shader_info,
3470 const struct radv_nir_compiler_options *options)
3471 {
3472 struct radv_shader_context ctx = {0};
3473 ctx.context = LLVMContextCreate();
3474 ctx.options = options;
3475 ctx.shader_info = shader_info;
3476
3477 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3478 options->family);
3479 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3480
3481 ctx.is_gs_copy_shader = true;
3482 LLVMSetTarget(ctx.ac.module, "amdgcn--");
3483
3484 enum ac_float_mode float_mode =
3485 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3486 AC_FLOAT_MODE_DEFAULT;
3487
3488 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3489 ctx.stage = MESA_SHADER_VERTEX;
3490
3491 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3492
3493 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3494 ac_setup_rings(&ctx);
3495
3496 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3497 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3498
3499 nir_foreach_variable(variable, &geom_shader->outputs) {
3500 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3501 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3502 variable, MESA_SHADER_VERTEX);
3503 }
3504
3505 ac_gs_copy_shader_emit(&ctx);
3506
3507 LLVMBuildRetVoid(ctx.ac.builder);
3508
3509 ac_llvm_finalize_module(&ctx);
3510
3511 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
3512 MESA_SHADER_VERTEX, options);
3513 }