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radv: port to use common passmgr code.
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "nir/nir.h"
31
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35 #if HAVE_LLVM >= 0x0700
36 #include <llvm-c/Transforms/Utils.h>
37 #endif
38
39 #include "sid.h"
40 #include "gfx9d.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_llvm_build.h"
44 #include "ac_shader_abi.h"
45 #include "ac_shader_util.h"
46 #include "ac_exp_param.h"
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct radv_shader_context {
51 struct ac_llvm_context ac;
52 const struct radv_nir_compiler_options *options;
53 struct radv_shader_variant_info *shader_info;
54 struct ac_shader_abi abi;
55
56 unsigned max_workgroup_size;
57 LLVMContextRef context;
58 LLVMValueRef main_function;
59
60 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
61 LLVMValueRef ring_offsets;
62
63 LLVMValueRef vertex_buffers;
64 LLVMValueRef rel_auto_id;
65 LLVMValueRef vs_prim_id;
66 LLVMValueRef es2gs_offset;
67
68 LLVMValueRef oc_lds;
69 LLVMValueRef merged_wave_info;
70 LLVMValueRef tess_factor_offset;
71 LLVMValueRef tes_rel_patch_id;
72 LLVMValueRef tes_u;
73 LLVMValueRef tes_v;
74
75 LLVMValueRef gs2vs_offset;
76 LLVMValueRef gs_wave_id;
77 LLVMValueRef gs_vtx_offset[6];
78
79 LLVMValueRef esgs_ring;
80 LLVMValueRef gsvs_ring;
81 LLVMValueRef hs_ring_tess_offchip;
82 LLVMValueRef hs_ring_tess_factor;
83
84 LLVMValueRef persp_sample, persp_center, persp_centroid;
85 LLVMValueRef linear_sample, linear_center, linear_centroid;
86
87 gl_shader_stage stage;
88
89 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
90
91 uint64_t input_mask;
92 uint64_t output_mask;
93 uint8_t num_output_clips;
94 uint8_t num_output_culls;
95
96 bool is_gs_copy_shader;
97 LLVMValueRef gs_next_vertex;
98 unsigned gs_max_out_vertices;
99
100 unsigned tes_primitive_mode;
101
102 uint32_t tcs_patch_outputs_read;
103 uint64_t tcs_outputs_read;
104 uint32_t tcs_vertices_per_patch;
105 uint32_t tcs_num_inputs;
106 uint32_t tcs_num_patches;
107 uint32_t max_gsvs_emit_size;
108 uint32_t gsvs_vertex_size;
109 };
110
111 enum radeon_llvm_calling_convention {
112 RADEON_LLVM_AMDGPU_VS = 87,
113 RADEON_LLVM_AMDGPU_GS = 88,
114 RADEON_LLVM_AMDGPU_PS = 89,
115 RADEON_LLVM_AMDGPU_CS = 90,
116 RADEON_LLVM_AMDGPU_HS = 93,
117 };
118
119 static inline struct radv_shader_context *
120 radv_shader_context_from_abi(struct ac_shader_abi *abi)
121 {
122 struct radv_shader_context *ctx = NULL;
123 return container_of(abi, ctx, abi);
124 }
125
126 struct ac_build_if_state
127 {
128 struct radv_shader_context *ctx;
129 LLVMValueRef condition;
130 LLVMBasicBlockRef entry_block;
131 LLVMBasicBlockRef true_block;
132 LLVMBasicBlockRef false_block;
133 LLVMBasicBlockRef merge_block;
134 };
135
136 static LLVMBasicBlockRef
137 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
138 {
139 LLVMBasicBlockRef current_block;
140 LLVMBasicBlockRef next_block;
141 LLVMBasicBlockRef new_block;
142
143 /* get current basic block */
144 current_block = LLVMGetInsertBlock(ctx->ac.builder);
145
146 /* chqeck if there's another block after this one */
147 next_block = LLVMGetNextBasicBlock(current_block);
148 if (next_block) {
149 /* insert the new block before the next block */
150 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
151 }
152 else {
153 /* append new block after current block */
154 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
155 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
156 }
157 return new_block;
158 }
159
160 static void
161 ac_nir_build_if(struct ac_build_if_state *ifthen,
162 struct radv_shader_context *ctx,
163 LLVMValueRef condition)
164 {
165 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
166
167 memset(ifthen, 0, sizeof *ifthen);
168 ifthen->ctx = ctx;
169 ifthen->condition = condition;
170 ifthen->entry_block = block;
171
172 /* create endif/merge basic block for the phi functions */
173 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
174
175 /* create/insert true_block before merge_block */
176 ifthen->true_block =
177 LLVMInsertBasicBlockInContext(ctx->context,
178 ifthen->merge_block,
179 "if-true-block");
180
181 /* successive code goes into the true block */
182 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
183 }
184
185 /**
186 * End a conditional.
187 */
188 static void
189 ac_nir_build_endif(struct ac_build_if_state *ifthen)
190 {
191 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
192
193 /* Insert branch to the merge block from current block */
194 LLVMBuildBr(builder, ifthen->merge_block);
195
196 /*
197 * Now patch in the various branch instructions.
198 */
199
200 /* Insert the conditional branch instruction at the end of entry_block */
201 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
202 if (ifthen->false_block) {
203 /* we have an else clause */
204 LLVMBuildCondBr(builder, ifthen->condition,
205 ifthen->true_block, ifthen->false_block);
206 }
207 else {
208 /* no else clause */
209 LLVMBuildCondBr(builder, ifthen->condition,
210 ifthen->true_block, ifthen->merge_block);
211 }
212
213 /* Resume building code at end of the ifthen->merge_block */
214 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
215 }
216
217
218 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
219 {
220 switch (ctx->stage) {
221 case MESA_SHADER_TESS_CTRL:
222 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
223 case MESA_SHADER_TESS_EVAL:
224 return ctx->tes_rel_patch_id;
225 break;
226 default:
227 unreachable("Illegal stage");
228 }
229 }
230
231 static unsigned
232 get_tcs_num_patches(struct radv_shader_context *ctx)
233 {
234 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
235 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
236 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
237 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
238 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
239 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
240 uint32_t output_vertex_size = num_tcs_outputs * 16;
241 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
242 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
243 unsigned num_patches;
244 unsigned hardware_lds_size;
245
246 /* Ensure that we only need one wave per SIMD so we don't need to check
247 * resource usage. Also ensures that the number of tcs in and out
248 * vertices per threadgroup are at most 256.
249 */
250 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
251 /* Make sure that the data fits in LDS. This assumes the shaders only
252 * use LDS for the inputs and outputs.
253 */
254 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
255 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
256 /* Make sure the output data fits in the offchip buffer */
257 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
258 /* Not necessary for correctness, but improves performance. The
259 * specific value is taken from the proprietary driver.
260 */
261 num_patches = MIN2(num_patches, 40);
262
263 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
264 if (ctx->options->chip_class == SI) {
265 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
266 num_patches = MIN2(num_patches, one_wave);
267 }
268 return num_patches;
269 }
270
271 static unsigned
272 calculate_tess_lds_size(struct radv_shader_context *ctx)
273 {
274 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
275 unsigned num_tcs_output_cp;
276 unsigned num_tcs_outputs, num_tcs_patch_outputs;
277 unsigned input_vertex_size, output_vertex_size;
278 unsigned input_patch_size, output_patch_size;
279 unsigned pervertex_output_patch_size;
280 unsigned output_patch0_offset;
281 unsigned num_patches;
282 unsigned lds_size;
283
284 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
285 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
286 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
287
288 input_vertex_size = ctx->tcs_num_inputs * 16;
289 output_vertex_size = num_tcs_outputs * 16;
290
291 input_patch_size = num_tcs_input_cp * input_vertex_size;
292
293 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
294 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
295
296 num_patches = ctx->tcs_num_patches;
297 output_patch0_offset = input_patch_size * num_patches;
298
299 lds_size = output_patch0_offset + output_patch_size * num_patches;
300 return lds_size;
301 }
302
303 /* Tessellation shaders pass outputs to the next shader using LDS.
304 *
305 * LS outputs = TCS inputs
306 * TCS outputs = TES inputs
307 *
308 * The LDS layout is:
309 * - TCS inputs for patch 0
310 * - TCS inputs for patch 1
311 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
312 * - ...
313 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
314 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
315 * - TCS outputs for patch 1
316 * - Per-patch TCS outputs for patch 1
317 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
318 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
319 * - ...
320 *
321 * All three shaders VS(LS), TCS, TES share the same LDS space.
322 */
323 static LLVMValueRef
324 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
325 {
326 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
327 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
328 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
329
330 input_patch_size /= 4;
331 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
332 }
333
334 static LLVMValueRef
335 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
336 {
337 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
338 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
339 uint32_t output_vertex_size = num_tcs_outputs * 16;
340 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
341 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
342 output_patch_size /= 4;
343 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
344 }
345
346 static LLVMValueRef
347 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
348 {
349 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
350 uint32_t output_vertex_size = num_tcs_outputs * 16;
351 output_vertex_size /= 4;
352 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
353 }
354
355 static LLVMValueRef
356 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
357 {
358 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
359 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
360 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
361 uint32_t output_patch0_offset = input_patch_size;
362 unsigned num_patches = ctx->tcs_num_patches;
363
364 output_patch0_offset *= num_patches;
365 output_patch0_offset /= 4;
366 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
367 }
368
369 static LLVMValueRef
370 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
371 {
372 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
373 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
374 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
375 uint32_t output_patch0_offset = input_patch_size;
376
377 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
378 uint32_t output_vertex_size = num_tcs_outputs * 16;
379 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
380 unsigned num_patches = ctx->tcs_num_patches;
381
382 output_patch0_offset *= num_patches;
383 output_patch0_offset += pervertex_output_patch_size;
384 output_patch0_offset /= 4;
385 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
386 }
387
388 static LLVMValueRef
389 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
390 {
391 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
392 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
393
394 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
395 }
396
397 static LLVMValueRef
398 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
399 {
400 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
401 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
402 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
403
404 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
405 LLVMBuildMul(ctx->ac.builder, patch_stride,
406 rel_patch_id, ""),
407 "");
408 }
409
410 static LLVMValueRef
411 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
412 {
413 LLVMValueRef patch0_patch_data_offset =
414 get_tcs_out_patch0_patch_data_offset(ctx);
415 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
416 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
417
418 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
419 LLVMBuildMul(ctx->ac.builder, patch_stride,
420 rel_patch_id, ""),
421 "");
422 }
423
424 #define MAX_ARGS 23
425 struct arg_info {
426 LLVMTypeRef types[MAX_ARGS];
427 LLVMValueRef *assign[MAX_ARGS];
428 unsigned array_params_mask;
429 uint8_t count;
430 uint8_t sgpr_count;
431 uint8_t num_sgprs_used;
432 uint8_t num_vgprs_used;
433 };
434
435 enum ac_arg_regfile {
436 ARG_SGPR,
437 ARG_VGPR,
438 };
439
440 static void
441 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
442 LLVMValueRef *param_ptr)
443 {
444 assert(info->count < MAX_ARGS);
445
446 info->assign[info->count] = param_ptr;
447 info->types[info->count] = type;
448 info->count++;
449
450 if (regfile == ARG_SGPR) {
451 info->num_sgprs_used += ac_get_type_size(type) / 4;
452 info->sgpr_count++;
453 } else {
454 assert(regfile == ARG_VGPR);
455 info->num_vgprs_used += ac_get_type_size(type) / 4;
456 }
457 }
458
459 static inline void
460 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
461 {
462 info->array_params_mask |= (1 << info->count);
463 add_arg(info, ARG_SGPR, type, param_ptr);
464 }
465
466 static void assign_arguments(LLVMValueRef main_function,
467 struct arg_info *info)
468 {
469 unsigned i;
470 for (i = 0; i < info->count; i++) {
471 if (info->assign[i])
472 *info->assign[i] = LLVMGetParam(main_function, i);
473 }
474 }
475
476 static LLVMValueRef
477 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
478 LLVMBuilderRef builder, LLVMTypeRef *return_types,
479 unsigned num_return_elems,
480 struct arg_info *args,
481 unsigned max_workgroup_size,
482 const struct radv_nir_compiler_options *options)
483 {
484 LLVMTypeRef main_function_type, ret_type;
485 LLVMBasicBlockRef main_function_body;
486
487 if (num_return_elems)
488 ret_type = LLVMStructTypeInContext(ctx, return_types,
489 num_return_elems, true);
490 else
491 ret_type = LLVMVoidTypeInContext(ctx);
492
493 /* Setup the function */
494 main_function_type =
495 LLVMFunctionType(ret_type, args->types, args->count, 0);
496 LLVMValueRef main_function =
497 LLVMAddFunction(module, "main", main_function_type);
498 main_function_body =
499 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
500 LLVMPositionBuilderAtEnd(builder, main_function_body);
501
502 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
503 for (unsigned i = 0; i < args->sgpr_count; ++i) {
504 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
505
506 if (args->array_params_mask & (1 << i)) {
507 LLVMValueRef P = LLVMGetParam(main_function, i);
508 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
509 ac_add_attr_dereferenceable(P, UINT64_MAX);
510 }
511 }
512
513 if (options->address32_hi) {
514 ac_llvm_add_target_dep_function_attr(main_function,
515 "amdgpu-32bit-address-high-bits",
516 options->address32_hi);
517 }
518
519 if (max_workgroup_size) {
520 ac_llvm_add_target_dep_function_attr(main_function,
521 "amdgpu-max-work-group-size",
522 max_workgroup_size);
523 }
524 if (options->unsafe_math) {
525 /* These were copied from some LLVM test. */
526 LLVMAddTargetDependentFunctionAttr(main_function,
527 "less-precise-fpmad",
528 "true");
529 LLVMAddTargetDependentFunctionAttr(main_function,
530 "no-infs-fp-math",
531 "true");
532 LLVMAddTargetDependentFunctionAttr(main_function,
533 "no-nans-fp-math",
534 "true");
535 LLVMAddTargetDependentFunctionAttr(main_function,
536 "unsafe-fp-math",
537 "true");
538 LLVMAddTargetDependentFunctionAttr(main_function,
539 "no-signed-zeros-fp-math",
540 "true");
541 }
542 return main_function;
543 }
544
545
546 static void
547 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
548 uint32_t indirect_offset)
549 {
550 ud_info->sgpr_idx = *sgpr_idx;
551 ud_info->num_sgprs = num_sgprs;
552 ud_info->indirect = indirect_offset > 0;
553 ud_info->indirect_offset = indirect_offset;
554 *sgpr_idx += num_sgprs;
555 }
556
557 static void
558 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
559 uint8_t num_sgprs)
560 {
561 struct radv_userdata_info *ud_info =
562 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
563 assert(ud_info);
564
565 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
566 }
567
568 static void
569 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
570 {
571 bool use_32bit_pointers = HAVE_32BIT_POINTERS &&
572 idx != AC_UD_SCRATCH_RING_OFFSETS;
573
574 set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
575 }
576
577 static void
578 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
579 uint32_t indirect_offset)
580 {
581 struct radv_userdata_info *ud_info =
582 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
583 assert(ud_info);
584
585 set_loc(ud_info, sgpr_idx, HAVE_32BIT_POINTERS ? 1 : 2, indirect_offset);
586 }
587
588 struct user_sgpr_info {
589 bool need_ring_offsets;
590 bool indirect_all_descriptor_sets;
591 };
592
593 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
594 gl_shader_stage stage)
595 {
596 switch (stage) {
597 case MESA_SHADER_VERTEX:
598 if (ctx->shader_info->info.needs_multiview_view_index ||
599 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
600 return true;
601 break;
602 case MESA_SHADER_TESS_EVAL:
603 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
604 return true;
605 break;
606 case MESA_SHADER_GEOMETRY:
607 case MESA_SHADER_TESS_CTRL:
608 if (ctx->shader_info->info.needs_multiview_view_index)
609 return true;
610 break;
611 default:
612 break;
613 }
614 return false;
615 }
616
617 static uint8_t
618 count_vs_user_sgprs(struct radv_shader_context *ctx)
619 {
620 uint8_t count = 0;
621
622 if (ctx->shader_info->info.vs.has_vertex_buffers)
623 count += HAVE_32BIT_POINTERS ? 1 : 2;
624 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
625
626 return count;
627 }
628
629 static void allocate_user_sgprs(struct radv_shader_context *ctx,
630 gl_shader_stage stage,
631 bool has_previous_stage,
632 gl_shader_stage previous_stage,
633 bool needs_view_index,
634 struct user_sgpr_info *user_sgpr_info)
635 {
636 uint8_t user_sgpr_count = 0;
637
638 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
639
640 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
641 if (stage == MESA_SHADER_GEOMETRY ||
642 stage == MESA_SHADER_VERTEX ||
643 stage == MESA_SHADER_TESS_CTRL ||
644 stage == MESA_SHADER_TESS_EVAL ||
645 ctx->is_gs_copy_shader)
646 user_sgpr_info->need_ring_offsets = true;
647
648 if (stage == MESA_SHADER_FRAGMENT &&
649 ctx->shader_info->info.ps.needs_sample_positions)
650 user_sgpr_info->need_ring_offsets = true;
651
652 /* 2 user sgprs will nearly always be allocated for scratch/rings */
653 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
654 user_sgpr_count += 2;
655 }
656
657 switch (stage) {
658 case MESA_SHADER_COMPUTE:
659 if (ctx->shader_info->info.cs.uses_grid_size)
660 user_sgpr_count += 3;
661 break;
662 case MESA_SHADER_FRAGMENT:
663 user_sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
664 break;
665 case MESA_SHADER_VERTEX:
666 if (!ctx->is_gs_copy_shader)
667 user_sgpr_count += count_vs_user_sgprs(ctx);
668 break;
669 case MESA_SHADER_TESS_CTRL:
670 if (has_previous_stage) {
671 if (previous_stage == MESA_SHADER_VERTEX)
672 user_sgpr_count += count_vs_user_sgprs(ctx);
673 }
674 break;
675 case MESA_SHADER_TESS_EVAL:
676 break;
677 case MESA_SHADER_GEOMETRY:
678 if (has_previous_stage) {
679 if (previous_stage == MESA_SHADER_VERTEX) {
680 user_sgpr_count += count_vs_user_sgprs(ctx);
681 }
682 }
683 break;
684 default:
685 break;
686 }
687
688 if (needs_view_index)
689 user_sgpr_count++;
690
691 if (ctx->shader_info->info.loads_push_constants)
692 user_sgpr_count += HAVE_32BIT_POINTERS ? 1 : 2;
693
694 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
695 uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
696 uint32_t num_desc_set =
697 util_bitcount(ctx->shader_info->info.desc_set_used_mask);
698
699 if (remaining_sgprs / (HAVE_32BIT_POINTERS ? 1 : 2) < num_desc_set) {
700 user_sgpr_info->indirect_all_descriptor_sets = true;
701 }
702 }
703
704 static void
705 declare_global_input_sgprs(struct radv_shader_context *ctx,
706 gl_shader_stage stage,
707 bool has_previous_stage,
708 gl_shader_stage previous_stage,
709 const struct user_sgpr_info *user_sgpr_info,
710 struct arg_info *args,
711 LLVMValueRef *desc_sets)
712 {
713 LLVMTypeRef type = ac_array_in_const32_addr_space(ctx->ac.i8);
714 unsigned num_sets = ctx->options->layout ?
715 ctx->options->layout->num_sets : 0;
716 unsigned stage_mask = 1 << stage;
717
718 if (has_previous_stage)
719 stage_mask |= 1 << previous_stage;
720
721 /* 1 for each descriptor set */
722 if (!user_sgpr_info->indirect_all_descriptor_sets) {
723 for (unsigned i = 0; i < num_sets; ++i) {
724 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
725 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
726 add_array_arg(args, type,
727 &ctx->descriptor_sets[i]);
728 }
729 }
730 } else {
731 add_array_arg(args, ac_array_in_const32_addr_space(type), desc_sets);
732 }
733
734 if (ctx->shader_info->info.loads_push_constants) {
735 /* 1 for push constants and dynamic descriptors */
736 add_array_arg(args, type, &ctx->abi.push_constants);
737 }
738 }
739
740 static void
741 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
742 gl_shader_stage stage,
743 bool has_previous_stage,
744 gl_shader_stage previous_stage,
745 struct arg_info *args)
746 {
747 if (!ctx->is_gs_copy_shader &&
748 (stage == MESA_SHADER_VERTEX ||
749 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
750 if (ctx->shader_info->info.vs.has_vertex_buffers) {
751 add_arg(args, ARG_SGPR,
752 ac_array_in_const32_addr_space(ctx->ac.v4i32),
753 &ctx->vertex_buffers);
754 }
755 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
756 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
757 if (ctx->shader_info->info.vs.needs_draw_id) {
758 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
759 }
760 }
761 }
762
763 static void
764 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
765 {
766 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
767 if (!ctx->is_gs_copy_shader) {
768 if (ctx->options->key.vs.as_ls) {
769 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
770 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
771 } else {
772 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
773 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
774 }
775 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
776 }
777 }
778
779 static void
780 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
781 {
782 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
783 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
784 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
785 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
786 }
787
788 static void
789 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
790 bool has_previous_stage, gl_shader_stage previous_stage,
791 const struct user_sgpr_info *user_sgpr_info,
792 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
793 {
794 unsigned num_sets = ctx->options->layout ?
795 ctx->options->layout->num_sets : 0;
796 unsigned stage_mask = 1 << stage;
797
798 if (has_previous_stage)
799 stage_mask |= 1 << previous_stage;
800
801 if (!user_sgpr_info->indirect_all_descriptor_sets) {
802 for (unsigned i = 0; i < num_sets; ++i) {
803 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
804 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
805 set_loc_desc(ctx, i, user_sgpr_idx, 0);
806 } else
807 ctx->descriptor_sets[i] = NULL;
808 }
809 } else {
810 set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
811 user_sgpr_idx);
812
813 for (unsigned i = 0; i < num_sets; ++i) {
814 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
815 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
816 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
817 ctx->descriptor_sets[i] =
818 ac_build_load_to_sgpr(&ctx->ac,
819 desc_sets,
820 LLVMConstInt(ctx->ac.i32, i, false));
821
822 } else
823 ctx->descriptor_sets[i] = NULL;
824 }
825 ctx->shader_info->need_indirect_descriptor_sets = true;
826 }
827
828 if (ctx->shader_info->info.loads_push_constants) {
829 set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
830 }
831 }
832
833 static void
834 set_vs_specific_input_locs(struct radv_shader_context *ctx,
835 gl_shader_stage stage, bool has_previous_stage,
836 gl_shader_stage previous_stage,
837 uint8_t *user_sgpr_idx)
838 {
839 if (!ctx->is_gs_copy_shader &&
840 (stage == MESA_SHADER_VERTEX ||
841 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
842 if (ctx->shader_info->info.vs.has_vertex_buffers) {
843 set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
844 user_sgpr_idx);
845 }
846
847 unsigned vs_num = 2;
848 if (ctx->shader_info->info.vs.needs_draw_id)
849 vs_num++;
850
851 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
852 user_sgpr_idx, vs_num);
853 }
854 }
855
856 static void set_llvm_calling_convention(LLVMValueRef func,
857 gl_shader_stage stage)
858 {
859 enum radeon_llvm_calling_convention calling_conv;
860
861 switch (stage) {
862 case MESA_SHADER_VERTEX:
863 case MESA_SHADER_TESS_EVAL:
864 calling_conv = RADEON_LLVM_AMDGPU_VS;
865 break;
866 case MESA_SHADER_GEOMETRY:
867 calling_conv = RADEON_LLVM_AMDGPU_GS;
868 break;
869 case MESA_SHADER_TESS_CTRL:
870 calling_conv = RADEON_LLVM_AMDGPU_HS;
871 break;
872 case MESA_SHADER_FRAGMENT:
873 calling_conv = RADEON_LLVM_AMDGPU_PS;
874 break;
875 case MESA_SHADER_COMPUTE:
876 calling_conv = RADEON_LLVM_AMDGPU_CS;
877 break;
878 default:
879 unreachable("Unhandle shader type");
880 }
881
882 LLVMSetFunctionCallConv(func, calling_conv);
883 }
884
885 static void create_function(struct radv_shader_context *ctx,
886 gl_shader_stage stage,
887 bool has_previous_stage,
888 gl_shader_stage previous_stage)
889 {
890 uint8_t user_sgpr_idx;
891 struct user_sgpr_info user_sgpr_info;
892 struct arg_info args = {};
893 LLVMValueRef desc_sets;
894 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
895 allocate_user_sgprs(ctx, stage, has_previous_stage,
896 previous_stage, needs_view_index, &user_sgpr_info);
897
898 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
899 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
900 &ctx->ring_offsets);
901 }
902
903 switch (stage) {
904 case MESA_SHADER_COMPUTE:
905 declare_global_input_sgprs(ctx, stage, has_previous_stage,
906 previous_stage, &user_sgpr_info,
907 &args, &desc_sets);
908
909 if (ctx->shader_info->info.cs.uses_grid_size) {
910 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
911 &ctx->abi.num_work_groups);
912 }
913
914 for (int i = 0; i < 3; i++) {
915 ctx->abi.workgroup_ids[i] = NULL;
916 if (ctx->shader_info->info.cs.uses_block_id[i]) {
917 add_arg(&args, ARG_SGPR, ctx->ac.i32,
918 &ctx->abi.workgroup_ids[i]);
919 }
920 }
921
922 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
923 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
924 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
925 &ctx->abi.local_invocation_ids);
926 break;
927 case MESA_SHADER_VERTEX:
928 declare_global_input_sgprs(ctx, stage, has_previous_stage,
929 previous_stage, &user_sgpr_info,
930 &args, &desc_sets);
931 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
932 previous_stage, &args);
933
934 if (needs_view_index)
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->abi.view_index);
937 if (ctx->options->key.vs.as_es)
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->es2gs_offset);
940
941 declare_vs_input_vgprs(ctx, &args);
942 break;
943 case MESA_SHADER_TESS_CTRL:
944 if (has_previous_stage) {
945 // First 6 system regs
946 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
947 add_arg(&args, ARG_SGPR, ctx->ac.i32,
948 &ctx->merged_wave_info);
949 add_arg(&args, ARG_SGPR, ctx->ac.i32,
950 &ctx->tess_factor_offset);
951
952 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
953 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
954 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
955
956 declare_global_input_sgprs(ctx, stage,
957 has_previous_stage,
958 previous_stage,
959 &user_sgpr_info, &args,
960 &desc_sets);
961 declare_vs_specific_input_sgprs(ctx, stage,
962 has_previous_stage,
963 previous_stage, &args);
964
965 if (needs_view_index)
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->abi.view_index);
968
969 add_arg(&args, ARG_VGPR, ctx->ac.i32,
970 &ctx->abi.tcs_patch_id);
971 add_arg(&args, ARG_VGPR, ctx->ac.i32,
972 &ctx->abi.tcs_rel_ids);
973
974 declare_vs_input_vgprs(ctx, &args);
975 } else {
976 declare_global_input_sgprs(ctx, stage,
977 has_previous_stage,
978 previous_stage,
979 &user_sgpr_info, &args,
980 &desc_sets);
981
982 if (needs_view_index)
983 add_arg(&args, ARG_SGPR, ctx->ac.i32,
984 &ctx->abi.view_index);
985
986 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
987 add_arg(&args, ARG_SGPR, ctx->ac.i32,
988 &ctx->tess_factor_offset);
989 add_arg(&args, ARG_VGPR, ctx->ac.i32,
990 &ctx->abi.tcs_patch_id);
991 add_arg(&args, ARG_VGPR, ctx->ac.i32,
992 &ctx->abi.tcs_rel_ids);
993 }
994 break;
995 case MESA_SHADER_TESS_EVAL:
996 declare_global_input_sgprs(ctx, stage, has_previous_stage,
997 previous_stage, &user_sgpr_info,
998 &args, &desc_sets);
999
1000 if (needs_view_index)
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1002 &ctx->abi.view_index);
1003
1004 if (ctx->options->key.tes.as_es) {
1005 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1007 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1008 &ctx->es2gs_offset);
1009 } else {
1010 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1011 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1012 }
1013 declare_tes_input_vgprs(ctx, &args);
1014 break;
1015 case MESA_SHADER_GEOMETRY:
1016 if (has_previous_stage) {
1017 // First 6 system regs
1018 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1019 &ctx->gs2vs_offset);
1020 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1021 &ctx->merged_wave_info);
1022 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1023
1024 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1025 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1026 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1027
1028 declare_global_input_sgprs(ctx, stage,
1029 has_previous_stage,
1030 previous_stage,
1031 &user_sgpr_info, &args,
1032 &desc_sets);
1033
1034 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1035 declare_vs_specific_input_sgprs(ctx, stage,
1036 has_previous_stage,
1037 previous_stage,
1038 &args);
1039 }
1040
1041 if (needs_view_index)
1042 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1043 &ctx->abi.view_index);
1044
1045 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1046 &ctx->gs_vtx_offset[0]);
1047 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1048 &ctx->gs_vtx_offset[2]);
1049 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1050 &ctx->abi.gs_prim_id);
1051 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1052 &ctx->abi.gs_invocation_id);
1053 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1054 &ctx->gs_vtx_offset[4]);
1055
1056 if (previous_stage == MESA_SHADER_VERTEX) {
1057 declare_vs_input_vgprs(ctx, &args);
1058 } else {
1059 declare_tes_input_vgprs(ctx, &args);
1060 }
1061 } else {
1062 declare_global_input_sgprs(ctx, stage,
1063 has_previous_stage,
1064 previous_stage,
1065 &user_sgpr_info, &args,
1066 &desc_sets);
1067
1068 if (needs_view_index)
1069 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1070 &ctx->abi.view_index);
1071
1072 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1073 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1074 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1075 &ctx->gs_vtx_offset[0]);
1076 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1077 &ctx->gs_vtx_offset[1]);
1078 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1079 &ctx->abi.gs_prim_id);
1080 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1081 &ctx->gs_vtx_offset[2]);
1082 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1083 &ctx->gs_vtx_offset[3]);
1084 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1085 &ctx->gs_vtx_offset[4]);
1086 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1087 &ctx->gs_vtx_offset[5]);
1088 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1089 &ctx->abi.gs_invocation_id);
1090 }
1091 break;
1092 case MESA_SHADER_FRAGMENT:
1093 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1094 previous_stage, &user_sgpr_info,
1095 &args, &desc_sets);
1096
1097 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1098 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1099 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1100 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1101 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1102 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1103 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1104 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1105 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1106 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1107 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1108 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1109 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1110 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1111 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1112 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1113 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1114 break;
1115 default:
1116 unreachable("Shader stage not implemented");
1117 }
1118
1119 ctx->main_function = create_llvm_function(
1120 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1121 ctx->max_workgroup_size, ctx->options);
1122 set_llvm_calling_convention(ctx->main_function, stage);
1123
1124
1125 ctx->shader_info->num_input_vgprs = 0;
1126 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1127
1128 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1129
1130 if (ctx->stage != MESA_SHADER_FRAGMENT)
1131 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1132
1133 assign_arguments(ctx->main_function, &args);
1134
1135 user_sgpr_idx = 0;
1136
1137 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1138 set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1139 &user_sgpr_idx);
1140 if (ctx->options->supports_spill) {
1141 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1142 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1143 NULL, 0, AC_FUNC_ATTR_READNONE);
1144 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1145 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1146 }
1147 }
1148
1149 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1150 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1151 if (has_previous_stage)
1152 user_sgpr_idx = 0;
1153
1154 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1155 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1156
1157 switch (stage) {
1158 case MESA_SHADER_COMPUTE:
1159 if (ctx->shader_info->info.cs.uses_grid_size) {
1160 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1161 &user_sgpr_idx, 3);
1162 }
1163 break;
1164 case MESA_SHADER_VERTEX:
1165 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1166 previous_stage, &user_sgpr_idx);
1167 if (ctx->abi.view_index)
1168 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1169 break;
1170 case MESA_SHADER_TESS_CTRL:
1171 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1172 previous_stage, &user_sgpr_idx);
1173 if (ctx->abi.view_index)
1174 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1175 break;
1176 case MESA_SHADER_TESS_EVAL:
1177 if (ctx->abi.view_index)
1178 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1179 break;
1180 case MESA_SHADER_GEOMETRY:
1181 if (has_previous_stage) {
1182 if (previous_stage == MESA_SHADER_VERTEX)
1183 set_vs_specific_input_locs(ctx, stage,
1184 has_previous_stage,
1185 previous_stage,
1186 &user_sgpr_idx);
1187 }
1188 if (ctx->abi.view_index)
1189 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1190 break;
1191 case MESA_SHADER_FRAGMENT:
1192 break;
1193 default:
1194 unreachable("Shader stage not implemented");
1195 }
1196
1197 if (stage == MESA_SHADER_TESS_CTRL ||
1198 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1199 /* GFX9 has the ESGS ring buffer in LDS. */
1200 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1201 ac_declare_lds_as_pointer(&ctx->ac);
1202 }
1203
1204 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1205 }
1206
1207
1208 static LLVMValueRef
1209 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1210 unsigned desc_set, unsigned binding)
1211 {
1212 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1213 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1214 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1215 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1216 unsigned base_offset = layout->binding[binding].offset;
1217 LLVMValueRef offset, stride;
1218
1219 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1220 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1221 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1222 layout->binding[binding].dynamic_offset_offset;
1223 desc_ptr = ctx->abi.push_constants;
1224 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1225 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1226 } else
1227 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1228
1229 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1230 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
1231 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
1232
1233 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1234 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1235 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1236
1237 return desc_ptr;
1238 }
1239
1240
1241 /* The offchip buffer layout for TCS->TES is
1242 *
1243 * - attribute 0 of patch 0 vertex 0
1244 * - attribute 0 of patch 0 vertex 1
1245 * - attribute 0 of patch 0 vertex 2
1246 * ...
1247 * - attribute 0 of patch 1 vertex 0
1248 * - attribute 0 of patch 1 vertex 1
1249 * ...
1250 * - attribute 1 of patch 0 vertex 0
1251 * - attribute 1 of patch 0 vertex 1
1252 * ...
1253 * - per patch attribute 0 of patch 0
1254 * - per patch attribute 0 of patch 1
1255 * ...
1256 *
1257 * Note that every attribute has 4 components.
1258 */
1259 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1260 {
1261 uint32_t num_patches = ctx->tcs_num_patches;
1262 uint32_t num_tcs_outputs;
1263 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1264 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1265 else
1266 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1267
1268 uint32_t output_vertex_size = num_tcs_outputs * 16;
1269 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1270
1271 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1272 }
1273
1274 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1275 LLVMValueRef vertex_index)
1276 {
1277 LLVMValueRef param_stride;
1278 if (vertex_index)
1279 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1280 else
1281 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1282 return param_stride;
1283 }
1284
1285 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1286 LLVMValueRef vertex_index,
1287 LLVMValueRef param_index)
1288 {
1289 LLVMValueRef base_addr;
1290 LLVMValueRef param_stride, constant16;
1291 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1292 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1293 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1294 param_stride = calc_param_stride(ctx, vertex_index);
1295 if (vertex_index) {
1296 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
1297 vertices_per_patch, "");
1298
1299 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1300 vertex_index, "");
1301 } else {
1302 base_addr = rel_patch_id;
1303 }
1304
1305 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1306 LLVMBuildMul(ctx->ac.builder, param_index,
1307 param_stride, ""), "");
1308
1309 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1310
1311 if (!vertex_index) {
1312 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1313
1314 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1315 patch_data_offset, "");
1316 }
1317 return base_addr;
1318 }
1319
1320 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1321 unsigned param,
1322 unsigned const_index,
1323 bool is_compact,
1324 LLVMValueRef vertex_index,
1325 LLVMValueRef indir_index)
1326 {
1327 LLVMValueRef param_index;
1328
1329 if (indir_index)
1330 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1331 indir_index, "");
1332 else {
1333 if (const_index && !is_compact)
1334 param += const_index;
1335 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1336 }
1337 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1338 }
1339
1340 static LLVMValueRef
1341 get_dw_address(struct radv_shader_context *ctx,
1342 LLVMValueRef dw_addr,
1343 unsigned param,
1344 unsigned const_index,
1345 bool compact_const_index,
1346 LLVMValueRef vertex_index,
1347 LLVMValueRef stride,
1348 LLVMValueRef indir_index)
1349
1350 {
1351
1352 if (vertex_index) {
1353 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1354 LLVMBuildMul(ctx->ac.builder,
1355 vertex_index,
1356 stride, ""), "");
1357 }
1358
1359 if (indir_index)
1360 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1361 LLVMBuildMul(ctx->ac.builder, indir_index,
1362 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1363 else if (const_index && !compact_const_index)
1364 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1365 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1366
1367 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1368 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1369
1370 if (const_index && compact_const_index)
1371 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1372 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1373 return dw_addr;
1374 }
1375
1376 static LLVMValueRef
1377 load_tcs_varyings(struct ac_shader_abi *abi,
1378 LLVMTypeRef type,
1379 LLVMValueRef vertex_index,
1380 LLVMValueRef indir_index,
1381 unsigned const_index,
1382 unsigned location,
1383 unsigned driver_location,
1384 unsigned component,
1385 unsigned num_components,
1386 bool is_patch,
1387 bool is_compact,
1388 bool load_input)
1389 {
1390 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1391 LLVMValueRef dw_addr, stride;
1392 LLVMValueRef value[4], result;
1393 unsigned param = shader_io_get_unique_index(location);
1394
1395 if (load_input) {
1396 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1397 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1398 dw_addr = get_tcs_in_current_patch_offset(ctx);
1399 } else {
1400 if (!is_patch) {
1401 stride = get_tcs_out_vertex_stride(ctx);
1402 dw_addr = get_tcs_out_current_patch_offset(ctx);
1403 } else {
1404 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1405 stride = NULL;
1406 }
1407 }
1408
1409 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1410 indir_index);
1411
1412 for (unsigned i = 0; i < num_components + component; i++) {
1413 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1414 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1415 ctx->ac.i32_1, "");
1416 }
1417 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1418 return result;
1419 }
1420
1421 static void
1422 store_tcs_output(struct ac_shader_abi *abi,
1423 const nir_variable *var,
1424 LLVMValueRef vertex_index,
1425 LLVMValueRef param_index,
1426 unsigned const_index,
1427 LLVMValueRef src,
1428 unsigned writemask)
1429 {
1430 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1431 const unsigned location = var->data.location;
1432 const unsigned component = var->data.location_frac;
1433 const bool is_patch = var->data.patch;
1434 const bool is_compact = var->data.compact;
1435 LLVMValueRef dw_addr;
1436 LLVMValueRef stride = NULL;
1437 LLVMValueRef buf_addr = NULL;
1438 unsigned param;
1439 bool store_lds = true;
1440
1441 if (is_patch) {
1442 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1443 store_lds = false;
1444 } else {
1445 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1446 store_lds = false;
1447 }
1448
1449 param = shader_io_get_unique_index(location);
1450 if (location == VARYING_SLOT_CLIP_DIST0 &&
1451 is_compact && const_index > 3) {
1452 const_index -= 3;
1453 param++;
1454 }
1455
1456 if (!is_patch) {
1457 stride = get_tcs_out_vertex_stride(ctx);
1458 dw_addr = get_tcs_out_current_patch_offset(ctx);
1459 } else {
1460 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1461 }
1462
1463 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1464 param_index);
1465 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1466 vertex_index, param_index);
1467
1468 bool is_tess_factor = false;
1469 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1470 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1471 is_tess_factor = true;
1472
1473 unsigned base = is_compact ? const_index : 0;
1474 for (unsigned chan = 0; chan < 8; chan++) {
1475 if (!(writemask & (1 << chan)))
1476 continue;
1477 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1478
1479 if (store_lds || is_tess_factor) {
1480 LLVMValueRef dw_addr_chan =
1481 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1482 LLVMConstInt(ctx->ac.i32, chan, false), "");
1483 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1484 }
1485
1486 if (!is_tess_factor && writemask != 0xF)
1487 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1488 buf_addr, ctx->oc_lds,
1489 4 * (base + chan), 1, 0, true, false);
1490 }
1491
1492 if (writemask == 0xF) {
1493 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1494 buf_addr, ctx->oc_lds,
1495 (base * 4), 1, 0, true, false);
1496 }
1497 }
1498
1499 static LLVMValueRef
1500 load_tes_input(struct ac_shader_abi *abi,
1501 LLVMTypeRef type,
1502 LLVMValueRef vertex_index,
1503 LLVMValueRef param_index,
1504 unsigned const_index,
1505 unsigned location,
1506 unsigned driver_location,
1507 unsigned component,
1508 unsigned num_components,
1509 bool is_patch,
1510 bool is_compact,
1511 bool load_input)
1512 {
1513 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1514 LLVMValueRef buf_addr;
1515 LLVMValueRef result;
1516 unsigned param = shader_io_get_unique_index(location);
1517
1518 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1519 const_index -= 3;
1520 param++;
1521 }
1522
1523 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1524 is_compact, vertex_index, param_index);
1525
1526 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1527 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1528
1529 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1530 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1531 result = ac_trim_vector(&ctx->ac, result, num_components);
1532 return result;
1533 }
1534
1535 static LLVMValueRef
1536 load_gs_input(struct ac_shader_abi *abi,
1537 unsigned location,
1538 unsigned driver_location,
1539 unsigned component,
1540 unsigned num_components,
1541 unsigned vertex_index,
1542 unsigned const_index,
1543 LLVMTypeRef type)
1544 {
1545 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1546 LLVMValueRef vtx_offset;
1547 unsigned param, vtx_offset_param;
1548 LLVMValueRef value[4], result;
1549
1550 vtx_offset_param = vertex_index;
1551 assert(vtx_offset_param < 6);
1552 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1553 LLVMConstInt(ctx->ac.i32, 4, false), "");
1554
1555 param = shader_io_get_unique_index(location);
1556
1557 for (unsigned i = component; i < num_components + component; i++) {
1558 if (ctx->ac.chip_class >= GFX9) {
1559 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1560 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1561 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1562 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1563 } else {
1564 LLVMValueRef soffset =
1565 LLVMConstInt(ctx->ac.i32,
1566 (param * 4 + i + const_index) * 256,
1567 false);
1568
1569 value[i] = ac_build_buffer_load(&ctx->ac,
1570 ctx->esgs_ring, 1,
1571 ctx->ac.i32_0,
1572 vtx_offset, soffset,
1573 0, 1, 0, true, false);
1574
1575 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
1576 type, "");
1577 }
1578 }
1579 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1580 result = ac_to_integer(&ctx->ac, result);
1581 return result;
1582 }
1583
1584
1585 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1586 {
1587 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1588 ac_build_kill_if_false(&ctx->ac, visible);
1589 }
1590
1591 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1592 enum glsl_interp_mode interp, unsigned location)
1593 {
1594 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1595
1596 switch (interp) {
1597 case INTERP_MODE_FLAT:
1598 default:
1599 return NULL;
1600 case INTERP_MODE_SMOOTH:
1601 case INTERP_MODE_NONE:
1602 if (location == INTERP_CENTER)
1603 return ctx->persp_center;
1604 else if (location == INTERP_CENTROID)
1605 return ctx->persp_centroid;
1606 else if (location == INTERP_SAMPLE)
1607 return ctx->persp_sample;
1608 break;
1609 case INTERP_MODE_NOPERSPECTIVE:
1610 if (location == INTERP_CENTER)
1611 return ctx->linear_center;
1612 else if (location == INTERP_CENTROID)
1613 return ctx->linear_centroid;
1614 else if (location == INTERP_SAMPLE)
1615 return ctx->linear_sample;
1616 break;
1617 }
1618 return NULL;
1619 }
1620
1621 static uint32_t
1622 radv_get_sample_pos_offset(uint32_t num_samples)
1623 {
1624 uint32_t sample_pos_offset = 0;
1625
1626 switch (num_samples) {
1627 case 2:
1628 sample_pos_offset = 1;
1629 break;
1630 case 4:
1631 sample_pos_offset = 3;
1632 break;
1633 case 8:
1634 sample_pos_offset = 7;
1635 break;
1636 case 16:
1637 sample_pos_offset = 15;
1638 break;
1639 default:
1640 break;
1641 }
1642 return sample_pos_offset;
1643 }
1644
1645 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1646 LLVMValueRef sample_id)
1647 {
1648 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1649
1650 LLVMValueRef result;
1651 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1652
1653 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1654 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1655
1656 uint32_t sample_pos_offset =
1657 radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
1658
1659 sample_id =
1660 LLVMBuildAdd(ctx->ac.builder, sample_id,
1661 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
1662 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1663
1664 return result;
1665 }
1666
1667
1668 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1669 {
1670 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1671 uint8_t log2_ps_iter_samples;
1672
1673 if (ctx->shader_info->info.ps.force_persample) {
1674 log2_ps_iter_samples =
1675 util_logbase2(ctx->options->key.fs.num_samples);
1676 } else {
1677 log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
1678 }
1679
1680 /* The bit pattern matches that used by fixed function fragment
1681 * processing. */
1682 static const uint16_t ps_iter_masks[] = {
1683 0xffff, /* not used */
1684 0x5555,
1685 0x1111,
1686 0x0101,
1687 0x0001,
1688 };
1689 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1690
1691 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1692
1693 LLVMValueRef result, sample_id;
1694 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1695 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1696 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1697 return result;
1698 }
1699
1700
1701 static void
1702 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1703 {
1704 LLVMValueRef gs_next_vertex;
1705 LLVMValueRef can_emit;
1706 int idx;
1707 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1708
1709 assert(stream == 0);
1710
1711 /* Write vertex attribute values to GSVS ring */
1712 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1713 ctx->gs_next_vertex,
1714 "");
1715
1716 /* If this thread has already emitted the declared maximum number of
1717 * vertices, kill it: excessive vertex emissions are not supposed to
1718 * have any effect, and GS threads have no externally observable
1719 * effects other than emitting vertices.
1720 */
1721 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1722 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1723 ac_build_kill_if_false(&ctx->ac, can_emit);
1724
1725 /* loop num outputs */
1726 idx = 0;
1727 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1728 unsigned output_usage_mask =
1729 ctx->shader_info->info.gs.output_usage_mask[i];
1730 LLVMValueRef *out_ptr = &addrs[i * 4];
1731 int length = 4;
1732 int slot = idx;
1733 int slot_inc = 1;
1734
1735 if (!(ctx->output_mask & (1ull << i)))
1736 continue;
1737
1738 if (i == VARYING_SLOT_CLIP_DIST0) {
1739 /* pack clip and cull into a single set of slots */
1740 length = ctx->num_output_clips + ctx->num_output_culls;
1741 if (length > 4)
1742 slot_inc = 2;
1743 output_usage_mask = (1 << length) - 1;
1744 }
1745
1746 for (unsigned j = 0; j < length; j++) {
1747 if (!(output_usage_mask & (1 << j)))
1748 continue;
1749
1750 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1751 out_ptr[j], "");
1752 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1753 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1754 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1755
1756 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1757
1758 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1759 out_val, 1,
1760 voffset, ctx->gs2vs_offset, 0,
1761 1, 1, true, true);
1762 }
1763 idx += slot_inc;
1764 }
1765
1766 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1767 ctx->ac.i32_1, "");
1768 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1769
1770 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1771 }
1772
1773 static void
1774 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1775 {
1776 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1777 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1778 }
1779
1780 static LLVMValueRef
1781 load_tess_coord(struct ac_shader_abi *abi)
1782 {
1783 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1784
1785 LLVMValueRef coord[4] = {
1786 ctx->tes_u,
1787 ctx->tes_v,
1788 ctx->ac.f32_0,
1789 ctx->ac.f32_0,
1790 };
1791
1792 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1793 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1794 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1795
1796 return ac_build_gather_values(&ctx->ac, coord, 3);
1797 }
1798
1799 static LLVMValueRef
1800 load_patch_vertices_in(struct ac_shader_abi *abi)
1801 {
1802 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1803 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1804 }
1805
1806
1807 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1808 {
1809 return abi->base_vertex;
1810 }
1811
1812 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1813 LLVMValueRef buffer_ptr, bool write)
1814 {
1815 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1816 LLVMValueRef result;
1817
1818 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1819
1820 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1821 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1822
1823 return result;
1824 }
1825
1826 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1827 {
1828 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1829 LLVMValueRef result;
1830
1831 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1832
1833 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1834 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1835
1836 return result;
1837 }
1838
1839 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1840 unsigned descriptor_set,
1841 unsigned base_index,
1842 unsigned constant_index,
1843 LLVMValueRef index,
1844 enum ac_descriptor_type desc_type,
1845 bool image, bool write,
1846 bool bindless)
1847 {
1848 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1849 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1850 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1851 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1852 unsigned offset = binding->offset;
1853 unsigned stride = binding->size;
1854 unsigned type_size;
1855 LLVMBuilderRef builder = ctx->ac.builder;
1856 LLVMTypeRef type;
1857
1858 assert(base_index < layout->binding_count);
1859
1860 switch (desc_type) {
1861 case AC_DESC_IMAGE:
1862 type = ctx->ac.v8i32;
1863 type_size = 32;
1864 break;
1865 case AC_DESC_FMASK:
1866 type = ctx->ac.v8i32;
1867 offset += 32;
1868 type_size = 32;
1869 break;
1870 case AC_DESC_SAMPLER:
1871 type = ctx->ac.v4i32;
1872 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1873 offset += 64;
1874
1875 type_size = 16;
1876 break;
1877 case AC_DESC_BUFFER:
1878 type = ctx->ac.v4i32;
1879 type_size = 16;
1880 break;
1881 default:
1882 unreachable("invalid desc_type\n");
1883 }
1884
1885 offset += constant_index * stride;
1886
1887 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1888 (!index || binding->immutable_samplers_equal)) {
1889 if (binding->immutable_samplers_equal)
1890 constant_index = 0;
1891
1892 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1893
1894 LLVMValueRef constants[] = {
1895 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1896 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1897 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1898 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1899 };
1900 return ac_build_gather_values(&ctx->ac, constants, 4);
1901 }
1902
1903 assert(stride % type_size == 0);
1904
1905 if (!index)
1906 index = ctx->ac.i32_0;
1907
1908 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1909
1910 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1911 list = LLVMBuildPointerCast(builder, list,
1912 ac_array_in_const32_addr_space(type), "");
1913
1914 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1915 }
1916
1917 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1918 * so we may need to fix it up. */
1919 static LLVMValueRef
1920 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1921 unsigned adjustment,
1922 LLVMValueRef alpha)
1923 {
1924 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1925 return alpha;
1926
1927 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1928
1929 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1930 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1931 else
1932 alpha = ac_to_integer(&ctx->ac, alpha);
1933
1934 /* For the integer-like cases, do a natural sign extension.
1935 *
1936 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1937 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1938 * exponent.
1939 */
1940 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1941 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1942 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1943 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1944
1945 /* Convert back to the right type. */
1946 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1947 LLVMValueRef clamp;
1948 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1949 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1950 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1951 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1952 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1953 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1954 }
1955
1956 return alpha;
1957 }
1958
1959 static void
1960 handle_vs_input_decl(struct radv_shader_context *ctx,
1961 struct nir_variable *variable)
1962 {
1963 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1964 LLVMValueRef t_offset;
1965 LLVMValueRef t_list;
1966 LLVMValueRef input;
1967 LLVMValueRef buffer_index;
1968 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1969 uint8_t input_usage_mask =
1970 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1971 unsigned num_channels = util_last_bit(input_usage_mask);
1972
1973 variable->data.driver_location = variable->data.location * 4;
1974
1975 for (unsigned i = 0; i < attrib_count; ++i) {
1976 LLVMValueRef output[4];
1977 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1978
1979 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1980 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
1981
1982 if (divisor) {
1983 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
1984 ctx->abi.start_instance, "");
1985
1986 if (divisor != 1) {
1987 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1988 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1989 }
1990
1991 if (ctx->options->key.vs.as_ls) {
1992 ctx->shader_info->vs.vgpr_comp_cnt =
1993 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1994 } else {
1995 ctx->shader_info->vs.vgpr_comp_cnt =
1996 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1997 }
1998 } else {
1999 buffer_index = ctx->ac.i32_0;
2000 }
2001 } else
2002 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
2003 ctx->abi.base_vertex, "");
2004 t_offset = LLVMConstInt(ctx->ac.i32, attrib_index, false);
2005
2006 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
2007
2008 input = ac_build_buffer_load_format(&ctx->ac, t_list,
2009 buffer_index,
2010 ctx->ac.i32_0,
2011 num_channels, false, true);
2012
2013 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
2014
2015 for (unsigned chan = 0; chan < 4; chan++) {
2016 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2017 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
2018 }
2019
2020 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
2021 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
2022
2023 for (unsigned chan = 0; chan < 4; chan++) {
2024 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] =
2025 ac_to_integer(&ctx->ac, output[chan]);
2026 }
2027 }
2028 }
2029
2030 static void interp_fs_input(struct radv_shader_context *ctx,
2031 unsigned attr,
2032 LLVMValueRef interp_param,
2033 LLVMValueRef prim_mask,
2034 LLVMValueRef result[4])
2035 {
2036 LLVMValueRef attr_number;
2037 unsigned chan;
2038 LLVMValueRef i, j;
2039 bool interp = interp_param != NULL;
2040
2041 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
2042
2043 /* fs.constant returns the param from the middle vertex, so it's not
2044 * really useful for flat shading. It's meant to be used for custom
2045 * interpolation (but the intrinsic can't fetch from the other two
2046 * vertices).
2047 *
2048 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2049 * to do the right thing. The only reason we use fs.constant is that
2050 * fs.interp cannot be used on integers, because they can be equal
2051 * to NaN.
2052 */
2053 if (interp) {
2054 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
2055 ctx->ac.v2f32, "");
2056
2057 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2058 ctx->ac.i32_0, "");
2059 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2060 ctx->ac.i32_1, "");
2061 }
2062
2063 for (chan = 0; chan < 4; chan++) {
2064 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2065
2066 if (interp) {
2067 result[chan] = ac_build_fs_interp(&ctx->ac,
2068 llvm_chan,
2069 attr_number,
2070 prim_mask, i, j);
2071 } else {
2072 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2073 LLVMConstInt(ctx->ac.i32, 2, false),
2074 llvm_chan,
2075 attr_number,
2076 prim_mask);
2077 }
2078 }
2079 }
2080
2081 static void
2082 handle_fs_input_decl(struct radv_shader_context *ctx,
2083 struct nir_variable *variable)
2084 {
2085 int idx = variable->data.location;
2086 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2087 LLVMValueRef interp;
2088
2089 variable->data.driver_location = idx * 4;
2090 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
2091
2092 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
2093 unsigned interp_type;
2094 if (variable->data.sample)
2095 interp_type = INTERP_SAMPLE;
2096 else if (variable->data.centroid)
2097 interp_type = INTERP_CENTROID;
2098 else
2099 interp_type = INTERP_CENTER;
2100
2101 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
2102 } else
2103 interp = NULL;
2104
2105 for (unsigned i = 0; i < attrib_count; ++i)
2106 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
2107
2108 }
2109
2110 static void
2111 handle_vs_inputs(struct radv_shader_context *ctx,
2112 struct nir_shader *nir) {
2113 nir_foreach_variable(variable, &nir->inputs)
2114 handle_vs_input_decl(ctx, variable);
2115 }
2116
2117 static void
2118 prepare_interp_optimize(struct radv_shader_context *ctx,
2119 struct nir_shader *nir)
2120 {
2121 bool uses_center = false;
2122 bool uses_centroid = false;
2123 nir_foreach_variable(variable, &nir->inputs) {
2124 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2125 variable->data.sample)
2126 continue;
2127
2128 if (variable->data.centroid)
2129 uses_centroid = true;
2130 else
2131 uses_center = true;
2132 }
2133
2134 if (uses_center && uses_centroid) {
2135 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2136 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
2137 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
2138 }
2139 }
2140
2141 static void
2142 handle_fs_inputs(struct radv_shader_context *ctx,
2143 struct nir_shader *nir)
2144 {
2145 prepare_interp_optimize(ctx, nir);
2146
2147 nir_foreach_variable(variable, &nir->inputs)
2148 handle_fs_input_decl(ctx, variable);
2149
2150 unsigned index = 0;
2151
2152 if (ctx->shader_info->info.ps.uses_input_attachments ||
2153 ctx->shader_info->info.needs_multiview_view_index)
2154 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
2155
2156 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
2157 LLVMValueRef interp_param;
2158 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
2159
2160 if (!(ctx->input_mask & (1ull << i)))
2161 continue;
2162
2163 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
2164 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
2165 interp_param = *inputs;
2166 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
2167 inputs);
2168
2169 if (!interp_param)
2170 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
2171 ++index;
2172 } else if (i == VARYING_SLOT_POS) {
2173 for(int i = 0; i < 3; ++i)
2174 inputs[i] = ctx->abi.frag_pos[i];
2175
2176 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2177 ctx->abi.frag_pos[3]);
2178 }
2179 }
2180 ctx->shader_info->fs.num_interp = index;
2181 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
2182
2183 if (ctx->shader_info->info.needs_multiview_view_index)
2184 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2185 }
2186
2187 static void
2188 scan_shader_output_decl(struct radv_shader_context *ctx,
2189 struct nir_variable *variable,
2190 struct nir_shader *shader,
2191 gl_shader_stage stage)
2192 {
2193 int idx = variable->data.location + variable->data.index;
2194 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2195 uint64_t mask_attribs;
2196
2197 variable->data.driver_location = idx * 4;
2198
2199 /* tess ctrl has it's own load/store paths for outputs */
2200 if (stage == MESA_SHADER_TESS_CTRL)
2201 return;
2202
2203 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2204 if (stage == MESA_SHADER_VERTEX ||
2205 stage == MESA_SHADER_TESS_EVAL ||
2206 stage == MESA_SHADER_GEOMETRY) {
2207 if (idx == VARYING_SLOT_CLIP_DIST0) {
2208 int length = shader->info.clip_distance_array_size +
2209 shader->info.cull_distance_array_size;
2210 if (stage == MESA_SHADER_VERTEX) {
2211 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2212 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2213 }
2214 if (stage == MESA_SHADER_TESS_EVAL) {
2215 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2216 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2217 }
2218
2219 if (length > 4)
2220 attrib_count = 2;
2221 else
2222 attrib_count = 1;
2223 mask_attribs = 1ull << idx;
2224 }
2225 }
2226
2227 ctx->output_mask |= mask_attribs;
2228 }
2229
2230
2231 /* Initialize arguments for the shader export intrinsic */
2232 static void
2233 si_llvm_init_export_args(struct radv_shader_context *ctx,
2234 LLVMValueRef *values,
2235 unsigned enabled_channels,
2236 unsigned target,
2237 struct ac_export_args *args)
2238 {
2239 /* Specify the channels that are enabled. */
2240 args->enabled_channels = enabled_channels;
2241
2242 /* Specify whether the EXEC mask represents the valid mask */
2243 args->valid_mask = 0;
2244
2245 /* Specify whether this is the last export */
2246 args->done = 0;
2247
2248 /* Specify the target we are exporting */
2249 args->target = target;
2250
2251 args->compr = false;
2252 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2253 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2254 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2255 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2256
2257 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2258 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2259 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2260 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2261 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2262 unsigned chan;
2263
2264 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2265 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2266 unsigned bits, bool hi) = NULL;
2267
2268 switch(col_format) {
2269 case V_028714_SPI_SHADER_ZERO:
2270 args->enabled_channels = 0; /* writemask */
2271 args->target = V_008DFC_SQ_EXP_NULL;
2272 break;
2273
2274 case V_028714_SPI_SHADER_32_R:
2275 args->enabled_channels = 1;
2276 args->out[0] = values[0];
2277 break;
2278
2279 case V_028714_SPI_SHADER_32_GR:
2280 args->enabled_channels = 0x3;
2281 args->out[0] = values[0];
2282 args->out[1] = values[1];
2283 break;
2284
2285 case V_028714_SPI_SHADER_32_AR:
2286 args->enabled_channels = 0x9;
2287 args->out[0] = values[0];
2288 args->out[3] = values[3];
2289 break;
2290
2291 case V_028714_SPI_SHADER_FP16_ABGR:
2292 args->enabled_channels = 0x5;
2293 packf = ac_build_cvt_pkrtz_f16;
2294 break;
2295
2296 case V_028714_SPI_SHADER_UNORM16_ABGR:
2297 args->enabled_channels = 0x5;
2298 packf = ac_build_cvt_pknorm_u16;
2299 break;
2300
2301 case V_028714_SPI_SHADER_SNORM16_ABGR:
2302 args->enabled_channels = 0x5;
2303 packf = ac_build_cvt_pknorm_i16;
2304 break;
2305
2306 case V_028714_SPI_SHADER_UINT16_ABGR:
2307 args->enabled_channels = 0x5;
2308 packi = ac_build_cvt_pk_u16;
2309 break;
2310
2311 case V_028714_SPI_SHADER_SINT16_ABGR:
2312 args->enabled_channels = 0x5;
2313 packi = ac_build_cvt_pk_i16;
2314 break;
2315
2316 default:
2317 case V_028714_SPI_SHADER_32_ABGR:
2318 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2319 break;
2320 }
2321
2322 /* Pack f16 or norm_i16/u16. */
2323 if (packf) {
2324 for (chan = 0; chan < 2; chan++) {
2325 LLVMValueRef pack_args[2] = {
2326 values[2 * chan],
2327 values[2 * chan + 1]
2328 };
2329 LLVMValueRef packed;
2330
2331 packed = packf(&ctx->ac, pack_args);
2332 args->out[chan] = ac_to_float(&ctx->ac, packed);
2333 }
2334 args->compr = 1; /* COMPR flag */
2335 }
2336
2337 /* Pack i16/u16. */
2338 if (packi) {
2339 for (chan = 0; chan < 2; chan++) {
2340 LLVMValueRef pack_args[2] = {
2341 ac_to_integer(&ctx->ac, values[2 * chan]),
2342 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2343 };
2344 LLVMValueRef packed;
2345
2346 packed = packi(&ctx->ac, pack_args,
2347 is_int8 ? 8 : is_int10 ? 10 : 16,
2348 chan == 1);
2349 args->out[chan] = ac_to_float(&ctx->ac, packed);
2350 }
2351 args->compr = 1; /* COMPR flag */
2352 }
2353 return;
2354 }
2355
2356 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2357
2358 for (unsigned i = 0; i < 4; ++i) {
2359 if (!(args->enabled_channels & (1 << i)))
2360 continue;
2361
2362 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2363 }
2364 }
2365
2366 static void
2367 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2368 LLVMValueRef *values, unsigned enabled_channels)
2369 {
2370 struct ac_export_args args;
2371
2372 si_llvm_init_export_args(ctx, values, enabled_channels,
2373 V_008DFC_SQ_EXP_PARAM + index, &args);
2374 ac_build_export(&ctx->ac, &args);
2375 }
2376
2377 static LLVMValueRef
2378 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2379 {
2380 LLVMValueRef output =
2381 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2382
2383 return LLVMBuildLoad(ctx->ac.builder, output, "");
2384 }
2385
2386 static void
2387 handle_vs_outputs_post(struct radv_shader_context *ctx,
2388 bool export_prim_id, bool export_layer_id,
2389 struct radv_vs_output_info *outinfo)
2390 {
2391 uint32_t param_count = 0;
2392 unsigned target;
2393 unsigned pos_idx, num_pos_exports = 0;
2394 struct ac_export_args args, pos_args[4] = {};
2395 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2396 int i;
2397
2398 if (ctx->options->key.has_multiview_view_index) {
2399 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2400 if(!*tmp_out) {
2401 for(unsigned i = 0; i < 4; ++i)
2402 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2403 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2404 }
2405
2406 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2407 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2408 }
2409
2410 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2411 sizeof(outinfo->vs_output_param_offset));
2412
2413 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2414 LLVMValueRef slots[8];
2415 unsigned j;
2416
2417 if (outinfo->cull_dist_mask)
2418 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2419
2420 i = VARYING_SLOT_CLIP_DIST0;
2421 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
2422 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2423
2424 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
2425 slots[i] = LLVMGetUndef(ctx->ac.f32);
2426
2427 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
2428 target = V_008DFC_SQ_EXP_POS + 3;
2429 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2430 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2431 &args, sizeof(args));
2432 }
2433
2434 target = V_008DFC_SQ_EXP_POS + 2;
2435 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2436 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2437 &args, sizeof(args));
2438
2439 }
2440
2441 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2442 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2443 for (unsigned j = 0; j < 4; j++)
2444 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2445 }
2446 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2447
2448 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2449 outinfo->writes_pointsize = true;
2450 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2451 }
2452
2453 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2454 outinfo->writes_layer = true;
2455 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2456 }
2457
2458 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2459 outinfo->writes_viewport_index = true;
2460 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2461 }
2462
2463 if (outinfo->writes_pointsize ||
2464 outinfo->writes_layer ||
2465 outinfo->writes_viewport_index) {
2466 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2467 (outinfo->writes_layer == true ? 4 : 0));
2468 pos_args[1].valid_mask = 0;
2469 pos_args[1].done = 0;
2470 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2471 pos_args[1].compr = 0;
2472 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2473 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2474 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2475 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2476
2477 if (outinfo->writes_pointsize == true)
2478 pos_args[1].out[0] = psize_value;
2479 if (outinfo->writes_layer == true)
2480 pos_args[1].out[2] = layer_value;
2481 if (outinfo->writes_viewport_index == true) {
2482 if (ctx->options->chip_class >= GFX9) {
2483 /* GFX9 has the layer in out.z[10:0] and the viewport
2484 * index in out.z[19:16].
2485 */
2486 LLVMValueRef v = viewport_index_value;
2487 v = ac_to_integer(&ctx->ac, v);
2488 v = LLVMBuildShl(ctx->ac.builder, v,
2489 LLVMConstInt(ctx->ac.i32, 16, false),
2490 "");
2491 v = LLVMBuildOr(ctx->ac.builder, v,
2492 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2493
2494 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2495 pos_args[1].enabled_channels |= 1 << 2;
2496 } else {
2497 pos_args[1].out[3] = viewport_index_value;
2498 pos_args[1].enabled_channels |= 1 << 3;
2499 }
2500 }
2501 }
2502 for (i = 0; i < 4; i++) {
2503 if (pos_args[i].out[0])
2504 num_pos_exports++;
2505 }
2506
2507 pos_idx = 0;
2508 for (i = 0; i < 4; i++) {
2509 if (!pos_args[i].out[0])
2510 continue;
2511
2512 /* Specify the target we are exporting */
2513 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2514 if (pos_idx == num_pos_exports)
2515 pos_args[i].done = 1;
2516 ac_build_export(&ctx->ac, &pos_args[i]);
2517 }
2518
2519 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2520 LLVMValueRef values[4];
2521 if (!(ctx->output_mask & (1ull << i)))
2522 continue;
2523
2524 if (i != VARYING_SLOT_LAYER &&
2525 i != VARYING_SLOT_PRIMITIVE_ID &&
2526 i < VARYING_SLOT_VAR0)
2527 continue;
2528
2529 for (unsigned j = 0; j < 4; j++)
2530 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2531
2532 unsigned output_usage_mask;
2533
2534 if (ctx->stage == MESA_SHADER_VERTEX &&
2535 !ctx->is_gs_copy_shader) {
2536 output_usage_mask =
2537 ctx->shader_info->info.vs.output_usage_mask[i];
2538 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2539 output_usage_mask =
2540 ctx->shader_info->info.tes.output_usage_mask[i];
2541 } else {
2542 assert(ctx->is_gs_copy_shader);
2543 output_usage_mask =
2544 ctx->shader_info->info.gs.output_usage_mask[i];
2545 }
2546
2547 radv_export_param(ctx, param_count, values, output_usage_mask);
2548
2549 outinfo->vs_output_param_offset[i] = param_count++;
2550 }
2551
2552 if (export_prim_id) {
2553 LLVMValueRef values[4];
2554
2555 values[0] = ctx->vs_prim_id;
2556 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2557 ctx->shader_info->vs.vgpr_comp_cnt);
2558 for (unsigned j = 1; j < 4; j++)
2559 values[j] = ctx->ac.f32_0;
2560
2561 radv_export_param(ctx, param_count, values, 0x1);
2562
2563 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2564 outinfo->export_prim_id = true;
2565 }
2566
2567 if (export_layer_id && layer_value) {
2568 LLVMValueRef values[4];
2569
2570 values[0] = layer_value;
2571 for (unsigned j = 1; j < 4; j++)
2572 values[j] = ctx->ac.f32_0;
2573
2574 radv_export_param(ctx, param_count, values, 0x1);
2575
2576 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2577 }
2578
2579 outinfo->pos_exports = num_pos_exports;
2580 outinfo->param_exports = param_count;
2581 }
2582
2583 static void
2584 handle_es_outputs_post(struct radv_shader_context *ctx,
2585 struct radv_es_output_info *outinfo)
2586 {
2587 int j;
2588 uint64_t max_output_written = 0;
2589 LLVMValueRef lds_base = NULL;
2590
2591 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2592 int param_index;
2593 int length = 4;
2594
2595 if (!(ctx->output_mask & (1ull << i)))
2596 continue;
2597
2598 if (i == VARYING_SLOT_CLIP_DIST0)
2599 length = ctx->num_output_clips + ctx->num_output_culls;
2600
2601 param_index = shader_io_get_unique_index(i);
2602
2603 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2604 }
2605
2606 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2607
2608 if (ctx->ac.chip_class >= GFX9) {
2609 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2610 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2611 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2612 LLVMConstInt(ctx->ac.i32, 24, false),
2613 LLVMConstInt(ctx->ac.i32, 4, false), false);
2614 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2615 LLVMBuildMul(ctx->ac.builder, wave_idx,
2616 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2617 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2618 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2619 }
2620
2621 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2622 LLVMValueRef dw_addr = NULL;
2623 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2624 unsigned output_usage_mask;
2625 int param_index;
2626 int length = 4;
2627
2628 if (!(ctx->output_mask & (1ull << i)))
2629 continue;
2630
2631 if (ctx->stage == MESA_SHADER_VERTEX) {
2632 output_usage_mask =
2633 ctx->shader_info->info.vs.output_usage_mask[i];
2634 } else {
2635 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2636 output_usage_mask =
2637 ctx->shader_info->info.tes.output_usage_mask[i];
2638 }
2639
2640 if (i == VARYING_SLOT_CLIP_DIST0) {
2641 length = ctx->num_output_clips + ctx->num_output_culls;
2642 output_usage_mask = (1 << length) - 1;
2643 }
2644
2645 param_index = shader_io_get_unique_index(i);
2646
2647 if (lds_base) {
2648 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2649 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2650 "");
2651 }
2652
2653 for (j = 0; j < length; j++) {
2654 if (!(output_usage_mask & (1 << j)))
2655 continue;
2656
2657 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2658 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2659
2660 if (ctx->ac.chip_class >= GFX9) {
2661 LLVMValueRef dw_addr_offset =
2662 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2663 LLVMConstInt(ctx->ac.i32,
2664 j, false), "");
2665
2666 ac_lds_store(&ctx->ac, dw_addr_offset,
2667 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2668 } else {
2669 ac_build_buffer_store_dword(&ctx->ac,
2670 ctx->esgs_ring,
2671 out_val, 1,
2672 NULL, ctx->es2gs_offset,
2673 (4 * param_index + j) * 4,
2674 1, 1, true, true);
2675 }
2676 }
2677 }
2678 }
2679
2680 static void
2681 handle_ls_outputs_post(struct radv_shader_context *ctx)
2682 {
2683 LLVMValueRef vertex_id = ctx->rel_auto_id;
2684 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2685 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2686 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2687 vertex_dw_stride, "");
2688
2689 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2690 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2691 int length = 4;
2692
2693 if (!(ctx->output_mask & (1ull << i)))
2694 continue;
2695
2696 if (i == VARYING_SLOT_CLIP_DIST0)
2697 length = ctx->num_output_clips + ctx->num_output_culls;
2698 int param = shader_io_get_unique_index(i);
2699 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2700 LLVMConstInt(ctx->ac.i32, param * 4, false),
2701 "");
2702 for (unsigned j = 0; j < length; j++) {
2703 ac_lds_store(&ctx->ac, dw_addr,
2704 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2705 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2706 }
2707 }
2708 }
2709
2710 static void
2711 write_tess_factors(struct radv_shader_context *ctx)
2712 {
2713 unsigned stride, outer_comps, inner_comps;
2714 struct ac_build_if_state if_ctx, inner_if_ctx;
2715 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2716 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2717 unsigned tess_inner_index = 0, tess_outer_index;
2718 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2719 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2720 int i;
2721 ac_emit_barrier(&ctx->ac, ctx->stage);
2722
2723 switch (ctx->options->key.tcs.primitive_mode) {
2724 case GL_ISOLINES:
2725 stride = 2;
2726 outer_comps = 2;
2727 inner_comps = 0;
2728 break;
2729 case GL_TRIANGLES:
2730 stride = 4;
2731 outer_comps = 3;
2732 inner_comps = 1;
2733 break;
2734 case GL_QUADS:
2735 stride = 6;
2736 outer_comps = 4;
2737 inner_comps = 2;
2738 break;
2739 default:
2740 return;
2741 }
2742
2743 ac_nir_build_if(&if_ctx, ctx,
2744 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2745 invocation_id, ctx->ac.i32_0, ""));
2746
2747 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2748
2749 if (inner_comps) {
2750 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2751 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2752 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2753 }
2754
2755 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2756 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2757 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2758
2759 for (i = 0; i < 4; i++) {
2760 inner[i] = LLVMGetUndef(ctx->ac.i32);
2761 outer[i] = LLVMGetUndef(ctx->ac.i32);
2762 }
2763
2764 // LINES reversal
2765 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2766 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2767 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2768 ctx->ac.i32_1, "");
2769 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2770 } else {
2771 for (i = 0; i < outer_comps; i++) {
2772 outer[i] = out[i] =
2773 ac_lds_load(&ctx->ac, lds_outer);
2774 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2775 ctx->ac.i32_1, "");
2776 }
2777 for (i = 0; i < inner_comps; i++) {
2778 inner[i] = out[outer_comps+i] =
2779 ac_lds_load(&ctx->ac, lds_inner);
2780 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2781 ctx->ac.i32_1, "");
2782 }
2783 }
2784
2785 /* Convert the outputs to vectors for stores. */
2786 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2787 vec1 = NULL;
2788
2789 if (stride > 4)
2790 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2791
2792
2793 buffer = ctx->hs_ring_tess_factor;
2794 tf_base = ctx->tess_factor_offset;
2795 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2796 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2797 unsigned tf_offset = 0;
2798
2799 if (ctx->options->chip_class <= VI) {
2800 ac_nir_build_if(&inner_if_ctx, ctx,
2801 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2802 rel_patch_id, ctx->ac.i32_0, ""));
2803
2804 /* Store the dynamic HS control word. */
2805 ac_build_buffer_store_dword(&ctx->ac, buffer,
2806 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2807 1, ctx->ac.i32_0, tf_base,
2808 0, 1, 0, true, false);
2809 tf_offset += 4;
2810
2811 ac_nir_build_endif(&inner_if_ctx);
2812 }
2813
2814 /* Store the tessellation factors. */
2815 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2816 MIN2(stride, 4), byteoffset, tf_base,
2817 tf_offset, 1, 0, true, false);
2818 if (vec1)
2819 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2820 stride - 4, byteoffset, tf_base,
2821 16 + tf_offset, 1, 0, true, false);
2822
2823 //store to offchip for TES to read - only if TES reads them
2824 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2825 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2826 LLVMValueRef tf_inner_offset;
2827 unsigned param_outer, param_inner;
2828
2829 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2830 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2831 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2832
2833 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2834 util_next_power_of_two(outer_comps));
2835
2836 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2837 outer_comps, tf_outer_offset,
2838 ctx->oc_lds, 0, 1, 0, true, false);
2839 if (inner_comps) {
2840 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2841 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2842 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2843
2844 inner_vec = inner_comps == 1 ? inner[0] :
2845 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2846 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2847 inner_comps, tf_inner_offset,
2848 ctx->oc_lds, 0, 1, 0, true, false);
2849 }
2850 }
2851 ac_nir_build_endif(&if_ctx);
2852 }
2853
2854 static void
2855 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2856 {
2857 write_tess_factors(ctx);
2858 }
2859
2860 static bool
2861 si_export_mrt_color(struct radv_shader_context *ctx,
2862 LLVMValueRef *color, unsigned index,
2863 struct ac_export_args *args)
2864 {
2865 /* Export */
2866 si_llvm_init_export_args(ctx, color, 0xf,
2867 V_008DFC_SQ_EXP_MRT + index, args);
2868 if (!args->enabled_channels)
2869 return false; /* unnecessary NULL export */
2870
2871 return true;
2872 }
2873
2874 static void
2875 radv_export_mrt_z(struct radv_shader_context *ctx,
2876 LLVMValueRef depth, LLVMValueRef stencil,
2877 LLVMValueRef samplemask)
2878 {
2879 struct ac_export_args args;
2880
2881 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2882
2883 ac_build_export(&ctx->ac, &args);
2884 }
2885
2886 static void
2887 handle_fs_outputs_post(struct radv_shader_context *ctx)
2888 {
2889 unsigned index = 0;
2890 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2891 struct ac_export_args color_args[8];
2892
2893 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2894 LLVMValueRef values[4];
2895
2896 if (!(ctx->output_mask & (1ull << i)))
2897 continue;
2898
2899 if (i < FRAG_RESULT_DATA0)
2900 continue;
2901
2902 for (unsigned j = 0; j < 4; j++)
2903 values[j] = ac_to_float(&ctx->ac,
2904 radv_load_output(ctx, i, j));
2905
2906 bool ret = si_export_mrt_color(ctx, values,
2907 i - FRAG_RESULT_DATA0,
2908 &color_args[index]);
2909 if (ret)
2910 index++;
2911 }
2912
2913 /* Process depth, stencil, samplemask. */
2914 if (ctx->shader_info->info.ps.writes_z) {
2915 depth = ac_to_float(&ctx->ac,
2916 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
2917 }
2918 if (ctx->shader_info->info.ps.writes_stencil) {
2919 stencil = ac_to_float(&ctx->ac,
2920 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
2921 }
2922 if (ctx->shader_info->info.ps.writes_sample_mask) {
2923 samplemask = ac_to_float(&ctx->ac,
2924 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
2925 }
2926
2927 /* Set the DONE bit on last non-null color export only if Z isn't
2928 * exported.
2929 */
2930 if (index > 0 &&
2931 !ctx->shader_info->info.ps.writes_z &&
2932 !ctx->shader_info->info.ps.writes_stencil &&
2933 !ctx->shader_info->info.ps.writes_sample_mask) {
2934 unsigned last = index - 1;
2935
2936 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
2937 color_args[last].done = 1; /* DONE bit */
2938 }
2939
2940 /* Export PS outputs. */
2941 for (unsigned i = 0; i < index; i++)
2942 ac_build_export(&ctx->ac, &color_args[i]);
2943
2944 if (depth || stencil || samplemask)
2945 radv_export_mrt_z(ctx, depth, stencil, samplemask);
2946 else if (!index)
2947 ac_build_export_null(&ctx->ac);
2948 }
2949
2950 static void
2951 emit_gs_epilogue(struct radv_shader_context *ctx)
2952 {
2953 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
2954 }
2955
2956 static void
2957 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
2958 LLVMValueRef *addrs)
2959 {
2960 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2961
2962 switch (ctx->stage) {
2963 case MESA_SHADER_VERTEX:
2964 if (ctx->options->key.vs.as_ls)
2965 handle_ls_outputs_post(ctx);
2966 else if (ctx->options->key.vs.as_es)
2967 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
2968 else
2969 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
2970 ctx->options->key.vs.export_layer_id,
2971 &ctx->shader_info->vs.outinfo);
2972 break;
2973 case MESA_SHADER_FRAGMENT:
2974 handle_fs_outputs_post(ctx);
2975 break;
2976 case MESA_SHADER_GEOMETRY:
2977 emit_gs_epilogue(ctx);
2978 break;
2979 case MESA_SHADER_TESS_CTRL:
2980 handle_tcs_outputs_post(ctx);
2981 break;
2982 case MESA_SHADER_TESS_EVAL:
2983 if (ctx->options->key.tes.as_es)
2984 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
2985 else
2986 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
2987 ctx->options->key.tes.export_layer_id,
2988 &ctx->shader_info->tes.outinfo);
2989 break;
2990 default:
2991 break;
2992 }
2993 }
2994
2995 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
2996 const struct radv_nir_compiler_options *options)
2997 {
2998 LLVMPassManagerRef passmgr;
2999
3000 passmgr = ac_create_passmgr(NULL, options->check_ir);
3001
3002 LLVMRunPassManager(passmgr, ctx->ac.module);
3003 LLVMDisposeBuilder(ctx->ac.builder);
3004 LLVMDisposePassManager(passmgr);
3005
3006 ac_llvm_context_dispose(&ctx->ac);
3007 }
3008
3009 static void
3010 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3011 {
3012 struct radv_vs_output_info *outinfo;
3013
3014 switch (ctx->stage) {
3015 case MESA_SHADER_FRAGMENT:
3016 case MESA_SHADER_COMPUTE:
3017 case MESA_SHADER_TESS_CTRL:
3018 case MESA_SHADER_GEOMETRY:
3019 return;
3020 case MESA_SHADER_VERTEX:
3021 if (ctx->options->key.vs.as_ls ||
3022 ctx->options->key.vs.as_es)
3023 return;
3024 outinfo = &ctx->shader_info->vs.outinfo;
3025 break;
3026 case MESA_SHADER_TESS_EVAL:
3027 if (ctx->options->key.vs.as_es)
3028 return;
3029 outinfo = &ctx->shader_info->tes.outinfo;
3030 break;
3031 default:
3032 unreachable("Unhandled shader type");
3033 }
3034
3035 ac_optimize_vs_outputs(&ctx->ac,
3036 ctx->main_function,
3037 outinfo->vs_output_param_offset,
3038 VARYING_SLOT_MAX,
3039 &outinfo->param_exports);
3040 }
3041
3042 static void
3043 ac_setup_rings(struct radv_shader_context *ctx)
3044 {
3045 if (ctx->options->chip_class <= VI &&
3046 (ctx->stage == MESA_SHADER_GEOMETRY ||
3047 ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
3048 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3049 : RING_ESGS_VS;
3050 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3051
3052 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3053 ctx->ring_offsets,
3054 offset);
3055 }
3056
3057 if (ctx->is_gs_copy_shader) {
3058 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
3059 }
3060 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3061 LLVMValueRef tmp;
3062 uint32_t num_entries = 64;
3063 LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size, false);
3064 LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size << 16, false);
3065 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
3066
3067 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
3068
3069 tmp = LLVMConstInt(ctx->ac.i32, num_entries, false);
3070 if (ctx->options->chip_class >= VI)
3071 tmp = LLVMBuildMul(ctx->ac.builder, gsvs_ring_stride, tmp, "");
3072 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
3073 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
3074 tmp = LLVMBuildOr(ctx->ac.builder, tmp, gsvs_ring_desc, "");
3075 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
3076 }
3077
3078 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3079 ctx->stage == MESA_SHADER_TESS_EVAL) {
3080 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3081 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3082 }
3083 }
3084
3085 static unsigned
3086 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
3087 const struct nir_shader *nir)
3088 {
3089 switch (nir->info.stage) {
3090 case MESA_SHADER_TESS_CTRL:
3091 return chip_class >= CIK ? 128 : 64;
3092 case MESA_SHADER_GEOMETRY:
3093 return chip_class >= GFX9 ? 128 : 64;
3094 case MESA_SHADER_COMPUTE:
3095 break;
3096 default:
3097 return 0;
3098 }
3099
3100 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
3101 nir->info.cs.local_size[1] *
3102 nir->info.cs.local_size[2];
3103 return max_workgroup_size;
3104 }
3105
3106 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3107 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3108 {
3109 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3110 LLVMConstInt(ctx->ac.i32, 8, false),
3111 LLVMConstInt(ctx->ac.i32, 8, false), false);
3112 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3113 ctx->ac.i32_0, "");
3114 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
3115 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
3116 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3117 }
3118
3119 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3120 {
3121 for(int i = 5; i >= 0; --i) {
3122 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3123 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
3124 LLVMConstInt(ctx->ac.i32, 16, false), false);
3125 }
3126
3127 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3128 LLVMConstInt(ctx->ac.i32, 16, false),
3129 LLVMConstInt(ctx->ac.i32, 8, false), false);
3130 }
3131
3132
3133 static
3134 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
3135 struct nir_shader *const *shaders,
3136 int shader_count,
3137 struct radv_shader_variant_info *shader_info,
3138 const struct radv_nir_compiler_options *options)
3139 {
3140 struct radv_shader_context ctx = {0};
3141 unsigned i;
3142 ctx.options = options;
3143 ctx.shader_info = shader_info;
3144 ctx.context = LLVMContextCreate();
3145
3146 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3147 options->family);
3148 ctx.ac.module = ac_create_module(tm, ctx.context);
3149
3150 enum ac_float_mode float_mode =
3151 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3152 AC_FLOAT_MODE_DEFAULT;
3153
3154 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3155
3156 memset(shader_info, 0, sizeof(*shader_info));
3157
3158 for(int i = 0; i < shader_count; ++i)
3159 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3160
3161 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3162 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3163 for (i = 0; i < AC_UD_MAX_UD; i++)
3164 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3165
3166 ctx.max_workgroup_size = 0;
3167 for (int i = 0; i < shader_count; ++i) {
3168 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3169 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3170 shaders[i]));
3171 }
3172
3173 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3174 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3175
3176 ctx.abi.inputs = &ctx.inputs[0];
3177 ctx.abi.emit_outputs = handle_shader_outputs_post;
3178 ctx.abi.emit_vertex = visit_emit_vertex;
3179 ctx.abi.load_ubo = radv_load_ubo;
3180 ctx.abi.load_ssbo = radv_load_ssbo;
3181 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3182 ctx.abi.load_resource = radv_load_resource;
3183 ctx.abi.clamp_shadow_reference = false;
3184 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9;
3185
3186 if (shader_count >= 2)
3187 ac_init_exec_full_mask(&ctx.ac);
3188
3189 if (ctx.ac.chip_class == GFX9 &&
3190 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3191 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3192
3193 for(int i = 0; i < shader_count; ++i) {
3194 ctx.stage = shaders[i]->info.stage;
3195 ctx.output_mask = 0;
3196 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3197 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3198
3199 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3200 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3201 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3202 ctx.abi.load_inputs = load_gs_input;
3203 ctx.abi.emit_primitive = visit_end_primitive;
3204 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3205 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3206 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3207 ctx.abi.load_tess_varyings = load_tcs_varyings;
3208 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3209 ctx.abi.store_tcs_outputs = store_tcs_output;
3210 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3211 if (shader_count == 1)
3212 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3213 else
3214 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3215 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3216 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3217 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3218 ctx.abi.load_tess_varyings = load_tes_input;
3219 ctx.abi.load_tess_coord = load_tess_coord;
3220 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3221 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3222 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3223 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3224 if (shader_info->info.vs.needs_instance_id) {
3225 if (ctx.options->key.vs.as_ls) {
3226 ctx.shader_info->vs.vgpr_comp_cnt =
3227 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3228 } else {
3229 ctx.shader_info->vs.vgpr_comp_cnt =
3230 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3231 }
3232 }
3233 ctx.abi.load_base_vertex = radv_load_base_vertex;
3234 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3235 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3236 ctx.abi.lookup_interp_param = lookup_interp_param;
3237 ctx.abi.load_sample_position = load_sample_position;
3238 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3239 ctx.abi.emit_kill = radv_emit_kill;
3240 }
3241
3242 if (i)
3243 ac_emit_barrier(&ctx.ac, ctx.stage);
3244
3245 nir_foreach_variable(variable, &shaders[i]->outputs)
3246 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3247
3248 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3249 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3250 shaders[i]->info.cull_distance_array_size > 4;
3251 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3252 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3253 shaders[i]->info.gs.vertices_out;
3254 }
3255
3256 ac_setup_rings(&ctx);
3257
3258 LLVMBasicBlockRef merge_block;
3259 if (shader_count >= 2) {
3260 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3261 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3262 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3263
3264 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3265 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3266 LLVMConstInt(ctx.ac.i32, 8, false), false);
3267 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3268 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3269 thread_id, count, "");
3270 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3271
3272 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3273 }
3274
3275 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3276 handle_fs_inputs(&ctx, shaders[i]);
3277 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3278 handle_vs_inputs(&ctx, shaders[i]);
3279 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3280 prepare_gs_input_vgprs(&ctx);
3281
3282 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3283
3284 if (shader_count >= 2) {
3285 LLVMBuildBr(ctx.ac.builder, merge_block);
3286 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3287 }
3288
3289 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3290 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3291 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3292 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3293 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3294 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3295 }
3296 }
3297
3298 LLVMBuildRetVoid(ctx.ac.builder);
3299
3300 if (options->dump_preoptir)
3301 ac_dump_module(ctx.ac.module);
3302
3303 ac_llvm_finalize_module(&ctx, options);
3304
3305 if (shader_count == 1)
3306 ac_nir_eliminate_const_vs_outputs(&ctx);
3307
3308 if (options->dump_shader) {
3309 ctx.shader_info->private_mem_vgprs =
3310 ac_count_scratch_private_memory(ctx.main_function);
3311 }
3312
3313 return ctx.ac.module;
3314 }
3315
3316 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3317 {
3318 unsigned *retval = (unsigned *)context;
3319 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3320 char *description = LLVMGetDiagInfoDescription(di);
3321
3322 if (severity == LLVMDSError) {
3323 *retval = 1;
3324 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3325 description);
3326 }
3327
3328 LLVMDisposeMessage(description);
3329 }
3330
3331 static unsigned ac_llvm_compile(LLVMModuleRef M,
3332 struct ac_shader_binary *binary,
3333 LLVMTargetMachineRef tm)
3334 {
3335 unsigned retval = 0;
3336 char *err;
3337 LLVMContextRef llvm_ctx;
3338 LLVMMemoryBufferRef out_buffer;
3339 unsigned buffer_size;
3340 const char *buffer_data;
3341 LLVMBool mem_err;
3342
3343 /* Setup Diagnostic Handler*/
3344 llvm_ctx = LLVMGetModuleContext(M);
3345
3346 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3347 &retval);
3348
3349 /* Compile IR*/
3350 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
3351 &err, &out_buffer);
3352
3353 /* Process Errors/Warnings */
3354 if (mem_err) {
3355 fprintf(stderr, "%s: %s", __FUNCTION__, err);
3356 free(err);
3357 retval = 1;
3358 goto out;
3359 }
3360
3361 /* Extract Shader Code*/
3362 buffer_size = LLVMGetBufferSize(out_buffer);
3363 buffer_data = LLVMGetBufferStart(out_buffer);
3364
3365 ac_elf_read(buffer_data, buffer_size, binary);
3366
3367 /* Clean up */
3368 LLVMDisposeMemoryBuffer(out_buffer);
3369
3370 out:
3371 return retval;
3372 }
3373
3374 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
3375 LLVMModuleRef llvm_module,
3376 struct ac_shader_binary *binary,
3377 struct ac_shader_config *config,
3378 struct radv_shader_variant_info *shader_info,
3379 gl_shader_stage stage,
3380 const struct radv_nir_compiler_options *options)
3381 {
3382 if (options->dump_shader)
3383 ac_dump_module(llvm_module);
3384
3385 memset(binary, 0, sizeof(*binary));
3386
3387 if (options->record_llvm_ir) {
3388 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3389 binary->llvm_ir_string = strdup(llvm_ir);
3390 LLVMDisposeMessage(llvm_ir);
3391 }
3392
3393 int v = ac_llvm_compile(llvm_module, binary, tm);
3394 if (v) {
3395 fprintf(stderr, "compile failed\n");
3396 }
3397
3398 if (options->dump_shader)
3399 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3400
3401 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3402
3403 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3404 LLVMDisposeModule(llvm_module);
3405 LLVMContextDispose(ctx);
3406
3407 if (stage == MESA_SHADER_FRAGMENT) {
3408 shader_info->num_input_vgprs = 0;
3409 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3410 shader_info->num_input_vgprs += 2;
3411 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3412 shader_info->num_input_vgprs += 2;
3413 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3414 shader_info->num_input_vgprs += 2;
3415 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3416 shader_info->num_input_vgprs += 3;
3417 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3418 shader_info->num_input_vgprs += 2;
3419 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3420 shader_info->num_input_vgprs += 2;
3421 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3422 shader_info->num_input_vgprs += 2;
3423 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3424 shader_info->num_input_vgprs += 1;
3425 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3426 shader_info->num_input_vgprs += 1;
3427 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3428 shader_info->num_input_vgprs += 1;
3429 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3430 shader_info->num_input_vgprs += 1;
3431 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3432 shader_info->num_input_vgprs += 1;
3433 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3434 shader_info->num_input_vgprs += 1;
3435 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3436 shader_info->num_input_vgprs += 1;
3437 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3438 shader_info->num_input_vgprs += 1;
3439 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3440 shader_info->num_input_vgprs += 1;
3441 }
3442 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3443
3444 /* +3 for scratch wave offset and VCC */
3445 config->num_sgprs = MAX2(config->num_sgprs,
3446 shader_info->num_input_sgprs + 3);
3447
3448 /* Enable 64-bit and 16-bit denormals, because there is no performance
3449 * cost.
3450 *
3451 * If denormals are enabled, all floating-point output modifiers are
3452 * ignored.
3453 *
3454 * Don't enable denormals for 32-bit floats, because:
3455 * - Floating-point output modifiers would be ignored by the hw.
3456 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3457 * have to stop using those.
3458 * - SI & CI would be very slow.
3459 */
3460 config->float_mode |= V_00B028_FP_64_DENORMS;
3461 }
3462
3463 static void
3464 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3465 {
3466 switch (nir->info.stage) {
3467 case MESA_SHADER_COMPUTE:
3468 for (int i = 0; i < 3; ++i)
3469 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3470 break;
3471 case MESA_SHADER_FRAGMENT:
3472 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3473 break;
3474 case MESA_SHADER_GEOMETRY:
3475 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3476 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3477 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3478 shader_info->gs.invocations = nir->info.gs.invocations;
3479 break;
3480 case MESA_SHADER_TESS_EVAL:
3481 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3482 shader_info->tes.spacing = nir->info.tess.spacing;
3483 shader_info->tes.ccw = nir->info.tess.ccw;
3484 shader_info->tes.point_mode = nir->info.tess.point_mode;
3485 shader_info->tes.as_es = options->key.tes.as_es;
3486 break;
3487 case MESA_SHADER_TESS_CTRL:
3488 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3489 break;
3490 case MESA_SHADER_VERTEX:
3491 shader_info->vs.as_es = options->key.vs.as_es;
3492 shader_info->vs.as_ls = options->key.vs.as_ls;
3493 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3494 if (options->key.vs.as_ls)
3495 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3496 break;
3497 default:
3498 break;
3499 }
3500 }
3501
3502 void
3503 radv_compile_nir_shader(LLVMTargetMachineRef tm,
3504 struct ac_shader_binary *binary,
3505 struct ac_shader_config *config,
3506 struct radv_shader_variant_info *shader_info,
3507 struct nir_shader *const *nir,
3508 int nir_count,
3509 const struct radv_nir_compiler_options *options)
3510 {
3511
3512 LLVMModuleRef llvm_module;
3513
3514 llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
3515 options);
3516
3517 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
3518 nir[0]->info.stage, options);
3519
3520 for (int i = 0; i < nir_count; ++i)
3521 ac_fill_shader_info(shader_info, nir[i], options);
3522
3523 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3524 if (options->chip_class == GFX9) {
3525 if (nir_count == 2 &&
3526 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3527 shader_info->gs.es_type = nir[0]->info.stage;
3528 }
3529 }
3530 }
3531
3532 static void
3533 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3534 {
3535 LLVMValueRef vtx_offset =
3536 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3537 LLVMConstInt(ctx->ac.i32, 4, false), "");
3538 int idx = 0;
3539
3540 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3541 int length = 4;
3542 int slot = idx;
3543 int slot_inc = 1;
3544 if (!(ctx->output_mask & (1ull << i)))
3545 continue;
3546
3547 if (i == VARYING_SLOT_CLIP_DIST0) {
3548 /* unpack clip and cull from a single set of slots */
3549 length = ctx->num_output_clips + ctx->num_output_culls;
3550 if (length > 4)
3551 slot_inc = 2;
3552 }
3553
3554 for (unsigned j = 0; j < length; j++) {
3555 LLVMValueRef value, soffset;
3556
3557 soffset = LLVMConstInt(ctx->ac.i32,
3558 (slot * 4 + j) *
3559 ctx->gs_max_out_vertices * 16 * 4, false);
3560
3561 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3562 1, ctx->ac.i32_0,
3563 vtx_offset, soffset,
3564 0, 1, 1, true, false);
3565
3566 LLVMBuildStore(ctx->ac.builder,
3567 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3568 }
3569 idx += slot_inc;
3570 }
3571 handle_vs_outputs_post(ctx, false, false, &ctx->shader_info->vs.outinfo);
3572 }
3573
3574 void
3575 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
3576 struct nir_shader *geom_shader,
3577 struct ac_shader_binary *binary,
3578 struct ac_shader_config *config,
3579 struct radv_shader_variant_info *shader_info,
3580 const struct radv_nir_compiler_options *options)
3581 {
3582 struct radv_shader_context ctx = {0};
3583 ctx.context = LLVMContextCreate();
3584 ctx.options = options;
3585 ctx.shader_info = shader_info;
3586
3587 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3588 options->family);
3589 ctx.ac.module = ac_create_module(tm, ctx.context);
3590
3591 ctx.is_gs_copy_shader = true;
3592
3593 enum ac_float_mode float_mode =
3594 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3595 AC_FLOAT_MODE_DEFAULT;
3596
3597 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3598 ctx.stage = MESA_SHADER_VERTEX;
3599
3600 radv_nir_shader_info_pass(geom_shader, options, &shader_info->info);
3601
3602 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3603
3604 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3605 ac_setup_rings(&ctx);
3606
3607 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3608 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3609
3610 nir_foreach_variable(variable, &geom_shader->outputs) {
3611 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3612 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3613 variable, MESA_SHADER_VERTEX);
3614 }
3615
3616 ac_gs_copy_shader_emit(&ctx);
3617
3618 LLVMBuildRetVoid(ctx.ac.builder);
3619
3620 ac_llvm_finalize_module(&ctx, options);
3621
3622 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
3623 MESA_SHADER_VERTEX, options);
3624 }