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radv: drop geometry stride user sgpr.
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "nir/nir.h"
31
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35
36 #include "sid.h"
37 #include "gfx9d.h"
38 #include "ac_binary.h"
39 #include "ac_llvm_util.h"
40 #include "ac_llvm_build.h"
41 #include "ac_shader_abi.h"
42 #include "ac_shader_util.h"
43 #include "ac_exp_param.h"
44
45 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
46
47 struct radv_shader_context {
48 struct ac_llvm_context ac;
49 const struct radv_nir_compiler_options *options;
50 struct radv_shader_variant_info *shader_info;
51 struct ac_shader_abi abi;
52
53 unsigned max_workgroup_size;
54 LLVMContextRef context;
55 LLVMValueRef main_function;
56
57 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
58 LLVMValueRef ring_offsets;
59
60 LLVMValueRef vertex_buffers;
61 LLVMValueRef rel_auto_id;
62 LLVMValueRef vs_prim_id;
63 LLVMValueRef es2gs_offset;
64
65 LLVMValueRef oc_lds;
66 LLVMValueRef merged_wave_info;
67 LLVMValueRef tess_factor_offset;
68 LLVMValueRef tes_rel_patch_id;
69 LLVMValueRef tes_u;
70 LLVMValueRef tes_v;
71
72 LLVMValueRef gs2vs_offset;
73 LLVMValueRef gs_wave_id;
74 LLVMValueRef gs_vtx_offset[6];
75
76 LLVMValueRef esgs_ring;
77 LLVMValueRef gsvs_ring;
78 LLVMValueRef hs_ring_tess_offchip;
79 LLVMValueRef hs_ring_tess_factor;
80
81 LLVMValueRef sample_pos_offset;
82 LLVMValueRef persp_sample, persp_center, persp_centroid;
83 LLVMValueRef linear_sample, linear_center, linear_centroid;
84
85 gl_shader_stage stage;
86
87 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
88
89 uint64_t input_mask;
90 uint64_t output_mask;
91 uint8_t num_output_clips;
92 uint8_t num_output_culls;
93
94 bool is_gs_copy_shader;
95 LLVMValueRef gs_next_vertex;
96 unsigned gs_max_out_vertices;
97
98 unsigned tes_primitive_mode;
99
100 uint32_t tcs_patch_outputs_read;
101 uint64_t tcs_outputs_read;
102 uint32_t tcs_vertices_per_patch;
103 uint32_t tcs_num_inputs;
104 uint32_t tcs_num_patches;
105 uint32_t max_gsvs_emit_size;
106 uint32_t gsvs_vertex_size;
107 };
108
109 enum radeon_llvm_calling_convention {
110 RADEON_LLVM_AMDGPU_VS = 87,
111 RADEON_LLVM_AMDGPU_GS = 88,
112 RADEON_LLVM_AMDGPU_PS = 89,
113 RADEON_LLVM_AMDGPU_CS = 90,
114 RADEON_LLVM_AMDGPU_HS = 93,
115 };
116
117 static inline struct radv_shader_context *
118 radv_shader_context_from_abi(struct ac_shader_abi *abi)
119 {
120 struct radv_shader_context *ctx = NULL;
121 return container_of(abi, ctx, abi);
122 }
123
124 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
125 {
126 switch (ctx->stage) {
127 case MESA_SHADER_TESS_CTRL:
128 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
129 case MESA_SHADER_TESS_EVAL:
130 return ctx->tes_rel_patch_id;
131 break;
132 default:
133 unreachable("Illegal stage");
134 }
135 }
136
137 static unsigned
138 get_tcs_num_patches(struct radv_shader_context *ctx)
139 {
140 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
141 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
142 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
143 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
144 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
145 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
146 uint32_t output_vertex_size = num_tcs_outputs * 16;
147 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
148 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
149 unsigned num_patches;
150 unsigned hardware_lds_size;
151
152 /* Ensure that we only need one wave per SIMD so we don't need to check
153 * resource usage. Also ensures that the number of tcs in and out
154 * vertices per threadgroup are at most 256.
155 */
156 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
157 /* Make sure that the data fits in LDS. This assumes the shaders only
158 * use LDS for the inputs and outputs.
159 */
160 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
161 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
162 /* Make sure the output data fits in the offchip buffer */
163 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
164 /* Not necessary for correctness, but improves performance. The
165 * specific value is taken from the proprietary driver.
166 */
167 num_patches = MIN2(num_patches, 40);
168
169 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
170 if (ctx->options->chip_class == SI) {
171 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
172 num_patches = MIN2(num_patches, one_wave);
173 }
174 return num_patches;
175 }
176
177 static unsigned
178 calculate_tess_lds_size(struct radv_shader_context *ctx)
179 {
180 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
181 unsigned num_tcs_output_cp;
182 unsigned num_tcs_outputs, num_tcs_patch_outputs;
183 unsigned input_vertex_size, output_vertex_size;
184 unsigned input_patch_size, output_patch_size;
185 unsigned pervertex_output_patch_size;
186 unsigned output_patch0_offset;
187 unsigned num_patches;
188 unsigned lds_size;
189
190 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
191 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
192 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
193
194 input_vertex_size = ctx->tcs_num_inputs * 16;
195 output_vertex_size = num_tcs_outputs * 16;
196
197 input_patch_size = num_tcs_input_cp * input_vertex_size;
198
199 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
200 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
201
202 num_patches = ctx->tcs_num_patches;
203 output_patch0_offset = input_patch_size * num_patches;
204
205 lds_size = output_patch0_offset + output_patch_size * num_patches;
206 return lds_size;
207 }
208
209 /* Tessellation shaders pass outputs to the next shader using LDS.
210 *
211 * LS outputs = TCS inputs
212 * TCS outputs = TES inputs
213 *
214 * The LDS layout is:
215 * - TCS inputs for patch 0
216 * - TCS inputs for patch 1
217 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
218 * - ...
219 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
220 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
221 * - TCS outputs for patch 1
222 * - Per-patch TCS outputs for patch 1
223 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
224 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
225 * - ...
226 *
227 * All three shaders VS(LS), TCS, TES share the same LDS space.
228 */
229 static LLVMValueRef
230 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
231 {
232 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
233 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
234 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
235
236 input_patch_size /= 4;
237 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
238 }
239
240 static LLVMValueRef
241 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
242 {
243 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
244 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
245 uint32_t output_vertex_size = num_tcs_outputs * 16;
246 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
247 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
248 output_patch_size /= 4;
249 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
250 }
251
252 static LLVMValueRef
253 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
254 {
255 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
256 uint32_t output_vertex_size = num_tcs_outputs * 16;
257 output_vertex_size /= 4;
258 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
259 }
260
261 static LLVMValueRef
262 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
263 {
264 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
265 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
266 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
267 uint32_t output_patch0_offset = input_patch_size;
268 unsigned num_patches = ctx->tcs_num_patches;
269
270 output_patch0_offset *= num_patches;
271 output_patch0_offset /= 4;
272 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
273 }
274
275 static LLVMValueRef
276 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
277 {
278 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
279 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
280 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
281 uint32_t output_patch0_offset = input_patch_size;
282
283 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
284 uint32_t output_vertex_size = num_tcs_outputs * 16;
285 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
286 unsigned num_patches = ctx->tcs_num_patches;
287
288 output_patch0_offset *= num_patches;
289 output_patch0_offset += pervertex_output_patch_size;
290 output_patch0_offset /= 4;
291 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
292 }
293
294 static LLVMValueRef
295 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
296 {
297 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
298 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
299
300 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
301 }
302
303 static LLVMValueRef
304 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
305 {
306 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
307 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
308 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
309
310 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
311 LLVMBuildMul(ctx->ac.builder, patch_stride,
312 rel_patch_id, ""),
313 "");
314 }
315
316 static LLVMValueRef
317 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
318 {
319 LLVMValueRef patch0_patch_data_offset =
320 get_tcs_out_patch0_patch_data_offset(ctx);
321 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
322 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
323
324 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
325 LLVMBuildMul(ctx->ac.builder, patch_stride,
326 rel_patch_id, ""),
327 "");
328 }
329
330 #define MAX_ARGS 23
331 struct arg_info {
332 LLVMTypeRef types[MAX_ARGS];
333 LLVMValueRef *assign[MAX_ARGS];
334 unsigned array_params_mask;
335 uint8_t count;
336 uint8_t sgpr_count;
337 uint8_t num_sgprs_used;
338 uint8_t num_vgprs_used;
339 };
340
341 enum ac_arg_regfile {
342 ARG_SGPR,
343 ARG_VGPR,
344 };
345
346 static void
347 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
348 LLVMValueRef *param_ptr)
349 {
350 assert(info->count < MAX_ARGS);
351
352 info->assign[info->count] = param_ptr;
353 info->types[info->count] = type;
354 info->count++;
355
356 if (regfile == ARG_SGPR) {
357 info->num_sgprs_used += ac_get_type_size(type) / 4;
358 info->sgpr_count++;
359 } else {
360 assert(regfile == ARG_VGPR);
361 info->num_vgprs_used += ac_get_type_size(type) / 4;
362 }
363 }
364
365 static inline void
366 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
367 {
368 info->array_params_mask |= (1 << info->count);
369 add_arg(info, ARG_SGPR, type, param_ptr);
370 }
371
372 static void assign_arguments(LLVMValueRef main_function,
373 struct arg_info *info)
374 {
375 unsigned i;
376 for (i = 0; i < info->count; i++) {
377 if (info->assign[i])
378 *info->assign[i] = LLVMGetParam(main_function, i);
379 }
380 }
381
382 static LLVMValueRef
383 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
384 LLVMBuilderRef builder, LLVMTypeRef *return_types,
385 unsigned num_return_elems,
386 struct arg_info *args,
387 unsigned max_workgroup_size,
388 bool unsafe_math)
389 {
390 LLVMTypeRef main_function_type, ret_type;
391 LLVMBasicBlockRef main_function_body;
392
393 if (num_return_elems)
394 ret_type = LLVMStructTypeInContext(ctx, return_types,
395 num_return_elems, true);
396 else
397 ret_type = LLVMVoidTypeInContext(ctx);
398
399 /* Setup the function */
400 main_function_type =
401 LLVMFunctionType(ret_type, args->types, args->count, 0);
402 LLVMValueRef main_function =
403 LLVMAddFunction(module, "main", main_function_type);
404 main_function_body =
405 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
406 LLVMPositionBuilderAtEnd(builder, main_function_body);
407
408 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
409 for (unsigned i = 0; i < args->sgpr_count; ++i) {
410 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
411
412 if (args->array_params_mask & (1 << i)) {
413 LLVMValueRef P = LLVMGetParam(main_function, i);
414 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
415 ac_add_attr_dereferenceable(P, UINT64_MAX);
416 }
417 }
418
419 if (max_workgroup_size) {
420 ac_llvm_add_target_dep_function_attr(main_function,
421 "amdgpu-max-work-group-size",
422 max_workgroup_size);
423 }
424 if (unsafe_math) {
425 /* These were copied from some LLVM test. */
426 LLVMAddTargetDependentFunctionAttr(main_function,
427 "less-precise-fpmad",
428 "true");
429 LLVMAddTargetDependentFunctionAttr(main_function,
430 "no-infs-fp-math",
431 "true");
432 LLVMAddTargetDependentFunctionAttr(main_function,
433 "no-nans-fp-math",
434 "true");
435 LLVMAddTargetDependentFunctionAttr(main_function,
436 "unsafe-fp-math",
437 "true");
438 LLVMAddTargetDependentFunctionAttr(main_function,
439 "no-signed-zeros-fp-math",
440 "true");
441 }
442 return main_function;
443 }
444
445
446 static void
447 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
448 uint32_t indirect_offset)
449 {
450 ud_info->sgpr_idx = *sgpr_idx;
451 ud_info->num_sgprs = num_sgprs;
452 ud_info->indirect = indirect_offset > 0;
453 ud_info->indirect_offset = indirect_offset;
454 *sgpr_idx += num_sgprs;
455 }
456
457 static void
458 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
459 uint8_t num_sgprs)
460 {
461 struct radv_userdata_info *ud_info =
462 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
463 assert(ud_info);
464
465 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
466 }
467
468 static void
469 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
470 uint32_t indirect_offset)
471 {
472 struct radv_userdata_info *ud_info =
473 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
474 assert(ud_info);
475
476 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
477 }
478
479 struct user_sgpr_info {
480 bool need_ring_offsets;
481 uint8_t sgpr_count;
482 bool indirect_all_descriptor_sets;
483 };
484
485 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
486 gl_shader_stage stage)
487 {
488 switch (stage) {
489 case MESA_SHADER_VERTEX:
490 if (ctx->shader_info->info.needs_multiview_view_index ||
491 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
492 return true;
493 break;
494 case MESA_SHADER_TESS_EVAL:
495 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
496 return true;
497 break;
498 case MESA_SHADER_GEOMETRY:
499 case MESA_SHADER_TESS_CTRL:
500 if (ctx->shader_info->info.needs_multiview_view_index)
501 return true;
502 break;
503 default:
504 break;
505 }
506 return false;
507 }
508
509 static uint8_t
510 count_vs_user_sgprs(struct radv_shader_context *ctx)
511 {
512 uint8_t count = 0;
513
514 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
515 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
516
517 return count;
518 }
519
520 static void allocate_user_sgprs(struct radv_shader_context *ctx,
521 gl_shader_stage stage,
522 bool has_previous_stage,
523 gl_shader_stage previous_stage,
524 bool needs_view_index,
525 struct user_sgpr_info *user_sgpr_info)
526 {
527 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
528
529 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
530 if (stage == MESA_SHADER_GEOMETRY ||
531 stage == MESA_SHADER_VERTEX ||
532 stage == MESA_SHADER_TESS_CTRL ||
533 stage == MESA_SHADER_TESS_EVAL ||
534 ctx->is_gs_copy_shader)
535 user_sgpr_info->need_ring_offsets = true;
536
537 if (stage == MESA_SHADER_FRAGMENT &&
538 ctx->shader_info->info.ps.needs_sample_positions)
539 user_sgpr_info->need_ring_offsets = true;
540
541 /* 2 user sgprs will nearly always be allocated for scratch/rings */
542 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
543 user_sgpr_info->sgpr_count += 2;
544 }
545
546 switch (stage) {
547 case MESA_SHADER_COMPUTE:
548 if (ctx->shader_info->info.cs.uses_grid_size)
549 user_sgpr_info->sgpr_count += 3;
550 break;
551 case MESA_SHADER_FRAGMENT:
552 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
553 break;
554 case MESA_SHADER_VERTEX:
555 if (!ctx->is_gs_copy_shader)
556 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
557 break;
558 case MESA_SHADER_TESS_CTRL:
559 if (has_previous_stage) {
560 if (previous_stage == MESA_SHADER_VERTEX)
561 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
562 }
563 break;
564 case MESA_SHADER_TESS_EVAL:
565 break;
566 case MESA_SHADER_GEOMETRY:
567 if (has_previous_stage) {
568 if (previous_stage == MESA_SHADER_VERTEX) {
569 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
570 }
571 }
572 break;
573 default:
574 break;
575 }
576
577 if (needs_view_index)
578 user_sgpr_info->sgpr_count++;
579
580 if (ctx->shader_info->info.loads_push_constants)
581 user_sgpr_info->sgpr_count += 2;
582
583 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
584 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
585
586 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
587 user_sgpr_info->sgpr_count += 2;
588 user_sgpr_info->indirect_all_descriptor_sets = true;
589 } else {
590 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
591 }
592 }
593
594 static void
595 declare_global_input_sgprs(struct radv_shader_context *ctx,
596 gl_shader_stage stage,
597 bool has_previous_stage,
598 gl_shader_stage previous_stage,
599 const struct user_sgpr_info *user_sgpr_info,
600 struct arg_info *args,
601 LLVMValueRef *desc_sets)
602 {
603 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
604 unsigned num_sets = ctx->options->layout ?
605 ctx->options->layout->num_sets : 0;
606 unsigned stage_mask = 1 << stage;
607
608 if (has_previous_stage)
609 stage_mask |= 1 << previous_stage;
610
611 /* 1 for each descriptor set */
612 if (!user_sgpr_info->indirect_all_descriptor_sets) {
613 for (unsigned i = 0; i < num_sets; ++i) {
614 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
615 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
616 add_array_arg(args, type,
617 &ctx->descriptor_sets[i]);
618 }
619 }
620 } else {
621 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
622 }
623
624 if (ctx->shader_info->info.loads_push_constants) {
625 /* 1 for push constants and dynamic descriptors */
626 add_array_arg(args, type, &ctx->abi.push_constants);
627 }
628 }
629
630 static void
631 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
632 gl_shader_stage stage,
633 bool has_previous_stage,
634 gl_shader_stage previous_stage,
635 struct arg_info *args)
636 {
637 if (!ctx->is_gs_copy_shader &&
638 (stage == MESA_SHADER_VERTEX ||
639 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
640 if (ctx->shader_info->info.vs.has_vertex_buffers) {
641 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
642 &ctx->vertex_buffers);
643 }
644 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
645 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
646 if (ctx->shader_info->info.vs.needs_draw_id) {
647 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
648 }
649 }
650 }
651
652 static void
653 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
654 {
655 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
656 if (!ctx->is_gs_copy_shader) {
657 if (ctx->options->key.vs.as_ls) {
658 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
659 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
660 } else {
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
662 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
663 }
664 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
665 }
666 }
667
668 static void
669 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
670 {
671 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
672 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
673 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
674 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
675 }
676
677 static void
678 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
679 bool has_previous_stage, gl_shader_stage previous_stage,
680 const struct user_sgpr_info *user_sgpr_info,
681 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
682 {
683 unsigned num_sets = ctx->options->layout ?
684 ctx->options->layout->num_sets : 0;
685 unsigned stage_mask = 1 << stage;
686
687 if (has_previous_stage)
688 stage_mask |= 1 << previous_stage;
689
690 if (!user_sgpr_info->indirect_all_descriptor_sets) {
691 for (unsigned i = 0; i < num_sets; ++i) {
692 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
693 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
694 set_loc_desc(ctx, i, user_sgpr_idx, 0);
695 } else
696 ctx->descriptor_sets[i] = NULL;
697 }
698 } else {
699 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
700 user_sgpr_idx, 2);
701
702 for (unsigned i = 0; i < num_sets; ++i) {
703 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
704 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
705 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
706 ctx->descriptor_sets[i] =
707 ac_build_load_to_sgpr(&ctx->ac,
708 desc_sets,
709 LLVMConstInt(ctx->ac.i32, i, false));
710
711 } else
712 ctx->descriptor_sets[i] = NULL;
713 }
714 ctx->shader_info->need_indirect_descriptor_sets = true;
715 }
716
717 if (ctx->shader_info->info.loads_push_constants) {
718 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
719 }
720 }
721
722 static void
723 set_vs_specific_input_locs(struct radv_shader_context *ctx,
724 gl_shader_stage stage, bool has_previous_stage,
725 gl_shader_stage previous_stage,
726 uint8_t *user_sgpr_idx)
727 {
728 if (!ctx->is_gs_copy_shader &&
729 (stage == MESA_SHADER_VERTEX ||
730 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
731 if (ctx->shader_info->info.vs.has_vertex_buffers) {
732 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
733 user_sgpr_idx, 2);
734 }
735
736 unsigned vs_num = 2;
737 if (ctx->shader_info->info.vs.needs_draw_id)
738 vs_num++;
739
740 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
741 user_sgpr_idx, vs_num);
742 }
743 }
744
745 static void set_llvm_calling_convention(LLVMValueRef func,
746 gl_shader_stage stage)
747 {
748 enum radeon_llvm_calling_convention calling_conv;
749
750 switch (stage) {
751 case MESA_SHADER_VERTEX:
752 case MESA_SHADER_TESS_EVAL:
753 calling_conv = RADEON_LLVM_AMDGPU_VS;
754 break;
755 case MESA_SHADER_GEOMETRY:
756 calling_conv = RADEON_LLVM_AMDGPU_GS;
757 break;
758 case MESA_SHADER_TESS_CTRL:
759 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
760 break;
761 case MESA_SHADER_FRAGMENT:
762 calling_conv = RADEON_LLVM_AMDGPU_PS;
763 break;
764 case MESA_SHADER_COMPUTE:
765 calling_conv = RADEON_LLVM_AMDGPU_CS;
766 break;
767 default:
768 unreachable("Unhandle shader type");
769 }
770
771 LLVMSetFunctionCallConv(func, calling_conv);
772 }
773
774 static void create_function(struct radv_shader_context *ctx,
775 gl_shader_stage stage,
776 bool has_previous_stage,
777 gl_shader_stage previous_stage)
778 {
779 uint8_t user_sgpr_idx;
780 struct user_sgpr_info user_sgpr_info;
781 struct arg_info args = {};
782 LLVMValueRef desc_sets;
783 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
784 allocate_user_sgprs(ctx, stage, has_previous_stage,
785 previous_stage, needs_view_index, &user_sgpr_info);
786
787 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
788 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
789 &ctx->ring_offsets);
790 }
791
792 switch (stage) {
793 case MESA_SHADER_COMPUTE:
794 declare_global_input_sgprs(ctx, stage, has_previous_stage,
795 previous_stage, &user_sgpr_info,
796 &args, &desc_sets);
797
798 if (ctx->shader_info->info.cs.uses_grid_size) {
799 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
800 &ctx->abi.num_work_groups);
801 }
802
803 for (int i = 0; i < 3; i++) {
804 ctx->abi.workgroup_ids[i] = NULL;
805 if (ctx->shader_info->info.cs.uses_block_id[i]) {
806 add_arg(&args, ARG_SGPR, ctx->ac.i32,
807 &ctx->abi.workgroup_ids[i]);
808 }
809 }
810
811 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
812 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
813 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
814 &ctx->abi.local_invocation_ids);
815 break;
816 case MESA_SHADER_VERTEX:
817 declare_global_input_sgprs(ctx, stage, has_previous_stage,
818 previous_stage, &user_sgpr_info,
819 &args, &desc_sets);
820 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
821 previous_stage, &args);
822
823 if (needs_view_index)
824 add_arg(&args, ARG_SGPR, ctx->ac.i32,
825 &ctx->abi.view_index);
826 if (ctx->options->key.vs.as_es)
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->es2gs_offset);
829
830 declare_vs_input_vgprs(ctx, &args);
831 break;
832 case MESA_SHADER_TESS_CTRL:
833 if (has_previous_stage) {
834 // First 6 system regs
835 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
836 add_arg(&args, ARG_SGPR, ctx->ac.i32,
837 &ctx->merged_wave_info);
838 add_arg(&args, ARG_SGPR, ctx->ac.i32,
839 &ctx->tess_factor_offset);
840
841 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
842 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
843 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
844
845 declare_global_input_sgprs(ctx, stage,
846 has_previous_stage,
847 previous_stage,
848 &user_sgpr_info, &args,
849 &desc_sets);
850 declare_vs_specific_input_sgprs(ctx, stage,
851 has_previous_stage,
852 previous_stage, &args);
853
854 if (needs_view_index)
855 add_arg(&args, ARG_SGPR, ctx->ac.i32,
856 &ctx->abi.view_index);
857
858 add_arg(&args, ARG_VGPR, ctx->ac.i32,
859 &ctx->abi.tcs_patch_id);
860 add_arg(&args, ARG_VGPR, ctx->ac.i32,
861 &ctx->abi.tcs_rel_ids);
862
863 declare_vs_input_vgprs(ctx, &args);
864 } else {
865 declare_global_input_sgprs(ctx, stage,
866 has_previous_stage,
867 previous_stage,
868 &user_sgpr_info, &args,
869 &desc_sets);
870
871 if (needs_view_index)
872 add_arg(&args, ARG_SGPR, ctx->ac.i32,
873 &ctx->abi.view_index);
874
875 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
876 add_arg(&args, ARG_SGPR, ctx->ac.i32,
877 &ctx->tess_factor_offset);
878 add_arg(&args, ARG_VGPR, ctx->ac.i32,
879 &ctx->abi.tcs_patch_id);
880 add_arg(&args, ARG_VGPR, ctx->ac.i32,
881 &ctx->abi.tcs_rel_ids);
882 }
883 break;
884 case MESA_SHADER_TESS_EVAL:
885 declare_global_input_sgprs(ctx, stage, has_previous_stage,
886 previous_stage, &user_sgpr_info,
887 &args, &desc_sets);
888
889 if (needs_view_index)
890 add_arg(&args, ARG_SGPR, ctx->ac.i32,
891 &ctx->abi.view_index);
892
893 if (ctx->options->key.tes.as_es) {
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32,
897 &ctx->es2gs_offset);
898 } else {
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901 }
902 declare_tes_input_vgprs(ctx, &args);
903 break;
904 case MESA_SHADER_GEOMETRY:
905 if (has_previous_stage) {
906 // First 6 system regs
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->gs2vs_offset);
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->merged_wave_info);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
912
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
916
917 declare_global_input_sgprs(ctx, stage,
918 has_previous_stage,
919 previous_stage,
920 &user_sgpr_info, &args,
921 &desc_sets);
922
923 if (previous_stage != MESA_SHADER_TESS_EVAL) {
924 declare_vs_specific_input_sgprs(ctx, stage,
925 has_previous_stage,
926 previous_stage,
927 &args);
928 }
929
930 if (needs_view_index)
931 add_arg(&args, ARG_SGPR, ctx->ac.i32,
932 &ctx->abi.view_index);
933
934 add_arg(&args, ARG_VGPR, ctx->ac.i32,
935 &ctx->gs_vtx_offset[0]);
936 add_arg(&args, ARG_VGPR, ctx->ac.i32,
937 &ctx->gs_vtx_offset[2]);
938 add_arg(&args, ARG_VGPR, ctx->ac.i32,
939 &ctx->abi.gs_prim_id);
940 add_arg(&args, ARG_VGPR, ctx->ac.i32,
941 &ctx->abi.gs_invocation_id);
942 add_arg(&args, ARG_VGPR, ctx->ac.i32,
943 &ctx->gs_vtx_offset[4]);
944
945 if (previous_stage == MESA_SHADER_VERTEX) {
946 declare_vs_input_vgprs(ctx, &args);
947 } else {
948 declare_tes_input_vgprs(ctx, &args);
949 }
950 } else {
951 declare_global_input_sgprs(ctx, stage,
952 has_previous_stage,
953 previous_stage,
954 &user_sgpr_info, &args,
955 &desc_sets);
956
957 if (needs_view_index)
958 add_arg(&args, ARG_SGPR, ctx->ac.i32,
959 &ctx->abi.view_index);
960
961 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
962 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
963 add_arg(&args, ARG_VGPR, ctx->ac.i32,
964 &ctx->gs_vtx_offset[0]);
965 add_arg(&args, ARG_VGPR, ctx->ac.i32,
966 &ctx->gs_vtx_offset[1]);
967 add_arg(&args, ARG_VGPR, ctx->ac.i32,
968 &ctx->abi.gs_prim_id);
969 add_arg(&args, ARG_VGPR, ctx->ac.i32,
970 &ctx->gs_vtx_offset[2]);
971 add_arg(&args, ARG_VGPR, ctx->ac.i32,
972 &ctx->gs_vtx_offset[3]);
973 add_arg(&args, ARG_VGPR, ctx->ac.i32,
974 &ctx->gs_vtx_offset[4]);
975 add_arg(&args, ARG_VGPR, ctx->ac.i32,
976 &ctx->gs_vtx_offset[5]);
977 add_arg(&args, ARG_VGPR, ctx->ac.i32,
978 &ctx->abi.gs_invocation_id);
979 }
980 break;
981 case MESA_SHADER_FRAGMENT:
982 declare_global_input_sgprs(ctx, stage, has_previous_stage,
983 previous_stage, &user_sgpr_info,
984 &args, &desc_sets);
985
986 if (ctx->shader_info->info.ps.needs_sample_positions)
987 add_arg(&args, ARG_SGPR, ctx->ac.i32,
988 &ctx->sample_pos_offset);
989
990 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
991 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
992 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
993 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
994 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
995 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
996 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
997 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
998 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
999 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1000 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1001 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1002 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1003 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1004 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1005 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1006 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1007 break;
1008 default:
1009 unreachable("Shader stage not implemented");
1010 }
1011
1012 ctx->main_function = create_llvm_function(
1013 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1014 ctx->max_workgroup_size,
1015 ctx->options->unsafe_math);
1016 set_llvm_calling_convention(ctx->main_function, stage);
1017
1018
1019 ctx->shader_info->num_input_vgprs = 0;
1020 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1021
1022 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1023
1024 if (ctx->stage != MESA_SHADER_FRAGMENT)
1025 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1026
1027 assign_arguments(ctx->main_function, &args);
1028
1029 user_sgpr_idx = 0;
1030
1031 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1032 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1033 &user_sgpr_idx, 2);
1034 if (ctx->options->supports_spill) {
1035 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1036 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1037 NULL, 0, AC_FUNC_ATTR_READNONE);
1038 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1039 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1040 }
1041 }
1042
1043 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1044 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1045 if (has_previous_stage)
1046 user_sgpr_idx = 0;
1047
1048 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1049 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1050
1051 switch (stage) {
1052 case MESA_SHADER_COMPUTE:
1053 if (ctx->shader_info->info.cs.uses_grid_size) {
1054 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1055 &user_sgpr_idx, 3);
1056 }
1057 break;
1058 case MESA_SHADER_VERTEX:
1059 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1060 previous_stage, &user_sgpr_idx);
1061 if (ctx->abi.view_index)
1062 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1063 break;
1064 case MESA_SHADER_TESS_CTRL:
1065 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1066 previous_stage, &user_sgpr_idx);
1067 if (ctx->abi.view_index)
1068 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1069 break;
1070 case MESA_SHADER_TESS_EVAL:
1071 if (ctx->abi.view_index)
1072 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1073 break;
1074 case MESA_SHADER_GEOMETRY:
1075 if (has_previous_stage) {
1076 if (previous_stage == MESA_SHADER_VERTEX)
1077 set_vs_specific_input_locs(ctx, stage,
1078 has_previous_stage,
1079 previous_stage,
1080 &user_sgpr_idx);
1081 }
1082 if (ctx->abi.view_index)
1083 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1084 break;
1085 case MESA_SHADER_FRAGMENT:
1086 if (ctx->shader_info->info.ps.needs_sample_positions) {
1087 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1088 &user_sgpr_idx, 1);
1089 }
1090 break;
1091 default:
1092 unreachable("Shader stage not implemented");
1093 }
1094
1095 if (stage == MESA_SHADER_TESS_CTRL ||
1096 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1097 /* GFX9 has the ESGS ring buffer in LDS. */
1098 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1099 ac_declare_lds_as_pointer(&ctx->ac);
1100 }
1101
1102 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1103 }
1104
1105
1106 static LLVMValueRef
1107 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1108 unsigned desc_set, unsigned binding)
1109 {
1110 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1111 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1112 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1113 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1114 unsigned base_offset = layout->binding[binding].offset;
1115 LLVMValueRef offset, stride;
1116
1117 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1118 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1119 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1120 layout->binding[binding].dynamic_offset_offset;
1121 desc_ptr = ctx->abi.push_constants;
1122 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1123 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1124 } else
1125 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1126
1127 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1128 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
1129 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
1130
1131 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1132 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1133 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1134
1135 return desc_ptr;
1136 }
1137
1138
1139 /* The offchip buffer layout for TCS->TES is
1140 *
1141 * - attribute 0 of patch 0 vertex 0
1142 * - attribute 0 of patch 0 vertex 1
1143 * - attribute 0 of patch 0 vertex 2
1144 * ...
1145 * - attribute 0 of patch 1 vertex 0
1146 * - attribute 0 of patch 1 vertex 1
1147 * ...
1148 * - attribute 1 of patch 0 vertex 0
1149 * - attribute 1 of patch 0 vertex 1
1150 * ...
1151 * - per patch attribute 0 of patch 0
1152 * - per patch attribute 0 of patch 1
1153 * ...
1154 *
1155 * Note that every attribute has 4 components.
1156 */
1157 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1158 {
1159 uint32_t num_patches = ctx->tcs_num_patches;
1160 uint32_t num_tcs_outputs;
1161 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1162 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1163 else
1164 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1165
1166 uint32_t output_vertex_size = num_tcs_outputs * 16;
1167 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1168
1169 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1170 }
1171
1172 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1173 LLVMValueRef vertex_index)
1174 {
1175 LLVMValueRef param_stride;
1176 if (vertex_index)
1177 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1178 else
1179 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1180 return param_stride;
1181 }
1182
1183 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1184 LLVMValueRef vertex_index,
1185 LLVMValueRef param_index)
1186 {
1187 LLVMValueRef base_addr;
1188 LLVMValueRef param_stride, constant16;
1189 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1190 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1191 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1192 param_stride = calc_param_stride(ctx, vertex_index);
1193 if (vertex_index) {
1194 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
1195 vertices_per_patch, "");
1196
1197 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1198 vertex_index, "");
1199 } else {
1200 base_addr = rel_patch_id;
1201 }
1202
1203 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1204 LLVMBuildMul(ctx->ac.builder, param_index,
1205 param_stride, ""), "");
1206
1207 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1208
1209 if (!vertex_index) {
1210 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1211
1212 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1213 patch_data_offset, "");
1214 }
1215 return base_addr;
1216 }
1217
1218 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1219 unsigned param,
1220 unsigned const_index,
1221 bool is_compact,
1222 LLVMValueRef vertex_index,
1223 LLVMValueRef indir_index)
1224 {
1225 LLVMValueRef param_index;
1226
1227 if (indir_index)
1228 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1229 indir_index, "");
1230 else {
1231 if (const_index && !is_compact)
1232 param += const_index;
1233 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1234 }
1235 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1236 }
1237
1238 static LLVMValueRef
1239 get_dw_address(struct radv_shader_context *ctx,
1240 LLVMValueRef dw_addr,
1241 unsigned param,
1242 unsigned const_index,
1243 bool compact_const_index,
1244 LLVMValueRef vertex_index,
1245 LLVMValueRef stride,
1246 LLVMValueRef indir_index)
1247
1248 {
1249
1250 if (vertex_index) {
1251 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1252 LLVMBuildMul(ctx->ac.builder,
1253 vertex_index,
1254 stride, ""), "");
1255 }
1256
1257 if (indir_index)
1258 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1259 LLVMBuildMul(ctx->ac.builder, indir_index,
1260 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1261 else if (const_index && !compact_const_index)
1262 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1263 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1264
1265 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1266 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1267
1268 if (const_index && compact_const_index)
1269 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1270 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1271 return dw_addr;
1272 }
1273
1274 static LLVMValueRef
1275 load_tcs_varyings(struct ac_shader_abi *abi,
1276 LLVMTypeRef type,
1277 LLVMValueRef vertex_index,
1278 LLVMValueRef indir_index,
1279 unsigned const_index,
1280 unsigned location,
1281 unsigned driver_location,
1282 unsigned component,
1283 unsigned num_components,
1284 bool is_patch,
1285 bool is_compact,
1286 bool load_input)
1287 {
1288 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1289 LLVMValueRef dw_addr, stride;
1290 LLVMValueRef value[4], result;
1291 unsigned param = shader_io_get_unique_index(location);
1292
1293 if (load_input) {
1294 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1295 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1296 dw_addr = get_tcs_in_current_patch_offset(ctx);
1297 } else {
1298 if (!is_patch) {
1299 stride = get_tcs_out_vertex_stride(ctx);
1300 dw_addr = get_tcs_out_current_patch_offset(ctx);
1301 } else {
1302 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1303 stride = NULL;
1304 }
1305 }
1306
1307 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1308 indir_index);
1309
1310 for (unsigned i = 0; i < num_components + component; i++) {
1311 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1312 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1313 ctx->ac.i32_1, "");
1314 }
1315 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1316 return result;
1317 }
1318
1319 static void
1320 store_tcs_output(struct ac_shader_abi *abi,
1321 const nir_variable *var,
1322 LLVMValueRef vertex_index,
1323 LLVMValueRef param_index,
1324 unsigned const_index,
1325 LLVMValueRef src,
1326 unsigned writemask)
1327 {
1328 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1329 const unsigned location = var->data.location;
1330 const unsigned component = var->data.location_frac;
1331 const bool is_patch = var->data.patch;
1332 const bool is_compact = var->data.compact;
1333 LLVMValueRef dw_addr;
1334 LLVMValueRef stride = NULL;
1335 LLVMValueRef buf_addr = NULL;
1336 unsigned param;
1337 bool store_lds = true;
1338
1339 if (is_patch) {
1340 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1341 store_lds = false;
1342 } else {
1343 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1344 store_lds = false;
1345 }
1346
1347 param = shader_io_get_unique_index(location);
1348 if (location == VARYING_SLOT_CLIP_DIST0 &&
1349 is_compact && const_index > 3) {
1350 const_index -= 3;
1351 param++;
1352 }
1353
1354 if (!is_patch) {
1355 stride = get_tcs_out_vertex_stride(ctx);
1356 dw_addr = get_tcs_out_current_patch_offset(ctx);
1357 } else {
1358 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1359 }
1360
1361 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1362 param_index);
1363 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1364 vertex_index, param_index);
1365
1366 bool is_tess_factor = false;
1367 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1368 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1369 is_tess_factor = true;
1370
1371 unsigned base = is_compact ? const_index : 0;
1372 for (unsigned chan = 0; chan < 8; chan++) {
1373 if (!(writemask & (1 << chan)))
1374 continue;
1375 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1376
1377 if (store_lds || is_tess_factor) {
1378 LLVMValueRef dw_addr_chan =
1379 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1380 LLVMConstInt(ctx->ac.i32, chan, false), "");
1381 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1382 }
1383
1384 if (!is_tess_factor && writemask != 0xF)
1385 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1386 buf_addr, ctx->oc_lds,
1387 4 * (base + chan), 1, 0, true, false);
1388 }
1389
1390 if (writemask == 0xF) {
1391 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1392 buf_addr, ctx->oc_lds,
1393 (base * 4), 1, 0, true, false);
1394 }
1395 }
1396
1397 static LLVMValueRef
1398 load_tes_input(struct ac_shader_abi *abi,
1399 LLVMTypeRef type,
1400 LLVMValueRef vertex_index,
1401 LLVMValueRef param_index,
1402 unsigned const_index,
1403 unsigned location,
1404 unsigned driver_location,
1405 unsigned component,
1406 unsigned num_components,
1407 bool is_patch,
1408 bool is_compact,
1409 bool load_input)
1410 {
1411 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1412 LLVMValueRef buf_addr;
1413 LLVMValueRef result;
1414 unsigned param = shader_io_get_unique_index(location);
1415
1416 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1417 const_index -= 3;
1418 param++;
1419 }
1420
1421 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1422 is_compact, vertex_index, param_index);
1423
1424 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1425 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1426
1427 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1428 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1429 result = ac_trim_vector(&ctx->ac, result, num_components);
1430 return result;
1431 }
1432
1433 static LLVMValueRef
1434 load_gs_input(struct ac_shader_abi *abi,
1435 unsigned location,
1436 unsigned driver_location,
1437 unsigned component,
1438 unsigned num_components,
1439 unsigned vertex_index,
1440 unsigned const_index,
1441 LLVMTypeRef type)
1442 {
1443 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1444 LLVMValueRef vtx_offset;
1445 unsigned param, vtx_offset_param;
1446 LLVMValueRef value[4], result;
1447
1448 vtx_offset_param = vertex_index;
1449 assert(vtx_offset_param < 6);
1450 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1451 LLVMConstInt(ctx->ac.i32, 4, false), "");
1452
1453 param = shader_io_get_unique_index(location);
1454
1455 for (unsigned i = component; i < num_components + component; i++) {
1456 if (ctx->ac.chip_class >= GFX9) {
1457 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1458 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1459 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1460 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1461 } else {
1462 LLVMValueRef soffset =
1463 LLVMConstInt(ctx->ac.i32,
1464 (param * 4 + i + const_index) * 256,
1465 false);
1466
1467 value[i] = ac_build_buffer_load(&ctx->ac,
1468 ctx->esgs_ring, 1,
1469 ctx->ac.i32_0,
1470 vtx_offset, soffset,
1471 0, 1, 0, true, false);
1472
1473 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
1474 type, "");
1475 }
1476 }
1477 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1478 result = ac_to_integer(&ctx->ac, result);
1479 return result;
1480 }
1481
1482
1483 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1484 {
1485 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1486 ac_build_kill_if_false(&ctx->ac, visible);
1487 }
1488
1489 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1490 enum glsl_interp_mode interp, unsigned location)
1491 {
1492 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1493
1494 switch (interp) {
1495 case INTERP_MODE_FLAT:
1496 default:
1497 return NULL;
1498 case INTERP_MODE_SMOOTH:
1499 case INTERP_MODE_NONE:
1500 if (location == INTERP_CENTER)
1501 return ctx->persp_center;
1502 else if (location == INTERP_CENTROID)
1503 return ctx->persp_centroid;
1504 else if (location == INTERP_SAMPLE)
1505 return ctx->persp_sample;
1506 break;
1507 case INTERP_MODE_NOPERSPECTIVE:
1508 if (location == INTERP_CENTER)
1509 return ctx->linear_center;
1510 else if (location == INTERP_CENTROID)
1511 return ctx->linear_centroid;
1512 else if (location == INTERP_SAMPLE)
1513 return ctx->linear_sample;
1514 break;
1515 }
1516 return NULL;
1517 }
1518
1519 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1520 LLVMValueRef sample_id)
1521 {
1522 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1523
1524 LLVMValueRef result;
1525 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1526
1527 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1528 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1529
1530 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
1531 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1532
1533 return result;
1534 }
1535
1536
1537 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1538 {
1539 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1540 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
1541 ctx->options->key.fs.log2_num_samples :
1542 ctx->options->key.fs.log2_ps_iter_samples;
1543
1544 /* The bit pattern matches that used by fixed function fragment
1545 * processing. */
1546 static const uint16_t ps_iter_masks[] = {
1547 0xffff, /* not used */
1548 0x5555,
1549 0x1111,
1550 0x0101,
1551 0x0001,
1552 };
1553 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1554
1555 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1556
1557 LLVMValueRef result, sample_id;
1558 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1559 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1560 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1561 return result;
1562 }
1563
1564
1565 static void
1566 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1567 {
1568 LLVMValueRef gs_next_vertex;
1569 LLVMValueRef can_emit;
1570 int idx;
1571 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1572
1573 assert(stream == 0);
1574
1575 /* Write vertex attribute values to GSVS ring */
1576 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1577 ctx->gs_next_vertex,
1578 "");
1579
1580 /* If this thread has already emitted the declared maximum number of
1581 * vertices, kill it: excessive vertex emissions are not supposed to
1582 * have any effect, and GS threads have no externally observable
1583 * effects other than emitting vertices.
1584 */
1585 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1586 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1587 ac_build_kill_if_false(&ctx->ac, can_emit);
1588
1589 /* loop num outputs */
1590 idx = 0;
1591 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1592 LLVMValueRef *out_ptr = &addrs[i * 4];
1593 int length = 4;
1594 int slot = idx;
1595 int slot_inc = 1;
1596
1597 if (!(ctx->output_mask & (1ull << i)))
1598 continue;
1599
1600 if (i == VARYING_SLOT_CLIP_DIST0) {
1601 /* pack clip and cull into a single set of slots */
1602 length = ctx->num_output_clips + ctx->num_output_culls;
1603 if (length > 4)
1604 slot_inc = 2;
1605 }
1606 for (unsigned j = 0; j < length; j++) {
1607 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1608 out_ptr[j], "");
1609 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1610 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1611 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1612
1613 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1614
1615 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1616 out_val, 1,
1617 voffset, ctx->gs2vs_offset, 0,
1618 1, 1, true, true);
1619 }
1620 idx += slot_inc;
1621 }
1622
1623 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1624 ctx->ac.i32_1, "");
1625 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1626
1627 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1628 }
1629
1630 static void
1631 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1632 {
1633 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1634 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1635 }
1636
1637 static LLVMValueRef
1638 load_tess_coord(struct ac_shader_abi *abi)
1639 {
1640 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1641
1642 LLVMValueRef coord[4] = {
1643 ctx->tes_u,
1644 ctx->tes_v,
1645 ctx->ac.f32_0,
1646 ctx->ac.f32_0,
1647 };
1648
1649 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1650 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1651 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1652
1653 return ac_build_gather_values(&ctx->ac, coord, 3);
1654 }
1655
1656 static LLVMValueRef
1657 load_patch_vertices_in(struct ac_shader_abi *abi)
1658 {
1659 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1660 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1661 }
1662
1663
1664 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1665 {
1666 return abi->base_vertex;
1667 }
1668
1669 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1670 LLVMValueRef buffer_ptr, bool write)
1671 {
1672 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1673 LLVMValueRef result;
1674
1675 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1676
1677 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1678 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1679
1680 return result;
1681 }
1682
1683 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1684 {
1685 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1686 LLVMValueRef result;
1687
1688 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1689
1690 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1691 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1692
1693 return result;
1694 }
1695
1696 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1697 unsigned descriptor_set,
1698 unsigned base_index,
1699 unsigned constant_index,
1700 LLVMValueRef index,
1701 enum ac_descriptor_type desc_type,
1702 bool image, bool write)
1703 {
1704 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1705 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1706 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1707 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1708 unsigned offset = binding->offset;
1709 unsigned stride = binding->size;
1710 unsigned type_size;
1711 LLVMBuilderRef builder = ctx->ac.builder;
1712 LLVMTypeRef type;
1713
1714 assert(base_index < layout->binding_count);
1715
1716 switch (desc_type) {
1717 case AC_DESC_IMAGE:
1718 type = ctx->ac.v8i32;
1719 type_size = 32;
1720 break;
1721 case AC_DESC_FMASK:
1722 type = ctx->ac.v8i32;
1723 offset += 32;
1724 type_size = 32;
1725 break;
1726 case AC_DESC_SAMPLER:
1727 type = ctx->ac.v4i32;
1728 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1729 offset += 64;
1730
1731 type_size = 16;
1732 break;
1733 case AC_DESC_BUFFER:
1734 type = ctx->ac.v4i32;
1735 type_size = 16;
1736 break;
1737 default:
1738 unreachable("invalid desc_type\n");
1739 }
1740
1741 offset += constant_index * stride;
1742
1743 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1744 (!index || binding->immutable_samplers_equal)) {
1745 if (binding->immutable_samplers_equal)
1746 constant_index = 0;
1747
1748 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1749
1750 LLVMValueRef constants[] = {
1751 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1752 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1753 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1754 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1755 };
1756 return ac_build_gather_values(&ctx->ac, constants, 4);
1757 }
1758
1759 assert(stride % type_size == 0);
1760
1761 if (!index)
1762 index = ctx->ac.i32_0;
1763
1764 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1765
1766 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1767 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
1768
1769 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1770 }
1771
1772
1773 static void
1774 handle_vs_input_decl(struct radv_shader_context *ctx,
1775 struct nir_variable *variable)
1776 {
1777 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1778 LLVMValueRef t_offset;
1779 LLVMValueRef t_list;
1780 LLVMValueRef input;
1781 LLVMValueRef buffer_index;
1782 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
1783 int idx = variable->data.location;
1784 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1785 uint8_t input_usage_mask =
1786 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1787 unsigned num_channels = util_last_bit(input_usage_mask);
1788
1789 variable->data.driver_location = idx * 4;
1790
1791 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
1792 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
1793 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
1794 ctx->abi.start_instance, "");
1795 if (ctx->options->key.vs.as_ls) {
1796 ctx->shader_info->vs.vgpr_comp_cnt =
1797 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1798 } else {
1799 ctx->shader_info->vs.vgpr_comp_cnt =
1800 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1801 }
1802 } else
1803 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
1804 ctx->abi.base_vertex, "");
1805 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
1806
1807 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1808
1809 input = ac_build_buffer_load_format(&ctx->ac, t_list,
1810 buffer_index,
1811 ctx->ac.i32_0,
1812 num_channels, false, true);
1813
1814 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
1815
1816 for (unsigned chan = 0; chan < 4; chan++) {
1817 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1818 ctx->inputs[ac_llvm_reg_index_soa(idx, chan)] =
1819 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
1820 input, llvm_chan, ""));
1821 }
1822 }
1823 }
1824
1825 static void interp_fs_input(struct radv_shader_context *ctx,
1826 unsigned attr,
1827 LLVMValueRef interp_param,
1828 LLVMValueRef prim_mask,
1829 LLVMValueRef result[4])
1830 {
1831 LLVMValueRef attr_number;
1832 unsigned chan;
1833 LLVMValueRef i, j;
1834 bool interp = interp_param != NULL;
1835
1836 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
1837
1838 /* fs.constant returns the param from the middle vertex, so it's not
1839 * really useful for flat shading. It's meant to be used for custom
1840 * interpolation (but the intrinsic can't fetch from the other two
1841 * vertices).
1842 *
1843 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1844 * to do the right thing. The only reason we use fs.constant is that
1845 * fs.interp cannot be used on integers, because they can be equal
1846 * to NaN.
1847 */
1848 if (interp) {
1849 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1850 ctx->ac.v2f32, "");
1851
1852 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1853 ctx->ac.i32_0, "");
1854 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1855 ctx->ac.i32_1, "");
1856 }
1857
1858 for (chan = 0; chan < 4; chan++) {
1859 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1860
1861 if (interp) {
1862 result[chan] = ac_build_fs_interp(&ctx->ac,
1863 llvm_chan,
1864 attr_number,
1865 prim_mask, i, j);
1866 } else {
1867 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1868 LLVMConstInt(ctx->ac.i32, 2, false),
1869 llvm_chan,
1870 attr_number,
1871 prim_mask);
1872 }
1873 }
1874 }
1875
1876 static void
1877 handle_fs_input_decl(struct radv_shader_context *ctx,
1878 struct nir_variable *variable)
1879 {
1880 int idx = variable->data.location;
1881 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1882 LLVMValueRef interp;
1883
1884 variable->data.driver_location = idx * 4;
1885 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
1886
1887 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
1888 unsigned interp_type;
1889 if (variable->data.sample)
1890 interp_type = INTERP_SAMPLE;
1891 else if (variable->data.centroid)
1892 interp_type = INTERP_CENTROID;
1893 else
1894 interp_type = INTERP_CENTER;
1895
1896 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
1897 } else
1898 interp = NULL;
1899
1900 for (unsigned i = 0; i < attrib_count; ++i)
1901 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
1902
1903 }
1904
1905 static void
1906 handle_vs_inputs(struct radv_shader_context *ctx,
1907 struct nir_shader *nir) {
1908 nir_foreach_variable(variable, &nir->inputs)
1909 handle_vs_input_decl(ctx, variable);
1910 }
1911
1912 static void
1913 prepare_interp_optimize(struct radv_shader_context *ctx,
1914 struct nir_shader *nir)
1915 {
1916 if (!ctx->options->key.fs.multisample)
1917 return;
1918
1919 bool uses_center = false;
1920 bool uses_centroid = false;
1921 nir_foreach_variable(variable, &nir->inputs) {
1922 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1923 variable->data.sample)
1924 continue;
1925
1926 if (variable->data.centroid)
1927 uses_centroid = true;
1928 else
1929 uses_center = true;
1930 }
1931
1932 if (uses_center && uses_centroid) {
1933 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
1934 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
1935 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
1936 }
1937 }
1938
1939 static void
1940 handle_fs_inputs(struct radv_shader_context *ctx,
1941 struct nir_shader *nir)
1942 {
1943 prepare_interp_optimize(ctx, nir);
1944
1945 nir_foreach_variable(variable, &nir->inputs)
1946 handle_fs_input_decl(ctx, variable);
1947
1948 unsigned index = 0;
1949
1950 if (ctx->shader_info->info.ps.uses_input_attachments ||
1951 ctx->shader_info->info.needs_multiview_view_index)
1952 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
1953
1954 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
1955 LLVMValueRef interp_param;
1956 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
1957
1958 if (!(ctx->input_mask & (1ull << i)))
1959 continue;
1960
1961 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
1962 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
1963 interp_param = *inputs;
1964 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
1965 inputs);
1966
1967 if (!interp_param)
1968 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
1969 ++index;
1970 } else if (i == VARYING_SLOT_POS) {
1971 for(int i = 0; i < 3; ++i)
1972 inputs[i] = ctx->abi.frag_pos[i];
1973
1974 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
1975 ctx->abi.frag_pos[3]);
1976 }
1977 }
1978 ctx->shader_info->fs.num_interp = index;
1979 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
1980
1981 if (ctx->shader_info->info.needs_multiview_view_index)
1982 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
1983 }
1984
1985 static void
1986 scan_shader_output_decl(struct radv_shader_context *ctx,
1987 struct nir_variable *variable,
1988 struct nir_shader *shader,
1989 gl_shader_stage stage)
1990 {
1991 int idx = variable->data.location + variable->data.index;
1992 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1993 uint64_t mask_attribs;
1994
1995 variable->data.driver_location = idx * 4;
1996
1997 /* tess ctrl has it's own load/store paths for outputs */
1998 if (stage == MESA_SHADER_TESS_CTRL)
1999 return;
2000
2001 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2002 if (stage == MESA_SHADER_VERTEX ||
2003 stage == MESA_SHADER_TESS_EVAL ||
2004 stage == MESA_SHADER_GEOMETRY) {
2005 if (idx == VARYING_SLOT_CLIP_DIST0) {
2006 int length = shader->info.clip_distance_array_size +
2007 shader->info.cull_distance_array_size;
2008 if (stage == MESA_SHADER_VERTEX) {
2009 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2010 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2011 }
2012 if (stage == MESA_SHADER_TESS_EVAL) {
2013 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2014 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2015 }
2016
2017 if (length > 4)
2018 attrib_count = 2;
2019 else
2020 attrib_count = 1;
2021 mask_attribs = 1ull << idx;
2022 }
2023 }
2024
2025 ctx->output_mask |= mask_attribs;
2026 }
2027
2028
2029 /* Initialize arguments for the shader export intrinsic */
2030 static void
2031 si_llvm_init_export_args(struct radv_shader_context *ctx,
2032 LLVMValueRef *values,
2033 unsigned enabled_channels,
2034 unsigned target,
2035 struct ac_export_args *args)
2036 {
2037 /* Specify the channels that are enabled. */
2038 args->enabled_channels = enabled_channels;
2039
2040 /* Specify whether the EXEC mask represents the valid mask */
2041 args->valid_mask = 0;
2042
2043 /* Specify whether this is the last export */
2044 args->done = 0;
2045
2046 /* Specify the target we are exporting */
2047 args->target = target;
2048
2049 args->compr = false;
2050 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2051 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2052 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2053 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2054
2055 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2056 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2057 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2058 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2059 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2060 unsigned chan;
2061
2062 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2063 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2064 unsigned bits, bool hi) = NULL;
2065
2066 switch(col_format) {
2067 case V_028714_SPI_SHADER_ZERO:
2068 args->enabled_channels = 0; /* writemask */
2069 args->target = V_008DFC_SQ_EXP_NULL;
2070 break;
2071
2072 case V_028714_SPI_SHADER_32_R:
2073 args->enabled_channels = 1;
2074 args->out[0] = values[0];
2075 break;
2076
2077 case V_028714_SPI_SHADER_32_GR:
2078 args->enabled_channels = 0x3;
2079 args->out[0] = values[0];
2080 args->out[1] = values[1];
2081 break;
2082
2083 case V_028714_SPI_SHADER_32_AR:
2084 args->enabled_channels = 0x9;
2085 args->out[0] = values[0];
2086 args->out[3] = values[3];
2087 break;
2088
2089 case V_028714_SPI_SHADER_FP16_ABGR:
2090 args->enabled_channels = 0x5;
2091 packf = ac_build_cvt_pkrtz_f16;
2092 break;
2093
2094 case V_028714_SPI_SHADER_UNORM16_ABGR:
2095 args->enabled_channels = 0x5;
2096 packf = ac_build_cvt_pknorm_u16;
2097 break;
2098
2099 case V_028714_SPI_SHADER_SNORM16_ABGR:
2100 args->enabled_channels = 0x5;
2101 packf = ac_build_cvt_pknorm_i16;
2102 break;
2103
2104 case V_028714_SPI_SHADER_UINT16_ABGR:
2105 args->enabled_channels = 0x5;
2106 packi = ac_build_cvt_pk_u16;
2107 break;
2108
2109 case V_028714_SPI_SHADER_SINT16_ABGR:
2110 args->enabled_channels = 0x5;
2111 packi = ac_build_cvt_pk_i16;
2112 break;
2113
2114 default:
2115 case V_028714_SPI_SHADER_32_ABGR:
2116 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2117 break;
2118 }
2119
2120 /* Pack f16 or norm_i16/u16. */
2121 if (packf) {
2122 for (chan = 0; chan < 2; chan++) {
2123 LLVMValueRef pack_args[2] = {
2124 values[2 * chan],
2125 values[2 * chan + 1]
2126 };
2127 LLVMValueRef packed;
2128
2129 packed = packf(&ctx->ac, pack_args);
2130 args->out[chan] = ac_to_float(&ctx->ac, packed);
2131 }
2132 args->compr = 1; /* COMPR flag */
2133 }
2134
2135 /* Pack i16/u16. */
2136 if (packi) {
2137 for (chan = 0; chan < 2; chan++) {
2138 LLVMValueRef pack_args[2] = {
2139 ac_to_integer(&ctx->ac, values[2 * chan]),
2140 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2141 };
2142 LLVMValueRef packed;
2143
2144 packed = packi(&ctx->ac, pack_args,
2145 is_int8 ? 8 : is_int10 ? 10 : 16,
2146 chan == 1);
2147 args->out[chan] = ac_to_float(&ctx->ac, packed);
2148 }
2149 args->compr = 1; /* COMPR flag */
2150 }
2151 return;
2152 }
2153
2154 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2155
2156 for (unsigned i = 0; i < 4; ++i) {
2157 if (!(args->enabled_channels & (1 << i)))
2158 continue;
2159
2160 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2161 }
2162 }
2163
2164 static void
2165 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2166 LLVMValueRef *values, unsigned enabled_channels)
2167 {
2168 struct ac_export_args args;
2169
2170 si_llvm_init_export_args(ctx, values, enabled_channels,
2171 V_008DFC_SQ_EXP_PARAM + index, &args);
2172 ac_build_export(&ctx->ac, &args);
2173 }
2174
2175 static LLVMValueRef
2176 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2177 {
2178 LLVMValueRef output =
2179 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2180
2181 return LLVMBuildLoad(ctx->ac.builder, output, "");
2182 }
2183
2184 static void
2185 handle_vs_outputs_post(struct radv_shader_context *ctx,
2186 bool export_prim_id,
2187 struct radv_vs_output_info *outinfo)
2188 {
2189 uint32_t param_count = 0;
2190 unsigned target;
2191 unsigned pos_idx, num_pos_exports = 0;
2192 struct ac_export_args args, pos_args[4] = {};
2193 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2194 int i;
2195
2196 if (ctx->options->key.has_multiview_view_index) {
2197 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2198 if(!*tmp_out) {
2199 for(unsigned i = 0; i < 4; ++i)
2200 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2201 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2202 }
2203
2204 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2205 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2206 }
2207
2208 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2209 sizeof(outinfo->vs_output_param_offset));
2210
2211 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2212 LLVMValueRef slots[8];
2213 unsigned j;
2214
2215 if (outinfo->cull_dist_mask)
2216 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2217
2218 i = VARYING_SLOT_CLIP_DIST0;
2219 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
2220 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2221
2222 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
2223 slots[i] = LLVMGetUndef(ctx->ac.f32);
2224
2225 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
2226 target = V_008DFC_SQ_EXP_POS + 3;
2227 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2228 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2229 &args, sizeof(args));
2230 }
2231
2232 target = V_008DFC_SQ_EXP_POS + 2;
2233 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2234 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2235 &args, sizeof(args));
2236
2237 }
2238
2239 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2240 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2241 for (unsigned j = 0; j < 4; j++)
2242 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2243 }
2244 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2245
2246 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2247 outinfo->writes_pointsize = true;
2248 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2249 }
2250
2251 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2252 outinfo->writes_layer = true;
2253 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2254 }
2255
2256 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2257 outinfo->writes_viewport_index = true;
2258 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2259 }
2260
2261 if (outinfo->writes_pointsize ||
2262 outinfo->writes_layer ||
2263 outinfo->writes_viewport_index) {
2264 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2265 (outinfo->writes_layer == true ? 4 : 0));
2266 pos_args[1].valid_mask = 0;
2267 pos_args[1].done = 0;
2268 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2269 pos_args[1].compr = 0;
2270 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2271 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2272 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2273 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2274
2275 if (outinfo->writes_pointsize == true)
2276 pos_args[1].out[0] = psize_value;
2277 if (outinfo->writes_layer == true)
2278 pos_args[1].out[2] = layer_value;
2279 if (outinfo->writes_viewport_index == true) {
2280 if (ctx->options->chip_class >= GFX9) {
2281 /* GFX9 has the layer in out.z[10:0] and the viewport
2282 * index in out.z[19:16].
2283 */
2284 LLVMValueRef v = viewport_index_value;
2285 v = ac_to_integer(&ctx->ac, v);
2286 v = LLVMBuildShl(ctx->ac.builder, v,
2287 LLVMConstInt(ctx->ac.i32, 16, false),
2288 "");
2289 v = LLVMBuildOr(ctx->ac.builder, v,
2290 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2291
2292 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2293 pos_args[1].enabled_channels |= 1 << 2;
2294 } else {
2295 pos_args[1].out[3] = viewport_index_value;
2296 pos_args[1].enabled_channels |= 1 << 3;
2297 }
2298 }
2299 }
2300 for (i = 0; i < 4; i++) {
2301 if (pos_args[i].out[0])
2302 num_pos_exports++;
2303 }
2304
2305 pos_idx = 0;
2306 for (i = 0; i < 4; i++) {
2307 if (!pos_args[i].out[0])
2308 continue;
2309
2310 /* Specify the target we are exporting */
2311 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2312 if (pos_idx == num_pos_exports)
2313 pos_args[i].done = 1;
2314 ac_build_export(&ctx->ac, &pos_args[i]);
2315 }
2316
2317 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2318 LLVMValueRef values[4];
2319 if (!(ctx->output_mask & (1ull << i)))
2320 continue;
2321
2322 if (i != VARYING_SLOT_LAYER &&
2323 i != VARYING_SLOT_PRIMITIVE_ID &&
2324 i < VARYING_SLOT_VAR0)
2325 continue;
2326
2327 for (unsigned j = 0; j < 4; j++)
2328 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2329
2330 unsigned output_usage_mask;
2331
2332 if (ctx->stage == MESA_SHADER_VERTEX &&
2333 !ctx->is_gs_copy_shader) {
2334 output_usage_mask =
2335 ctx->shader_info->info.vs.output_usage_mask[i];
2336 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2337 output_usage_mask =
2338 ctx->shader_info->info.tes.output_usage_mask[i];
2339 } else {
2340 /* Enable all channels for the GS copy shader because
2341 * we don't know the output usage mask currently.
2342 */
2343 output_usage_mask = 0xf;
2344 }
2345
2346 radv_export_param(ctx, param_count, values, output_usage_mask);
2347
2348 outinfo->vs_output_param_offset[i] = param_count++;
2349 }
2350
2351 if (export_prim_id) {
2352 LLVMValueRef values[4];
2353
2354 values[0] = ctx->vs_prim_id;
2355 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2356 ctx->shader_info->vs.vgpr_comp_cnt);
2357 for (unsigned j = 1; j < 4; j++)
2358 values[j] = ctx->ac.f32_0;
2359
2360 radv_export_param(ctx, param_count, values, 0xf);
2361
2362 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2363 outinfo->export_prim_id = true;
2364 }
2365
2366 outinfo->pos_exports = num_pos_exports;
2367 outinfo->param_exports = param_count;
2368 }
2369
2370 static void
2371 handle_es_outputs_post(struct radv_shader_context *ctx,
2372 struct radv_es_output_info *outinfo)
2373 {
2374 int j;
2375 uint64_t max_output_written = 0;
2376 LLVMValueRef lds_base = NULL;
2377
2378 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2379 int param_index;
2380 int length = 4;
2381
2382 if (!(ctx->output_mask & (1ull << i)))
2383 continue;
2384
2385 if (i == VARYING_SLOT_CLIP_DIST0)
2386 length = ctx->num_output_clips + ctx->num_output_culls;
2387
2388 param_index = shader_io_get_unique_index(i);
2389
2390 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2391 }
2392
2393 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2394
2395 if (ctx->ac.chip_class >= GFX9) {
2396 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2397 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2398 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2399 LLVMConstInt(ctx->ac.i32, 24, false),
2400 LLVMConstInt(ctx->ac.i32, 4, false), false);
2401 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2402 LLVMBuildMul(ctx->ac.builder, wave_idx,
2403 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2404 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2405 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2406 }
2407
2408 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2409 LLVMValueRef dw_addr = NULL;
2410 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2411 int param_index;
2412 int length = 4;
2413
2414 if (!(ctx->output_mask & (1ull << i)))
2415 continue;
2416
2417 if (i == VARYING_SLOT_CLIP_DIST0)
2418 length = ctx->num_output_clips + ctx->num_output_culls;
2419
2420 param_index = shader_io_get_unique_index(i);
2421
2422 if (lds_base) {
2423 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2424 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2425 "");
2426 }
2427 for (j = 0; j < length; j++) {
2428 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2429 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2430
2431 if (ctx->ac.chip_class >= GFX9) {
2432 ac_lds_store(&ctx->ac, dw_addr,
2433 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2434 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2435 } else {
2436 ac_build_buffer_store_dword(&ctx->ac,
2437 ctx->esgs_ring,
2438 out_val, 1,
2439 NULL, ctx->es2gs_offset,
2440 (4 * param_index + j) * 4,
2441 1, 1, true, true);
2442 }
2443 }
2444 }
2445 }
2446
2447 static void
2448 handle_ls_outputs_post(struct radv_shader_context *ctx)
2449 {
2450 LLVMValueRef vertex_id = ctx->rel_auto_id;
2451 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2452 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2453 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2454 vertex_dw_stride, "");
2455
2456 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2457 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2458 int length = 4;
2459
2460 if (!(ctx->output_mask & (1ull << i)))
2461 continue;
2462
2463 if (i == VARYING_SLOT_CLIP_DIST0)
2464 length = ctx->num_output_clips + ctx->num_output_culls;
2465 int param = shader_io_get_unique_index(i);
2466 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2467 LLVMConstInt(ctx->ac.i32, param * 4, false),
2468 "");
2469 for (unsigned j = 0; j < length; j++) {
2470 ac_lds_store(&ctx->ac, dw_addr,
2471 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2472 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2473 }
2474 }
2475 }
2476
2477 struct ac_build_if_state
2478 {
2479 struct radv_shader_context *ctx;
2480 LLVMValueRef condition;
2481 LLVMBasicBlockRef entry_block;
2482 LLVMBasicBlockRef true_block;
2483 LLVMBasicBlockRef false_block;
2484 LLVMBasicBlockRef merge_block;
2485 };
2486
2487 static LLVMBasicBlockRef
2488 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
2489 {
2490 LLVMBasicBlockRef current_block;
2491 LLVMBasicBlockRef next_block;
2492 LLVMBasicBlockRef new_block;
2493
2494 /* get current basic block */
2495 current_block = LLVMGetInsertBlock(ctx->ac.builder);
2496
2497 /* chqeck if there's another block after this one */
2498 next_block = LLVMGetNextBasicBlock(current_block);
2499 if (next_block) {
2500 /* insert the new block before the next block */
2501 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
2502 }
2503 else {
2504 /* append new block after current block */
2505 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
2506 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
2507 }
2508 return new_block;
2509 }
2510
2511 static void
2512 ac_nir_build_if(struct ac_build_if_state *ifthen,
2513 struct radv_shader_context *ctx,
2514 LLVMValueRef condition)
2515 {
2516 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
2517
2518 memset(ifthen, 0, sizeof *ifthen);
2519 ifthen->ctx = ctx;
2520 ifthen->condition = condition;
2521 ifthen->entry_block = block;
2522
2523 /* create endif/merge basic block for the phi functions */
2524 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
2525
2526 /* create/insert true_block before merge_block */
2527 ifthen->true_block =
2528 LLVMInsertBasicBlockInContext(ctx->context,
2529 ifthen->merge_block,
2530 "if-true-block");
2531
2532 /* successive code goes into the true block */
2533 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
2534 }
2535
2536 /**
2537 * End a conditional.
2538 */
2539 static void
2540 ac_nir_build_endif(struct ac_build_if_state *ifthen)
2541 {
2542 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
2543
2544 /* Insert branch to the merge block from current block */
2545 LLVMBuildBr(builder, ifthen->merge_block);
2546
2547 /*
2548 * Now patch in the various branch instructions.
2549 */
2550
2551 /* Insert the conditional branch instruction at the end of entry_block */
2552 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
2553 if (ifthen->false_block) {
2554 /* we have an else clause */
2555 LLVMBuildCondBr(builder, ifthen->condition,
2556 ifthen->true_block, ifthen->false_block);
2557 }
2558 else {
2559 /* no else clause */
2560 LLVMBuildCondBr(builder, ifthen->condition,
2561 ifthen->true_block, ifthen->merge_block);
2562 }
2563
2564 /* Resume building code at end of the ifthen->merge_block */
2565 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
2566 }
2567
2568 static void
2569 write_tess_factors(struct radv_shader_context *ctx)
2570 {
2571 unsigned stride, outer_comps, inner_comps;
2572 struct ac_build_if_state if_ctx, inner_if_ctx;
2573 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2574 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2575 unsigned tess_inner_index = 0, tess_outer_index;
2576 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2577 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2578 int i;
2579 ac_emit_barrier(&ctx->ac, ctx->stage);
2580
2581 switch (ctx->options->key.tcs.primitive_mode) {
2582 case GL_ISOLINES:
2583 stride = 2;
2584 outer_comps = 2;
2585 inner_comps = 0;
2586 break;
2587 case GL_TRIANGLES:
2588 stride = 4;
2589 outer_comps = 3;
2590 inner_comps = 1;
2591 break;
2592 case GL_QUADS:
2593 stride = 6;
2594 outer_comps = 4;
2595 inner_comps = 2;
2596 break;
2597 default:
2598 return;
2599 }
2600
2601 ac_nir_build_if(&if_ctx, ctx,
2602 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2603 invocation_id, ctx->ac.i32_0, ""));
2604
2605 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2606
2607 if (inner_comps) {
2608 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2609 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2610 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2611 }
2612
2613 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2614 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2615 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2616
2617 for (i = 0; i < 4; i++) {
2618 inner[i] = LLVMGetUndef(ctx->ac.i32);
2619 outer[i] = LLVMGetUndef(ctx->ac.i32);
2620 }
2621
2622 // LINES reverseal
2623 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2624 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2625 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2626 ctx->ac.i32_1, "");
2627 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2628 } else {
2629 for (i = 0; i < outer_comps; i++) {
2630 outer[i] = out[i] =
2631 ac_lds_load(&ctx->ac, lds_outer);
2632 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2633 ctx->ac.i32_1, "");
2634 }
2635 for (i = 0; i < inner_comps; i++) {
2636 inner[i] = out[outer_comps+i] =
2637 ac_lds_load(&ctx->ac, lds_inner);
2638 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2639 ctx->ac.i32_1, "");
2640 }
2641 }
2642
2643 /* Convert the outputs to vectors for stores. */
2644 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2645 vec1 = NULL;
2646
2647 if (stride > 4)
2648 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2649
2650
2651 buffer = ctx->hs_ring_tess_factor;
2652 tf_base = ctx->tess_factor_offset;
2653 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2654 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2655 unsigned tf_offset = 0;
2656
2657 if (ctx->options->chip_class <= VI) {
2658 ac_nir_build_if(&inner_if_ctx, ctx,
2659 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2660 rel_patch_id, ctx->ac.i32_0, ""));
2661
2662 /* Store the dynamic HS control word. */
2663 ac_build_buffer_store_dword(&ctx->ac, buffer,
2664 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2665 1, ctx->ac.i32_0, tf_base,
2666 0, 1, 0, true, false);
2667 tf_offset += 4;
2668
2669 ac_nir_build_endif(&inner_if_ctx);
2670 }
2671
2672 /* Store the tessellation factors. */
2673 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2674 MIN2(stride, 4), byteoffset, tf_base,
2675 tf_offset, 1, 0, true, false);
2676 if (vec1)
2677 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2678 stride - 4, byteoffset, tf_base,
2679 16 + tf_offset, 1, 0, true, false);
2680
2681 //store to offchip for TES to read - only if TES reads them
2682 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2683 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2684 LLVMValueRef tf_inner_offset;
2685 unsigned param_outer, param_inner;
2686
2687 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2688 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2689 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2690
2691 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2692 util_next_power_of_two(outer_comps));
2693
2694 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2695 outer_comps, tf_outer_offset,
2696 ctx->oc_lds, 0, 1, 0, true, false);
2697 if (inner_comps) {
2698 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2699 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2700 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2701
2702 inner_vec = inner_comps == 1 ? inner[0] :
2703 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2704 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2705 inner_comps, tf_inner_offset,
2706 ctx->oc_lds, 0, 1, 0, true, false);
2707 }
2708 }
2709 ac_nir_build_endif(&if_ctx);
2710 }
2711
2712 static void
2713 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2714 {
2715 write_tess_factors(ctx);
2716 }
2717
2718 static bool
2719 si_export_mrt_color(struct radv_shader_context *ctx,
2720 LLVMValueRef *color, unsigned index,
2721 struct ac_export_args *args)
2722 {
2723 /* Export */
2724 si_llvm_init_export_args(ctx, color, 0xf,
2725 V_008DFC_SQ_EXP_MRT + index, args);
2726 if (!args->enabled_channels)
2727 return false; /* unnecessary NULL export */
2728
2729 return true;
2730 }
2731
2732 static void
2733 radv_export_mrt_z(struct radv_shader_context *ctx,
2734 LLVMValueRef depth, LLVMValueRef stencil,
2735 LLVMValueRef samplemask)
2736 {
2737 struct ac_export_args args;
2738
2739 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2740
2741 ac_build_export(&ctx->ac, &args);
2742 }
2743
2744 static void
2745 handle_fs_outputs_post(struct radv_shader_context *ctx)
2746 {
2747 unsigned index = 0;
2748 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2749 struct ac_export_args color_args[8];
2750
2751 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2752 LLVMValueRef values[4];
2753
2754 if (!(ctx->output_mask & (1ull << i)))
2755 continue;
2756
2757 if (i < FRAG_RESULT_DATA0)
2758 continue;
2759
2760 for (unsigned j = 0; j < 4; j++)
2761 values[j] = ac_to_float(&ctx->ac,
2762 radv_load_output(ctx, i, j));
2763
2764 bool ret = si_export_mrt_color(ctx, values,
2765 i - FRAG_RESULT_DATA0,
2766 &color_args[index]);
2767 if (ret)
2768 index++;
2769 }
2770
2771 /* Process depth, stencil, samplemask. */
2772 if (ctx->shader_info->info.ps.writes_z) {
2773 depth = ac_to_float(&ctx->ac,
2774 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
2775 }
2776 if (ctx->shader_info->info.ps.writes_stencil) {
2777 stencil = ac_to_float(&ctx->ac,
2778 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
2779 }
2780 if (ctx->shader_info->info.ps.writes_sample_mask) {
2781 samplemask = ac_to_float(&ctx->ac,
2782 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
2783 }
2784
2785 /* Set the DONE bit on last non-null color export only if Z isn't
2786 * exported.
2787 */
2788 if (index > 0 &&
2789 !ctx->shader_info->info.ps.writes_z &&
2790 !ctx->shader_info->info.ps.writes_stencil &&
2791 !ctx->shader_info->info.ps.writes_sample_mask) {
2792 unsigned last = index - 1;
2793
2794 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
2795 color_args[last].done = 1; /* DONE bit */
2796 }
2797
2798 /* Export PS outputs. */
2799 for (unsigned i = 0; i < index; i++)
2800 ac_build_export(&ctx->ac, &color_args[i]);
2801
2802 if (depth || stencil || samplemask)
2803 radv_export_mrt_z(ctx, depth, stencil, samplemask);
2804 else if (!index)
2805 ac_build_export_null(&ctx->ac);
2806 }
2807
2808 static void
2809 emit_gs_epilogue(struct radv_shader_context *ctx)
2810 {
2811 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
2812 }
2813
2814 static void
2815 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
2816 LLVMValueRef *addrs)
2817 {
2818 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2819
2820 switch (ctx->stage) {
2821 case MESA_SHADER_VERTEX:
2822 if (ctx->options->key.vs.as_ls)
2823 handle_ls_outputs_post(ctx);
2824 else if (ctx->options->key.vs.as_es)
2825 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
2826 else
2827 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
2828 &ctx->shader_info->vs.outinfo);
2829 break;
2830 case MESA_SHADER_FRAGMENT:
2831 handle_fs_outputs_post(ctx);
2832 break;
2833 case MESA_SHADER_GEOMETRY:
2834 emit_gs_epilogue(ctx);
2835 break;
2836 case MESA_SHADER_TESS_CTRL:
2837 handle_tcs_outputs_post(ctx);
2838 break;
2839 case MESA_SHADER_TESS_EVAL:
2840 if (ctx->options->key.tes.as_es)
2841 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
2842 else
2843 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
2844 &ctx->shader_info->tes.outinfo);
2845 break;
2846 default:
2847 break;
2848 }
2849 }
2850
2851 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
2852 {
2853 LLVMPassManagerRef passmgr;
2854 /* Create the pass manager */
2855 passmgr = LLVMCreateFunctionPassManagerForModule(
2856 ctx->ac.module);
2857
2858 /* This pass should eliminate all the load and store instructions */
2859 LLVMAddPromoteMemoryToRegisterPass(passmgr);
2860
2861 /* Add some optimization passes */
2862 LLVMAddScalarReplAggregatesPass(passmgr);
2863 LLVMAddLICMPass(passmgr);
2864 LLVMAddAggressiveDCEPass(passmgr);
2865 LLVMAddCFGSimplificationPass(passmgr);
2866 LLVMAddInstructionCombiningPass(passmgr);
2867
2868 /* Run the pass */
2869 LLVMInitializeFunctionPassManager(passmgr);
2870 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
2871 LLVMFinalizeFunctionPassManager(passmgr);
2872
2873 LLVMDisposeBuilder(ctx->ac.builder);
2874 LLVMDisposePassManager(passmgr);
2875
2876 ac_llvm_context_dispose(&ctx->ac);
2877 }
2878
2879 static void
2880 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
2881 {
2882 struct radv_vs_output_info *outinfo;
2883
2884 switch (ctx->stage) {
2885 case MESA_SHADER_FRAGMENT:
2886 case MESA_SHADER_COMPUTE:
2887 case MESA_SHADER_TESS_CTRL:
2888 case MESA_SHADER_GEOMETRY:
2889 return;
2890 case MESA_SHADER_VERTEX:
2891 if (ctx->options->key.vs.as_ls ||
2892 ctx->options->key.vs.as_es)
2893 return;
2894 outinfo = &ctx->shader_info->vs.outinfo;
2895 break;
2896 case MESA_SHADER_TESS_EVAL:
2897 if (ctx->options->key.vs.as_es)
2898 return;
2899 outinfo = &ctx->shader_info->tes.outinfo;
2900 break;
2901 default:
2902 unreachable("Unhandled shader type");
2903 }
2904
2905 ac_optimize_vs_outputs(&ctx->ac,
2906 ctx->main_function,
2907 outinfo->vs_output_param_offset,
2908 VARYING_SLOT_MAX,
2909 &outinfo->param_exports);
2910 }
2911
2912 static void
2913 ac_setup_rings(struct radv_shader_context *ctx)
2914 {
2915 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
2916 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
2917 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
2918 }
2919
2920 if (ctx->is_gs_copy_shader) {
2921 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
2922 }
2923 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2924 LLVMValueRef tmp;
2925 uint32_t num_entries = 64;
2926 LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size, false);
2927 LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size << 16, false);
2928 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
2929 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
2930
2931 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
2932
2933 tmp = LLVMConstInt(ctx->ac.i32, num_entries, false);
2934 if (ctx->options->chip_class >= VI)
2935 tmp = LLVMBuildMul(ctx->ac.builder, gsvs_ring_stride, tmp, "");
2936 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
2937 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
2938 tmp = LLVMBuildOr(ctx->ac.builder, tmp, gsvs_ring_desc, "");
2939 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
2940 }
2941
2942 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
2943 ctx->stage == MESA_SHADER_TESS_EVAL) {
2944 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
2945 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
2946 }
2947 }
2948
2949 static unsigned
2950 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
2951 const struct nir_shader *nir)
2952 {
2953 switch (nir->info.stage) {
2954 case MESA_SHADER_TESS_CTRL:
2955 return chip_class >= CIK ? 128 : 64;
2956 case MESA_SHADER_GEOMETRY:
2957 return chip_class >= GFX9 ? 128 : 64;
2958 case MESA_SHADER_COMPUTE:
2959 break;
2960 default:
2961 return 0;
2962 }
2963
2964 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
2965 nir->info.cs.local_size[1] *
2966 nir->info.cs.local_size[2];
2967 return max_workgroup_size;
2968 }
2969
2970 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
2971 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
2972 {
2973 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2974 LLVMConstInt(ctx->ac.i32, 8, false),
2975 LLVMConstInt(ctx->ac.i32, 8, false), false);
2976 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
2977 ctx->ac.i32_0, "");
2978 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
2979 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
2980 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
2981 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
2982 }
2983
2984 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
2985 {
2986 for(int i = 5; i >= 0; --i) {
2987 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
2988 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
2989 LLVMConstInt(ctx->ac.i32, 16, false), false);
2990 }
2991
2992 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2993 LLVMConstInt(ctx->ac.i32, 16, false),
2994 LLVMConstInt(ctx->ac.i32, 8, false), false);
2995 }
2996
2997
2998 static
2999 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
3000 struct nir_shader *const *shaders,
3001 int shader_count,
3002 struct radv_shader_variant_info *shader_info,
3003 const struct radv_nir_compiler_options *options)
3004 {
3005 struct radv_shader_context ctx = {0};
3006 unsigned i;
3007 ctx.options = options;
3008 ctx.shader_info = shader_info;
3009 ctx.context = LLVMContextCreate();
3010
3011 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3012 options->family);
3013 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3014 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
3015
3016 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
3017 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
3018 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
3019 LLVMDisposeTargetData(data_layout);
3020 LLVMDisposeMessage(data_layout_str);
3021
3022 enum ac_float_mode float_mode =
3023 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3024 AC_FLOAT_MODE_DEFAULT;
3025
3026 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3027
3028 memset(shader_info, 0, sizeof(*shader_info));
3029
3030 for(int i = 0; i < shader_count; ++i)
3031 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3032
3033 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3034 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3035 for (i = 0; i < AC_UD_MAX_UD; i++)
3036 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3037
3038 ctx.max_workgroup_size = 0;
3039 for (int i = 0; i < shader_count; ++i) {
3040 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3041 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3042 shaders[i]));
3043 }
3044
3045 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3046 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3047
3048 ctx.abi.inputs = &ctx.inputs[0];
3049 ctx.abi.emit_outputs = handle_shader_outputs_post;
3050 ctx.abi.emit_vertex = visit_emit_vertex;
3051 ctx.abi.load_ubo = radv_load_ubo;
3052 ctx.abi.load_ssbo = radv_load_ssbo;
3053 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3054 ctx.abi.load_resource = radv_load_resource;
3055 ctx.abi.clamp_shadow_reference = false;
3056
3057 if (shader_count >= 2)
3058 ac_init_exec_full_mask(&ctx.ac);
3059
3060 if (ctx.ac.chip_class == GFX9 &&
3061 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3062 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3063
3064 for(int i = 0; i < shader_count; ++i) {
3065 ctx.stage = shaders[i]->info.stage;
3066 ctx.output_mask = 0;
3067 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3068 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3069
3070 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3071 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3072 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3073 ctx.abi.load_inputs = load_gs_input;
3074 ctx.abi.emit_primitive = visit_end_primitive;
3075 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3076 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3077 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3078 ctx.abi.load_tess_varyings = load_tcs_varyings;
3079 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3080 ctx.abi.store_tcs_outputs = store_tcs_output;
3081 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3082 if (shader_count == 1)
3083 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3084 else
3085 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3086 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3087 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3088 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3089 ctx.abi.load_tess_varyings = load_tes_input;
3090 ctx.abi.load_tess_coord = load_tess_coord;
3091 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3092 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3093 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3094 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3095 if (shader_info->info.vs.needs_instance_id) {
3096 if (ctx.options->key.vs.as_ls) {
3097 ctx.shader_info->vs.vgpr_comp_cnt =
3098 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3099 } else {
3100 ctx.shader_info->vs.vgpr_comp_cnt =
3101 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3102 }
3103 }
3104 ctx.abi.load_base_vertex = radv_load_base_vertex;
3105 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3106 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3107 ctx.abi.lookup_interp_param = lookup_interp_param;
3108 ctx.abi.load_sample_position = load_sample_position;
3109 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3110 ctx.abi.emit_kill = radv_emit_kill;
3111 }
3112
3113 if (i)
3114 ac_emit_barrier(&ctx.ac, ctx.stage);
3115
3116 nir_foreach_variable(variable, &shaders[i]->outputs)
3117 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3118
3119 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3120 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3121 shaders[i]->info.cull_distance_array_size > 4;
3122 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3123 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3124 shaders[i]->info.gs.vertices_out;
3125 }
3126
3127 ac_setup_rings(&ctx);
3128
3129 LLVMBasicBlockRef merge_block;
3130 if (shader_count >= 2) {
3131 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3132 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3133 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3134
3135 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3136 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3137 LLVMConstInt(ctx.ac.i32, 8, false), false);
3138 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3139 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3140 thread_id, count, "");
3141 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3142
3143 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3144 }
3145
3146 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3147 handle_fs_inputs(&ctx, shaders[i]);
3148 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3149 handle_vs_inputs(&ctx, shaders[i]);
3150 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3151 prepare_gs_input_vgprs(&ctx);
3152
3153 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3154
3155 if (shader_count >= 2) {
3156 LLVMBuildBr(ctx.ac.builder, merge_block);
3157 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3158 }
3159
3160 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3161 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3162 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3163 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3164 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3165 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3166 }
3167 }
3168
3169 LLVMBuildRetVoid(ctx.ac.builder);
3170
3171 if (options->dump_preoptir)
3172 ac_dump_module(ctx.ac.module);
3173
3174 ac_llvm_finalize_module(&ctx);
3175
3176 if (shader_count == 1)
3177 ac_nir_eliminate_const_vs_outputs(&ctx);
3178
3179 if (options->dump_shader) {
3180 ctx.shader_info->private_mem_vgprs =
3181 ac_count_scratch_private_memory(ctx.main_function);
3182 }
3183
3184 return ctx.ac.module;
3185 }
3186
3187 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3188 {
3189 unsigned *retval = (unsigned *)context;
3190 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3191 char *description = LLVMGetDiagInfoDescription(di);
3192
3193 if (severity == LLVMDSError) {
3194 *retval = 1;
3195 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3196 description);
3197 }
3198
3199 LLVMDisposeMessage(description);
3200 }
3201
3202 static unsigned ac_llvm_compile(LLVMModuleRef M,
3203 struct ac_shader_binary *binary,
3204 LLVMTargetMachineRef tm)
3205 {
3206 unsigned retval = 0;
3207 char *err;
3208 LLVMContextRef llvm_ctx;
3209 LLVMMemoryBufferRef out_buffer;
3210 unsigned buffer_size;
3211 const char *buffer_data;
3212 LLVMBool mem_err;
3213
3214 /* Setup Diagnostic Handler*/
3215 llvm_ctx = LLVMGetModuleContext(M);
3216
3217 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3218 &retval);
3219
3220 /* Compile IR*/
3221 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
3222 &err, &out_buffer);
3223
3224 /* Process Errors/Warnings */
3225 if (mem_err) {
3226 fprintf(stderr, "%s: %s", __FUNCTION__, err);
3227 free(err);
3228 retval = 1;
3229 goto out;
3230 }
3231
3232 /* Extract Shader Code*/
3233 buffer_size = LLVMGetBufferSize(out_buffer);
3234 buffer_data = LLVMGetBufferStart(out_buffer);
3235
3236 ac_elf_read(buffer_data, buffer_size, binary);
3237
3238 /* Clean up */
3239 LLVMDisposeMemoryBuffer(out_buffer);
3240
3241 out:
3242 return retval;
3243 }
3244
3245 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
3246 LLVMModuleRef llvm_module,
3247 struct ac_shader_binary *binary,
3248 struct ac_shader_config *config,
3249 struct radv_shader_variant_info *shader_info,
3250 gl_shader_stage stage,
3251 const struct radv_nir_compiler_options *options)
3252 {
3253 if (options->dump_shader)
3254 ac_dump_module(llvm_module);
3255
3256 memset(binary, 0, sizeof(*binary));
3257
3258 if (options->record_llvm_ir) {
3259 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3260 binary->llvm_ir_string = strdup(llvm_ir);
3261 LLVMDisposeMessage(llvm_ir);
3262 }
3263
3264 int v = ac_llvm_compile(llvm_module, binary, tm);
3265 if (v) {
3266 fprintf(stderr, "compile failed\n");
3267 }
3268
3269 if (options->dump_shader)
3270 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3271
3272 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3273
3274 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3275 LLVMDisposeModule(llvm_module);
3276 LLVMContextDispose(ctx);
3277
3278 if (stage == MESA_SHADER_FRAGMENT) {
3279 shader_info->num_input_vgprs = 0;
3280 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3281 shader_info->num_input_vgprs += 2;
3282 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3283 shader_info->num_input_vgprs += 2;
3284 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3285 shader_info->num_input_vgprs += 2;
3286 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3287 shader_info->num_input_vgprs += 3;
3288 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3289 shader_info->num_input_vgprs += 2;
3290 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3291 shader_info->num_input_vgprs += 2;
3292 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3293 shader_info->num_input_vgprs += 2;
3294 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3295 shader_info->num_input_vgprs += 1;
3296 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3297 shader_info->num_input_vgprs += 1;
3298 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3299 shader_info->num_input_vgprs += 1;
3300 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3301 shader_info->num_input_vgprs += 1;
3302 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3303 shader_info->num_input_vgprs += 1;
3304 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3305 shader_info->num_input_vgprs += 1;
3306 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3307 shader_info->num_input_vgprs += 1;
3308 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3309 shader_info->num_input_vgprs += 1;
3310 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3311 shader_info->num_input_vgprs += 1;
3312 }
3313 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3314
3315 /* +3 for scratch wave offset and VCC */
3316 config->num_sgprs = MAX2(config->num_sgprs,
3317 shader_info->num_input_sgprs + 3);
3318
3319 /* Enable 64-bit and 16-bit denormals, because there is no performance
3320 * cost.
3321 *
3322 * If denormals are enabled, all floating-point output modifiers are
3323 * ignored.
3324 *
3325 * Don't enable denormals for 32-bit floats, because:
3326 * - Floating-point output modifiers would be ignored by the hw.
3327 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3328 * have to stop using those.
3329 * - SI & CI would be very slow.
3330 */
3331 config->float_mode |= V_00B028_FP_64_DENORMS;
3332 }
3333
3334 static void
3335 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3336 {
3337 switch (nir->info.stage) {
3338 case MESA_SHADER_COMPUTE:
3339 for (int i = 0; i < 3; ++i)
3340 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3341 break;
3342 case MESA_SHADER_FRAGMENT:
3343 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3344 break;
3345 case MESA_SHADER_GEOMETRY:
3346 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3347 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3348 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3349 shader_info->gs.invocations = nir->info.gs.invocations;
3350 break;
3351 case MESA_SHADER_TESS_EVAL:
3352 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3353 shader_info->tes.spacing = nir->info.tess.spacing;
3354 shader_info->tes.ccw = nir->info.tess.ccw;
3355 shader_info->tes.point_mode = nir->info.tess.point_mode;
3356 shader_info->tes.as_es = options->key.tes.as_es;
3357 break;
3358 case MESA_SHADER_TESS_CTRL:
3359 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3360 break;
3361 case MESA_SHADER_VERTEX:
3362 shader_info->vs.as_es = options->key.vs.as_es;
3363 shader_info->vs.as_ls = options->key.vs.as_ls;
3364 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3365 if (options->key.vs.as_ls)
3366 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3367 break;
3368 default:
3369 break;
3370 }
3371 }
3372
3373 void
3374 radv_compile_nir_shader(LLVMTargetMachineRef tm,
3375 struct ac_shader_binary *binary,
3376 struct ac_shader_config *config,
3377 struct radv_shader_variant_info *shader_info,
3378 struct nir_shader *const *nir,
3379 int nir_count,
3380 const struct radv_nir_compiler_options *options)
3381 {
3382
3383 LLVMModuleRef llvm_module;
3384
3385 llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
3386 options);
3387
3388 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
3389 nir[0]->info.stage, options);
3390
3391 for (int i = 0; i < nir_count; ++i)
3392 ac_fill_shader_info(shader_info, nir[i], options);
3393
3394 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3395 if (options->chip_class == GFX9) {
3396 if (nir_count == 2 &&
3397 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3398 shader_info->gs.es_type = nir[0]->info.stage;
3399 }
3400 }
3401 }
3402
3403 static void
3404 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3405 {
3406 LLVMValueRef vtx_offset =
3407 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3408 LLVMConstInt(ctx->ac.i32, 4, false), "");
3409 int idx = 0;
3410
3411 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3412 int length = 4;
3413 int slot = idx;
3414 int slot_inc = 1;
3415 if (!(ctx->output_mask & (1ull << i)))
3416 continue;
3417
3418 if (i == VARYING_SLOT_CLIP_DIST0) {
3419 /* unpack clip and cull from a single set of slots */
3420 length = ctx->num_output_clips + ctx->num_output_culls;
3421 if (length > 4)
3422 slot_inc = 2;
3423 }
3424
3425 for (unsigned j = 0; j < length; j++) {
3426 LLVMValueRef value, soffset;
3427
3428 soffset = LLVMConstInt(ctx->ac.i32,
3429 (slot * 4 + j) *
3430 ctx->gs_max_out_vertices * 16 * 4, false);
3431
3432 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3433 1, ctx->ac.i32_0,
3434 vtx_offset, soffset,
3435 0, 1, 1, true, false);
3436
3437 LLVMBuildStore(ctx->ac.builder,
3438 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3439 }
3440 idx += slot_inc;
3441 }
3442 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
3443 }
3444
3445 void
3446 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
3447 struct nir_shader *geom_shader,
3448 struct ac_shader_binary *binary,
3449 struct ac_shader_config *config,
3450 struct radv_shader_variant_info *shader_info,
3451 const struct radv_nir_compiler_options *options)
3452 {
3453 struct radv_shader_context ctx = {0};
3454 ctx.context = LLVMContextCreate();
3455 ctx.options = options;
3456 ctx.shader_info = shader_info;
3457
3458 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3459 options->family);
3460 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3461
3462 ctx.is_gs_copy_shader = true;
3463 LLVMSetTarget(ctx.ac.module, "amdgcn--");
3464
3465 enum ac_float_mode float_mode =
3466 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3467 AC_FLOAT_MODE_DEFAULT;
3468
3469 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3470 ctx.stage = MESA_SHADER_VERTEX;
3471
3472 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3473
3474 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3475 ac_setup_rings(&ctx);
3476
3477 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3478 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3479
3480 nir_foreach_variable(variable, &geom_shader->outputs) {
3481 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3482 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3483 variable, MESA_SHADER_VERTEX);
3484 }
3485
3486 ac_gs_copy_shader_emit(&ctx);
3487
3488 LLVMBuildRetVoid(ctx.ac.builder);
3489
3490 ac_llvm_finalize_module(&ctx);
3491
3492 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
3493 MESA_SHADER_VERTEX, options);
3494 }