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radv: bump the maximum number of arguments to 64
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "nir/nir.h"
32
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #if HAVE_LLVM >= 0x0700
37 #include <llvm-c/Transforms/Utils.h>
38 #endif
39
40 #include "sid.h"
41 #include "gfx9d.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_llvm_build.h"
45 #include "ac_shader_abi.h"
46 #include "ac_shader_util.h"
47 #include "ac_exp_param.h"
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct radv_shader_context {
52 struct ac_llvm_context ac;
53 const struct radv_nir_compiler_options *options;
54 struct radv_shader_variant_info *shader_info;
55 struct ac_shader_abi abi;
56
57 unsigned max_workgroup_size;
58 LLVMContextRef context;
59 LLVMValueRef main_function;
60
61 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
62 LLVMValueRef ring_offsets;
63
64 LLVMValueRef vertex_buffers;
65 LLVMValueRef rel_auto_id;
66 LLVMValueRef vs_prim_id;
67 LLVMValueRef es2gs_offset;
68
69 LLVMValueRef oc_lds;
70 LLVMValueRef merged_wave_info;
71 LLVMValueRef tess_factor_offset;
72 LLVMValueRef tes_rel_patch_id;
73 LLVMValueRef tes_u;
74 LLVMValueRef tes_v;
75
76 LLVMValueRef gs2vs_offset;
77 LLVMValueRef gs_wave_id;
78 LLVMValueRef gs_vtx_offset[6];
79
80 LLVMValueRef esgs_ring;
81 LLVMValueRef gsvs_ring;
82 LLVMValueRef hs_ring_tess_offchip;
83 LLVMValueRef hs_ring_tess_factor;
84
85 LLVMValueRef persp_sample, persp_center, persp_centroid;
86 LLVMValueRef linear_sample, linear_center, linear_centroid;
87
88 gl_shader_stage stage;
89
90 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
91
92 uint64_t input_mask;
93 uint64_t output_mask;
94
95 bool is_gs_copy_shader;
96 LLVMValueRef gs_next_vertex;
97 unsigned gs_max_out_vertices;
98
99 unsigned tes_primitive_mode;
100
101 uint32_t tcs_patch_outputs_read;
102 uint64_t tcs_outputs_read;
103 uint32_t tcs_vertices_per_patch;
104 uint32_t tcs_num_inputs;
105 uint32_t tcs_num_patches;
106 uint32_t max_gsvs_emit_size;
107 uint32_t gsvs_vertex_size;
108 };
109
110 enum radeon_llvm_calling_convention {
111 RADEON_LLVM_AMDGPU_VS = 87,
112 RADEON_LLVM_AMDGPU_GS = 88,
113 RADEON_LLVM_AMDGPU_PS = 89,
114 RADEON_LLVM_AMDGPU_CS = 90,
115 RADEON_LLVM_AMDGPU_HS = 93,
116 };
117
118 static inline struct radv_shader_context *
119 radv_shader_context_from_abi(struct ac_shader_abi *abi)
120 {
121 struct radv_shader_context *ctx = NULL;
122 return container_of(abi, ctx, abi);
123 }
124
125 struct ac_build_if_state
126 {
127 struct radv_shader_context *ctx;
128 LLVMValueRef condition;
129 LLVMBasicBlockRef entry_block;
130 LLVMBasicBlockRef true_block;
131 LLVMBasicBlockRef false_block;
132 LLVMBasicBlockRef merge_block;
133 };
134
135 static LLVMBasicBlockRef
136 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
137 {
138 LLVMBasicBlockRef current_block;
139 LLVMBasicBlockRef next_block;
140 LLVMBasicBlockRef new_block;
141
142 /* get current basic block */
143 current_block = LLVMGetInsertBlock(ctx->ac.builder);
144
145 /* chqeck if there's another block after this one */
146 next_block = LLVMGetNextBasicBlock(current_block);
147 if (next_block) {
148 /* insert the new block before the next block */
149 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
150 }
151 else {
152 /* append new block after current block */
153 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
154 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
155 }
156 return new_block;
157 }
158
159 static void
160 ac_nir_build_if(struct ac_build_if_state *ifthen,
161 struct radv_shader_context *ctx,
162 LLVMValueRef condition)
163 {
164 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
165
166 memset(ifthen, 0, sizeof *ifthen);
167 ifthen->ctx = ctx;
168 ifthen->condition = condition;
169 ifthen->entry_block = block;
170
171 /* create endif/merge basic block for the phi functions */
172 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
173
174 /* create/insert true_block before merge_block */
175 ifthen->true_block =
176 LLVMInsertBasicBlockInContext(ctx->context,
177 ifthen->merge_block,
178 "if-true-block");
179
180 /* successive code goes into the true block */
181 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
182 }
183
184 /**
185 * End a conditional.
186 */
187 static void
188 ac_nir_build_endif(struct ac_build_if_state *ifthen)
189 {
190 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
191
192 /* Insert branch to the merge block from current block */
193 LLVMBuildBr(builder, ifthen->merge_block);
194
195 /*
196 * Now patch in the various branch instructions.
197 */
198
199 /* Insert the conditional branch instruction at the end of entry_block */
200 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
201 if (ifthen->false_block) {
202 /* we have an else clause */
203 LLVMBuildCondBr(builder, ifthen->condition,
204 ifthen->true_block, ifthen->false_block);
205 }
206 else {
207 /* no else clause */
208 LLVMBuildCondBr(builder, ifthen->condition,
209 ifthen->true_block, ifthen->merge_block);
210 }
211
212 /* Resume building code at end of the ifthen->merge_block */
213 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
214 }
215
216
217 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
218 {
219 switch (ctx->stage) {
220 case MESA_SHADER_TESS_CTRL:
221 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
222 case MESA_SHADER_TESS_EVAL:
223 return ctx->tes_rel_patch_id;
224 break;
225 default:
226 unreachable("Illegal stage");
227 }
228 }
229
230 static unsigned
231 get_tcs_num_patches(struct radv_shader_context *ctx)
232 {
233 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
234 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
235 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
236 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
237 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
238 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
239 uint32_t output_vertex_size = num_tcs_outputs * 16;
240 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
241 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
242 unsigned num_patches;
243 unsigned hardware_lds_size;
244
245 /* Ensure that we only need one wave per SIMD so we don't need to check
246 * resource usage. Also ensures that the number of tcs in and out
247 * vertices per threadgroup are at most 256.
248 */
249 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
250 /* Make sure that the data fits in LDS. This assumes the shaders only
251 * use LDS for the inputs and outputs.
252 */
253 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
254 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
255 /* Make sure the output data fits in the offchip buffer */
256 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
257 /* Not necessary for correctness, but improves performance. The
258 * specific value is taken from the proprietary driver.
259 */
260 num_patches = MIN2(num_patches, 40);
261
262 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
263 if (ctx->options->chip_class == SI) {
264 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
265 num_patches = MIN2(num_patches, one_wave);
266 }
267 return num_patches;
268 }
269
270 static unsigned
271 calculate_tess_lds_size(struct radv_shader_context *ctx)
272 {
273 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
274 unsigned num_tcs_output_cp;
275 unsigned num_tcs_outputs, num_tcs_patch_outputs;
276 unsigned input_vertex_size, output_vertex_size;
277 unsigned input_patch_size, output_patch_size;
278 unsigned pervertex_output_patch_size;
279 unsigned output_patch0_offset;
280 unsigned num_patches;
281 unsigned lds_size;
282
283 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
284 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
285 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
286
287 input_vertex_size = ctx->tcs_num_inputs * 16;
288 output_vertex_size = num_tcs_outputs * 16;
289
290 input_patch_size = num_tcs_input_cp * input_vertex_size;
291
292 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
293 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
294
295 num_patches = ctx->tcs_num_patches;
296 output_patch0_offset = input_patch_size * num_patches;
297
298 lds_size = output_patch0_offset + output_patch_size * num_patches;
299 return lds_size;
300 }
301
302 /* Tessellation shaders pass outputs to the next shader using LDS.
303 *
304 * LS outputs = TCS inputs
305 * TCS outputs = TES inputs
306 *
307 * The LDS layout is:
308 * - TCS inputs for patch 0
309 * - TCS inputs for patch 1
310 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
311 * - ...
312 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
313 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
314 * - TCS outputs for patch 1
315 * - Per-patch TCS outputs for patch 1
316 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
317 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
318 * - ...
319 *
320 * All three shaders VS(LS), TCS, TES share the same LDS space.
321 */
322 static LLVMValueRef
323 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
324 {
325 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
326 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
327 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
328
329 input_patch_size /= 4;
330 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
331 }
332
333 static LLVMValueRef
334 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
335 {
336 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
337 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
338 uint32_t output_vertex_size = num_tcs_outputs * 16;
339 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
340 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
341 output_patch_size /= 4;
342 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
343 }
344
345 static LLVMValueRef
346 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
347 {
348 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
349 uint32_t output_vertex_size = num_tcs_outputs * 16;
350 output_vertex_size /= 4;
351 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
352 }
353
354 static LLVMValueRef
355 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
356 {
357 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
358 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
359 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
360 uint32_t output_patch0_offset = input_patch_size;
361 unsigned num_patches = ctx->tcs_num_patches;
362
363 output_patch0_offset *= num_patches;
364 output_patch0_offset /= 4;
365 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
366 }
367
368 static LLVMValueRef
369 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
370 {
371 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
372 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
373 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
374 uint32_t output_patch0_offset = input_patch_size;
375
376 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
377 uint32_t output_vertex_size = num_tcs_outputs * 16;
378 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
379 unsigned num_patches = ctx->tcs_num_patches;
380
381 output_patch0_offset *= num_patches;
382 output_patch0_offset += pervertex_output_patch_size;
383 output_patch0_offset /= 4;
384 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
385 }
386
387 static LLVMValueRef
388 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
389 {
390 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
391 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
392
393 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
394 }
395
396 static LLVMValueRef
397 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
398 {
399 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
400 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
401 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
402
403 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
404 patch0_offset);
405 }
406
407 static LLVMValueRef
408 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
409 {
410 LLVMValueRef patch0_patch_data_offset =
411 get_tcs_out_patch0_patch_data_offset(ctx);
412 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
413 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
414
415 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
416 patch0_patch_data_offset);
417 }
418
419 #define MAX_ARGS 64
420 struct arg_info {
421 LLVMTypeRef types[MAX_ARGS];
422 LLVMValueRef *assign[MAX_ARGS];
423 unsigned array_params_mask;
424 uint8_t count;
425 uint8_t sgpr_count;
426 uint8_t num_sgprs_used;
427 uint8_t num_vgprs_used;
428 };
429
430 enum ac_arg_regfile {
431 ARG_SGPR,
432 ARG_VGPR,
433 };
434
435 static void
436 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
437 LLVMValueRef *param_ptr)
438 {
439 assert(info->count < MAX_ARGS);
440
441 info->assign[info->count] = param_ptr;
442 info->types[info->count] = type;
443 info->count++;
444
445 if (regfile == ARG_SGPR) {
446 info->num_sgprs_used += ac_get_type_size(type) / 4;
447 info->sgpr_count++;
448 } else {
449 assert(regfile == ARG_VGPR);
450 info->num_vgprs_used += ac_get_type_size(type) / 4;
451 }
452 }
453
454 static inline void
455 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
456 {
457 info->array_params_mask |= (1 << info->count);
458 add_arg(info, ARG_SGPR, type, param_ptr);
459 }
460
461 static void assign_arguments(LLVMValueRef main_function,
462 struct arg_info *info)
463 {
464 unsigned i;
465 for (i = 0; i < info->count; i++) {
466 if (info->assign[i])
467 *info->assign[i] = LLVMGetParam(main_function, i);
468 }
469 }
470
471 static LLVMValueRef
472 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
473 LLVMBuilderRef builder, LLVMTypeRef *return_types,
474 unsigned num_return_elems,
475 struct arg_info *args,
476 unsigned max_workgroup_size,
477 const struct radv_nir_compiler_options *options)
478 {
479 LLVMTypeRef main_function_type, ret_type;
480 LLVMBasicBlockRef main_function_body;
481
482 if (num_return_elems)
483 ret_type = LLVMStructTypeInContext(ctx, return_types,
484 num_return_elems, true);
485 else
486 ret_type = LLVMVoidTypeInContext(ctx);
487
488 /* Setup the function */
489 main_function_type =
490 LLVMFunctionType(ret_type, args->types, args->count, 0);
491 LLVMValueRef main_function =
492 LLVMAddFunction(module, "main", main_function_type);
493 main_function_body =
494 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
495 LLVMPositionBuilderAtEnd(builder, main_function_body);
496
497 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
498 for (unsigned i = 0; i < args->sgpr_count; ++i) {
499 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
500
501 if (args->array_params_mask & (1 << i)) {
502 LLVMValueRef P = LLVMGetParam(main_function, i);
503 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
504 ac_add_attr_dereferenceable(P, UINT64_MAX);
505 }
506 }
507
508 if (options->address32_hi) {
509 ac_llvm_add_target_dep_function_attr(main_function,
510 "amdgpu-32bit-address-high-bits",
511 options->address32_hi);
512 }
513
514 if (max_workgroup_size) {
515 ac_llvm_add_target_dep_function_attr(main_function,
516 "amdgpu-max-work-group-size",
517 max_workgroup_size);
518 }
519 if (options->unsafe_math) {
520 /* These were copied from some LLVM test. */
521 LLVMAddTargetDependentFunctionAttr(main_function,
522 "less-precise-fpmad",
523 "true");
524 LLVMAddTargetDependentFunctionAttr(main_function,
525 "no-infs-fp-math",
526 "true");
527 LLVMAddTargetDependentFunctionAttr(main_function,
528 "no-nans-fp-math",
529 "true");
530 LLVMAddTargetDependentFunctionAttr(main_function,
531 "unsafe-fp-math",
532 "true");
533 LLVMAddTargetDependentFunctionAttr(main_function,
534 "no-signed-zeros-fp-math",
535 "true");
536 }
537 return main_function;
538 }
539
540
541 static void
542 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
543 uint32_t indirect_offset)
544 {
545 ud_info->sgpr_idx = *sgpr_idx;
546 ud_info->num_sgprs = num_sgprs;
547 ud_info->indirect = indirect_offset > 0;
548 ud_info->indirect_offset = indirect_offset;
549 *sgpr_idx += num_sgprs;
550 }
551
552 static void
553 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
554 uint8_t num_sgprs)
555 {
556 struct radv_userdata_info *ud_info =
557 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
558 assert(ud_info);
559
560 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
561 }
562
563 static void
564 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
565 {
566 bool use_32bit_pointers = HAVE_32BIT_POINTERS &&
567 idx != AC_UD_SCRATCH_RING_OFFSETS;
568
569 set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
570 }
571
572 static void
573 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
574 uint32_t indirect_offset)
575 {
576 struct radv_userdata_locations *locs =
577 &ctx->shader_info->user_sgprs_locs;
578 struct radv_userdata_info *ud_info = &locs->descriptor_sets[idx];
579 assert(ud_info);
580
581 set_loc(ud_info, sgpr_idx, HAVE_32BIT_POINTERS ? 1 : 2, indirect_offset);
582 if (indirect_offset == 0)
583 locs->descriptor_sets_enabled |= 1 << idx;
584 }
585
586 struct user_sgpr_info {
587 bool need_ring_offsets;
588 bool indirect_all_descriptor_sets;
589 };
590
591 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
592 gl_shader_stage stage)
593 {
594 switch (stage) {
595 case MESA_SHADER_VERTEX:
596 if (ctx->shader_info->info.needs_multiview_view_index ||
597 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
598 return true;
599 break;
600 case MESA_SHADER_TESS_EVAL:
601 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
602 return true;
603 break;
604 case MESA_SHADER_GEOMETRY:
605 case MESA_SHADER_TESS_CTRL:
606 if (ctx->shader_info->info.needs_multiview_view_index)
607 return true;
608 break;
609 default:
610 break;
611 }
612 return false;
613 }
614
615 static uint8_t
616 count_vs_user_sgprs(struct radv_shader_context *ctx)
617 {
618 uint8_t count = 0;
619
620 if (ctx->shader_info->info.vs.has_vertex_buffers)
621 count += HAVE_32BIT_POINTERS ? 1 : 2;
622 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
623
624 return count;
625 }
626
627 static void allocate_user_sgprs(struct radv_shader_context *ctx,
628 gl_shader_stage stage,
629 bool has_previous_stage,
630 gl_shader_stage previous_stage,
631 bool needs_view_index,
632 struct user_sgpr_info *user_sgpr_info)
633 {
634 uint8_t user_sgpr_count = 0;
635
636 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
637
638 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
639 if (stage == MESA_SHADER_GEOMETRY ||
640 stage == MESA_SHADER_VERTEX ||
641 stage == MESA_SHADER_TESS_CTRL ||
642 stage == MESA_SHADER_TESS_EVAL ||
643 ctx->is_gs_copy_shader)
644 user_sgpr_info->need_ring_offsets = true;
645
646 if (stage == MESA_SHADER_FRAGMENT &&
647 ctx->shader_info->info.ps.needs_sample_positions)
648 user_sgpr_info->need_ring_offsets = true;
649
650 /* 2 user sgprs will nearly always be allocated for scratch/rings */
651 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
652 user_sgpr_count += 2;
653 }
654
655 switch (stage) {
656 case MESA_SHADER_COMPUTE:
657 if (ctx->shader_info->info.cs.uses_grid_size)
658 user_sgpr_count += 3;
659 break;
660 case MESA_SHADER_FRAGMENT:
661 user_sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
662 break;
663 case MESA_SHADER_VERTEX:
664 if (!ctx->is_gs_copy_shader)
665 user_sgpr_count += count_vs_user_sgprs(ctx);
666 break;
667 case MESA_SHADER_TESS_CTRL:
668 if (has_previous_stage) {
669 if (previous_stage == MESA_SHADER_VERTEX)
670 user_sgpr_count += count_vs_user_sgprs(ctx);
671 }
672 break;
673 case MESA_SHADER_TESS_EVAL:
674 break;
675 case MESA_SHADER_GEOMETRY:
676 if (has_previous_stage) {
677 if (previous_stage == MESA_SHADER_VERTEX) {
678 user_sgpr_count += count_vs_user_sgprs(ctx);
679 }
680 }
681 break;
682 default:
683 break;
684 }
685
686 if (needs_view_index)
687 user_sgpr_count++;
688
689 if (ctx->shader_info->info.loads_push_constants)
690 user_sgpr_count += HAVE_32BIT_POINTERS ? 1 : 2;
691
692 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
693 uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
694 uint32_t num_desc_set =
695 util_bitcount(ctx->shader_info->info.desc_set_used_mask);
696
697 if (remaining_sgprs / (HAVE_32BIT_POINTERS ? 1 : 2) < num_desc_set) {
698 user_sgpr_info->indirect_all_descriptor_sets = true;
699 }
700 }
701
702 static void
703 declare_global_input_sgprs(struct radv_shader_context *ctx,
704 gl_shader_stage stage,
705 bool has_previous_stage,
706 gl_shader_stage previous_stage,
707 const struct user_sgpr_info *user_sgpr_info,
708 struct arg_info *args,
709 LLVMValueRef *desc_sets)
710 {
711 LLVMTypeRef type = ac_array_in_const32_addr_space(ctx->ac.i8);
712 unsigned num_sets = ctx->options->layout ?
713 ctx->options->layout->num_sets : 0;
714 unsigned stage_mask = 1 << stage;
715
716 if (has_previous_stage)
717 stage_mask |= 1 << previous_stage;
718
719 /* 1 for each descriptor set */
720 if (!user_sgpr_info->indirect_all_descriptor_sets) {
721 for (unsigned i = 0; i < num_sets; ++i) {
722 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
723 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
724 add_array_arg(args, type,
725 &ctx->descriptor_sets[i]);
726 }
727 }
728 } else {
729 add_array_arg(args, ac_array_in_const32_addr_space(type), desc_sets);
730 }
731
732 if (ctx->shader_info->info.loads_push_constants) {
733 /* 1 for push constants and dynamic descriptors */
734 add_array_arg(args, type, &ctx->abi.push_constants);
735 }
736 }
737
738 static void
739 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
740 gl_shader_stage stage,
741 bool has_previous_stage,
742 gl_shader_stage previous_stage,
743 struct arg_info *args)
744 {
745 if (!ctx->is_gs_copy_shader &&
746 (stage == MESA_SHADER_VERTEX ||
747 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
748 if (ctx->shader_info->info.vs.has_vertex_buffers) {
749 add_arg(args, ARG_SGPR,
750 ac_array_in_const32_addr_space(ctx->ac.v4i32),
751 &ctx->vertex_buffers);
752 }
753 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
754 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
755 if (ctx->shader_info->info.vs.needs_draw_id) {
756 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
757 }
758 }
759 }
760
761 static void
762 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
763 {
764 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
765 if (!ctx->is_gs_copy_shader) {
766 if (ctx->options->key.vs.as_ls) {
767 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
768 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
769 } else {
770 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
771 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
772 }
773 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
774 }
775 }
776
777 static void
778 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
779 {
780 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
781 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
782 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
783 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
784 }
785
786 static void
787 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
788 bool has_previous_stage, gl_shader_stage previous_stage,
789 const struct user_sgpr_info *user_sgpr_info,
790 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
791 {
792 unsigned num_sets = ctx->options->layout ?
793 ctx->options->layout->num_sets : 0;
794 unsigned stage_mask = 1 << stage;
795
796 if (has_previous_stage)
797 stage_mask |= 1 << previous_stage;
798
799 if (!user_sgpr_info->indirect_all_descriptor_sets) {
800 for (unsigned i = 0; i < num_sets; ++i) {
801 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
802 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
803 set_loc_desc(ctx, i, user_sgpr_idx, 0);
804 } else
805 ctx->descriptor_sets[i] = NULL;
806 }
807 } else {
808 set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
809 user_sgpr_idx);
810
811 for (unsigned i = 0; i < num_sets; ++i) {
812 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
813 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
814 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
815 ctx->descriptor_sets[i] =
816 ac_build_load_to_sgpr(&ctx->ac,
817 desc_sets,
818 LLVMConstInt(ctx->ac.i32, i, false));
819
820 } else
821 ctx->descriptor_sets[i] = NULL;
822 }
823 ctx->shader_info->need_indirect_descriptor_sets = true;
824 }
825
826 if (ctx->shader_info->info.loads_push_constants) {
827 set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
828 }
829 }
830
831 static void
832 set_vs_specific_input_locs(struct radv_shader_context *ctx,
833 gl_shader_stage stage, bool has_previous_stage,
834 gl_shader_stage previous_stage,
835 uint8_t *user_sgpr_idx)
836 {
837 if (!ctx->is_gs_copy_shader &&
838 (stage == MESA_SHADER_VERTEX ||
839 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
840 if (ctx->shader_info->info.vs.has_vertex_buffers) {
841 set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
842 user_sgpr_idx);
843 }
844
845 unsigned vs_num = 2;
846 if (ctx->shader_info->info.vs.needs_draw_id)
847 vs_num++;
848
849 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
850 user_sgpr_idx, vs_num);
851 }
852 }
853
854 static void set_llvm_calling_convention(LLVMValueRef func,
855 gl_shader_stage stage)
856 {
857 enum radeon_llvm_calling_convention calling_conv;
858
859 switch (stage) {
860 case MESA_SHADER_VERTEX:
861 case MESA_SHADER_TESS_EVAL:
862 calling_conv = RADEON_LLVM_AMDGPU_VS;
863 break;
864 case MESA_SHADER_GEOMETRY:
865 calling_conv = RADEON_LLVM_AMDGPU_GS;
866 break;
867 case MESA_SHADER_TESS_CTRL:
868 calling_conv = RADEON_LLVM_AMDGPU_HS;
869 break;
870 case MESA_SHADER_FRAGMENT:
871 calling_conv = RADEON_LLVM_AMDGPU_PS;
872 break;
873 case MESA_SHADER_COMPUTE:
874 calling_conv = RADEON_LLVM_AMDGPU_CS;
875 break;
876 default:
877 unreachable("Unhandle shader type");
878 }
879
880 LLVMSetFunctionCallConv(func, calling_conv);
881 }
882
883 static void create_function(struct radv_shader_context *ctx,
884 gl_shader_stage stage,
885 bool has_previous_stage,
886 gl_shader_stage previous_stage)
887 {
888 uint8_t user_sgpr_idx;
889 struct user_sgpr_info user_sgpr_info;
890 struct arg_info args = {};
891 LLVMValueRef desc_sets;
892 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
893 allocate_user_sgprs(ctx, stage, has_previous_stage,
894 previous_stage, needs_view_index, &user_sgpr_info);
895
896 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
897 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
898 &ctx->ring_offsets);
899 }
900
901 switch (stage) {
902 case MESA_SHADER_COMPUTE:
903 declare_global_input_sgprs(ctx, stage, has_previous_stage,
904 previous_stage, &user_sgpr_info,
905 &args, &desc_sets);
906
907 if (ctx->shader_info->info.cs.uses_grid_size) {
908 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
909 &ctx->abi.num_work_groups);
910 }
911
912 for (int i = 0; i < 3; i++) {
913 ctx->abi.workgroup_ids[i] = NULL;
914 if (ctx->shader_info->info.cs.uses_block_id[i]) {
915 add_arg(&args, ARG_SGPR, ctx->ac.i32,
916 &ctx->abi.workgroup_ids[i]);
917 }
918 }
919
920 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
921 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
922 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
923 &ctx->abi.local_invocation_ids);
924 break;
925 case MESA_SHADER_VERTEX:
926 declare_global_input_sgprs(ctx, stage, has_previous_stage,
927 previous_stage, &user_sgpr_info,
928 &args, &desc_sets);
929 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
930 previous_stage, &args);
931
932 if (needs_view_index)
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->abi.view_index);
935 if (ctx->options->key.vs.as_es)
936 add_arg(&args, ARG_SGPR, ctx->ac.i32,
937 &ctx->es2gs_offset);
938
939 declare_vs_input_vgprs(ctx, &args);
940 break;
941 case MESA_SHADER_TESS_CTRL:
942 if (has_previous_stage) {
943 // First 6 system regs
944 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
945 add_arg(&args, ARG_SGPR, ctx->ac.i32,
946 &ctx->merged_wave_info);
947 add_arg(&args, ARG_SGPR, ctx->ac.i32,
948 &ctx->tess_factor_offset);
949
950 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
951 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
952 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
953
954 declare_global_input_sgprs(ctx, stage,
955 has_previous_stage,
956 previous_stage,
957 &user_sgpr_info, &args,
958 &desc_sets);
959 declare_vs_specific_input_sgprs(ctx, stage,
960 has_previous_stage,
961 previous_stage, &args);
962
963 if (needs_view_index)
964 add_arg(&args, ARG_SGPR, ctx->ac.i32,
965 &ctx->abi.view_index);
966
967 add_arg(&args, ARG_VGPR, ctx->ac.i32,
968 &ctx->abi.tcs_patch_id);
969 add_arg(&args, ARG_VGPR, ctx->ac.i32,
970 &ctx->abi.tcs_rel_ids);
971
972 declare_vs_input_vgprs(ctx, &args);
973 } else {
974 declare_global_input_sgprs(ctx, stage,
975 has_previous_stage,
976 previous_stage,
977 &user_sgpr_info, &args,
978 &desc_sets);
979
980 if (needs_view_index)
981 add_arg(&args, ARG_SGPR, ctx->ac.i32,
982 &ctx->abi.view_index);
983
984 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
985 add_arg(&args, ARG_SGPR, ctx->ac.i32,
986 &ctx->tess_factor_offset);
987 add_arg(&args, ARG_VGPR, ctx->ac.i32,
988 &ctx->abi.tcs_patch_id);
989 add_arg(&args, ARG_VGPR, ctx->ac.i32,
990 &ctx->abi.tcs_rel_ids);
991 }
992 break;
993 case MESA_SHADER_TESS_EVAL:
994 declare_global_input_sgprs(ctx, stage, has_previous_stage,
995 previous_stage, &user_sgpr_info,
996 &args, &desc_sets);
997
998 if (needs_view_index)
999 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1000 &ctx->abi.view_index);
1001
1002 if (ctx->options->key.tes.as_es) {
1003 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1004 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1005 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1006 &ctx->es2gs_offset);
1007 } else {
1008 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1009 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1010 }
1011 declare_tes_input_vgprs(ctx, &args);
1012 break;
1013 case MESA_SHADER_GEOMETRY:
1014 if (has_previous_stage) {
1015 // First 6 system regs
1016 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1017 &ctx->gs2vs_offset);
1018 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1019 &ctx->merged_wave_info);
1020 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1021
1022 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1023 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1024 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1025
1026 declare_global_input_sgprs(ctx, stage,
1027 has_previous_stage,
1028 previous_stage,
1029 &user_sgpr_info, &args,
1030 &desc_sets);
1031
1032 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1033 declare_vs_specific_input_sgprs(ctx, stage,
1034 has_previous_stage,
1035 previous_stage,
1036 &args);
1037 }
1038
1039 if (needs_view_index)
1040 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1041 &ctx->abi.view_index);
1042
1043 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1044 &ctx->gs_vtx_offset[0]);
1045 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1046 &ctx->gs_vtx_offset[2]);
1047 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1048 &ctx->abi.gs_prim_id);
1049 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1050 &ctx->abi.gs_invocation_id);
1051 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1052 &ctx->gs_vtx_offset[4]);
1053
1054 if (previous_stage == MESA_SHADER_VERTEX) {
1055 declare_vs_input_vgprs(ctx, &args);
1056 } else {
1057 declare_tes_input_vgprs(ctx, &args);
1058 }
1059 } else {
1060 declare_global_input_sgprs(ctx, stage,
1061 has_previous_stage,
1062 previous_stage,
1063 &user_sgpr_info, &args,
1064 &desc_sets);
1065
1066 if (needs_view_index)
1067 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1068 &ctx->abi.view_index);
1069
1070 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1071 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1072 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1073 &ctx->gs_vtx_offset[0]);
1074 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1075 &ctx->gs_vtx_offset[1]);
1076 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1077 &ctx->abi.gs_prim_id);
1078 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1079 &ctx->gs_vtx_offset[2]);
1080 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1081 &ctx->gs_vtx_offset[3]);
1082 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1083 &ctx->gs_vtx_offset[4]);
1084 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1085 &ctx->gs_vtx_offset[5]);
1086 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1087 &ctx->abi.gs_invocation_id);
1088 }
1089 break;
1090 case MESA_SHADER_FRAGMENT:
1091 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1092 previous_stage, &user_sgpr_info,
1093 &args, &desc_sets);
1094
1095 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1096 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1097 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1098 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1099 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1100 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1101 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1102 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1103 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1104 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1105 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1106 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1107 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1108 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1109 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1110 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1111 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1112 break;
1113 default:
1114 unreachable("Shader stage not implemented");
1115 }
1116
1117 ctx->main_function = create_llvm_function(
1118 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1119 ctx->max_workgroup_size, ctx->options);
1120 set_llvm_calling_convention(ctx->main_function, stage);
1121
1122
1123 ctx->shader_info->num_input_vgprs = 0;
1124 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1125
1126 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1127
1128 if (ctx->stage != MESA_SHADER_FRAGMENT)
1129 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1130
1131 assign_arguments(ctx->main_function, &args);
1132
1133 user_sgpr_idx = 0;
1134
1135 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1136 set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1137 &user_sgpr_idx);
1138 if (ctx->options->supports_spill) {
1139 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1140 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1141 NULL, 0, AC_FUNC_ATTR_READNONE);
1142 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1143 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1144 }
1145 }
1146
1147 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1148 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1149 if (has_previous_stage)
1150 user_sgpr_idx = 0;
1151
1152 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1153 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1154
1155 switch (stage) {
1156 case MESA_SHADER_COMPUTE:
1157 if (ctx->shader_info->info.cs.uses_grid_size) {
1158 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1159 &user_sgpr_idx, 3);
1160 }
1161 break;
1162 case MESA_SHADER_VERTEX:
1163 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1164 previous_stage, &user_sgpr_idx);
1165 if (ctx->abi.view_index)
1166 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1167 break;
1168 case MESA_SHADER_TESS_CTRL:
1169 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1170 previous_stage, &user_sgpr_idx);
1171 if (ctx->abi.view_index)
1172 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1173 break;
1174 case MESA_SHADER_TESS_EVAL:
1175 if (ctx->abi.view_index)
1176 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1177 break;
1178 case MESA_SHADER_GEOMETRY:
1179 if (has_previous_stage) {
1180 if (previous_stage == MESA_SHADER_VERTEX)
1181 set_vs_specific_input_locs(ctx, stage,
1182 has_previous_stage,
1183 previous_stage,
1184 &user_sgpr_idx);
1185 }
1186 if (ctx->abi.view_index)
1187 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1188 break;
1189 case MESA_SHADER_FRAGMENT:
1190 break;
1191 default:
1192 unreachable("Shader stage not implemented");
1193 }
1194
1195 if (stage == MESA_SHADER_TESS_CTRL ||
1196 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1197 /* GFX9 has the ESGS ring buffer in LDS. */
1198 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1199 ac_declare_lds_as_pointer(&ctx->ac);
1200 }
1201
1202 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1203 }
1204
1205
1206 static LLVMValueRef
1207 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1208 unsigned desc_set, unsigned binding)
1209 {
1210 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1211 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1212 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1213 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1214 unsigned base_offset = layout->binding[binding].offset;
1215 LLVMValueRef offset, stride;
1216
1217 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1218 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1219 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1220 layout->binding[binding].dynamic_offset_offset;
1221 desc_ptr = ctx->abi.push_constants;
1222 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1223 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1224 } else
1225 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1226
1227 offset = ac_build_imad(&ctx->ac, index, stride,
1228 LLVMConstInt(ctx->ac.i32, base_offset, false));
1229
1230 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1231 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1232 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1233
1234 return desc_ptr;
1235 }
1236
1237
1238 /* The offchip buffer layout for TCS->TES is
1239 *
1240 * - attribute 0 of patch 0 vertex 0
1241 * - attribute 0 of patch 0 vertex 1
1242 * - attribute 0 of patch 0 vertex 2
1243 * ...
1244 * - attribute 0 of patch 1 vertex 0
1245 * - attribute 0 of patch 1 vertex 1
1246 * ...
1247 * - attribute 1 of patch 0 vertex 0
1248 * - attribute 1 of patch 0 vertex 1
1249 * ...
1250 * - per patch attribute 0 of patch 0
1251 * - per patch attribute 0 of patch 1
1252 * ...
1253 *
1254 * Note that every attribute has 4 components.
1255 */
1256 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1257 {
1258 uint32_t num_patches = ctx->tcs_num_patches;
1259 uint32_t num_tcs_outputs;
1260 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1261 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1262 else
1263 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1264
1265 uint32_t output_vertex_size = num_tcs_outputs * 16;
1266 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1267
1268 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1269 }
1270
1271 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1272 LLVMValueRef vertex_index)
1273 {
1274 LLVMValueRef param_stride;
1275 if (vertex_index)
1276 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1277 else
1278 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1279 return param_stride;
1280 }
1281
1282 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1283 LLVMValueRef vertex_index,
1284 LLVMValueRef param_index)
1285 {
1286 LLVMValueRef base_addr;
1287 LLVMValueRef param_stride, constant16;
1288 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1289 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1290 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1291 param_stride = calc_param_stride(ctx, vertex_index);
1292 if (vertex_index) {
1293 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
1294 vertices_per_patch, vertex_index);
1295 } else {
1296 base_addr = rel_patch_id;
1297 }
1298
1299 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1300 LLVMBuildMul(ctx->ac.builder, param_index,
1301 param_stride, ""), "");
1302
1303 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1304
1305 if (!vertex_index) {
1306 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1307
1308 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1309 patch_data_offset, "");
1310 }
1311 return base_addr;
1312 }
1313
1314 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1315 unsigned param,
1316 unsigned const_index,
1317 bool is_compact,
1318 LLVMValueRef vertex_index,
1319 LLVMValueRef indir_index)
1320 {
1321 LLVMValueRef param_index;
1322
1323 if (indir_index)
1324 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1325 indir_index, "");
1326 else {
1327 if (const_index && !is_compact)
1328 param += const_index;
1329 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1330 }
1331 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1332 }
1333
1334 static LLVMValueRef
1335 get_dw_address(struct radv_shader_context *ctx,
1336 LLVMValueRef dw_addr,
1337 unsigned param,
1338 unsigned const_index,
1339 bool compact_const_index,
1340 LLVMValueRef vertex_index,
1341 LLVMValueRef stride,
1342 LLVMValueRef indir_index)
1343
1344 {
1345
1346 if (vertex_index) {
1347 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1348 LLVMBuildMul(ctx->ac.builder,
1349 vertex_index,
1350 stride, ""), "");
1351 }
1352
1353 if (indir_index)
1354 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1355 LLVMBuildMul(ctx->ac.builder, indir_index,
1356 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1357 else if (const_index && !compact_const_index)
1358 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1359 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1360
1361 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1362 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1363
1364 if (const_index && compact_const_index)
1365 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1366 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1367 return dw_addr;
1368 }
1369
1370 static LLVMValueRef
1371 load_tcs_varyings(struct ac_shader_abi *abi,
1372 LLVMTypeRef type,
1373 LLVMValueRef vertex_index,
1374 LLVMValueRef indir_index,
1375 unsigned const_index,
1376 unsigned location,
1377 unsigned driver_location,
1378 unsigned component,
1379 unsigned num_components,
1380 bool is_patch,
1381 bool is_compact,
1382 bool load_input)
1383 {
1384 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1385 LLVMValueRef dw_addr, stride;
1386 LLVMValueRef value[4], result;
1387 unsigned param = shader_io_get_unique_index(location);
1388
1389 if (load_input) {
1390 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1391 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1392 dw_addr = get_tcs_in_current_patch_offset(ctx);
1393 } else {
1394 if (!is_patch) {
1395 stride = get_tcs_out_vertex_stride(ctx);
1396 dw_addr = get_tcs_out_current_patch_offset(ctx);
1397 } else {
1398 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1399 stride = NULL;
1400 }
1401 }
1402
1403 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1404 indir_index);
1405
1406 for (unsigned i = 0; i < num_components + component; i++) {
1407 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1408 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1409 ctx->ac.i32_1, "");
1410 }
1411 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1412 return result;
1413 }
1414
1415 static void
1416 store_tcs_output(struct ac_shader_abi *abi,
1417 const nir_variable *var,
1418 LLVMValueRef vertex_index,
1419 LLVMValueRef param_index,
1420 unsigned const_index,
1421 LLVMValueRef src,
1422 unsigned writemask)
1423 {
1424 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1425 const unsigned location = var->data.location;
1426 const unsigned component = var->data.location_frac;
1427 const bool is_patch = var->data.patch;
1428 const bool is_compact = var->data.compact;
1429 LLVMValueRef dw_addr;
1430 LLVMValueRef stride = NULL;
1431 LLVMValueRef buf_addr = NULL;
1432 unsigned param;
1433 bool store_lds = true;
1434
1435 if (is_patch) {
1436 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1437 store_lds = false;
1438 } else {
1439 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1440 store_lds = false;
1441 }
1442
1443 param = shader_io_get_unique_index(location);
1444 if (location == VARYING_SLOT_CLIP_DIST0 &&
1445 is_compact && const_index > 3) {
1446 const_index -= 3;
1447 param++;
1448 }
1449
1450 if (!is_patch) {
1451 stride = get_tcs_out_vertex_stride(ctx);
1452 dw_addr = get_tcs_out_current_patch_offset(ctx);
1453 } else {
1454 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1455 }
1456
1457 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1458 param_index);
1459 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1460 vertex_index, param_index);
1461
1462 bool is_tess_factor = false;
1463 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1464 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1465 is_tess_factor = true;
1466
1467 unsigned base = is_compact ? const_index : 0;
1468 for (unsigned chan = 0; chan < 8; chan++) {
1469 if (!(writemask & (1 << chan)))
1470 continue;
1471 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1472 value = ac_to_integer(&ctx->ac, value);
1473 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
1474
1475 if (store_lds || is_tess_factor) {
1476 LLVMValueRef dw_addr_chan =
1477 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1478 LLVMConstInt(ctx->ac.i32, chan, false), "");
1479 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1480 }
1481
1482 if (!is_tess_factor && writemask != 0xF)
1483 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1484 buf_addr, ctx->oc_lds,
1485 4 * (base + chan), 1, 0, true, false);
1486 }
1487
1488 if (writemask == 0xF) {
1489 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1490 buf_addr, ctx->oc_lds,
1491 (base * 4), 1, 0, true, false);
1492 }
1493 }
1494
1495 static LLVMValueRef
1496 load_tes_input(struct ac_shader_abi *abi,
1497 LLVMTypeRef type,
1498 LLVMValueRef vertex_index,
1499 LLVMValueRef param_index,
1500 unsigned const_index,
1501 unsigned location,
1502 unsigned driver_location,
1503 unsigned component,
1504 unsigned num_components,
1505 bool is_patch,
1506 bool is_compact,
1507 bool load_input)
1508 {
1509 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1510 LLVMValueRef buf_addr;
1511 LLVMValueRef result;
1512 unsigned param = shader_io_get_unique_index(location);
1513
1514 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1515 const_index -= 3;
1516 param++;
1517 }
1518
1519 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1520 is_compact, vertex_index, param_index);
1521
1522 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1523 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1524
1525 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1526 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1527 result = ac_trim_vector(&ctx->ac, result, num_components);
1528 return result;
1529 }
1530
1531 static LLVMValueRef
1532 load_gs_input(struct ac_shader_abi *abi,
1533 unsigned location,
1534 unsigned driver_location,
1535 unsigned component,
1536 unsigned num_components,
1537 unsigned vertex_index,
1538 unsigned const_index,
1539 LLVMTypeRef type)
1540 {
1541 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1542 LLVMValueRef vtx_offset;
1543 unsigned param, vtx_offset_param;
1544 LLVMValueRef value[4], result;
1545
1546 vtx_offset_param = vertex_index;
1547 assert(vtx_offset_param < 6);
1548 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1549 LLVMConstInt(ctx->ac.i32, 4, false), "");
1550
1551 param = shader_io_get_unique_index(location);
1552
1553 for (unsigned i = component; i < num_components + component; i++) {
1554 if (ctx->ac.chip_class >= GFX9) {
1555 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1556 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1557 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1558 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1559 } else {
1560 LLVMValueRef soffset =
1561 LLVMConstInt(ctx->ac.i32,
1562 (param * 4 + i + const_index) * 256,
1563 false);
1564
1565 value[i] = ac_build_buffer_load(&ctx->ac,
1566 ctx->esgs_ring, 1,
1567 ctx->ac.i32_0,
1568 vtx_offset, soffset,
1569 0, 1, 0, true, false);
1570 }
1571
1572 if (ac_get_type_size(type) == 2) {
1573 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
1574 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
1575 }
1576 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
1577 }
1578 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1579 result = ac_to_integer(&ctx->ac, result);
1580 return result;
1581 }
1582
1583
1584 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1585 {
1586 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1587 ac_build_kill_if_false(&ctx->ac, visible);
1588 }
1589
1590 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1591 enum glsl_interp_mode interp, unsigned location)
1592 {
1593 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1594
1595 switch (interp) {
1596 case INTERP_MODE_FLAT:
1597 default:
1598 return NULL;
1599 case INTERP_MODE_SMOOTH:
1600 case INTERP_MODE_NONE:
1601 if (location == INTERP_CENTER)
1602 return ctx->persp_center;
1603 else if (location == INTERP_CENTROID)
1604 return ctx->persp_centroid;
1605 else if (location == INTERP_SAMPLE)
1606 return ctx->persp_sample;
1607 break;
1608 case INTERP_MODE_NOPERSPECTIVE:
1609 if (location == INTERP_CENTER)
1610 return ctx->linear_center;
1611 else if (location == INTERP_CENTROID)
1612 return ctx->linear_centroid;
1613 else if (location == INTERP_SAMPLE)
1614 return ctx->linear_sample;
1615 break;
1616 }
1617 return NULL;
1618 }
1619
1620 static uint32_t
1621 radv_get_sample_pos_offset(uint32_t num_samples)
1622 {
1623 uint32_t sample_pos_offset = 0;
1624
1625 switch (num_samples) {
1626 case 2:
1627 sample_pos_offset = 1;
1628 break;
1629 case 4:
1630 sample_pos_offset = 3;
1631 break;
1632 case 8:
1633 sample_pos_offset = 7;
1634 break;
1635 case 16:
1636 sample_pos_offset = 15;
1637 break;
1638 default:
1639 break;
1640 }
1641 return sample_pos_offset;
1642 }
1643
1644 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1645 LLVMValueRef sample_id)
1646 {
1647 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1648
1649 LLVMValueRef result;
1650 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1651
1652 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1653 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1654
1655 uint32_t sample_pos_offset =
1656 radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
1657
1658 sample_id =
1659 LLVMBuildAdd(ctx->ac.builder, sample_id,
1660 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
1661 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1662
1663 return result;
1664 }
1665
1666
1667 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1668 {
1669 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1670 uint8_t log2_ps_iter_samples;
1671
1672 if (ctx->shader_info->info.ps.force_persample) {
1673 log2_ps_iter_samples =
1674 util_logbase2(ctx->options->key.fs.num_samples);
1675 } else {
1676 log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
1677 }
1678
1679 /* The bit pattern matches that used by fixed function fragment
1680 * processing. */
1681 static const uint16_t ps_iter_masks[] = {
1682 0xffff, /* not used */
1683 0x5555,
1684 0x1111,
1685 0x0101,
1686 0x0001,
1687 };
1688 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1689
1690 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1691
1692 LLVMValueRef result, sample_id;
1693 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1694 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1695 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1696 return result;
1697 }
1698
1699
1700 static void
1701 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1702 {
1703 LLVMValueRef gs_next_vertex;
1704 LLVMValueRef can_emit;
1705 unsigned offset = 0;
1706 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1707
1708 assert(stream == 0);
1709
1710 /* Write vertex attribute values to GSVS ring */
1711 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1712 ctx->gs_next_vertex,
1713 "");
1714
1715 /* If this thread has already emitted the declared maximum number of
1716 * vertices, kill it: excessive vertex emissions are not supposed to
1717 * have any effect, and GS threads have no externally observable
1718 * effects other than emitting vertices.
1719 */
1720 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1721 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1722 ac_build_kill_if_false(&ctx->ac, can_emit);
1723
1724 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1725 unsigned output_usage_mask =
1726 ctx->shader_info->info.gs.output_usage_mask[i];
1727 LLVMValueRef *out_ptr = &addrs[i * 4];
1728 int length = util_last_bit(output_usage_mask);
1729
1730 if (!(ctx->output_mask & (1ull << i)))
1731 continue;
1732
1733 for (unsigned j = 0; j < length; j++) {
1734 if (!(output_usage_mask & (1 << j)))
1735 continue;
1736
1737 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1738 out_ptr[j], "");
1739 LLVMValueRef voffset =
1740 LLVMConstInt(ctx->ac.i32, offset *
1741 ctx->gs_max_out_vertices, false);
1742
1743 offset++;
1744
1745 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1746 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1747
1748 out_val = ac_to_integer(&ctx->ac, out_val);
1749 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1750
1751 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1752 out_val, 1,
1753 voffset, ctx->gs2vs_offset, 0,
1754 1, 1, true, true);
1755 }
1756 }
1757
1758 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1759 ctx->ac.i32_1, "");
1760 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1761
1762 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1763 }
1764
1765 static void
1766 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1767 {
1768 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1769 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1770 }
1771
1772 static LLVMValueRef
1773 load_tess_coord(struct ac_shader_abi *abi)
1774 {
1775 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1776
1777 LLVMValueRef coord[4] = {
1778 ctx->tes_u,
1779 ctx->tes_v,
1780 ctx->ac.f32_0,
1781 ctx->ac.f32_0,
1782 };
1783
1784 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1785 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1786 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1787
1788 return ac_build_gather_values(&ctx->ac, coord, 3);
1789 }
1790
1791 static LLVMValueRef
1792 load_patch_vertices_in(struct ac_shader_abi *abi)
1793 {
1794 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1795 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1796 }
1797
1798
1799 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1800 {
1801 return abi->base_vertex;
1802 }
1803
1804 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1805 LLVMValueRef buffer_ptr, bool write)
1806 {
1807 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1808 LLVMValueRef result;
1809
1810 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1811
1812 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1813 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1814
1815 return result;
1816 }
1817
1818 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1819 {
1820 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1821 LLVMValueRef result;
1822
1823 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1824
1825 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1826 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1827
1828 return result;
1829 }
1830
1831 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1832 unsigned descriptor_set,
1833 unsigned base_index,
1834 unsigned constant_index,
1835 LLVMValueRef index,
1836 enum ac_descriptor_type desc_type,
1837 bool image, bool write,
1838 bool bindless)
1839 {
1840 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1841 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1842 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1843 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1844 unsigned offset = binding->offset;
1845 unsigned stride = binding->size;
1846 unsigned type_size;
1847 LLVMBuilderRef builder = ctx->ac.builder;
1848 LLVMTypeRef type;
1849
1850 assert(base_index < layout->binding_count);
1851
1852 switch (desc_type) {
1853 case AC_DESC_IMAGE:
1854 type = ctx->ac.v8i32;
1855 type_size = 32;
1856 break;
1857 case AC_DESC_FMASK:
1858 type = ctx->ac.v8i32;
1859 offset += 32;
1860 type_size = 32;
1861 break;
1862 case AC_DESC_SAMPLER:
1863 type = ctx->ac.v4i32;
1864 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1865 offset += 64;
1866
1867 type_size = 16;
1868 break;
1869 case AC_DESC_BUFFER:
1870 type = ctx->ac.v4i32;
1871 type_size = 16;
1872 break;
1873 default:
1874 unreachable("invalid desc_type\n");
1875 }
1876
1877 offset += constant_index * stride;
1878
1879 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1880 (!index || binding->immutable_samplers_equal)) {
1881 if (binding->immutable_samplers_equal)
1882 constant_index = 0;
1883
1884 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1885
1886 LLVMValueRef constants[] = {
1887 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1888 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1889 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1890 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1891 };
1892 return ac_build_gather_values(&ctx->ac, constants, 4);
1893 }
1894
1895 assert(stride % type_size == 0);
1896
1897 if (!index)
1898 index = ctx->ac.i32_0;
1899
1900 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1901
1902 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1903 list = LLVMBuildPointerCast(builder, list,
1904 ac_array_in_const32_addr_space(type), "");
1905
1906 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1907 }
1908
1909 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1910 * so we may need to fix it up. */
1911 static LLVMValueRef
1912 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1913 unsigned adjustment,
1914 LLVMValueRef alpha)
1915 {
1916 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1917 return alpha;
1918
1919 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1920
1921 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1922 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1923 else
1924 alpha = ac_to_integer(&ctx->ac, alpha);
1925
1926 /* For the integer-like cases, do a natural sign extension.
1927 *
1928 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1929 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1930 * exponent.
1931 */
1932 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1933 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1934 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1935 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1936
1937 /* Convert back to the right type. */
1938 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1939 LLVMValueRef clamp;
1940 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1941 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1942 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1943 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1944 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1945 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1946 }
1947
1948 return alpha;
1949 }
1950
1951 static void
1952 handle_vs_input_decl(struct radv_shader_context *ctx,
1953 struct nir_variable *variable)
1954 {
1955 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1956 LLVMValueRef t_offset;
1957 LLVMValueRef t_list;
1958 LLVMValueRef input;
1959 LLVMValueRef buffer_index;
1960 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1961 uint8_t input_usage_mask =
1962 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1963 unsigned num_channels = util_last_bit(input_usage_mask);
1964
1965 variable->data.driver_location = variable->data.location * 4;
1966
1967 enum glsl_base_type type = glsl_get_base_type(variable->type);
1968 for (unsigned i = 0; i < attrib_count; ++i) {
1969 LLVMValueRef output[4];
1970 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1971
1972 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1973 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
1974
1975 if (divisor) {
1976 buffer_index = ctx->abi.instance_id;
1977
1978 if (divisor != 1) {
1979 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1980 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1981 }
1982
1983 if (ctx->options->key.vs.as_ls) {
1984 ctx->shader_info->vs.vgpr_comp_cnt =
1985 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1986 } else {
1987 ctx->shader_info->vs.vgpr_comp_cnt =
1988 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1989 }
1990 } else {
1991 buffer_index = ctx->ac.i32_0;
1992 }
1993
1994 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index, "");
1995 } else
1996 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
1997 ctx->abi.base_vertex, "");
1998 t_offset = LLVMConstInt(ctx->ac.i32, attrib_index, false);
1999
2000 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
2001
2002 input = ac_build_buffer_load_format(&ctx->ac, t_list,
2003 buffer_index,
2004 ctx->ac.i32_0,
2005 num_channels, false, true);
2006
2007 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
2008
2009 for (unsigned chan = 0; chan < 4; chan++) {
2010 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2011 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
2012 if (type == GLSL_TYPE_FLOAT16) {
2013 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
2014 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
2015 }
2016 }
2017
2018 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
2019 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
2020
2021 for (unsigned chan = 0; chan < 4; chan++) {
2022 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
2023 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
2024 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
2025
2026 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
2027 }
2028 }
2029 }
2030
2031 static void interp_fs_input(struct radv_shader_context *ctx,
2032 unsigned attr,
2033 LLVMValueRef interp_param,
2034 LLVMValueRef prim_mask,
2035 LLVMValueRef result[4])
2036 {
2037 LLVMValueRef attr_number;
2038 unsigned chan;
2039 LLVMValueRef i, j;
2040 bool interp = !LLVMIsUndef(interp_param);
2041
2042 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
2043
2044 /* fs.constant returns the param from the middle vertex, so it's not
2045 * really useful for flat shading. It's meant to be used for custom
2046 * interpolation (but the intrinsic can't fetch from the other two
2047 * vertices).
2048 *
2049 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2050 * to do the right thing. The only reason we use fs.constant is that
2051 * fs.interp cannot be used on integers, because they can be equal
2052 * to NaN.
2053 */
2054 if (interp) {
2055 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
2056 ctx->ac.v2f32, "");
2057
2058 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2059 ctx->ac.i32_0, "");
2060 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2061 ctx->ac.i32_1, "");
2062 }
2063
2064 for (chan = 0; chan < 4; chan++) {
2065 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2066
2067 if (interp) {
2068 result[chan] = ac_build_fs_interp(&ctx->ac,
2069 llvm_chan,
2070 attr_number,
2071 prim_mask, i, j);
2072 } else {
2073 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2074 LLVMConstInt(ctx->ac.i32, 2, false),
2075 llvm_chan,
2076 attr_number,
2077 prim_mask);
2078 result[chan] = LLVMBuildBitCast(ctx->ac.builder, result[chan], ctx->ac.i32, "");
2079 result[chan] = LLVMBuildTruncOrBitCast(ctx->ac.builder, result[chan], LLVMTypeOf(interp_param), "");
2080 }
2081 }
2082 }
2083
2084 static void
2085 handle_fs_input_decl(struct radv_shader_context *ctx,
2086 struct nir_variable *variable)
2087 {
2088 int idx = variable->data.location;
2089 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2090 LLVMValueRef interp = NULL;
2091 uint64_t mask;
2092
2093 variable->data.driver_location = idx * 4;
2094 mask = ((1ull << attrib_count) - 1) << variable->data.location;
2095
2096 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
2097 unsigned interp_type;
2098 if (variable->data.sample)
2099 interp_type = INTERP_SAMPLE;
2100 else if (variable->data.centroid)
2101 interp_type = INTERP_CENTROID;
2102 else
2103 interp_type = INTERP_CENTER;
2104
2105 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
2106 }
2107 bool is_16bit = glsl_type_is_16bit(variable->type);
2108 LLVMTypeRef type = is_16bit ? ctx->ac.i16 : ctx->ac.i32;
2109 if (interp == NULL)
2110 interp = LLVMGetUndef(type);
2111
2112 for (unsigned i = 0; i < attrib_count; ++i)
2113 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
2114
2115 if (idx == VARYING_SLOT_CLIP_DIST0) {
2116 /* Do not account for the number of components inside the array
2117 * of clip/cull distances because this might wrongly set other
2118 * bits like primitive ID or layer.
2119 */
2120 mask = 1ull << VARYING_SLOT_CLIP_DIST0;
2121 }
2122
2123 ctx->input_mask |= mask;
2124 }
2125
2126 static void
2127 handle_vs_inputs(struct radv_shader_context *ctx,
2128 struct nir_shader *nir) {
2129 nir_foreach_variable(variable, &nir->inputs)
2130 handle_vs_input_decl(ctx, variable);
2131 }
2132
2133 static void
2134 prepare_interp_optimize(struct radv_shader_context *ctx,
2135 struct nir_shader *nir)
2136 {
2137 bool uses_center = false;
2138 bool uses_centroid = false;
2139 nir_foreach_variable(variable, &nir->inputs) {
2140 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2141 variable->data.sample)
2142 continue;
2143
2144 if (variable->data.centroid)
2145 uses_centroid = true;
2146 else
2147 uses_center = true;
2148 }
2149
2150 if (uses_center && uses_centroid) {
2151 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2152 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
2153 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
2154 }
2155 }
2156
2157 static void
2158 handle_fs_inputs(struct radv_shader_context *ctx,
2159 struct nir_shader *nir)
2160 {
2161 prepare_interp_optimize(ctx, nir);
2162
2163 nir_foreach_variable(variable, &nir->inputs)
2164 handle_fs_input_decl(ctx, variable);
2165
2166 unsigned index = 0;
2167
2168 if (ctx->shader_info->info.ps.uses_input_attachments ||
2169 ctx->shader_info->info.needs_multiview_view_index) {
2170 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
2171 ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)] = LLVMGetUndef(ctx->ac.i32);
2172 }
2173
2174 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
2175 LLVMValueRef interp_param;
2176 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
2177
2178 if (!(ctx->input_mask & (1ull << i)))
2179 continue;
2180
2181 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
2182 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
2183 interp_param = *inputs;
2184 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
2185 inputs);
2186
2187 if (LLVMIsUndef(interp_param))
2188 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
2189 ++index;
2190 } else if (i == VARYING_SLOT_CLIP_DIST0) {
2191 int length = ctx->shader_info->info.ps.num_input_clips_culls;
2192
2193 for (unsigned j = 0; j < length; j += 4) {
2194 inputs = ctx->inputs + ac_llvm_reg_index_soa(i, j);
2195
2196 interp_param = *inputs;
2197 interp_fs_input(ctx, index, interp_param,
2198 ctx->abi.prim_mask, inputs);
2199 ++index;
2200 }
2201 } else if (i == VARYING_SLOT_POS) {
2202 for(int i = 0; i < 3; ++i)
2203 inputs[i] = ctx->abi.frag_pos[i];
2204
2205 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2206 ctx->abi.frag_pos[3]);
2207 }
2208 }
2209 ctx->shader_info->fs.num_interp = index;
2210 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
2211
2212 if (ctx->shader_info->info.needs_multiview_view_index)
2213 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2214 }
2215
2216 static void
2217 scan_shader_output_decl(struct radv_shader_context *ctx,
2218 struct nir_variable *variable,
2219 struct nir_shader *shader,
2220 gl_shader_stage stage)
2221 {
2222 int idx = variable->data.location + variable->data.index;
2223 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2224 uint64_t mask_attribs;
2225
2226 variable->data.driver_location = idx * 4;
2227
2228 /* tess ctrl has it's own load/store paths for outputs */
2229 if (stage == MESA_SHADER_TESS_CTRL)
2230 return;
2231
2232 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2233 if (stage == MESA_SHADER_VERTEX ||
2234 stage == MESA_SHADER_TESS_EVAL ||
2235 stage == MESA_SHADER_GEOMETRY) {
2236 if (idx == VARYING_SLOT_CLIP_DIST0) {
2237 if (stage == MESA_SHADER_VERTEX) {
2238 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2239 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2240 ctx->shader_info->vs.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
2241 }
2242 if (stage == MESA_SHADER_TESS_EVAL) {
2243 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2244 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2245 ctx->shader_info->tes.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
2246 }
2247
2248 mask_attribs = 1ull << idx;
2249 }
2250 }
2251
2252 ctx->output_mask |= mask_attribs;
2253 }
2254
2255
2256 /* Initialize arguments for the shader export intrinsic */
2257 static void
2258 si_llvm_init_export_args(struct radv_shader_context *ctx,
2259 LLVMValueRef *values,
2260 unsigned enabled_channels,
2261 unsigned target,
2262 struct ac_export_args *args)
2263 {
2264 /* Specify the channels that are enabled. */
2265 args->enabled_channels = enabled_channels;
2266
2267 /* Specify whether the EXEC mask represents the valid mask */
2268 args->valid_mask = 0;
2269
2270 /* Specify whether this is the last export */
2271 args->done = 0;
2272
2273 /* Specify the target we are exporting */
2274 args->target = target;
2275
2276 args->compr = false;
2277 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2278 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2279 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2280 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2281
2282 if (!values)
2283 return;
2284
2285 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
2286 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2287 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2288 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2289 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2290 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2291 unsigned chan;
2292
2293 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2294 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2295 unsigned bits, bool hi) = NULL;
2296
2297 switch(col_format) {
2298 case V_028714_SPI_SHADER_ZERO:
2299 args->enabled_channels = 0; /* writemask */
2300 args->target = V_008DFC_SQ_EXP_NULL;
2301 break;
2302
2303 case V_028714_SPI_SHADER_32_R:
2304 args->enabled_channels = 1;
2305 args->out[0] = values[0];
2306 break;
2307
2308 case V_028714_SPI_SHADER_32_GR:
2309 args->enabled_channels = 0x3;
2310 args->out[0] = values[0];
2311 args->out[1] = values[1];
2312 break;
2313
2314 case V_028714_SPI_SHADER_32_AR:
2315 args->enabled_channels = 0x9;
2316 args->out[0] = values[0];
2317 args->out[3] = values[3];
2318 break;
2319
2320 case V_028714_SPI_SHADER_FP16_ABGR:
2321 args->enabled_channels = 0x5;
2322 packf = ac_build_cvt_pkrtz_f16;
2323 if (is_16bit) {
2324 for (unsigned chan = 0; chan < 4; chan++)
2325 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
2326 values[chan],
2327 ctx->ac.f32, "");
2328 }
2329 break;
2330
2331 case V_028714_SPI_SHADER_UNORM16_ABGR:
2332 args->enabled_channels = 0x5;
2333 packf = ac_build_cvt_pknorm_u16;
2334 break;
2335
2336 case V_028714_SPI_SHADER_SNORM16_ABGR:
2337 args->enabled_channels = 0x5;
2338 packf = ac_build_cvt_pknorm_i16;
2339 break;
2340
2341 case V_028714_SPI_SHADER_UINT16_ABGR:
2342 args->enabled_channels = 0x5;
2343 packi = ac_build_cvt_pk_u16;
2344 if (is_16bit) {
2345 for (unsigned chan = 0; chan < 4; chan++)
2346 values[chan] = LLVMBuildZExt(ctx->ac.builder,
2347 values[chan],
2348 ctx->ac.i32, "");
2349 }
2350 break;
2351
2352 case V_028714_SPI_SHADER_SINT16_ABGR:
2353 args->enabled_channels = 0x5;
2354 packi = ac_build_cvt_pk_i16;
2355 if (is_16bit) {
2356 for (unsigned chan = 0; chan < 4; chan++)
2357 values[chan] = LLVMBuildSExt(ctx->ac.builder,
2358 values[chan],
2359 ctx->ac.i32, "");
2360 }
2361 break;
2362
2363 default:
2364 case V_028714_SPI_SHADER_32_ABGR:
2365 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2366 break;
2367 }
2368
2369 /* Pack f16 or norm_i16/u16. */
2370 if (packf) {
2371 for (chan = 0; chan < 2; chan++) {
2372 LLVMValueRef pack_args[2] = {
2373 values[2 * chan],
2374 values[2 * chan + 1]
2375 };
2376 LLVMValueRef packed;
2377
2378 packed = packf(&ctx->ac, pack_args);
2379 args->out[chan] = ac_to_float(&ctx->ac, packed);
2380 }
2381 args->compr = 1; /* COMPR flag */
2382 }
2383
2384 /* Pack i16/u16. */
2385 if (packi) {
2386 for (chan = 0; chan < 2; chan++) {
2387 LLVMValueRef pack_args[2] = {
2388 ac_to_integer(&ctx->ac, values[2 * chan]),
2389 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2390 };
2391 LLVMValueRef packed;
2392
2393 packed = packi(&ctx->ac, pack_args,
2394 is_int8 ? 8 : is_int10 ? 10 : 16,
2395 chan == 1);
2396 args->out[chan] = ac_to_float(&ctx->ac, packed);
2397 }
2398 args->compr = 1; /* COMPR flag */
2399 }
2400 return;
2401 }
2402
2403 if (is_16bit) {
2404 for (unsigned chan = 0; chan < 4; chan++) {
2405 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
2406 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
2407 }
2408 } else
2409 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2410
2411 for (unsigned i = 0; i < 4; ++i) {
2412 if (!(args->enabled_channels & (1 << i)))
2413 continue;
2414
2415 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2416 }
2417 }
2418
2419 static void
2420 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2421 LLVMValueRef *values, unsigned enabled_channels)
2422 {
2423 struct ac_export_args args;
2424
2425 si_llvm_init_export_args(ctx, values, enabled_channels,
2426 V_008DFC_SQ_EXP_PARAM + index, &args);
2427 ac_build_export(&ctx->ac, &args);
2428 }
2429
2430 static LLVMValueRef
2431 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2432 {
2433 LLVMValueRef output =
2434 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2435
2436 return LLVMBuildLoad(ctx->ac.builder, output, "");
2437 }
2438
2439 static void
2440 handle_vs_outputs_post(struct radv_shader_context *ctx,
2441 bool export_prim_id, bool export_layer_id,
2442 struct radv_vs_output_info *outinfo)
2443 {
2444 uint32_t param_count = 0;
2445 unsigned target;
2446 unsigned pos_idx, num_pos_exports = 0;
2447 struct ac_export_args args, pos_args[4] = {};
2448 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2449 int i;
2450
2451 if (ctx->options->key.has_multiview_view_index) {
2452 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2453 if(!*tmp_out) {
2454 for(unsigned i = 0; i < 4; ++i)
2455 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2456 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2457 }
2458
2459 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2460 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2461 }
2462
2463 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2464 sizeof(outinfo->vs_output_param_offset));
2465
2466 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2467 unsigned output_usage_mask, length;
2468 LLVMValueRef slots[8];
2469 unsigned j;
2470
2471 if (ctx->stage == MESA_SHADER_VERTEX &&
2472 !ctx->is_gs_copy_shader) {
2473 output_usage_mask =
2474 ctx->shader_info->info.vs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2475 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2476 output_usage_mask =
2477 ctx->shader_info->info.tes.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2478 } else {
2479 assert(ctx->is_gs_copy_shader);
2480 output_usage_mask =
2481 ctx->shader_info->info.gs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2482 }
2483
2484 length = util_last_bit(output_usage_mask);
2485
2486 i = VARYING_SLOT_CLIP_DIST0;
2487 for (j = 0; j < length; j++)
2488 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2489
2490 for (i = length; i < 8; i++)
2491 slots[i] = LLVMGetUndef(ctx->ac.f32);
2492
2493 if (length > 4) {
2494 target = V_008DFC_SQ_EXP_POS + 3;
2495 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2496 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2497 &args, sizeof(args));
2498 }
2499
2500 target = V_008DFC_SQ_EXP_POS + 2;
2501 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2502 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2503 &args, sizeof(args));
2504
2505 /* Export the clip/cull distances values to the next stage. */
2506 radv_export_param(ctx, param_count, &slots[0], 0xf);
2507 outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0] = param_count++;
2508 if (length > 4) {
2509 radv_export_param(ctx, param_count, &slots[4], 0xf);
2510 outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1] = param_count++;
2511 }
2512 }
2513
2514 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2515 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2516 for (unsigned j = 0; j < 4; j++)
2517 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2518 }
2519 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2520
2521 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2522 outinfo->writes_pointsize = true;
2523 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2524 }
2525
2526 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2527 outinfo->writes_layer = true;
2528 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2529 }
2530
2531 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2532 outinfo->writes_viewport_index = true;
2533 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2534 }
2535
2536 if (outinfo->writes_pointsize ||
2537 outinfo->writes_layer ||
2538 outinfo->writes_viewport_index) {
2539 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2540 (outinfo->writes_layer == true ? 4 : 0));
2541 pos_args[1].valid_mask = 0;
2542 pos_args[1].done = 0;
2543 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2544 pos_args[1].compr = 0;
2545 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2546 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2547 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2548 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2549
2550 if (outinfo->writes_pointsize == true)
2551 pos_args[1].out[0] = psize_value;
2552 if (outinfo->writes_layer == true)
2553 pos_args[1].out[2] = layer_value;
2554 if (outinfo->writes_viewport_index == true) {
2555 if (ctx->options->chip_class >= GFX9) {
2556 /* GFX9 has the layer in out.z[10:0] and the viewport
2557 * index in out.z[19:16].
2558 */
2559 LLVMValueRef v = viewport_index_value;
2560 v = ac_to_integer(&ctx->ac, v);
2561 v = LLVMBuildShl(ctx->ac.builder, v,
2562 LLVMConstInt(ctx->ac.i32, 16, false),
2563 "");
2564 v = LLVMBuildOr(ctx->ac.builder, v,
2565 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2566
2567 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2568 pos_args[1].enabled_channels |= 1 << 2;
2569 } else {
2570 pos_args[1].out[3] = viewport_index_value;
2571 pos_args[1].enabled_channels |= 1 << 3;
2572 }
2573 }
2574 }
2575 for (i = 0; i < 4; i++) {
2576 if (pos_args[i].out[0])
2577 num_pos_exports++;
2578 }
2579
2580 pos_idx = 0;
2581 for (i = 0; i < 4; i++) {
2582 if (!pos_args[i].out[0])
2583 continue;
2584
2585 /* Specify the target we are exporting */
2586 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2587 if (pos_idx == num_pos_exports)
2588 pos_args[i].done = 1;
2589 ac_build_export(&ctx->ac, &pos_args[i]);
2590 }
2591
2592 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2593 LLVMValueRef values[4];
2594 if (!(ctx->output_mask & (1ull << i)))
2595 continue;
2596
2597 if (i != VARYING_SLOT_LAYER &&
2598 i != VARYING_SLOT_PRIMITIVE_ID &&
2599 i < VARYING_SLOT_VAR0)
2600 continue;
2601
2602 for (unsigned j = 0; j < 4; j++)
2603 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2604
2605 unsigned output_usage_mask;
2606
2607 if (ctx->stage == MESA_SHADER_VERTEX &&
2608 !ctx->is_gs_copy_shader) {
2609 output_usage_mask =
2610 ctx->shader_info->info.vs.output_usage_mask[i];
2611 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2612 output_usage_mask =
2613 ctx->shader_info->info.tes.output_usage_mask[i];
2614 } else {
2615 assert(ctx->is_gs_copy_shader);
2616 output_usage_mask =
2617 ctx->shader_info->info.gs.output_usage_mask[i];
2618 }
2619
2620 radv_export_param(ctx, param_count, values, output_usage_mask);
2621
2622 outinfo->vs_output_param_offset[i] = param_count++;
2623 }
2624
2625 if (export_prim_id) {
2626 LLVMValueRef values[4];
2627
2628 values[0] = ctx->vs_prim_id;
2629 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2630 ctx->shader_info->vs.vgpr_comp_cnt);
2631 for (unsigned j = 1; j < 4; j++)
2632 values[j] = ctx->ac.f32_0;
2633
2634 radv_export_param(ctx, param_count, values, 0x1);
2635
2636 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2637 outinfo->export_prim_id = true;
2638 }
2639
2640 if (export_layer_id && layer_value) {
2641 LLVMValueRef values[4];
2642
2643 values[0] = layer_value;
2644 for (unsigned j = 1; j < 4; j++)
2645 values[j] = ctx->ac.f32_0;
2646
2647 radv_export_param(ctx, param_count, values, 0x1);
2648
2649 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2650 }
2651
2652 outinfo->pos_exports = num_pos_exports;
2653 outinfo->param_exports = param_count;
2654 }
2655
2656 static void
2657 handle_es_outputs_post(struct radv_shader_context *ctx,
2658 struct radv_es_output_info *outinfo)
2659 {
2660 int j;
2661 uint64_t max_output_written = 0;
2662 LLVMValueRef lds_base = NULL;
2663
2664 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2665 unsigned output_usage_mask;
2666 int param_index;
2667 int length = 4;
2668
2669 if (!(ctx->output_mask & (1ull << i)))
2670 continue;
2671
2672 if (ctx->stage == MESA_SHADER_VERTEX) {
2673 output_usage_mask =
2674 ctx->shader_info->info.vs.output_usage_mask[i];
2675 } else {
2676 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2677 output_usage_mask =
2678 ctx->shader_info->info.tes.output_usage_mask[i];
2679 }
2680
2681 if (i == VARYING_SLOT_CLIP_DIST0)
2682 length = util_last_bit(output_usage_mask);
2683
2684 param_index = shader_io_get_unique_index(i);
2685
2686 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2687 }
2688
2689 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2690
2691 if (ctx->ac.chip_class >= GFX9) {
2692 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2693 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2694 LLVMValueRef wave_idx = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
2695 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2696 LLVMBuildMul(ctx->ac.builder, wave_idx,
2697 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2698 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2699 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2700 }
2701
2702 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2703 LLVMValueRef dw_addr = NULL;
2704 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2705 unsigned output_usage_mask;
2706 int param_index;
2707 int length = 4;
2708
2709 if (!(ctx->output_mask & (1ull << i)))
2710 continue;
2711
2712 if (ctx->stage == MESA_SHADER_VERTEX) {
2713 output_usage_mask =
2714 ctx->shader_info->info.vs.output_usage_mask[i];
2715 } else {
2716 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2717 output_usage_mask =
2718 ctx->shader_info->info.tes.output_usage_mask[i];
2719 }
2720
2721 if (i == VARYING_SLOT_CLIP_DIST0)
2722 length = util_last_bit(output_usage_mask);
2723
2724 param_index = shader_io_get_unique_index(i);
2725
2726 if (lds_base) {
2727 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2728 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2729 "");
2730 }
2731
2732 for (j = 0; j < length; j++) {
2733 if (!(output_usage_mask & (1 << j)))
2734 continue;
2735
2736 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2737 out_val = ac_to_integer(&ctx->ac, out_val);
2738 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2739
2740 if (ctx->ac.chip_class >= GFX9) {
2741 LLVMValueRef dw_addr_offset =
2742 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2743 LLVMConstInt(ctx->ac.i32,
2744 j, false), "");
2745
2746 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2747 } else {
2748 ac_build_buffer_store_dword(&ctx->ac,
2749 ctx->esgs_ring,
2750 out_val, 1,
2751 NULL, ctx->es2gs_offset,
2752 (4 * param_index + j) * 4,
2753 1, 1, true, true);
2754 }
2755 }
2756 }
2757 }
2758
2759 static void
2760 handle_ls_outputs_post(struct radv_shader_context *ctx)
2761 {
2762 LLVMValueRef vertex_id = ctx->rel_auto_id;
2763 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2764 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2765 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2766 vertex_dw_stride, "");
2767
2768 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2769 unsigned output_usage_mask =
2770 ctx->shader_info->info.vs.output_usage_mask[i];
2771 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2772 int length = 4;
2773
2774 if (!(ctx->output_mask & (1ull << i)))
2775 continue;
2776
2777 if (i == VARYING_SLOT_CLIP_DIST0)
2778 length = util_last_bit(output_usage_mask);
2779
2780 int param = shader_io_get_unique_index(i);
2781 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2782 LLVMConstInt(ctx->ac.i32, param * 4, false),
2783 "");
2784 for (unsigned j = 0; j < length; j++) {
2785 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2786 value = ac_to_integer(&ctx->ac, value);
2787 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2788 ac_lds_store(&ctx->ac, dw_addr, value);
2789 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2790 }
2791 }
2792 }
2793
2794 static void
2795 write_tess_factors(struct radv_shader_context *ctx)
2796 {
2797 unsigned stride, outer_comps, inner_comps;
2798 struct ac_build_if_state if_ctx, inner_if_ctx;
2799 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2800 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2801 unsigned tess_inner_index = 0, tess_outer_index;
2802 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2803 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2804 int i;
2805 ac_emit_barrier(&ctx->ac, ctx->stage);
2806
2807 switch (ctx->options->key.tcs.primitive_mode) {
2808 case GL_ISOLINES:
2809 stride = 2;
2810 outer_comps = 2;
2811 inner_comps = 0;
2812 break;
2813 case GL_TRIANGLES:
2814 stride = 4;
2815 outer_comps = 3;
2816 inner_comps = 1;
2817 break;
2818 case GL_QUADS:
2819 stride = 6;
2820 outer_comps = 4;
2821 inner_comps = 2;
2822 break;
2823 default:
2824 return;
2825 }
2826
2827 ac_nir_build_if(&if_ctx, ctx,
2828 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2829 invocation_id, ctx->ac.i32_0, ""));
2830
2831 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2832
2833 if (inner_comps) {
2834 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2835 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2836 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2837 }
2838
2839 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2840 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2841 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2842
2843 for (i = 0; i < 4; i++) {
2844 inner[i] = LLVMGetUndef(ctx->ac.i32);
2845 outer[i] = LLVMGetUndef(ctx->ac.i32);
2846 }
2847
2848 // LINES reversal
2849 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2850 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2851 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2852 ctx->ac.i32_1, "");
2853 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2854 } else {
2855 for (i = 0; i < outer_comps; i++) {
2856 outer[i] = out[i] =
2857 ac_lds_load(&ctx->ac, lds_outer);
2858 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2859 ctx->ac.i32_1, "");
2860 }
2861 for (i = 0; i < inner_comps; i++) {
2862 inner[i] = out[outer_comps+i] =
2863 ac_lds_load(&ctx->ac, lds_inner);
2864 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2865 ctx->ac.i32_1, "");
2866 }
2867 }
2868
2869 /* Convert the outputs to vectors for stores. */
2870 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2871 vec1 = NULL;
2872
2873 if (stride > 4)
2874 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2875
2876
2877 buffer = ctx->hs_ring_tess_factor;
2878 tf_base = ctx->tess_factor_offset;
2879 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2880 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2881 unsigned tf_offset = 0;
2882
2883 if (ctx->options->chip_class <= VI) {
2884 ac_nir_build_if(&inner_if_ctx, ctx,
2885 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2886 rel_patch_id, ctx->ac.i32_0, ""));
2887
2888 /* Store the dynamic HS control word. */
2889 ac_build_buffer_store_dword(&ctx->ac, buffer,
2890 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2891 1, ctx->ac.i32_0, tf_base,
2892 0, 1, 0, true, false);
2893 tf_offset += 4;
2894
2895 ac_nir_build_endif(&inner_if_ctx);
2896 }
2897
2898 /* Store the tessellation factors. */
2899 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2900 MIN2(stride, 4), byteoffset, tf_base,
2901 tf_offset, 1, 0, true, false);
2902 if (vec1)
2903 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2904 stride - 4, byteoffset, tf_base,
2905 16 + tf_offset, 1, 0, true, false);
2906
2907 //store to offchip for TES to read - only if TES reads them
2908 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2909 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2910 LLVMValueRef tf_inner_offset;
2911 unsigned param_outer, param_inner;
2912
2913 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2914 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2915 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2916
2917 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2918 util_next_power_of_two(outer_comps));
2919
2920 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2921 outer_comps, tf_outer_offset,
2922 ctx->oc_lds, 0, 1, 0, true, false);
2923 if (inner_comps) {
2924 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2925 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2926 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2927
2928 inner_vec = inner_comps == 1 ? inner[0] :
2929 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2930 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2931 inner_comps, tf_inner_offset,
2932 ctx->oc_lds, 0, 1, 0, true, false);
2933 }
2934 }
2935 ac_nir_build_endif(&if_ctx);
2936 }
2937
2938 static void
2939 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2940 {
2941 write_tess_factors(ctx);
2942 }
2943
2944 static bool
2945 si_export_mrt_color(struct radv_shader_context *ctx,
2946 LLVMValueRef *color, unsigned index,
2947 struct ac_export_args *args)
2948 {
2949 /* Export */
2950 si_llvm_init_export_args(ctx, color, 0xf,
2951 V_008DFC_SQ_EXP_MRT + index, args);
2952 if (!args->enabled_channels)
2953 return false; /* unnecessary NULL export */
2954
2955 return true;
2956 }
2957
2958 static void
2959 radv_export_mrt_z(struct radv_shader_context *ctx,
2960 LLVMValueRef depth, LLVMValueRef stencil,
2961 LLVMValueRef samplemask)
2962 {
2963 struct ac_export_args args;
2964
2965 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2966
2967 ac_build_export(&ctx->ac, &args);
2968 }
2969
2970 static void
2971 handle_fs_outputs_post(struct radv_shader_context *ctx)
2972 {
2973 unsigned index = 0;
2974 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2975 struct ac_export_args color_args[8];
2976
2977 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2978 LLVMValueRef values[4];
2979
2980 if (!(ctx->output_mask & (1ull << i)))
2981 continue;
2982
2983 if (i < FRAG_RESULT_DATA0)
2984 continue;
2985
2986 for (unsigned j = 0; j < 4; j++)
2987 values[j] = ac_to_float(&ctx->ac,
2988 radv_load_output(ctx, i, j));
2989
2990 bool ret = si_export_mrt_color(ctx, values,
2991 i - FRAG_RESULT_DATA0,
2992 &color_args[index]);
2993 if (ret)
2994 index++;
2995 }
2996
2997 /* Process depth, stencil, samplemask. */
2998 if (ctx->shader_info->info.ps.writes_z) {
2999 depth = ac_to_float(&ctx->ac,
3000 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3001 }
3002 if (ctx->shader_info->info.ps.writes_stencil) {
3003 stencil = ac_to_float(&ctx->ac,
3004 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3005 }
3006 if (ctx->shader_info->info.ps.writes_sample_mask) {
3007 samplemask = ac_to_float(&ctx->ac,
3008 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3009 }
3010
3011 /* Set the DONE bit on last non-null color export only if Z isn't
3012 * exported.
3013 */
3014 if (index > 0 &&
3015 !ctx->shader_info->info.ps.writes_z &&
3016 !ctx->shader_info->info.ps.writes_stencil &&
3017 !ctx->shader_info->info.ps.writes_sample_mask) {
3018 unsigned last = index - 1;
3019
3020 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3021 color_args[last].done = 1; /* DONE bit */
3022 }
3023
3024 /* Export PS outputs. */
3025 for (unsigned i = 0; i < index; i++)
3026 ac_build_export(&ctx->ac, &color_args[i]);
3027
3028 if (depth || stencil || samplemask)
3029 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3030 else if (!index)
3031 ac_build_export_null(&ctx->ac);
3032 }
3033
3034 static void
3035 emit_gs_epilogue(struct radv_shader_context *ctx)
3036 {
3037 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3038 }
3039
3040 static void
3041 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3042 LLVMValueRef *addrs)
3043 {
3044 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3045
3046 switch (ctx->stage) {
3047 case MESA_SHADER_VERTEX:
3048 if (ctx->options->key.vs.as_ls)
3049 handle_ls_outputs_post(ctx);
3050 else if (ctx->options->key.vs.as_es)
3051 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
3052 else
3053 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
3054 ctx->options->key.vs.export_layer_id,
3055 &ctx->shader_info->vs.outinfo);
3056 break;
3057 case MESA_SHADER_FRAGMENT:
3058 handle_fs_outputs_post(ctx);
3059 break;
3060 case MESA_SHADER_GEOMETRY:
3061 emit_gs_epilogue(ctx);
3062 break;
3063 case MESA_SHADER_TESS_CTRL:
3064 handle_tcs_outputs_post(ctx);
3065 break;
3066 case MESA_SHADER_TESS_EVAL:
3067 if (ctx->options->key.tes.as_es)
3068 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
3069 else
3070 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
3071 ctx->options->key.tes.export_layer_id,
3072 &ctx->shader_info->tes.outinfo);
3073 break;
3074 default:
3075 break;
3076 }
3077 }
3078
3079 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3080 LLVMPassManagerRef passmgr,
3081 const struct radv_nir_compiler_options *options)
3082 {
3083 LLVMRunPassManager(passmgr, ctx->ac.module);
3084 LLVMDisposeBuilder(ctx->ac.builder);
3085
3086 ac_llvm_context_dispose(&ctx->ac);
3087 }
3088
3089 static void
3090 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3091 {
3092 struct radv_vs_output_info *outinfo;
3093
3094 switch (ctx->stage) {
3095 case MESA_SHADER_FRAGMENT:
3096 case MESA_SHADER_COMPUTE:
3097 case MESA_SHADER_TESS_CTRL:
3098 case MESA_SHADER_GEOMETRY:
3099 return;
3100 case MESA_SHADER_VERTEX:
3101 if (ctx->options->key.vs.as_ls ||
3102 ctx->options->key.vs.as_es)
3103 return;
3104 outinfo = &ctx->shader_info->vs.outinfo;
3105 break;
3106 case MESA_SHADER_TESS_EVAL:
3107 if (ctx->options->key.vs.as_es)
3108 return;
3109 outinfo = &ctx->shader_info->tes.outinfo;
3110 break;
3111 default:
3112 unreachable("Unhandled shader type");
3113 }
3114
3115 ac_optimize_vs_outputs(&ctx->ac,
3116 ctx->main_function,
3117 outinfo->vs_output_param_offset,
3118 VARYING_SLOT_MAX,
3119 &outinfo->param_exports);
3120 }
3121
3122 static void
3123 ac_setup_rings(struct radv_shader_context *ctx)
3124 {
3125 if (ctx->options->chip_class <= VI &&
3126 (ctx->stage == MESA_SHADER_GEOMETRY ||
3127 ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
3128 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3129 : RING_ESGS_VS;
3130 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3131
3132 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3133 ctx->ring_offsets,
3134 offset);
3135 }
3136
3137 if (ctx->is_gs_copy_shader) {
3138 ctx->gsvs_ring =
3139 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3140 LLVMConstInt(ctx->ac.i32,
3141 RING_GSVS_VS, false));
3142 }
3143
3144 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3145 unsigned num_records = 64;
3146 LLVMValueRef base_ring;
3147 LLVMValueRef ring, tmp;
3148 unsigned stride;
3149
3150 base_ring =
3151 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3152 LLVMConstInt(ctx->ac.i32,
3153 RING_GSVS_GS, false));
3154
3155 stride = ctx->max_gsvs_emit_size;
3156
3157 ring = LLVMBuildBitCast(ctx->ac.builder, base_ring,
3158 ctx->ac.v4i32, "");
3159
3160 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3161 ctx->ac.i32_1, "");
3162 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3163 LLVMConstInt(ctx->ac.i32,
3164 S_008F04_STRIDE(stride), false), "");
3165 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3166 ctx->ac.i32_1, "");
3167
3168 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3169 LLVMConstInt(ctx->ac.i32,
3170 num_records, false),
3171 LLVMConstInt(ctx->ac.i32, 2, false), "");
3172
3173 ctx->gsvs_ring = ring;
3174 }
3175
3176 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3177 ctx->stage == MESA_SHADER_TESS_EVAL) {
3178 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3179 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3180 }
3181 }
3182
3183 static unsigned
3184 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
3185 const struct nir_shader *nir)
3186 {
3187 switch (nir->info.stage) {
3188 case MESA_SHADER_TESS_CTRL:
3189 return chip_class >= CIK ? 128 : 64;
3190 case MESA_SHADER_GEOMETRY:
3191 return chip_class >= GFX9 ? 128 : 64;
3192 case MESA_SHADER_COMPUTE:
3193 break;
3194 default:
3195 return 0;
3196 }
3197
3198 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
3199 nir->info.cs.local_size[1] *
3200 nir->info.cs.local_size[2];
3201 return max_workgroup_size;
3202 }
3203
3204 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3205 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3206 {
3207 LLVMValueRef count = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
3208 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3209 ctx->ac.i32_0, "");
3210 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
3211 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
3212 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3213 }
3214
3215 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3216 {
3217 for(int i = 5; i >= 0; --i) {
3218 ctx->gs_vtx_offset[i] = ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3219 (i & 1) * 16, 16);
3220 }
3221
3222 ctx->gs_wave_id = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 16, 8);
3223 }
3224
3225
3226 static
3227 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
3228 struct nir_shader *const *shaders,
3229 int shader_count,
3230 struct radv_shader_variant_info *shader_info,
3231 const struct radv_nir_compiler_options *options)
3232 {
3233 struct radv_shader_context ctx = {0};
3234 unsigned i;
3235 ctx.options = options;
3236 ctx.shader_info = shader_info;
3237
3238 ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
3239 ctx.context = ctx.ac.context;
3240 ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
3241
3242 enum ac_float_mode float_mode =
3243 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3244 AC_FLOAT_MODE_DEFAULT;
3245
3246 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3247
3248 memset(shader_info, 0, sizeof(*shader_info));
3249
3250 for(int i = 0; i < shader_count; ++i)
3251 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3252
3253 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3254 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3255 for (i = 0; i < AC_UD_MAX_UD; i++)
3256 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3257
3258 ctx.max_workgroup_size = 0;
3259 for (int i = 0; i < shader_count; ++i) {
3260 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3261 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3262 shaders[i]));
3263 }
3264
3265 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3266 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3267
3268 ctx.abi.inputs = &ctx.inputs[0];
3269 ctx.abi.emit_outputs = handle_shader_outputs_post;
3270 ctx.abi.emit_vertex = visit_emit_vertex;
3271 ctx.abi.load_ubo = radv_load_ubo;
3272 ctx.abi.load_ssbo = radv_load_ssbo;
3273 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3274 ctx.abi.load_resource = radv_load_resource;
3275 ctx.abi.clamp_shadow_reference = false;
3276 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9;
3277
3278 if (shader_count >= 2)
3279 ac_init_exec_full_mask(&ctx.ac);
3280
3281 if (ctx.ac.chip_class == GFX9 &&
3282 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3283 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3284
3285 for(int i = 0; i < shader_count; ++i) {
3286 ctx.stage = shaders[i]->info.stage;
3287 ctx.output_mask = 0;
3288
3289 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3290 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3291 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3292 ctx.abi.load_inputs = load_gs_input;
3293 ctx.abi.emit_primitive = visit_end_primitive;
3294 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3295 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3296 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3297 ctx.abi.load_tess_varyings = load_tcs_varyings;
3298 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3299 ctx.abi.store_tcs_outputs = store_tcs_output;
3300 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3301 if (shader_count == 1)
3302 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3303 else
3304 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3305 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3306 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3307 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3308 ctx.abi.load_tess_varyings = load_tes_input;
3309 ctx.abi.load_tess_coord = load_tess_coord;
3310 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3311 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3312 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3313 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3314 if (shader_info->info.vs.needs_instance_id) {
3315 if (ctx.options->key.vs.as_ls) {
3316 ctx.shader_info->vs.vgpr_comp_cnt =
3317 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3318 } else {
3319 ctx.shader_info->vs.vgpr_comp_cnt =
3320 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3321 }
3322 }
3323 ctx.abi.load_base_vertex = radv_load_base_vertex;
3324 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3325 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3326 ctx.abi.lookup_interp_param = lookup_interp_param;
3327 ctx.abi.load_sample_position = load_sample_position;
3328 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3329 ctx.abi.emit_kill = radv_emit_kill;
3330 }
3331
3332 if (i)
3333 ac_emit_barrier(&ctx.ac, ctx.stage);
3334
3335 nir_foreach_variable(variable, &shaders[i]->outputs)
3336 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3337
3338 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3339 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3340 shaders[i]->info.cull_distance_array_size > 4;
3341 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3342 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3343 shaders[i]->info.gs.vertices_out;
3344 }
3345
3346 ac_setup_rings(&ctx);
3347
3348 LLVMBasicBlockRef merge_block;
3349 if (shader_count >= 2) {
3350 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3351 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3352 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3353
3354 LLVMValueRef count = ac_unpack_param(&ctx.ac, ctx.merged_wave_info, 8 * i, 8);
3355 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3356 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3357 thread_id, count, "");
3358 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3359
3360 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3361 }
3362
3363 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3364 handle_fs_inputs(&ctx, shaders[i]);
3365 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3366 handle_vs_inputs(&ctx, shaders[i]);
3367 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3368 prepare_gs_input_vgprs(&ctx);
3369
3370 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3371
3372 if (shader_count >= 2) {
3373 LLVMBuildBr(ctx.ac.builder, merge_block);
3374 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3375 }
3376
3377 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3378 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3379 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3380 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3381 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3382 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3383 }
3384 }
3385
3386 LLVMBuildRetVoid(ctx.ac.builder);
3387
3388 if (options->dump_preoptir)
3389 ac_dump_module(ctx.ac.module);
3390
3391 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
3392
3393 if (shader_count == 1)
3394 ac_nir_eliminate_const_vs_outputs(&ctx);
3395
3396 if (options->dump_shader) {
3397 ctx.shader_info->private_mem_vgprs =
3398 ac_count_scratch_private_memory(ctx.main_function);
3399 }
3400
3401 return ctx.ac.module;
3402 }
3403
3404 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3405 {
3406 unsigned *retval = (unsigned *)context;
3407 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3408 char *description = LLVMGetDiagInfoDescription(di);
3409
3410 if (severity == LLVMDSError) {
3411 *retval = 1;
3412 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3413 description);
3414 }
3415
3416 LLVMDisposeMessage(description);
3417 }
3418
3419 static unsigned ac_llvm_compile(LLVMModuleRef M,
3420 struct ac_shader_binary *binary,
3421 struct ac_llvm_compiler *ac_llvm)
3422 {
3423 unsigned retval = 0;
3424 LLVMContextRef llvm_ctx;
3425
3426 /* Setup Diagnostic Handler*/
3427 llvm_ctx = LLVMGetModuleContext(M);
3428
3429 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3430 &retval);
3431
3432 /* Compile IR*/
3433 if (!radv_compile_to_binary(ac_llvm, M, binary))
3434 retval = 1;
3435 return retval;
3436 }
3437
3438 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
3439 LLVMModuleRef llvm_module,
3440 struct ac_shader_binary *binary,
3441 struct ac_shader_config *config,
3442 struct radv_shader_variant_info *shader_info,
3443 gl_shader_stage stage,
3444 const struct radv_nir_compiler_options *options)
3445 {
3446 if (options->dump_shader)
3447 ac_dump_module(llvm_module);
3448
3449 memset(binary, 0, sizeof(*binary));
3450
3451 if (options->record_llvm_ir) {
3452 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3453 binary->llvm_ir_string = strdup(llvm_ir);
3454 LLVMDisposeMessage(llvm_ir);
3455 }
3456
3457 int v = ac_llvm_compile(llvm_module, binary, ac_llvm);
3458 if (v) {
3459 fprintf(stderr, "compile failed\n");
3460 }
3461
3462 if (options->dump_shader)
3463 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3464
3465 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3466
3467 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3468 LLVMDisposeModule(llvm_module);
3469 LLVMContextDispose(ctx);
3470
3471 if (stage == MESA_SHADER_FRAGMENT) {
3472 shader_info->num_input_vgprs = 0;
3473 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3474 shader_info->num_input_vgprs += 2;
3475 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3476 shader_info->num_input_vgprs += 2;
3477 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3478 shader_info->num_input_vgprs += 2;
3479 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3480 shader_info->num_input_vgprs += 3;
3481 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3482 shader_info->num_input_vgprs += 2;
3483 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3484 shader_info->num_input_vgprs += 2;
3485 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3486 shader_info->num_input_vgprs += 2;
3487 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3488 shader_info->num_input_vgprs += 1;
3489 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3490 shader_info->num_input_vgprs += 1;
3491 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3492 shader_info->num_input_vgprs += 1;
3493 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3494 shader_info->num_input_vgprs += 1;
3495 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3496 shader_info->num_input_vgprs += 1;
3497 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3498 shader_info->num_input_vgprs += 1;
3499 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3500 shader_info->num_input_vgprs += 1;
3501 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3502 shader_info->num_input_vgprs += 1;
3503 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3504 shader_info->num_input_vgprs += 1;
3505 }
3506 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3507
3508 /* +3 for scratch wave offset and VCC */
3509 config->num_sgprs = MAX2(config->num_sgprs,
3510 shader_info->num_input_sgprs + 3);
3511
3512 /* Enable 64-bit and 16-bit denormals, because there is no performance
3513 * cost.
3514 *
3515 * If denormals are enabled, all floating-point output modifiers are
3516 * ignored.
3517 *
3518 * Don't enable denormals for 32-bit floats, because:
3519 * - Floating-point output modifiers would be ignored by the hw.
3520 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3521 * have to stop using those.
3522 * - SI & CI would be very slow.
3523 */
3524 config->float_mode |= V_00B028_FP_64_DENORMS;
3525 }
3526
3527 static void
3528 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3529 {
3530 switch (nir->info.stage) {
3531 case MESA_SHADER_COMPUTE:
3532 for (int i = 0; i < 3; ++i)
3533 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3534 break;
3535 case MESA_SHADER_FRAGMENT:
3536 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3537 break;
3538 case MESA_SHADER_GEOMETRY:
3539 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3540 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3541 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3542 shader_info->gs.invocations = nir->info.gs.invocations;
3543 break;
3544 case MESA_SHADER_TESS_EVAL:
3545 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3546 shader_info->tes.spacing = nir->info.tess.spacing;
3547 shader_info->tes.ccw = nir->info.tess.ccw;
3548 shader_info->tes.point_mode = nir->info.tess.point_mode;
3549 shader_info->tes.as_es = options->key.tes.as_es;
3550 break;
3551 case MESA_SHADER_TESS_CTRL:
3552 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3553 break;
3554 case MESA_SHADER_VERTEX:
3555 shader_info->vs.as_es = options->key.vs.as_es;
3556 shader_info->vs.as_ls = options->key.vs.as_ls;
3557 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3558 if (options->key.vs.as_ls)
3559 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3560 break;
3561 default:
3562 break;
3563 }
3564 }
3565
3566 void
3567 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
3568 struct ac_shader_binary *binary,
3569 struct ac_shader_config *config,
3570 struct radv_shader_variant_info *shader_info,
3571 struct nir_shader *const *nir,
3572 int nir_count,
3573 const struct radv_nir_compiler_options *options)
3574 {
3575
3576 LLVMModuleRef llvm_module;
3577
3578 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, shader_info,
3579 options);
3580
3581 ac_compile_llvm_module(ac_llvm, llvm_module, binary, config, shader_info,
3582 nir[0]->info.stage, options);
3583
3584 for (int i = 0; i < nir_count; ++i)
3585 ac_fill_shader_info(shader_info, nir[i], options);
3586
3587 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3588 if (options->chip_class == GFX9) {
3589 if (nir_count == 2 &&
3590 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3591 shader_info->gs.es_type = nir[0]->info.stage;
3592 }
3593 }
3594 }
3595
3596 static void
3597 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3598 {
3599 LLVMValueRef vtx_offset =
3600 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3601 LLVMConstInt(ctx->ac.i32, 4, false), "");
3602 unsigned offset = 0;
3603
3604 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3605 unsigned output_usage_mask =
3606 ctx->shader_info->info.gs.output_usage_mask[i];
3607 int length = util_last_bit(output_usage_mask);
3608
3609 if (!(ctx->output_mask & (1ull << i)))
3610 continue;
3611
3612 for (unsigned j = 0; j < length; j++) {
3613 LLVMValueRef value, soffset;
3614
3615 if (!(output_usage_mask & (1 << j)))
3616 continue;
3617
3618 soffset = LLVMConstInt(ctx->ac.i32,
3619 offset *
3620 ctx->gs_max_out_vertices * 16 * 4, false);
3621
3622 offset++;
3623
3624 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3625 1, ctx->ac.i32_0,
3626 vtx_offset, soffset,
3627 0, 1, 1, true, false);
3628
3629 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3630 if (ac_get_type_size(type) == 2) {
3631 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
3632 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
3633 }
3634
3635 LLVMBuildStore(ctx->ac.builder,
3636 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3637 }
3638 }
3639 handle_vs_outputs_post(ctx, false, false, &ctx->shader_info->vs.outinfo);
3640 }
3641
3642 void
3643 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
3644 struct nir_shader *geom_shader,
3645 struct ac_shader_binary *binary,
3646 struct ac_shader_config *config,
3647 struct radv_shader_variant_info *shader_info,
3648 const struct radv_nir_compiler_options *options)
3649 {
3650 struct radv_shader_context ctx = {0};
3651 ctx.options = options;
3652 ctx.shader_info = shader_info;
3653
3654 ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
3655 ctx.context = ctx.ac.context;
3656 ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
3657
3658 ctx.is_gs_copy_shader = true;
3659
3660 enum ac_float_mode float_mode =
3661 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3662 AC_FLOAT_MODE_DEFAULT;
3663
3664 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3665 ctx.stage = MESA_SHADER_VERTEX;
3666
3667 radv_nir_shader_info_pass(geom_shader, options, &shader_info->info);
3668
3669 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3670
3671 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3672 ac_setup_rings(&ctx);
3673
3674 nir_foreach_variable(variable, &geom_shader->outputs) {
3675 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3676 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3677 variable, MESA_SHADER_VERTEX);
3678 }
3679
3680 ac_gs_copy_shader_emit(&ctx);
3681
3682 LLVMBuildRetVoid(ctx.ac.builder);
3683
3684 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
3685
3686 ac_compile_llvm_module(ac_llvm, ctx.ac.module, binary, config, shader_info,
3687 MESA_SHADER_VERTEX, options);
3688 }