2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_llvm_build.h"
42 #include "ac_shader_abi.h"
43 #include "ac_shader_util.h"
44 #include "ac_exp_param.h"
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 struct radv_shader_context
{
49 struct ac_llvm_context ac
;
50 const struct radv_nir_compiler_options
*options
;
51 struct radv_shader_variant_info
*shader_info
;
52 struct ac_shader_abi abi
;
54 unsigned max_workgroup_size
;
55 LLVMContextRef context
;
56 LLVMValueRef main_function
;
58 LLVMValueRef descriptor_sets
[RADV_UD_MAX_SETS
];
59 LLVMValueRef ring_offsets
;
61 LLVMValueRef vertex_buffers
;
62 LLVMValueRef rel_auto_id
;
63 LLVMValueRef vs_prim_id
;
64 LLVMValueRef es2gs_offset
;
67 LLVMValueRef merged_wave_info
;
68 LLVMValueRef tess_factor_offset
;
69 LLVMValueRef tes_rel_patch_id
;
73 LLVMValueRef gs2vs_offset
;
74 LLVMValueRef gs_wave_id
;
75 LLVMValueRef gs_vtx_offset
[6];
77 LLVMValueRef esgs_ring
;
78 LLVMValueRef gsvs_ring
[4];
79 LLVMValueRef hs_ring_tess_offchip
;
80 LLVMValueRef hs_ring_tess_factor
;
82 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
83 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
86 LLVMValueRef streamout_buffers
;
87 LLVMValueRef streamout_write_idx
;
88 LLVMValueRef streamout_config
;
89 LLVMValueRef streamout_offset
[4];
91 gl_shader_stage stage
;
93 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
94 uint64_t float16_shaded_mask
;
99 bool is_gs_copy_shader
;
100 LLVMValueRef gs_next_vertex
[4];
101 unsigned gs_max_out_vertices
;
103 unsigned tes_primitive_mode
;
105 uint32_t tcs_patch_outputs_read
;
106 uint64_t tcs_outputs_read
;
107 uint32_t tcs_vertices_per_patch
;
108 uint32_t tcs_num_inputs
;
109 uint32_t tcs_num_patches
;
110 uint32_t max_gsvs_emit_size
;
111 uint32_t gsvs_vertex_size
;
114 enum radeon_llvm_calling_convention
{
115 RADEON_LLVM_AMDGPU_VS
= 87,
116 RADEON_LLVM_AMDGPU_GS
= 88,
117 RADEON_LLVM_AMDGPU_PS
= 89,
118 RADEON_LLVM_AMDGPU_CS
= 90,
119 RADEON_LLVM_AMDGPU_HS
= 93,
122 static inline struct radv_shader_context
*
123 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
125 struct radv_shader_context
*ctx
= NULL
;
126 return container_of(abi
, ctx
, abi
);
129 struct ac_build_if_state
131 struct radv_shader_context
*ctx
;
132 LLVMValueRef condition
;
133 LLVMBasicBlockRef entry_block
;
134 LLVMBasicBlockRef true_block
;
135 LLVMBasicBlockRef false_block
;
136 LLVMBasicBlockRef merge_block
;
139 static LLVMBasicBlockRef
140 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
142 LLVMBasicBlockRef current_block
;
143 LLVMBasicBlockRef next_block
;
144 LLVMBasicBlockRef new_block
;
146 /* get current basic block */
147 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
149 /* chqeck if there's another block after this one */
150 next_block
= LLVMGetNextBasicBlock(current_block
);
152 /* insert the new block before the next block */
153 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
156 /* append new block after current block */
157 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
158 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
164 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
165 struct radv_shader_context
*ctx
,
166 LLVMValueRef condition
)
168 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
170 memset(ifthen
, 0, sizeof *ifthen
);
172 ifthen
->condition
= condition
;
173 ifthen
->entry_block
= block
;
175 /* create endif/merge basic block for the phi functions */
176 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
178 /* create/insert true_block before merge_block */
180 LLVMInsertBasicBlockInContext(ctx
->context
,
184 /* successive code goes into the true block */
185 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
192 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
194 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
196 /* Insert branch to the merge block from current block */
197 LLVMBuildBr(builder
, ifthen
->merge_block
);
200 * Now patch in the various branch instructions.
203 /* Insert the conditional branch instruction at the end of entry_block */
204 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
205 if (ifthen
->false_block
) {
206 /* we have an else clause */
207 LLVMBuildCondBr(builder
, ifthen
->condition
,
208 ifthen
->true_block
, ifthen
->false_block
);
212 LLVMBuildCondBr(builder
, ifthen
->condition
,
213 ifthen
->true_block
, ifthen
->merge_block
);
216 /* Resume building code at end of the ifthen->merge_block */
217 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
221 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
223 switch (ctx
->stage
) {
224 case MESA_SHADER_TESS_CTRL
:
225 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
226 case MESA_SHADER_TESS_EVAL
:
227 return ctx
->tes_rel_patch_id
;
230 unreachable("Illegal stage");
235 get_tcs_num_patches(struct radv_shader_context
*ctx
)
237 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
238 unsigned num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
239 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
240 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
241 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
242 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
243 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
244 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
245 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
246 unsigned num_patches
;
247 unsigned hardware_lds_size
;
249 /* Ensure that we only need one wave per SIMD so we don't need to check
250 * resource usage. Also ensures that the number of tcs in and out
251 * vertices per threadgroup are at most 256.
253 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
254 /* Make sure that the data fits in LDS. This assumes the shaders only
255 * use LDS for the inputs and outputs.
257 hardware_lds_size
= 32768;
259 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
260 * threadgroup, even though there is more than 32 KiB LDS.
262 * Test: dEQP-VK.tessellation.shader_input_output.barrier
264 if (ctx
->options
->chip_class
>= GFX7
&& ctx
->options
->family
!= CHIP_STONEY
)
265 hardware_lds_size
= 65536;
267 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
268 /* Make sure the output data fits in the offchip buffer */
269 num_patches
= MIN2(num_patches
, (ctx
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
270 /* Not necessary for correctness, but improves performance. The
271 * specific value is taken from the proprietary driver.
273 num_patches
= MIN2(num_patches
, 40);
275 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
276 if (ctx
->options
->chip_class
== GFX6
) {
277 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
278 num_patches
= MIN2(num_patches
, one_wave
);
284 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
286 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
287 unsigned num_tcs_output_cp
;
288 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
289 unsigned input_vertex_size
, output_vertex_size
;
290 unsigned input_patch_size
, output_patch_size
;
291 unsigned pervertex_output_patch_size
;
292 unsigned output_patch0_offset
;
293 unsigned num_patches
;
296 num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
297 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
298 num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
300 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
301 output_vertex_size
= num_tcs_outputs
* 16;
303 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
305 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
306 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
308 num_patches
= ctx
->tcs_num_patches
;
309 output_patch0_offset
= input_patch_size
* num_patches
;
311 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
315 /* Tessellation shaders pass outputs to the next shader using LDS.
317 * LS outputs = TCS inputs
318 * TCS outputs = TES inputs
321 * - TCS inputs for patch 0
322 * - TCS inputs for patch 1
323 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
325 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
326 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
327 * - TCS outputs for patch 1
328 * - Per-patch TCS outputs for patch 1
329 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
330 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
333 * All three shaders VS(LS), TCS, TES share the same LDS space.
336 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
338 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
339 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
340 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
342 input_patch_size
/= 4;
343 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
347 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
349 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
350 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
351 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
352 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
353 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
354 output_patch_size
/= 4;
355 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
359 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
361 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
362 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
363 output_vertex_size
/= 4;
364 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
368 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
370 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
371 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
372 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
373 uint32_t output_patch0_offset
= input_patch_size
;
374 unsigned num_patches
= ctx
->tcs_num_patches
;
376 output_patch0_offset
*= num_patches
;
377 output_patch0_offset
/= 4;
378 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
382 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
384 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
385 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
386 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
387 uint32_t output_patch0_offset
= input_patch_size
;
389 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
390 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
391 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
392 unsigned num_patches
= ctx
->tcs_num_patches
;
394 output_patch0_offset
*= num_patches
;
395 output_patch0_offset
+= pervertex_output_patch_size
;
396 output_patch0_offset
/= 4;
397 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
401 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
403 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
404 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
406 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
410 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
412 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
413 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
414 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
416 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
421 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
423 LLVMValueRef patch0_patch_data_offset
=
424 get_tcs_out_patch0_patch_data_offset(ctx
);
425 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
426 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
428 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
429 patch0_patch_data_offset
);
434 LLVMTypeRef types
[MAX_ARGS
];
435 LLVMValueRef
*assign
[MAX_ARGS
];
438 uint8_t num_sgprs_used
;
439 uint8_t num_vgprs_used
;
442 enum ac_arg_regfile
{
448 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
449 LLVMValueRef
*param_ptr
)
451 assert(info
->count
< MAX_ARGS
);
453 info
->assign
[info
->count
] = param_ptr
;
454 info
->types
[info
->count
] = type
;
457 if (regfile
== ARG_SGPR
) {
458 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
461 assert(regfile
== ARG_VGPR
);
462 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
466 static void assign_arguments(LLVMValueRef main_function
,
467 struct arg_info
*info
)
470 for (i
= 0; i
< info
->count
; i
++) {
472 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
477 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
478 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
479 unsigned num_return_elems
,
480 struct arg_info
*args
,
481 unsigned max_workgroup_size
,
482 const struct radv_nir_compiler_options
*options
)
484 LLVMTypeRef main_function_type
, ret_type
;
485 LLVMBasicBlockRef main_function_body
;
487 if (num_return_elems
)
488 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
489 num_return_elems
, true);
491 ret_type
= LLVMVoidTypeInContext(ctx
);
493 /* Setup the function */
495 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
496 LLVMValueRef main_function
=
497 LLVMAddFunction(module
, "main", main_function_type
);
499 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
500 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
502 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
503 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
504 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
506 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
508 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
509 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
510 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
514 if (options
->address32_hi
) {
515 ac_llvm_add_target_dep_function_attr(main_function
,
516 "amdgpu-32bit-address-high-bits",
517 options
->address32_hi
);
520 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
522 if (options
->unsafe_math
) {
523 /* These were copied from some LLVM test. */
524 LLVMAddTargetDependentFunctionAttr(main_function
,
525 "less-precise-fpmad",
527 LLVMAddTargetDependentFunctionAttr(main_function
,
530 LLVMAddTargetDependentFunctionAttr(main_function
,
533 LLVMAddTargetDependentFunctionAttr(main_function
,
536 LLVMAddTargetDependentFunctionAttr(main_function
,
537 "no-signed-zeros-fp-math",
540 return main_function
;
545 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
,
548 ud_info
->sgpr_idx
= *sgpr_idx
;
549 ud_info
->num_sgprs
= num_sgprs
;
550 *sgpr_idx
+= num_sgprs
;
554 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
557 struct radv_userdata_info
*ud_info
=
558 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
561 set_loc(ud_info
, sgpr_idx
, num_sgprs
);
565 set_loc_shader_ptr(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
567 bool use_32bit_pointers
= idx
!= AC_UD_SCRATCH_RING_OFFSETS
;
569 set_loc_shader(ctx
, idx
, sgpr_idx
, use_32bit_pointers
? 1 : 2);
573 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
575 struct radv_userdata_locations
*locs
=
576 &ctx
->shader_info
->user_sgprs_locs
;
577 struct radv_userdata_info
*ud_info
= &locs
->descriptor_sets
[idx
];
580 set_loc(ud_info
, sgpr_idx
, 1);
582 locs
->descriptor_sets_enabled
|= 1 << idx
;
585 struct user_sgpr_info
{
586 bool need_ring_offsets
;
587 bool indirect_all_descriptor_sets
;
588 uint8_t remaining_sgprs
;
591 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
592 gl_shader_stage stage
)
595 case MESA_SHADER_VERTEX
:
596 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
597 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
600 case MESA_SHADER_TESS_EVAL
:
601 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
604 case MESA_SHADER_GEOMETRY
:
605 case MESA_SHADER_TESS_CTRL
:
606 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
616 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
620 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
622 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
627 static void allocate_inline_push_consts(struct radv_shader_context
*ctx
,
628 struct user_sgpr_info
*user_sgpr_info
)
630 uint8_t remaining_sgprs
= user_sgpr_info
->remaining_sgprs
;
632 /* Only supported if shaders use push constants. */
633 if (ctx
->shader_info
->info
.min_push_constant_used
== UINT8_MAX
)
636 /* Only supported if shaders don't have indirect push constants. */
637 if (ctx
->shader_info
->info
.has_indirect_push_constants
)
640 /* Only supported for 32-bit push constants. */
641 if (!ctx
->shader_info
->info
.has_only_32bit_push_constants
)
644 uint8_t num_push_consts
=
645 (ctx
->shader_info
->info
.max_push_constant_used
-
646 ctx
->shader_info
->info
.min_push_constant_used
) / 4;
648 /* Check if the number of user SGPRs is large enough. */
649 if (num_push_consts
< remaining_sgprs
) {
650 ctx
->shader_info
->info
.num_inline_push_consts
= num_push_consts
;
652 ctx
->shader_info
->info
.num_inline_push_consts
= remaining_sgprs
;
655 /* Clamp to the maximum number of allowed inlined push constants. */
656 if (ctx
->shader_info
->info
.num_inline_push_consts
> AC_MAX_INLINE_PUSH_CONSTS
)
657 ctx
->shader_info
->info
.num_inline_push_consts
= AC_MAX_INLINE_PUSH_CONSTS
;
659 if (ctx
->shader_info
->info
.num_inline_push_consts
== num_push_consts
&&
660 !ctx
->shader_info
->info
.loads_dynamic_offsets
) {
661 /* Disable the default push constants path if all constants are
662 * inlined and if shaders don't use dynamic descriptors.
664 ctx
->shader_info
->info
.loads_push_constants
= false;
667 ctx
->shader_info
->info
.base_inline_push_consts
=
668 ctx
->shader_info
->info
.min_push_constant_used
/ 4;
671 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
672 gl_shader_stage stage
,
673 bool has_previous_stage
,
674 gl_shader_stage previous_stage
,
675 bool needs_view_index
,
676 struct user_sgpr_info
*user_sgpr_info
)
678 uint8_t user_sgpr_count
= 0;
680 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
682 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
683 if (stage
== MESA_SHADER_GEOMETRY
||
684 stage
== MESA_SHADER_VERTEX
||
685 stage
== MESA_SHADER_TESS_CTRL
||
686 stage
== MESA_SHADER_TESS_EVAL
||
687 ctx
->is_gs_copy_shader
)
688 user_sgpr_info
->need_ring_offsets
= true;
690 if (stage
== MESA_SHADER_FRAGMENT
&&
691 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
692 user_sgpr_info
->need_ring_offsets
= true;
694 /* 2 user sgprs will nearly always be allocated for scratch/rings */
695 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
696 user_sgpr_count
+= 2;
700 case MESA_SHADER_COMPUTE
:
701 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
702 user_sgpr_count
+= 3;
704 case MESA_SHADER_FRAGMENT
:
705 user_sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
707 case MESA_SHADER_VERTEX
:
708 if (!ctx
->is_gs_copy_shader
)
709 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
711 case MESA_SHADER_TESS_CTRL
:
712 if (has_previous_stage
) {
713 if (previous_stage
== MESA_SHADER_VERTEX
)
714 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
717 case MESA_SHADER_TESS_EVAL
:
719 case MESA_SHADER_GEOMETRY
:
720 if (has_previous_stage
) {
721 if (previous_stage
== MESA_SHADER_VERTEX
) {
722 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
730 if (needs_view_index
)
733 if (ctx
->shader_info
->info
.loads_push_constants
)
736 if (ctx
->streamout_buffers
)
739 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
&& stage
!= MESA_SHADER_COMPUTE
? 32 : 16;
740 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_count
;
741 uint32_t num_desc_set
=
742 util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
);
744 if (remaining_sgprs
< num_desc_set
) {
745 user_sgpr_info
->indirect_all_descriptor_sets
= true;
746 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- 1;
748 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- num_desc_set
;
751 allocate_inline_push_consts(ctx
, user_sgpr_info
);
755 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
756 const struct user_sgpr_info
*user_sgpr_info
,
757 struct arg_info
*args
,
758 LLVMValueRef
*desc_sets
)
760 LLVMTypeRef type
= ac_array_in_const32_addr_space(ctx
->ac
.i8
);
762 /* 1 for each descriptor set */
763 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
764 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
767 int i
= u_bit_scan(&mask
);
769 add_arg(args
, ARG_SGPR
, type
, &ctx
->descriptor_sets
[i
]);
772 add_arg(args
, ARG_SGPR
, ac_array_in_const32_addr_space(type
),
776 if (ctx
->shader_info
->info
.loads_push_constants
) {
777 /* 1 for push constants and dynamic descriptors */
778 add_arg(args
, ARG_SGPR
, type
, &ctx
->abi
.push_constants
);
781 for (unsigned i
= 0; i
< ctx
->shader_info
->info
.num_inline_push_consts
; i
++) {
782 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
,
783 &ctx
->abi
.inline_push_consts
[i
]);
785 ctx
->abi
.num_inline_push_consts
= ctx
->shader_info
->info
.num_inline_push_consts
;
786 ctx
->abi
.base_inline_push_consts
= ctx
->shader_info
->info
.base_inline_push_consts
;
788 if (ctx
->shader_info
->info
.so
.num_outputs
) {
789 add_arg(args
, ARG_SGPR
,
790 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
791 &ctx
->streamout_buffers
);
796 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
797 gl_shader_stage stage
,
798 bool has_previous_stage
,
799 gl_shader_stage previous_stage
,
800 struct arg_info
*args
)
802 if (!ctx
->is_gs_copy_shader
&&
803 (stage
== MESA_SHADER_VERTEX
||
804 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
805 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
806 add_arg(args
, ARG_SGPR
,
807 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
808 &ctx
->vertex_buffers
);
810 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
811 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
812 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
813 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
819 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
821 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
822 if (!ctx
->is_gs_copy_shader
) {
823 if (ctx
->options
->key
.vs
.as_ls
) {
824 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
825 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
827 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
828 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
830 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
835 declare_streamout_sgprs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
836 struct arg_info
*args
)
840 if (ctx
->ac
.chip_class
>= GFX10
)
843 /* Streamout SGPRs. */
844 if (ctx
->shader_info
->info
.so
.num_outputs
) {
845 assert(stage
== MESA_SHADER_VERTEX
||
846 stage
== MESA_SHADER_TESS_EVAL
);
848 if (stage
!= MESA_SHADER_TESS_EVAL
) {
849 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_config
);
851 args
->assign
[args
->count
- 1] = &ctx
->streamout_config
;
852 args
->types
[args
->count
- 1] = ctx
->ac
.i32
;
855 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_write_idx
);
858 /* A streamout buffer offset is loaded if the stride is non-zero. */
859 for (i
= 0; i
< 4; i
++) {
860 if (!ctx
->shader_info
->info
.so
.strides
[i
])
863 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_offset
[i
]);
868 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
870 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
871 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
872 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
873 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
877 set_global_input_locs(struct radv_shader_context
*ctx
,
878 const struct user_sgpr_info
*user_sgpr_info
,
879 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
881 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
883 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
885 int i
= u_bit_scan(&mask
);
887 set_loc_desc(ctx
, i
, user_sgpr_idx
);
890 set_loc_shader_ptr(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
894 int i
= u_bit_scan(&mask
);
896 ctx
->descriptor_sets
[i
] =
897 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
898 LLVMConstInt(ctx
->ac
.i32
, i
, false));
902 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
905 if (ctx
->shader_info
->info
.loads_push_constants
) {
906 set_loc_shader_ptr(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
);
909 if (ctx
->shader_info
->info
.num_inline_push_consts
) {
910 set_loc_shader(ctx
, AC_UD_INLINE_PUSH_CONSTANTS
, user_sgpr_idx
,
911 ctx
->shader_info
->info
.num_inline_push_consts
);
914 if (ctx
->streamout_buffers
) {
915 set_loc_shader_ptr(ctx
, AC_UD_STREAMOUT_BUFFERS
,
921 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
922 gl_shader_stage stage
, bool has_previous_stage
,
923 gl_shader_stage previous_stage
,
924 uint8_t *user_sgpr_idx
)
926 if (!ctx
->is_gs_copy_shader
&&
927 (stage
== MESA_SHADER_VERTEX
||
928 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
929 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
930 set_loc_shader_ptr(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
935 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
938 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
939 user_sgpr_idx
, vs_num
);
943 static void set_llvm_calling_convention(LLVMValueRef func
,
944 gl_shader_stage stage
)
946 enum radeon_llvm_calling_convention calling_conv
;
949 case MESA_SHADER_VERTEX
:
950 case MESA_SHADER_TESS_EVAL
:
951 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
953 case MESA_SHADER_GEOMETRY
:
954 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
956 case MESA_SHADER_TESS_CTRL
:
957 calling_conv
= RADEON_LLVM_AMDGPU_HS
;
959 case MESA_SHADER_FRAGMENT
:
960 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
962 case MESA_SHADER_COMPUTE
:
963 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
966 unreachable("Unhandle shader type");
969 LLVMSetFunctionCallConv(func
, calling_conv
);
972 static void create_function(struct radv_shader_context
*ctx
,
973 gl_shader_stage stage
,
974 bool has_previous_stage
,
975 gl_shader_stage previous_stage
)
977 uint8_t user_sgpr_idx
;
978 struct user_sgpr_info user_sgpr_info
;
979 struct arg_info args
= {};
980 LLVMValueRef desc_sets
;
981 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
982 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
983 previous_stage
, needs_view_index
, &user_sgpr_info
);
985 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
986 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
991 case MESA_SHADER_COMPUTE
:
992 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
995 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
996 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
997 &ctx
->abi
.num_work_groups
);
1000 for (int i
= 0; i
< 3; i
++) {
1001 ctx
->abi
.workgroup_ids
[i
] = NULL
;
1002 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
1003 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1004 &ctx
->abi
.workgroup_ids
[i
]);
1008 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
1009 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
1010 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
1011 &ctx
->abi
.local_invocation_ids
);
1013 case MESA_SHADER_VERTEX
:
1014 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1017 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
1018 previous_stage
, &args
);
1020 if (needs_view_index
)
1021 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1022 &ctx
->abi
.view_index
);
1023 if (ctx
->options
->key
.vs
.as_es
) {
1024 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1025 &ctx
->es2gs_offset
);
1026 } else if (ctx
->options
->key
.vs
.as_ls
) {
1027 /* no extra parameters */
1029 declare_streamout_sgprs(ctx
, stage
, &args
);
1032 declare_vs_input_vgprs(ctx
, &args
);
1034 case MESA_SHADER_TESS_CTRL
:
1035 if (has_previous_stage
) {
1036 // First 6 system regs
1037 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1038 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1039 &ctx
->merged_wave_info
);
1040 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1041 &ctx
->tess_factor_offset
);
1043 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1044 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1045 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1047 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1050 declare_vs_specific_input_sgprs(ctx
, stage
,
1052 previous_stage
, &args
);
1054 if (needs_view_index
)
1055 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1056 &ctx
->abi
.view_index
);
1058 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1059 &ctx
->abi
.tcs_patch_id
);
1060 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1061 &ctx
->abi
.tcs_rel_ids
);
1063 declare_vs_input_vgprs(ctx
, &args
);
1065 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1068 if (needs_view_index
)
1069 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1070 &ctx
->abi
.view_index
);
1072 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1073 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1074 &ctx
->tess_factor_offset
);
1075 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1076 &ctx
->abi
.tcs_patch_id
);
1077 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1078 &ctx
->abi
.tcs_rel_ids
);
1081 case MESA_SHADER_TESS_EVAL
:
1082 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1085 if (needs_view_index
)
1086 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1087 &ctx
->abi
.view_index
);
1089 if (ctx
->options
->key
.tes
.as_es
) {
1090 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1091 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1092 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1093 &ctx
->es2gs_offset
);
1095 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1096 declare_streamout_sgprs(ctx
, stage
, &args
);
1097 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1099 declare_tes_input_vgprs(ctx
, &args
);
1101 case MESA_SHADER_GEOMETRY
:
1102 if (has_previous_stage
) {
1103 // First 6 system regs
1104 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1105 &ctx
->gs2vs_offset
);
1106 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1107 &ctx
->merged_wave_info
);
1108 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1110 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1111 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1112 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1114 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1117 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
1118 declare_vs_specific_input_sgprs(ctx
, stage
,
1124 if (needs_view_index
)
1125 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1126 &ctx
->abi
.view_index
);
1128 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1129 &ctx
->gs_vtx_offset
[0]);
1130 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1131 &ctx
->gs_vtx_offset
[2]);
1132 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1133 &ctx
->abi
.gs_prim_id
);
1134 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1135 &ctx
->abi
.gs_invocation_id
);
1136 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1137 &ctx
->gs_vtx_offset
[4]);
1139 if (previous_stage
== MESA_SHADER_VERTEX
) {
1140 declare_vs_input_vgprs(ctx
, &args
);
1142 declare_tes_input_vgprs(ctx
, &args
);
1145 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1148 if (needs_view_index
)
1149 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1150 &ctx
->abi
.view_index
);
1152 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1153 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1154 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1155 &ctx
->gs_vtx_offset
[0]);
1156 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1157 &ctx
->gs_vtx_offset
[1]);
1158 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1159 &ctx
->abi
.gs_prim_id
);
1160 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1161 &ctx
->gs_vtx_offset
[2]);
1162 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1163 &ctx
->gs_vtx_offset
[3]);
1164 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1165 &ctx
->gs_vtx_offset
[4]);
1166 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1167 &ctx
->gs_vtx_offset
[5]);
1168 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1169 &ctx
->abi
.gs_invocation_id
);
1172 case MESA_SHADER_FRAGMENT
:
1173 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1176 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1177 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1178 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1179 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1180 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1181 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1182 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1183 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1184 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1185 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1186 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1187 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1188 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1189 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1190 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1191 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1192 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1195 unreachable("Shader stage not implemented");
1198 ctx
->main_function
= create_llvm_function(
1199 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1200 ctx
->max_workgroup_size
, ctx
->options
);
1201 set_llvm_calling_convention(ctx
->main_function
, stage
);
1204 ctx
->shader_info
->num_input_vgprs
= 0;
1205 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1207 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1209 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1210 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1212 assign_arguments(ctx
->main_function
, &args
);
1216 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1217 set_loc_shader_ptr(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1219 if (ctx
->options
->supports_spill
) {
1220 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1221 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
1222 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1223 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1224 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1228 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1229 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1230 if (has_previous_stage
)
1233 set_global_input_locs(ctx
, &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1236 case MESA_SHADER_COMPUTE
:
1237 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1238 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1242 case MESA_SHADER_VERTEX
:
1243 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1244 previous_stage
, &user_sgpr_idx
);
1245 if (ctx
->abi
.view_index
)
1246 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1248 case MESA_SHADER_TESS_CTRL
:
1249 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1250 previous_stage
, &user_sgpr_idx
);
1251 if (ctx
->abi
.view_index
)
1252 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1254 case MESA_SHADER_TESS_EVAL
:
1255 if (ctx
->abi
.view_index
)
1256 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1258 case MESA_SHADER_GEOMETRY
:
1259 if (has_previous_stage
) {
1260 if (previous_stage
== MESA_SHADER_VERTEX
)
1261 set_vs_specific_input_locs(ctx
, stage
,
1266 if (ctx
->abi
.view_index
)
1267 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1269 case MESA_SHADER_FRAGMENT
:
1272 unreachable("Shader stage not implemented");
1275 if (stage
== MESA_SHADER_TESS_CTRL
||
1276 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_ls
) ||
1277 /* GFX9 has the ESGS ring buffer in LDS. */
1278 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1279 ac_declare_lds_as_pointer(&ctx
->ac
);
1282 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1287 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1288 unsigned desc_set
, unsigned binding
)
1290 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1291 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1292 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
1293 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1294 unsigned base_offset
= layout
->binding
[binding
].offset
;
1295 LLVMValueRef offset
, stride
;
1297 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1298 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1299 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1300 layout
->binding
[binding
].dynamic_offset_offset
;
1301 desc_ptr
= ctx
->abi
.push_constants
;
1302 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1303 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1305 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1307 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
1309 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1310 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
1313 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
1314 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1315 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1317 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1318 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1319 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1320 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1321 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1322 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1323 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1325 LLVMValueRef desc_components
[4] = {
1326 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
1327 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
), false),
1328 /* High limit to support variable sizes. */
1329 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
1330 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
1333 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
1340 /* The offchip buffer layout for TCS->TES is
1342 * - attribute 0 of patch 0 vertex 0
1343 * - attribute 0 of patch 0 vertex 1
1344 * - attribute 0 of patch 0 vertex 2
1346 * - attribute 0 of patch 1 vertex 0
1347 * - attribute 0 of patch 1 vertex 1
1349 * - attribute 1 of patch 0 vertex 0
1350 * - attribute 1 of patch 0 vertex 1
1352 * - per patch attribute 0 of patch 0
1353 * - per patch attribute 0 of patch 1
1356 * Note that every attribute has 4 components.
1358 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1360 uint32_t num_patches
= ctx
->tcs_num_patches
;
1361 uint32_t num_tcs_outputs
;
1362 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1363 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
1365 num_tcs_outputs
= ctx
->options
->key
.tes
.tcs_num_outputs
;
1367 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1368 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
1370 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1373 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1374 LLVMValueRef vertex_index
)
1376 LLVMValueRef param_stride
;
1378 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
* ctx
->tcs_num_patches
, false);
1380 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1381 return param_stride
;
1384 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1385 LLVMValueRef vertex_index
,
1386 LLVMValueRef param_index
)
1388 LLVMValueRef base_addr
;
1389 LLVMValueRef param_stride
, constant16
;
1390 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1391 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
1392 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1393 param_stride
= calc_param_stride(ctx
, vertex_index
);
1395 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
1396 vertices_per_patch
, vertex_index
);
1398 base_addr
= rel_patch_id
;
1401 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1402 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1403 param_stride
, ""), "");
1405 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1407 if (!vertex_index
) {
1408 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1410 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1411 patch_data_offset
, "");
1416 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1418 unsigned const_index
,
1420 LLVMValueRef vertex_index
,
1421 LLVMValueRef indir_index
)
1423 LLVMValueRef param_index
;
1426 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1429 if (const_index
&& !is_compact
)
1430 param
+= const_index
;
1431 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1433 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1437 get_dw_address(struct radv_shader_context
*ctx
,
1438 LLVMValueRef dw_addr
,
1440 unsigned const_index
,
1441 bool compact_const_index
,
1442 LLVMValueRef vertex_index
,
1443 LLVMValueRef stride
,
1444 LLVMValueRef indir_index
)
1449 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1450 LLVMBuildMul(ctx
->ac
.builder
,
1456 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1457 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1458 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1459 else if (const_index
&& !compact_const_index
)
1460 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1461 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1463 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1464 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1466 if (const_index
&& compact_const_index
)
1467 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1468 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1473 load_tcs_varyings(struct ac_shader_abi
*abi
,
1475 LLVMValueRef vertex_index
,
1476 LLVMValueRef indir_index
,
1477 unsigned const_index
,
1479 unsigned driver_location
,
1481 unsigned num_components
,
1486 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1487 LLVMValueRef dw_addr
, stride
;
1488 LLVMValueRef value
[4], result
;
1489 unsigned param
= shader_io_get_unique_index(location
);
1492 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1493 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1494 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1497 stride
= get_tcs_out_vertex_stride(ctx
);
1498 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1500 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1505 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1508 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1509 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1510 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1513 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1518 store_tcs_output(struct ac_shader_abi
*abi
,
1519 const nir_variable
*var
,
1520 LLVMValueRef vertex_index
,
1521 LLVMValueRef param_index
,
1522 unsigned const_index
,
1526 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1527 const unsigned location
= var
->data
.location
;
1528 unsigned component
= var
->data
.location_frac
;
1529 const bool is_patch
= var
->data
.patch
;
1530 const bool is_compact
= var
->data
.compact
;
1531 LLVMValueRef dw_addr
;
1532 LLVMValueRef stride
= NULL
;
1533 LLVMValueRef buf_addr
= NULL
;
1535 bool store_lds
= true;
1538 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1541 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
1545 param
= shader_io_get_unique_index(location
);
1546 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1547 const_index
+= component
;
1550 if (const_index
>= 4) {
1557 stride
= get_tcs_out_vertex_stride(ctx
);
1558 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1560 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1563 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1565 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1566 vertex_index
, param_index
);
1568 bool is_tess_factor
= false;
1569 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1570 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1571 is_tess_factor
= true;
1573 unsigned base
= is_compact
? const_index
: 0;
1574 for (unsigned chan
= 0; chan
< 8; chan
++) {
1575 if (!(writemask
& (1 << chan
)))
1577 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1578 value
= ac_to_integer(&ctx
->ac
, value
);
1579 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
1581 if (store_lds
|| is_tess_factor
) {
1582 LLVMValueRef dw_addr_chan
=
1583 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1584 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1585 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1588 if (!is_tess_factor
&& writemask
!= 0xF)
1589 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1590 buf_addr
, ctx
->oc_lds
,
1591 4 * (base
+ chan
), ac_glc
, false);
1594 if (writemask
== 0xF) {
1595 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1596 buf_addr
, ctx
->oc_lds
,
1597 (base
* 4), ac_glc
, false);
1602 load_tes_input(struct ac_shader_abi
*abi
,
1604 LLVMValueRef vertex_index
,
1605 LLVMValueRef param_index
,
1606 unsigned const_index
,
1608 unsigned driver_location
,
1610 unsigned num_components
,
1615 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1616 LLVMValueRef buf_addr
;
1617 LLVMValueRef result
;
1618 unsigned param
= shader_io_get_unique_index(location
);
1620 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1621 const_index
+= component
;
1623 if (const_index
>= 4) {
1629 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1630 is_compact
, vertex_index
, param_index
);
1632 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1633 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1635 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1636 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
1637 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1642 load_gs_input(struct ac_shader_abi
*abi
,
1644 unsigned driver_location
,
1646 unsigned num_components
,
1647 unsigned vertex_index
,
1648 unsigned const_index
,
1651 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1652 LLVMValueRef vtx_offset
;
1653 unsigned param
, vtx_offset_param
;
1654 LLVMValueRef value
[4], result
;
1656 vtx_offset_param
= vertex_index
;
1657 assert(vtx_offset_param
< 6);
1658 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1659 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1661 param
= shader_io_get_unique_index(location
);
1663 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1664 if (ctx
->ac
.chip_class
>= GFX9
) {
1665 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1666 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1667 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1668 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1670 LLVMValueRef soffset
=
1671 LLVMConstInt(ctx
->ac
.i32
,
1672 (param
* 4 + i
+ const_index
) * 256,
1675 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1678 vtx_offset
, soffset
,
1679 0, ac_glc
, true, false);
1682 if (ac_get_type_size(type
) == 2) {
1683 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
1684 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
1686 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
1688 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1689 result
= ac_to_integer(&ctx
->ac
, result
);
1694 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1696 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1697 ac_build_kill_if_false(&ctx
->ac
, visible
);
1700 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
1701 enum glsl_interp_mode interp
, unsigned location
)
1703 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1706 case INTERP_MODE_FLAT
:
1709 case INTERP_MODE_SMOOTH
:
1710 case INTERP_MODE_NONE
:
1711 if (location
== INTERP_CENTER
)
1712 return ctx
->persp_center
;
1713 else if (location
== INTERP_CENTROID
)
1714 return ctx
->persp_centroid
;
1715 else if (location
== INTERP_SAMPLE
)
1716 return ctx
->persp_sample
;
1718 case INTERP_MODE_NOPERSPECTIVE
:
1719 if (location
== INTERP_CENTER
)
1720 return ctx
->linear_center
;
1721 else if (location
== INTERP_CENTROID
)
1722 return ctx
->linear_centroid
;
1723 else if (location
== INTERP_SAMPLE
)
1724 return ctx
->linear_sample
;
1731 radv_get_sample_pos_offset(uint32_t num_samples
)
1733 uint32_t sample_pos_offset
= 0;
1735 switch (num_samples
) {
1737 sample_pos_offset
= 1;
1740 sample_pos_offset
= 3;
1743 sample_pos_offset
= 7;
1748 return sample_pos_offset
;
1751 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1752 LLVMValueRef sample_id
)
1754 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1756 LLVMValueRef result
;
1757 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
1758 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
1760 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1761 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1763 uint32_t sample_pos_offset
=
1764 radv_get_sample_pos_offset(ctx
->options
->key
.fs
.num_samples
);
1767 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
1768 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
1769 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1775 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1777 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1778 uint8_t log2_ps_iter_samples
;
1780 if (ctx
->shader_info
->info
.ps
.force_persample
) {
1781 log2_ps_iter_samples
=
1782 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
1784 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
1787 /* The bit pattern matches that used by fixed function fragment
1789 static const uint16_t ps_iter_masks
[] = {
1790 0xffff, /* not used */
1796 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1798 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1800 LLVMValueRef result
, sample_id
;
1801 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
1802 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1803 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
1809 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1811 LLVMValueRef gs_next_vertex
;
1812 LLVMValueRef can_emit
;
1813 unsigned offset
= 0;
1814 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1816 /* Write vertex attribute values to GSVS ring */
1817 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1818 ctx
->gs_next_vertex
[stream
],
1821 /* If this thread has already emitted the declared maximum number of
1822 * vertices, kill it: excessive vertex emissions are not supposed to
1823 * have any effect, and GS threads have no externally observable
1824 * effects other than emitting vertices.
1826 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1827 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
1828 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1830 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1831 unsigned output_usage_mask
=
1832 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
1833 uint8_t output_stream
=
1834 ctx
->shader_info
->info
.gs
.output_streams
[i
];
1835 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1836 int length
= util_last_bit(output_usage_mask
);
1838 if (!(ctx
->output_mask
& (1ull << i
)) ||
1839 output_stream
!= stream
)
1842 for (unsigned j
= 0; j
< length
; j
++) {
1843 if (!(output_usage_mask
& (1 << j
)))
1846 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1848 LLVMValueRef voffset
=
1849 LLVMConstInt(ctx
->ac
.i32
, offset
*
1850 ctx
->gs_max_out_vertices
, false);
1854 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1855 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1857 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1858 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1860 ac_build_buffer_store_dword(&ctx
->ac
,
1861 ctx
->gsvs_ring
[stream
],
1863 voffset
, ctx
->gs2vs_offset
, 0,
1864 ac_glc
| ac_slc
, true);
1868 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1870 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1872 ac_build_sendmsg(&ctx
->ac
,
1873 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1878 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1880 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1881 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1885 load_tess_coord(struct ac_shader_abi
*abi
)
1887 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1889 LLVMValueRef coord
[4] = {
1896 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
1897 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1898 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1900 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1904 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1906 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1907 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
1911 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1913 return abi
->base_vertex
;
1916 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1917 LLVMValueRef buffer_ptr
, bool write
)
1919 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1920 LLVMValueRef result
;
1922 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1924 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1925 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1930 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1932 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1933 LLVMValueRef result
;
1935 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
1936 /* Do not load the descriptor for inlined uniform blocks. */
1940 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1942 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1943 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1948 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1949 unsigned descriptor_set
,
1950 unsigned base_index
,
1951 unsigned constant_index
,
1953 enum ac_descriptor_type desc_type
,
1954 bool image
, bool write
,
1957 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1958 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1959 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
1960 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1961 unsigned offset
= binding
->offset
;
1962 unsigned stride
= binding
->size
;
1964 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1967 assert(base_index
< layout
->binding_count
);
1969 switch (desc_type
) {
1971 type
= ctx
->ac
.v8i32
;
1975 type
= ctx
->ac
.v8i32
;
1979 case AC_DESC_SAMPLER
:
1980 type
= ctx
->ac
.v4i32
;
1981 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
1982 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
1987 case AC_DESC_BUFFER
:
1988 type
= ctx
->ac
.v4i32
;
1991 case AC_DESC_PLANE_0
:
1992 case AC_DESC_PLANE_1
:
1993 case AC_DESC_PLANE_2
:
1994 type
= ctx
->ac
.v8i32
;
1996 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
1999 unreachable("invalid desc_type\n");
2002 offset
+= constant_index
* stride
;
2004 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
2005 (!index
|| binding
->immutable_samplers_equal
)) {
2006 if (binding
->immutable_samplers_equal
)
2009 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
2011 LLVMValueRef constants
[] = {
2012 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
2013 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
2014 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
2015 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
2017 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
2020 assert(stride
% type_size
== 0);
2022 LLVMValueRef adjusted_index
= index
;
2023 if (!adjusted_index
)
2024 adjusted_index
= ctx
->ac
.i32_0
;
2026 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
2028 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
2029 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
2030 list
= LLVMBuildPointerCast(builder
, list
,
2031 ac_array_in_const32_addr_space(type
), "");
2033 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
2035 /* 3 plane formats always have same size and format for plane 1 & 2, so
2036 * use the tail from plane 1 so that we can store only the first 16 bytes
2037 * of the last plane. */
2038 if (desc_type
== AC_DESC_PLANE_2
) {
2039 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
2041 LLVMValueRef components
[8];
2042 for (unsigned i
= 0; i
< 4; ++i
)
2043 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
2045 for (unsigned i
= 4; i
< 8; ++i
)
2046 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
2047 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
2053 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
2054 * so we may need to fix it up. */
2056 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
2057 unsigned adjustment
,
2060 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
2063 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
2065 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2067 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
2068 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2070 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
2072 /* For the integer-like cases, do a natural sign extension.
2074 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2075 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2078 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
2079 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
2080 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
2081 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
2083 /* Convert back to the right type. */
2084 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
2086 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
2087 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2088 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
2089 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
2090 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
2091 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2094 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2098 get_num_channels_from_data_format(unsigned data_format
)
2100 switch (data_format
) {
2101 case V_008F0C_BUF_DATA_FORMAT_8
:
2102 case V_008F0C_BUF_DATA_FORMAT_16
:
2103 case V_008F0C_BUF_DATA_FORMAT_32
:
2105 case V_008F0C_BUF_DATA_FORMAT_8_8
:
2106 case V_008F0C_BUF_DATA_FORMAT_16_16
:
2107 case V_008F0C_BUF_DATA_FORMAT_32_32
:
2109 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
2110 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
2111 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
2113 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
2114 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
2115 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
2116 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
2117 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
2127 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
2129 unsigned num_channels
,
2132 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
2133 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
2134 LLVMValueRef chan
[4];
2136 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
2137 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
2139 if (num_channels
== 4 && num_channels
== vec_size
)
2142 num_channels
= MIN2(num_channels
, vec_size
);
2144 for (unsigned i
= 0; i
< num_channels
; i
++)
2145 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
2148 assert(num_channels
== 1);
2153 for (unsigned i
= num_channels
; i
< 4; i
++) {
2154 chan
[i
] = i
== 3 ? one
: zero
;
2155 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
2158 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
2162 handle_vs_input_decl(struct radv_shader_context
*ctx
,
2163 struct nir_variable
*variable
)
2165 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
2166 LLVMValueRef t_offset
;
2167 LLVMValueRef t_list
;
2169 LLVMValueRef buffer_index
;
2170 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
2171 uint8_t input_usage_mask
=
2172 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
2173 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
2175 variable
->data
.driver_location
= variable
->data
.location
* 4;
2177 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
2178 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
2179 LLVMValueRef output
[4];
2180 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
2181 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
2182 unsigned data_format
= attrib_format
& 0x0f;
2183 unsigned num_format
= (attrib_format
>> 4) & 0x07;
2184 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
2185 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
2187 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
2188 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
2191 buffer_index
= ctx
->abi
.instance_id
;
2194 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
2195 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
2198 buffer_index
= ctx
->ac
.i32_0
;
2201 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.start_instance
, buffer_index
, "");
2203 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
2204 ctx
->abi
.base_vertex
, "");
2206 /* Adjust the number of channels to load based on the vertex
2209 unsigned num_format_channels
= get_num_channels_from_data_format(data_format
);
2210 unsigned num_channels
= MIN2(num_input_channels
, num_format_channels
);
2211 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
2212 unsigned attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
2213 unsigned attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
2215 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2216 /* Always load, at least, 3 channels for formats that
2217 * need to be shuffled because X<->Z.
2219 num_channels
= MAX2(num_channels
, 3);
2222 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
2223 LLVMValueRef buffer_offset
=
2224 LLVMConstInt(ctx
->ac
.i32
,
2225 attrib_offset
/ attrib_stride
, false);
2227 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
2231 attrib_offset
= attrib_offset
% attrib_stride
;
2234 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
2235 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
2237 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
2239 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
2240 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
2242 data_format
, num_format
, 0, true);
2244 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2246 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
2247 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
2248 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
2249 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
2251 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
2254 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
2257 for (unsigned chan
= 0; chan
< 4; chan
++) {
2258 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2259 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
2260 if (type
== GLSL_TYPE_FLOAT16
) {
2261 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
2262 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
2266 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
2267 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
2269 for (unsigned chan
= 0; chan
< 4; chan
++) {
2270 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
2271 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
2272 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
2274 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
2279 static void interp_fs_input(struct radv_shader_context
*ctx
,
2281 LLVMValueRef interp_param
,
2282 LLVMValueRef prim_mask
,
2284 LLVMValueRef result
[4])
2286 LLVMValueRef attr_number
;
2289 bool interp
= !LLVMIsUndef(interp_param
);
2291 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
2293 /* fs.constant returns the param from the middle vertex, so it's not
2294 * really useful for flat shading. It's meant to be used for custom
2295 * interpolation (but the intrinsic can't fetch from the other two
2298 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2299 * to do the right thing. The only reason we use fs.constant is that
2300 * fs.interp cannot be used on integers, because they can be equal
2304 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
2307 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
2309 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
2313 for (chan
= 0; chan
< 4; chan
++) {
2314 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2316 if (interp
&& float16
) {
2317 result
[chan
] = ac_build_fs_interp_f16(&ctx
->ac
,
2321 } else if (interp
) {
2322 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
2327 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
2328 LLVMConstInt(ctx
->ac
.i32
, 2, false),
2332 result
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, result
[chan
], ctx
->ac
.i32
, "");
2333 result
[chan
] = LLVMBuildTruncOrBitCast(ctx
->ac
.builder
, result
[chan
], float16
? ctx
->ac
.i16
: ctx
->ac
.i32
, "");
2338 static void mark_16bit_fs_input(struct radv_shader_context
*ctx
,
2339 const struct glsl_type
*type
,
2342 if (glsl_type_is_scalar(type
) || glsl_type_is_vector(type
) || glsl_type_is_matrix(type
)) {
2343 unsigned attrib_count
= glsl_count_attribute_slots(type
, false);
2344 if (glsl_type_is_16bit(type
)) {
2345 ctx
->float16_shaded_mask
|= ((1ull << attrib_count
) - 1) << location
;
2347 } else if (glsl_type_is_array(type
)) {
2348 unsigned stride
= glsl_count_attribute_slots(glsl_get_array_element(type
), false);
2349 for (unsigned i
= 0; i
< glsl_get_length(type
); ++i
) {
2350 mark_16bit_fs_input(ctx
, glsl_get_array_element(type
), location
+ i
* stride
);
2353 assert(glsl_type_is_struct_or_ifc(type
));
2354 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
2355 mark_16bit_fs_input(ctx
, glsl_get_struct_field(type
, i
), location
);
2356 location
+= glsl_count_attribute_slots(glsl_get_struct_field(type
, i
), false);
2362 handle_fs_input_decl(struct radv_shader_context
*ctx
,
2363 struct nir_variable
*variable
)
2365 int idx
= variable
->data
.location
;
2366 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2367 LLVMValueRef interp
= NULL
;
2370 variable
->data
.driver_location
= idx
* 4;
2373 if (variable
->data
.compact
) {
2374 unsigned component_count
= variable
->data
.location_frac
+
2375 glsl_get_length(variable
->type
);
2376 attrib_count
= (component_count
+ 3) / 4;
2378 mark_16bit_fs_input(ctx
, variable
->type
, idx
);
2380 mask
= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
2382 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
||
2383 glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT16
||
2384 glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_STRUCT
) {
2385 unsigned interp_type
;
2386 if (variable
->data
.sample
)
2387 interp_type
= INTERP_SAMPLE
;
2388 else if (variable
->data
.centroid
)
2389 interp_type
= INTERP_CENTROID
;
2391 interp_type
= INTERP_CENTER
;
2393 interp
= lookup_interp_param(&ctx
->abi
, variable
->data
.interpolation
, interp_type
);
2396 interp
= LLVMGetUndef(ctx
->ac
.i32
);
2398 for (unsigned i
= 0; i
< attrib_count
; ++i
)
2399 ctx
->inputs
[ac_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
2401 ctx
->input_mask
|= mask
;
2405 handle_vs_inputs(struct radv_shader_context
*ctx
,
2406 struct nir_shader
*nir
) {
2407 nir_foreach_variable(variable
, &nir
->inputs
)
2408 handle_vs_input_decl(ctx
, variable
);
2412 prepare_interp_optimize(struct radv_shader_context
*ctx
,
2413 struct nir_shader
*nir
)
2415 bool uses_center
= false;
2416 bool uses_centroid
= false;
2417 nir_foreach_variable(variable
, &nir
->inputs
) {
2418 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
2419 variable
->data
.sample
)
2422 if (variable
->data
.centroid
)
2423 uses_centroid
= true;
2428 if (uses_center
&& uses_centroid
) {
2429 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
2430 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
2431 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
2436 handle_fs_inputs(struct radv_shader_context
*ctx
,
2437 struct nir_shader
*nir
)
2439 prepare_interp_optimize(ctx
, nir
);
2441 nir_foreach_variable(variable
, &nir
->inputs
)
2442 handle_fs_input_decl(ctx
, variable
);
2446 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
2447 ctx
->shader_info
->info
.needs_multiview_view_index
) {
2448 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
2449 ctx
->inputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)] = LLVMGetUndef(ctx
->ac
.i32
);
2452 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
2453 LLVMValueRef interp_param
;
2454 LLVMValueRef
*inputs
= ctx
->inputs
+ac_llvm_reg_index_soa(i
, 0);
2456 if (!(ctx
->input_mask
& (1ull << i
)))
2459 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
2460 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
2461 interp_param
= *inputs
;
2462 bool float16
= (ctx
->float16_shaded_mask
>> i
) & 1;
2463 interp_fs_input(ctx
, index
, interp_param
, ctx
->abi
.prim_mask
, float16
,
2466 if (LLVMIsUndef(interp_param
))
2467 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
2469 ctx
->shader_info
->fs
.float16_shaded_mask
|= 1u << index
;
2470 if (i
>= VARYING_SLOT_VAR0
)
2471 ctx
->abi
.fs_input_attr_indices
[i
- VARYING_SLOT_VAR0
] = index
;
2473 } else if (i
== VARYING_SLOT_CLIP_DIST0
) {
2474 int length
= ctx
->shader_info
->info
.ps
.num_input_clips_culls
;
2476 for (unsigned j
= 0; j
< length
; j
+= 4) {
2477 inputs
= ctx
->inputs
+ ac_llvm_reg_index_soa(i
, j
);
2479 interp_param
= *inputs
;
2480 interp_fs_input(ctx
, index
, interp_param
,
2481 ctx
->abi
.prim_mask
, false, inputs
);
2484 } else if (i
== VARYING_SLOT_POS
) {
2485 for(int i
= 0; i
< 3; ++i
)
2486 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
2488 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
2489 ctx
->abi
.frag_pos
[3]);
2492 ctx
->shader_info
->fs
.num_interp
= index
;
2493 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
2495 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
2496 ctx
->abi
.view_index
= ctx
->inputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2500 scan_shader_output_decl(struct radv_shader_context
*ctx
,
2501 struct nir_variable
*variable
,
2502 struct nir_shader
*shader
,
2503 gl_shader_stage stage
)
2505 int idx
= variable
->data
.location
+ variable
->data
.index
;
2506 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2507 uint64_t mask_attribs
;
2509 variable
->data
.driver_location
= idx
* 4;
2511 /* tess ctrl has it's own load/store paths for outputs */
2512 if (stage
== MESA_SHADER_TESS_CTRL
)
2515 if (variable
->data
.compact
) {
2516 unsigned component_count
= variable
->data
.location_frac
+
2517 glsl_get_length(variable
->type
);
2518 attrib_count
= (component_count
+ 3) / 4;
2521 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2522 if (stage
== MESA_SHADER_VERTEX
||
2523 stage
== MESA_SHADER_TESS_EVAL
||
2524 stage
== MESA_SHADER_GEOMETRY
) {
2525 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2526 if (stage
== MESA_SHADER_VERTEX
) {
2527 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2528 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2529 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2531 if (stage
== MESA_SHADER_TESS_EVAL
) {
2532 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2533 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2534 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2539 ctx
->output_mask
|= mask_attribs
;
2543 /* Initialize arguments for the shader export intrinsic */
2545 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2546 LLVMValueRef
*values
,
2547 unsigned enabled_channels
,
2549 struct ac_export_args
*args
)
2551 /* Specify the channels that are enabled. */
2552 args
->enabled_channels
= enabled_channels
;
2554 /* Specify whether the EXEC mask represents the valid mask */
2555 args
->valid_mask
= 0;
2557 /* Specify whether this is the last export */
2560 /* Specify the target we are exporting */
2561 args
->target
= target
;
2563 args
->compr
= false;
2564 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2565 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2566 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2567 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2572 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
2573 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2574 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2575 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2576 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2577 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2580 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2581 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2582 unsigned bits
, bool hi
) = NULL
;
2584 switch(col_format
) {
2585 case V_028714_SPI_SHADER_ZERO
:
2586 args
->enabled_channels
= 0; /* writemask */
2587 args
->target
= V_008DFC_SQ_EXP_NULL
;
2590 case V_028714_SPI_SHADER_32_R
:
2591 args
->enabled_channels
= 1;
2592 args
->out
[0] = values
[0];
2595 case V_028714_SPI_SHADER_32_GR
:
2596 args
->enabled_channels
= 0x3;
2597 args
->out
[0] = values
[0];
2598 args
->out
[1] = values
[1];
2601 case V_028714_SPI_SHADER_32_AR
:
2602 if (ctx
->ac
.chip_class
>= GFX10
) {
2603 args
->enabled_channels
= 0x3;
2604 args
->out
[0] = values
[0];
2605 args
->out
[1] = values
[3];
2607 args
->enabled_channels
= 0x9;
2608 args
->out
[0] = values
[0];
2609 args
->out
[3] = values
[3];
2613 case V_028714_SPI_SHADER_FP16_ABGR
:
2614 args
->enabled_channels
= 0x5;
2615 packf
= ac_build_cvt_pkrtz_f16
;
2617 for (unsigned chan
= 0; chan
< 4; chan
++)
2618 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
2624 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2625 args
->enabled_channels
= 0x5;
2626 packf
= ac_build_cvt_pknorm_u16
;
2629 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2630 args
->enabled_channels
= 0x5;
2631 packf
= ac_build_cvt_pknorm_i16
;
2634 case V_028714_SPI_SHADER_UINT16_ABGR
:
2635 args
->enabled_channels
= 0x5;
2636 packi
= ac_build_cvt_pk_u16
;
2638 for (unsigned chan
= 0; chan
< 4; chan
++)
2639 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
2640 ac_to_integer(&ctx
->ac
, values
[chan
]),
2645 case V_028714_SPI_SHADER_SINT16_ABGR
:
2646 args
->enabled_channels
= 0x5;
2647 packi
= ac_build_cvt_pk_i16
;
2649 for (unsigned chan
= 0; chan
< 4; chan
++)
2650 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
2651 ac_to_integer(&ctx
->ac
, values
[chan
]),
2657 case V_028714_SPI_SHADER_32_ABGR
:
2658 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2662 /* Pack f16 or norm_i16/u16. */
2664 for (chan
= 0; chan
< 2; chan
++) {
2665 LLVMValueRef pack_args
[2] = {
2667 values
[2 * chan
+ 1]
2669 LLVMValueRef packed
;
2671 packed
= packf(&ctx
->ac
, pack_args
);
2672 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2674 args
->compr
= 1; /* COMPR flag */
2679 for (chan
= 0; chan
< 2; chan
++) {
2680 LLVMValueRef pack_args
[2] = {
2681 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2682 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2684 LLVMValueRef packed
;
2686 packed
= packi(&ctx
->ac
, pack_args
,
2687 is_int8
? 8 : is_int10
? 10 : 16,
2689 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2691 args
->compr
= 1; /* COMPR flag */
2697 for (unsigned chan
= 0; chan
< 4; chan
++) {
2698 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
2699 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
2702 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2704 for (unsigned i
= 0; i
< 4; ++i
)
2705 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2709 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2710 LLVMValueRef
*values
, unsigned enabled_channels
)
2712 struct ac_export_args args
;
2714 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2715 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2716 ac_build_export(&ctx
->ac
, &args
);
2720 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2722 LLVMValueRef output
=
2723 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2725 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2729 radv_emit_stream_output(struct radv_shader_context
*ctx
,
2730 LLVMValueRef
const *so_buffers
,
2731 LLVMValueRef
const *so_write_offsets
,
2732 const struct radv_stream_output
*output
)
2734 unsigned num_comps
= util_bitcount(output
->component_mask
);
2735 unsigned loc
= output
->location
;
2736 unsigned buf
= output
->buffer
;
2737 unsigned offset
= output
->offset
;
2739 LLVMValueRef out
[4];
2741 assert(num_comps
&& num_comps
<= 4);
2742 if (!num_comps
|| num_comps
> 4)
2745 /* Get the first component. */
2746 start
= ffs(output
->component_mask
) - 1;
2748 /* Load the output as int. */
2749 for (int i
= 0; i
< num_comps
; i
++) {
2750 out
[i
] = ac_to_integer(&ctx
->ac
,
2751 radv_load_output(ctx
, loc
, start
+ i
));
2754 /* Pack the output. */
2755 LLVMValueRef vdata
= NULL
;
2757 switch (num_comps
) {
2758 case 1: /* as i32 */
2761 case 2: /* as v2i32 */
2762 case 3: /* as v4i32 (aligned to 4) */
2763 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
2765 case 4: /* as v4i32 */
2766 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
2767 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
2768 util_next_power_of_two(num_comps
) :
2773 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
2774 vdata
, num_comps
, so_write_offsets
[buf
],
2775 ctx
->ac
.i32_0
, offset
,
2776 ac_glc
| ac_slc
, false);
2780 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
2782 struct ac_build_if_state if_ctx
;
2785 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2786 assert(ctx
->streamout_config
);
2787 LLVMValueRef so_vtx_count
=
2788 ac_build_bfe(&ctx
->ac
, ctx
->streamout_config
,
2789 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2790 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
2792 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2794 /* can_emit = tid < so_vtx_count; */
2795 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
2796 tid
, so_vtx_count
, "");
2798 /* Emit the streamout code conditionally. This actually avoids
2799 * out-of-bounds buffer access. The hw tells us via the SGPR
2800 * (so_vtx_count) which threads are allowed to emit streamout data.
2802 ac_nir_build_if(&if_ctx
, ctx
, can_emit
);
2804 /* The buffer offset is computed as follows:
2805 * ByteOffset = streamout_offset[buffer_id]*4 +
2806 * (streamout_write_index + thread_id)*stride[buffer_id] +
2809 LLVMValueRef so_write_index
= ctx
->streamout_write_idx
;
2811 /* Compute (streamout_write_index + thread_id). */
2813 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
2815 /* Load the descriptor and compute the write offset for each
2818 LLVMValueRef so_write_offset
[4] = {};
2819 LLVMValueRef so_buffers
[4] = {};
2820 LLVMValueRef buf_ptr
= ctx
->streamout_buffers
;
2822 for (i
= 0; i
< 4; i
++) {
2823 uint16_t stride
= ctx
->shader_info
->info
.so
.strides
[i
];
2828 LLVMValueRef offset
=
2829 LLVMConstInt(ctx
->ac
.i32
, i
, false);
2831 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
2834 LLVMValueRef so_offset
= ctx
->streamout_offset
[i
];
2836 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
2837 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2839 so_write_offset
[i
] =
2840 ac_build_imad(&ctx
->ac
, so_write_index
,
2841 LLVMConstInt(ctx
->ac
.i32
,
2846 /* Write streamout data. */
2847 for (i
= 0; i
< ctx
->shader_info
->info
.so
.num_outputs
; i
++) {
2848 struct radv_stream_output
*output
=
2849 &ctx
->shader_info
->info
.so
.outputs
[i
];
2851 if (stream
!= output
->stream
)
2854 radv_emit_stream_output(ctx
, so_buffers
,
2855 so_write_offset
, output
);
2858 ac_nir_build_endif(&if_ctx
);
2862 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2863 bool export_prim_id
, bool export_layer_id
,
2864 bool export_clip_dists
,
2865 struct radv_vs_output_info
*outinfo
)
2867 uint32_t param_count
= 0;
2869 unsigned pos_idx
, num_pos_exports
= 0;
2870 struct ac_export_args args
, pos_args
[4] = {};
2871 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2874 if (ctx
->options
->key
.has_multiview_view_index
) {
2875 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2877 for(unsigned i
= 0; i
< 4; ++i
)
2878 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2879 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2882 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
2883 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2886 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2887 sizeof(outinfo
->vs_output_param_offset
));
2889 for(unsigned location
= VARYING_SLOT_CLIP_DIST0
; location
<= VARYING_SLOT_CLIP_DIST1
; ++location
) {
2890 if (ctx
->output_mask
& (1ull << location
)) {
2891 unsigned output_usage_mask
, length
;
2892 LLVMValueRef slots
[4];
2895 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2896 !ctx
->is_gs_copy_shader
) {
2898 ctx
->shader_info
->info
.vs
.output_usage_mask
[location
];
2899 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2901 ctx
->shader_info
->info
.tes
.output_usage_mask
[location
];
2903 assert(ctx
->is_gs_copy_shader
);
2905 ctx
->shader_info
->info
.gs
.output_usage_mask
[location
];
2908 length
= util_last_bit(output_usage_mask
);
2910 for (j
= 0; j
< length
; j
++)
2911 slots
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, location
, j
));
2913 for (i
= length
; i
< 4; i
++)
2914 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
2916 target
= V_008DFC_SQ_EXP_POS
+ 2 + (location
- VARYING_SLOT_CLIP_DIST0
);
2917 si_llvm_init_export_args(ctx
, &slots
[0], 0xf, target
, &args
);
2918 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2919 &args
, sizeof(args
));
2921 if (export_clip_dists
) {
2922 /* Export the clip/cull distances values to the next stage. */
2923 radv_export_param(ctx
, param_count
, &slots
[0], 0xf);
2924 outinfo
->vs_output_param_offset
[location
] = param_count
++;
2929 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
2930 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
2931 for (unsigned j
= 0; j
< 4; j
++)
2932 pos_values
[j
] = radv_load_output(ctx
, VARYING_SLOT_POS
, j
);
2934 si_llvm_init_export_args(ctx
, pos_values
, 0xf, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2936 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
2937 outinfo
->writes_pointsize
= true;
2938 psize_value
= radv_load_output(ctx
, VARYING_SLOT_PSIZ
, 0);
2941 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
2942 outinfo
->writes_layer
= true;
2943 layer_value
= radv_load_output(ctx
, VARYING_SLOT_LAYER
, 0);
2946 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
2947 outinfo
->writes_viewport_index
= true;
2948 viewport_index_value
= radv_load_output(ctx
, VARYING_SLOT_VIEWPORT
, 0);
2951 if (ctx
->shader_info
->info
.so
.num_outputs
&&
2952 !ctx
->is_gs_copy_shader
) {
2953 /* The GS copy shader emission already emits streamout. */
2954 radv_emit_streamout(ctx
, 0);
2957 if (outinfo
->writes_pointsize
||
2958 outinfo
->writes_layer
||
2959 outinfo
->writes_viewport_index
) {
2960 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2961 (outinfo
->writes_layer
== true ? 4 : 0));
2962 pos_args
[1].valid_mask
= 0;
2963 pos_args
[1].done
= 0;
2964 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2965 pos_args
[1].compr
= 0;
2966 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2967 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2968 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2969 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2971 if (outinfo
->writes_pointsize
== true)
2972 pos_args
[1].out
[0] = psize_value
;
2973 if (outinfo
->writes_layer
== true)
2974 pos_args
[1].out
[2] = layer_value
;
2975 if (outinfo
->writes_viewport_index
== true) {
2976 if (ctx
->options
->chip_class
>= GFX9
) {
2977 /* GFX9 has the layer in out.z[10:0] and the viewport
2978 * index in out.z[19:16].
2980 LLVMValueRef v
= viewport_index_value
;
2981 v
= ac_to_integer(&ctx
->ac
, v
);
2982 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2983 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2985 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2986 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2988 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2989 pos_args
[1].enabled_channels
|= 1 << 2;
2991 pos_args
[1].out
[3] = viewport_index_value
;
2992 pos_args
[1].enabled_channels
|= 1 << 3;
2996 for (i
= 0; i
< 4; i
++) {
2997 if (pos_args
[i
].out
[0])
3001 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
3002 * Setting valid_mask=1 prevents it and has no other effect.
3004 if (ctx
->ac
.family
== CHIP_NAVI10
||
3005 ctx
->ac
.family
== CHIP_NAVI12
||
3006 ctx
->ac
.family
== CHIP_NAVI14
)
3007 pos_args
[0].valid_mask
= 1;
3010 for (i
= 0; i
< 4; i
++) {
3011 if (!pos_args
[i
].out
[0])
3014 /* Specify the target we are exporting */
3015 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
3016 if (pos_idx
== num_pos_exports
)
3017 pos_args
[i
].done
= 1;
3018 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
3021 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3022 LLVMValueRef values
[4];
3023 if (!(ctx
->output_mask
& (1ull << i
)))
3026 if (i
!= VARYING_SLOT_LAYER
&&
3027 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
3028 i
< VARYING_SLOT_VAR0
)
3031 for (unsigned j
= 0; j
< 4; j
++)
3032 values
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
3034 unsigned output_usage_mask
;
3036 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
3037 !ctx
->is_gs_copy_shader
) {
3039 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
3040 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3042 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
3044 assert(ctx
->is_gs_copy_shader
);
3046 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
3049 radv_export_param(ctx
, param_count
, values
, output_usage_mask
);
3051 outinfo
->vs_output_param_offset
[i
] = param_count
++;
3054 if (export_prim_id
) {
3055 LLVMValueRef values
[4];
3057 values
[0] = ctx
->vs_prim_id
;
3058 for (unsigned j
= 1; j
< 4; j
++)
3059 values
[j
] = ctx
->ac
.f32_0
;
3061 radv_export_param(ctx
, param_count
, values
, 0x1);
3063 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
3064 outinfo
->export_prim_id
= true;
3067 if (export_layer_id
&& layer_value
) {
3068 LLVMValueRef values
[4];
3070 values
[0] = layer_value
;
3071 for (unsigned j
= 1; j
< 4; j
++)
3072 values
[j
] = ctx
->ac
.f32_0
;
3074 radv_export_param(ctx
, param_count
, values
, 0x1);
3076 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
++;
3079 outinfo
->pos_exports
= num_pos_exports
;
3080 outinfo
->param_exports
= param_count
;
3084 handle_es_outputs_post(struct radv_shader_context
*ctx
,
3085 struct radv_es_output_info
*outinfo
)
3088 uint64_t max_output_written
= 0;
3089 LLVMValueRef lds_base
= NULL
;
3091 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3094 if (!(ctx
->output_mask
& (1ull << i
)))
3097 param_index
= shader_io_get_unique_index(i
);
3099 max_output_written
= MAX2(param_index
, max_output_written
);
3102 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
3104 if (ctx
->ac
.chip_class
>= GFX9
) {
3105 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
3106 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
3107 LLVMValueRef wave_idx
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
3108 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
3109 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
3110 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
3111 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
3112 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
3115 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3116 LLVMValueRef dw_addr
= NULL
;
3117 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
3118 unsigned output_usage_mask
;
3121 if (!(ctx
->output_mask
& (1ull << i
)))
3124 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3126 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
3128 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3130 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
3133 param_index
= shader_io_get_unique_index(i
);
3136 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3137 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
3141 for (j
= 0; j
< 4; j
++) {
3142 if (!(output_usage_mask
& (1 << j
)))
3145 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
3146 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3147 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3149 if (ctx
->ac
.chip_class
>= GFX9
) {
3150 LLVMValueRef dw_addr_offset
=
3151 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3152 LLVMConstInt(ctx
->ac
.i32
,
3155 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
3157 ac_build_buffer_store_dword(&ctx
->ac
,
3160 NULL
, ctx
->es2gs_offset
,
3161 (4 * param_index
+ j
) * 4,
3162 ac_glc
| ac_slc
, true);
3169 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
3171 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
3172 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->shader_info
->info
.vs
.ls_outputs_written
);
3173 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
3174 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
3175 vertex_dw_stride
, "");
3177 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3178 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
3180 if (!(ctx
->output_mask
& (1ull << i
)))
3183 int param
= shader_io_get_unique_index(i
);
3184 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
3185 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
3187 for (unsigned j
= 0; j
< 4; j
++) {
3188 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
3189 value
= ac_to_integer(&ctx
->ac
, value
);
3190 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
3191 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
3192 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
3198 write_tess_factors(struct radv_shader_context
*ctx
)
3200 unsigned stride
, outer_comps
, inner_comps
;
3201 struct ac_build_if_state if_ctx
, inner_if_ctx
;
3202 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3203 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
3204 unsigned tess_inner_index
= 0, tess_outer_index
;
3205 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3206 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3208 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3210 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
3230 ac_nir_build_if(&if_ctx
, ctx
,
3231 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3232 invocation_id
, ctx
->ac
.i32_0
, ""));
3234 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3237 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3238 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3239 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3242 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3243 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3244 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3246 for (i
= 0; i
< 4; i
++) {
3247 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3248 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3252 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3253 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3254 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3256 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3258 for (i
= 0; i
< outer_comps
; i
++) {
3260 ac_lds_load(&ctx
->ac
, lds_outer
);
3261 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3264 for (i
= 0; i
< inner_comps
; i
++) {
3265 inner
[i
] = out
[outer_comps
+i
] =
3266 ac_lds_load(&ctx
->ac
, lds_inner
);
3267 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3272 /* Convert the outputs to vectors for stores. */
3273 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3277 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3280 buffer
= ctx
->hs_ring_tess_factor
;
3281 tf_base
= ctx
->tess_factor_offset
;
3282 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3283 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3284 unsigned tf_offset
= 0;
3286 if (ctx
->options
->chip_class
<= GFX8
) {
3287 ac_nir_build_if(&inner_if_ctx
, ctx
,
3288 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3289 rel_patch_id
, ctx
->ac
.i32_0
, ""));
3291 /* Store the dynamic HS control word. */
3292 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3293 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3294 1, ctx
->ac
.i32_0
, tf_base
,
3298 ac_nir_build_endif(&inner_if_ctx
);
3301 /* Store the tessellation factors. */
3302 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3303 MIN2(stride
, 4), byteoffset
, tf_base
,
3304 tf_offset
, ac_glc
, false);
3306 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3307 stride
- 4, byteoffset
, tf_base
,
3308 16 + tf_offset
, ac_glc
, false);
3310 //store to offchip for TES to read - only if TES reads them
3311 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
3312 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3313 LLVMValueRef tf_inner_offset
;
3314 unsigned param_outer
, param_inner
;
3316 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3317 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3318 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3320 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3321 util_next_power_of_two(outer_comps
));
3323 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3324 outer_comps
, tf_outer_offset
,
3325 ctx
->oc_lds
, 0, ac_glc
, false);
3327 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3328 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3329 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3331 inner_vec
= inner_comps
== 1 ? inner
[0] :
3332 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3333 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3334 inner_comps
, tf_inner_offset
,
3335 ctx
->oc_lds
, 0, ac_glc
, false);
3338 ac_nir_build_endif(&if_ctx
);
3342 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3344 write_tess_factors(ctx
);
3348 si_export_mrt_color(struct radv_shader_context
*ctx
,
3349 LLVMValueRef
*color
, unsigned index
,
3350 struct ac_export_args
*args
)
3353 si_llvm_init_export_args(ctx
, color
, 0xf,
3354 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3355 if (!args
->enabled_channels
)
3356 return false; /* unnecessary NULL export */
3362 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3363 LLVMValueRef depth
, LLVMValueRef stencil
,
3364 LLVMValueRef samplemask
)
3366 struct ac_export_args args
;
3368 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3370 ac_build_export(&ctx
->ac
, &args
);
3374 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3377 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3378 struct ac_export_args color_args
[8];
3380 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3381 LLVMValueRef values
[4];
3383 if (!(ctx
->output_mask
& (1ull << i
)))
3386 if (i
< FRAG_RESULT_DATA0
)
3389 for (unsigned j
= 0; j
< 4; j
++)
3390 values
[j
] = ac_to_float(&ctx
->ac
,
3391 radv_load_output(ctx
, i
, j
));
3393 bool ret
= si_export_mrt_color(ctx
, values
,
3394 i
- FRAG_RESULT_DATA0
,
3395 &color_args
[index
]);
3400 /* Process depth, stencil, samplemask. */
3401 if (ctx
->shader_info
->info
.ps
.writes_z
) {
3402 depth
= ac_to_float(&ctx
->ac
,
3403 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3405 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
3406 stencil
= ac_to_float(&ctx
->ac
,
3407 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
3409 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3410 samplemask
= ac_to_float(&ctx
->ac
,
3411 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
3414 /* Set the DONE bit on last non-null color export only if Z isn't
3418 !ctx
->shader_info
->info
.ps
.writes_z
&&
3419 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
3420 !ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3421 unsigned last
= index
- 1;
3423 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
3424 color_args
[last
].done
= 1; /* DONE bit */
3427 /* Export PS outputs. */
3428 for (unsigned i
= 0; i
< index
; i
++)
3429 ac_build_export(&ctx
->ac
, &color_args
[i
]);
3431 if (depth
|| stencil
|| samplemask
)
3432 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
3434 ac_build_export_null(&ctx
->ac
);
3438 emit_gs_epilogue(struct radv_shader_context
*ctx
)
3440 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
3444 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
3445 LLVMValueRef
*addrs
)
3447 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3449 switch (ctx
->stage
) {
3450 case MESA_SHADER_VERTEX
:
3451 if (ctx
->options
->key
.vs
.as_ls
)
3452 handle_ls_outputs_post(ctx
);
3453 else if (ctx
->options
->key
.vs
.as_es
)
3454 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
3456 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
3457 ctx
->options
->key
.vs
.export_layer_id
,
3458 ctx
->options
->key
.vs
.export_clip_dists
,
3459 &ctx
->shader_info
->vs
.outinfo
);
3461 case MESA_SHADER_FRAGMENT
:
3462 handle_fs_outputs_post(ctx
);
3464 case MESA_SHADER_GEOMETRY
:
3465 emit_gs_epilogue(ctx
);
3467 case MESA_SHADER_TESS_CTRL
:
3468 handle_tcs_outputs_post(ctx
);
3470 case MESA_SHADER_TESS_EVAL
:
3471 if (ctx
->options
->key
.tes
.as_es
)
3472 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
3474 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
3475 ctx
->options
->key
.tes
.export_layer_id
,
3476 ctx
->options
->key
.tes
.export_clip_dists
,
3477 &ctx
->shader_info
->tes
.outinfo
);
3484 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
3485 LLVMPassManagerRef passmgr
,
3486 const struct radv_nir_compiler_options
*options
)
3488 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
3489 LLVMDisposeBuilder(ctx
->ac
.builder
);
3491 ac_llvm_context_dispose(&ctx
->ac
);
3495 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
3497 struct radv_vs_output_info
*outinfo
;
3499 switch (ctx
->stage
) {
3500 case MESA_SHADER_FRAGMENT
:
3501 case MESA_SHADER_COMPUTE
:
3502 case MESA_SHADER_TESS_CTRL
:
3503 case MESA_SHADER_GEOMETRY
:
3505 case MESA_SHADER_VERTEX
:
3506 if (ctx
->options
->key
.vs
.as_ls
||
3507 ctx
->options
->key
.vs
.as_es
)
3509 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
3511 case MESA_SHADER_TESS_EVAL
:
3512 if (ctx
->options
->key
.vs
.as_es
)
3514 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
3517 unreachable("Unhandled shader type");
3520 ac_optimize_vs_outputs(&ctx
->ac
,
3522 outinfo
->vs_output_param_offset
,
3524 &outinfo
->param_exports
);
3528 ac_setup_rings(struct radv_shader_context
*ctx
)
3530 if (ctx
->options
->chip_class
<= GFX8
&&
3531 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
3532 ctx
->options
->key
.vs
.as_es
|| ctx
->options
->key
.tes
.as_es
)) {
3533 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
3535 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
3537 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
3542 if (ctx
->is_gs_copy_shader
) {
3544 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3545 LLVMConstInt(ctx
->ac
.i32
,
3546 RING_GSVS_VS
, false));
3549 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3550 /* The conceptual layout of the GSVS ring is
3551 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3552 * but the real memory layout is swizzled across
3554 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3556 * Override the buffer descriptor accordingly.
3558 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
3559 uint64_t stream_offset
= 0;
3560 unsigned num_records
= 64;
3561 LLVMValueRef base_ring
;
3564 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3565 LLVMConstInt(ctx
->ac
.i32
,
3566 RING_GSVS_GS
, false));
3568 for (unsigned stream
= 0; stream
< 4; stream
++) {
3569 unsigned num_components
, stride
;
3570 LLVMValueRef ring
, tmp
;
3573 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
3575 if (!num_components
)
3578 stride
= 4 * num_components
* ctx
->gs_max_out_vertices
;
3580 /* Limit on the stride field for <= GFX7. */
3581 assert(stride
< (1 << 14));
3583 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
3584 base_ring
, v2i64
, "");
3585 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3586 ring
, ctx
->ac
.i32_0
, "");
3587 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
3588 LLVMConstInt(ctx
->ac
.i64
,
3589 stream_offset
, 0), "");
3590 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
3591 ring
, tmp
, ctx
->ac
.i32_0
, "");
3593 stream_offset
+= stride
* 64;
3595 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
3598 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
3600 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
3601 LLVMConstInt(ctx
->ac
.i32
,
3602 S_008F04_STRIDE(stride
), false), "");
3603 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
3606 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
3607 LLVMConstInt(ctx
->ac
.i32
,
3608 num_records
, false),
3609 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3611 ctx
->gsvs_ring
[stream
] = ring
;
3615 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3616 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3617 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
3618 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
3623 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
3624 const struct nir_shader
*nir
)
3626 switch (nir
->info
.stage
) {
3627 case MESA_SHADER_TESS_CTRL
:
3628 return chip_class
>= GFX7
? 128 : 64;
3629 case MESA_SHADER_GEOMETRY
:
3630 return chip_class
>= GFX9
? 128 : 64;
3631 case MESA_SHADER_COMPUTE
:
3637 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
3638 nir
->info
.cs
.local_size
[1] *
3639 nir
->info
.cs
.local_size
[2];
3640 return max_workgroup_size
;
3643 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3644 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
3646 LLVMValueRef count
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
3647 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
3649 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
3650 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
3651 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
3654 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
3656 for(int i
= 5; i
>= 0; --i
) {
3657 ctx
->gs_vtx_offset
[i
] = ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
3661 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 16, 8);
3666 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
3667 struct nir_shader
*const *shaders
,
3669 struct radv_shader_variant_info
*shader_info
,
3670 const struct radv_nir_compiler_options
*options
)
3672 struct radv_shader_context ctx
= {0};
3674 ctx
.options
= options
;
3675 ctx
.shader_info
= shader_info
;
3677 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
3678 ctx
.context
= ctx
.ac
.context
;
3679 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
3681 enum ac_float_mode float_mode
=
3682 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
3683 AC_FLOAT_MODE_DEFAULT
;
3685 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
3687 memset(shader_info
, 0, sizeof(*shader_info
));
3689 radv_nir_shader_info_init(&shader_info
->info
);
3691 for(int i
= 0; i
< shader_count
; ++i
)
3692 radv_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
3694 for (i
= 0; i
< RADV_UD_MAX_SETS
; i
++)
3695 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
3696 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
3697 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
3699 ctx
.max_workgroup_size
= 0;
3700 for (int i
= 0; i
< shader_count
; ++i
) {
3701 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
3702 radv_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
3706 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
3707 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
3709 ctx
.abi
.inputs
= &ctx
.inputs
[0];
3710 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
3711 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
3712 ctx
.abi
.load_ubo
= radv_load_ubo
;
3713 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
3714 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
3715 ctx
.abi
.load_resource
= radv_load_resource
;
3716 ctx
.abi
.clamp_shadow_reference
= false;
3717 ctx
.abi
.gfx9_stride_size_workaround
= ctx
.ac
.chip_class
== GFX9
&& HAVE_LLVM
< 0x800;
3719 /* Because the new raw/struct atomic intrinsics are buggy with LLVM 8,
3720 * we fallback to the old intrinsics for atomic buffer image operations
3721 * and thus we need to apply the indexing workaround...
3723 ctx
.abi
.gfx9_stride_size_workaround_for_atomic
= ctx
.ac
.chip_class
== GFX9
&& HAVE_LLVM
< 0x900;
3725 if (shader_count
>= 2)
3726 ac_init_exec_full_mask(&ctx
.ac
);
3728 if ((ctx
.ac
.family
== CHIP_VEGA10
||
3729 ctx
.ac
.family
== CHIP_RAVEN
) &&
3730 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
3731 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
3733 for(int i
= 0; i
< shader_count
; ++i
) {
3734 ctx
.stage
= shaders
[i
]->info
.stage
;
3735 ctx
.output_mask
= 0;
3737 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3738 for (int i
= 0; i
< 4; i
++) {
3739 ctx
.gs_next_vertex
[i
] =
3740 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
3742 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
3743 ctx
.abi
.load_inputs
= load_gs_input
;
3744 ctx
.abi
.emit_primitive
= visit_end_primitive
;
3745 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3746 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
3747 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
3748 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
3749 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3750 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
3751 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3752 if (shader_count
== 1)
3753 ctx
.tcs_num_inputs
= ctx
.options
->key
.tcs
.num_inputs
;
3755 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->info
.vs
.ls_outputs_written
);
3756 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
3757 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
3758 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
3759 ctx
.abi
.load_tess_varyings
= load_tes_input
;
3760 ctx
.abi
.load_tess_coord
= load_tess_coord
;
3761 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3762 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3763 ctx
.tcs_num_patches
= ctx
.options
->key
.tes
.num_patches
;
3764 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
3765 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
3766 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
3767 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
3768 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
3769 ctx
.abi
.load_sample_position
= load_sample_position
;
3770 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
3771 ctx
.abi
.emit_kill
= radv_emit_kill
;
3775 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
3777 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
3778 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
3780 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3781 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
3782 shaders
[i
]->info
.cull_distance_array_size
> 4;
3783 ctx
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
3784 ctx
.max_gsvs_emit_size
= ctx
.gsvs_vertex_size
*
3785 shaders
[i
]->info
.gs
.vertices_out
;
3788 ac_setup_rings(&ctx
);
3790 LLVMBasicBlockRef merge_block
;
3791 if (shader_count
>= 2) {
3792 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
3793 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3794 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3796 LLVMValueRef count
= ac_unpack_param(&ctx
.ac
, ctx
.merged_wave_info
, 8 * i
, 8);
3797 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
3798 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
3799 thread_id
, count
, "");
3800 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
3802 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
3805 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
3806 handle_fs_inputs(&ctx
, shaders
[i
]);
3807 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
3808 handle_vs_inputs(&ctx
, shaders
[i
]);
3809 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
3810 prepare_gs_input_vgprs(&ctx
);
3812 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
3814 if (shader_count
>= 2) {
3815 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
3816 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
3819 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3820 shader_info
->gs
.gsvs_vertex_size
= ctx
.gsvs_vertex_size
;
3821 shader_info
->gs
.max_gsvs_emit_size
= ctx
.max_gsvs_emit_size
;
3822 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3823 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
3824 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
3828 LLVMBuildRetVoid(ctx
.ac
.builder
);
3830 if (options
->dump_preoptir
)
3831 ac_dump_module(ctx
.ac
.module
);
3833 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
3835 if (shader_count
== 1)
3836 ac_nir_eliminate_const_vs_outputs(&ctx
);
3838 if (options
->dump_shader
) {
3839 ctx
.shader_info
->private_mem_vgprs
=
3840 ac_count_scratch_private_memory(ctx
.main_function
);
3843 return ctx
.ac
.module
;
3846 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
3848 unsigned *retval
= (unsigned *)context
;
3849 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
3850 char *description
= LLVMGetDiagInfoDescription(di
);
3852 if (severity
== LLVMDSError
) {
3854 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
3858 LLVMDisposeMessage(description
);
3861 static unsigned radv_llvm_compile(LLVMModuleRef M
,
3862 char **pelf_buffer
, size_t *pelf_size
,
3863 struct ac_llvm_compiler
*ac_llvm
)
3865 unsigned retval
= 0;
3866 LLVMContextRef llvm_ctx
;
3868 /* Setup Diagnostic Handler*/
3869 llvm_ctx
= LLVMGetModuleContext(M
);
3871 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
3875 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
3880 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
3881 LLVMModuleRef llvm_module
,
3882 struct radv_shader_binary
**rbinary
,
3883 struct radv_shader_variant_info
*shader_info
,
3884 gl_shader_stage stage
,
3885 const struct radv_nir_compiler_options
*options
)
3887 char *elf_buffer
= NULL
;
3888 size_t elf_size
= 0;
3889 char *llvm_ir_string
= NULL
;
3890 if (options
->dump_shader
)
3891 ac_dump_module(llvm_module
);
3893 if (options
->record_llvm_ir
) {
3894 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
3895 llvm_ir_string
= strdup(llvm_ir
);
3896 LLVMDisposeMessage(llvm_ir
);
3899 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
3901 fprintf(stderr
, "compile failed\n");
3904 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
3905 LLVMDisposeModule(llvm_module
);
3906 LLVMContextDispose(ctx
);
3908 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
3909 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
3910 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
3911 memcpy(rbin
->data
, elf_buffer
, elf_size
);
3913 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
3915 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
3916 rbin
->base
.stage
= stage
;
3917 rbin
->base
.total_size
= alloc_size
;
3918 rbin
->elf_size
= elf_size
;
3919 rbin
->llvm_ir_size
= llvm_ir_size
;
3920 *rbinary
= &rbin
->base
;
3922 free(llvm_ir_string
);
3927 ac_fill_shader_info(struct radv_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct radv_nir_compiler_options
*options
)
3929 switch (nir
->info
.stage
) {
3930 case MESA_SHADER_COMPUTE
:
3931 for (int i
= 0; i
< 3; ++i
)
3932 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
3934 case MESA_SHADER_FRAGMENT
:
3935 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
3937 case MESA_SHADER_GEOMETRY
:
3938 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
3939 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
3940 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
3941 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
3943 case MESA_SHADER_TESS_EVAL
:
3944 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
3945 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
3946 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
3947 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
3948 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
3949 shader_info
->tes
.export_prim_id
= options
->key
.tes
.export_prim_id
;
3951 case MESA_SHADER_TESS_CTRL
:
3952 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
3954 case MESA_SHADER_VERTEX
:
3955 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
3956 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
3957 shader_info
->vs
.export_prim_id
= options
->key
.vs
.export_prim_id
;
3965 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
3966 struct radv_shader_binary
**rbinary
,
3967 struct radv_shader_variant_info
*shader_info
,
3968 struct nir_shader
*const *nir
,
3970 const struct radv_nir_compiler_options
*options
)
3973 LLVMModuleRef llvm_module
;
3975 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, shader_info
,
3978 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
, shader_info
,
3979 nir
[nir_count
- 1]->info
.stage
, options
);
3981 for (int i
= 0; i
< nir_count
; ++i
)
3982 ac_fill_shader_info(shader_info
, nir
[i
], options
);
3984 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3985 if (options
->chip_class
== GFX9
) {
3986 if (nir_count
== 2 &&
3987 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3988 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
3994 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
3996 LLVMValueRef vtx_offset
=
3997 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
3998 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3999 LLVMValueRef stream_id
;
4001 /* Fetch the vertex stream ID. */
4002 if (ctx
->shader_info
->info
.so
.num_outputs
) {
4004 ac_unpack_param(&ctx
->ac
, ctx
->streamout_config
, 24, 2);
4006 stream_id
= ctx
->ac
.i32_0
;
4009 LLVMBasicBlockRef end_bb
;
4010 LLVMValueRef switch_inst
;
4012 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
4013 ctx
->main_function
, "end");
4014 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
4016 for (unsigned stream
= 0; stream
< 4; stream
++) {
4017 unsigned num_components
=
4018 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
4019 LLVMBasicBlockRef bb
;
4022 if (!num_components
)
4025 if (stream
> 0 && !ctx
->shader_info
->info
.so
.num_outputs
)
4028 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
4029 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
4030 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
4033 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4034 unsigned output_usage_mask
=
4035 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
4036 unsigned output_stream
=
4037 ctx
->shader_info
->info
.gs
.output_streams
[i
];
4038 int length
= util_last_bit(output_usage_mask
);
4040 if (!(ctx
->output_mask
& (1ull << i
)) ||
4041 output_stream
!= stream
)
4044 for (unsigned j
= 0; j
< length
; j
++) {
4045 LLVMValueRef value
, soffset
;
4047 if (!(output_usage_mask
& (1 << j
)))
4050 soffset
= LLVMConstInt(ctx
->ac
.i32
,
4052 ctx
->gs_max_out_vertices
* 16 * 4, false);
4056 value
= ac_build_buffer_load(&ctx
->ac
,
4059 vtx_offset
, soffset
,
4060 0, ac_glc
| ac_slc
, true, false);
4062 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4063 if (ac_get_type_size(type
) == 2) {
4064 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
4065 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
4068 LLVMBuildStore(ctx
->ac
.builder
,
4069 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4073 if (ctx
->shader_info
->info
.so
.num_outputs
)
4074 radv_emit_streamout(ctx
, stream
);
4077 handle_vs_outputs_post(ctx
, false, false, true,
4078 &ctx
->shader_info
->vs
.outinfo
);
4081 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
4084 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
4088 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
4089 struct nir_shader
*geom_shader
,
4090 struct radv_shader_binary
**rbinary
,
4091 struct radv_shader_variant_info
*shader_info
,
4092 const struct radv_nir_compiler_options
*options
)
4094 struct radv_shader_context ctx
= {0};
4095 ctx
.options
= options
;
4096 ctx
.shader_info
= shader_info
;
4098 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
4099 ctx
.context
= ctx
.ac
.context
;
4100 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
4102 ctx
.is_gs_copy_shader
= true;
4104 enum ac_float_mode float_mode
=
4105 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
4106 AC_FLOAT_MODE_DEFAULT
;
4108 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
4109 ctx
.stage
= MESA_SHADER_VERTEX
;
4111 radv_nir_shader_info_pass(geom_shader
, options
, &shader_info
->info
);
4113 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
4115 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
4116 ac_setup_rings(&ctx
);
4118 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
4119 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
4120 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
4121 variable
, MESA_SHADER_VERTEX
);
4124 ac_gs_copy_shader_emit(&ctx
);
4126 LLVMBuildRetVoid(ctx
.ac
.builder
);
4128 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
4130 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
, shader_info
,
4131 MESA_SHADER_VERTEX
, options
);
4132 (*rbinary
)->is_gs_copy_shader
= true;