2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 struct radv_shader_context
{
50 struct ac_llvm_context ac
;
51 const struct radv_nir_compiler_options
*options
;
52 struct radv_shader_variant_info
*shader_info
;
53 struct ac_shader_abi abi
;
55 unsigned max_workgroup_size
;
56 LLVMContextRef context
;
57 LLVMValueRef main_function
;
59 LLVMValueRef descriptor_sets
[RADV_UD_MAX_SETS
];
60 LLVMValueRef ring_offsets
;
62 LLVMValueRef vertex_buffers
;
63 LLVMValueRef rel_auto_id
;
64 LLVMValueRef vs_prim_id
;
65 LLVMValueRef es2gs_offset
;
68 LLVMValueRef merged_wave_info
;
69 LLVMValueRef tess_factor_offset
;
70 LLVMValueRef tes_rel_patch_id
;
74 LLVMValueRef gs2vs_offset
;
75 LLVMValueRef gs_wave_id
;
76 LLVMValueRef gs_vtx_offset
[6];
78 LLVMValueRef esgs_ring
;
79 LLVMValueRef gsvs_ring
[4];
80 LLVMValueRef hs_ring_tess_offchip
;
81 LLVMValueRef hs_ring_tess_factor
;
83 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
84 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
87 LLVMValueRef streamout_buffers
;
88 LLVMValueRef streamout_write_idx
;
89 LLVMValueRef streamout_config
;
90 LLVMValueRef streamout_offset
[4];
92 gl_shader_stage stage
;
94 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
99 bool is_gs_copy_shader
;
100 LLVMValueRef gs_next_vertex
[4];
101 unsigned gs_max_out_vertices
;
103 unsigned tes_primitive_mode
;
105 uint32_t tcs_patch_outputs_read
;
106 uint64_t tcs_outputs_read
;
107 uint32_t tcs_vertices_per_patch
;
108 uint32_t tcs_num_inputs
;
109 uint32_t tcs_num_patches
;
110 uint32_t max_gsvs_emit_size
;
111 uint32_t gsvs_vertex_size
;
114 enum radeon_llvm_calling_convention
{
115 RADEON_LLVM_AMDGPU_VS
= 87,
116 RADEON_LLVM_AMDGPU_GS
= 88,
117 RADEON_LLVM_AMDGPU_PS
= 89,
118 RADEON_LLVM_AMDGPU_CS
= 90,
119 RADEON_LLVM_AMDGPU_HS
= 93,
122 static inline struct radv_shader_context
*
123 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
125 struct radv_shader_context
*ctx
= NULL
;
126 return container_of(abi
, ctx
, abi
);
129 struct ac_build_if_state
131 struct radv_shader_context
*ctx
;
132 LLVMValueRef condition
;
133 LLVMBasicBlockRef entry_block
;
134 LLVMBasicBlockRef true_block
;
135 LLVMBasicBlockRef false_block
;
136 LLVMBasicBlockRef merge_block
;
139 static LLVMBasicBlockRef
140 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
142 LLVMBasicBlockRef current_block
;
143 LLVMBasicBlockRef next_block
;
144 LLVMBasicBlockRef new_block
;
146 /* get current basic block */
147 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
149 /* chqeck if there's another block after this one */
150 next_block
= LLVMGetNextBasicBlock(current_block
);
152 /* insert the new block before the next block */
153 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
156 /* append new block after current block */
157 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
158 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
164 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
165 struct radv_shader_context
*ctx
,
166 LLVMValueRef condition
)
168 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
170 memset(ifthen
, 0, sizeof *ifthen
);
172 ifthen
->condition
= condition
;
173 ifthen
->entry_block
= block
;
175 /* create endif/merge basic block for the phi functions */
176 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
178 /* create/insert true_block before merge_block */
180 LLVMInsertBasicBlockInContext(ctx
->context
,
184 /* successive code goes into the true block */
185 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
192 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
194 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
196 /* Insert branch to the merge block from current block */
197 LLVMBuildBr(builder
, ifthen
->merge_block
);
200 * Now patch in the various branch instructions.
203 /* Insert the conditional branch instruction at the end of entry_block */
204 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
205 if (ifthen
->false_block
) {
206 /* we have an else clause */
207 LLVMBuildCondBr(builder
, ifthen
->condition
,
208 ifthen
->true_block
, ifthen
->false_block
);
212 LLVMBuildCondBr(builder
, ifthen
->condition
,
213 ifthen
->true_block
, ifthen
->merge_block
);
216 /* Resume building code at end of the ifthen->merge_block */
217 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
221 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
223 switch (ctx
->stage
) {
224 case MESA_SHADER_TESS_CTRL
:
225 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
226 case MESA_SHADER_TESS_EVAL
:
227 return ctx
->tes_rel_patch_id
;
230 unreachable("Illegal stage");
235 get_tcs_num_patches(struct radv_shader_context
*ctx
)
237 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
238 unsigned num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
239 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
240 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
241 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
242 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
243 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
244 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
245 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
246 unsigned num_patches
;
247 unsigned hardware_lds_size
;
249 /* Ensure that we only need one wave per SIMD so we don't need to check
250 * resource usage. Also ensures that the number of tcs in and out
251 * vertices per threadgroup are at most 256.
253 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
254 /* Make sure that the data fits in LDS. This assumes the shaders only
255 * use LDS for the inputs and outputs.
257 hardware_lds_size
= 32768;
259 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
260 * threadgroup, even though there is more than 32 KiB LDS.
262 * Test: dEQP-VK.tessellation.shader_input_output.barrier
264 if (ctx
->options
->chip_class
>= CIK
&& ctx
->options
->family
!= CHIP_STONEY
)
265 hardware_lds_size
= 65536;
267 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
268 /* Make sure the output data fits in the offchip buffer */
269 num_patches
= MIN2(num_patches
, (ctx
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
270 /* Not necessary for correctness, but improves performance. The
271 * specific value is taken from the proprietary driver.
273 num_patches
= MIN2(num_patches
, 40);
275 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
276 if (ctx
->options
->chip_class
== SI
) {
277 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
278 num_patches
= MIN2(num_patches
, one_wave
);
284 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
286 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
287 unsigned num_tcs_output_cp
;
288 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
289 unsigned input_vertex_size
, output_vertex_size
;
290 unsigned input_patch_size
, output_patch_size
;
291 unsigned pervertex_output_patch_size
;
292 unsigned output_patch0_offset
;
293 unsigned num_patches
;
296 num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
297 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
298 num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
300 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
301 output_vertex_size
= num_tcs_outputs
* 16;
303 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
305 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
306 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
308 num_patches
= ctx
->tcs_num_patches
;
309 output_patch0_offset
= input_patch_size
* num_patches
;
311 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
315 /* Tessellation shaders pass outputs to the next shader using LDS.
317 * LS outputs = TCS inputs
318 * TCS outputs = TES inputs
321 * - TCS inputs for patch 0
322 * - TCS inputs for patch 1
323 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
325 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
326 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
327 * - TCS outputs for patch 1
328 * - Per-patch TCS outputs for patch 1
329 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
330 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
333 * All three shaders VS(LS), TCS, TES share the same LDS space.
336 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
338 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
339 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
340 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
342 input_patch_size
/= 4;
343 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
347 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
349 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
350 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
351 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
352 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
353 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
354 output_patch_size
/= 4;
355 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
359 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
361 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
362 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
363 output_vertex_size
/= 4;
364 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
368 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
370 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
371 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
372 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
373 uint32_t output_patch0_offset
= input_patch_size
;
374 unsigned num_patches
= ctx
->tcs_num_patches
;
376 output_patch0_offset
*= num_patches
;
377 output_patch0_offset
/= 4;
378 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
382 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
384 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
385 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
386 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
387 uint32_t output_patch0_offset
= input_patch_size
;
389 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
390 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
391 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
392 unsigned num_patches
= ctx
->tcs_num_patches
;
394 output_patch0_offset
*= num_patches
;
395 output_patch0_offset
+= pervertex_output_patch_size
;
396 output_patch0_offset
/= 4;
397 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
401 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
403 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
404 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
406 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
410 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
412 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
413 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
414 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
416 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
421 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
423 LLVMValueRef patch0_patch_data_offset
=
424 get_tcs_out_patch0_patch_data_offset(ctx
);
425 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
426 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
428 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
429 patch0_patch_data_offset
);
434 LLVMTypeRef types
[MAX_ARGS
];
435 LLVMValueRef
*assign
[MAX_ARGS
];
436 unsigned array_params_mask
;
439 uint8_t num_sgprs_used
;
440 uint8_t num_vgprs_used
;
443 enum ac_arg_regfile
{
449 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
450 LLVMValueRef
*param_ptr
)
452 assert(info
->count
< MAX_ARGS
);
454 info
->assign
[info
->count
] = param_ptr
;
455 info
->types
[info
->count
] = type
;
458 if (regfile
== ARG_SGPR
) {
459 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
462 assert(regfile
== ARG_VGPR
);
463 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
468 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
470 info
->array_params_mask
|= (1 << info
->count
);
471 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
474 static void assign_arguments(LLVMValueRef main_function
,
475 struct arg_info
*info
)
478 for (i
= 0; i
< info
->count
; i
++) {
480 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
485 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
486 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
487 unsigned num_return_elems
,
488 struct arg_info
*args
,
489 unsigned max_workgroup_size
,
490 const struct radv_nir_compiler_options
*options
)
492 LLVMTypeRef main_function_type
, ret_type
;
493 LLVMBasicBlockRef main_function_body
;
495 if (num_return_elems
)
496 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
497 num_return_elems
, true);
499 ret_type
= LLVMVoidTypeInContext(ctx
);
501 /* Setup the function */
503 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
504 LLVMValueRef main_function
=
505 LLVMAddFunction(module
, "main", main_function_type
);
507 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
508 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
510 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
511 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
512 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
514 if (args
->array_params_mask
& (1 << i
)) {
515 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
516 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
517 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
521 if (options
->address32_hi
) {
522 ac_llvm_add_target_dep_function_attr(main_function
,
523 "amdgpu-32bit-address-high-bits",
524 options
->address32_hi
);
527 if (max_workgroup_size
) {
528 ac_llvm_add_target_dep_function_attr(main_function
,
529 "amdgpu-max-work-group-size",
532 if (options
->unsafe_math
) {
533 /* These were copied from some LLVM test. */
534 LLVMAddTargetDependentFunctionAttr(main_function
,
535 "less-precise-fpmad",
537 LLVMAddTargetDependentFunctionAttr(main_function
,
540 LLVMAddTargetDependentFunctionAttr(main_function
,
543 LLVMAddTargetDependentFunctionAttr(main_function
,
546 LLVMAddTargetDependentFunctionAttr(main_function
,
547 "no-signed-zeros-fp-math",
550 return main_function
;
555 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
,
558 ud_info
->sgpr_idx
= *sgpr_idx
;
559 ud_info
->num_sgprs
= num_sgprs
;
560 *sgpr_idx
+= num_sgprs
;
564 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
567 struct radv_userdata_info
*ud_info
=
568 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
571 set_loc(ud_info
, sgpr_idx
, num_sgprs
);
575 set_loc_shader_ptr(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
577 bool use_32bit_pointers
= idx
!= AC_UD_SCRATCH_RING_OFFSETS
;
579 set_loc_shader(ctx
, idx
, sgpr_idx
, use_32bit_pointers
? 1 : 2);
583 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
585 struct radv_userdata_locations
*locs
=
586 &ctx
->shader_info
->user_sgprs_locs
;
587 struct radv_userdata_info
*ud_info
= &locs
->descriptor_sets
[idx
];
590 set_loc(ud_info
, sgpr_idx
, 1);
592 locs
->descriptor_sets_enabled
|= 1 << idx
;
595 struct user_sgpr_info
{
596 bool need_ring_offsets
;
597 bool indirect_all_descriptor_sets
;
600 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
601 gl_shader_stage stage
)
604 case MESA_SHADER_VERTEX
:
605 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
606 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
609 case MESA_SHADER_TESS_EVAL
:
610 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
613 case MESA_SHADER_GEOMETRY
:
614 case MESA_SHADER_TESS_CTRL
:
615 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
625 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
629 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
631 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
636 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
637 gl_shader_stage stage
,
638 bool has_previous_stage
,
639 gl_shader_stage previous_stage
,
640 bool needs_view_index
,
641 struct user_sgpr_info
*user_sgpr_info
)
643 uint8_t user_sgpr_count
= 0;
645 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
647 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
648 if (stage
== MESA_SHADER_GEOMETRY
||
649 stage
== MESA_SHADER_VERTEX
||
650 stage
== MESA_SHADER_TESS_CTRL
||
651 stage
== MESA_SHADER_TESS_EVAL
||
652 ctx
->is_gs_copy_shader
)
653 user_sgpr_info
->need_ring_offsets
= true;
655 if (stage
== MESA_SHADER_FRAGMENT
&&
656 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
657 user_sgpr_info
->need_ring_offsets
= true;
659 /* 2 user sgprs will nearly always be allocated for scratch/rings */
660 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
661 user_sgpr_count
+= 2;
665 case MESA_SHADER_COMPUTE
:
666 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
667 user_sgpr_count
+= 3;
669 case MESA_SHADER_FRAGMENT
:
670 user_sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
672 case MESA_SHADER_VERTEX
:
673 if (!ctx
->is_gs_copy_shader
)
674 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
676 case MESA_SHADER_TESS_CTRL
:
677 if (has_previous_stage
) {
678 if (previous_stage
== MESA_SHADER_VERTEX
)
679 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
682 case MESA_SHADER_TESS_EVAL
:
684 case MESA_SHADER_GEOMETRY
:
685 if (has_previous_stage
) {
686 if (previous_stage
== MESA_SHADER_VERTEX
) {
687 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
695 if (needs_view_index
)
698 if (ctx
->shader_info
->info
.loads_push_constants
)
701 if (ctx
->streamout_buffers
)
704 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
&& stage
!= MESA_SHADER_COMPUTE
? 32 : 16;
705 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_count
;
706 uint32_t num_desc_set
=
707 util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
);
709 if (remaining_sgprs
< num_desc_set
) {
710 user_sgpr_info
->indirect_all_descriptor_sets
= true;
715 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
716 gl_shader_stage stage
,
717 bool has_previous_stage
,
718 gl_shader_stage previous_stage
,
719 const struct user_sgpr_info
*user_sgpr_info
,
720 struct arg_info
*args
,
721 LLVMValueRef
*desc_sets
)
723 LLVMTypeRef type
= ac_array_in_const32_addr_space(ctx
->ac
.i8
);
724 unsigned num_sets
= ctx
->options
->layout
?
725 ctx
->options
->layout
->num_sets
: 0;
726 unsigned stage_mask
= 1 << stage
;
728 if (has_previous_stage
)
729 stage_mask
|= 1 << previous_stage
;
731 /* 1 for each descriptor set */
732 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
733 for (unsigned i
= 0; i
< num_sets
; ++i
) {
734 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
735 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
736 add_array_arg(args
, type
,
737 &ctx
->descriptor_sets
[i
]);
741 add_array_arg(args
, ac_array_in_const32_addr_space(type
), desc_sets
);
744 if (ctx
->shader_info
->info
.loads_push_constants
) {
745 /* 1 for push constants and dynamic descriptors */
746 add_array_arg(args
, type
, &ctx
->abi
.push_constants
);
749 if (ctx
->shader_info
->info
.so
.num_outputs
) {
750 add_arg(args
, ARG_SGPR
,
751 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
752 &ctx
->streamout_buffers
);
757 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
758 gl_shader_stage stage
,
759 bool has_previous_stage
,
760 gl_shader_stage previous_stage
,
761 struct arg_info
*args
)
763 if (!ctx
->is_gs_copy_shader
&&
764 (stage
== MESA_SHADER_VERTEX
||
765 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
766 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
767 add_arg(args
, ARG_SGPR
,
768 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
769 &ctx
->vertex_buffers
);
771 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
772 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
773 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
774 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
780 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
782 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
783 if (!ctx
->is_gs_copy_shader
) {
784 if (ctx
->options
->key
.vs
.as_ls
) {
785 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
786 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
788 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
789 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
791 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
796 declare_streamout_sgprs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
797 struct arg_info
*args
)
801 /* Streamout SGPRs. */
802 if (ctx
->shader_info
->info
.so
.num_outputs
) {
803 assert(stage
== MESA_SHADER_VERTEX
||
804 stage
== MESA_SHADER_TESS_EVAL
);
806 if (stage
!= MESA_SHADER_TESS_EVAL
) {
807 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_config
);
809 args
->assign
[args
->count
- 1] = &ctx
->streamout_config
;
810 args
->types
[args
->count
- 1] = ctx
->ac
.i32
;
813 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_write_idx
);
816 /* A streamout buffer offset is loaded if the stride is non-zero. */
817 for (i
= 0; i
< 4; i
++) {
818 if (!ctx
->shader_info
->info
.so
.strides
[i
])
821 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_offset
[i
]);
826 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
828 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
829 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
830 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
831 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
835 set_global_input_locs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
836 bool has_previous_stage
, gl_shader_stage previous_stage
,
837 const struct user_sgpr_info
*user_sgpr_info
,
838 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
840 unsigned num_sets
= ctx
->options
->layout
?
841 ctx
->options
->layout
->num_sets
: 0;
842 unsigned stage_mask
= 1 << stage
;
844 if (has_previous_stage
)
845 stage_mask
|= 1 << previous_stage
;
847 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
848 for (unsigned i
= 0; i
< num_sets
; ++i
) {
849 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
850 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
851 set_loc_desc(ctx
, i
, user_sgpr_idx
);
853 ctx
->descriptor_sets
[i
] = NULL
;
856 set_loc_shader_ptr(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
859 for (unsigned i
= 0; i
< num_sets
; ++i
) {
860 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
861 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
862 ctx
->descriptor_sets
[i
] =
863 ac_build_load_to_sgpr(&ctx
->ac
,
865 LLVMConstInt(ctx
->ac
.i32
, i
, false));
868 ctx
->descriptor_sets
[i
] = NULL
;
870 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
873 if (ctx
->shader_info
->info
.loads_push_constants
) {
874 set_loc_shader_ptr(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
);
877 if (ctx
->streamout_buffers
) {
878 set_loc_shader_ptr(ctx
, AC_UD_STREAMOUT_BUFFERS
,
884 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
885 gl_shader_stage stage
, bool has_previous_stage
,
886 gl_shader_stage previous_stage
,
887 uint8_t *user_sgpr_idx
)
889 if (!ctx
->is_gs_copy_shader
&&
890 (stage
== MESA_SHADER_VERTEX
||
891 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
892 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
893 set_loc_shader_ptr(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
898 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
901 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
902 user_sgpr_idx
, vs_num
);
906 static void set_llvm_calling_convention(LLVMValueRef func
,
907 gl_shader_stage stage
)
909 enum radeon_llvm_calling_convention calling_conv
;
912 case MESA_SHADER_VERTEX
:
913 case MESA_SHADER_TESS_EVAL
:
914 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
916 case MESA_SHADER_GEOMETRY
:
917 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
919 case MESA_SHADER_TESS_CTRL
:
920 calling_conv
= RADEON_LLVM_AMDGPU_HS
;
922 case MESA_SHADER_FRAGMENT
:
923 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
925 case MESA_SHADER_COMPUTE
:
926 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
929 unreachable("Unhandle shader type");
932 LLVMSetFunctionCallConv(func
, calling_conv
);
935 static void create_function(struct radv_shader_context
*ctx
,
936 gl_shader_stage stage
,
937 bool has_previous_stage
,
938 gl_shader_stage previous_stage
)
940 uint8_t user_sgpr_idx
;
941 struct user_sgpr_info user_sgpr_info
;
942 struct arg_info args
= {};
943 LLVMValueRef desc_sets
;
944 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
945 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
946 previous_stage
, needs_view_index
, &user_sgpr_info
);
948 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
949 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
954 case MESA_SHADER_COMPUTE
:
955 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
956 previous_stage
, &user_sgpr_info
,
959 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
960 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
961 &ctx
->abi
.num_work_groups
);
964 for (int i
= 0; i
< 3; i
++) {
965 ctx
->abi
.workgroup_ids
[i
] = NULL
;
966 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
967 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
968 &ctx
->abi
.workgroup_ids
[i
]);
972 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
973 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
974 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
975 &ctx
->abi
.local_invocation_ids
);
977 case MESA_SHADER_VERTEX
:
978 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
979 previous_stage
, &user_sgpr_info
,
981 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
982 previous_stage
, &args
);
984 if (needs_view_index
)
985 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
986 &ctx
->abi
.view_index
);
987 if (ctx
->options
->key
.vs
.as_es
) {
988 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
990 } else if (ctx
->options
->key
.vs
.as_ls
) {
991 /* no extra parameters */
993 declare_streamout_sgprs(ctx
, stage
, &args
);
996 declare_vs_input_vgprs(ctx
, &args
);
998 case MESA_SHADER_TESS_CTRL
:
999 if (has_previous_stage
) {
1000 // First 6 system regs
1001 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1002 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1003 &ctx
->merged_wave_info
);
1004 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1005 &ctx
->tess_factor_offset
);
1007 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1008 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1009 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1011 declare_global_input_sgprs(ctx
, stage
,
1014 &user_sgpr_info
, &args
,
1016 declare_vs_specific_input_sgprs(ctx
, stage
,
1018 previous_stage
, &args
);
1020 if (needs_view_index
)
1021 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1022 &ctx
->abi
.view_index
);
1024 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1025 &ctx
->abi
.tcs_patch_id
);
1026 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1027 &ctx
->abi
.tcs_rel_ids
);
1029 declare_vs_input_vgprs(ctx
, &args
);
1031 declare_global_input_sgprs(ctx
, stage
,
1034 &user_sgpr_info
, &args
,
1037 if (needs_view_index
)
1038 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1039 &ctx
->abi
.view_index
);
1041 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1042 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1043 &ctx
->tess_factor_offset
);
1044 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1045 &ctx
->abi
.tcs_patch_id
);
1046 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1047 &ctx
->abi
.tcs_rel_ids
);
1050 case MESA_SHADER_TESS_EVAL
:
1051 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
1052 previous_stage
, &user_sgpr_info
,
1055 if (needs_view_index
)
1056 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1057 &ctx
->abi
.view_index
);
1059 if (ctx
->options
->key
.tes
.as_es
) {
1060 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1061 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1062 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1063 &ctx
->es2gs_offset
);
1065 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1066 declare_streamout_sgprs(ctx
, stage
, &args
);
1067 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1069 declare_tes_input_vgprs(ctx
, &args
);
1071 case MESA_SHADER_GEOMETRY
:
1072 if (has_previous_stage
) {
1073 // First 6 system regs
1074 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1075 &ctx
->gs2vs_offset
);
1076 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1077 &ctx
->merged_wave_info
);
1078 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1080 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1081 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1082 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1084 declare_global_input_sgprs(ctx
, stage
,
1087 &user_sgpr_info
, &args
,
1090 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
1091 declare_vs_specific_input_sgprs(ctx
, stage
,
1097 if (needs_view_index
)
1098 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1099 &ctx
->abi
.view_index
);
1101 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1102 &ctx
->gs_vtx_offset
[0]);
1103 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1104 &ctx
->gs_vtx_offset
[2]);
1105 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1106 &ctx
->abi
.gs_prim_id
);
1107 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1108 &ctx
->abi
.gs_invocation_id
);
1109 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1110 &ctx
->gs_vtx_offset
[4]);
1112 if (previous_stage
== MESA_SHADER_VERTEX
) {
1113 declare_vs_input_vgprs(ctx
, &args
);
1115 declare_tes_input_vgprs(ctx
, &args
);
1118 declare_global_input_sgprs(ctx
, stage
,
1121 &user_sgpr_info
, &args
,
1124 if (needs_view_index
)
1125 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1126 &ctx
->abi
.view_index
);
1128 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1129 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1130 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1131 &ctx
->gs_vtx_offset
[0]);
1132 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1133 &ctx
->gs_vtx_offset
[1]);
1134 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1135 &ctx
->abi
.gs_prim_id
);
1136 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1137 &ctx
->gs_vtx_offset
[2]);
1138 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1139 &ctx
->gs_vtx_offset
[3]);
1140 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1141 &ctx
->gs_vtx_offset
[4]);
1142 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1143 &ctx
->gs_vtx_offset
[5]);
1144 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1145 &ctx
->abi
.gs_invocation_id
);
1148 case MESA_SHADER_FRAGMENT
:
1149 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
1150 previous_stage
, &user_sgpr_info
,
1153 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1154 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1155 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1156 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1157 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1158 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1159 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1160 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1161 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1162 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1163 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1164 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1165 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1166 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1167 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1168 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1169 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1172 unreachable("Shader stage not implemented");
1175 ctx
->main_function
= create_llvm_function(
1176 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1177 ctx
->max_workgroup_size
, ctx
->options
);
1178 set_llvm_calling_convention(ctx
->main_function
, stage
);
1181 ctx
->shader_info
->num_input_vgprs
= 0;
1182 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1184 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1186 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1187 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1189 assign_arguments(ctx
->main_function
, &args
);
1193 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1194 set_loc_shader_ptr(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1196 if (ctx
->options
->supports_spill
) {
1197 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1198 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
1199 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1200 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1201 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1205 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1206 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1207 if (has_previous_stage
)
1210 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1211 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1214 case MESA_SHADER_COMPUTE
:
1215 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1216 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1220 case MESA_SHADER_VERTEX
:
1221 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1222 previous_stage
, &user_sgpr_idx
);
1223 if (ctx
->abi
.view_index
)
1224 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1226 case MESA_SHADER_TESS_CTRL
:
1227 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1228 previous_stage
, &user_sgpr_idx
);
1229 if (ctx
->abi
.view_index
)
1230 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1232 case MESA_SHADER_TESS_EVAL
:
1233 if (ctx
->abi
.view_index
)
1234 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1236 case MESA_SHADER_GEOMETRY
:
1237 if (has_previous_stage
) {
1238 if (previous_stage
== MESA_SHADER_VERTEX
)
1239 set_vs_specific_input_locs(ctx
, stage
,
1244 if (ctx
->abi
.view_index
)
1245 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1247 case MESA_SHADER_FRAGMENT
:
1250 unreachable("Shader stage not implemented");
1253 if (stage
== MESA_SHADER_TESS_CTRL
||
1254 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_ls
) ||
1255 /* GFX9 has the ESGS ring buffer in LDS. */
1256 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1257 ac_declare_lds_as_pointer(&ctx
->ac
);
1260 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1265 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1266 unsigned desc_set
, unsigned binding
)
1268 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1269 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1270 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
1271 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1272 unsigned base_offset
= layout
->binding
[binding
].offset
;
1273 LLVMValueRef offset
, stride
;
1275 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1276 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1277 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1278 layout
->binding
[binding
].dynamic_offset_offset
;
1279 desc_ptr
= ctx
->abi
.push_constants
;
1280 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1281 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1283 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1285 offset
= ac_build_imad(&ctx
->ac
, index
, stride
,
1286 LLVMConstInt(ctx
->ac
.i32
, base_offset
, false));
1288 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
1289 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1290 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1296 /* The offchip buffer layout for TCS->TES is
1298 * - attribute 0 of patch 0 vertex 0
1299 * - attribute 0 of patch 0 vertex 1
1300 * - attribute 0 of patch 0 vertex 2
1302 * - attribute 0 of patch 1 vertex 0
1303 * - attribute 0 of patch 1 vertex 1
1305 * - attribute 1 of patch 0 vertex 0
1306 * - attribute 1 of patch 0 vertex 1
1308 * - per patch attribute 0 of patch 0
1309 * - per patch attribute 0 of patch 1
1312 * Note that every attribute has 4 components.
1314 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1316 uint32_t num_patches
= ctx
->tcs_num_patches
;
1317 uint32_t num_tcs_outputs
;
1318 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1319 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
1321 num_tcs_outputs
= ctx
->options
->key
.tes
.tcs_num_outputs
;
1323 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1324 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
1326 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1329 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1330 LLVMValueRef vertex_index
)
1332 LLVMValueRef param_stride
;
1334 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
* ctx
->tcs_num_patches
, false);
1336 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1337 return param_stride
;
1340 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1341 LLVMValueRef vertex_index
,
1342 LLVMValueRef param_index
)
1344 LLVMValueRef base_addr
;
1345 LLVMValueRef param_stride
, constant16
;
1346 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1347 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
1348 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1349 param_stride
= calc_param_stride(ctx
, vertex_index
);
1351 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
1352 vertices_per_patch
, vertex_index
);
1354 base_addr
= rel_patch_id
;
1357 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1358 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1359 param_stride
, ""), "");
1361 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1363 if (!vertex_index
) {
1364 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1366 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1367 patch_data_offset
, "");
1372 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1374 unsigned const_index
,
1376 LLVMValueRef vertex_index
,
1377 LLVMValueRef indir_index
)
1379 LLVMValueRef param_index
;
1382 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1385 if (const_index
&& !is_compact
)
1386 param
+= const_index
;
1387 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1389 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1393 get_dw_address(struct radv_shader_context
*ctx
,
1394 LLVMValueRef dw_addr
,
1396 unsigned const_index
,
1397 bool compact_const_index
,
1398 LLVMValueRef vertex_index
,
1399 LLVMValueRef stride
,
1400 LLVMValueRef indir_index
)
1405 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1406 LLVMBuildMul(ctx
->ac
.builder
,
1412 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1413 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1414 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1415 else if (const_index
&& !compact_const_index
)
1416 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1417 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1419 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1420 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1422 if (const_index
&& compact_const_index
)
1423 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1424 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1429 load_tcs_varyings(struct ac_shader_abi
*abi
,
1431 LLVMValueRef vertex_index
,
1432 LLVMValueRef indir_index
,
1433 unsigned const_index
,
1435 unsigned driver_location
,
1437 unsigned num_components
,
1442 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1443 LLVMValueRef dw_addr
, stride
;
1444 LLVMValueRef value
[4], result
;
1445 unsigned param
= shader_io_get_unique_index(location
);
1448 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1449 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1450 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1453 stride
= get_tcs_out_vertex_stride(ctx
);
1454 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1456 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1461 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1464 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1465 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1466 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1469 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1474 store_tcs_output(struct ac_shader_abi
*abi
,
1475 const nir_variable
*var
,
1476 LLVMValueRef vertex_index
,
1477 LLVMValueRef param_index
,
1478 unsigned const_index
,
1482 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1483 const unsigned location
= var
->data
.location
;
1484 const unsigned component
= var
->data
.location_frac
;
1485 const bool is_patch
= var
->data
.patch
;
1486 const bool is_compact
= var
->data
.compact
;
1487 LLVMValueRef dw_addr
;
1488 LLVMValueRef stride
= NULL
;
1489 LLVMValueRef buf_addr
= NULL
;
1491 bool store_lds
= true;
1494 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1497 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
1501 param
= shader_io_get_unique_index(location
);
1502 if (location
== VARYING_SLOT_CLIP_DIST0
&&
1503 is_compact
&& const_index
> 3) {
1509 stride
= get_tcs_out_vertex_stride(ctx
);
1510 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1512 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1515 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1517 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1518 vertex_index
, param_index
);
1520 bool is_tess_factor
= false;
1521 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1522 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1523 is_tess_factor
= true;
1525 unsigned base
= is_compact
? const_index
: 0;
1526 for (unsigned chan
= 0; chan
< 8; chan
++) {
1527 if (!(writemask
& (1 << chan
)))
1529 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1530 value
= ac_to_integer(&ctx
->ac
, value
);
1531 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
1533 if (store_lds
|| is_tess_factor
) {
1534 LLVMValueRef dw_addr_chan
=
1535 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1536 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1537 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1540 if (!is_tess_factor
&& writemask
!= 0xF)
1541 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1542 buf_addr
, ctx
->oc_lds
,
1543 4 * (base
+ chan
), 1, 0, true, false);
1546 if (writemask
== 0xF) {
1547 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1548 buf_addr
, ctx
->oc_lds
,
1549 (base
* 4), 1, 0, true, false);
1554 load_tes_input(struct ac_shader_abi
*abi
,
1556 LLVMValueRef vertex_index
,
1557 LLVMValueRef param_index
,
1558 unsigned const_index
,
1560 unsigned driver_location
,
1562 unsigned num_components
,
1567 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1568 LLVMValueRef buf_addr
;
1569 LLVMValueRef result
;
1570 unsigned param
= shader_io_get_unique_index(location
);
1572 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
1577 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1578 is_compact
, vertex_index
, param_index
);
1580 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1581 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1583 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1584 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
1585 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1590 load_gs_input(struct ac_shader_abi
*abi
,
1592 unsigned driver_location
,
1594 unsigned num_components
,
1595 unsigned vertex_index
,
1596 unsigned const_index
,
1599 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1600 LLVMValueRef vtx_offset
;
1601 unsigned param
, vtx_offset_param
;
1602 LLVMValueRef value
[4], result
;
1604 vtx_offset_param
= vertex_index
;
1605 assert(vtx_offset_param
< 6);
1606 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1607 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1609 param
= shader_io_get_unique_index(location
);
1611 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1612 if (ctx
->ac
.chip_class
>= GFX9
) {
1613 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1614 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1615 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1616 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1618 LLVMValueRef soffset
=
1619 LLVMConstInt(ctx
->ac
.i32
,
1620 (param
* 4 + i
+ const_index
) * 256,
1623 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1626 vtx_offset
, soffset
,
1627 0, 1, 0, true, false);
1630 if (ac_get_type_size(type
) == 2) {
1631 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
1632 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
1634 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
1636 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1637 result
= ac_to_integer(&ctx
->ac
, result
);
1642 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1644 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1645 ac_build_kill_if_false(&ctx
->ac
, visible
);
1648 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
1649 enum glsl_interp_mode interp
, unsigned location
)
1651 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1654 case INTERP_MODE_FLAT
:
1657 case INTERP_MODE_SMOOTH
:
1658 case INTERP_MODE_NONE
:
1659 if (location
== INTERP_CENTER
)
1660 return ctx
->persp_center
;
1661 else if (location
== INTERP_CENTROID
)
1662 return ctx
->persp_centroid
;
1663 else if (location
== INTERP_SAMPLE
)
1664 return ctx
->persp_sample
;
1666 case INTERP_MODE_NOPERSPECTIVE
:
1667 if (location
== INTERP_CENTER
)
1668 return ctx
->linear_center
;
1669 else if (location
== INTERP_CENTROID
)
1670 return ctx
->linear_centroid
;
1671 else if (location
== INTERP_SAMPLE
)
1672 return ctx
->linear_sample
;
1679 radv_get_sample_pos_offset(uint32_t num_samples
)
1681 uint32_t sample_pos_offset
= 0;
1683 switch (num_samples
) {
1685 sample_pos_offset
= 1;
1688 sample_pos_offset
= 3;
1691 sample_pos_offset
= 7;
1696 return sample_pos_offset
;
1699 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1700 LLVMValueRef sample_id
)
1702 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1704 LLVMValueRef result
;
1705 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
1707 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1708 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1710 uint32_t sample_pos_offset
=
1711 radv_get_sample_pos_offset(ctx
->options
->key
.fs
.num_samples
);
1714 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
1715 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
1716 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1722 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1724 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1725 uint8_t log2_ps_iter_samples
;
1727 if (ctx
->shader_info
->info
.ps
.force_persample
) {
1728 log2_ps_iter_samples
=
1729 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
1731 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
1734 /* The bit pattern matches that used by fixed function fragment
1736 static const uint16_t ps_iter_masks
[] = {
1737 0xffff, /* not used */
1743 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1745 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1747 LLVMValueRef result
, sample_id
;
1748 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
1749 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1750 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
1756 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1758 LLVMValueRef gs_next_vertex
;
1759 LLVMValueRef can_emit
;
1760 unsigned offset
= 0;
1761 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1763 /* Write vertex attribute values to GSVS ring */
1764 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1765 ctx
->gs_next_vertex
[stream
],
1768 /* If this thread has already emitted the declared maximum number of
1769 * vertices, kill it: excessive vertex emissions are not supposed to
1770 * have any effect, and GS threads have no externally observable
1771 * effects other than emitting vertices.
1773 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1774 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
1775 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1777 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1778 unsigned output_usage_mask
=
1779 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
1780 uint8_t output_stream
=
1781 ctx
->shader_info
->info
.gs
.output_streams
[i
];
1782 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1783 int length
= util_last_bit(output_usage_mask
);
1785 if (!(ctx
->output_mask
& (1ull << i
)) ||
1786 output_stream
!= stream
)
1789 for (unsigned j
= 0; j
< length
; j
++) {
1790 if (!(output_usage_mask
& (1 << j
)))
1793 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1795 LLVMValueRef voffset
=
1796 LLVMConstInt(ctx
->ac
.i32
, offset
*
1797 ctx
->gs_max_out_vertices
, false);
1801 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1802 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1804 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1805 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1807 ac_build_buffer_store_dword(&ctx
->ac
,
1808 ctx
->gsvs_ring
[stream
],
1810 voffset
, ctx
->gs2vs_offset
, 0,
1815 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1817 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1819 ac_build_sendmsg(&ctx
->ac
,
1820 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1825 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1827 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1828 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1832 load_tess_coord(struct ac_shader_abi
*abi
)
1834 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1836 LLVMValueRef coord
[4] = {
1843 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
1844 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1845 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1847 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1851 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1853 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1854 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
1858 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1860 return abi
->base_vertex
;
1863 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1864 LLVMValueRef buffer_ptr
, bool write
)
1866 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1867 LLVMValueRef result
;
1869 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1871 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1872 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1877 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1879 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1880 LLVMValueRef result
;
1882 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1884 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1885 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1890 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1891 unsigned descriptor_set
,
1892 unsigned base_index
,
1893 unsigned constant_index
,
1895 enum ac_descriptor_type desc_type
,
1896 bool image
, bool write
,
1899 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1900 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1901 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
1902 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1903 unsigned offset
= binding
->offset
;
1904 unsigned stride
= binding
->size
;
1906 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1909 assert(base_index
< layout
->binding_count
);
1911 switch (desc_type
) {
1913 type
= ctx
->ac
.v8i32
;
1917 type
= ctx
->ac
.v8i32
;
1921 case AC_DESC_SAMPLER
:
1922 type
= ctx
->ac
.v4i32
;
1923 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1928 case AC_DESC_BUFFER
:
1929 type
= ctx
->ac
.v4i32
;
1933 unreachable("invalid desc_type\n");
1936 offset
+= constant_index
* stride
;
1938 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
1939 (!index
|| binding
->immutable_samplers_equal
)) {
1940 if (binding
->immutable_samplers_equal
)
1943 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
1945 LLVMValueRef constants
[] = {
1946 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
1947 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
1948 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
1949 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
1951 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
1954 assert(stride
% type_size
== 0);
1957 index
= ctx
->ac
.i32_0
;
1959 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
1961 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
1962 list
= LLVMBuildPointerCast(builder
, list
,
1963 ac_array_in_const32_addr_space(type
), "");
1965 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
1968 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1969 * so we may need to fix it up. */
1971 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
1972 unsigned adjustment
,
1975 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
1978 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
1980 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
1981 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1983 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
1985 /* For the integer-like cases, do a natural sign extension.
1987 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1988 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1991 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
1992 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
1993 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
1994 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
1996 /* Convert back to the right type. */
1997 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
1999 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
2000 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2001 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
2002 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
2003 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
2004 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2011 handle_vs_input_decl(struct radv_shader_context
*ctx
,
2012 struct nir_variable
*variable
)
2014 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
2015 LLVMValueRef t_offset
;
2016 LLVMValueRef t_list
;
2018 LLVMValueRef buffer_index
;
2019 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
2020 uint8_t input_usage_mask
=
2021 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
2022 unsigned num_channels
= util_last_bit(input_usage_mask
);
2024 variable
->data
.driver_location
= variable
->data
.location
* 4;
2026 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
2027 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
2028 LLVMValueRef output
[4];
2029 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
2031 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
2032 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
2035 buffer_index
= ctx
->abi
.instance_id
;
2038 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
2039 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
2042 if (ctx
->options
->key
.vs
.as_ls
) {
2043 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
2044 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
2046 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
2047 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
2050 buffer_index
= ctx
->ac
.i32_0
;
2053 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.start_instance
, buffer_index
, "");
2055 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
2056 ctx
->abi
.base_vertex
, "");
2057 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_index
, false);
2059 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
2061 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
2064 num_channels
, false, true);
2066 input
= ac_build_expand_to_vec4(&ctx
->ac
, input
, num_channels
);
2068 for (unsigned chan
= 0; chan
< 4; chan
++) {
2069 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2070 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
2071 if (type
== GLSL_TYPE_FLOAT16
) {
2072 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
2073 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
2077 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
2078 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
2080 for (unsigned chan
= 0; chan
< 4; chan
++) {
2081 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
2082 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
2083 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
2085 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
2090 static void interp_fs_input(struct radv_shader_context
*ctx
,
2092 LLVMValueRef interp_param
,
2093 LLVMValueRef prim_mask
,
2094 LLVMValueRef result
[4])
2096 LLVMValueRef attr_number
;
2099 bool interp
= !LLVMIsUndef(interp_param
);
2101 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
2103 /* fs.constant returns the param from the middle vertex, so it's not
2104 * really useful for flat shading. It's meant to be used for custom
2105 * interpolation (but the intrinsic can't fetch from the other two
2108 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2109 * to do the right thing. The only reason we use fs.constant is that
2110 * fs.interp cannot be used on integers, because they can be equal
2114 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
2117 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
2119 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
2123 for (chan
= 0; chan
< 4; chan
++) {
2124 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2127 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
2132 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
2133 LLVMConstInt(ctx
->ac
.i32
, 2, false),
2137 result
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, result
[chan
], ctx
->ac
.i32
, "");
2138 result
[chan
] = LLVMBuildTruncOrBitCast(ctx
->ac
.builder
, result
[chan
], LLVMTypeOf(interp_param
), "");
2144 handle_fs_input_decl(struct radv_shader_context
*ctx
,
2145 struct nir_variable
*variable
)
2147 int idx
= variable
->data
.location
;
2148 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2149 LLVMValueRef interp
= NULL
;
2152 variable
->data
.driver_location
= idx
* 4;
2153 mask
= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
2155 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
2156 unsigned interp_type
;
2157 if (variable
->data
.sample
)
2158 interp_type
= INTERP_SAMPLE
;
2159 else if (variable
->data
.centroid
)
2160 interp_type
= INTERP_CENTROID
;
2162 interp_type
= INTERP_CENTER
;
2164 interp
= lookup_interp_param(&ctx
->abi
, variable
->data
.interpolation
, interp_type
);
2166 bool is_16bit
= glsl_type_is_16bit(glsl_without_array(variable
->type
));
2167 LLVMTypeRef type
= is_16bit
? ctx
->ac
.i16
: ctx
->ac
.i32
;
2169 interp
= LLVMGetUndef(type
);
2171 for (unsigned i
= 0; i
< attrib_count
; ++i
)
2172 ctx
->inputs
[ac_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
2174 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2175 /* Do not account for the number of components inside the array
2176 * of clip/cull distances because this might wrongly set other
2177 * bits like primitive ID or layer.
2179 mask
= 1ull << VARYING_SLOT_CLIP_DIST0
;
2182 ctx
->input_mask
|= mask
;
2186 handle_vs_inputs(struct radv_shader_context
*ctx
,
2187 struct nir_shader
*nir
) {
2188 nir_foreach_variable(variable
, &nir
->inputs
)
2189 handle_vs_input_decl(ctx
, variable
);
2193 prepare_interp_optimize(struct radv_shader_context
*ctx
,
2194 struct nir_shader
*nir
)
2196 bool uses_center
= false;
2197 bool uses_centroid
= false;
2198 nir_foreach_variable(variable
, &nir
->inputs
) {
2199 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
2200 variable
->data
.sample
)
2203 if (variable
->data
.centroid
)
2204 uses_centroid
= true;
2209 if (uses_center
&& uses_centroid
) {
2210 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
2211 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
2212 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
2217 handle_fs_inputs(struct radv_shader_context
*ctx
,
2218 struct nir_shader
*nir
)
2220 prepare_interp_optimize(ctx
, nir
);
2222 nir_foreach_variable(variable
, &nir
->inputs
)
2223 handle_fs_input_decl(ctx
, variable
);
2227 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
2228 ctx
->shader_info
->info
.needs_multiview_view_index
) {
2229 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
2230 ctx
->inputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)] = LLVMGetUndef(ctx
->ac
.i32
);
2233 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
2234 LLVMValueRef interp_param
;
2235 LLVMValueRef
*inputs
= ctx
->inputs
+ac_llvm_reg_index_soa(i
, 0);
2237 if (!(ctx
->input_mask
& (1ull << i
)))
2240 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
2241 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
2242 interp_param
= *inputs
;
2243 interp_fs_input(ctx
, index
, interp_param
, ctx
->abi
.prim_mask
,
2246 if (LLVMIsUndef(interp_param
))
2247 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
2248 if (i
>= VARYING_SLOT_VAR0
)
2249 ctx
->abi
.fs_input_attr_indices
[i
- VARYING_SLOT_VAR0
] = index
;
2251 } else if (i
== VARYING_SLOT_CLIP_DIST0
) {
2252 int length
= ctx
->shader_info
->info
.ps
.num_input_clips_culls
;
2254 for (unsigned j
= 0; j
< length
; j
+= 4) {
2255 inputs
= ctx
->inputs
+ ac_llvm_reg_index_soa(i
, j
);
2257 interp_param
= *inputs
;
2258 interp_fs_input(ctx
, index
, interp_param
,
2259 ctx
->abi
.prim_mask
, inputs
);
2262 } else if (i
== VARYING_SLOT_POS
) {
2263 for(int i
= 0; i
< 3; ++i
)
2264 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
2266 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
2267 ctx
->abi
.frag_pos
[3]);
2270 ctx
->shader_info
->fs
.num_interp
= index
;
2271 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
2273 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
2274 ctx
->abi
.view_index
= ctx
->inputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2278 scan_shader_output_decl(struct radv_shader_context
*ctx
,
2279 struct nir_variable
*variable
,
2280 struct nir_shader
*shader
,
2281 gl_shader_stage stage
)
2283 int idx
= variable
->data
.location
+ variable
->data
.index
;
2284 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2285 uint64_t mask_attribs
;
2287 variable
->data
.driver_location
= idx
* 4;
2289 /* tess ctrl has it's own load/store paths for outputs */
2290 if (stage
== MESA_SHADER_TESS_CTRL
)
2293 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2294 if (stage
== MESA_SHADER_VERTEX
||
2295 stage
== MESA_SHADER_TESS_EVAL
||
2296 stage
== MESA_SHADER_GEOMETRY
) {
2297 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2298 if (stage
== MESA_SHADER_VERTEX
) {
2299 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2300 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2301 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2303 if (stage
== MESA_SHADER_TESS_EVAL
) {
2304 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2305 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2306 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2309 mask_attribs
= 1ull << idx
;
2313 ctx
->output_mask
|= mask_attribs
;
2317 /* Initialize arguments for the shader export intrinsic */
2319 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2320 LLVMValueRef
*values
,
2321 unsigned enabled_channels
,
2323 struct ac_export_args
*args
)
2325 /* Specify the channels that are enabled. */
2326 args
->enabled_channels
= enabled_channels
;
2328 /* Specify whether the EXEC mask represents the valid mask */
2329 args
->valid_mask
= 0;
2331 /* Specify whether this is the last export */
2334 /* Specify the target we are exporting */
2335 args
->target
= target
;
2337 args
->compr
= false;
2338 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2339 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2340 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2341 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2346 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
2347 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2348 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2349 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2350 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2351 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2354 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2355 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2356 unsigned bits
, bool hi
) = NULL
;
2358 switch(col_format
) {
2359 case V_028714_SPI_SHADER_ZERO
:
2360 args
->enabled_channels
= 0; /* writemask */
2361 args
->target
= V_008DFC_SQ_EXP_NULL
;
2364 case V_028714_SPI_SHADER_32_R
:
2365 args
->enabled_channels
= 1;
2366 args
->out
[0] = values
[0];
2369 case V_028714_SPI_SHADER_32_GR
:
2370 args
->enabled_channels
= 0x3;
2371 args
->out
[0] = values
[0];
2372 args
->out
[1] = values
[1];
2375 case V_028714_SPI_SHADER_32_AR
:
2376 args
->enabled_channels
= 0x9;
2377 args
->out
[0] = values
[0];
2378 args
->out
[3] = values
[3];
2381 case V_028714_SPI_SHADER_FP16_ABGR
:
2382 args
->enabled_channels
= 0x5;
2383 packf
= ac_build_cvt_pkrtz_f16
;
2385 for (unsigned chan
= 0; chan
< 4; chan
++)
2386 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
2392 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2393 args
->enabled_channels
= 0x5;
2394 packf
= ac_build_cvt_pknorm_u16
;
2397 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2398 args
->enabled_channels
= 0x5;
2399 packf
= ac_build_cvt_pknorm_i16
;
2402 case V_028714_SPI_SHADER_UINT16_ABGR
:
2403 args
->enabled_channels
= 0x5;
2404 packi
= ac_build_cvt_pk_u16
;
2406 for (unsigned chan
= 0; chan
< 4; chan
++)
2407 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
2413 case V_028714_SPI_SHADER_SINT16_ABGR
:
2414 args
->enabled_channels
= 0x5;
2415 packi
= ac_build_cvt_pk_i16
;
2417 for (unsigned chan
= 0; chan
< 4; chan
++)
2418 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
2425 case V_028714_SPI_SHADER_32_ABGR
:
2426 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2430 /* Pack f16 or norm_i16/u16. */
2432 for (chan
= 0; chan
< 2; chan
++) {
2433 LLVMValueRef pack_args
[2] = {
2435 values
[2 * chan
+ 1]
2437 LLVMValueRef packed
;
2439 packed
= packf(&ctx
->ac
, pack_args
);
2440 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2442 args
->compr
= 1; /* COMPR flag */
2447 for (chan
= 0; chan
< 2; chan
++) {
2448 LLVMValueRef pack_args
[2] = {
2449 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2450 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2452 LLVMValueRef packed
;
2454 packed
= packi(&ctx
->ac
, pack_args
,
2455 is_int8
? 8 : is_int10
? 10 : 16,
2457 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2459 args
->compr
= 1; /* COMPR flag */
2465 for (unsigned chan
= 0; chan
< 4; chan
++) {
2466 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
2467 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
2470 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2472 for (unsigned i
= 0; i
< 4; ++i
) {
2473 if (!(args
->enabled_channels
& (1 << i
)))
2476 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2481 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2482 LLVMValueRef
*values
, unsigned enabled_channels
)
2484 struct ac_export_args args
;
2486 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2487 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2488 ac_build_export(&ctx
->ac
, &args
);
2492 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2494 LLVMValueRef output
=
2495 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2497 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2501 radv_emit_stream_output(struct radv_shader_context
*ctx
,
2502 LLVMValueRef
const *so_buffers
,
2503 LLVMValueRef
const *so_write_offsets
,
2504 const struct radv_stream_output
*output
)
2506 unsigned num_comps
= util_bitcount(output
->component_mask
);
2507 unsigned loc
= output
->location
;
2508 unsigned buf
= output
->buffer
;
2509 unsigned offset
= output
->offset
;
2511 LLVMValueRef out
[4];
2513 assert(num_comps
&& num_comps
<= 4);
2514 if (!num_comps
|| num_comps
> 4)
2517 /* Get the first component. */
2518 start
= ffs(output
->component_mask
) - 1;
2520 /* Load the output as int. */
2521 for (int i
= 0; i
< num_comps
; i
++) {
2522 out
[i
] = ac_to_integer(&ctx
->ac
,
2523 radv_load_output(ctx
, loc
, start
+ i
));
2526 /* Pack the output. */
2527 LLVMValueRef vdata
= NULL
;
2529 switch (num_comps
) {
2530 case 1: /* as i32 */
2533 case 2: /* as v2i32 */
2534 case 3: /* as v4i32 (aligned to 4) */
2535 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
2537 case 4: /* as v4i32 */
2538 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
2539 util_next_power_of_two(num_comps
));
2543 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
2544 vdata
, num_comps
, so_write_offsets
[buf
],
2545 ctx
->ac
.i32_0
, offset
,
2550 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
2552 struct ac_build_if_state if_ctx
;
2555 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2556 assert(ctx
->streamout_config
);
2557 LLVMValueRef so_vtx_count
=
2558 ac_build_bfe(&ctx
->ac
, ctx
->streamout_config
,
2559 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2560 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
2562 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2564 /* can_emit = tid < so_vtx_count; */
2565 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
2566 tid
, so_vtx_count
, "");
2568 /* Emit the streamout code conditionally. This actually avoids
2569 * out-of-bounds buffer access. The hw tells us via the SGPR
2570 * (so_vtx_count) which threads are allowed to emit streamout data.
2572 ac_nir_build_if(&if_ctx
, ctx
, can_emit
);
2574 /* The buffer offset is computed as follows:
2575 * ByteOffset = streamout_offset[buffer_id]*4 +
2576 * (streamout_write_index + thread_id)*stride[buffer_id] +
2579 LLVMValueRef so_write_index
= ctx
->streamout_write_idx
;
2581 /* Compute (streamout_write_index + thread_id). */
2583 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
2585 /* Load the descriptor and compute the write offset for each
2588 LLVMValueRef so_write_offset
[4] = {};
2589 LLVMValueRef so_buffers
[4] = {};
2590 LLVMValueRef buf_ptr
= ctx
->streamout_buffers
;
2592 for (i
= 0; i
< 4; i
++) {
2593 uint16_t stride
= ctx
->shader_info
->info
.so
.strides
[i
];
2598 LLVMValueRef offset
=
2599 LLVMConstInt(ctx
->ac
.i32
, i
, false);
2601 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
2604 LLVMValueRef so_offset
= ctx
->streamout_offset
[i
];
2606 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
2607 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2609 so_write_offset
[i
] =
2610 ac_build_imad(&ctx
->ac
, so_write_index
,
2611 LLVMConstInt(ctx
->ac
.i32
,
2616 /* Write streamout data. */
2617 for (i
= 0; i
< ctx
->shader_info
->info
.so
.num_outputs
; i
++) {
2618 struct radv_stream_output
*output
=
2619 &ctx
->shader_info
->info
.so
.outputs
[i
];
2621 if (stream
!= output
->stream
)
2624 radv_emit_stream_output(ctx
, so_buffers
,
2625 so_write_offset
, output
);
2628 ac_nir_build_endif(&if_ctx
);
2632 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2633 bool export_prim_id
, bool export_layer_id
,
2634 struct radv_vs_output_info
*outinfo
)
2636 uint32_t param_count
= 0;
2638 unsigned pos_idx
, num_pos_exports
= 0;
2639 struct ac_export_args args
, pos_args
[4] = {};
2640 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2643 if (ctx
->options
->key
.has_multiview_view_index
) {
2644 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2646 for(unsigned i
= 0; i
< 4; ++i
)
2647 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2648 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2651 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
2652 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2655 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2656 sizeof(outinfo
->vs_output_param_offset
));
2658 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
2659 unsigned output_usage_mask
, length
;
2660 LLVMValueRef slots
[8];
2663 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2664 !ctx
->is_gs_copy_shader
) {
2666 ctx
->shader_info
->info
.vs
.output_usage_mask
[VARYING_SLOT_CLIP_DIST0
];
2667 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2669 ctx
->shader_info
->info
.tes
.output_usage_mask
[VARYING_SLOT_CLIP_DIST0
];
2671 assert(ctx
->is_gs_copy_shader
);
2673 ctx
->shader_info
->info
.gs
.output_usage_mask
[VARYING_SLOT_CLIP_DIST0
];
2676 length
= util_last_bit(output_usage_mask
);
2678 i
= VARYING_SLOT_CLIP_DIST0
;
2679 for (j
= 0; j
< length
; j
++)
2680 slots
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2682 for (i
= length
; i
< 8; i
++)
2683 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
2686 target
= V_008DFC_SQ_EXP_POS
+ 3;
2687 si_llvm_init_export_args(ctx
, &slots
[4], 0xf, target
, &args
);
2688 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2689 &args
, sizeof(args
));
2692 target
= V_008DFC_SQ_EXP_POS
+ 2;
2693 si_llvm_init_export_args(ctx
, &slots
[0], 0xf, target
, &args
);
2694 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2695 &args
, sizeof(args
));
2697 /* Export the clip/cull distances values to the next stage. */
2698 radv_export_param(ctx
, param_count
, &slots
[0], 0xf);
2699 outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
] = param_count
++;
2701 radv_export_param(ctx
, param_count
, &slots
[4], 0xf);
2702 outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
] = param_count
++;
2706 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
2707 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
2708 for (unsigned j
= 0; j
< 4; j
++)
2709 pos_values
[j
] = radv_load_output(ctx
, VARYING_SLOT_POS
, j
);
2711 si_llvm_init_export_args(ctx
, pos_values
, 0xf, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2713 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
2714 outinfo
->writes_pointsize
= true;
2715 psize_value
= radv_load_output(ctx
, VARYING_SLOT_PSIZ
, 0);
2718 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
2719 outinfo
->writes_layer
= true;
2720 layer_value
= radv_load_output(ctx
, VARYING_SLOT_LAYER
, 0);
2723 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
2724 outinfo
->writes_viewport_index
= true;
2725 viewport_index_value
= radv_load_output(ctx
, VARYING_SLOT_VIEWPORT
, 0);
2728 if (ctx
->shader_info
->info
.so
.num_outputs
&&
2729 !ctx
->is_gs_copy_shader
) {
2730 /* The GS copy shader emission already emits streamout. */
2731 radv_emit_streamout(ctx
, 0);
2734 if (outinfo
->writes_pointsize
||
2735 outinfo
->writes_layer
||
2736 outinfo
->writes_viewport_index
) {
2737 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2738 (outinfo
->writes_layer
== true ? 4 : 0));
2739 pos_args
[1].valid_mask
= 0;
2740 pos_args
[1].done
= 0;
2741 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2742 pos_args
[1].compr
= 0;
2743 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2744 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2745 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2746 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2748 if (outinfo
->writes_pointsize
== true)
2749 pos_args
[1].out
[0] = psize_value
;
2750 if (outinfo
->writes_layer
== true)
2751 pos_args
[1].out
[2] = layer_value
;
2752 if (outinfo
->writes_viewport_index
== true) {
2753 if (ctx
->options
->chip_class
>= GFX9
) {
2754 /* GFX9 has the layer in out.z[10:0] and the viewport
2755 * index in out.z[19:16].
2757 LLVMValueRef v
= viewport_index_value
;
2758 v
= ac_to_integer(&ctx
->ac
, v
);
2759 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2760 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2762 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2763 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2765 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2766 pos_args
[1].enabled_channels
|= 1 << 2;
2768 pos_args
[1].out
[3] = viewport_index_value
;
2769 pos_args
[1].enabled_channels
|= 1 << 3;
2773 for (i
= 0; i
< 4; i
++) {
2774 if (pos_args
[i
].out
[0])
2779 for (i
= 0; i
< 4; i
++) {
2780 if (!pos_args
[i
].out
[0])
2783 /* Specify the target we are exporting */
2784 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2785 if (pos_idx
== num_pos_exports
)
2786 pos_args
[i
].done
= 1;
2787 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2790 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2791 LLVMValueRef values
[4];
2792 if (!(ctx
->output_mask
& (1ull << i
)))
2795 if (i
!= VARYING_SLOT_LAYER
&&
2796 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
2797 i
< VARYING_SLOT_VAR0
)
2800 for (unsigned j
= 0; j
< 4; j
++)
2801 values
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2803 unsigned output_usage_mask
;
2805 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2806 !ctx
->is_gs_copy_shader
) {
2808 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2809 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2811 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2813 assert(ctx
->is_gs_copy_shader
);
2815 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
2818 radv_export_param(ctx
, param_count
, values
, output_usage_mask
);
2820 outinfo
->vs_output_param_offset
[i
] = param_count
++;
2823 if (export_prim_id
) {
2824 LLVMValueRef values
[4];
2826 values
[0] = ctx
->vs_prim_id
;
2827 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
2828 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
2829 for (unsigned j
= 1; j
< 4; j
++)
2830 values
[j
] = ctx
->ac
.f32_0
;
2832 radv_export_param(ctx
, param_count
, values
, 0x1);
2834 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
2835 outinfo
->export_prim_id
= true;
2838 if (export_layer_id
&& layer_value
) {
2839 LLVMValueRef values
[4];
2841 values
[0] = layer_value
;
2842 for (unsigned j
= 1; j
< 4; j
++)
2843 values
[j
] = ctx
->ac
.f32_0
;
2845 radv_export_param(ctx
, param_count
, values
, 0x1);
2847 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
++;
2850 outinfo
->pos_exports
= num_pos_exports
;
2851 outinfo
->param_exports
= param_count
;
2855 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2856 struct radv_es_output_info
*outinfo
)
2859 uint64_t max_output_written
= 0;
2860 LLVMValueRef lds_base
= NULL
;
2862 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2863 unsigned output_usage_mask
;
2867 if (!(ctx
->output_mask
& (1ull << i
)))
2870 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2872 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2874 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2876 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2879 if (i
== VARYING_SLOT_CLIP_DIST0
)
2880 length
= util_last_bit(output_usage_mask
);
2882 param_index
= shader_io_get_unique_index(i
);
2884 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
2887 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
2889 if (ctx
->ac
.chip_class
>= GFX9
) {
2890 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2891 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2892 LLVMValueRef wave_idx
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
2893 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2894 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2895 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
2896 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2897 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2900 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2901 LLVMValueRef dw_addr
= NULL
;
2902 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2903 unsigned output_usage_mask
;
2907 if (!(ctx
->output_mask
& (1ull << i
)))
2910 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2912 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2914 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2916 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2919 if (i
== VARYING_SLOT_CLIP_DIST0
)
2920 length
= util_last_bit(output_usage_mask
);
2922 param_index
= shader_io_get_unique_index(i
);
2925 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2926 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
2930 for (j
= 0; j
< length
; j
++) {
2931 if (!(output_usage_mask
& (1 << j
)))
2934 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2935 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
2936 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
2938 if (ctx
->ac
.chip_class
>= GFX9
) {
2939 LLVMValueRef dw_addr_offset
=
2940 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2941 LLVMConstInt(ctx
->ac
.i32
,
2944 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
2946 ac_build_buffer_store_dword(&ctx
->ac
,
2949 NULL
, ctx
->es2gs_offset
,
2950 (4 * param_index
+ j
) * 4,
2958 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
2960 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
2961 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->shader_info
->info
.vs
.ls_outputs_written
);
2962 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
2963 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
2964 vertex_dw_stride
, "");
2966 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2967 unsigned output_usage_mask
=
2968 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2969 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2972 if (!(ctx
->output_mask
& (1ull << i
)))
2975 if (i
== VARYING_SLOT_CLIP_DIST0
)
2976 length
= util_last_bit(output_usage_mask
);
2978 int param
= shader_io_get_unique_index(i
);
2979 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
2980 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
2982 for (unsigned j
= 0; j
< length
; j
++) {
2983 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2984 value
= ac_to_integer(&ctx
->ac
, value
);
2985 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
2986 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2987 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
2993 write_tess_factors(struct radv_shader_context
*ctx
)
2995 unsigned stride
, outer_comps
, inner_comps
;
2996 struct ac_build_if_state if_ctx
, inner_if_ctx
;
2997 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
2998 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
2999 unsigned tess_inner_index
= 0, tess_outer_index
;
3000 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3001 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3003 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3005 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
3025 ac_nir_build_if(&if_ctx
, ctx
,
3026 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3027 invocation_id
, ctx
->ac
.i32_0
, ""));
3029 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3032 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3033 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3034 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3037 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3038 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3039 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3041 for (i
= 0; i
< 4; i
++) {
3042 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3043 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3047 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3048 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3049 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3051 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3053 for (i
= 0; i
< outer_comps
; i
++) {
3055 ac_lds_load(&ctx
->ac
, lds_outer
);
3056 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3059 for (i
= 0; i
< inner_comps
; i
++) {
3060 inner
[i
] = out
[outer_comps
+i
] =
3061 ac_lds_load(&ctx
->ac
, lds_inner
);
3062 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3067 /* Convert the outputs to vectors for stores. */
3068 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3072 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3075 buffer
= ctx
->hs_ring_tess_factor
;
3076 tf_base
= ctx
->tess_factor_offset
;
3077 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3078 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3079 unsigned tf_offset
= 0;
3081 if (ctx
->options
->chip_class
<= VI
) {
3082 ac_nir_build_if(&inner_if_ctx
, ctx
,
3083 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3084 rel_patch_id
, ctx
->ac
.i32_0
, ""));
3086 /* Store the dynamic HS control word. */
3087 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3088 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3089 1, ctx
->ac
.i32_0
, tf_base
,
3090 0, 1, 0, true, false);
3093 ac_nir_build_endif(&inner_if_ctx
);
3096 /* Store the tessellation factors. */
3097 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3098 MIN2(stride
, 4), byteoffset
, tf_base
,
3099 tf_offset
, 1, 0, true, false);
3101 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3102 stride
- 4, byteoffset
, tf_base
,
3103 16 + tf_offset
, 1, 0, true, false);
3105 //store to offchip for TES to read - only if TES reads them
3106 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
3107 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3108 LLVMValueRef tf_inner_offset
;
3109 unsigned param_outer
, param_inner
;
3111 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3112 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3113 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3115 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3116 util_next_power_of_two(outer_comps
));
3118 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3119 outer_comps
, tf_outer_offset
,
3120 ctx
->oc_lds
, 0, 1, 0, true, false);
3122 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3123 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3124 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3126 inner_vec
= inner_comps
== 1 ? inner
[0] :
3127 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3128 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3129 inner_comps
, tf_inner_offset
,
3130 ctx
->oc_lds
, 0, 1, 0, true, false);
3133 ac_nir_build_endif(&if_ctx
);
3137 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3139 write_tess_factors(ctx
);
3143 si_export_mrt_color(struct radv_shader_context
*ctx
,
3144 LLVMValueRef
*color
, unsigned index
,
3145 struct ac_export_args
*args
)
3148 si_llvm_init_export_args(ctx
, color
, 0xf,
3149 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3150 if (!args
->enabled_channels
)
3151 return false; /* unnecessary NULL export */
3157 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3158 LLVMValueRef depth
, LLVMValueRef stencil
,
3159 LLVMValueRef samplemask
)
3161 struct ac_export_args args
;
3163 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3165 ac_build_export(&ctx
->ac
, &args
);
3169 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3172 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3173 struct ac_export_args color_args
[8];
3175 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3176 LLVMValueRef values
[4];
3178 if (!(ctx
->output_mask
& (1ull << i
)))
3181 if (i
< FRAG_RESULT_DATA0
)
3184 for (unsigned j
= 0; j
< 4; j
++)
3185 values
[j
] = ac_to_float(&ctx
->ac
,
3186 radv_load_output(ctx
, i
, j
));
3188 bool ret
= si_export_mrt_color(ctx
, values
,
3189 i
- FRAG_RESULT_DATA0
,
3190 &color_args
[index
]);
3195 /* Process depth, stencil, samplemask. */
3196 if (ctx
->shader_info
->info
.ps
.writes_z
) {
3197 depth
= ac_to_float(&ctx
->ac
,
3198 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3200 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
3201 stencil
= ac_to_float(&ctx
->ac
,
3202 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
3204 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3205 samplemask
= ac_to_float(&ctx
->ac
,
3206 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
3209 /* Set the DONE bit on last non-null color export only if Z isn't
3213 !ctx
->shader_info
->info
.ps
.writes_z
&&
3214 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
3215 !ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3216 unsigned last
= index
- 1;
3218 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
3219 color_args
[last
].done
= 1; /* DONE bit */
3222 /* Export PS outputs. */
3223 for (unsigned i
= 0; i
< index
; i
++)
3224 ac_build_export(&ctx
->ac
, &color_args
[i
]);
3226 if (depth
|| stencil
|| samplemask
)
3227 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
3229 ac_build_export_null(&ctx
->ac
);
3233 emit_gs_epilogue(struct radv_shader_context
*ctx
)
3235 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
3239 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
3240 LLVMValueRef
*addrs
)
3242 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3244 switch (ctx
->stage
) {
3245 case MESA_SHADER_VERTEX
:
3246 if (ctx
->options
->key
.vs
.as_ls
)
3247 handle_ls_outputs_post(ctx
);
3248 else if (ctx
->options
->key
.vs
.as_es
)
3249 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
3251 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
3252 ctx
->options
->key
.vs
.export_layer_id
,
3253 &ctx
->shader_info
->vs
.outinfo
);
3255 case MESA_SHADER_FRAGMENT
:
3256 handle_fs_outputs_post(ctx
);
3258 case MESA_SHADER_GEOMETRY
:
3259 emit_gs_epilogue(ctx
);
3261 case MESA_SHADER_TESS_CTRL
:
3262 handle_tcs_outputs_post(ctx
);
3264 case MESA_SHADER_TESS_EVAL
:
3265 if (ctx
->options
->key
.tes
.as_es
)
3266 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
3268 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
3269 ctx
->options
->key
.tes
.export_layer_id
,
3270 &ctx
->shader_info
->tes
.outinfo
);
3277 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
3278 LLVMPassManagerRef passmgr
,
3279 const struct radv_nir_compiler_options
*options
)
3281 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
3282 LLVMDisposeBuilder(ctx
->ac
.builder
);
3284 ac_llvm_context_dispose(&ctx
->ac
);
3288 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
3290 struct radv_vs_output_info
*outinfo
;
3292 switch (ctx
->stage
) {
3293 case MESA_SHADER_FRAGMENT
:
3294 case MESA_SHADER_COMPUTE
:
3295 case MESA_SHADER_TESS_CTRL
:
3296 case MESA_SHADER_GEOMETRY
:
3298 case MESA_SHADER_VERTEX
:
3299 if (ctx
->options
->key
.vs
.as_ls
||
3300 ctx
->options
->key
.vs
.as_es
)
3302 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
3304 case MESA_SHADER_TESS_EVAL
:
3305 if (ctx
->options
->key
.vs
.as_es
)
3307 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
3310 unreachable("Unhandled shader type");
3313 ac_optimize_vs_outputs(&ctx
->ac
,
3315 outinfo
->vs_output_param_offset
,
3317 &outinfo
->param_exports
);
3321 ac_setup_rings(struct radv_shader_context
*ctx
)
3323 if (ctx
->options
->chip_class
<= VI
&&
3324 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
3325 ctx
->options
->key
.vs
.as_es
|| ctx
->options
->key
.tes
.as_es
)) {
3326 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
3328 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
3330 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
3335 if (ctx
->is_gs_copy_shader
) {
3337 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3338 LLVMConstInt(ctx
->ac
.i32
,
3339 RING_GSVS_VS
, false));
3342 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3343 /* The conceptual layout of the GSVS ring is
3344 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3345 * but the real memory layout is swizzled across
3347 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3349 * Override the buffer descriptor accordingly.
3351 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
3352 uint64_t stream_offset
= 0;
3353 unsigned num_records
= 64;
3354 LLVMValueRef base_ring
;
3357 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3358 LLVMConstInt(ctx
->ac
.i32
,
3359 RING_GSVS_GS
, false));
3361 for (unsigned stream
= 0; stream
< 4; stream
++) {
3362 unsigned num_components
, stride
;
3363 LLVMValueRef ring
, tmp
;
3366 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
3368 if (!num_components
)
3371 stride
= 4 * num_components
* ctx
->gs_max_out_vertices
;
3373 /* Limit on the stride field for <= CIK. */
3374 assert(stride
< (1 << 14));
3376 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
3377 base_ring
, v2i64
, "");
3378 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3379 ring
, ctx
->ac
.i32_0
, "");
3380 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
3381 LLVMConstInt(ctx
->ac
.i64
,
3382 stream_offset
, 0), "");
3383 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
3384 ring
, tmp
, ctx
->ac
.i32_0
, "");
3386 stream_offset
+= stride
* 64;
3388 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
3391 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
3393 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
3394 LLVMConstInt(ctx
->ac
.i32
,
3395 S_008F04_STRIDE(stride
), false), "");
3396 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
3399 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
3400 LLVMConstInt(ctx
->ac
.i32
,
3401 num_records
, false),
3402 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3404 ctx
->gsvs_ring
[stream
] = ring
;
3408 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3409 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3410 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
3411 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
3416 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
3417 const struct nir_shader
*nir
)
3419 switch (nir
->info
.stage
) {
3420 case MESA_SHADER_TESS_CTRL
:
3421 return chip_class
>= CIK
? 128 : 64;
3422 case MESA_SHADER_GEOMETRY
:
3423 return chip_class
>= GFX9
? 128 : 64;
3424 case MESA_SHADER_COMPUTE
:
3430 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
3431 nir
->info
.cs
.local_size
[1] *
3432 nir
->info
.cs
.local_size
[2];
3433 return max_workgroup_size
;
3436 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3437 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
3439 LLVMValueRef count
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
3440 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
3442 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
3443 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
3444 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
3447 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
3449 for(int i
= 5; i
>= 0; --i
) {
3450 ctx
->gs_vtx_offset
[i
] = ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
3454 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 16, 8);
3459 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
3460 struct nir_shader
*const *shaders
,
3462 struct radv_shader_variant_info
*shader_info
,
3463 const struct radv_nir_compiler_options
*options
)
3465 struct radv_shader_context ctx
= {0};
3467 ctx
.options
= options
;
3468 ctx
.shader_info
= shader_info
;
3470 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
3471 ctx
.context
= ctx
.ac
.context
;
3472 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
3474 enum ac_float_mode float_mode
=
3475 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
3476 AC_FLOAT_MODE_DEFAULT
;
3478 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
3480 memset(shader_info
, 0, sizeof(*shader_info
));
3482 for(int i
= 0; i
< shader_count
; ++i
)
3483 radv_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
3485 for (i
= 0; i
< RADV_UD_MAX_SETS
; i
++)
3486 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
3487 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
3488 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
3490 ctx
.max_workgroup_size
= 0;
3491 for (int i
= 0; i
< shader_count
; ++i
) {
3492 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
3493 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
3497 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
3498 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
3500 ctx
.abi
.inputs
= &ctx
.inputs
[0];
3501 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
3502 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
3503 ctx
.abi
.load_ubo
= radv_load_ubo
;
3504 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
3505 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
3506 ctx
.abi
.load_resource
= radv_load_resource
;
3507 ctx
.abi
.clamp_shadow_reference
= false;
3508 ctx
.abi
.gfx9_stride_size_workaround
= ctx
.ac
.chip_class
== GFX9
&& HAVE_LLVM
< 0x800;
3510 if (shader_count
>= 2)
3511 ac_init_exec_full_mask(&ctx
.ac
);
3513 if (ctx
.ac
.chip_class
== GFX9
&&
3514 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
3515 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
3517 for(int i
= 0; i
< shader_count
; ++i
) {
3518 ctx
.stage
= shaders
[i
]->info
.stage
;
3519 ctx
.output_mask
= 0;
3521 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3522 for (int i
= 0; i
< 4; i
++) {
3523 ctx
.gs_next_vertex
[i
] =
3524 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
3526 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
3527 ctx
.abi
.load_inputs
= load_gs_input
;
3528 ctx
.abi
.emit_primitive
= visit_end_primitive
;
3529 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3530 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
3531 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
3532 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
3533 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3534 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
3535 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3536 if (shader_count
== 1)
3537 ctx
.tcs_num_inputs
= ctx
.options
->key
.tcs
.num_inputs
;
3539 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->info
.vs
.ls_outputs_written
);
3540 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
3541 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
3542 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
3543 ctx
.abi
.load_tess_varyings
= load_tes_input
;
3544 ctx
.abi
.load_tess_coord
= load_tess_coord
;
3545 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3546 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3547 ctx
.tcs_num_patches
= ctx
.options
->key
.tes
.num_patches
;
3548 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
3549 if (shader_info
->info
.vs
.needs_instance_id
) {
3550 if (ctx
.options
->key
.vs
.as_ls
) {
3551 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
3552 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
3554 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
3555 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
3558 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
3559 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
3560 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
3561 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
3562 ctx
.abi
.load_sample_position
= load_sample_position
;
3563 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
3564 ctx
.abi
.emit_kill
= radv_emit_kill
;
3568 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
3570 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
3571 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
3573 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3574 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
3575 shaders
[i
]->info
.cull_distance_array_size
> 4;
3576 ctx
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
3577 ctx
.max_gsvs_emit_size
= ctx
.gsvs_vertex_size
*
3578 shaders
[i
]->info
.gs
.vertices_out
;
3581 ac_setup_rings(&ctx
);
3583 LLVMBasicBlockRef merge_block
;
3584 if (shader_count
>= 2) {
3585 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
3586 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3587 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3589 LLVMValueRef count
= ac_unpack_param(&ctx
.ac
, ctx
.merged_wave_info
, 8 * i
, 8);
3590 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
3591 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
3592 thread_id
, count
, "");
3593 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
3595 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
3598 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
3599 handle_fs_inputs(&ctx
, shaders
[i
]);
3600 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
3601 handle_vs_inputs(&ctx
, shaders
[i
]);
3602 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
3603 prepare_gs_input_vgprs(&ctx
);
3605 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
3607 if (shader_count
>= 2) {
3608 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
3609 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
3612 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3613 shader_info
->gs
.gsvs_vertex_size
= ctx
.gsvs_vertex_size
;
3614 shader_info
->gs
.max_gsvs_emit_size
= ctx
.max_gsvs_emit_size
;
3615 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3616 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
3617 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
3621 LLVMBuildRetVoid(ctx
.ac
.builder
);
3623 if (options
->dump_preoptir
)
3624 ac_dump_module(ctx
.ac
.module
);
3626 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
3628 if (shader_count
== 1)
3629 ac_nir_eliminate_const_vs_outputs(&ctx
);
3631 if (options
->dump_shader
) {
3632 ctx
.shader_info
->private_mem_vgprs
=
3633 ac_count_scratch_private_memory(ctx
.main_function
);
3636 return ctx
.ac
.module
;
3639 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
3641 unsigned *retval
= (unsigned *)context
;
3642 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
3643 char *description
= LLVMGetDiagInfoDescription(di
);
3645 if (severity
== LLVMDSError
) {
3647 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
3651 LLVMDisposeMessage(description
);
3654 static unsigned ac_llvm_compile(LLVMModuleRef M
,
3655 struct ac_shader_binary
*binary
,
3656 struct ac_llvm_compiler
*ac_llvm
)
3658 unsigned retval
= 0;
3659 LLVMContextRef llvm_ctx
;
3661 /* Setup Diagnostic Handler*/
3662 llvm_ctx
= LLVMGetModuleContext(M
);
3664 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
3668 if (!radv_compile_to_binary(ac_llvm
, M
, binary
))
3673 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
3674 LLVMModuleRef llvm_module
,
3675 struct ac_shader_binary
*binary
,
3676 struct ac_shader_config
*config
,
3677 struct radv_shader_variant_info
*shader_info
,
3678 gl_shader_stage stage
,
3679 const struct radv_nir_compiler_options
*options
)
3681 if (options
->dump_shader
)
3682 ac_dump_module(llvm_module
);
3684 memset(binary
, 0, sizeof(*binary
));
3686 if (options
->record_llvm_ir
) {
3687 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
3688 binary
->llvm_ir_string
= strdup(llvm_ir
);
3689 LLVMDisposeMessage(llvm_ir
);
3692 int v
= ac_llvm_compile(llvm_module
, binary
, ac_llvm
);
3694 fprintf(stderr
, "compile failed\n");
3697 if (options
->dump_shader
)
3698 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
3700 ac_shader_binary_read_config(binary
, config
, 0, options
->supports_spill
);
3702 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
3703 LLVMDisposeModule(llvm_module
);
3704 LLVMContextDispose(ctx
);
3706 if (stage
== MESA_SHADER_FRAGMENT
) {
3707 shader_info
->num_input_vgprs
= 0;
3708 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
3709 shader_info
->num_input_vgprs
+= 2;
3710 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
3711 shader_info
->num_input_vgprs
+= 2;
3712 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
3713 shader_info
->num_input_vgprs
+= 2;
3714 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
3715 shader_info
->num_input_vgprs
+= 3;
3716 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
3717 shader_info
->num_input_vgprs
+= 2;
3718 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
3719 shader_info
->num_input_vgprs
+= 2;
3720 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
3721 shader_info
->num_input_vgprs
+= 2;
3722 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
3723 shader_info
->num_input_vgprs
+= 1;
3724 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
3725 shader_info
->num_input_vgprs
+= 1;
3726 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
3727 shader_info
->num_input_vgprs
+= 1;
3728 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
3729 shader_info
->num_input_vgprs
+= 1;
3730 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
3731 shader_info
->num_input_vgprs
+= 1;
3732 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
3733 shader_info
->num_input_vgprs
+= 1;
3734 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
3735 shader_info
->num_input_vgprs
+= 1;
3736 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
3737 shader_info
->num_input_vgprs
+= 1;
3738 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
3739 shader_info
->num_input_vgprs
+= 1;
3741 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
3743 /* +3 for scratch wave offset and VCC */
3744 config
->num_sgprs
= MAX2(config
->num_sgprs
,
3745 shader_info
->num_input_sgprs
+ 3);
3747 /* Enable 64-bit and 16-bit denormals, because there is no performance
3750 * If denormals are enabled, all floating-point output modifiers are
3753 * Don't enable denormals for 32-bit floats, because:
3754 * - Floating-point output modifiers would be ignored by the hw.
3755 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3756 * have to stop using those.
3757 * - SI & CI would be very slow.
3759 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
3763 ac_fill_shader_info(struct radv_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct radv_nir_compiler_options
*options
)
3765 switch (nir
->info
.stage
) {
3766 case MESA_SHADER_COMPUTE
:
3767 for (int i
= 0; i
< 3; ++i
)
3768 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
3770 case MESA_SHADER_FRAGMENT
:
3771 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
3773 case MESA_SHADER_GEOMETRY
:
3774 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
3775 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
3776 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
3777 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
3779 case MESA_SHADER_TESS_EVAL
:
3780 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
3781 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
3782 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
3783 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
3784 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
3786 case MESA_SHADER_TESS_CTRL
:
3787 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
3789 case MESA_SHADER_VERTEX
:
3790 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
3791 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
3792 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3793 if (options
->key
.vs
.as_ls
)
3794 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
3802 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
3803 struct ac_shader_binary
*binary
,
3804 struct ac_shader_config
*config
,
3805 struct radv_shader_variant_info
*shader_info
,
3806 struct nir_shader
*const *nir
,
3808 const struct radv_nir_compiler_options
*options
)
3811 LLVMModuleRef llvm_module
;
3813 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, shader_info
,
3816 ac_compile_llvm_module(ac_llvm
, llvm_module
, binary
, config
, shader_info
,
3817 nir
[0]->info
.stage
, options
);
3819 for (int i
= 0; i
< nir_count
; ++i
)
3820 ac_fill_shader_info(shader_info
, nir
[i
], options
);
3822 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3823 if (options
->chip_class
== GFX9
) {
3824 if (nir_count
== 2 &&
3825 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3826 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
3832 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
3834 LLVMValueRef vtx_offset
=
3835 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
3836 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3837 LLVMValueRef stream_id
;
3839 /* Fetch the vertex stream ID. */
3840 if (ctx
->shader_info
->info
.so
.num_outputs
) {
3842 ac_unpack_param(&ctx
->ac
, ctx
->streamout_config
, 24, 2);
3844 stream_id
= ctx
->ac
.i32_0
;
3847 LLVMBasicBlockRef end_bb
;
3848 LLVMValueRef switch_inst
;
3850 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
3851 ctx
->main_function
, "end");
3852 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
3854 for (unsigned stream
= 0; stream
< 4; stream
++) {
3855 unsigned num_components
=
3856 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
3857 LLVMBasicBlockRef bb
;
3860 if (!num_components
)
3863 if (stream
> 0 && !ctx
->shader_info
->info
.so
.num_outputs
)
3866 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
3867 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
3868 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
3871 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3872 unsigned output_usage_mask
=
3873 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
3874 unsigned output_stream
=
3875 ctx
->shader_info
->info
.gs
.output_streams
[i
];
3876 int length
= util_last_bit(output_usage_mask
);
3878 if (!(ctx
->output_mask
& (1ull << i
)) ||
3879 output_stream
!= stream
)
3882 for (unsigned j
= 0; j
< length
; j
++) {
3883 LLVMValueRef value
, soffset
;
3885 if (!(output_usage_mask
& (1 << j
)))
3888 soffset
= LLVMConstInt(ctx
->ac
.i32
,
3890 ctx
->gs_max_out_vertices
* 16 * 4, false);
3894 value
= ac_build_buffer_load(&ctx
->ac
,
3897 vtx_offset
, soffset
,
3898 0, 1, 1, true, false);
3900 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3901 if (ac_get_type_size(type
) == 2) {
3902 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
3903 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
3906 LLVMBuildStore(ctx
->ac
.builder
,
3907 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3911 if (ctx
->shader_info
->info
.so
.num_outputs
)
3912 radv_emit_streamout(ctx
, stream
);
3915 handle_vs_outputs_post(ctx
, false, false,
3916 &ctx
->shader_info
->vs
.outinfo
);
3919 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
3922 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
3926 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
3927 struct nir_shader
*geom_shader
,
3928 struct ac_shader_binary
*binary
,
3929 struct ac_shader_config
*config
,
3930 struct radv_shader_variant_info
*shader_info
,
3931 const struct radv_nir_compiler_options
*options
)
3933 struct radv_shader_context ctx
= {0};
3934 ctx
.options
= options
;
3935 ctx
.shader_info
= shader_info
;
3937 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
3938 ctx
.context
= ctx
.ac
.context
;
3939 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
3941 ctx
.is_gs_copy_shader
= true;
3943 enum ac_float_mode float_mode
=
3944 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
3945 AC_FLOAT_MODE_DEFAULT
;
3947 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
3948 ctx
.stage
= MESA_SHADER_VERTEX
;
3950 radv_nir_shader_info_pass(geom_shader
, options
, &shader_info
->info
);
3952 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
3954 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
3955 ac_setup_rings(&ctx
);
3957 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
3958 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
3959 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
3960 variable
, MESA_SHADER_VERTEX
);
3963 ac_gs_copy_shader_emit(&ctx
);
3965 LLVMBuildRetVoid(ctx
.ac
.builder
);
3967 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
3969 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, binary
, config
, shader_info
,
3970 MESA_SHADER_VERTEX
, options
);