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radv: set amdgpu-32bit-address-high-bits LLVM attribute
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "nir/nir.h"
31
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35 #if HAVE_LLVM >= 0x0700
36 #include <llvm-c/Transforms/Utils.h>
37 #endif
38
39 #include "sid.h"
40 #include "gfx9d.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_llvm_build.h"
44 #include "ac_shader_abi.h"
45 #include "ac_shader_util.h"
46 #include "ac_exp_param.h"
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct radv_shader_context {
51 struct ac_llvm_context ac;
52 const struct radv_nir_compiler_options *options;
53 struct radv_shader_variant_info *shader_info;
54 struct ac_shader_abi abi;
55
56 unsigned max_workgroup_size;
57 LLVMContextRef context;
58 LLVMValueRef main_function;
59
60 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
61 LLVMValueRef ring_offsets;
62
63 LLVMValueRef vertex_buffers;
64 LLVMValueRef rel_auto_id;
65 LLVMValueRef vs_prim_id;
66 LLVMValueRef es2gs_offset;
67
68 LLVMValueRef oc_lds;
69 LLVMValueRef merged_wave_info;
70 LLVMValueRef tess_factor_offset;
71 LLVMValueRef tes_rel_patch_id;
72 LLVMValueRef tes_u;
73 LLVMValueRef tes_v;
74
75 LLVMValueRef gs2vs_offset;
76 LLVMValueRef gs_wave_id;
77 LLVMValueRef gs_vtx_offset[6];
78
79 LLVMValueRef esgs_ring;
80 LLVMValueRef gsvs_ring;
81 LLVMValueRef hs_ring_tess_offchip;
82 LLVMValueRef hs_ring_tess_factor;
83
84 LLVMValueRef sample_pos_offset;
85 LLVMValueRef persp_sample, persp_center, persp_centroid;
86 LLVMValueRef linear_sample, linear_center, linear_centroid;
87
88 gl_shader_stage stage;
89
90 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
91
92 uint64_t input_mask;
93 uint64_t output_mask;
94 uint8_t num_output_clips;
95 uint8_t num_output_culls;
96
97 bool is_gs_copy_shader;
98 LLVMValueRef gs_next_vertex;
99 unsigned gs_max_out_vertices;
100
101 unsigned tes_primitive_mode;
102
103 uint32_t tcs_patch_outputs_read;
104 uint64_t tcs_outputs_read;
105 uint32_t tcs_vertices_per_patch;
106 uint32_t tcs_num_inputs;
107 uint32_t tcs_num_patches;
108 uint32_t max_gsvs_emit_size;
109 uint32_t gsvs_vertex_size;
110 };
111
112 enum radeon_llvm_calling_convention {
113 RADEON_LLVM_AMDGPU_VS = 87,
114 RADEON_LLVM_AMDGPU_GS = 88,
115 RADEON_LLVM_AMDGPU_PS = 89,
116 RADEON_LLVM_AMDGPU_CS = 90,
117 RADEON_LLVM_AMDGPU_HS = 93,
118 };
119
120 static inline struct radv_shader_context *
121 radv_shader_context_from_abi(struct ac_shader_abi *abi)
122 {
123 struct radv_shader_context *ctx = NULL;
124 return container_of(abi, ctx, abi);
125 }
126
127 struct ac_build_if_state
128 {
129 struct radv_shader_context *ctx;
130 LLVMValueRef condition;
131 LLVMBasicBlockRef entry_block;
132 LLVMBasicBlockRef true_block;
133 LLVMBasicBlockRef false_block;
134 LLVMBasicBlockRef merge_block;
135 };
136
137 static LLVMBasicBlockRef
138 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
139 {
140 LLVMBasicBlockRef current_block;
141 LLVMBasicBlockRef next_block;
142 LLVMBasicBlockRef new_block;
143
144 /* get current basic block */
145 current_block = LLVMGetInsertBlock(ctx->ac.builder);
146
147 /* chqeck if there's another block after this one */
148 next_block = LLVMGetNextBasicBlock(current_block);
149 if (next_block) {
150 /* insert the new block before the next block */
151 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
152 }
153 else {
154 /* append new block after current block */
155 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
156 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
157 }
158 return new_block;
159 }
160
161 static void
162 ac_nir_build_if(struct ac_build_if_state *ifthen,
163 struct radv_shader_context *ctx,
164 LLVMValueRef condition)
165 {
166 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
167
168 memset(ifthen, 0, sizeof *ifthen);
169 ifthen->ctx = ctx;
170 ifthen->condition = condition;
171 ifthen->entry_block = block;
172
173 /* create endif/merge basic block for the phi functions */
174 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
175
176 /* create/insert true_block before merge_block */
177 ifthen->true_block =
178 LLVMInsertBasicBlockInContext(ctx->context,
179 ifthen->merge_block,
180 "if-true-block");
181
182 /* successive code goes into the true block */
183 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
184 }
185
186 /**
187 * End a conditional.
188 */
189 static void
190 ac_nir_build_endif(struct ac_build_if_state *ifthen)
191 {
192 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
193
194 /* Insert branch to the merge block from current block */
195 LLVMBuildBr(builder, ifthen->merge_block);
196
197 /*
198 * Now patch in the various branch instructions.
199 */
200
201 /* Insert the conditional branch instruction at the end of entry_block */
202 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
203 if (ifthen->false_block) {
204 /* we have an else clause */
205 LLVMBuildCondBr(builder, ifthen->condition,
206 ifthen->true_block, ifthen->false_block);
207 }
208 else {
209 /* no else clause */
210 LLVMBuildCondBr(builder, ifthen->condition,
211 ifthen->true_block, ifthen->merge_block);
212 }
213
214 /* Resume building code at end of the ifthen->merge_block */
215 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
216 }
217
218
219 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
220 {
221 switch (ctx->stage) {
222 case MESA_SHADER_TESS_CTRL:
223 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
224 case MESA_SHADER_TESS_EVAL:
225 return ctx->tes_rel_patch_id;
226 break;
227 default:
228 unreachable("Illegal stage");
229 }
230 }
231
232 static unsigned
233 get_tcs_num_patches(struct radv_shader_context *ctx)
234 {
235 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
236 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
237 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
238 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
239 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
240 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
241 uint32_t output_vertex_size = num_tcs_outputs * 16;
242 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
243 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
244 unsigned num_patches;
245 unsigned hardware_lds_size;
246
247 /* Ensure that we only need one wave per SIMD so we don't need to check
248 * resource usage. Also ensures that the number of tcs in and out
249 * vertices per threadgroup are at most 256.
250 */
251 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
252 /* Make sure that the data fits in LDS. This assumes the shaders only
253 * use LDS for the inputs and outputs.
254 */
255 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
256 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
257 /* Make sure the output data fits in the offchip buffer */
258 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
259 /* Not necessary for correctness, but improves performance. The
260 * specific value is taken from the proprietary driver.
261 */
262 num_patches = MIN2(num_patches, 40);
263
264 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
265 if (ctx->options->chip_class == SI) {
266 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
267 num_patches = MIN2(num_patches, one_wave);
268 }
269 return num_patches;
270 }
271
272 static unsigned
273 calculate_tess_lds_size(struct radv_shader_context *ctx)
274 {
275 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
276 unsigned num_tcs_output_cp;
277 unsigned num_tcs_outputs, num_tcs_patch_outputs;
278 unsigned input_vertex_size, output_vertex_size;
279 unsigned input_patch_size, output_patch_size;
280 unsigned pervertex_output_patch_size;
281 unsigned output_patch0_offset;
282 unsigned num_patches;
283 unsigned lds_size;
284
285 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
286 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
287 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
288
289 input_vertex_size = ctx->tcs_num_inputs * 16;
290 output_vertex_size = num_tcs_outputs * 16;
291
292 input_patch_size = num_tcs_input_cp * input_vertex_size;
293
294 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
295 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
296
297 num_patches = ctx->tcs_num_patches;
298 output_patch0_offset = input_patch_size * num_patches;
299
300 lds_size = output_patch0_offset + output_patch_size * num_patches;
301 return lds_size;
302 }
303
304 /* Tessellation shaders pass outputs to the next shader using LDS.
305 *
306 * LS outputs = TCS inputs
307 * TCS outputs = TES inputs
308 *
309 * The LDS layout is:
310 * - TCS inputs for patch 0
311 * - TCS inputs for patch 1
312 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
313 * - ...
314 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
315 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
316 * - TCS outputs for patch 1
317 * - Per-patch TCS outputs for patch 1
318 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
319 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
320 * - ...
321 *
322 * All three shaders VS(LS), TCS, TES share the same LDS space.
323 */
324 static LLVMValueRef
325 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
326 {
327 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
328 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
329 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
330
331 input_patch_size /= 4;
332 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
333 }
334
335 static LLVMValueRef
336 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
337 {
338 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
339 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
340 uint32_t output_vertex_size = num_tcs_outputs * 16;
341 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
342 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
343 output_patch_size /= 4;
344 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
345 }
346
347 static LLVMValueRef
348 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
349 {
350 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
351 uint32_t output_vertex_size = num_tcs_outputs * 16;
352 output_vertex_size /= 4;
353 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
354 }
355
356 static LLVMValueRef
357 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
358 {
359 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
360 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
361 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
362 uint32_t output_patch0_offset = input_patch_size;
363 unsigned num_patches = ctx->tcs_num_patches;
364
365 output_patch0_offset *= num_patches;
366 output_patch0_offset /= 4;
367 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
368 }
369
370 static LLVMValueRef
371 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
372 {
373 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
374 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
375 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
376 uint32_t output_patch0_offset = input_patch_size;
377
378 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
379 uint32_t output_vertex_size = num_tcs_outputs * 16;
380 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
381 unsigned num_patches = ctx->tcs_num_patches;
382
383 output_patch0_offset *= num_patches;
384 output_patch0_offset += pervertex_output_patch_size;
385 output_patch0_offset /= 4;
386 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
387 }
388
389 static LLVMValueRef
390 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
391 {
392 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
393 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
394
395 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
396 }
397
398 static LLVMValueRef
399 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
400 {
401 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
402 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
403 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
404
405 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
406 LLVMBuildMul(ctx->ac.builder, patch_stride,
407 rel_patch_id, ""),
408 "");
409 }
410
411 static LLVMValueRef
412 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
413 {
414 LLVMValueRef patch0_patch_data_offset =
415 get_tcs_out_patch0_patch_data_offset(ctx);
416 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
417 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
418
419 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
420 LLVMBuildMul(ctx->ac.builder, patch_stride,
421 rel_patch_id, ""),
422 "");
423 }
424
425 #define MAX_ARGS 23
426 struct arg_info {
427 LLVMTypeRef types[MAX_ARGS];
428 LLVMValueRef *assign[MAX_ARGS];
429 unsigned array_params_mask;
430 uint8_t count;
431 uint8_t sgpr_count;
432 uint8_t num_sgprs_used;
433 uint8_t num_vgprs_used;
434 };
435
436 enum ac_arg_regfile {
437 ARG_SGPR,
438 ARG_VGPR,
439 };
440
441 static void
442 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
443 LLVMValueRef *param_ptr)
444 {
445 assert(info->count < MAX_ARGS);
446
447 info->assign[info->count] = param_ptr;
448 info->types[info->count] = type;
449 info->count++;
450
451 if (regfile == ARG_SGPR) {
452 info->num_sgprs_used += ac_get_type_size(type) / 4;
453 info->sgpr_count++;
454 } else {
455 assert(regfile == ARG_VGPR);
456 info->num_vgprs_used += ac_get_type_size(type) / 4;
457 }
458 }
459
460 static inline void
461 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
462 {
463 info->array_params_mask |= (1 << info->count);
464 add_arg(info, ARG_SGPR, type, param_ptr);
465 }
466
467 static void assign_arguments(LLVMValueRef main_function,
468 struct arg_info *info)
469 {
470 unsigned i;
471 for (i = 0; i < info->count; i++) {
472 if (info->assign[i])
473 *info->assign[i] = LLVMGetParam(main_function, i);
474 }
475 }
476
477 static LLVMValueRef
478 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
479 LLVMBuilderRef builder, LLVMTypeRef *return_types,
480 unsigned num_return_elems,
481 struct arg_info *args,
482 unsigned max_workgroup_size,
483 const struct radv_nir_compiler_options *options)
484 {
485 LLVMTypeRef main_function_type, ret_type;
486 LLVMBasicBlockRef main_function_body;
487
488 if (num_return_elems)
489 ret_type = LLVMStructTypeInContext(ctx, return_types,
490 num_return_elems, true);
491 else
492 ret_type = LLVMVoidTypeInContext(ctx);
493
494 /* Setup the function */
495 main_function_type =
496 LLVMFunctionType(ret_type, args->types, args->count, 0);
497 LLVMValueRef main_function =
498 LLVMAddFunction(module, "main", main_function_type);
499 main_function_body =
500 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
501 LLVMPositionBuilderAtEnd(builder, main_function_body);
502
503 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
504 for (unsigned i = 0; i < args->sgpr_count; ++i) {
505 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
506
507 if (args->array_params_mask & (1 << i)) {
508 LLVMValueRef P = LLVMGetParam(main_function, i);
509 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
510 ac_add_attr_dereferenceable(P, UINT64_MAX);
511 }
512 }
513
514 if (options->address32_hi) {
515 ac_llvm_add_target_dep_function_attr(main_function,
516 "amdgpu-32bit-address-high-bits",
517 options->address32_hi);
518 }
519
520 if (max_workgroup_size) {
521 ac_llvm_add_target_dep_function_attr(main_function,
522 "amdgpu-max-work-group-size",
523 max_workgroup_size);
524 }
525 if (options->unsafe_math) {
526 /* These were copied from some LLVM test. */
527 LLVMAddTargetDependentFunctionAttr(main_function,
528 "less-precise-fpmad",
529 "true");
530 LLVMAddTargetDependentFunctionAttr(main_function,
531 "no-infs-fp-math",
532 "true");
533 LLVMAddTargetDependentFunctionAttr(main_function,
534 "no-nans-fp-math",
535 "true");
536 LLVMAddTargetDependentFunctionAttr(main_function,
537 "unsafe-fp-math",
538 "true");
539 LLVMAddTargetDependentFunctionAttr(main_function,
540 "no-signed-zeros-fp-math",
541 "true");
542 }
543 return main_function;
544 }
545
546
547 static void
548 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
549 uint32_t indirect_offset)
550 {
551 ud_info->sgpr_idx = *sgpr_idx;
552 ud_info->num_sgprs = num_sgprs;
553 ud_info->indirect = indirect_offset > 0;
554 ud_info->indirect_offset = indirect_offset;
555 *sgpr_idx += num_sgprs;
556 }
557
558 static void
559 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
560 uint8_t num_sgprs)
561 {
562 struct radv_userdata_info *ud_info =
563 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
564 assert(ud_info);
565
566 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
567 }
568
569 static void
570 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
571 uint32_t indirect_offset)
572 {
573 struct radv_userdata_info *ud_info =
574 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
575 assert(ud_info);
576
577 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
578 }
579
580 struct user_sgpr_info {
581 bool need_ring_offsets;
582 uint8_t sgpr_count;
583 bool indirect_all_descriptor_sets;
584 };
585
586 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
587 gl_shader_stage stage)
588 {
589 switch (stage) {
590 case MESA_SHADER_VERTEX:
591 if (ctx->shader_info->info.needs_multiview_view_index ||
592 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
593 return true;
594 break;
595 case MESA_SHADER_TESS_EVAL:
596 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
597 return true;
598 break;
599 case MESA_SHADER_GEOMETRY:
600 case MESA_SHADER_TESS_CTRL:
601 if (ctx->shader_info->info.needs_multiview_view_index)
602 return true;
603 break;
604 default:
605 break;
606 }
607 return false;
608 }
609
610 static uint8_t
611 count_vs_user_sgprs(struct radv_shader_context *ctx)
612 {
613 uint8_t count = 0;
614
615 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
616 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
617
618 return count;
619 }
620
621 static void allocate_user_sgprs(struct radv_shader_context *ctx,
622 gl_shader_stage stage,
623 bool has_previous_stage,
624 gl_shader_stage previous_stage,
625 bool needs_view_index,
626 struct user_sgpr_info *user_sgpr_info)
627 {
628 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
629
630 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
631 if (stage == MESA_SHADER_GEOMETRY ||
632 stage == MESA_SHADER_VERTEX ||
633 stage == MESA_SHADER_TESS_CTRL ||
634 stage == MESA_SHADER_TESS_EVAL ||
635 ctx->is_gs_copy_shader)
636 user_sgpr_info->need_ring_offsets = true;
637
638 if (stage == MESA_SHADER_FRAGMENT &&
639 ctx->shader_info->info.ps.needs_sample_positions)
640 user_sgpr_info->need_ring_offsets = true;
641
642 /* 2 user sgprs will nearly always be allocated for scratch/rings */
643 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
644 user_sgpr_info->sgpr_count += 2;
645 }
646
647 switch (stage) {
648 case MESA_SHADER_COMPUTE:
649 if (ctx->shader_info->info.cs.uses_grid_size)
650 user_sgpr_info->sgpr_count += 3;
651 break;
652 case MESA_SHADER_FRAGMENT:
653 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
654 break;
655 case MESA_SHADER_VERTEX:
656 if (!ctx->is_gs_copy_shader)
657 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
658 break;
659 case MESA_SHADER_TESS_CTRL:
660 if (has_previous_stage) {
661 if (previous_stage == MESA_SHADER_VERTEX)
662 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
663 }
664 break;
665 case MESA_SHADER_TESS_EVAL:
666 break;
667 case MESA_SHADER_GEOMETRY:
668 if (has_previous_stage) {
669 if (previous_stage == MESA_SHADER_VERTEX) {
670 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
671 }
672 }
673 break;
674 default:
675 break;
676 }
677
678 if (needs_view_index)
679 user_sgpr_info->sgpr_count++;
680
681 if (ctx->shader_info->info.loads_push_constants)
682 user_sgpr_info->sgpr_count += 2;
683
684 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
685 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
686
687 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
688 user_sgpr_info->sgpr_count += 2;
689 user_sgpr_info->indirect_all_descriptor_sets = true;
690 } else {
691 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
692 }
693 }
694
695 static void
696 declare_global_input_sgprs(struct radv_shader_context *ctx,
697 gl_shader_stage stage,
698 bool has_previous_stage,
699 gl_shader_stage previous_stage,
700 const struct user_sgpr_info *user_sgpr_info,
701 struct arg_info *args,
702 LLVMValueRef *desc_sets)
703 {
704 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
705 unsigned num_sets = ctx->options->layout ?
706 ctx->options->layout->num_sets : 0;
707 unsigned stage_mask = 1 << stage;
708
709 if (has_previous_stage)
710 stage_mask |= 1 << previous_stage;
711
712 /* 1 for each descriptor set */
713 if (!user_sgpr_info->indirect_all_descriptor_sets) {
714 for (unsigned i = 0; i < num_sets; ++i) {
715 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
716 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
717 add_array_arg(args, type,
718 &ctx->descriptor_sets[i]);
719 }
720 }
721 } else {
722 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
723 }
724
725 if (ctx->shader_info->info.loads_push_constants) {
726 /* 1 for push constants and dynamic descriptors */
727 add_array_arg(args, type, &ctx->abi.push_constants);
728 }
729 }
730
731 static void
732 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
733 gl_shader_stage stage,
734 bool has_previous_stage,
735 gl_shader_stage previous_stage,
736 struct arg_info *args)
737 {
738 if (!ctx->is_gs_copy_shader &&
739 (stage == MESA_SHADER_VERTEX ||
740 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
741 if (ctx->shader_info->info.vs.has_vertex_buffers) {
742 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
743 &ctx->vertex_buffers);
744 }
745 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
746 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
747 if (ctx->shader_info->info.vs.needs_draw_id) {
748 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
749 }
750 }
751 }
752
753 static void
754 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
755 {
756 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
757 if (!ctx->is_gs_copy_shader) {
758 if (ctx->options->key.vs.as_ls) {
759 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
760 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
761 } else {
762 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
763 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
764 }
765 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
766 }
767 }
768
769 static void
770 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
771 {
772 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
773 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
774 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
775 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
776 }
777
778 static void
779 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
780 bool has_previous_stage, gl_shader_stage previous_stage,
781 const struct user_sgpr_info *user_sgpr_info,
782 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
783 {
784 unsigned num_sets = ctx->options->layout ?
785 ctx->options->layout->num_sets : 0;
786 unsigned stage_mask = 1 << stage;
787
788 if (has_previous_stage)
789 stage_mask |= 1 << previous_stage;
790
791 if (!user_sgpr_info->indirect_all_descriptor_sets) {
792 for (unsigned i = 0; i < num_sets; ++i) {
793 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
794 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
795 set_loc_desc(ctx, i, user_sgpr_idx, 0);
796 } else
797 ctx->descriptor_sets[i] = NULL;
798 }
799 } else {
800 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
801 user_sgpr_idx, 2);
802
803 for (unsigned i = 0; i < num_sets; ++i) {
804 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
805 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
806 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
807 ctx->descriptor_sets[i] =
808 ac_build_load_to_sgpr(&ctx->ac,
809 desc_sets,
810 LLVMConstInt(ctx->ac.i32, i, false));
811
812 } else
813 ctx->descriptor_sets[i] = NULL;
814 }
815 ctx->shader_info->need_indirect_descriptor_sets = true;
816 }
817
818 if (ctx->shader_info->info.loads_push_constants) {
819 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
820 }
821 }
822
823 static void
824 set_vs_specific_input_locs(struct radv_shader_context *ctx,
825 gl_shader_stage stage, bool has_previous_stage,
826 gl_shader_stage previous_stage,
827 uint8_t *user_sgpr_idx)
828 {
829 if (!ctx->is_gs_copy_shader &&
830 (stage == MESA_SHADER_VERTEX ||
831 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
832 if (ctx->shader_info->info.vs.has_vertex_buffers) {
833 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
834 user_sgpr_idx, 2);
835 }
836
837 unsigned vs_num = 2;
838 if (ctx->shader_info->info.vs.needs_draw_id)
839 vs_num++;
840
841 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
842 user_sgpr_idx, vs_num);
843 }
844 }
845
846 static void set_llvm_calling_convention(LLVMValueRef func,
847 gl_shader_stage stage)
848 {
849 enum radeon_llvm_calling_convention calling_conv;
850
851 switch (stage) {
852 case MESA_SHADER_VERTEX:
853 case MESA_SHADER_TESS_EVAL:
854 calling_conv = RADEON_LLVM_AMDGPU_VS;
855 break;
856 case MESA_SHADER_GEOMETRY:
857 calling_conv = RADEON_LLVM_AMDGPU_GS;
858 break;
859 case MESA_SHADER_TESS_CTRL:
860 calling_conv = RADEON_LLVM_AMDGPU_HS;
861 break;
862 case MESA_SHADER_FRAGMENT:
863 calling_conv = RADEON_LLVM_AMDGPU_PS;
864 break;
865 case MESA_SHADER_COMPUTE:
866 calling_conv = RADEON_LLVM_AMDGPU_CS;
867 break;
868 default:
869 unreachable("Unhandle shader type");
870 }
871
872 LLVMSetFunctionCallConv(func, calling_conv);
873 }
874
875 static void create_function(struct radv_shader_context *ctx,
876 gl_shader_stage stage,
877 bool has_previous_stage,
878 gl_shader_stage previous_stage)
879 {
880 uint8_t user_sgpr_idx;
881 struct user_sgpr_info user_sgpr_info;
882 struct arg_info args = {};
883 LLVMValueRef desc_sets;
884 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
885 allocate_user_sgprs(ctx, stage, has_previous_stage,
886 previous_stage, needs_view_index, &user_sgpr_info);
887
888 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
889 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
890 &ctx->ring_offsets);
891 }
892
893 switch (stage) {
894 case MESA_SHADER_COMPUTE:
895 declare_global_input_sgprs(ctx, stage, has_previous_stage,
896 previous_stage, &user_sgpr_info,
897 &args, &desc_sets);
898
899 if (ctx->shader_info->info.cs.uses_grid_size) {
900 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
901 &ctx->abi.num_work_groups);
902 }
903
904 for (int i = 0; i < 3; i++) {
905 ctx->abi.workgroup_ids[i] = NULL;
906 if (ctx->shader_info->info.cs.uses_block_id[i]) {
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->abi.workgroup_ids[i]);
909 }
910 }
911
912 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
914 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
915 &ctx->abi.local_invocation_ids);
916 break;
917 case MESA_SHADER_VERTEX:
918 declare_global_input_sgprs(ctx, stage, has_previous_stage,
919 previous_stage, &user_sgpr_info,
920 &args, &desc_sets);
921 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
922 previous_stage, &args);
923
924 if (needs_view_index)
925 add_arg(&args, ARG_SGPR, ctx->ac.i32,
926 &ctx->abi.view_index);
927 if (ctx->options->key.vs.as_es)
928 add_arg(&args, ARG_SGPR, ctx->ac.i32,
929 &ctx->es2gs_offset);
930
931 declare_vs_input_vgprs(ctx, &args);
932 break;
933 case MESA_SHADER_TESS_CTRL:
934 if (has_previous_stage) {
935 // First 6 system regs
936 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
937 add_arg(&args, ARG_SGPR, ctx->ac.i32,
938 &ctx->merged_wave_info);
939 add_arg(&args, ARG_SGPR, ctx->ac.i32,
940 &ctx->tess_factor_offset);
941
942 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
943 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
944 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
945
946 declare_global_input_sgprs(ctx, stage,
947 has_previous_stage,
948 previous_stage,
949 &user_sgpr_info, &args,
950 &desc_sets);
951 declare_vs_specific_input_sgprs(ctx, stage,
952 has_previous_stage,
953 previous_stage, &args);
954
955 if (needs_view_index)
956 add_arg(&args, ARG_SGPR, ctx->ac.i32,
957 &ctx->abi.view_index);
958
959 add_arg(&args, ARG_VGPR, ctx->ac.i32,
960 &ctx->abi.tcs_patch_id);
961 add_arg(&args, ARG_VGPR, ctx->ac.i32,
962 &ctx->abi.tcs_rel_ids);
963
964 declare_vs_input_vgprs(ctx, &args);
965 } else {
966 declare_global_input_sgprs(ctx, stage,
967 has_previous_stage,
968 previous_stage,
969 &user_sgpr_info, &args,
970 &desc_sets);
971
972 if (needs_view_index)
973 add_arg(&args, ARG_SGPR, ctx->ac.i32,
974 &ctx->abi.view_index);
975
976 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
977 add_arg(&args, ARG_SGPR, ctx->ac.i32,
978 &ctx->tess_factor_offset);
979 add_arg(&args, ARG_VGPR, ctx->ac.i32,
980 &ctx->abi.tcs_patch_id);
981 add_arg(&args, ARG_VGPR, ctx->ac.i32,
982 &ctx->abi.tcs_rel_ids);
983 }
984 break;
985 case MESA_SHADER_TESS_EVAL:
986 declare_global_input_sgprs(ctx, stage, has_previous_stage,
987 previous_stage, &user_sgpr_info,
988 &args, &desc_sets);
989
990 if (needs_view_index)
991 add_arg(&args, ARG_SGPR, ctx->ac.i32,
992 &ctx->abi.view_index);
993
994 if (ctx->options->key.tes.as_es) {
995 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
996 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
997 add_arg(&args, ARG_SGPR, ctx->ac.i32,
998 &ctx->es2gs_offset);
999 } else {
1000 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1002 }
1003 declare_tes_input_vgprs(ctx, &args);
1004 break;
1005 case MESA_SHADER_GEOMETRY:
1006 if (has_previous_stage) {
1007 // First 6 system regs
1008 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1009 &ctx->gs2vs_offset);
1010 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1011 &ctx->merged_wave_info);
1012 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1013
1014 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1015 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1016 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1017
1018 declare_global_input_sgprs(ctx, stage,
1019 has_previous_stage,
1020 previous_stage,
1021 &user_sgpr_info, &args,
1022 &desc_sets);
1023
1024 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1025 declare_vs_specific_input_sgprs(ctx, stage,
1026 has_previous_stage,
1027 previous_stage,
1028 &args);
1029 }
1030
1031 if (needs_view_index)
1032 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1033 &ctx->abi.view_index);
1034
1035 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1036 &ctx->gs_vtx_offset[0]);
1037 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1038 &ctx->gs_vtx_offset[2]);
1039 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1040 &ctx->abi.gs_prim_id);
1041 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1042 &ctx->abi.gs_invocation_id);
1043 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1044 &ctx->gs_vtx_offset[4]);
1045
1046 if (previous_stage == MESA_SHADER_VERTEX) {
1047 declare_vs_input_vgprs(ctx, &args);
1048 } else {
1049 declare_tes_input_vgprs(ctx, &args);
1050 }
1051 } else {
1052 declare_global_input_sgprs(ctx, stage,
1053 has_previous_stage,
1054 previous_stage,
1055 &user_sgpr_info, &args,
1056 &desc_sets);
1057
1058 if (needs_view_index)
1059 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1060 &ctx->abi.view_index);
1061
1062 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1063 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1064 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1065 &ctx->gs_vtx_offset[0]);
1066 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1067 &ctx->gs_vtx_offset[1]);
1068 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1069 &ctx->abi.gs_prim_id);
1070 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1071 &ctx->gs_vtx_offset[2]);
1072 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1073 &ctx->gs_vtx_offset[3]);
1074 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1075 &ctx->gs_vtx_offset[4]);
1076 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1077 &ctx->gs_vtx_offset[5]);
1078 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1079 &ctx->abi.gs_invocation_id);
1080 }
1081 break;
1082 case MESA_SHADER_FRAGMENT:
1083 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1084 previous_stage, &user_sgpr_info,
1085 &args, &desc_sets);
1086
1087 if (ctx->shader_info->info.ps.needs_sample_positions)
1088 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1089 &ctx->sample_pos_offset);
1090
1091 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1092 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1093 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1094 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1095 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1096 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1097 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1098 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1099 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1100 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1101 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1102 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1103 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1104 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1105 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1106 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1107 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1108 break;
1109 default:
1110 unreachable("Shader stage not implemented");
1111 }
1112
1113 ctx->main_function = create_llvm_function(
1114 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1115 ctx->max_workgroup_size, ctx->options);
1116 set_llvm_calling_convention(ctx->main_function, stage);
1117
1118
1119 ctx->shader_info->num_input_vgprs = 0;
1120 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1121
1122 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1123
1124 if (ctx->stage != MESA_SHADER_FRAGMENT)
1125 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1126
1127 assign_arguments(ctx->main_function, &args);
1128
1129 user_sgpr_idx = 0;
1130
1131 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1132 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1133 &user_sgpr_idx, 2);
1134 if (ctx->options->supports_spill) {
1135 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1136 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1137 NULL, 0, AC_FUNC_ATTR_READNONE);
1138 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1139 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1140 }
1141 }
1142
1143 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1144 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1145 if (has_previous_stage)
1146 user_sgpr_idx = 0;
1147
1148 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1149 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1150
1151 switch (stage) {
1152 case MESA_SHADER_COMPUTE:
1153 if (ctx->shader_info->info.cs.uses_grid_size) {
1154 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1155 &user_sgpr_idx, 3);
1156 }
1157 break;
1158 case MESA_SHADER_VERTEX:
1159 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1160 previous_stage, &user_sgpr_idx);
1161 if (ctx->abi.view_index)
1162 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1163 break;
1164 case MESA_SHADER_TESS_CTRL:
1165 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1166 previous_stage, &user_sgpr_idx);
1167 if (ctx->abi.view_index)
1168 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1169 break;
1170 case MESA_SHADER_TESS_EVAL:
1171 if (ctx->abi.view_index)
1172 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1173 break;
1174 case MESA_SHADER_GEOMETRY:
1175 if (has_previous_stage) {
1176 if (previous_stage == MESA_SHADER_VERTEX)
1177 set_vs_specific_input_locs(ctx, stage,
1178 has_previous_stage,
1179 previous_stage,
1180 &user_sgpr_idx);
1181 }
1182 if (ctx->abi.view_index)
1183 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1184 break;
1185 case MESA_SHADER_FRAGMENT:
1186 if (ctx->shader_info->info.ps.needs_sample_positions) {
1187 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1188 &user_sgpr_idx, 1);
1189 }
1190 break;
1191 default:
1192 unreachable("Shader stage not implemented");
1193 }
1194
1195 if (stage == MESA_SHADER_TESS_CTRL ||
1196 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1197 /* GFX9 has the ESGS ring buffer in LDS. */
1198 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1199 ac_declare_lds_as_pointer(&ctx->ac);
1200 }
1201
1202 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1203 }
1204
1205
1206 static LLVMValueRef
1207 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1208 unsigned desc_set, unsigned binding)
1209 {
1210 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1211 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1212 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1213 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1214 unsigned base_offset = layout->binding[binding].offset;
1215 LLVMValueRef offset, stride;
1216
1217 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1218 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1219 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1220 layout->binding[binding].dynamic_offset_offset;
1221 desc_ptr = ctx->abi.push_constants;
1222 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1223 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1224 } else
1225 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1226
1227 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1228 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
1229 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
1230
1231 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1232 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1233 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1234
1235 return desc_ptr;
1236 }
1237
1238
1239 /* The offchip buffer layout for TCS->TES is
1240 *
1241 * - attribute 0 of patch 0 vertex 0
1242 * - attribute 0 of patch 0 vertex 1
1243 * - attribute 0 of patch 0 vertex 2
1244 * ...
1245 * - attribute 0 of patch 1 vertex 0
1246 * - attribute 0 of patch 1 vertex 1
1247 * ...
1248 * - attribute 1 of patch 0 vertex 0
1249 * - attribute 1 of patch 0 vertex 1
1250 * ...
1251 * - per patch attribute 0 of patch 0
1252 * - per patch attribute 0 of patch 1
1253 * ...
1254 *
1255 * Note that every attribute has 4 components.
1256 */
1257 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1258 {
1259 uint32_t num_patches = ctx->tcs_num_patches;
1260 uint32_t num_tcs_outputs;
1261 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1262 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1263 else
1264 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1265
1266 uint32_t output_vertex_size = num_tcs_outputs * 16;
1267 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1268
1269 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1270 }
1271
1272 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1273 LLVMValueRef vertex_index)
1274 {
1275 LLVMValueRef param_stride;
1276 if (vertex_index)
1277 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1278 else
1279 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1280 return param_stride;
1281 }
1282
1283 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1284 LLVMValueRef vertex_index,
1285 LLVMValueRef param_index)
1286 {
1287 LLVMValueRef base_addr;
1288 LLVMValueRef param_stride, constant16;
1289 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1290 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1291 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1292 param_stride = calc_param_stride(ctx, vertex_index);
1293 if (vertex_index) {
1294 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
1295 vertices_per_patch, "");
1296
1297 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1298 vertex_index, "");
1299 } else {
1300 base_addr = rel_patch_id;
1301 }
1302
1303 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1304 LLVMBuildMul(ctx->ac.builder, param_index,
1305 param_stride, ""), "");
1306
1307 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1308
1309 if (!vertex_index) {
1310 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1311
1312 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1313 patch_data_offset, "");
1314 }
1315 return base_addr;
1316 }
1317
1318 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1319 unsigned param,
1320 unsigned const_index,
1321 bool is_compact,
1322 LLVMValueRef vertex_index,
1323 LLVMValueRef indir_index)
1324 {
1325 LLVMValueRef param_index;
1326
1327 if (indir_index)
1328 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1329 indir_index, "");
1330 else {
1331 if (const_index && !is_compact)
1332 param += const_index;
1333 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1334 }
1335 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1336 }
1337
1338 static LLVMValueRef
1339 get_dw_address(struct radv_shader_context *ctx,
1340 LLVMValueRef dw_addr,
1341 unsigned param,
1342 unsigned const_index,
1343 bool compact_const_index,
1344 LLVMValueRef vertex_index,
1345 LLVMValueRef stride,
1346 LLVMValueRef indir_index)
1347
1348 {
1349
1350 if (vertex_index) {
1351 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1352 LLVMBuildMul(ctx->ac.builder,
1353 vertex_index,
1354 stride, ""), "");
1355 }
1356
1357 if (indir_index)
1358 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1359 LLVMBuildMul(ctx->ac.builder, indir_index,
1360 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1361 else if (const_index && !compact_const_index)
1362 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1363 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1364
1365 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1366 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1367
1368 if (const_index && compact_const_index)
1369 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1370 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1371 return dw_addr;
1372 }
1373
1374 static LLVMValueRef
1375 load_tcs_varyings(struct ac_shader_abi *abi,
1376 LLVMTypeRef type,
1377 LLVMValueRef vertex_index,
1378 LLVMValueRef indir_index,
1379 unsigned const_index,
1380 unsigned location,
1381 unsigned driver_location,
1382 unsigned component,
1383 unsigned num_components,
1384 bool is_patch,
1385 bool is_compact,
1386 bool load_input)
1387 {
1388 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1389 LLVMValueRef dw_addr, stride;
1390 LLVMValueRef value[4], result;
1391 unsigned param = shader_io_get_unique_index(location);
1392
1393 if (load_input) {
1394 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1395 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1396 dw_addr = get_tcs_in_current_patch_offset(ctx);
1397 } else {
1398 if (!is_patch) {
1399 stride = get_tcs_out_vertex_stride(ctx);
1400 dw_addr = get_tcs_out_current_patch_offset(ctx);
1401 } else {
1402 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1403 stride = NULL;
1404 }
1405 }
1406
1407 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1408 indir_index);
1409
1410 for (unsigned i = 0; i < num_components + component; i++) {
1411 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1412 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1413 ctx->ac.i32_1, "");
1414 }
1415 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1416 return result;
1417 }
1418
1419 static void
1420 store_tcs_output(struct ac_shader_abi *abi,
1421 const nir_variable *var,
1422 LLVMValueRef vertex_index,
1423 LLVMValueRef param_index,
1424 unsigned const_index,
1425 LLVMValueRef src,
1426 unsigned writemask)
1427 {
1428 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1429 const unsigned location = var->data.location;
1430 const unsigned component = var->data.location_frac;
1431 const bool is_patch = var->data.patch;
1432 const bool is_compact = var->data.compact;
1433 LLVMValueRef dw_addr;
1434 LLVMValueRef stride = NULL;
1435 LLVMValueRef buf_addr = NULL;
1436 unsigned param;
1437 bool store_lds = true;
1438
1439 if (is_patch) {
1440 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1441 store_lds = false;
1442 } else {
1443 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1444 store_lds = false;
1445 }
1446
1447 param = shader_io_get_unique_index(location);
1448 if (location == VARYING_SLOT_CLIP_DIST0 &&
1449 is_compact && const_index > 3) {
1450 const_index -= 3;
1451 param++;
1452 }
1453
1454 if (!is_patch) {
1455 stride = get_tcs_out_vertex_stride(ctx);
1456 dw_addr = get_tcs_out_current_patch_offset(ctx);
1457 } else {
1458 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1459 }
1460
1461 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1462 param_index);
1463 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1464 vertex_index, param_index);
1465
1466 bool is_tess_factor = false;
1467 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1468 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1469 is_tess_factor = true;
1470
1471 unsigned base = is_compact ? const_index : 0;
1472 for (unsigned chan = 0; chan < 8; chan++) {
1473 if (!(writemask & (1 << chan)))
1474 continue;
1475 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1476
1477 if (store_lds || is_tess_factor) {
1478 LLVMValueRef dw_addr_chan =
1479 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1480 LLVMConstInt(ctx->ac.i32, chan, false), "");
1481 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1482 }
1483
1484 if (!is_tess_factor && writemask != 0xF)
1485 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1486 buf_addr, ctx->oc_lds,
1487 4 * (base + chan), 1, 0, true, false);
1488 }
1489
1490 if (writemask == 0xF) {
1491 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1492 buf_addr, ctx->oc_lds,
1493 (base * 4), 1, 0, true, false);
1494 }
1495 }
1496
1497 static LLVMValueRef
1498 load_tes_input(struct ac_shader_abi *abi,
1499 LLVMTypeRef type,
1500 LLVMValueRef vertex_index,
1501 LLVMValueRef param_index,
1502 unsigned const_index,
1503 unsigned location,
1504 unsigned driver_location,
1505 unsigned component,
1506 unsigned num_components,
1507 bool is_patch,
1508 bool is_compact,
1509 bool load_input)
1510 {
1511 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1512 LLVMValueRef buf_addr;
1513 LLVMValueRef result;
1514 unsigned param = shader_io_get_unique_index(location);
1515
1516 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1517 const_index -= 3;
1518 param++;
1519 }
1520
1521 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1522 is_compact, vertex_index, param_index);
1523
1524 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1525 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1526
1527 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1528 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1529 result = ac_trim_vector(&ctx->ac, result, num_components);
1530 return result;
1531 }
1532
1533 static LLVMValueRef
1534 load_gs_input(struct ac_shader_abi *abi,
1535 unsigned location,
1536 unsigned driver_location,
1537 unsigned component,
1538 unsigned num_components,
1539 unsigned vertex_index,
1540 unsigned const_index,
1541 LLVMTypeRef type)
1542 {
1543 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1544 LLVMValueRef vtx_offset;
1545 unsigned param, vtx_offset_param;
1546 LLVMValueRef value[4], result;
1547
1548 vtx_offset_param = vertex_index;
1549 assert(vtx_offset_param < 6);
1550 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1551 LLVMConstInt(ctx->ac.i32, 4, false), "");
1552
1553 param = shader_io_get_unique_index(location);
1554
1555 for (unsigned i = component; i < num_components + component; i++) {
1556 if (ctx->ac.chip_class >= GFX9) {
1557 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1558 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1559 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1560 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1561 } else {
1562 LLVMValueRef soffset =
1563 LLVMConstInt(ctx->ac.i32,
1564 (param * 4 + i + const_index) * 256,
1565 false);
1566
1567 value[i] = ac_build_buffer_load(&ctx->ac,
1568 ctx->esgs_ring, 1,
1569 ctx->ac.i32_0,
1570 vtx_offset, soffset,
1571 0, 1, 0, true, false);
1572
1573 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
1574 type, "");
1575 }
1576 }
1577 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1578 result = ac_to_integer(&ctx->ac, result);
1579 return result;
1580 }
1581
1582
1583 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1584 {
1585 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1586 ac_build_kill_if_false(&ctx->ac, visible);
1587 }
1588
1589 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1590 enum glsl_interp_mode interp, unsigned location)
1591 {
1592 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1593
1594 switch (interp) {
1595 case INTERP_MODE_FLAT:
1596 default:
1597 return NULL;
1598 case INTERP_MODE_SMOOTH:
1599 case INTERP_MODE_NONE:
1600 if (location == INTERP_CENTER)
1601 return ctx->persp_center;
1602 else if (location == INTERP_CENTROID)
1603 return ctx->persp_centroid;
1604 else if (location == INTERP_SAMPLE)
1605 return ctx->persp_sample;
1606 break;
1607 case INTERP_MODE_NOPERSPECTIVE:
1608 if (location == INTERP_CENTER)
1609 return ctx->linear_center;
1610 else if (location == INTERP_CENTROID)
1611 return ctx->linear_centroid;
1612 else if (location == INTERP_SAMPLE)
1613 return ctx->linear_sample;
1614 break;
1615 }
1616 return NULL;
1617 }
1618
1619 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1620 LLVMValueRef sample_id)
1621 {
1622 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1623
1624 LLVMValueRef result;
1625 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1626
1627 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1628 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1629
1630 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
1631 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1632
1633 return result;
1634 }
1635
1636
1637 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1638 {
1639 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1640 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
1641 ctx->options->key.fs.log2_num_samples :
1642 ctx->options->key.fs.log2_ps_iter_samples;
1643
1644 /* The bit pattern matches that used by fixed function fragment
1645 * processing. */
1646 static const uint16_t ps_iter_masks[] = {
1647 0xffff, /* not used */
1648 0x5555,
1649 0x1111,
1650 0x0101,
1651 0x0001,
1652 };
1653 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1654
1655 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1656
1657 LLVMValueRef result, sample_id;
1658 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1659 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1660 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1661 return result;
1662 }
1663
1664
1665 static void
1666 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1667 {
1668 LLVMValueRef gs_next_vertex;
1669 LLVMValueRef can_emit;
1670 int idx;
1671 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1672
1673 assert(stream == 0);
1674
1675 /* Write vertex attribute values to GSVS ring */
1676 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1677 ctx->gs_next_vertex,
1678 "");
1679
1680 /* If this thread has already emitted the declared maximum number of
1681 * vertices, kill it: excessive vertex emissions are not supposed to
1682 * have any effect, and GS threads have no externally observable
1683 * effects other than emitting vertices.
1684 */
1685 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1686 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1687 ac_build_kill_if_false(&ctx->ac, can_emit);
1688
1689 /* loop num outputs */
1690 idx = 0;
1691 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1692 unsigned output_usage_mask =
1693 ctx->shader_info->info.gs.output_usage_mask[i];
1694 LLVMValueRef *out_ptr = &addrs[i * 4];
1695 int length = 4;
1696 int slot = idx;
1697 int slot_inc = 1;
1698
1699 if (!(ctx->output_mask & (1ull << i)))
1700 continue;
1701
1702 if (i == VARYING_SLOT_CLIP_DIST0) {
1703 /* pack clip and cull into a single set of slots */
1704 length = ctx->num_output_clips + ctx->num_output_culls;
1705 if (length > 4)
1706 slot_inc = 2;
1707 output_usage_mask = (1 << length) - 1;
1708 }
1709
1710 for (unsigned j = 0; j < length; j++) {
1711 if (!(output_usage_mask & (1 << j)))
1712 continue;
1713
1714 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1715 out_ptr[j], "");
1716 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1717 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1718 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1719
1720 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1721
1722 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1723 out_val, 1,
1724 voffset, ctx->gs2vs_offset, 0,
1725 1, 1, true, true);
1726 }
1727 idx += slot_inc;
1728 }
1729
1730 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1731 ctx->ac.i32_1, "");
1732 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1733
1734 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1735 }
1736
1737 static void
1738 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1739 {
1740 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1741 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1742 }
1743
1744 static LLVMValueRef
1745 load_tess_coord(struct ac_shader_abi *abi)
1746 {
1747 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1748
1749 LLVMValueRef coord[4] = {
1750 ctx->tes_u,
1751 ctx->tes_v,
1752 ctx->ac.f32_0,
1753 ctx->ac.f32_0,
1754 };
1755
1756 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1757 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1758 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1759
1760 return ac_build_gather_values(&ctx->ac, coord, 3);
1761 }
1762
1763 static LLVMValueRef
1764 load_patch_vertices_in(struct ac_shader_abi *abi)
1765 {
1766 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1767 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1768 }
1769
1770
1771 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1772 {
1773 return abi->base_vertex;
1774 }
1775
1776 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1777 LLVMValueRef buffer_ptr, bool write)
1778 {
1779 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1780 LLVMValueRef result;
1781
1782 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1783
1784 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1785 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1786
1787 return result;
1788 }
1789
1790 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1791 {
1792 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1793 LLVMValueRef result;
1794
1795 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1796
1797 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1798 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1799
1800 return result;
1801 }
1802
1803 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1804 unsigned descriptor_set,
1805 unsigned base_index,
1806 unsigned constant_index,
1807 LLVMValueRef index,
1808 enum ac_descriptor_type desc_type,
1809 bool image, bool write,
1810 bool bindless)
1811 {
1812 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1813 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1814 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1815 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1816 unsigned offset = binding->offset;
1817 unsigned stride = binding->size;
1818 unsigned type_size;
1819 LLVMBuilderRef builder = ctx->ac.builder;
1820 LLVMTypeRef type;
1821
1822 assert(base_index < layout->binding_count);
1823
1824 switch (desc_type) {
1825 case AC_DESC_IMAGE:
1826 type = ctx->ac.v8i32;
1827 type_size = 32;
1828 break;
1829 case AC_DESC_FMASK:
1830 type = ctx->ac.v8i32;
1831 offset += 32;
1832 type_size = 32;
1833 break;
1834 case AC_DESC_SAMPLER:
1835 type = ctx->ac.v4i32;
1836 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1837 offset += 64;
1838
1839 type_size = 16;
1840 break;
1841 case AC_DESC_BUFFER:
1842 type = ctx->ac.v4i32;
1843 type_size = 16;
1844 break;
1845 default:
1846 unreachable("invalid desc_type\n");
1847 }
1848
1849 offset += constant_index * stride;
1850
1851 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1852 (!index || binding->immutable_samplers_equal)) {
1853 if (binding->immutable_samplers_equal)
1854 constant_index = 0;
1855
1856 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1857
1858 LLVMValueRef constants[] = {
1859 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1860 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1861 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1862 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1863 };
1864 return ac_build_gather_values(&ctx->ac, constants, 4);
1865 }
1866
1867 assert(stride % type_size == 0);
1868
1869 if (!index)
1870 index = ctx->ac.i32_0;
1871
1872 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1873
1874 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1875 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
1876
1877 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1878 }
1879
1880 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1881 * so we may need to fix it up. */
1882 static LLVMValueRef
1883 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1884 unsigned adjustment,
1885 LLVMValueRef alpha)
1886 {
1887 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1888 return alpha;
1889
1890 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1891
1892 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1893 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1894 else
1895 alpha = ac_to_integer(&ctx->ac, alpha);
1896
1897 /* For the integer-like cases, do a natural sign extension.
1898 *
1899 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1900 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1901 * exponent.
1902 */
1903 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1904 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1905 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1906 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1907
1908 /* Convert back to the right type. */
1909 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1910 LLVMValueRef clamp;
1911 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1912 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1913 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1914 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1915 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1916 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1917 }
1918
1919 return alpha;
1920 }
1921
1922 static void
1923 handle_vs_input_decl(struct radv_shader_context *ctx,
1924 struct nir_variable *variable)
1925 {
1926 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1927 LLVMValueRef t_offset;
1928 LLVMValueRef t_list;
1929 LLVMValueRef input;
1930 LLVMValueRef buffer_index;
1931 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1932 uint8_t input_usage_mask =
1933 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1934 unsigned num_channels = util_last_bit(input_usage_mask);
1935
1936 variable->data.driver_location = variable->data.location * 4;
1937
1938 for (unsigned i = 0; i < attrib_count; ++i) {
1939 LLVMValueRef output[4];
1940 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1941
1942 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1943 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
1944
1945 if (divisor) {
1946 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
1947 ctx->abi.start_instance, "");
1948
1949 if (divisor != 1) {
1950 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1951 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1952 }
1953
1954 if (ctx->options->key.vs.as_ls) {
1955 ctx->shader_info->vs.vgpr_comp_cnt =
1956 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1957 } else {
1958 ctx->shader_info->vs.vgpr_comp_cnt =
1959 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1960 }
1961 } else {
1962 buffer_index = ctx->ac.i32_0;
1963 }
1964 } else
1965 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
1966 ctx->abi.base_vertex, "");
1967 t_offset = LLVMConstInt(ctx->ac.i32, attrib_index, false);
1968
1969 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1970
1971 input = ac_build_buffer_load_format(&ctx->ac, t_list,
1972 buffer_index,
1973 ctx->ac.i32_0,
1974 num_channels, false, true);
1975
1976 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
1977
1978 for (unsigned chan = 0; chan < 4; chan++) {
1979 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1980 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1981 }
1982
1983 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
1984 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
1985
1986 for (unsigned chan = 0; chan < 4; chan++) {
1987 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] =
1988 ac_to_integer(&ctx->ac, output[chan]);
1989 }
1990 }
1991 }
1992
1993 static void interp_fs_input(struct radv_shader_context *ctx,
1994 unsigned attr,
1995 LLVMValueRef interp_param,
1996 LLVMValueRef prim_mask,
1997 LLVMValueRef result[4])
1998 {
1999 LLVMValueRef attr_number;
2000 unsigned chan;
2001 LLVMValueRef i, j;
2002 bool interp = interp_param != NULL;
2003
2004 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
2005
2006 /* fs.constant returns the param from the middle vertex, so it's not
2007 * really useful for flat shading. It's meant to be used for custom
2008 * interpolation (but the intrinsic can't fetch from the other two
2009 * vertices).
2010 *
2011 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2012 * to do the right thing. The only reason we use fs.constant is that
2013 * fs.interp cannot be used on integers, because they can be equal
2014 * to NaN.
2015 */
2016 if (interp) {
2017 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
2018 ctx->ac.v2f32, "");
2019
2020 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2021 ctx->ac.i32_0, "");
2022 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2023 ctx->ac.i32_1, "");
2024 }
2025
2026 for (chan = 0; chan < 4; chan++) {
2027 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2028
2029 if (interp) {
2030 result[chan] = ac_build_fs_interp(&ctx->ac,
2031 llvm_chan,
2032 attr_number,
2033 prim_mask, i, j);
2034 } else {
2035 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2036 LLVMConstInt(ctx->ac.i32, 2, false),
2037 llvm_chan,
2038 attr_number,
2039 prim_mask);
2040 }
2041 }
2042 }
2043
2044 static void
2045 handle_fs_input_decl(struct radv_shader_context *ctx,
2046 struct nir_variable *variable)
2047 {
2048 int idx = variable->data.location;
2049 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2050 LLVMValueRef interp;
2051
2052 variable->data.driver_location = idx * 4;
2053 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
2054
2055 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
2056 unsigned interp_type;
2057 if (variable->data.sample)
2058 interp_type = INTERP_SAMPLE;
2059 else if (variable->data.centroid)
2060 interp_type = INTERP_CENTROID;
2061 else
2062 interp_type = INTERP_CENTER;
2063
2064 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
2065 } else
2066 interp = NULL;
2067
2068 for (unsigned i = 0; i < attrib_count; ++i)
2069 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
2070
2071 }
2072
2073 static void
2074 handle_vs_inputs(struct radv_shader_context *ctx,
2075 struct nir_shader *nir) {
2076 nir_foreach_variable(variable, &nir->inputs)
2077 handle_vs_input_decl(ctx, variable);
2078 }
2079
2080 static void
2081 prepare_interp_optimize(struct radv_shader_context *ctx,
2082 struct nir_shader *nir)
2083 {
2084 bool uses_center = false;
2085 bool uses_centroid = false;
2086 nir_foreach_variable(variable, &nir->inputs) {
2087 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2088 variable->data.sample)
2089 continue;
2090
2091 if (variable->data.centroid)
2092 uses_centroid = true;
2093 else
2094 uses_center = true;
2095 }
2096
2097 if (uses_center && uses_centroid) {
2098 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2099 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
2100 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
2101 }
2102 }
2103
2104 static void
2105 handle_fs_inputs(struct radv_shader_context *ctx,
2106 struct nir_shader *nir)
2107 {
2108 prepare_interp_optimize(ctx, nir);
2109
2110 nir_foreach_variable(variable, &nir->inputs)
2111 handle_fs_input_decl(ctx, variable);
2112
2113 unsigned index = 0;
2114
2115 if (ctx->shader_info->info.ps.uses_input_attachments ||
2116 ctx->shader_info->info.needs_multiview_view_index)
2117 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
2118
2119 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
2120 LLVMValueRef interp_param;
2121 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
2122
2123 if (!(ctx->input_mask & (1ull << i)))
2124 continue;
2125
2126 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
2127 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
2128 interp_param = *inputs;
2129 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
2130 inputs);
2131
2132 if (!interp_param)
2133 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
2134 ++index;
2135 } else if (i == VARYING_SLOT_POS) {
2136 for(int i = 0; i < 3; ++i)
2137 inputs[i] = ctx->abi.frag_pos[i];
2138
2139 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2140 ctx->abi.frag_pos[3]);
2141 }
2142 }
2143 ctx->shader_info->fs.num_interp = index;
2144 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
2145
2146 if (ctx->shader_info->info.needs_multiview_view_index)
2147 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2148 }
2149
2150 static void
2151 scan_shader_output_decl(struct radv_shader_context *ctx,
2152 struct nir_variable *variable,
2153 struct nir_shader *shader,
2154 gl_shader_stage stage)
2155 {
2156 int idx = variable->data.location + variable->data.index;
2157 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2158 uint64_t mask_attribs;
2159
2160 variable->data.driver_location = idx * 4;
2161
2162 /* tess ctrl has it's own load/store paths for outputs */
2163 if (stage == MESA_SHADER_TESS_CTRL)
2164 return;
2165
2166 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2167 if (stage == MESA_SHADER_VERTEX ||
2168 stage == MESA_SHADER_TESS_EVAL ||
2169 stage == MESA_SHADER_GEOMETRY) {
2170 if (idx == VARYING_SLOT_CLIP_DIST0) {
2171 int length = shader->info.clip_distance_array_size +
2172 shader->info.cull_distance_array_size;
2173 if (stage == MESA_SHADER_VERTEX) {
2174 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2175 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2176 }
2177 if (stage == MESA_SHADER_TESS_EVAL) {
2178 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2179 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2180 }
2181
2182 if (length > 4)
2183 attrib_count = 2;
2184 else
2185 attrib_count = 1;
2186 mask_attribs = 1ull << idx;
2187 }
2188 }
2189
2190 ctx->output_mask |= mask_attribs;
2191 }
2192
2193
2194 /* Initialize arguments for the shader export intrinsic */
2195 static void
2196 si_llvm_init_export_args(struct radv_shader_context *ctx,
2197 LLVMValueRef *values,
2198 unsigned enabled_channels,
2199 unsigned target,
2200 struct ac_export_args *args)
2201 {
2202 /* Specify the channels that are enabled. */
2203 args->enabled_channels = enabled_channels;
2204
2205 /* Specify whether the EXEC mask represents the valid mask */
2206 args->valid_mask = 0;
2207
2208 /* Specify whether this is the last export */
2209 args->done = 0;
2210
2211 /* Specify the target we are exporting */
2212 args->target = target;
2213
2214 args->compr = false;
2215 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2216 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2217 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2218 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2219
2220 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2221 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2222 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2223 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2224 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2225 unsigned chan;
2226
2227 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2228 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2229 unsigned bits, bool hi) = NULL;
2230
2231 switch(col_format) {
2232 case V_028714_SPI_SHADER_ZERO:
2233 args->enabled_channels = 0; /* writemask */
2234 args->target = V_008DFC_SQ_EXP_NULL;
2235 break;
2236
2237 case V_028714_SPI_SHADER_32_R:
2238 args->enabled_channels = 1;
2239 args->out[0] = values[0];
2240 break;
2241
2242 case V_028714_SPI_SHADER_32_GR:
2243 args->enabled_channels = 0x3;
2244 args->out[0] = values[0];
2245 args->out[1] = values[1];
2246 break;
2247
2248 case V_028714_SPI_SHADER_32_AR:
2249 args->enabled_channels = 0x9;
2250 args->out[0] = values[0];
2251 args->out[3] = values[3];
2252 break;
2253
2254 case V_028714_SPI_SHADER_FP16_ABGR:
2255 args->enabled_channels = 0x5;
2256 packf = ac_build_cvt_pkrtz_f16;
2257 break;
2258
2259 case V_028714_SPI_SHADER_UNORM16_ABGR:
2260 args->enabled_channels = 0x5;
2261 packf = ac_build_cvt_pknorm_u16;
2262 break;
2263
2264 case V_028714_SPI_SHADER_SNORM16_ABGR:
2265 args->enabled_channels = 0x5;
2266 packf = ac_build_cvt_pknorm_i16;
2267 break;
2268
2269 case V_028714_SPI_SHADER_UINT16_ABGR:
2270 args->enabled_channels = 0x5;
2271 packi = ac_build_cvt_pk_u16;
2272 break;
2273
2274 case V_028714_SPI_SHADER_SINT16_ABGR:
2275 args->enabled_channels = 0x5;
2276 packi = ac_build_cvt_pk_i16;
2277 break;
2278
2279 default:
2280 case V_028714_SPI_SHADER_32_ABGR:
2281 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2282 break;
2283 }
2284
2285 /* Pack f16 or norm_i16/u16. */
2286 if (packf) {
2287 for (chan = 0; chan < 2; chan++) {
2288 LLVMValueRef pack_args[2] = {
2289 values[2 * chan],
2290 values[2 * chan + 1]
2291 };
2292 LLVMValueRef packed;
2293
2294 packed = packf(&ctx->ac, pack_args);
2295 args->out[chan] = ac_to_float(&ctx->ac, packed);
2296 }
2297 args->compr = 1; /* COMPR flag */
2298 }
2299
2300 /* Pack i16/u16. */
2301 if (packi) {
2302 for (chan = 0; chan < 2; chan++) {
2303 LLVMValueRef pack_args[2] = {
2304 ac_to_integer(&ctx->ac, values[2 * chan]),
2305 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2306 };
2307 LLVMValueRef packed;
2308
2309 packed = packi(&ctx->ac, pack_args,
2310 is_int8 ? 8 : is_int10 ? 10 : 16,
2311 chan == 1);
2312 args->out[chan] = ac_to_float(&ctx->ac, packed);
2313 }
2314 args->compr = 1; /* COMPR flag */
2315 }
2316 return;
2317 }
2318
2319 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2320
2321 for (unsigned i = 0; i < 4; ++i) {
2322 if (!(args->enabled_channels & (1 << i)))
2323 continue;
2324
2325 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2326 }
2327 }
2328
2329 static void
2330 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2331 LLVMValueRef *values, unsigned enabled_channels)
2332 {
2333 struct ac_export_args args;
2334
2335 si_llvm_init_export_args(ctx, values, enabled_channels,
2336 V_008DFC_SQ_EXP_PARAM + index, &args);
2337 ac_build_export(&ctx->ac, &args);
2338 }
2339
2340 static LLVMValueRef
2341 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2342 {
2343 LLVMValueRef output =
2344 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2345
2346 return LLVMBuildLoad(ctx->ac.builder, output, "");
2347 }
2348
2349 static void
2350 handle_vs_outputs_post(struct radv_shader_context *ctx,
2351 bool export_prim_id, bool export_layer_id,
2352 struct radv_vs_output_info *outinfo)
2353 {
2354 uint32_t param_count = 0;
2355 unsigned target;
2356 unsigned pos_idx, num_pos_exports = 0;
2357 struct ac_export_args args, pos_args[4] = {};
2358 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2359 int i;
2360
2361 if (ctx->options->key.has_multiview_view_index) {
2362 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2363 if(!*tmp_out) {
2364 for(unsigned i = 0; i < 4; ++i)
2365 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2366 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2367 }
2368
2369 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2370 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2371 }
2372
2373 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2374 sizeof(outinfo->vs_output_param_offset));
2375
2376 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2377 LLVMValueRef slots[8];
2378 unsigned j;
2379
2380 if (outinfo->cull_dist_mask)
2381 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2382
2383 i = VARYING_SLOT_CLIP_DIST0;
2384 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
2385 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2386
2387 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
2388 slots[i] = LLVMGetUndef(ctx->ac.f32);
2389
2390 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
2391 target = V_008DFC_SQ_EXP_POS + 3;
2392 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2393 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2394 &args, sizeof(args));
2395 }
2396
2397 target = V_008DFC_SQ_EXP_POS + 2;
2398 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2399 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2400 &args, sizeof(args));
2401
2402 }
2403
2404 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2405 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2406 for (unsigned j = 0; j < 4; j++)
2407 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2408 }
2409 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2410
2411 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2412 outinfo->writes_pointsize = true;
2413 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2414 }
2415
2416 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2417 outinfo->writes_layer = true;
2418 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2419 }
2420
2421 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2422 outinfo->writes_viewport_index = true;
2423 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2424 }
2425
2426 if (outinfo->writes_pointsize ||
2427 outinfo->writes_layer ||
2428 outinfo->writes_viewport_index) {
2429 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2430 (outinfo->writes_layer == true ? 4 : 0));
2431 pos_args[1].valid_mask = 0;
2432 pos_args[1].done = 0;
2433 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2434 pos_args[1].compr = 0;
2435 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2436 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2437 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2438 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2439
2440 if (outinfo->writes_pointsize == true)
2441 pos_args[1].out[0] = psize_value;
2442 if (outinfo->writes_layer == true)
2443 pos_args[1].out[2] = layer_value;
2444 if (outinfo->writes_viewport_index == true) {
2445 if (ctx->options->chip_class >= GFX9) {
2446 /* GFX9 has the layer in out.z[10:0] and the viewport
2447 * index in out.z[19:16].
2448 */
2449 LLVMValueRef v = viewport_index_value;
2450 v = ac_to_integer(&ctx->ac, v);
2451 v = LLVMBuildShl(ctx->ac.builder, v,
2452 LLVMConstInt(ctx->ac.i32, 16, false),
2453 "");
2454 v = LLVMBuildOr(ctx->ac.builder, v,
2455 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2456
2457 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2458 pos_args[1].enabled_channels |= 1 << 2;
2459 } else {
2460 pos_args[1].out[3] = viewport_index_value;
2461 pos_args[1].enabled_channels |= 1 << 3;
2462 }
2463 }
2464 }
2465 for (i = 0; i < 4; i++) {
2466 if (pos_args[i].out[0])
2467 num_pos_exports++;
2468 }
2469
2470 pos_idx = 0;
2471 for (i = 0; i < 4; i++) {
2472 if (!pos_args[i].out[0])
2473 continue;
2474
2475 /* Specify the target we are exporting */
2476 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2477 if (pos_idx == num_pos_exports)
2478 pos_args[i].done = 1;
2479 ac_build_export(&ctx->ac, &pos_args[i]);
2480 }
2481
2482 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2483 LLVMValueRef values[4];
2484 if (!(ctx->output_mask & (1ull << i)))
2485 continue;
2486
2487 if (i != VARYING_SLOT_LAYER &&
2488 i != VARYING_SLOT_PRIMITIVE_ID &&
2489 i < VARYING_SLOT_VAR0)
2490 continue;
2491
2492 for (unsigned j = 0; j < 4; j++)
2493 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2494
2495 unsigned output_usage_mask;
2496
2497 if (ctx->stage == MESA_SHADER_VERTEX &&
2498 !ctx->is_gs_copy_shader) {
2499 output_usage_mask =
2500 ctx->shader_info->info.vs.output_usage_mask[i];
2501 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2502 output_usage_mask =
2503 ctx->shader_info->info.tes.output_usage_mask[i];
2504 } else {
2505 assert(ctx->is_gs_copy_shader);
2506 output_usage_mask =
2507 ctx->shader_info->info.gs.output_usage_mask[i];
2508 }
2509
2510 radv_export_param(ctx, param_count, values, output_usage_mask);
2511
2512 outinfo->vs_output_param_offset[i] = param_count++;
2513 }
2514
2515 if (export_prim_id) {
2516 LLVMValueRef values[4];
2517
2518 values[0] = ctx->vs_prim_id;
2519 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2520 ctx->shader_info->vs.vgpr_comp_cnt);
2521 for (unsigned j = 1; j < 4; j++)
2522 values[j] = ctx->ac.f32_0;
2523
2524 radv_export_param(ctx, param_count, values, 0x1);
2525
2526 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2527 outinfo->export_prim_id = true;
2528 }
2529
2530 if (export_layer_id && layer_value) {
2531 LLVMValueRef values[4];
2532
2533 values[0] = layer_value;
2534 for (unsigned j = 1; j < 4; j++)
2535 values[j] = ctx->ac.f32_0;
2536
2537 radv_export_param(ctx, param_count, values, 0x1);
2538
2539 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2540 }
2541
2542 outinfo->pos_exports = num_pos_exports;
2543 outinfo->param_exports = param_count;
2544 }
2545
2546 static void
2547 handle_es_outputs_post(struct radv_shader_context *ctx,
2548 struct radv_es_output_info *outinfo)
2549 {
2550 int j;
2551 uint64_t max_output_written = 0;
2552 LLVMValueRef lds_base = NULL;
2553
2554 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2555 int param_index;
2556 int length = 4;
2557
2558 if (!(ctx->output_mask & (1ull << i)))
2559 continue;
2560
2561 if (i == VARYING_SLOT_CLIP_DIST0)
2562 length = ctx->num_output_clips + ctx->num_output_culls;
2563
2564 param_index = shader_io_get_unique_index(i);
2565
2566 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2567 }
2568
2569 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2570
2571 if (ctx->ac.chip_class >= GFX9) {
2572 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2573 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2574 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2575 LLVMConstInt(ctx->ac.i32, 24, false),
2576 LLVMConstInt(ctx->ac.i32, 4, false), false);
2577 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2578 LLVMBuildMul(ctx->ac.builder, wave_idx,
2579 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2580 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2581 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2582 }
2583
2584 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2585 LLVMValueRef dw_addr = NULL;
2586 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2587 unsigned output_usage_mask;
2588 int param_index;
2589 int length = 4;
2590
2591 if (!(ctx->output_mask & (1ull << i)))
2592 continue;
2593
2594 if (ctx->stage == MESA_SHADER_VERTEX) {
2595 output_usage_mask =
2596 ctx->shader_info->info.vs.output_usage_mask[i];
2597 } else {
2598 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2599 output_usage_mask =
2600 ctx->shader_info->info.tes.output_usage_mask[i];
2601 }
2602
2603 if (i == VARYING_SLOT_CLIP_DIST0) {
2604 length = ctx->num_output_clips + ctx->num_output_culls;
2605 output_usage_mask = (1 << length) - 1;
2606 }
2607
2608 param_index = shader_io_get_unique_index(i);
2609
2610 if (lds_base) {
2611 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2612 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2613 "");
2614 }
2615
2616 for (j = 0; j < length; j++) {
2617 if (!(output_usage_mask & (1 << j)))
2618 continue;
2619
2620 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2621 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2622
2623 if (ctx->ac.chip_class >= GFX9) {
2624 LLVMValueRef dw_addr_offset =
2625 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2626 LLVMConstInt(ctx->ac.i32,
2627 j, false), "");
2628
2629 ac_lds_store(&ctx->ac, dw_addr_offset,
2630 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2631 } else {
2632 ac_build_buffer_store_dword(&ctx->ac,
2633 ctx->esgs_ring,
2634 out_val, 1,
2635 NULL, ctx->es2gs_offset,
2636 (4 * param_index + j) * 4,
2637 1, 1, true, true);
2638 }
2639 }
2640 }
2641 }
2642
2643 static void
2644 handle_ls_outputs_post(struct radv_shader_context *ctx)
2645 {
2646 LLVMValueRef vertex_id = ctx->rel_auto_id;
2647 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2648 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2649 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2650 vertex_dw_stride, "");
2651
2652 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2653 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2654 int length = 4;
2655
2656 if (!(ctx->output_mask & (1ull << i)))
2657 continue;
2658
2659 if (i == VARYING_SLOT_CLIP_DIST0)
2660 length = ctx->num_output_clips + ctx->num_output_culls;
2661 int param = shader_io_get_unique_index(i);
2662 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2663 LLVMConstInt(ctx->ac.i32, param * 4, false),
2664 "");
2665 for (unsigned j = 0; j < length; j++) {
2666 ac_lds_store(&ctx->ac, dw_addr,
2667 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2668 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2669 }
2670 }
2671 }
2672
2673 static void
2674 write_tess_factors(struct radv_shader_context *ctx)
2675 {
2676 unsigned stride, outer_comps, inner_comps;
2677 struct ac_build_if_state if_ctx, inner_if_ctx;
2678 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2679 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2680 unsigned tess_inner_index = 0, tess_outer_index;
2681 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2682 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2683 int i;
2684 ac_emit_barrier(&ctx->ac, ctx->stage);
2685
2686 switch (ctx->options->key.tcs.primitive_mode) {
2687 case GL_ISOLINES:
2688 stride = 2;
2689 outer_comps = 2;
2690 inner_comps = 0;
2691 break;
2692 case GL_TRIANGLES:
2693 stride = 4;
2694 outer_comps = 3;
2695 inner_comps = 1;
2696 break;
2697 case GL_QUADS:
2698 stride = 6;
2699 outer_comps = 4;
2700 inner_comps = 2;
2701 break;
2702 default:
2703 return;
2704 }
2705
2706 ac_nir_build_if(&if_ctx, ctx,
2707 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2708 invocation_id, ctx->ac.i32_0, ""));
2709
2710 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2711
2712 if (inner_comps) {
2713 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2714 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2715 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2716 }
2717
2718 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2719 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2720 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2721
2722 for (i = 0; i < 4; i++) {
2723 inner[i] = LLVMGetUndef(ctx->ac.i32);
2724 outer[i] = LLVMGetUndef(ctx->ac.i32);
2725 }
2726
2727 // LINES reversal
2728 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2729 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2730 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2731 ctx->ac.i32_1, "");
2732 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2733 } else {
2734 for (i = 0; i < outer_comps; i++) {
2735 outer[i] = out[i] =
2736 ac_lds_load(&ctx->ac, lds_outer);
2737 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2738 ctx->ac.i32_1, "");
2739 }
2740 for (i = 0; i < inner_comps; i++) {
2741 inner[i] = out[outer_comps+i] =
2742 ac_lds_load(&ctx->ac, lds_inner);
2743 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2744 ctx->ac.i32_1, "");
2745 }
2746 }
2747
2748 /* Convert the outputs to vectors for stores. */
2749 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2750 vec1 = NULL;
2751
2752 if (stride > 4)
2753 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2754
2755
2756 buffer = ctx->hs_ring_tess_factor;
2757 tf_base = ctx->tess_factor_offset;
2758 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2759 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2760 unsigned tf_offset = 0;
2761
2762 if (ctx->options->chip_class <= VI) {
2763 ac_nir_build_if(&inner_if_ctx, ctx,
2764 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2765 rel_patch_id, ctx->ac.i32_0, ""));
2766
2767 /* Store the dynamic HS control word. */
2768 ac_build_buffer_store_dword(&ctx->ac, buffer,
2769 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2770 1, ctx->ac.i32_0, tf_base,
2771 0, 1, 0, true, false);
2772 tf_offset += 4;
2773
2774 ac_nir_build_endif(&inner_if_ctx);
2775 }
2776
2777 /* Store the tessellation factors. */
2778 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2779 MIN2(stride, 4), byteoffset, tf_base,
2780 tf_offset, 1, 0, true, false);
2781 if (vec1)
2782 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2783 stride - 4, byteoffset, tf_base,
2784 16 + tf_offset, 1, 0, true, false);
2785
2786 //store to offchip for TES to read - only if TES reads them
2787 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2788 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2789 LLVMValueRef tf_inner_offset;
2790 unsigned param_outer, param_inner;
2791
2792 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2793 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2794 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2795
2796 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2797 util_next_power_of_two(outer_comps));
2798
2799 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2800 outer_comps, tf_outer_offset,
2801 ctx->oc_lds, 0, 1, 0, true, false);
2802 if (inner_comps) {
2803 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2804 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2805 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2806
2807 inner_vec = inner_comps == 1 ? inner[0] :
2808 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2809 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2810 inner_comps, tf_inner_offset,
2811 ctx->oc_lds, 0, 1, 0, true, false);
2812 }
2813 }
2814 ac_nir_build_endif(&if_ctx);
2815 }
2816
2817 static void
2818 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2819 {
2820 write_tess_factors(ctx);
2821 }
2822
2823 static bool
2824 si_export_mrt_color(struct radv_shader_context *ctx,
2825 LLVMValueRef *color, unsigned index,
2826 struct ac_export_args *args)
2827 {
2828 /* Export */
2829 si_llvm_init_export_args(ctx, color, 0xf,
2830 V_008DFC_SQ_EXP_MRT + index, args);
2831 if (!args->enabled_channels)
2832 return false; /* unnecessary NULL export */
2833
2834 return true;
2835 }
2836
2837 static void
2838 radv_export_mrt_z(struct radv_shader_context *ctx,
2839 LLVMValueRef depth, LLVMValueRef stencil,
2840 LLVMValueRef samplemask)
2841 {
2842 struct ac_export_args args;
2843
2844 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2845
2846 ac_build_export(&ctx->ac, &args);
2847 }
2848
2849 static void
2850 handle_fs_outputs_post(struct radv_shader_context *ctx)
2851 {
2852 unsigned index = 0;
2853 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2854 struct ac_export_args color_args[8];
2855
2856 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2857 LLVMValueRef values[4];
2858
2859 if (!(ctx->output_mask & (1ull << i)))
2860 continue;
2861
2862 if (i < FRAG_RESULT_DATA0)
2863 continue;
2864
2865 for (unsigned j = 0; j < 4; j++)
2866 values[j] = ac_to_float(&ctx->ac,
2867 radv_load_output(ctx, i, j));
2868
2869 bool ret = si_export_mrt_color(ctx, values,
2870 i - FRAG_RESULT_DATA0,
2871 &color_args[index]);
2872 if (ret)
2873 index++;
2874 }
2875
2876 /* Process depth, stencil, samplemask. */
2877 if (ctx->shader_info->info.ps.writes_z) {
2878 depth = ac_to_float(&ctx->ac,
2879 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
2880 }
2881 if (ctx->shader_info->info.ps.writes_stencil) {
2882 stencil = ac_to_float(&ctx->ac,
2883 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
2884 }
2885 if (ctx->shader_info->info.ps.writes_sample_mask) {
2886 samplemask = ac_to_float(&ctx->ac,
2887 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
2888 }
2889
2890 /* Set the DONE bit on last non-null color export only if Z isn't
2891 * exported.
2892 */
2893 if (index > 0 &&
2894 !ctx->shader_info->info.ps.writes_z &&
2895 !ctx->shader_info->info.ps.writes_stencil &&
2896 !ctx->shader_info->info.ps.writes_sample_mask) {
2897 unsigned last = index - 1;
2898
2899 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
2900 color_args[last].done = 1; /* DONE bit */
2901 }
2902
2903 /* Export PS outputs. */
2904 for (unsigned i = 0; i < index; i++)
2905 ac_build_export(&ctx->ac, &color_args[i]);
2906
2907 if (depth || stencil || samplemask)
2908 radv_export_mrt_z(ctx, depth, stencil, samplemask);
2909 else if (!index)
2910 ac_build_export_null(&ctx->ac);
2911 }
2912
2913 static void
2914 emit_gs_epilogue(struct radv_shader_context *ctx)
2915 {
2916 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
2917 }
2918
2919 static void
2920 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
2921 LLVMValueRef *addrs)
2922 {
2923 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2924
2925 switch (ctx->stage) {
2926 case MESA_SHADER_VERTEX:
2927 if (ctx->options->key.vs.as_ls)
2928 handle_ls_outputs_post(ctx);
2929 else if (ctx->options->key.vs.as_es)
2930 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
2931 else
2932 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
2933 ctx->options->key.vs.export_layer_id,
2934 &ctx->shader_info->vs.outinfo);
2935 break;
2936 case MESA_SHADER_FRAGMENT:
2937 handle_fs_outputs_post(ctx);
2938 break;
2939 case MESA_SHADER_GEOMETRY:
2940 emit_gs_epilogue(ctx);
2941 break;
2942 case MESA_SHADER_TESS_CTRL:
2943 handle_tcs_outputs_post(ctx);
2944 break;
2945 case MESA_SHADER_TESS_EVAL:
2946 if (ctx->options->key.tes.as_es)
2947 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
2948 else
2949 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
2950 ctx->options->key.tes.export_layer_id,
2951 &ctx->shader_info->tes.outinfo);
2952 break;
2953 default:
2954 break;
2955 }
2956 }
2957
2958 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
2959 {
2960 LLVMPassManagerRef passmgr;
2961 /* Create the pass manager */
2962 passmgr = LLVMCreateFunctionPassManagerForModule(
2963 ctx->ac.module);
2964
2965 /* This pass should eliminate all the load and store instructions */
2966 LLVMAddPromoteMemoryToRegisterPass(passmgr);
2967
2968 /* Add some optimization passes */
2969 LLVMAddScalarReplAggregatesPass(passmgr);
2970 LLVMAddLICMPass(passmgr);
2971 LLVMAddAggressiveDCEPass(passmgr);
2972 LLVMAddCFGSimplificationPass(passmgr);
2973 LLVMAddInstructionCombiningPass(passmgr);
2974
2975 /* Run the pass */
2976 LLVMInitializeFunctionPassManager(passmgr);
2977 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
2978 LLVMFinalizeFunctionPassManager(passmgr);
2979
2980 LLVMDisposeBuilder(ctx->ac.builder);
2981 LLVMDisposePassManager(passmgr);
2982
2983 ac_llvm_context_dispose(&ctx->ac);
2984 }
2985
2986 static void
2987 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
2988 {
2989 struct radv_vs_output_info *outinfo;
2990
2991 switch (ctx->stage) {
2992 case MESA_SHADER_FRAGMENT:
2993 case MESA_SHADER_COMPUTE:
2994 case MESA_SHADER_TESS_CTRL:
2995 case MESA_SHADER_GEOMETRY:
2996 return;
2997 case MESA_SHADER_VERTEX:
2998 if (ctx->options->key.vs.as_ls ||
2999 ctx->options->key.vs.as_es)
3000 return;
3001 outinfo = &ctx->shader_info->vs.outinfo;
3002 break;
3003 case MESA_SHADER_TESS_EVAL:
3004 if (ctx->options->key.vs.as_es)
3005 return;
3006 outinfo = &ctx->shader_info->tes.outinfo;
3007 break;
3008 default:
3009 unreachable("Unhandled shader type");
3010 }
3011
3012 ac_optimize_vs_outputs(&ctx->ac,
3013 ctx->main_function,
3014 outinfo->vs_output_param_offset,
3015 VARYING_SLOT_MAX,
3016 &outinfo->param_exports);
3017 }
3018
3019 static void
3020 ac_setup_rings(struct radv_shader_context *ctx)
3021 {
3022 if (ctx->options->chip_class <= VI &&
3023 (ctx->stage == MESA_SHADER_GEOMETRY ||
3024 ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
3025 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3026 : RING_ESGS_VS;
3027 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3028
3029 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3030 ctx->ring_offsets,
3031 offset);
3032 }
3033
3034 if (ctx->is_gs_copy_shader) {
3035 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
3036 }
3037 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3038 LLVMValueRef tmp;
3039 uint32_t num_entries = 64;
3040 LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size, false);
3041 LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size << 16, false);
3042 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
3043
3044 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
3045
3046 tmp = LLVMConstInt(ctx->ac.i32, num_entries, false);
3047 if (ctx->options->chip_class >= VI)
3048 tmp = LLVMBuildMul(ctx->ac.builder, gsvs_ring_stride, tmp, "");
3049 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
3050 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
3051 tmp = LLVMBuildOr(ctx->ac.builder, tmp, gsvs_ring_desc, "");
3052 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
3053 }
3054
3055 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3056 ctx->stage == MESA_SHADER_TESS_EVAL) {
3057 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3058 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3059 }
3060 }
3061
3062 static unsigned
3063 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
3064 const struct nir_shader *nir)
3065 {
3066 switch (nir->info.stage) {
3067 case MESA_SHADER_TESS_CTRL:
3068 return chip_class >= CIK ? 128 : 64;
3069 case MESA_SHADER_GEOMETRY:
3070 return chip_class >= GFX9 ? 128 : 64;
3071 case MESA_SHADER_COMPUTE:
3072 break;
3073 default:
3074 return 0;
3075 }
3076
3077 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
3078 nir->info.cs.local_size[1] *
3079 nir->info.cs.local_size[2];
3080 return max_workgroup_size;
3081 }
3082
3083 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3084 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3085 {
3086 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3087 LLVMConstInt(ctx->ac.i32, 8, false),
3088 LLVMConstInt(ctx->ac.i32, 8, false), false);
3089 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3090 ctx->ac.i32_0, "");
3091 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
3092 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
3093 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
3094 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3095 }
3096
3097 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3098 {
3099 for(int i = 5; i >= 0; --i) {
3100 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3101 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
3102 LLVMConstInt(ctx->ac.i32, 16, false), false);
3103 }
3104
3105 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3106 LLVMConstInt(ctx->ac.i32, 16, false),
3107 LLVMConstInt(ctx->ac.i32, 8, false), false);
3108 }
3109
3110
3111 static
3112 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
3113 struct nir_shader *const *shaders,
3114 int shader_count,
3115 struct radv_shader_variant_info *shader_info,
3116 const struct radv_nir_compiler_options *options)
3117 {
3118 struct radv_shader_context ctx = {0};
3119 unsigned i;
3120 ctx.options = options;
3121 ctx.shader_info = shader_info;
3122 ctx.context = LLVMContextCreate();
3123
3124 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3125 options->family);
3126 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3127 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
3128
3129 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
3130 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
3131 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
3132 LLVMDisposeTargetData(data_layout);
3133 LLVMDisposeMessage(data_layout_str);
3134
3135 enum ac_float_mode float_mode =
3136 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3137 AC_FLOAT_MODE_DEFAULT;
3138
3139 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3140
3141 memset(shader_info, 0, sizeof(*shader_info));
3142
3143 for(int i = 0; i < shader_count; ++i)
3144 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3145
3146 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3147 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3148 for (i = 0; i < AC_UD_MAX_UD; i++)
3149 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3150
3151 ctx.max_workgroup_size = 0;
3152 for (int i = 0; i < shader_count; ++i) {
3153 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3154 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3155 shaders[i]));
3156 }
3157
3158 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3159 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3160
3161 ctx.abi.inputs = &ctx.inputs[0];
3162 ctx.abi.emit_outputs = handle_shader_outputs_post;
3163 ctx.abi.emit_vertex = visit_emit_vertex;
3164 ctx.abi.load_ubo = radv_load_ubo;
3165 ctx.abi.load_ssbo = radv_load_ssbo;
3166 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3167 ctx.abi.load_resource = radv_load_resource;
3168 ctx.abi.clamp_shadow_reference = false;
3169 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9;
3170
3171 if (shader_count >= 2)
3172 ac_init_exec_full_mask(&ctx.ac);
3173
3174 if (ctx.ac.chip_class == GFX9 &&
3175 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3176 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3177
3178 for(int i = 0; i < shader_count; ++i) {
3179 ctx.stage = shaders[i]->info.stage;
3180 ctx.output_mask = 0;
3181 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3182 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3183
3184 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3185 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3186 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3187 ctx.abi.load_inputs = load_gs_input;
3188 ctx.abi.emit_primitive = visit_end_primitive;
3189 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3190 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3191 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3192 ctx.abi.load_tess_varyings = load_tcs_varyings;
3193 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3194 ctx.abi.store_tcs_outputs = store_tcs_output;
3195 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3196 if (shader_count == 1)
3197 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3198 else
3199 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3200 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3201 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3202 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3203 ctx.abi.load_tess_varyings = load_tes_input;
3204 ctx.abi.load_tess_coord = load_tess_coord;
3205 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3206 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3207 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3208 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3209 if (shader_info->info.vs.needs_instance_id) {
3210 if (ctx.options->key.vs.as_ls) {
3211 ctx.shader_info->vs.vgpr_comp_cnt =
3212 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3213 } else {
3214 ctx.shader_info->vs.vgpr_comp_cnt =
3215 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3216 }
3217 }
3218 ctx.abi.load_base_vertex = radv_load_base_vertex;
3219 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3220 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3221 ctx.abi.lookup_interp_param = lookup_interp_param;
3222 ctx.abi.load_sample_position = load_sample_position;
3223 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3224 ctx.abi.emit_kill = radv_emit_kill;
3225 }
3226
3227 if (i)
3228 ac_emit_barrier(&ctx.ac, ctx.stage);
3229
3230 nir_foreach_variable(variable, &shaders[i]->outputs)
3231 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3232
3233 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3234 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3235 shaders[i]->info.cull_distance_array_size > 4;
3236 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3237 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3238 shaders[i]->info.gs.vertices_out;
3239 }
3240
3241 ac_setup_rings(&ctx);
3242
3243 LLVMBasicBlockRef merge_block;
3244 if (shader_count >= 2) {
3245 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3246 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3247 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3248
3249 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3250 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3251 LLVMConstInt(ctx.ac.i32, 8, false), false);
3252 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3253 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3254 thread_id, count, "");
3255 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3256
3257 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3258 }
3259
3260 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3261 handle_fs_inputs(&ctx, shaders[i]);
3262 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3263 handle_vs_inputs(&ctx, shaders[i]);
3264 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3265 prepare_gs_input_vgprs(&ctx);
3266
3267 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3268
3269 if (shader_count >= 2) {
3270 LLVMBuildBr(ctx.ac.builder, merge_block);
3271 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3272 }
3273
3274 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3275 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3276 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3277 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3278 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3279 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3280 }
3281 }
3282
3283 LLVMBuildRetVoid(ctx.ac.builder);
3284
3285 if (options->dump_preoptir)
3286 ac_dump_module(ctx.ac.module);
3287
3288 ac_llvm_finalize_module(&ctx);
3289
3290 if (shader_count == 1)
3291 ac_nir_eliminate_const_vs_outputs(&ctx);
3292
3293 if (options->dump_shader) {
3294 ctx.shader_info->private_mem_vgprs =
3295 ac_count_scratch_private_memory(ctx.main_function);
3296 }
3297
3298 return ctx.ac.module;
3299 }
3300
3301 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3302 {
3303 unsigned *retval = (unsigned *)context;
3304 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3305 char *description = LLVMGetDiagInfoDescription(di);
3306
3307 if (severity == LLVMDSError) {
3308 *retval = 1;
3309 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3310 description);
3311 }
3312
3313 LLVMDisposeMessage(description);
3314 }
3315
3316 static unsigned ac_llvm_compile(LLVMModuleRef M,
3317 struct ac_shader_binary *binary,
3318 LLVMTargetMachineRef tm)
3319 {
3320 unsigned retval = 0;
3321 char *err;
3322 LLVMContextRef llvm_ctx;
3323 LLVMMemoryBufferRef out_buffer;
3324 unsigned buffer_size;
3325 const char *buffer_data;
3326 LLVMBool mem_err;
3327
3328 /* Setup Diagnostic Handler*/
3329 llvm_ctx = LLVMGetModuleContext(M);
3330
3331 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3332 &retval);
3333
3334 /* Compile IR*/
3335 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
3336 &err, &out_buffer);
3337
3338 /* Process Errors/Warnings */
3339 if (mem_err) {
3340 fprintf(stderr, "%s: %s", __FUNCTION__, err);
3341 free(err);
3342 retval = 1;
3343 goto out;
3344 }
3345
3346 /* Extract Shader Code*/
3347 buffer_size = LLVMGetBufferSize(out_buffer);
3348 buffer_data = LLVMGetBufferStart(out_buffer);
3349
3350 ac_elf_read(buffer_data, buffer_size, binary);
3351
3352 /* Clean up */
3353 LLVMDisposeMemoryBuffer(out_buffer);
3354
3355 out:
3356 return retval;
3357 }
3358
3359 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
3360 LLVMModuleRef llvm_module,
3361 struct ac_shader_binary *binary,
3362 struct ac_shader_config *config,
3363 struct radv_shader_variant_info *shader_info,
3364 gl_shader_stage stage,
3365 const struct radv_nir_compiler_options *options)
3366 {
3367 if (options->dump_shader)
3368 ac_dump_module(llvm_module);
3369
3370 memset(binary, 0, sizeof(*binary));
3371
3372 if (options->record_llvm_ir) {
3373 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3374 binary->llvm_ir_string = strdup(llvm_ir);
3375 LLVMDisposeMessage(llvm_ir);
3376 }
3377
3378 int v = ac_llvm_compile(llvm_module, binary, tm);
3379 if (v) {
3380 fprintf(stderr, "compile failed\n");
3381 }
3382
3383 if (options->dump_shader)
3384 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3385
3386 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3387
3388 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3389 LLVMDisposeModule(llvm_module);
3390 LLVMContextDispose(ctx);
3391
3392 if (stage == MESA_SHADER_FRAGMENT) {
3393 shader_info->num_input_vgprs = 0;
3394 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3395 shader_info->num_input_vgprs += 2;
3396 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3397 shader_info->num_input_vgprs += 2;
3398 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3399 shader_info->num_input_vgprs += 2;
3400 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3401 shader_info->num_input_vgprs += 3;
3402 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3403 shader_info->num_input_vgprs += 2;
3404 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3405 shader_info->num_input_vgprs += 2;
3406 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3407 shader_info->num_input_vgprs += 2;
3408 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3409 shader_info->num_input_vgprs += 1;
3410 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3411 shader_info->num_input_vgprs += 1;
3412 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3413 shader_info->num_input_vgprs += 1;
3414 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3415 shader_info->num_input_vgprs += 1;
3416 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3417 shader_info->num_input_vgprs += 1;
3418 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3419 shader_info->num_input_vgprs += 1;
3420 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3421 shader_info->num_input_vgprs += 1;
3422 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3423 shader_info->num_input_vgprs += 1;
3424 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3425 shader_info->num_input_vgprs += 1;
3426 }
3427 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3428
3429 /* +3 for scratch wave offset and VCC */
3430 config->num_sgprs = MAX2(config->num_sgprs,
3431 shader_info->num_input_sgprs + 3);
3432
3433 /* Enable 64-bit and 16-bit denormals, because there is no performance
3434 * cost.
3435 *
3436 * If denormals are enabled, all floating-point output modifiers are
3437 * ignored.
3438 *
3439 * Don't enable denormals for 32-bit floats, because:
3440 * - Floating-point output modifiers would be ignored by the hw.
3441 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3442 * have to stop using those.
3443 * - SI & CI would be very slow.
3444 */
3445 config->float_mode |= V_00B028_FP_64_DENORMS;
3446 }
3447
3448 static void
3449 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3450 {
3451 switch (nir->info.stage) {
3452 case MESA_SHADER_COMPUTE:
3453 for (int i = 0; i < 3; ++i)
3454 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3455 break;
3456 case MESA_SHADER_FRAGMENT:
3457 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3458 break;
3459 case MESA_SHADER_GEOMETRY:
3460 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3461 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3462 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3463 shader_info->gs.invocations = nir->info.gs.invocations;
3464 break;
3465 case MESA_SHADER_TESS_EVAL:
3466 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3467 shader_info->tes.spacing = nir->info.tess.spacing;
3468 shader_info->tes.ccw = nir->info.tess.ccw;
3469 shader_info->tes.point_mode = nir->info.tess.point_mode;
3470 shader_info->tes.as_es = options->key.tes.as_es;
3471 break;
3472 case MESA_SHADER_TESS_CTRL:
3473 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3474 break;
3475 case MESA_SHADER_VERTEX:
3476 shader_info->vs.as_es = options->key.vs.as_es;
3477 shader_info->vs.as_ls = options->key.vs.as_ls;
3478 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3479 if (options->key.vs.as_ls)
3480 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3481 break;
3482 default:
3483 break;
3484 }
3485 }
3486
3487 void
3488 radv_compile_nir_shader(LLVMTargetMachineRef tm,
3489 struct ac_shader_binary *binary,
3490 struct ac_shader_config *config,
3491 struct radv_shader_variant_info *shader_info,
3492 struct nir_shader *const *nir,
3493 int nir_count,
3494 const struct radv_nir_compiler_options *options)
3495 {
3496
3497 LLVMModuleRef llvm_module;
3498
3499 llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
3500 options);
3501
3502 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
3503 nir[0]->info.stage, options);
3504
3505 for (int i = 0; i < nir_count; ++i)
3506 ac_fill_shader_info(shader_info, nir[i], options);
3507
3508 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3509 if (options->chip_class == GFX9) {
3510 if (nir_count == 2 &&
3511 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3512 shader_info->gs.es_type = nir[0]->info.stage;
3513 }
3514 }
3515 }
3516
3517 static void
3518 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3519 {
3520 LLVMValueRef vtx_offset =
3521 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3522 LLVMConstInt(ctx->ac.i32, 4, false), "");
3523 int idx = 0;
3524
3525 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3526 int length = 4;
3527 int slot = idx;
3528 int slot_inc = 1;
3529 if (!(ctx->output_mask & (1ull << i)))
3530 continue;
3531
3532 if (i == VARYING_SLOT_CLIP_DIST0) {
3533 /* unpack clip and cull from a single set of slots */
3534 length = ctx->num_output_clips + ctx->num_output_culls;
3535 if (length > 4)
3536 slot_inc = 2;
3537 }
3538
3539 for (unsigned j = 0; j < length; j++) {
3540 LLVMValueRef value, soffset;
3541
3542 soffset = LLVMConstInt(ctx->ac.i32,
3543 (slot * 4 + j) *
3544 ctx->gs_max_out_vertices * 16 * 4, false);
3545
3546 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3547 1, ctx->ac.i32_0,
3548 vtx_offset, soffset,
3549 0, 1, 1, true, false);
3550
3551 LLVMBuildStore(ctx->ac.builder,
3552 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3553 }
3554 idx += slot_inc;
3555 }
3556 handle_vs_outputs_post(ctx, false, false, &ctx->shader_info->vs.outinfo);
3557 }
3558
3559 void
3560 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
3561 struct nir_shader *geom_shader,
3562 struct ac_shader_binary *binary,
3563 struct ac_shader_config *config,
3564 struct radv_shader_variant_info *shader_info,
3565 const struct radv_nir_compiler_options *options)
3566 {
3567 struct radv_shader_context ctx = {0};
3568 ctx.context = LLVMContextCreate();
3569 ctx.options = options;
3570 ctx.shader_info = shader_info;
3571
3572 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3573 options->family);
3574 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3575
3576 ctx.is_gs_copy_shader = true;
3577 LLVMSetTarget(ctx.ac.module, "amdgcn--");
3578
3579 enum ac_float_mode float_mode =
3580 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3581 AC_FLOAT_MODE_DEFAULT;
3582
3583 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3584 ctx.stage = MESA_SHADER_VERTEX;
3585
3586 radv_nir_shader_info_pass(geom_shader, options, &shader_info->info);
3587
3588 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3589
3590 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3591 ac_setup_rings(&ctx);
3592
3593 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3594 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3595
3596 nir_foreach_variable(variable, &geom_shader->outputs) {
3597 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3598 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3599 variable, MESA_SHADER_VERTEX);
3600 }
3601
3602 ac_gs_copy_shader_emit(&ctx);
3603
3604 LLVMBuildRetVoid(ctx.ac.builder);
3605
3606 ac_llvm_finalize_module(&ctx);
3607
3608 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
3609 MESA_SHADER_VERTEX, options);
3610 }