2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_llvm_build.h"
42 #include "ac_shader_abi.h"
43 #include "ac_shader_util.h"
44 #include "ac_exp_param.h"
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 struct radv_shader_context
{
49 struct ac_llvm_context ac
;
50 const struct radv_nir_compiler_options
*options
;
51 struct radv_shader_variant_info
*shader_info
;
52 struct ac_shader_abi abi
;
54 unsigned max_workgroup_size
;
55 LLVMContextRef context
;
56 LLVMValueRef main_function
;
58 LLVMValueRef descriptor_sets
[RADV_UD_MAX_SETS
];
59 LLVMValueRef ring_offsets
;
61 LLVMValueRef vertex_buffers
;
62 LLVMValueRef rel_auto_id
;
63 LLVMValueRef vs_prim_id
;
64 LLVMValueRef es2gs_offset
;
67 LLVMValueRef merged_wave_info
;
68 LLVMValueRef tess_factor_offset
;
69 LLVMValueRef tes_rel_patch_id
;
75 * - bits 0..10: ordered_wave_id
76 * - bits 12..20: number of vertices in group
77 * - bits 22..30: number of primitives in group
79 LLVMValueRef gs_tg_info
;
80 LLVMValueRef gs2vs_offset
;
81 LLVMValueRef gs_wave_id
;
82 LLVMValueRef gs_vtx_offset
[6];
84 LLVMValueRef esgs_ring
;
85 LLVMValueRef gsvs_ring
[4];
86 LLVMValueRef hs_ring_tess_offchip
;
87 LLVMValueRef hs_ring_tess_factor
;
89 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
90 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
93 LLVMValueRef streamout_buffers
;
94 LLVMValueRef streamout_write_idx
;
95 LLVMValueRef streamout_config
;
96 LLVMValueRef streamout_offset
[4];
98 gl_shader_stage stage
;
100 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
101 uint64_t float16_shaded_mask
;
104 uint64_t output_mask
;
106 bool is_gs_copy_shader
;
107 LLVMValueRef gs_next_vertex
[4];
108 unsigned gs_max_out_vertices
;
110 unsigned tes_primitive_mode
;
112 uint32_t tcs_patch_outputs_read
;
113 uint64_t tcs_outputs_read
;
114 uint32_t tcs_vertices_per_patch
;
115 uint32_t tcs_num_inputs
;
116 uint32_t tcs_num_patches
;
117 uint32_t max_gsvs_emit_size
;
118 uint32_t gsvs_vertex_size
;
121 enum radeon_llvm_calling_convention
{
122 RADEON_LLVM_AMDGPU_VS
= 87,
123 RADEON_LLVM_AMDGPU_GS
= 88,
124 RADEON_LLVM_AMDGPU_PS
= 89,
125 RADEON_LLVM_AMDGPU_CS
= 90,
126 RADEON_LLVM_AMDGPU_HS
= 93,
129 static inline struct radv_shader_context
*
130 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
132 struct radv_shader_context
*ctx
= NULL
;
133 return container_of(abi
, ctx
, abi
);
136 struct ac_build_if_state
138 struct radv_shader_context
*ctx
;
139 LLVMValueRef condition
;
140 LLVMBasicBlockRef entry_block
;
141 LLVMBasicBlockRef true_block
;
142 LLVMBasicBlockRef false_block
;
143 LLVMBasicBlockRef merge_block
;
146 static LLVMBasicBlockRef
147 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
149 LLVMBasicBlockRef current_block
;
150 LLVMBasicBlockRef next_block
;
151 LLVMBasicBlockRef new_block
;
153 /* get current basic block */
154 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
156 /* chqeck if there's another block after this one */
157 next_block
= LLVMGetNextBasicBlock(current_block
);
159 /* insert the new block before the next block */
160 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
163 /* append new block after current block */
164 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
165 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
171 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
172 struct radv_shader_context
*ctx
,
173 LLVMValueRef condition
)
175 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
177 memset(ifthen
, 0, sizeof *ifthen
);
179 ifthen
->condition
= condition
;
180 ifthen
->entry_block
= block
;
182 /* create endif/merge basic block for the phi functions */
183 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
185 /* create/insert true_block before merge_block */
187 LLVMInsertBasicBlockInContext(ctx
->context
,
191 /* successive code goes into the true block */
192 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
199 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
201 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
203 /* Insert branch to the merge block from current block */
204 LLVMBuildBr(builder
, ifthen
->merge_block
);
207 * Now patch in the various branch instructions.
210 /* Insert the conditional branch instruction at the end of entry_block */
211 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
212 if (ifthen
->false_block
) {
213 /* we have an else clause */
214 LLVMBuildCondBr(builder
, ifthen
->condition
,
215 ifthen
->true_block
, ifthen
->false_block
);
219 LLVMBuildCondBr(builder
, ifthen
->condition
,
220 ifthen
->true_block
, ifthen
->merge_block
);
223 /* Resume building code at end of the ifthen->merge_block */
224 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
228 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
230 switch (ctx
->stage
) {
231 case MESA_SHADER_TESS_CTRL
:
232 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
233 case MESA_SHADER_TESS_EVAL
:
234 return ctx
->tes_rel_patch_id
;
237 unreachable("Illegal stage");
242 get_tcs_num_patches(struct radv_shader_context
*ctx
)
244 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
245 unsigned num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
246 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
247 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
248 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
249 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
250 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
251 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
252 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
253 unsigned num_patches
;
254 unsigned hardware_lds_size
;
256 /* Ensure that we only need one wave per SIMD so we don't need to check
257 * resource usage. Also ensures that the number of tcs in and out
258 * vertices per threadgroup are at most 256.
260 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
261 /* Make sure that the data fits in LDS. This assumes the shaders only
262 * use LDS for the inputs and outputs.
264 hardware_lds_size
= 32768;
266 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
267 * threadgroup, even though there is more than 32 KiB LDS.
269 * Test: dEQP-VK.tessellation.shader_input_output.barrier
271 if (ctx
->options
->chip_class
>= GFX7
&& ctx
->options
->family
!= CHIP_STONEY
)
272 hardware_lds_size
= 65536;
274 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
275 /* Make sure the output data fits in the offchip buffer */
276 num_patches
= MIN2(num_patches
, (ctx
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
277 /* Not necessary for correctness, but improves performance. The
278 * specific value is taken from the proprietary driver.
280 num_patches
= MIN2(num_patches
, 40);
282 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
283 if (ctx
->options
->chip_class
== GFX6
) {
284 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
285 num_patches
= MIN2(num_patches
, one_wave
);
291 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
293 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
294 unsigned num_tcs_output_cp
;
295 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
296 unsigned input_vertex_size
, output_vertex_size
;
297 unsigned input_patch_size
, output_patch_size
;
298 unsigned pervertex_output_patch_size
;
299 unsigned output_patch0_offset
;
300 unsigned num_patches
;
303 num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
304 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
305 num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
307 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
308 output_vertex_size
= num_tcs_outputs
* 16;
310 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
312 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
313 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
315 num_patches
= ctx
->tcs_num_patches
;
316 output_patch0_offset
= input_patch_size
* num_patches
;
318 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
322 /* Tessellation shaders pass outputs to the next shader using LDS.
324 * LS outputs = TCS inputs
325 * TCS outputs = TES inputs
328 * - TCS inputs for patch 0
329 * - TCS inputs for patch 1
330 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
332 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
333 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
334 * - TCS outputs for patch 1
335 * - Per-patch TCS outputs for patch 1
336 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
337 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
340 * All three shaders VS(LS), TCS, TES share the same LDS space.
343 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
345 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
346 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
347 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
349 input_patch_size
/= 4;
350 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
354 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
356 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
357 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
358 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
359 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
360 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
361 output_patch_size
/= 4;
362 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
366 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
368 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
369 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
370 output_vertex_size
/= 4;
371 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
375 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
377 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
378 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
379 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
380 uint32_t output_patch0_offset
= input_patch_size
;
381 unsigned num_patches
= ctx
->tcs_num_patches
;
383 output_patch0_offset
*= num_patches
;
384 output_patch0_offset
/= 4;
385 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
389 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
391 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
392 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
393 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
394 uint32_t output_patch0_offset
= input_patch_size
;
396 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
397 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
398 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
399 unsigned num_patches
= ctx
->tcs_num_patches
;
401 output_patch0_offset
*= num_patches
;
402 output_patch0_offset
+= pervertex_output_patch_size
;
403 output_patch0_offset
/= 4;
404 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
408 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
410 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
411 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
413 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
417 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
419 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
420 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
421 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
423 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
428 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
430 LLVMValueRef patch0_patch_data_offset
=
431 get_tcs_out_patch0_patch_data_offset(ctx
);
432 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
433 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
435 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
436 patch0_patch_data_offset
);
441 LLVMTypeRef types
[MAX_ARGS
];
442 LLVMValueRef
*assign
[MAX_ARGS
];
445 uint8_t num_sgprs_used
;
446 uint8_t num_vgprs_used
;
449 enum ac_arg_regfile
{
455 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
456 LLVMValueRef
*param_ptr
)
458 assert(info
->count
< MAX_ARGS
);
460 info
->assign
[info
->count
] = param_ptr
;
461 info
->types
[info
->count
] = type
;
464 if (regfile
== ARG_SGPR
) {
465 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
468 assert(regfile
== ARG_VGPR
);
469 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
473 static void assign_arguments(LLVMValueRef main_function
,
474 struct arg_info
*info
)
477 for (i
= 0; i
< info
->count
; i
++) {
479 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
484 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
485 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
486 unsigned num_return_elems
,
487 struct arg_info
*args
,
488 unsigned max_workgroup_size
,
489 const struct radv_nir_compiler_options
*options
)
491 LLVMTypeRef main_function_type
, ret_type
;
492 LLVMBasicBlockRef main_function_body
;
494 if (num_return_elems
)
495 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
496 num_return_elems
, true);
498 ret_type
= LLVMVoidTypeInContext(ctx
);
500 /* Setup the function */
502 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
503 LLVMValueRef main_function
=
504 LLVMAddFunction(module
, "main", main_function_type
);
506 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
507 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
509 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
510 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
511 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
513 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
515 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
516 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
517 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
521 if (options
->address32_hi
) {
522 ac_llvm_add_target_dep_function_attr(main_function
,
523 "amdgpu-32bit-address-high-bits",
524 options
->address32_hi
);
527 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
529 if (options
->unsafe_math
) {
530 /* These were copied from some LLVM test. */
531 LLVMAddTargetDependentFunctionAttr(main_function
,
532 "less-precise-fpmad",
534 LLVMAddTargetDependentFunctionAttr(main_function
,
537 LLVMAddTargetDependentFunctionAttr(main_function
,
540 LLVMAddTargetDependentFunctionAttr(main_function
,
543 LLVMAddTargetDependentFunctionAttr(main_function
,
544 "no-signed-zeros-fp-math",
547 return main_function
;
552 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
,
555 ud_info
->sgpr_idx
= *sgpr_idx
;
556 ud_info
->num_sgprs
= num_sgprs
;
557 *sgpr_idx
+= num_sgprs
;
561 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
564 struct radv_userdata_info
*ud_info
=
565 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
568 set_loc(ud_info
, sgpr_idx
, num_sgprs
);
572 set_loc_shader_ptr(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
574 bool use_32bit_pointers
= idx
!= AC_UD_SCRATCH_RING_OFFSETS
;
576 set_loc_shader(ctx
, idx
, sgpr_idx
, use_32bit_pointers
? 1 : 2);
580 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
582 struct radv_userdata_locations
*locs
=
583 &ctx
->shader_info
->user_sgprs_locs
;
584 struct radv_userdata_info
*ud_info
= &locs
->descriptor_sets
[idx
];
587 set_loc(ud_info
, sgpr_idx
, 1);
589 locs
->descriptor_sets_enabled
|= 1 << idx
;
592 struct user_sgpr_info
{
593 bool need_ring_offsets
;
594 bool indirect_all_descriptor_sets
;
595 uint8_t remaining_sgprs
;
598 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
599 gl_shader_stage stage
)
602 case MESA_SHADER_VERTEX
:
603 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
604 (!ctx
->options
->key
.vs
.out
.as_es
&& !ctx
->options
->key
.vs
.out
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
607 case MESA_SHADER_TESS_EVAL
:
608 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.out
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
611 case MESA_SHADER_GEOMETRY
:
612 case MESA_SHADER_TESS_CTRL
:
613 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
623 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
627 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
629 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
634 static void allocate_inline_push_consts(struct radv_shader_context
*ctx
,
635 struct user_sgpr_info
*user_sgpr_info
)
637 uint8_t remaining_sgprs
= user_sgpr_info
->remaining_sgprs
;
639 /* Only supported if shaders use push constants. */
640 if (ctx
->shader_info
->info
.min_push_constant_used
== UINT8_MAX
)
643 /* Only supported if shaders don't have indirect push constants. */
644 if (ctx
->shader_info
->info
.has_indirect_push_constants
)
647 /* Only supported for 32-bit push constants. */
648 if (!ctx
->shader_info
->info
.has_only_32bit_push_constants
)
651 uint8_t num_push_consts
=
652 (ctx
->shader_info
->info
.max_push_constant_used
-
653 ctx
->shader_info
->info
.min_push_constant_used
) / 4;
655 /* Check if the number of user SGPRs is large enough. */
656 if (num_push_consts
< remaining_sgprs
) {
657 ctx
->shader_info
->info
.num_inline_push_consts
= num_push_consts
;
659 ctx
->shader_info
->info
.num_inline_push_consts
= remaining_sgprs
;
662 /* Clamp to the maximum number of allowed inlined push constants. */
663 if (ctx
->shader_info
->info
.num_inline_push_consts
> AC_MAX_INLINE_PUSH_CONSTS
)
664 ctx
->shader_info
->info
.num_inline_push_consts
= AC_MAX_INLINE_PUSH_CONSTS
;
666 if (ctx
->shader_info
->info
.num_inline_push_consts
== num_push_consts
&&
667 !ctx
->shader_info
->info
.loads_dynamic_offsets
) {
668 /* Disable the default push constants path if all constants are
669 * inlined and if shaders don't use dynamic descriptors.
671 ctx
->shader_info
->info
.loads_push_constants
= false;
674 ctx
->shader_info
->info
.base_inline_push_consts
=
675 ctx
->shader_info
->info
.min_push_constant_used
/ 4;
678 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
679 gl_shader_stage stage
,
680 bool has_previous_stage
,
681 gl_shader_stage previous_stage
,
682 bool needs_view_index
,
683 struct user_sgpr_info
*user_sgpr_info
)
685 uint8_t user_sgpr_count
= 0;
687 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
689 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
690 if (stage
== MESA_SHADER_GEOMETRY
||
691 stage
== MESA_SHADER_VERTEX
||
692 stage
== MESA_SHADER_TESS_CTRL
||
693 stage
== MESA_SHADER_TESS_EVAL
||
694 ctx
->is_gs_copy_shader
)
695 user_sgpr_info
->need_ring_offsets
= true;
697 if (stage
== MESA_SHADER_FRAGMENT
&&
698 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
699 user_sgpr_info
->need_ring_offsets
= true;
701 /* 2 user sgprs will nearly always be allocated for scratch/rings */
702 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
703 user_sgpr_count
+= 2;
707 case MESA_SHADER_COMPUTE
:
708 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
709 user_sgpr_count
+= 3;
711 case MESA_SHADER_FRAGMENT
:
712 user_sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
714 case MESA_SHADER_VERTEX
:
715 if (!ctx
->is_gs_copy_shader
)
716 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
718 case MESA_SHADER_TESS_CTRL
:
719 if (has_previous_stage
) {
720 if (previous_stage
== MESA_SHADER_VERTEX
)
721 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
724 case MESA_SHADER_TESS_EVAL
:
726 case MESA_SHADER_GEOMETRY
:
727 if (has_previous_stage
) {
728 if (previous_stage
== MESA_SHADER_VERTEX
) {
729 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
737 if (needs_view_index
)
740 if (ctx
->shader_info
->info
.loads_push_constants
)
743 if (ctx
->streamout_buffers
)
746 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
&& stage
!= MESA_SHADER_COMPUTE
? 32 : 16;
747 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_count
;
748 uint32_t num_desc_set
=
749 util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
);
751 if (remaining_sgprs
< num_desc_set
) {
752 user_sgpr_info
->indirect_all_descriptor_sets
= true;
753 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- 1;
755 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- num_desc_set
;
758 allocate_inline_push_consts(ctx
, user_sgpr_info
);
762 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
763 const struct user_sgpr_info
*user_sgpr_info
,
764 struct arg_info
*args
,
765 LLVMValueRef
*desc_sets
)
767 LLVMTypeRef type
= ac_array_in_const32_addr_space(ctx
->ac
.i8
);
769 /* 1 for each descriptor set */
770 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
771 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
774 int i
= u_bit_scan(&mask
);
776 add_arg(args
, ARG_SGPR
, type
, &ctx
->descriptor_sets
[i
]);
779 add_arg(args
, ARG_SGPR
, ac_array_in_const32_addr_space(type
),
783 if (ctx
->shader_info
->info
.loads_push_constants
) {
784 /* 1 for push constants and dynamic descriptors */
785 add_arg(args
, ARG_SGPR
, type
, &ctx
->abi
.push_constants
);
788 for (unsigned i
= 0; i
< ctx
->shader_info
->info
.num_inline_push_consts
; i
++) {
789 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
,
790 &ctx
->abi
.inline_push_consts
[i
]);
792 ctx
->abi
.num_inline_push_consts
= ctx
->shader_info
->info
.num_inline_push_consts
;
793 ctx
->abi
.base_inline_push_consts
= ctx
->shader_info
->info
.base_inline_push_consts
;
795 if (ctx
->shader_info
->info
.so
.num_outputs
) {
796 add_arg(args
, ARG_SGPR
,
797 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
798 &ctx
->streamout_buffers
);
803 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
804 gl_shader_stage stage
,
805 bool has_previous_stage
,
806 gl_shader_stage previous_stage
,
807 struct arg_info
*args
)
809 if (!ctx
->is_gs_copy_shader
&&
810 (stage
== MESA_SHADER_VERTEX
||
811 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
812 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
813 add_arg(args
, ARG_SGPR
,
814 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
815 &ctx
->vertex_buffers
);
817 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
818 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
819 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
820 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
826 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
828 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
829 if (!ctx
->is_gs_copy_shader
) {
830 if (ctx
->options
->key
.vs
.out
.as_ls
) {
831 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
832 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
833 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
835 if (ctx
->ac
.chip_class
>= GFX10
) {
836 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
837 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
838 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
840 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
841 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
842 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
849 declare_streamout_sgprs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
850 struct arg_info
*args
)
854 if (ctx
->ac
.chip_class
>= GFX10
)
857 /* Streamout SGPRs. */
858 if (ctx
->shader_info
->info
.so
.num_outputs
) {
859 assert(stage
== MESA_SHADER_VERTEX
||
860 stage
== MESA_SHADER_TESS_EVAL
);
862 if (stage
!= MESA_SHADER_TESS_EVAL
) {
863 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_config
);
865 args
->assign
[args
->count
- 1] = &ctx
->streamout_config
;
866 args
->types
[args
->count
- 1] = ctx
->ac
.i32
;
869 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_write_idx
);
872 /* A streamout buffer offset is loaded if the stride is non-zero. */
873 for (i
= 0; i
< 4; i
++) {
874 if (!ctx
->shader_info
->info
.so
.strides
[i
])
877 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_offset
[i
]);
882 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
884 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
885 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
886 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
887 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
891 set_global_input_locs(struct radv_shader_context
*ctx
,
892 const struct user_sgpr_info
*user_sgpr_info
,
893 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
895 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
897 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
899 int i
= u_bit_scan(&mask
);
901 set_loc_desc(ctx
, i
, user_sgpr_idx
);
904 set_loc_shader_ptr(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
908 int i
= u_bit_scan(&mask
);
910 ctx
->descriptor_sets
[i
] =
911 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
912 LLVMConstInt(ctx
->ac
.i32
, i
, false));
916 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
919 if (ctx
->shader_info
->info
.loads_push_constants
) {
920 set_loc_shader_ptr(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
);
923 if (ctx
->shader_info
->info
.num_inline_push_consts
) {
924 set_loc_shader(ctx
, AC_UD_INLINE_PUSH_CONSTANTS
, user_sgpr_idx
,
925 ctx
->shader_info
->info
.num_inline_push_consts
);
928 if (ctx
->streamout_buffers
) {
929 set_loc_shader_ptr(ctx
, AC_UD_STREAMOUT_BUFFERS
,
935 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
936 gl_shader_stage stage
, bool has_previous_stage
,
937 gl_shader_stage previous_stage
,
938 uint8_t *user_sgpr_idx
)
940 if (!ctx
->is_gs_copy_shader
&&
941 (stage
== MESA_SHADER_VERTEX
||
942 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
943 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
944 set_loc_shader_ptr(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
949 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
952 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
953 user_sgpr_idx
, vs_num
);
957 static void set_llvm_calling_convention(LLVMValueRef func
,
958 gl_shader_stage stage
)
960 enum radeon_llvm_calling_convention calling_conv
;
963 case MESA_SHADER_VERTEX
:
964 case MESA_SHADER_TESS_EVAL
:
965 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
967 case MESA_SHADER_GEOMETRY
:
968 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
970 case MESA_SHADER_TESS_CTRL
:
971 calling_conv
= RADEON_LLVM_AMDGPU_HS
;
973 case MESA_SHADER_FRAGMENT
:
974 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
976 case MESA_SHADER_COMPUTE
:
977 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
980 unreachable("Unhandle shader type");
983 LLVMSetFunctionCallConv(func
, calling_conv
);
986 /* Returns whether the stage is a stage that can be directly before the GS */
987 static bool is_pre_gs_stage(gl_shader_stage stage
)
989 return stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
;
992 static void create_function(struct radv_shader_context
*ctx
,
993 gl_shader_stage stage
,
994 bool has_previous_stage
,
995 gl_shader_stage previous_stage
)
997 uint8_t user_sgpr_idx
;
998 struct user_sgpr_info user_sgpr_info
;
999 struct arg_info args
= {};
1000 LLVMValueRef desc_sets
;
1001 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
1002 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
1003 previous_stage
, needs_view_index
, &user_sgpr_info
);
1005 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
1006 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
1007 &ctx
->ring_offsets
);
1010 if (ctx
->ac
.chip_class
>= GFX10
) {
1011 if (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.out
.as_ngg
) {
1012 /* On GFX10, VS is merged into GS for NGG. */
1013 stage
= MESA_SHADER_GEOMETRY
;
1014 has_previous_stage
= true;
1015 previous_stage
= MESA_SHADER_VERTEX
;
1020 case MESA_SHADER_COMPUTE
:
1021 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1024 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1025 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
1026 &ctx
->abi
.num_work_groups
);
1029 for (int i
= 0; i
< 3; i
++) {
1030 ctx
->abi
.workgroup_ids
[i
] = NULL
;
1031 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
1032 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1033 &ctx
->abi
.workgroup_ids
[i
]);
1037 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
1038 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
1039 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
1040 &ctx
->abi
.local_invocation_ids
);
1042 case MESA_SHADER_VERTEX
:
1043 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1046 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
1047 previous_stage
, &args
);
1049 if (needs_view_index
)
1050 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1051 &ctx
->abi
.view_index
);
1052 if (ctx
->options
->key
.vs
.out
.as_es
) {
1053 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1054 &ctx
->es2gs_offset
);
1055 } else if (ctx
->options
->key
.vs
.out
.as_ls
) {
1056 /* no extra parameters */
1058 declare_streamout_sgprs(ctx
, stage
, &args
);
1061 declare_vs_input_vgprs(ctx
, &args
);
1063 case MESA_SHADER_TESS_CTRL
:
1064 if (has_previous_stage
) {
1065 // First 6 system regs
1066 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1067 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1068 &ctx
->merged_wave_info
);
1069 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1070 &ctx
->tess_factor_offset
);
1072 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1073 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1074 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1076 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1079 declare_vs_specific_input_sgprs(ctx
, stage
,
1081 previous_stage
, &args
);
1083 if (needs_view_index
)
1084 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1085 &ctx
->abi
.view_index
);
1087 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1088 &ctx
->abi
.tcs_patch_id
);
1089 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1090 &ctx
->abi
.tcs_rel_ids
);
1092 declare_vs_input_vgprs(ctx
, &args
);
1094 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1097 if (needs_view_index
)
1098 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1099 &ctx
->abi
.view_index
);
1101 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1102 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1103 &ctx
->tess_factor_offset
);
1104 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1105 &ctx
->abi
.tcs_patch_id
);
1106 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1107 &ctx
->abi
.tcs_rel_ids
);
1110 case MESA_SHADER_TESS_EVAL
:
1111 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1114 if (needs_view_index
)
1115 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1116 &ctx
->abi
.view_index
);
1118 if (ctx
->options
->key
.tes
.out
.as_es
) {
1119 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1120 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1121 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1122 &ctx
->es2gs_offset
);
1124 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1125 declare_streamout_sgprs(ctx
, stage
, &args
);
1126 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1128 declare_tes_input_vgprs(ctx
, &args
);
1130 case MESA_SHADER_GEOMETRY
:
1131 if (has_previous_stage
) {
1132 // First 6 system regs
1133 if (ctx
->options
->key
.vs
.out
.as_ngg
) {
1134 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1137 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1138 &ctx
->gs2vs_offset
);
1141 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1142 &ctx
->merged_wave_info
);
1143 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1145 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1146 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1147 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1149 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1152 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
1153 declare_vs_specific_input_sgprs(ctx
, stage
,
1159 if (needs_view_index
)
1160 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1161 &ctx
->abi
.view_index
);
1163 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1164 &ctx
->gs_vtx_offset
[0]);
1165 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1166 &ctx
->gs_vtx_offset
[2]);
1167 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1168 &ctx
->abi
.gs_prim_id
);
1169 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1170 &ctx
->abi
.gs_invocation_id
);
1171 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1172 &ctx
->gs_vtx_offset
[4]);
1174 if (previous_stage
== MESA_SHADER_VERTEX
) {
1175 declare_vs_input_vgprs(ctx
, &args
);
1177 declare_tes_input_vgprs(ctx
, &args
);
1180 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1183 if (needs_view_index
)
1184 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1185 &ctx
->abi
.view_index
);
1187 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1188 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1189 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1190 &ctx
->gs_vtx_offset
[0]);
1191 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1192 &ctx
->gs_vtx_offset
[1]);
1193 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1194 &ctx
->abi
.gs_prim_id
);
1195 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1196 &ctx
->gs_vtx_offset
[2]);
1197 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1198 &ctx
->gs_vtx_offset
[3]);
1199 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1200 &ctx
->gs_vtx_offset
[4]);
1201 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1202 &ctx
->gs_vtx_offset
[5]);
1203 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1204 &ctx
->abi
.gs_invocation_id
);
1207 case MESA_SHADER_FRAGMENT
:
1208 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1211 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1212 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1213 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1214 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1215 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1216 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1217 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1218 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1219 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1220 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1221 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1222 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1223 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1224 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1225 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1226 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1227 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1230 unreachable("Shader stage not implemented");
1233 ctx
->main_function
= create_llvm_function(
1234 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1235 ctx
->max_workgroup_size
, ctx
->options
);
1236 set_llvm_calling_convention(ctx
->main_function
, stage
);
1239 ctx
->shader_info
->num_input_vgprs
= 0;
1240 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1242 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1244 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1245 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1247 assign_arguments(ctx
->main_function
, &args
);
1251 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1252 set_loc_shader_ptr(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1254 if (ctx
->options
->supports_spill
) {
1255 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1256 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
1257 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1258 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1259 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1263 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1264 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1265 if (has_previous_stage
)
1268 set_global_input_locs(ctx
, &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1271 case MESA_SHADER_COMPUTE
:
1272 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1273 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1277 case MESA_SHADER_VERTEX
:
1278 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1279 previous_stage
, &user_sgpr_idx
);
1280 if (ctx
->abi
.view_index
)
1281 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1283 case MESA_SHADER_TESS_CTRL
:
1284 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1285 previous_stage
, &user_sgpr_idx
);
1286 if (ctx
->abi
.view_index
)
1287 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1289 case MESA_SHADER_TESS_EVAL
:
1290 if (ctx
->abi
.view_index
)
1291 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1293 case MESA_SHADER_GEOMETRY
:
1294 if (has_previous_stage
) {
1295 if (previous_stage
== MESA_SHADER_VERTEX
)
1296 set_vs_specific_input_locs(ctx
, stage
,
1301 if (ctx
->abi
.view_index
)
1302 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1304 case MESA_SHADER_FRAGMENT
:
1307 unreachable("Shader stage not implemented");
1310 if (stage
== MESA_SHADER_TESS_CTRL
||
1311 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.out
.as_ls
) ||
1312 /* GFX9 has the ESGS ring buffer in LDS. */
1313 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1314 ac_declare_lds_as_pointer(&ctx
->ac
);
1317 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1322 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1323 unsigned desc_set
, unsigned binding
)
1325 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1326 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1327 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
1328 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1329 unsigned base_offset
= layout
->binding
[binding
].offset
;
1330 LLVMValueRef offset
, stride
;
1332 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1333 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1334 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1335 layout
->binding
[binding
].dynamic_offset_offset
;
1336 desc_ptr
= ctx
->abi
.push_constants
;
1337 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1338 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1340 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1342 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
1344 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1345 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
1348 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
1349 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1350 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1352 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1353 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1354 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1355 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1356 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1357 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1358 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1360 LLVMValueRef desc_components
[4] = {
1361 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
1362 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
), false),
1363 /* High limit to support variable sizes. */
1364 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
1365 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
1368 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
1375 /* The offchip buffer layout for TCS->TES is
1377 * - attribute 0 of patch 0 vertex 0
1378 * - attribute 0 of patch 0 vertex 1
1379 * - attribute 0 of patch 0 vertex 2
1381 * - attribute 0 of patch 1 vertex 0
1382 * - attribute 0 of patch 1 vertex 1
1384 * - attribute 1 of patch 0 vertex 0
1385 * - attribute 1 of patch 0 vertex 1
1387 * - per patch attribute 0 of patch 0
1388 * - per patch attribute 0 of patch 1
1391 * Note that every attribute has 4 components.
1393 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1395 uint32_t num_patches
= ctx
->tcs_num_patches
;
1396 uint32_t num_tcs_outputs
;
1397 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1398 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
1400 num_tcs_outputs
= ctx
->options
->key
.tes
.tcs_num_outputs
;
1402 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1403 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
1405 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1408 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1409 LLVMValueRef vertex_index
)
1411 LLVMValueRef param_stride
;
1413 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
* ctx
->tcs_num_patches
, false);
1415 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1416 return param_stride
;
1419 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1420 LLVMValueRef vertex_index
,
1421 LLVMValueRef param_index
)
1423 LLVMValueRef base_addr
;
1424 LLVMValueRef param_stride
, constant16
;
1425 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1426 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
1427 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1428 param_stride
= calc_param_stride(ctx
, vertex_index
);
1430 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
1431 vertices_per_patch
, vertex_index
);
1433 base_addr
= rel_patch_id
;
1436 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1437 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1438 param_stride
, ""), "");
1440 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1442 if (!vertex_index
) {
1443 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1445 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1446 patch_data_offset
, "");
1451 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1453 unsigned const_index
,
1455 LLVMValueRef vertex_index
,
1456 LLVMValueRef indir_index
)
1458 LLVMValueRef param_index
;
1461 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1464 if (const_index
&& !is_compact
)
1465 param
+= const_index
;
1466 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1468 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1472 get_dw_address(struct radv_shader_context
*ctx
,
1473 LLVMValueRef dw_addr
,
1475 unsigned const_index
,
1476 bool compact_const_index
,
1477 LLVMValueRef vertex_index
,
1478 LLVMValueRef stride
,
1479 LLVMValueRef indir_index
)
1484 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1485 LLVMBuildMul(ctx
->ac
.builder
,
1491 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1492 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1493 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1494 else if (const_index
&& !compact_const_index
)
1495 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1496 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1498 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1499 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1501 if (const_index
&& compact_const_index
)
1502 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1503 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1508 load_tcs_varyings(struct ac_shader_abi
*abi
,
1510 LLVMValueRef vertex_index
,
1511 LLVMValueRef indir_index
,
1512 unsigned const_index
,
1514 unsigned driver_location
,
1516 unsigned num_components
,
1521 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1522 LLVMValueRef dw_addr
, stride
;
1523 LLVMValueRef value
[4], result
;
1524 unsigned param
= shader_io_get_unique_index(location
);
1527 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1528 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1529 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1532 stride
= get_tcs_out_vertex_stride(ctx
);
1533 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1535 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1540 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1543 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1544 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1545 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1548 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1553 store_tcs_output(struct ac_shader_abi
*abi
,
1554 const nir_variable
*var
,
1555 LLVMValueRef vertex_index
,
1556 LLVMValueRef param_index
,
1557 unsigned const_index
,
1561 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1562 const unsigned location
= var
->data
.location
;
1563 unsigned component
= var
->data
.location_frac
;
1564 const bool is_patch
= var
->data
.patch
;
1565 const bool is_compact
= var
->data
.compact
;
1566 LLVMValueRef dw_addr
;
1567 LLVMValueRef stride
= NULL
;
1568 LLVMValueRef buf_addr
= NULL
;
1570 bool store_lds
= true;
1573 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1576 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
1580 param
= shader_io_get_unique_index(location
);
1581 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1582 const_index
+= component
;
1585 if (const_index
>= 4) {
1592 stride
= get_tcs_out_vertex_stride(ctx
);
1593 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1595 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1598 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1600 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1601 vertex_index
, param_index
);
1603 bool is_tess_factor
= false;
1604 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1605 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1606 is_tess_factor
= true;
1608 unsigned base
= is_compact
? const_index
: 0;
1609 for (unsigned chan
= 0; chan
< 8; chan
++) {
1610 if (!(writemask
& (1 << chan
)))
1612 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1613 value
= ac_to_integer(&ctx
->ac
, value
);
1614 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
1616 if (store_lds
|| is_tess_factor
) {
1617 LLVMValueRef dw_addr_chan
=
1618 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1619 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1620 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1623 if (!is_tess_factor
&& writemask
!= 0xF)
1624 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1625 buf_addr
, ctx
->oc_lds
,
1626 4 * (base
+ chan
), ac_glc
, false);
1629 if (writemask
== 0xF) {
1630 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1631 buf_addr
, ctx
->oc_lds
,
1632 (base
* 4), ac_glc
, false);
1637 load_tes_input(struct ac_shader_abi
*abi
,
1639 LLVMValueRef vertex_index
,
1640 LLVMValueRef param_index
,
1641 unsigned const_index
,
1643 unsigned driver_location
,
1645 unsigned num_components
,
1650 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1651 LLVMValueRef buf_addr
;
1652 LLVMValueRef result
;
1653 unsigned param
= shader_io_get_unique_index(location
);
1655 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1656 const_index
+= component
;
1658 if (const_index
>= 4) {
1664 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1665 is_compact
, vertex_index
, param_index
);
1667 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1668 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1670 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1671 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
1672 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1677 load_gs_input(struct ac_shader_abi
*abi
,
1679 unsigned driver_location
,
1681 unsigned num_components
,
1682 unsigned vertex_index
,
1683 unsigned const_index
,
1686 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1687 LLVMValueRef vtx_offset
;
1688 unsigned param
, vtx_offset_param
;
1689 LLVMValueRef value
[4], result
;
1691 vtx_offset_param
= vertex_index
;
1692 assert(vtx_offset_param
< 6);
1693 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1694 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1696 param
= shader_io_get_unique_index(location
);
1698 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1699 if (ctx
->ac
.chip_class
>= GFX9
) {
1700 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1701 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1702 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1703 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1705 LLVMValueRef soffset
=
1706 LLVMConstInt(ctx
->ac
.i32
,
1707 (param
* 4 + i
+ const_index
) * 256,
1710 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1713 vtx_offset
, soffset
,
1714 0, ac_glc
, true, false);
1717 if (ac_get_type_size(type
) == 2) {
1718 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
1719 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
1721 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
1723 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1724 result
= ac_to_integer(&ctx
->ac
, result
);
1729 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1731 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1732 ac_build_kill_if_false(&ctx
->ac
, visible
);
1735 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
1736 enum glsl_interp_mode interp
, unsigned location
)
1738 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1741 case INTERP_MODE_FLAT
:
1744 case INTERP_MODE_SMOOTH
:
1745 case INTERP_MODE_NONE
:
1746 if (location
== INTERP_CENTER
)
1747 return ctx
->persp_center
;
1748 else if (location
== INTERP_CENTROID
)
1749 return ctx
->persp_centroid
;
1750 else if (location
== INTERP_SAMPLE
)
1751 return ctx
->persp_sample
;
1753 case INTERP_MODE_NOPERSPECTIVE
:
1754 if (location
== INTERP_CENTER
)
1755 return ctx
->linear_center
;
1756 else if (location
== INTERP_CENTROID
)
1757 return ctx
->linear_centroid
;
1758 else if (location
== INTERP_SAMPLE
)
1759 return ctx
->linear_sample
;
1766 radv_get_sample_pos_offset(uint32_t num_samples
)
1768 uint32_t sample_pos_offset
= 0;
1770 switch (num_samples
) {
1772 sample_pos_offset
= 1;
1775 sample_pos_offset
= 3;
1778 sample_pos_offset
= 7;
1783 return sample_pos_offset
;
1786 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1787 LLVMValueRef sample_id
)
1789 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1791 LLVMValueRef result
;
1792 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
1793 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
1795 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1796 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1798 uint32_t sample_pos_offset
=
1799 radv_get_sample_pos_offset(ctx
->options
->key
.fs
.num_samples
);
1802 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
1803 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
1804 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1810 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1812 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1813 uint8_t log2_ps_iter_samples
;
1815 if (ctx
->shader_info
->info
.ps
.force_persample
) {
1816 log2_ps_iter_samples
=
1817 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
1819 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
1822 /* The bit pattern matches that used by fixed function fragment
1824 static const uint16_t ps_iter_masks
[] = {
1825 0xffff, /* not used */
1831 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1833 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1835 LLVMValueRef result
, sample_id
;
1836 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
1837 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1838 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
1844 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1846 LLVMValueRef gs_next_vertex
;
1847 LLVMValueRef can_emit
;
1848 unsigned offset
= 0;
1849 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1851 /* Write vertex attribute values to GSVS ring */
1852 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1853 ctx
->gs_next_vertex
[stream
],
1856 /* If this thread has already emitted the declared maximum number of
1857 * vertices, kill it: excessive vertex emissions are not supposed to
1858 * have any effect, and GS threads have no externally observable
1859 * effects other than emitting vertices.
1861 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1862 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
1863 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1865 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1866 unsigned output_usage_mask
=
1867 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
1868 uint8_t output_stream
=
1869 ctx
->shader_info
->info
.gs
.output_streams
[i
];
1870 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1871 int length
= util_last_bit(output_usage_mask
);
1873 if (!(ctx
->output_mask
& (1ull << i
)) ||
1874 output_stream
!= stream
)
1877 for (unsigned j
= 0; j
< length
; j
++) {
1878 if (!(output_usage_mask
& (1 << j
)))
1881 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1883 LLVMValueRef voffset
=
1884 LLVMConstInt(ctx
->ac
.i32
, offset
*
1885 ctx
->gs_max_out_vertices
, false);
1889 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1890 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1892 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1893 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1895 ac_build_buffer_store_dword(&ctx
->ac
,
1896 ctx
->gsvs_ring
[stream
],
1898 voffset
, ctx
->gs2vs_offset
, 0,
1899 ac_glc
| ac_slc
, true);
1903 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1905 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1907 ac_build_sendmsg(&ctx
->ac
,
1908 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1913 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1915 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1916 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1920 load_tess_coord(struct ac_shader_abi
*abi
)
1922 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1924 LLVMValueRef coord
[4] = {
1931 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
1932 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1933 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1935 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1939 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1941 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1942 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
1946 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1948 return abi
->base_vertex
;
1951 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1952 LLVMValueRef buffer_ptr
, bool write
)
1954 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1955 LLVMValueRef result
;
1957 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1959 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1960 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1965 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1967 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1968 LLVMValueRef result
;
1970 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
1971 /* Do not load the descriptor for inlined uniform blocks. */
1975 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1977 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1978 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1983 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1984 unsigned descriptor_set
,
1985 unsigned base_index
,
1986 unsigned constant_index
,
1988 enum ac_descriptor_type desc_type
,
1989 bool image
, bool write
,
1992 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1993 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1994 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
1995 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1996 unsigned offset
= binding
->offset
;
1997 unsigned stride
= binding
->size
;
1999 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2002 assert(base_index
< layout
->binding_count
);
2004 switch (desc_type
) {
2006 type
= ctx
->ac
.v8i32
;
2010 type
= ctx
->ac
.v8i32
;
2014 case AC_DESC_SAMPLER
:
2015 type
= ctx
->ac
.v4i32
;
2016 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
2017 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
2022 case AC_DESC_BUFFER
:
2023 type
= ctx
->ac
.v4i32
;
2026 case AC_DESC_PLANE_0
:
2027 case AC_DESC_PLANE_1
:
2028 case AC_DESC_PLANE_2
:
2029 type
= ctx
->ac
.v8i32
;
2031 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
2034 unreachable("invalid desc_type\n");
2037 offset
+= constant_index
* stride
;
2039 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
2040 (!index
|| binding
->immutable_samplers_equal
)) {
2041 if (binding
->immutable_samplers_equal
)
2044 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
2046 LLVMValueRef constants
[] = {
2047 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
2048 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
2049 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
2050 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
2052 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
2055 assert(stride
% type_size
== 0);
2057 LLVMValueRef adjusted_index
= index
;
2058 if (!adjusted_index
)
2059 adjusted_index
= ctx
->ac
.i32_0
;
2061 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
2063 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
2064 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
2065 list
= LLVMBuildPointerCast(builder
, list
,
2066 ac_array_in_const32_addr_space(type
), "");
2068 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
2070 /* 3 plane formats always have same size and format for plane 1 & 2, so
2071 * use the tail from plane 1 so that we can store only the first 16 bytes
2072 * of the last plane. */
2073 if (desc_type
== AC_DESC_PLANE_2
) {
2074 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
2076 LLVMValueRef components
[8];
2077 for (unsigned i
= 0; i
< 4; ++i
)
2078 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
2080 for (unsigned i
= 4; i
< 8; ++i
)
2081 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
2082 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
2088 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
2089 * so we may need to fix it up. */
2091 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
2092 unsigned adjustment
,
2095 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
2098 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
2100 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2102 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
2103 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2105 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
2107 /* For the integer-like cases, do a natural sign extension.
2109 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2110 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2113 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
2114 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
2115 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
2116 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
2118 /* Convert back to the right type. */
2119 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
2121 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
2122 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2123 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
2124 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
2125 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
2126 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2129 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2133 get_num_channels_from_data_format(unsigned data_format
)
2135 switch (data_format
) {
2136 case V_008F0C_BUF_DATA_FORMAT_8
:
2137 case V_008F0C_BUF_DATA_FORMAT_16
:
2138 case V_008F0C_BUF_DATA_FORMAT_32
:
2140 case V_008F0C_BUF_DATA_FORMAT_8_8
:
2141 case V_008F0C_BUF_DATA_FORMAT_16_16
:
2142 case V_008F0C_BUF_DATA_FORMAT_32_32
:
2144 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
2145 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
2146 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
2148 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
2149 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
2150 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
2151 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
2152 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
2162 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
2164 unsigned num_channels
,
2167 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
2168 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
2169 LLVMValueRef chan
[4];
2171 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
2172 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
2174 if (num_channels
== 4 && num_channels
== vec_size
)
2177 num_channels
= MIN2(num_channels
, vec_size
);
2179 for (unsigned i
= 0; i
< num_channels
; i
++)
2180 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
2183 assert(num_channels
== 1);
2188 for (unsigned i
= num_channels
; i
< 4; i
++) {
2189 chan
[i
] = i
== 3 ? one
: zero
;
2190 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
2193 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
2197 handle_vs_input_decl(struct radv_shader_context
*ctx
,
2198 struct nir_variable
*variable
)
2200 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
2201 LLVMValueRef t_offset
;
2202 LLVMValueRef t_list
;
2204 LLVMValueRef buffer_index
;
2205 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
2206 uint8_t input_usage_mask
=
2207 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
2208 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
2210 variable
->data
.driver_location
= variable
->data
.location
* 4;
2212 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
2213 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
2214 LLVMValueRef output
[4];
2215 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
2216 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
2217 unsigned data_format
= attrib_format
& 0x0f;
2218 unsigned num_format
= (attrib_format
>> 4) & 0x07;
2219 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
2220 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
2222 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
2223 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
2226 buffer_index
= ctx
->abi
.instance_id
;
2229 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
2230 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
2233 buffer_index
= ctx
->ac
.i32_0
;
2236 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.start_instance
, buffer_index
, "");
2238 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
2239 ctx
->abi
.base_vertex
, "");
2241 /* Adjust the number of channels to load based on the vertex
2244 unsigned num_format_channels
= get_num_channels_from_data_format(data_format
);
2245 unsigned num_channels
= MIN2(num_input_channels
, num_format_channels
);
2246 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
2247 unsigned attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
2248 unsigned attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
2250 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2251 /* Always load, at least, 3 channels for formats that
2252 * need to be shuffled because X<->Z.
2254 num_channels
= MAX2(num_channels
, 3);
2257 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
2258 LLVMValueRef buffer_offset
=
2259 LLVMConstInt(ctx
->ac
.i32
,
2260 attrib_offset
/ attrib_stride
, false);
2262 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
2266 attrib_offset
= attrib_offset
% attrib_stride
;
2269 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
2270 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
2272 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
2274 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
2275 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
2277 data_format
, num_format
, 0, true);
2279 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2281 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
2282 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
2283 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
2284 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
2286 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
2289 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
2292 for (unsigned chan
= 0; chan
< 4; chan
++) {
2293 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2294 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
2295 if (type
== GLSL_TYPE_FLOAT16
) {
2296 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
2297 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
2301 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
2302 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
2304 for (unsigned chan
= 0; chan
< 4; chan
++) {
2305 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
2306 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
2307 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
2309 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
2314 static void interp_fs_input(struct radv_shader_context
*ctx
,
2316 LLVMValueRef interp_param
,
2317 LLVMValueRef prim_mask
,
2319 LLVMValueRef result
[4])
2321 LLVMValueRef attr_number
;
2324 bool interp
= !LLVMIsUndef(interp_param
);
2326 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
2328 /* fs.constant returns the param from the middle vertex, so it's not
2329 * really useful for flat shading. It's meant to be used for custom
2330 * interpolation (but the intrinsic can't fetch from the other two
2333 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2334 * to do the right thing. The only reason we use fs.constant is that
2335 * fs.interp cannot be used on integers, because they can be equal
2339 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
2342 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
2344 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
2348 for (chan
= 0; chan
< 4; chan
++) {
2349 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2351 if (interp
&& float16
) {
2352 result
[chan
] = ac_build_fs_interp_f16(&ctx
->ac
,
2356 } else if (interp
) {
2357 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
2362 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
2363 LLVMConstInt(ctx
->ac
.i32
, 2, false),
2367 result
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, result
[chan
], ctx
->ac
.i32
, "");
2368 result
[chan
] = LLVMBuildTruncOrBitCast(ctx
->ac
.builder
, result
[chan
], float16
? ctx
->ac
.i16
: ctx
->ac
.i32
, "");
2373 static void mark_16bit_fs_input(struct radv_shader_context
*ctx
,
2374 const struct glsl_type
*type
,
2377 if (glsl_type_is_scalar(type
) || glsl_type_is_vector(type
) || glsl_type_is_matrix(type
)) {
2378 unsigned attrib_count
= glsl_count_attribute_slots(type
, false);
2379 if (glsl_type_is_16bit(type
)) {
2380 ctx
->float16_shaded_mask
|= ((1ull << attrib_count
) - 1) << location
;
2382 } else if (glsl_type_is_array(type
)) {
2383 unsigned stride
= glsl_count_attribute_slots(glsl_get_array_element(type
), false);
2384 for (unsigned i
= 0; i
< glsl_get_length(type
); ++i
) {
2385 mark_16bit_fs_input(ctx
, glsl_get_array_element(type
), location
+ i
* stride
);
2388 assert(glsl_type_is_struct_or_ifc(type
));
2389 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
2390 mark_16bit_fs_input(ctx
, glsl_get_struct_field(type
, i
), location
);
2391 location
+= glsl_count_attribute_slots(glsl_get_struct_field(type
, i
), false);
2397 handle_fs_input_decl(struct radv_shader_context
*ctx
,
2398 struct nir_variable
*variable
)
2400 int idx
= variable
->data
.location
;
2401 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2402 LLVMValueRef interp
= NULL
;
2405 variable
->data
.driver_location
= idx
* 4;
2408 if (variable
->data
.compact
) {
2409 unsigned component_count
= variable
->data
.location_frac
+
2410 glsl_get_length(variable
->type
);
2411 attrib_count
= (component_count
+ 3) / 4;
2413 mark_16bit_fs_input(ctx
, variable
->type
, idx
);
2415 mask
= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
2417 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
||
2418 glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT16
||
2419 glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_STRUCT
) {
2420 unsigned interp_type
;
2421 if (variable
->data
.sample
)
2422 interp_type
= INTERP_SAMPLE
;
2423 else if (variable
->data
.centroid
)
2424 interp_type
= INTERP_CENTROID
;
2426 interp_type
= INTERP_CENTER
;
2428 interp
= lookup_interp_param(&ctx
->abi
, variable
->data
.interpolation
, interp_type
);
2431 interp
= LLVMGetUndef(ctx
->ac
.i32
);
2433 for (unsigned i
= 0; i
< attrib_count
; ++i
)
2434 ctx
->inputs
[ac_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
2436 ctx
->input_mask
|= mask
;
2440 handle_vs_inputs(struct radv_shader_context
*ctx
,
2441 struct nir_shader
*nir
) {
2442 nir_foreach_variable(variable
, &nir
->inputs
)
2443 handle_vs_input_decl(ctx
, variable
);
2447 prepare_interp_optimize(struct radv_shader_context
*ctx
,
2448 struct nir_shader
*nir
)
2450 bool uses_center
= false;
2451 bool uses_centroid
= false;
2452 nir_foreach_variable(variable
, &nir
->inputs
) {
2453 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
2454 variable
->data
.sample
)
2457 if (variable
->data
.centroid
)
2458 uses_centroid
= true;
2463 if (uses_center
&& uses_centroid
) {
2464 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
2465 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
2466 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
2471 handle_fs_inputs(struct radv_shader_context
*ctx
,
2472 struct nir_shader
*nir
)
2474 prepare_interp_optimize(ctx
, nir
);
2476 nir_foreach_variable(variable
, &nir
->inputs
)
2477 handle_fs_input_decl(ctx
, variable
);
2481 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
2482 ctx
->shader_info
->info
.ps
.layer_input
) {
2483 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
2484 ctx
->inputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)] = LLVMGetUndef(ctx
->ac
.i32
);
2487 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
2488 LLVMValueRef interp_param
;
2489 LLVMValueRef
*inputs
= ctx
->inputs
+ac_llvm_reg_index_soa(i
, 0);
2491 if (!(ctx
->input_mask
& (1ull << i
)))
2494 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
2495 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
2496 interp_param
= *inputs
;
2497 bool float16
= (ctx
->float16_shaded_mask
>> i
) & 1;
2498 interp_fs_input(ctx
, index
, interp_param
, ctx
->abi
.prim_mask
, float16
,
2501 if (LLVMIsUndef(interp_param
))
2502 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
2504 ctx
->shader_info
->fs
.float16_shaded_mask
|= 1u << index
;
2505 if (i
>= VARYING_SLOT_VAR0
)
2506 ctx
->abi
.fs_input_attr_indices
[i
- VARYING_SLOT_VAR0
] = index
;
2508 } else if (i
== VARYING_SLOT_CLIP_DIST0
) {
2509 int length
= ctx
->shader_info
->info
.ps
.num_input_clips_culls
;
2511 for (unsigned j
= 0; j
< length
; j
+= 4) {
2512 inputs
= ctx
->inputs
+ ac_llvm_reg_index_soa(i
, j
);
2514 interp_param
= *inputs
;
2515 interp_fs_input(ctx
, index
, interp_param
,
2516 ctx
->abi
.prim_mask
, false, inputs
);
2519 } else if (i
== VARYING_SLOT_POS
) {
2520 for(int i
= 0; i
< 3; ++i
)
2521 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
2523 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
2524 ctx
->abi
.frag_pos
[3]);
2527 ctx
->shader_info
->fs
.num_interp
= index
;
2528 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
2530 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
2531 ctx
->abi
.view_index
= ctx
->inputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2535 scan_shader_output_decl(struct radv_shader_context
*ctx
,
2536 struct nir_variable
*variable
,
2537 struct nir_shader
*shader
,
2538 gl_shader_stage stage
)
2540 int idx
= variable
->data
.location
+ variable
->data
.index
;
2541 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2542 uint64_t mask_attribs
;
2544 variable
->data
.driver_location
= idx
* 4;
2546 /* tess ctrl has it's own load/store paths for outputs */
2547 if (stage
== MESA_SHADER_TESS_CTRL
)
2550 if (variable
->data
.compact
) {
2551 unsigned component_count
= variable
->data
.location_frac
+
2552 glsl_get_length(variable
->type
);
2553 attrib_count
= (component_count
+ 3) / 4;
2556 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2557 if (stage
== MESA_SHADER_VERTEX
||
2558 stage
== MESA_SHADER_TESS_EVAL
||
2559 stage
== MESA_SHADER_GEOMETRY
) {
2560 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2561 if (stage
== MESA_SHADER_VERTEX
) {
2562 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2563 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2564 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2566 if (stage
== MESA_SHADER_TESS_EVAL
) {
2567 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2568 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2569 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2574 ctx
->output_mask
|= mask_attribs
;
2578 /* Initialize arguments for the shader export intrinsic */
2580 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2581 LLVMValueRef
*values
,
2582 unsigned enabled_channels
,
2584 struct ac_export_args
*args
)
2586 /* Specify the channels that are enabled. */
2587 args
->enabled_channels
= enabled_channels
;
2589 /* Specify whether the EXEC mask represents the valid mask */
2590 args
->valid_mask
= 0;
2592 /* Specify whether this is the last export */
2595 /* Specify the target we are exporting */
2596 args
->target
= target
;
2598 args
->compr
= false;
2599 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2600 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2601 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2602 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2607 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
2608 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2609 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2610 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2611 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2612 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2615 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2616 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2617 unsigned bits
, bool hi
) = NULL
;
2619 switch(col_format
) {
2620 case V_028714_SPI_SHADER_ZERO
:
2621 args
->enabled_channels
= 0; /* writemask */
2622 args
->target
= V_008DFC_SQ_EXP_NULL
;
2625 case V_028714_SPI_SHADER_32_R
:
2626 args
->enabled_channels
= 1;
2627 args
->out
[0] = values
[0];
2630 case V_028714_SPI_SHADER_32_GR
:
2631 args
->enabled_channels
= 0x3;
2632 args
->out
[0] = values
[0];
2633 args
->out
[1] = values
[1];
2636 case V_028714_SPI_SHADER_32_AR
:
2637 if (ctx
->ac
.chip_class
>= GFX10
) {
2638 args
->enabled_channels
= 0x3;
2639 args
->out
[0] = values
[0];
2640 args
->out
[1] = values
[3];
2642 args
->enabled_channels
= 0x9;
2643 args
->out
[0] = values
[0];
2644 args
->out
[3] = values
[3];
2648 case V_028714_SPI_SHADER_FP16_ABGR
:
2649 args
->enabled_channels
= 0x5;
2650 packf
= ac_build_cvt_pkrtz_f16
;
2652 for (unsigned chan
= 0; chan
< 4; chan
++)
2653 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
2659 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2660 args
->enabled_channels
= 0x5;
2661 packf
= ac_build_cvt_pknorm_u16
;
2664 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2665 args
->enabled_channels
= 0x5;
2666 packf
= ac_build_cvt_pknorm_i16
;
2669 case V_028714_SPI_SHADER_UINT16_ABGR
:
2670 args
->enabled_channels
= 0x5;
2671 packi
= ac_build_cvt_pk_u16
;
2673 for (unsigned chan
= 0; chan
< 4; chan
++)
2674 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
2675 ac_to_integer(&ctx
->ac
, values
[chan
]),
2680 case V_028714_SPI_SHADER_SINT16_ABGR
:
2681 args
->enabled_channels
= 0x5;
2682 packi
= ac_build_cvt_pk_i16
;
2684 for (unsigned chan
= 0; chan
< 4; chan
++)
2685 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
2686 ac_to_integer(&ctx
->ac
, values
[chan
]),
2692 case V_028714_SPI_SHADER_32_ABGR
:
2693 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2697 /* Pack f16 or norm_i16/u16. */
2699 for (chan
= 0; chan
< 2; chan
++) {
2700 LLVMValueRef pack_args
[2] = {
2702 values
[2 * chan
+ 1]
2704 LLVMValueRef packed
;
2706 packed
= packf(&ctx
->ac
, pack_args
);
2707 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2709 args
->compr
= 1; /* COMPR flag */
2714 for (chan
= 0; chan
< 2; chan
++) {
2715 LLVMValueRef pack_args
[2] = {
2716 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2717 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2719 LLVMValueRef packed
;
2721 packed
= packi(&ctx
->ac
, pack_args
,
2722 is_int8
? 8 : is_int10
? 10 : 16,
2724 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2726 args
->compr
= 1; /* COMPR flag */
2732 for (unsigned chan
= 0; chan
< 4; chan
++) {
2733 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
2734 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
2737 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2739 for (unsigned i
= 0; i
< 4; ++i
)
2740 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2744 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2745 LLVMValueRef
*values
, unsigned enabled_channels
)
2747 struct ac_export_args args
;
2749 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2750 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2751 ac_build_export(&ctx
->ac
, &args
);
2755 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2757 LLVMValueRef output
=
2758 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2760 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2764 radv_emit_stream_output(struct radv_shader_context
*ctx
,
2765 LLVMValueRef
const *so_buffers
,
2766 LLVMValueRef
const *so_write_offsets
,
2767 const struct radv_stream_output
*output
)
2769 unsigned num_comps
= util_bitcount(output
->component_mask
);
2770 unsigned loc
= output
->location
;
2771 unsigned buf
= output
->buffer
;
2772 unsigned offset
= output
->offset
;
2774 LLVMValueRef out
[4];
2776 assert(num_comps
&& num_comps
<= 4);
2777 if (!num_comps
|| num_comps
> 4)
2780 /* Get the first component. */
2781 start
= ffs(output
->component_mask
) - 1;
2783 /* Load the output as int. */
2784 for (int i
= 0; i
< num_comps
; i
++) {
2785 out
[i
] = ac_to_integer(&ctx
->ac
,
2786 radv_load_output(ctx
, loc
, start
+ i
));
2789 /* Pack the output. */
2790 LLVMValueRef vdata
= NULL
;
2792 switch (num_comps
) {
2793 case 1: /* as i32 */
2796 case 2: /* as v2i32 */
2797 case 3: /* as v4i32 (aligned to 4) */
2798 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
2800 case 4: /* as v4i32 */
2801 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
2802 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
2803 util_next_power_of_two(num_comps
) :
2808 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
2809 vdata
, num_comps
, so_write_offsets
[buf
],
2810 ctx
->ac
.i32_0
, offset
,
2811 ac_glc
| ac_slc
, false);
2815 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
2817 struct ac_build_if_state if_ctx
;
2820 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2821 assert(ctx
->streamout_config
);
2822 LLVMValueRef so_vtx_count
=
2823 ac_build_bfe(&ctx
->ac
, ctx
->streamout_config
,
2824 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2825 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
2827 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2829 /* can_emit = tid < so_vtx_count; */
2830 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
2831 tid
, so_vtx_count
, "");
2833 /* Emit the streamout code conditionally. This actually avoids
2834 * out-of-bounds buffer access. The hw tells us via the SGPR
2835 * (so_vtx_count) which threads are allowed to emit streamout data.
2837 ac_nir_build_if(&if_ctx
, ctx
, can_emit
);
2839 /* The buffer offset is computed as follows:
2840 * ByteOffset = streamout_offset[buffer_id]*4 +
2841 * (streamout_write_index + thread_id)*stride[buffer_id] +
2844 LLVMValueRef so_write_index
= ctx
->streamout_write_idx
;
2846 /* Compute (streamout_write_index + thread_id). */
2848 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
2850 /* Load the descriptor and compute the write offset for each
2853 LLVMValueRef so_write_offset
[4] = {};
2854 LLVMValueRef so_buffers
[4] = {};
2855 LLVMValueRef buf_ptr
= ctx
->streamout_buffers
;
2857 for (i
= 0; i
< 4; i
++) {
2858 uint16_t stride
= ctx
->shader_info
->info
.so
.strides
[i
];
2863 LLVMValueRef offset
=
2864 LLVMConstInt(ctx
->ac
.i32
, i
, false);
2866 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
2869 LLVMValueRef so_offset
= ctx
->streamout_offset
[i
];
2871 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
2872 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2874 so_write_offset
[i
] =
2875 ac_build_imad(&ctx
->ac
, so_write_index
,
2876 LLVMConstInt(ctx
->ac
.i32
,
2881 /* Write streamout data. */
2882 for (i
= 0; i
< ctx
->shader_info
->info
.so
.num_outputs
; i
++) {
2883 struct radv_stream_output
*output
=
2884 &ctx
->shader_info
->info
.so
.outputs
[i
];
2886 if (stream
!= output
->stream
)
2889 radv_emit_stream_output(ctx
, so_buffers
,
2890 so_write_offset
, output
);
2893 ac_nir_build_endif(&if_ctx
);
2897 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2898 bool export_prim_id
, bool export_layer_id
,
2899 bool export_clip_dists
,
2900 struct radv_vs_output_info
*outinfo
)
2902 uint32_t param_count
= 0;
2904 unsigned pos_idx
, num_pos_exports
= 0;
2905 struct ac_export_args args
, pos_args
[4] = {};
2906 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2909 if (ctx
->options
->key
.has_multiview_view_index
) {
2910 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2912 for(unsigned i
= 0; i
< 4; ++i
)
2913 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2914 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2917 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
2918 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2921 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2922 sizeof(outinfo
->vs_output_param_offset
));
2924 for(unsigned location
= VARYING_SLOT_CLIP_DIST0
; location
<= VARYING_SLOT_CLIP_DIST1
; ++location
) {
2925 if (ctx
->output_mask
& (1ull << location
)) {
2926 unsigned output_usage_mask
, length
;
2927 LLVMValueRef slots
[4];
2930 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2931 !ctx
->is_gs_copy_shader
) {
2933 ctx
->shader_info
->info
.vs
.output_usage_mask
[location
];
2934 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2936 ctx
->shader_info
->info
.tes
.output_usage_mask
[location
];
2938 assert(ctx
->is_gs_copy_shader
);
2940 ctx
->shader_info
->info
.gs
.output_usage_mask
[location
];
2943 length
= util_last_bit(output_usage_mask
);
2945 for (j
= 0; j
< length
; j
++)
2946 slots
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, location
, j
));
2948 for (i
= length
; i
< 4; i
++)
2949 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
2951 target
= V_008DFC_SQ_EXP_POS
+ 2 + (location
- VARYING_SLOT_CLIP_DIST0
);
2952 si_llvm_init_export_args(ctx
, &slots
[0], 0xf, target
, &args
);
2953 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2954 &args
, sizeof(args
));
2956 if (export_clip_dists
) {
2957 /* Export the clip/cull distances values to the next stage. */
2958 radv_export_param(ctx
, param_count
, &slots
[0], 0xf);
2959 outinfo
->vs_output_param_offset
[location
] = param_count
++;
2964 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
2965 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
2966 for (unsigned j
= 0; j
< 4; j
++)
2967 pos_values
[j
] = radv_load_output(ctx
, VARYING_SLOT_POS
, j
);
2969 si_llvm_init_export_args(ctx
, pos_values
, 0xf, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2971 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
2972 outinfo
->writes_pointsize
= true;
2973 psize_value
= radv_load_output(ctx
, VARYING_SLOT_PSIZ
, 0);
2976 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
2977 outinfo
->writes_layer
= true;
2978 layer_value
= radv_load_output(ctx
, VARYING_SLOT_LAYER
, 0);
2981 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
2982 outinfo
->writes_viewport_index
= true;
2983 viewport_index_value
= radv_load_output(ctx
, VARYING_SLOT_VIEWPORT
, 0);
2986 if (ctx
->shader_info
->info
.so
.num_outputs
&&
2987 !ctx
->is_gs_copy_shader
) {
2988 /* The GS copy shader emission already emits streamout. */
2989 radv_emit_streamout(ctx
, 0);
2992 if (outinfo
->writes_pointsize
||
2993 outinfo
->writes_layer
||
2994 outinfo
->writes_viewport_index
) {
2995 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2996 (outinfo
->writes_layer
== true ? 4 : 0));
2997 pos_args
[1].valid_mask
= 0;
2998 pos_args
[1].done
= 0;
2999 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
3000 pos_args
[1].compr
= 0;
3001 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
3002 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
3003 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
3004 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
3006 if (outinfo
->writes_pointsize
== true)
3007 pos_args
[1].out
[0] = psize_value
;
3008 if (outinfo
->writes_layer
== true)
3009 pos_args
[1].out
[2] = layer_value
;
3010 if (outinfo
->writes_viewport_index
== true) {
3011 if (ctx
->options
->chip_class
>= GFX9
) {
3012 /* GFX9 has the layer in out.z[10:0] and the viewport
3013 * index in out.z[19:16].
3015 LLVMValueRef v
= viewport_index_value
;
3016 v
= ac_to_integer(&ctx
->ac
, v
);
3017 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
3018 LLVMConstInt(ctx
->ac
.i32
, 16, false),
3020 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
3021 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
3023 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
3024 pos_args
[1].enabled_channels
|= 1 << 2;
3026 pos_args
[1].out
[3] = viewport_index_value
;
3027 pos_args
[1].enabled_channels
|= 1 << 3;
3031 for (i
= 0; i
< 4; i
++) {
3032 if (pos_args
[i
].out
[0])
3036 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
3037 * Setting valid_mask=1 prevents it and has no other effect.
3039 if (ctx
->ac
.family
== CHIP_NAVI10
||
3040 ctx
->ac
.family
== CHIP_NAVI12
||
3041 ctx
->ac
.family
== CHIP_NAVI14
)
3042 pos_args
[0].valid_mask
= 1;
3045 for (i
= 0; i
< 4; i
++) {
3046 if (!pos_args
[i
].out
[0])
3049 /* Specify the target we are exporting */
3050 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
3051 if (pos_idx
== num_pos_exports
)
3052 pos_args
[i
].done
= 1;
3053 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
3056 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3057 LLVMValueRef values
[4];
3058 if (!(ctx
->output_mask
& (1ull << i
)))
3061 if (i
!= VARYING_SLOT_LAYER
&&
3062 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
3063 i
< VARYING_SLOT_VAR0
)
3066 for (unsigned j
= 0; j
< 4; j
++)
3067 values
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
3069 unsigned output_usage_mask
;
3071 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
3072 !ctx
->is_gs_copy_shader
) {
3074 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
3075 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3077 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
3079 assert(ctx
->is_gs_copy_shader
);
3081 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
3084 radv_export_param(ctx
, param_count
, values
, output_usage_mask
);
3086 outinfo
->vs_output_param_offset
[i
] = param_count
++;
3089 if (export_prim_id
) {
3090 LLVMValueRef values
[4];
3092 values
[0] = ctx
->vs_prim_id
;
3093 for (unsigned j
= 1; j
< 4; j
++)
3094 values
[j
] = ctx
->ac
.f32_0
;
3096 radv_export_param(ctx
, param_count
, values
, 0x1);
3098 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
3099 outinfo
->export_prim_id
= true;
3102 if (export_layer_id
&& layer_value
) {
3103 LLVMValueRef values
[4];
3105 values
[0] = layer_value
;
3106 for (unsigned j
= 1; j
< 4; j
++)
3107 values
[j
] = ctx
->ac
.f32_0
;
3109 radv_export_param(ctx
, param_count
, values
, 0x1);
3111 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
++;
3114 outinfo
->pos_exports
= num_pos_exports
;
3115 outinfo
->param_exports
= param_count
;
3119 handle_es_outputs_post(struct radv_shader_context
*ctx
,
3120 struct radv_es_output_info
*outinfo
)
3123 uint64_t max_output_written
= 0;
3124 LLVMValueRef lds_base
= NULL
;
3126 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3129 if (!(ctx
->output_mask
& (1ull << i
)))
3132 param_index
= shader_io_get_unique_index(i
);
3134 max_output_written
= MAX2(param_index
, max_output_written
);
3137 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
3139 if (ctx
->ac
.chip_class
>= GFX9
) {
3140 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
3141 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
3142 LLVMValueRef wave_idx
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
3143 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
3144 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
3145 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
3146 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
3147 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
3150 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3151 LLVMValueRef dw_addr
= NULL
;
3152 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
3153 unsigned output_usage_mask
;
3156 if (!(ctx
->output_mask
& (1ull << i
)))
3159 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3161 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
3163 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3165 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
3168 param_index
= shader_io_get_unique_index(i
);
3171 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3172 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
3176 for (j
= 0; j
< 4; j
++) {
3177 if (!(output_usage_mask
& (1 << j
)))
3180 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
3181 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3182 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3184 if (ctx
->ac
.chip_class
>= GFX9
) {
3185 LLVMValueRef dw_addr_offset
=
3186 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3187 LLVMConstInt(ctx
->ac
.i32
,
3190 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
3192 ac_build_buffer_store_dword(&ctx
->ac
,
3195 NULL
, ctx
->es2gs_offset
,
3196 (4 * param_index
+ j
) * 4,
3197 ac_glc
| ac_slc
, true);
3204 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
3206 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
3207 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->shader_info
->info
.vs
.ls_outputs_written
);
3208 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
3209 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
3210 vertex_dw_stride
, "");
3212 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3213 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
3215 if (!(ctx
->output_mask
& (1ull << i
)))
3218 int param
= shader_io_get_unique_index(i
);
3219 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
3220 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
3222 for (unsigned j
= 0; j
< 4; j
++) {
3223 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
3224 value
= ac_to_integer(&ctx
->ac
, value
);
3225 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
3226 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
3227 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
3232 static LLVMValueRef
get_wave_id_in_tg(struct radv_shader_context
*ctx
)
3234 return ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
3237 static LLVMValueRef
ngg_get_vtx_cnt(struct radv_shader_context
*ctx
)
3239 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
3240 LLVMConstInt(ctx
->ac
.i32
, 12, false),
3241 LLVMConstInt(ctx
->ac
.i32
, 9, false),
3245 static LLVMValueRef
ngg_get_prim_cnt(struct radv_shader_context
*ctx
)
3247 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
3248 LLVMConstInt(ctx
->ac
.i32
, 22, false),
3249 LLVMConstInt(ctx
->ac
.i32
, 9, false),
3253 /* Send GS Alloc Req message from the first wave of the group to SPI.
3254 * Message payload is:
3255 * - bits 0..10: vertices in group
3256 * - bits 12..22: primitives in group
3258 static void build_sendmsg_gs_alloc_req(struct radv_shader_context
*ctx
,
3259 LLVMValueRef vtx_cnt
,
3260 LLVMValueRef prim_cnt
)
3262 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3265 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
3266 ac_build_ifcc(&ctx
->ac
, tmp
, 5020);
3268 tmp
= LLVMBuildShl(builder
, prim_cnt
, LLVMConstInt(ctx
->ac
.i32
, 12, false),"");
3269 tmp
= LLVMBuildOr(builder
, tmp
, vtx_cnt
, "");
3270 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_ALLOC_REQ
, tmp
);
3272 ac_build_endif(&ctx
->ac
, 5020);
3276 unsigned num_vertices
;
3277 LLVMValueRef isnull
;
3278 LLVMValueRef index
[3];
3279 LLVMValueRef edgeflag
[3];
3282 static void build_export_prim(struct radv_shader_context
*ctx
,
3283 const struct ngg_prim
*prim
)
3285 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3286 struct ac_export_args args
;
3289 tmp
= LLVMBuildZExt(builder
, prim
->isnull
, ctx
->ac
.i32
, "");
3290 args
.out
[0] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 31, false), "");
3292 for (unsigned i
= 0; i
< prim
->num_vertices
; ++i
) {
3293 tmp
= LLVMBuildShl(builder
, prim
->index
[i
],
3294 LLVMConstInt(ctx
->ac
.i32
, 10 * i
, false), "");
3295 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3296 tmp
= LLVMBuildZExt(builder
, prim
->edgeflag
[i
], ctx
->ac
.i32
, "");
3297 tmp
= LLVMBuildShl(builder
, tmp
,
3298 LLVMConstInt(ctx
->ac
.i32
, 10 * i
+ 9, false), "");
3299 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3302 args
.out
[0] = LLVMBuildBitCast(builder
, args
.out
[0], ctx
->ac
.f32
, "");
3303 args
.out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
3304 args
.out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
3305 args
.out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
3307 args
.target
= V_008DFC_SQ_EXP_PRIM
;
3308 args
.enabled_channels
= 1;
3310 args
.valid_mask
= false;
3313 ac_build_export(&ctx
->ac
, &args
);
3317 handle_ngg_outputs_post(struct radv_shader_context
*ctx
)
3319 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3320 struct ac_build_if_state if_state
;
3321 unsigned num_vertices
= 3;
3324 assert(ctx
->stage
== MESA_SHADER_VERTEX
&& !ctx
->is_gs_copy_shader
);
3326 LLVMValueRef prims_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
3327 LLVMValueRef vtx_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 0, 8);
3328 LLVMValueRef is_gs_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3329 ac_get_thread_id(&ctx
->ac
), prims_in_wave
, "");
3330 LLVMValueRef is_es_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3331 ac_get_thread_id(&ctx
->ac
), vtx_in_wave
, "");
3332 LLVMValueRef vtxindex
[] = {
3333 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 0, 16),
3334 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 16, 16),
3335 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[2], 0, 16),
3338 /* TODO: streamout */
3340 /* TODO: VS primitive ID */
3341 if (ctx
->options
->key
.vs
.out
.export_prim_id
)
3344 /* TODO: primitive culling */
3346 build_sendmsg_gs_alloc_req(ctx
, ngg_get_vtx_cnt(ctx
), ngg_get_prim_cnt(ctx
));
3348 /* TODO: streamout queries */
3349 /* Export primitive data to the index buffer. Format is:
3350 * - bits 0..8: index 0
3351 * - bit 9: edge flag 0
3352 * - bits 10..18: index 1
3353 * - bit 19: edge flag 1
3354 * - bits 20..28: index 2
3355 * - bit 29: edge flag 2
3356 * - bit 31: null primitive (skip)
3358 * For the first version, we will always build up all three indices
3359 * independent of the primitive type. The additional garbage data
3362 * TODO: culling depends on the primitive type, so can have some
3365 ac_nir_build_if(&if_state
, ctx
, is_gs_thread
);
3367 struct ngg_prim prim
= {};
3369 prim
.num_vertices
= num_vertices
;
3370 prim
.isnull
= ctx
->ac
.i1false
;
3371 memcpy(prim
.index
, vtxindex
, sizeof(vtxindex
[0]) * 3);
3373 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
3374 tmp
= LLVMBuildLShr(builder
, ctx
->abi
.gs_invocation_id
,
3375 LLVMConstInt(ctx
->ac
.i32
, 8 + i
, false), "");
3376 prim
.edgeflag
[i
] = LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3379 build_export_prim(ctx
, &prim
);
3381 ac_nir_build_endif(&if_state
);
3383 /* Export per-vertex data (positions and parameters). */
3384 ac_nir_build_if(&if_state
, ctx
, is_es_thread
);
3386 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.out
.export_prim_id
,
3387 ctx
->options
->key
.vs
.out
.export_layer_id
,
3388 ctx
->options
->key
.vs
.out
.export_clip_dists
,
3389 &ctx
->shader_info
->vs
.outinfo
);
3391 ac_nir_build_endif(&if_state
);
3395 write_tess_factors(struct radv_shader_context
*ctx
)
3397 unsigned stride
, outer_comps
, inner_comps
;
3398 struct ac_build_if_state if_ctx
, inner_if_ctx
;
3399 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3400 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
3401 unsigned tess_inner_index
= 0, tess_outer_index
;
3402 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3403 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3405 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3407 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
3427 ac_nir_build_if(&if_ctx
, ctx
,
3428 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3429 invocation_id
, ctx
->ac
.i32_0
, ""));
3431 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3434 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3435 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3436 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3439 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3440 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3441 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3443 for (i
= 0; i
< 4; i
++) {
3444 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3445 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3449 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3450 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3451 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3453 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3455 for (i
= 0; i
< outer_comps
; i
++) {
3457 ac_lds_load(&ctx
->ac
, lds_outer
);
3458 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3461 for (i
= 0; i
< inner_comps
; i
++) {
3462 inner
[i
] = out
[outer_comps
+i
] =
3463 ac_lds_load(&ctx
->ac
, lds_inner
);
3464 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3469 /* Convert the outputs to vectors for stores. */
3470 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3474 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3477 buffer
= ctx
->hs_ring_tess_factor
;
3478 tf_base
= ctx
->tess_factor_offset
;
3479 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3480 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3481 unsigned tf_offset
= 0;
3483 if (ctx
->options
->chip_class
<= GFX8
) {
3484 ac_nir_build_if(&inner_if_ctx
, ctx
,
3485 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3486 rel_patch_id
, ctx
->ac
.i32_0
, ""));
3488 /* Store the dynamic HS control word. */
3489 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3490 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3491 1, ctx
->ac
.i32_0
, tf_base
,
3495 ac_nir_build_endif(&inner_if_ctx
);
3498 /* Store the tessellation factors. */
3499 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3500 MIN2(stride
, 4), byteoffset
, tf_base
,
3501 tf_offset
, ac_glc
, false);
3503 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3504 stride
- 4, byteoffset
, tf_base
,
3505 16 + tf_offset
, ac_glc
, false);
3507 //store to offchip for TES to read - only if TES reads them
3508 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
3509 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3510 LLVMValueRef tf_inner_offset
;
3511 unsigned param_outer
, param_inner
;
3513 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3514 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3515 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3517 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3518 util_next_power_of_two(outer_comps
));
3520 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3521 outer_comps
, tf_outer_offset
,
3522 ctx
->oc_lds
, 0, ac_glc
, false);
3524 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3525 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3526 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3528 inner_vec
= inner_comps
== 1 ? inner
[0] :
3529 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3530 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3531 inner_comps
, tf_inner_offset
,
3532 ctx
->oc_lds
, 0, ac_glc
, false);
3535 ac_nir_build_endif(&if_ctx
);
3539 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3541 write_tess_factors(ctx
);
3545 si_export_mrt_color(struct radv_shader_context
*ctx
,
3546 LLVMValueRef
*color
, unsigned index
,
3547 struct ac_export_args
*args
)
3550 si_llvm_init_export_args(ctx
, color
, 0xf,
3551 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3552 if (!args
->enabled_channels
)
3553 return false; /* unnecessary NULL export */
3559 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3560 LLVMValueRef depth
, LLVMValueRef stencil
,
3561 LLVMValueRef samplemask
)
3563 struct ac_export_args args
;
3565 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3567 ac_build_export(&ctx
->ac
, &args
);
3571 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3574 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3575 struct ac_export_args color_args
[8];
3577 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3578 LLVMValueRef values
[4];
3580 if (!(ctx
->output_mask
& (1ull << i
)))
3583 if (i
< FRAG_RESULT_DATA0
)
3586 for (unsigned j
= 0; j
< 4; j
++)
3587 values
[j
] = ac_to_float(&ctx
->ac
,
3588 radv_load_output(ctx
, i
, j
));
3590 bool ret
= si_export_mrt_color(ctx
, values
,
3591 i
- FRAG_RESULT_DATA0
,
3592 &color_args
[index
]);
3597 /* Process depth, stencil, samplemask. */
3598 if (ctx
->shader_info
->info
.ps
.writes_z
) {
3599 depth
= ac_to_float(&ctx
->ac
,
3600 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3602 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
3603 stencil
= ac_to_float(&ctx
->ac
,
3604 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
3606 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3607 samplemask
= ac_to_float(&ctx
->ac
,
3608 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
3611 /* Set the DONE bit on last non-null color export only if Z isn't
3615 !ctx
->shader_info
->info
.ps
.writes_z
&&
3616 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
3617 !ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3618 unsigned last
= index
- 1;
3620 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
3621 color_args
[last
].done
= 1; /* DONE bit */
3624 /* Export PS outputs. */
3625 for (unsigned i
= 0; i
< index
; i
++)
3626 ac_build_export(&ctx
->ac
, &color_args
[i
]);
3628 if (depth
|| stencil
|| samplemask
)
3629 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
3631 ac_build_export_null(&ctx
->ac
);
3635 emit_gs_epilogue(struct radv_shader_context
*ctx
)
3637 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
3641 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
3642 LLVMValueRef
*addrs
)
3644 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3646 switch (ctx
->stage
) {
3647 case MESA_SHADER_VERTEX
:
3648 if (ctx
->options
->key
.vs
.out
.as_ls
)
3649 handle_ls_outputs_post(ctx
);
3650 else if (ctx
->options
->key
.vs
.out
.as_ngg
)
3651 break; /* handled outside of the shader body */
3652 else if (ctx
->options
->key
.vs
.out
.as_es
)
3653 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
3655 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.out
.export_prim_id
,
3656 ctx
->options
->key
.vs
.out
.export_layer_id
,
3657 ctx
->options
->key
.vs
.out
.export_clip_dists
,
3658 &ctx
->shader_info
->vs
.outinfo
);
3660 case MESA_SHADER_FRAGMENT
:
3661 handle_fs_outputs_post(ctx
);
3663 case MESA_SHADER_GEOMETRY
:
3664 emit_gs_epilogue(ctx
);
3666 case MESA_SHADER_TESS_CTRL
:
3667 handle_tcs_outputs_post(ctx
);
3669 case MESA_SHADER_TESS_EVAL
:
3670 if (ctx
->options
->key
.tes
.out
.as_es
)
3671 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
3673 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.out
.export_prim_id
,
3674 ctx
->options
->key
.tes
.out
.export_layer_id
,
3675 ctx
->options
->key
.tes
.out
.export_clip_dists
,
3676 &ctx
->shader_info
->tes
.outinfo
);
3683 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
3684 LLVMPassManagerRef passmgr
,
3685 const struct radv_nir_compiler_options
*options
)
3687 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
3688 LLVMDisposeBuilder(ctx
->ac
.builder
);
3690 ac_llvm_context_dispose(&ctx
->ac
);
3694 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
3696 struct radv_vs_output_info
*outinfo
;
3698 switch (ctx
->stage
) {
3699 case MESA_SHADER_FRAGMENT
:
3700 case MESA_SHADER_COMPUTE
:
3701 case MESA_SHADER_TESS_CTRL
:
3702 case MESA_SHADER_GEOMETRY
:
3704 case MESA_SHADER_VERTEX
:
3705 if (ctx
->options
->key
.vs
.out
.as_ls
||
3706 ctx
->options
->key
.vs
.out
.as_es
)
3708 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
3710 case MESA_SHADER_TESS_EVAL
:
3711 if (ctx
->options
->key
.vs
.out
.as_es
)
3713 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
3716 unreachable("Unhandled shader type");
3719 ac_optimize_vs_outputs(&ctx
->ac
,
3721 outinfo
->vs_output_param_offset
,
3723 &outinfo
->param_exports
);
3727 ac_setup_rings(struct radv_shader_context
*ctx
)
3729 if (ctx
->options
->chip_class
<= GFX8
&&
3730 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
3731 ctx
->options
->key
.vs
.out
.as_es
|| ctx
->options
->key
.tes
.out
.as_es
)) {
3732 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
3734 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
3736 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
3741 if (ctx
->is_gs_copy_shader
) {
3743 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3744 LLVMConstInt(ctx
->ac
.i32
,
3745 RING_GSVS_VS
, false));
3748 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3749 /* The conceptual layout of the GSVS ring is
3750 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3751 * but the real memory layout is swizzled across
3753 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3755 * Override the buffer descriptor accordingly.
3757 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
3758 uint64_t stream_offset
= 0;
3759 unsigned num_records
= 64;
3760 LLVMValueRef base_ring
;
3763 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3764 LLVMConstInt(ctx
->ac
.i32
,
3765 RING_GSVS_GS
, false));
3767 for (unsigned stream
= 0; stream
< 4; stream
++) {
3768 unsigned num_components
, stride
;
3769 LLVMValueRef ring
, tmp
;
3772 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
3774 if (!num_components
)
3777 stride
= 4 * num_components
* ctx
->gs_max_out_vertices
;
3779 /* Limit on the stride field for <= GFX7. */
3780 assert(stride
< (1 << 14));
3782 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
3783 base_ring
, v2i64
, "");
3784 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3785 ring
, ctx
->ac
.i32_0
, "");
3786 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
3787 LLVMConstInt(ctx
->ac
.i64
,
3788 stream_offset
, 0), "");
3789 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
3790 ring
, tmp
, ctx
->ac
.i32_0
, "");
3792 stream_offset
+= stride
* 64;
3794 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
3797 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
3799 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
3800 LLVMConstInt(ctx
->ac
.i32
,
3801 S_008F04_STRIDE(stride
), false), "");
3802 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
3805 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
3806 LLVMConstInt(ctx
->ac
.i32
,
3807 num_records
, false),
3808 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3810 ctx
->gsvs_ring
[stream
] = ring
;
3814 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3815 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3816 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
3817 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
3822 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
3823 const struct nir_shader
*nir
)
3825 switch (nir
->info
.stage
) {
3826 case MESA_SHADER_TESS_CTRL
:
3827 return chip_class
>= GFX7
? 128 : 64;
3828 case MESA_SHADER_GEOMETRY
:
3829 return chip_class
>= GFX9
? 128 : 64;
3830 case MESA_SHADER_COMPUTE
:
3836 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
3837 nir
->info
.cs
.local_size
[1] *
3838 nir
->info
.cs
.local_size
[2];
3839 return max_workgroup_size
;
3842 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3843 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
3845 LLVMValueRef count
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
3846 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
3848 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
3849 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
3850 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
3853 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
3855 for(int i
= 5; i
>= 0; --i
) {
3856 ctx
->gs_vtx_offset
[i
] = ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
3860 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 16, 8);
3865 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
3866 struct nir_shader
*const *shaders
,
3868 struct radv_shader_variant_info
*shader_info
,
3869 const struct radv_nir_compiler_options
*options
)
3871 struct radv_shader_context ctx
= {0};
3873 ctx
.options
= options
;
3874 ctx
.shader_info
= shader_info
;
3876 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
3877 ctx
.context
= ctx
.ac
.context
;
3878 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
3880 enum ac_float_mode float_mode
=
3881 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
3882 AC_FLOAT_MODE_DEFAULT
;
3884 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
3886 memset(shader_info
, 0, sizeof(*shader_info
));
3888 radv_nir_shader_info_init(&shader_info
->info
);
3890 for(int i
= 0; i
< shader_count
; ++i
)
3891 radv_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
3893 for (i
= 0; i
< RADV_UD_MAX_SETS
; i
++)
3894 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
3895 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
3896 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
3898 ctx
.max_workgroup_size
= 0;
3899 for (int i
= 0; i
< shader_count
; ++i
) {
3900 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
3901 radv_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
3905 if (ctx
.ac
.chip_class
>= GFX10
) {
3906 if (shaders
[0]->info
.stage
== MESA_SHADER_VERTEX
&&
3907 options
->key
.vs
.out
.as_ngg
) {
3908 ctx
.max_workgroup_size
= 128;
3912 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
3913 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
3915 ctx
.abi
.inputs
= &ctx
.inputs
[0];
3916 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
3917 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
3918 ctx
.abi
.load_ubo
= radv_load_ubo
;
3919 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
3920 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
3921 ctx
.abi
.load_resource
= radv_load_resource
;
3922 ctx
.abi
.clamp_shadow_reference
= false;
3923 ctx
.abi
.gfx9_stride_size_workaround
= ctx
.ac
.chip_class
== GFX9
&& HAVE_LLVM
< 0x800;
3925 /* Because the new raw/struct atomic intrinsics are buggy with LLVM 8,
3926 * we fallback to the old intrinsics for atomic buffer image operations
3927 * and thus we need to apply the indexing workaround...
3929 ctx
.abi
.gfx9_stride_size_workaround_for_atomic
= ctx
.ac
.chip_class
== GFX9
&& HAVE_LLVM
< 0x900;
3931 bool is_ngg
= is_pre_gs_stage(shaders
[0]->info
.stage
) && ctx
.options
->key
.vs
.out
.as_ngg
;
3932 if (shader_count
>= 2 || is_ngg
)
3933 ac_init_exec_full_mask(&ctx
.ac
);
3935 if ((ctx
.ac
.family
== CHIP_VEGA10
||
3936 ctx
.ac
.family
== CHIP_RAVEN
) &&
3937 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
3938 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
3940 for(int i
= 0; i
< shader_count
; ++i
) {
3941 ctx
.stage
= shaders
[i
]->info
.stage
;
3942 ctx
.output_mask
= 0;
3944 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3945 for (int i
= 0; i
< 4; i
++) {
3946 ctx
.gs_next_vertex
[i
] =
3947 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
3949 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
3950 ctx
.abi
.load_inputs
= load_gs_input
;
3951 ctx
.abi
.emit_primitive
= visit_end_primitive
;
3952 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3953 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
3954 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
3955 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
3956 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3957 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
3958 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3959 if (shader_count
== 1)
3960 ctx
.tcs_num_inputs
= ctx
.options
->key
.tcs
.num_inputs
;
3962 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->info
.vs
.ls_outputs_written
);
3963 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
3964 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
3965 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
3966 ctx
.abi
.load_tess_varyings
= load_tes_input
;
3967 ctx
.abi
.load_tess_coord
= load_tess_coord
;
3968 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3969 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3970 ctx
.tcs_num_patches
= ctx
.options
->key
.tes
.num_patches
;
3971 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
3972 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
3973 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
3974 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
3975 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
3976 ctx
.abi
.load_sample_position
= load_sample_position
;
3977 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
3978 ctx
.abi
.emit_kill
= radv_emit_kill
;
3982 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
3984 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
3985 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
3987 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3988 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
3989 shaders
[i
]->info
.cull_distance_array_size
> 4;
3990 ctx
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
3991 ctx
.max_gsvs_emit_size
= ctx
.gsvs_vertex_size
*
3992 shaders
[i
]->info
.gs
.vertices_out
;
3995 ac_setup_rings(&ctx
);
3997 LLVMBasicBlockRef merge_block
;
3998 if (shader_count
>= 2 || is_ngg
) {
3999 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
4000 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4001 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4003 LLVMValueRef count
= ac_unpack_param(&ctx
.ac
, ctx
.merged_wave_info
, 8 * i
, 8);
4004 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
4005 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
4006 thread_id
, count
, "");
4007 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
4009 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
4012 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
4013 handle_fs_inputs(&ctx
, shaders
[i
]);
4014 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
4015 handle_vs_inputs(&ctx
, shaders
[i
]);
4016 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
4017 prepare_gs_input_vgprs(&ctx
);
4019 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
4021 if (shader_count
>= 2 || is_ngg
) {
4022 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
4023 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
4026 /* This needs to be outside the if wrapping the shader body, as sometimes
4027 * the HW generates waves with 0 es/vs threads. */
4028 if (is_pre_gs_stage(shaders
[i
]->info
.stage
) &&
4029 ctx
.options
->key
.vs
.out
.as_ngg
&&
4030 i
== shader_count
- 1) {
4031 handle_ngg_outputs_post(&ctx
);
4034 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4035 shader_info
->gs
.gsvs_vertex_size
= ctx
.gsvs_vertex_size
;
4036 shader_info
->gs
.max_gsvs_emit_size
= ctx
.max_gsvs_emit_size
;
4037 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4038 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
4039 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
4043 LLVMBuildRetVoid(ctx
.ac
.builder
);
4045 if (options
->dump_preoptir
)
4046 ac_dump_module(ctx
.ac
.module
);
4048 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
4050 if (shader_count
== 1)
4051 ac_nir_eliminate_const_vs_outputs(&ctx
);
4053 if (options
->dump_shader
) {
4054 ctx
.shader_info
->private_mem_vgprs
=
4055 ac_count_scratch_private_memory(ctx
.main_function
);
4058 return ctx
.ac
.module
;
4061 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
4063 unsigned *retval
= (unsigned *)context
;
4064 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
4065 char *description
= LLVMGetDiagInfoDescription(di
);
4067 if (severity
== LLVMDSError
) {
4069 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
4073 LLVMDisposeMessage(description
);
4076 static unsigned radv_llvm_compile(LLVMModuleRef M
,
4077 char **pelf_buffer
, size_t *pelf_size
,
4078 struct ac_llvm_compiler
*ac_llvm
)
4080 unsigned retval
= 0;
4081 LLVMContextRef llvm_ctx
;
4083 /* Setup Diagnostic Handler*/
4084 llvm_ctx
= LLVMGetModuleContext(M
);
4086 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
4090 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
4095 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
4096 LLVMModuleRef llvm_module
,
4097 struct radv_shader_binary
**rbinary
,
4098 struct radv_shader_variant_info
*shader_info
,
4099 gl_shader_stage stage
,
4100 const struct radv_nir_compiler_options
*options
)
4102 char *elf_buffer
= NULL
;
4103 size_t elf_size
= 0;
4104 char *llvm_ir_string
= NULL
;
4105 if (options
->dump_shader
)
4106 ac_dump_module(llvm_module
);
4108 if (options
->record_llvm_ir
) {
4109 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
4110 llvm_ir_string
= strdup(llvm_ir
);
4111 LLVMDisposeMessage(llvm_ir
);
4114 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
4116 fprintf(stderr
, "compile failed\n");
4119 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
4120 LLVMDisposeModule(llvm_module
);
4121 LLVMContextDispose(ctx
);
4123 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
4124 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
4125 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
4126 memcpy(rbin
->data
, elf_buffer
, elf_size
);
4128 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
4130 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
4131 rbin
->base
.stage
= stage
;
4132 rbin
->base
.total_size
= alloc_size
;
4133 rbin
->elf_size
= elf_size
;
4134 rbin
->llvm_ir_size
= llvm_ir_size
;
4135 *rbinary
= &rbin
->base
;
4137 free(llvm_ir_string
);
4142 ac_fill_shader_info(struct radv_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct radv_nir_compiler_options
*options
)
4144 switch (nir
->info
.stage
) {
4145 case MESA_SHADER_COMPUTE
:
4146 for (int i
= 0; i
< 3; ++i
)
4147 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
4149 case MESA_SHADER_FRAGMENT
:
4150 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
4152 case MESA_SHADER_GEOMETRY
:
4153 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
4154 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
4155 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
4156 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
4158 case MESA_SHADER_TESS_EVAL
:
4159 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
4160 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
4161 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
4162 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
4163 shader_info
->tes
.as_es
= options
->key
.tes
.out
.as_es
;
4164 shader_info
->tes
.export_prim_id
= options
->key
.tes
.out
.export_prim_id
;
4166 case MESA_SHADER_TESS_CTRL
:
4167 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
4169 case MESA_SHADER_VERTEX
:
4170 shader_info
->vs
.as_es
= options
->key
.vs
.out
.as_es
;
4171 shader_info
->vs
.as_ls
= options
->key
.vs
.out
.as_ls
;
4172 shader_info
->vs
.export_prim_id
= options
->key
.vs
.out
.export_prim_id
;
4173 shader_info
->is_ngg
= options
->key
.vs
.out
.as_ngg
;
4181 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
4182 struct radv_shader_binary
**rbinary
,
4183 struct radv_shader_variant_info
*shader_info
,
4184 struct nir_shader
*const *nir
,
4186 const struct radv_nir_compiler_options
*options
)
4189 LLVMModuleRef llvm_module
;
4191 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, shader_info
,
4194 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
, shader_info
,
4195 nir
[nir_count
- 1]->info
.stage
, options
);
4197 for (int i
= 0; i
< nir_count
; ++i
)
4198 ac_fill_shader_info(shader_info
, nir
[i
], options
);
4200 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4201 if (options
->chip_class
== GFX9
) {
4202 if (nir_count
== 2 &&
4203 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4204 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
4210 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
4212 LLVMValueRef vtx_offset
=
4213 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
4214 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4215 LLVMValueRef stream_id
;
4217 /* Fetch the vertex stream ID. */
4218 if (ctx
->shader_info
->info
.so
.num_outputs
) {
4220 ac_unpack_param(&ctx
->ac
, ctx
->streamout_config
, 24, 2);
4222 stream_id
= ctx
->ac
.i32_0
;
4225 LLVMBasicBlockRef end_bb
;
4226 LLVMValueRef switch_inst
;
4228 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
4229 ctx
->main_function
, "end");
4230 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
4232 for (unsigned stream
= 0; stream
< 4; stream
++) {
4233 unsigned num_components
=
4234 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
4235 LLVMBasicBlockRef bb
;
4238 if (!num_components
)
4241 if (stream
> 0 && !ctx
->shader_info
->info
.so
.num_outputs
)
4244 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
4245 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
4246 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
4249 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4250 unsigned output_usage_mask
=
4251 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
4252 unsigned output_stream
=
4253 ctx
->shader_info
->info
.gs
.output_streams
[i
];
4254 int length
= util_last_bit(output_usage_mask
);
4256 if (!(ctx
->output_mask
& (1ull << i
)) ||
4257 output_stream
!= stream
)
4260 for (unsigned j
= 0; j
< length
; j
++) {
4261 LLVMValueRef value
, soffset
;
4263 if (!(output_usage_mask
& (1 << j
)))
4266 soffset
= LLVMConstInt(ctx
->ac
.i32
,
4268 ctx
->gs_max_out_vertices
* 16 * 4, false);
4272 value
= ac_build_buffer_load(&ctx
->ac
,
4275 vtx_offset
, soffset
,
4276 0, ac_glc
| ac_slc
, true, false);
4278 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4279 if (ac_get_type_size(type
) == 2) {
4280 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
4281 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
4284 LLVMBuildStore(ctx
->ac
.builder
,
4285 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4289 if (ctx
->shader_info
->info
.so
.num_outputs
)
4290 radv_emit_streamout(ctx
, stream
);
4293 handle_vs_outputs_post(ctx
, false, false, true,
4294 &ctx
->shader_info
->vs
.outinfo
);
4297 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
4300 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
4304 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
4305 struct nir_shader
*geom_shader
,
4306 struct radv_shader_binary
**rbinary
,
4307 struct radv_shader_variant_info
*shader_info
,
4308 const struct radv_nir_compiler_options
*options
)
4310 struct radv_shader_context ctx
= {0};
4311 ctx
.options
= options
;
4312 ctx
.shader_info
= shader_info
;
4314 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
4315 ctx
.context
= ctx
.ac
.context
;
4316 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
4318 ctx
.is_gs_copy_shader
= true;
4320 enum ac_float_mode float_mode
=
4321 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
4322 AC_FLOAT_MODE_DEFAULT
;
4324 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
4325 ctx
.stage
= MESA_SHADER_VERTEX
;
4327 radv_nir_shader_info_pass(geom_shader
, options
, &shader_info
->info
);
4329 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
4331 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
4332 ac_setup_rings(&ctx
);
4334 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
4335 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
4336 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
4337 variable
, MESA_SHADER_VERTEX
);
4340 ac_gs_copy_shader_emit(&ctx
);
4342 LLVMBuildRetVoid(ctx
.ac
.builder
);
4344 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
4346 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
, shader_info
,
4347 MESA_SHADER_VERTEX
, options
);
4348 (*rbinary
)->is_gs_copy_shader
= true;