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radv: get length of the clip/cull distances array from usage mask
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "nir/nir.h"
32
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #if HAVE_LLVM >= 0x0700
37 #include <llvm-c/Transforms/Utils.h>
38 #endif
39
40 #include "sid.h"
41 #include "gfx9d.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_llvm_build.h"
45 #include "ac_shader_abi.h"
46 #include "ac_shader_util.h"
47 #include "ac_exp_param.h"
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct radv_shader_context {
52 struct ac_llvm_context ac;
53 const struct radv_nir_compiler_options *options;
54 struct radv_shader_variant_info *shader_info;
55 struct ac_shader_abi abi;
56
57 unsigned max_workgroup_size;
58 LLVMContextRef context;
59 LLVMValueRef main_function;
60
61 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
62 LLVMValueRef ring_offsets;
63
64 LLVMValueRef vertex_buffers;
65 LLVMValueRef rel_auto_id;
66 LLVMValueRef vs_prim_id;
67 LLVMValueRef es2gs_offset;
68
69 LLVMValueRef oc_lds;
70 LLVMValueRef merged_wave_info;
71 LLVMValueRef tess_factor_offset;
72 LLVMValueRef tes_rel_patch_id;
73 LLVMValueRef tes_u;
74 LLVMValueRef tes_v;
75
76 LLVMValueRef gs2vs_offset;
77 LLVMValueRef gs_wave_id;
78 LLVMValueRef gs_vtx_offset[6];
79
80 LLVMValueRef esgs_ring;
81 LLVMValueRef gsvs_ring;
82 LLVMValueRef hs_ring_tess_offchip;
83 LLVMValueRef hs_ring_tess_factor;
84
85 LLVMValueRef persp_sample, persp_center, persp_centroid;
86 LLVMValueRef linear_sample, linear_center, linear_centroid;
87
88 gl_shader_stage stage;
89
90 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
91
92 uint64_t input_mask;
93 uint64_t output_mask;
94 uint8_t num_output_clips;
95 uint8_t num_output_culls;
96
97 bool is_gs_copy_shader;
98 LLVMValueRef gs_next_vertex;
99 unsigned gs_max_out_vertices;
100
101 unsigned tes_primitive_mode;
102
103 uint32_t tcs_patch_outputs_read;
104 uint64_t tcs_outputs_read;
105 uint32_t tcs_vertices_per_patch;
106 uint32_t tcs_num_inputs;
107 uint32_t tcs_num_patches;
108 uint32_t max_gsvs_emit_size;
109 uint32_t gsvs_vertex_size;
110 };
111
112 enum radeon_llvm_calling_convention {
113 RADEON_LLVM_AMDGPU_VS = 87,
114 RADEON_LLVM_AMDGPU_GS = 88,
115 RADEON_LLVM_AMDGPU_PS = 89,
116 RADEON_LLVM_AMDGPU_CS = 90,
117 RADEON_LLVM_AMDGPU_HS = 93,
118 };
119
120 static inline struct radv_shader_context *
121 radv_shader_context_from_abi(struct ac_shader_abi *abi)
122 {
123 struct radv_shader_context *ctx = NULL;
124 return container_of(abi, ctx, abi);
125 }
126
127 struct ac_build_if_state
128 {
129 struct radv_shader_context *ctx;
130 LLVMValueRef condition;
131 LLVMBasicBlockRef entry_block;
132 LLVMBasicBlockRef true_block;
133 LLVMBasicBlockRef false_block;
134 LLVMBasicBlockRef merge_block;
135 };
136
137 static LLVMBasicBlockRef
138 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
139 {
140 LLVMBasicBlockRef current_block;
141 LLVMBasicBlockRef next_block;
142 LLVMBasicBlockRef new_block;
143
144 /* get current basic block */
145 current_block = LLVMGetInsertBlock(ctx->ac.builder);
146
147 /* chqeck if there's another block after this one */
148 next_block = LLVMGetNextBasicBlock(current_block);
149 if (next_block) {
150 /* insert the new block before the next block */
151 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
152 }
153 else {
154 /* append new block after current block */
155 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
156 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
157 }
158 return new_block;
159 }
160
161 static void
162 ac_nir_build_if(struct ac_build_if_state *ifthen,
163 struct radv_shader_context *ctx,
164 LLVMValueRef condition)
165 {
166 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
167
168 memset(ifthen, 0, sizeof *ifthen);
169 ifthen->ctx = ctx;
170 ifthen->condition = condition;
171 ifthen->entry_block = block;
172
173 /* create endif/merge basic block for the phi functions */
174 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
175
176 /* create/insert true_block before merge_block */
177 ifthen->true_block =
178 LLVMInsertBasicBlockInContext(ctx->context,
179 ifthen->merge_block,
180 "if-true-block");
181
182 /* successive code goes into the true block */
183 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
184 }
185
186 /**
187 * End a conditional.
188 */
189 static void
190 ac_nir_build_endif(struct ac_build_if_state *ifthen)
191 {
192 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
193
194 /* Insert branch to the merge block from current block */
195 LLVMBuildBr(builder, ifthen->merge_block);
196
197 /*
198 * Now patch in the various branch instructions.
199 */
200
201 /* Insert the conditional branch instruction at the end of entry_block */
202 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
203 if (ifthen->false_block) {
204 /* we have an else clause */
205 LLVMBuildCondBr(builder, ifthen->condition,
206 ifthen->true_block, ifthen->false_block);
207 }
208 else {
209 /* no else clause */
210 LLVMBuildCondBr(builder, ifthen->condition,
211 ifthen->true_block, ifthen->merge_block);
212 }
213
214 /* Resume building code at end of the ifthen->merge_block */
215 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
216 }
217
218
219 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
220 {
221 switch (ctx->stage) {
222 case MESA_SHADER_TESS_CTRL:
223 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
224 case MESA_SHADER_TESS_EVAL:
225 return ctx->tes_rel_patch_id;
226 break;
227 default:
228 unreachable("Illegal stage");
229 }
230 }
231
232 static unsigned
233 get_tcs_num_patches(struct radv_shader_context *ctx)
234 {
235 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
236 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
237 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
238 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
239 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
240 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
241 uint32_t output_vertex_size = num_tcs_outputs * 16;
242 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
243 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
244 unsigned num_patches;
245 unsigned hardware_lds_size;
246
247 /* Ensure that we only need one wave per SIMD so we don't need to check
248 * resource usage. Also ensures that the number of tcs in and out
249 * vertices per threadgroup are at most 256.
250 */
251 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
252 /* Make sure that the data fits in LDS. This assumes the shaders only
253 * use LDS for the inputs and outputs.
254 */
255 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
256 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
257 /* Make sure the output data fits in the offchip buffer */
258 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
259 /* Not necessary for correctness, but improves performance. The
260 * specific value is taken from the proprietary driver.
261 */
262 num_patches = MIN2(num_patches, 40);
263
264 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
265 if (ctx->options->chip_class == SI) {
266 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
267 num_patches = MIN2(num_patches, one_wave);
268 }
269 return num_patches;
270 }
271
272 static unsigned
273 calculate_tess_lds_size(struct radv_shader_context *ctx)
274 {
275 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
276 unsigned num_tcs_output_cp;
277 unsigned num_tcs_outputs, num_tcs_patch_outputs;
278 unsigned input_vertex_size, output_vertex_size;
279 unsigned input_patch_size, output_patch_size;
280 unsigned pervertex_output_patch_size;
281 unsigned output_patch0_offset;
282 unsigned num_patches;
283 unsigned lds_size;
284
285 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
286 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
287 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
288
289 input_vertex_size = ctx->tcs_num_inputs * 16;
290 output_vertex_size = num_tcs_outputs * 16;
291
292 input_patch_size = num_tcs_input_cp * input_vertex_size;
293
294 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
295 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
296
297 num_patches = ctx->tcs_num_patches;
298 output_patch0_offset = input_patch_size * num_patches;
299
300 lds_size = output_patch0_offset + output_patch_size * num_patches;
301 return lds_size;
302 }
303
304 /* Tessellation shaders pass outputs to the next shader using LDS.
305 *
306 * LS outputs = TCS inputs
307 * TCS outputs = TES inputs
308 *
309 * The LDS layout is:
310 * - TCS inputs for patch 0
311 * - TCS inputs for patch 1
312 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
313 * - ...
314 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
315 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
316 * - TCS outputs for patch 1
317 * - Per-patch TCS outputs for patch 1
318 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
319 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
320 * - ...
321 *
322 * All three shaders VS(LS), TCS, TES share the same LDS space.
323 */
324 static LLVMValueRef
325 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
326 {
327 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
328 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
329 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
330
331 input_patch_size /= 4;
332 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
333 }
334
335 static LLVMValueRef
336 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
337 {
338 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
339 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
340 uint32_t output_vertex_size = num_tcs_outputs * 16;
341 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
342 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
343 output_patch_size /= 4;
344 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
345 }
346
347 static LLVMValueRef
348 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
349 {
350 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
351 uint32_t output_vertex_size = num_tcs_outputs * 16;
352 output_vertex_size /= 4;
353 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
354 }
355
356 static LLVMValueRef
357 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
358 {
359 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
360 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
361 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
362 uint32_t output_patch0_offset = input_patch_size;
363 unsigned num_patches = ctx->tcs_num_patches;
364
365 output_patch0_offset *= num_patches;
366 output_patch0_offset /= 4;
367 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
368 }
369
370 static LLVMValueRef
371 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
372 {
373 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
374 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
375 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
376 uint32_t output_patch0_offset = input_patch_size;
377
378 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
379 uint32_t output_vertex_size = num_tcs_outputs * 16;
380 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
381 unsigned num_patches = ctx->tcs_num_patches;
382
383 output_patch0_offset *= num_patches;
384 output_patch0_offset += pervertex_output_patch_size;
385 output_patch0_offset /= 4;
386 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
387 }
388
389 static LLVMValueRef
390 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
391 {
392 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
393 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
394
395 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
396 }
397
398 static LLVMValueRef
399 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
400 {
401 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
402 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
403 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
404
405 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
406 patch0_offset);
407 }
408
409 static LLVMValueRef
410 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
411 {
412 LLVMValueRef patch0_patch_data_offset =
413 get_tcs_out_patch0_patch_data_offset(ctx);
414 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
415 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
416
417 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
418 patch0_patch_data_offset);
419 }
420
421 #define MAX_ARGS 23
422 struct arg_info {
423 LLVMTypeRef types[MAX_ARGS];
424 LLVMValueRef *assign[MAX_ARGS];
425 unsigned array_params_mask;
426 uint8_t count;
427 uint8_t sgpr_count;
428 uint8_t num_sgprs_used;
429 uint8_t num_vgprs_used;
430 };
431
432 enum ac_arg_regfile {
433 ARG_SGPR,
434 ARG_VGPR,
435 };
436
437 static void
438 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
439 LLVMValueRef *param_ptr)
440 {
441 assert(info->count < MAX_ARGS);
442
443 info->assign[info->count] = param_ptr;
444 info->types[info->count] = type;
445 info->count++;
446
447 if (regfile == ARG_SGPR) {
448 info->num_sgprs_used += ac_get_type_size(type) / 4;
449 info->sgpr_count++;
450 } else {
451 assert(regfile == ARG_VGPR);
452 info->num_vgprs_used += ac_get_type_size(type) / 4;
453 }
454 }
455
456 static inline void
457 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
458 {
459 info->array_params_mask |= (1 << info->count);
460 add_arg(info, ARG_SGPR, type, param_ptr);
461 }
462
463 static void assign_arguments(LLVMValueRef main_function,
464 struct arg_info *info)
465 {
466 unsigned i;
467 for (i = 0; i < info->count; i++) {
468 if (info->assign[i])
469 *info->assign[i] = LLVMGetParam(main_function, i);
470 }
471 }
472
473 static LLVMValueRef
474 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
475 LLVMBuilderRef builder, LLVMTypeRef *return_types,
476 unsigned num_return_elems,
477 struct arg_info *args,
478 unsigned max_workgroup_size,
479 const struct radv_nir_compiler_options *options)
480 {
481 LLVMTypeRef main_function_type, ret_type;
482 LLVMBasicBlockRef main_function_body;
483
484 if (num_return_elems)
485 ret_type = LLVMStructTypeInContext(ctx, return_types,
486 num_return_elems, true);
487 else
488 ret_type = LLVMVoidTypeInContext(ctx);
489
490 /* Setup the function */
491 main_function_type =
492 LLVMFunctionType(ret_type, args->types, args->count, 0);
493 LLVMValueRef main_function =
494 LLVMAddFunction(module, "main", main_function_type);
495 main_function_body =
496 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
497 LLVMPositionBuilderAtEnd(builder, main_function_body);
498
499 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
500 for (unsigned i = 0; i < args->sgpr_count; ++i) {
501 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
502
503 if (args->array_params_mask & (1 << i)) {
504 LLVMValueRef P = LLVMGetParam(main_function, i);
505 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
506 ac_add_attr_dereferenceable(P, UINT64_MAX);
507 }
508 }
509
510 if (options->address32_hi) {
511 ac_llvm_add_target_dep_function_attr(main_function,
512 "amdgpu-32bit-address-high-bits",
513 options->address32_hi);
514 }
515
516 if (max_workgroup_size) {
517 ac_llvm_add_target_dep_function_attr(main_function,
518 "amdgpu-max-work-group-size",
519 max_workgroup_size);
520 }
521 if (options->unsafe_math) {
522 /* These were copied from some LLVM test. */
523 LLVMAddTargetDependentFunctionAttr(main_function,
524 "less-precise-fpmad",
525 "true");
526 LLVMAddTargetDependentFunctionAttr(main_function,
527 "no-infs-fp-math",
528 "true");
529 LLVMAddTargetDependentFunctionAttr(main_function,
530 "no-nans-fp-math",
531 "true");
532 LLVMAddTargetDependentFunctionAttr(main_function,
533 "unsafe-fp-math",
534 "true");
535 LLVMAddTargetDependentFunctionAttr(main_function,
536 "no-signed-zeros-fp-math",
537 "true");
538 }
539 return main_function;
540 }
541
542
543 static void
544 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
545 uint32_t indirect_offset)
546 {
547 ud_info->sgpr_idx = *sgpr_idx;
548 ud_info->num_sgprs = num_sgprs;
549 ud_info->indirect = indirect_offset > 0;
550 ud_info->indirect_offset = indirect_offset;
551 *sgpr_idx += num_sgprs;
552 }
553
554 static void
555 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
556 uint8_t num_sgprs)
557 {
558 struct radv_userdata_info *ud_info =
559 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
560 assert(ud_info);
561
562 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
563 }
564
565 static void
566 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
567 {
568 bool use_32bit_pointers = HAVE_32BIT_POINTERS &&
569 idx != AC_UD_SCRATCH_RING_OFFSETS;
570
571 set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
572 }
573
574 static void
575 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
576 uint32_t indirect_offset)
577 {
578 struct radv_userdata_locations *locs =
579 &ctx->shader_info->user_sgprs_locs;
580 struct radv_userdata_info *ud_info = &locs->descriptor_sets[idx];
581 assert(ud_info);
582
583 set_loc(ud_info, sgpr_idx, HAVE_32BIT_POINTERS ? 1 : 2, indirect_offset);
584 if (indirect_offset == 0)
585 locs->descriptor_sets_enabled |= 1 << idx;
586 }
587
588 struct user_sgpr_info {
589 bool need_ring_offsets;
590 bool indirect_all_descriptor_sets;
591 };
592
593 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
594 gl_shader_stage stage)
595 {
596 switch (stage) {
597 case MESA_SHADER_VERTEX:
598 if (ctx->shader_info->info.needs_multiview_view_index ||
599 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
600 return true;
601 break;
602 case MESA_SHADER_TESS_EVAL:
603 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
604 return true;
605 break;
606 case MESA_SHADER_GEOMETRY:
607 case MESA_SHADER_TESS_CTRL:
608 if (ctx->shader_info->info.needs_multiview_view_index)
609 return true;
610 break;
611 default:
612 break;
613 }
614 return false;
615 }
616
617 static uint8_t
618 count_vs_user_sgprs(struct radv_shader_context *ctx)
619 {
620 uint8_t count = 0;
621
622 if (ctx->shader_info->info.vs.has_vertex_buffers)
623 count += HAVE_32BIT_POINTERS ? 1 : 2;
624 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
625
626 return count;
627 }
628
629 static void allocate_user_sgprs(struct radv_shader_context *ctx,
630 gl_shader_stage stage,
631 bool has_previous_stage,
632 gl_shader_stage previous_stage,
633 bool needs_view_index,
634 struct user_sgpr_info *user_sgpr_info)
635 {
636 uint8_t user_sgpr_count = 0;
637
638 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
639
640 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
641 if (stage == MESA_SHADER_GEOMETRY ||
642 stage == MESA_SHADER_VERTEX ||
643 stage == MESA_SHADER_TESS_CTRL ||
644 stage == MESA_SHADER_TESS_EVAL ||
645 ctx->is_gs_copy_shader)
646 user_sgpr_info->need_ring_offsets = true;
647
648 if (stage == MESA_SHADER_FRAGMENT &&
649 ctx->shader_info->info.ps.needs_sample_positions)
650 user_sgpr_info->need_ring_offsets = true;
651
652 /* 2 user sgprs will nearly always be allocated for scratch/rings */
653 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
654 user_sgpr_count += 2;
655 }
656
657 switch (stage) {
658 case MESA_SHADER_COMPUTE:
659 if (ctx->shader_info->info.cs.uses_grid_size)
660 user_sgpr_count += 3;
661 break;
662 case MESA_SHADER_FRAGMENT:
663 user_sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
664 break;
665 case MESA_SHADER_VERTEX:
666 if (!ctx->is_gs_copy_shader)
667 user_sgpr_count += count_vs_user_sgprs(ctx);
668 break;
669 case MESA_SHADER_TESS_CTRL:
670 if (has_previous_stage) {
671 if (previous_stage == MESA_SHADER_VERTEX)
672 user_sgpr_count += count_vs_user_sgprs(ctx);
673 }
674 break;
675 case MESA_SHADER_TESS_EVAL:
676 break;
677 case MESA_SHADER_GEOMETRY:
678 if (has_previous_stage) {
679 if (previous_stage == MESA_SHADER_VERTEX) {
680 user_sgpr_count += count_vs_user_sgprs(ctx);
681 }
682 }
683 break;
684 default:
685 break;
686 }
687
688 if (needs_view_index)
689 user_sgpr_count++;
690
691 if (ctx->shader_info->info.loads_push_constants)
692 user_sgpr_count += HAVE_32BIT_POINTERS ? 1 : 2;
693
694 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
695 uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
696 uint32_t num_desc_set =
697 util_bitcount(ctx->shader_info->info.desc_set_used_mask);
698
699 if (remaining_sgprs / (HAVE_32BIT_POINTERS ? 1 : 2) < num_desc_set) {
700 user_sgpr_info->indirect_all_descriptor_sets = true;
701 }
702 }
703
704 static void
705 declare_global_input_sgprs(struct radv_shader_context *ctx,
706 gl_shader_stage stage,
707 bool has_previous_stage,
708 gl_shader_stage previous_stage,
709 const struct user_sgpr_info *user_sgpr_info,
710 struct arg_info *args,
711 LLVMValueRef *desc_sets)
712 {
713 LLVMTypeRef type = ac_array_in_const32_addr_space(ctx->ac.i8);
714 unsigned num_sets = ctx->options->layout ?
715 ctx->options->layout->num_sets : 0;
716 unsigned stage_mask = 1 << stage;
717
718 if (has_previous_stage)
719 stage_mask |= 1 << previous_stage;
720
721 /* 1 for each descriptor set */
722 if (!user_sgpr_info->indirect_all_descriptor_sets) {
723 for (unsigned i = 0; i < num_sets; ++i) {
724 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
725 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
726 add_array_arg(args, type,
727 &ctx->descriptor_sets[i]);
728 }
729 }
730 } else {
731 add_array_arg(args, ac_array_in_const32_addr_space(type), desc_sets);
732 }
733
734 if (ctx->shader_info->info.loads_push_constants) {
735 /* 1 for push constants and dynamic descriptors */
736 add_array_arg(args, type, &ctx->abi.push_constants);
737 }
738 }
739
740 static void
741 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
742 gl_shader_stage stage,
743 bool has_previous_stage,
744 gl_shader_stage previous_stage,
745 struct arg_info *args)
746 {
747 if (!ctx->is_gs_copy_shader &&
748 (stage == MESA_SHADER_VERTEX ||
749 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
750 if (ctx->shader_info->info.vs.has_vertex_buffers) {
751 add_arg(args, ARG_SGPR,
752 ac_array_in_const32_addr_space(ctx->ac.v4i32),
753 &ctx->vertex_buffers);
754 }
755 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
756 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
757 if (ctx->shader_info->info.vs.needs_draw_id) {
758 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
759 }
760 }
761 }
762
763 static void
764 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
765 {
766 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
767 if (!ctx->is_gs_copy_shader) {
768 if (ctx->options->key.vs.as_ls) {
769 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
770 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
771 } else {
772 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
773 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
774 }
775 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
776 }
777 }
778
779 static void
780 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
781 {
782 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
783 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
784 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
785 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
786 }
787
788 static void
789 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
790 bool has_previous_stage, gl_shader_stage previous_stage,
791 const struct user_sgpr_info *user_sgpr_info,
792 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
793 {
794 unsigned num_sets = ctx->options->layout ?
795 ctx->options->layout->num_sets : 0;
796 unsigned stage_mask = 1 << stage;
797
798 if (has_previous_stage)
799 stage_mask |= 1 << previous_stage;
800
801 if (!user_sgpr_info->indirect_all_descriptor_sets) {
802 for (unsigned i = 0; i < num_sets; ++i) {
803 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
804 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
805 set_loc_desc(ctx, i, user_sgpr_idx, 0);
806 } else
807 ctx->descriptor_sets[i] = NULL;
808 }
809 } else {
810 set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
811 user_sgpr_idx);
812
813 for (unsigned i = 0; i < num_sets; ++i) {
814 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
815 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
816 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
817 ctx->descriptor_sets[i] =
818 ac_build_load_to_sgpr(&ctx->ac,
819 desc_sets,
820 LLVMConstInt(ctx->ac.i32, i, false));
821
822 } else
823 ctx->descriptor_sets[i] = NULL;
824 }
825 ctx->shader_info->need_indirect_descriptor_sets = true;
826 }
827
828 if (ctx->shader_info->info.loads_push_constants) {
829 set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
830 }
831 }
832
833 static void
834 set_vs_specific_input_locs(struct radv_shader_context *ctx,
835 gl_shader_stage stage, bool has_previous_stage,
836 gl_shader_stage previous_stage,
837 uint8_t *user_sgpr_idx)
838 {
839 if (!ctx->is_gs_copy_shader &&
840 (stage == MESA_SHADER_VERTEX ||
841 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
842 if (ctx->shader_info->info.vs.has_vertex_buffers) {
843 set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
844 user_sgpr_idx);
845 }
846
847 unsigned vs_num = 2;
848 if (ctx->shader_info->info.vs.needs_draw_id)
849 vs_num++;
850
851 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
852 user_sgpr_idx, vs_num);
853 }
854 }
855
856 static void set_llvm_calling_convention(LLVMValueRef func,
857 gl_shader_stage stage)
858 {
859 enum radeon_llvm_calling_convention calling_conv;
860
861 switch (stage) {
862 case MESA_SHADER_VERTEX:
863 case MESA_SHADER_TESS_EVAL:
864 calling_conv = RADEON_LLVM_AMDGPU_VS;
865 break;
866 case MESA_SHADER_GEOMETRY:
867 calling_conv = RADEON_LLVM_AMDGPU_GS;
868 break;
869 case MESA_SHADER_TESS_CTRL:
870 calling_conv = RADEON_LLVM_AMDGPU_HS;
871 break;
872 case MESA_SHADER_FRAGMENT:
873 calling_conv = RADEON_LLVM_AMDGPU_PS;
874 break;
875 case MESA_SHADER_COMPUTE:
876 calling_conv = RADEON_LLVM_AMDGPU_CS;
877 break;
878 default:
879 unreachable("Unhandle shader type");
880 }
881
882 LLVMSetFunctionCallConv(func, calling_conv);
883 }
884
885 static void create_function(struct radv_shader_context *ctx,
886 gl_shader_stage stage,
887 bool has_previous_stage,
888 gl_shader_stage previous_stage)
889 {
890 uint8_t user_sgpr_idx;
891 struct user_sgpr_info user_sgpr_info;
892 struct arg_info args = {};
893 LLVMValueRef desc_sets;
894 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
895 allocate_user_sgprs(ctx, stage, has_previous_stage,
896 previous_stage, needs_view_index, &user_sgpr_info);
897
898 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
899 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
900 &ctx->ring_offsets);
901 }
902
903 switch (stage) {
904 case MESA_SHADER_COMPUTE:
905 declare_global_input_sgprs(ctx, stage, has_previous_stage,
906 previous_stage, &user_sgpr_info,
907 &args, &desc_sets);
908
909 if (ctx->shader_info->info.cs.uses_grid_size) {
910 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
911 &ctx->abi.num_work_groups);
912 }
913
914 for (int i = 0; i < 3; i++) {
915 ctx->abi.workgroup_ids[i] = NULL;
916 if (ctx->shader_info->info.cs.uses_block_id[i]) {
917 add_arg(&args, ARG_SGPR, ctx->ac.i32,
918 &ctx->abi.workgroup_ids[i]);
919 }
920 }
921
922 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
923 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
924 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
925 &ctx->abi.local_invocation_ids);
926 break;
927 case MESA_SHADER_VERTEX:
928 declare_global_input_sgprs(ctx, stage, has_previous_stage,
929 previous_stage, &user_sgpr_info,
930 &args, &desc_sets);
931 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
932 previous_stage, &args);
933
934 if (needs_view_index)
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->abi.view_index);
937 if (ctx->options->key.vs.as_es)
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->es2gs_offset);
940
941 declare_vs_input_vgprs(ctx, &args);
942 break;
943 case MESA_SHADER_TESS_CTRL:
944 if (has_previous_stage) {
945 // First 6 system regs
946 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
947 add_arg(&args, ARG_SGPR, ctx->ac.i32,
948 &ctx->merged_wave_info);
949 add_arg(&args, ARG_SGPR, ctx->ac.i32,
950 &ctx->tess_factor_offset);
951
952 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
953 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
954 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
955
956 declare_global_input_sgprs(ctx, stage,
957 has_previous_stage,
958 previous_stage,
959 &user_sgpr_info, &args,
960 &desc_sets);
961 declare_vs_specific_input_sgprs(ctx, stage,
962 has_previous_stage,
963 previous_stage, &args);
964
965 if (needs_view_index)
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->abi.view_index);
968
969 add_arg(&args, ARG_VGPR, ctx->ac.i32,
970 &ctx->abi.tcs_patch_id);
971 add_arg(&args, ARG_VGPR, ctx->ac.i32,
972 &ctx->abi.tcs_rel_ids);
973
974 declare_vs_input_vgprs(ctx, &args);
975 } else {
976 declare_global_input_sgprs(ctx, stage,
977 has_previous_stage,
978 previous_stage,
979 &user_sgpr_info, &args,
980 &desc_sets);
981
982 if (needs_view_index)
983 add_arg(&args, ARG_SGPR, ctx->ac.i32,
984 &ctx->abi.view_index);
985
986 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
987 add_arg(&args, ARG_SGPR, ctx->ac.i32,
988 &ctx->tess_factor_offset);
989 add_arg(&args, ARG_VGPR, ctx->ac.i32,
990 &ctx->abi.tcs_patch_id);
991 add_arg(&args, ARG_VGPR, ctx->ac.i32,
992 &ctx->abi.tcs_rel_ids);
993 }
994 break;
995 case MESA_SHADER_TESS_EVAL:
996 declare_global_input_sgprs(ctx, stage, has_previous_stage,
997 previous_stage, &user_sgpr_info,
998 &args, &desc_sets);
999
1000 if (needs_view_index)
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1002 &ctx->abi.view_index);
1003
1004 if (ctx->options->key.tes.as_es) {
1005 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1007 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1008 &ctx->es2gs_offset);
1009 } else {
1010 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1011 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1012 }
1013 declare_tes_input_vgprs(ctx, &args);
1014 break;
1015 case MESA_SHADER_GEOMETRY:
1016 if (has_previous_stage) {
1017 // First 6 system regs
1018 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1019 &ctx->gs2vs_offset);
1020 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1021 &ctx->merged_wave_info);
1022 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1023
1024 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1025 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1026 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1027
1028 declare_global_input_sgprs(ctx, stage,
1029 has_previous_stage,
1030 previous_stage,
1031 &user_sgpr_info, &args,
1032 &desc_sets);
1033
1034 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1035 declare_vs_specific_input_sgprs(ctx, stage,
1036 has_previous_stage,
1037 previous_stage,
1038 &args);
1039 }
1040
1041 if (needs_view_index)
1042 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1043 &ctx->abi.view_index);
1044
1045 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1046 &ctx->gs_vtx_offset[0]);
1047 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1048 &ctx->gs_vtx_offset[2]);
1049 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1050 &ctx->abi.gs_prim_id);
1051 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1052 &ctx->abi.gs_invocation_id);
1053 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1054 &ctx->gs_vtx_offset[4]);
1055
1056 if (previous_stage == MESA_SHADER_VERTEX) {
1057 declare_vs_input_vgprs(ctx, &args);
1058 } else {
1059 declare_tes_input_vgprs(ctx, &args);
1060 }
1061 } else {
1062 declare_global_input_sgprs(ctx, stage,
1063 has_previous_stage,
1064 previous_stage,
1065 &user_sgpr_info, &args,
1066 &desc_sets);
1067
1068 if (needs_view_index)
1069 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1070 &ctx->abi.view_index);
1071
1072 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1073 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1074 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1075 &ctx->gs_vtx_offset[0]);
1076 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1077 &ctx->gs_vtx_offset[1]);
1078 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1079 &ctx->abi.gs_prim_id);
1080 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1081 &ctx->gs_vtx_offset[2]);
1082 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1083 &ctx->gs_vtx_offset[3]);
1084 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1085 &ctx->gs_vtx_offset[4]);
1086 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1087 &ctx->gs_vtx_offset[5]);
1088 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1089 &ctx->abi.gs_invocation_id);
1090 }
1091 break;
1092 case MESA_SHADER_FRAGMENT:
1093 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1094 previous_stage, &user_sgpr_info,
1095 &args, &desc_sets);
1096
1097 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1098 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1099 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1100 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1101 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1102 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1103 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1104 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1105 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1106 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1107 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1108 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1109 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1110 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1111 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1112 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1113 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1114 break;
1115 default:
1116 unreachable("Shader stage not implemented");
1117 }
1118
1119 ctx->main_function = create_llvm_function(
1120 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1121 ctx->max_workgroup_size, ctx->options);
1122 set_llvm_calling_convention(ctx->main_function, stage);
1123
1124
1125 ctx->shader_info->num_input_vgprs = 0;
1126 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1127
1128 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1129
1130 if (ctx->stage != MESA_SHADER_FRAGMENT)
1131 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1132
1133 assign_arguments(ctx->main_function, &args);
1134
1135 user_sgpr_idx = 0;
1136
1137 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1138 set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1139 &user_sgpr_idx);
1140 if (ctx->options->supports_spill) {
1141 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1142 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1143 NULL, 0, AC_FUNC_ATTR_READNONE);
1144 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1145 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1146 }
1147 }
1148
1149 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1150 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1151 if (has_previous_stage)
1152 user_sgpr_idx = 0;
1153
1154 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1155 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1156
1157 switch (stage) {
1158 case MESA_SHADER_COMPUTE:
1159 if (ctx->shader_info->info.cs.uses_grid_size) {
1160 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1161 &user_sgpr_idx, 3);
1162 }
1163 break;
1164 case MESA_SHADER_VERTEX:
1165 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1166 previous_stage, &user_sgpr_idx);
1167 if (ctx->abi.view_index)
1168 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1169 break;
1170 case MESA_SHADER_TESS_CTRL:
1171 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1172 previous_stage, &user_sgpr_idx);
1173 if (ctx->abi.view_index)
1174 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1175 break;
1176 case MESA_SHADER_TESS_EVAL:
1177 if (ctx->abi.view_index)
1178 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1179 break;
1180 case MESA_SHADER_GEOMETRY:
1181 if (has_previous_stage) {
1182 if (previous_stage == MESA_SHADER_VERTEX)
1183 set_vs_specific_input_locs(ctx, stage,
1184 has_previous_stage,
1185 previous_stage,
1186 &user_sgpr_idx);
1187 }
1188 if (ctx->abi.view_index)
1189 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1190 break;
1191 case MESA_SHADER_FRAGMENT:
1192 break;
1193 default:
1194 unreachable("Shader stage not implemented");
1195 }
1196
1197 if (stage == MESA_SHADER_TESS_CTRL ||
1198 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1199 /* GFX9 has the ESGS ring buffer in LDS. */
1200 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1201 ac_declare_lds_as_pointer(&ctx->ac);
1202 }
1203
1204 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1205 }
1206
1207
1208 static LLVMValueRef
1209 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1210 unsigned desc_set, unsigned binding)
1211 {
1212 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1213 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1214 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1215 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1216 unsigned base_offset = layout->binding[binding].offset;
1217 LLVMValueRef offset, stride;
1218
1219 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1220 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1221 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1222 layout->binding[binding].dynamic_offset_offset;
1223 desc_ptr = ctx->abi.push_constants;
1224 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1225 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1226 } else
1227 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1228
1229 offset = ac_build_imad(&ctx->ac, index, stride,
1230 LLVMConstInt(ctx->ac.i32, base_offset, false));
1231
1232 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1233 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1234 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1235
1236 return desc_ptr;
1237 }
1238
1239
1240 /* The offchip buffer layout for TCS->TES is
1241 *
1242 * - attribute 0 of patch 0 vertex 0
1243 * - attribute 0 of patch 0 vertex 1
1244 * - attribute 0 of patch 0 vertex 2
1245 * ...
1246 * - attribute 0 of patch 1 vertex 0
1247 * - attribute 0 of patch 1 vertex 1
1248 * ...
1249 * - attribute 1 of patch 0 vertex 0
1250 * - attribute 1 of patch 0 vertex 1
1251 * ...
1252 * - per patch attribute 0 of patch 0
1253 * - per patch attribute 0 of patch 1
1254 * ...
1255 *
1256 * Note that every attribute has 4 components.
1257 */
1258 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1259 {
1260 uint32_t num_patches = ctx->tcs_num_patches;
1261 uint32_t num_tcs_outputs;
1262 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1263 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1264 else
1265 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1266
1267 uint32_t output_vertex_size = num_tcs_outputs * 16;
1268 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1269
1270 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1271 }
1272
1273 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1274 LLVMValueRef vertex_index)
1275 {
1276 LLVMValueRef param_stride;
1277 if (vertex_index)
1278 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1279 else
1280 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1281 return param_stride;
1282 }
1283
1284 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1285 LLVMValueRef vertex_index,
1286 LLVMValueRef param_index)
1287 {
1288 LLVMValueRef base_addr;
1289 LLVMValueRef param_stride, constant16;
1290 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1291 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1292 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1293 param_stride = calc_param_stride(ctx, vertex_index);
1294 if (vertex_index) {
1295 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
1296 vertices_per_patch, vertex_index);
1297 } else {
1298 base_addr = rel_patch_id;
1299 }
1300
1301 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1302 LLVMBuildMul(ctx->ac.builder, param_index,
1303 param_stride, ""), "");
1304
1305 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1306
1307 if (!vertex_index) {
1308 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1309
1310 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1311 patch_data_offset, "");
1312 }
1313 return base_addr;
1314 }
1315
1316 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1317 unsigned param,
1318 unsigned const_index,
1319 bool is_compact,
1320 LLVMValueRef vertex_index,
1321 LLVMValueRef indir_index)
1322 {
1323 LLVMValueRef param_index;
1324
1325 if (indir_index)
1326 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1327 indir_index, "");
1328 else {
1329 if (const_index && !is_compact)
1330 param += const_index;
1331 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1332 }
1333 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1334 }
1335
1336 static LLVMValueRef
1337 get_dw_address(struct radv_shader_context *ctx,
1338 LLVMValueRef dw_addr,
1339 unsigned param,
1340 unsigned const_index,
1341 bool compact_const_index,
1342 LLVMValueRef vertex_index,
1343 LLVMValueRef stride,
1344 LLVMValueRef indir_index)
1345
1346 {
1347
1348 if (vertex_index) {
1349 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1350 LLVMBuildMul(ctx->ac.builder,
1351 vertex_index,
1352 stride, ""), "");
1353 }
1354
1355 if (indir_index)
1356 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1357 LLVMBuildMul(ctx->ac.builder, indir_index,
1358 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1359 else if (const_index && !compact_const_index)
1360 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1361 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1362
1363 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1364 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1365
1366 if (const_index && compact_const_index)
1367 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1368 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1369 return dw_addr;
1370 }
1371
1372 static LLVMValueRef
1373 load_tcs_varyings(struct ac_shader_abi *abi,
1374 LLVMTypeRef type,
1375 LLVMValueRef vertex_index,
1376 LLVMValueRef indir_index,
1377 unsigned const_index,
1378 unsigned location,
1379 unsigned driver_location,
1380 unsigned component,
1381 unsigned num_components,
1382 bool is_patch,
1383 bool is_compact,
1384 bool load_input)
1385 {
1386 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1387 LLVMValueRef dw_addr, stride;
1388 LLVMValueRef value[4], result;
1389 unsigned param = shader_io_get_unique_index(location);
1390
1391 if (load_input) {
1392 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1393 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1394 dw_addr = get_tcs_in_current_patch_offset(ctx);
1395 } else {
1396 if (!is_patch) {
1397 stride = get_tcs_out_vertex_stride(ctx);
1398 dw_addr = get_tcs_out_current_patch_offset(ctx);
1399 } else {
1400 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1401 stride = NULL;
1402 }
1403 }
1404
1405 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1406 indir_index);
1407
1408 for (unsigned i = 0; i < num_components + component; i++) {
1409 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1410 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1411 ctx->ac.i32_1, "");
1412 }
1413 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1414 return result;
1415 }
1416
1417 static void
1418 store_tcs_output(struct ac_shader_abi *abi,
1419 const nir_variable *var,
1420 LLVMValueRef vertex_index,
1421 LLVMValueRef param_index,
1422 unsigned const_index,
1423 LLVMValueRef src,
1424 unsigned writemask)
1425 {
1426 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1427 const unsigned location = var->data.location;
1428 const unsigned component = var->data.location_frac;
1429 const bool is_patch = var->data.patch;
1430 const bool is_compact = var->data.compact;
1431 LLVMValueRef dw_addr;
1432 LLVMValueRef stride = NULL;
1433 LLVMValueRef buf_addr = NULL;
1434 unsigned param;
1435 bool store_lds = true;
1436
1437 if (is_patch) {
1438 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1439 store_lds = false;
1440 } else {
1441 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1442 store_lds = false;
1443 }
1444
1445 param = shader_io_get_unique_index(location);
1446 if (location == VARYING_SLOT_CLIP_DIST0 &&
1447 is_compact && const_index > 3) {
1448 const_index -= 3;
1449 param++;
1450 }
1451
1452 if (!is_patch) {
1453 stride = get_tcs_out_vertex_stride(ctx);
1454 dw_addr = get_tcs_out_current_patch_offset(ctx);
1455 } else {
1456 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1457 }
1458
1459 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1460 param_index);
1461 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1462 vertex_index, param_index);
1463
1464 bool is_tess_factor = false;
1465 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1466 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1467 is_tess_factor = true;
1468
1469 unsigned base = is_compact ? const_index : 0;
1470 for (unsigned chan = 0; chan < 8; chan++) {
1471 if (!(writemask & (1 << chan)))
1472 continue;
1473 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1474 value = ac_to_integer(&ctx->ac, value);
1475 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
1476
1477 if (store_lds || is_tess_factor) {
1478 LLVMValueRef dw_addr_chan =
1479 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1480 LLVMConstInt(ctx->ac.i32, chan, false), "");
1481 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1482 }
1483
1484 if (!is_tess_factor && writemask != 0xF)
1485 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1486 buf_addr, ctx->oc_lds,
1487 4 * (base + chan), 1, 0, true, false);
1488 }
1489
1490 if (writemask == 0xF) {
1491 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1492 buf_addr, ctx->oc_lds,
1493 (base * 4), 1, 0, true, false);
1494 }
1495 }
1496
1497 static LLVMValueRef
1498 load_tes_input(struct ac_shader_abi *abi,
1499 LLVMTypeRef type,
1500 LLVMValueRef vertex_index,
1501 LLVMValueRef param_index,
1502 unsigned const_index,
1503 unsigned location,
1504 unsigned driver_location,
1505 unsigned component,
1506 unsigned num_components,
1507 bool is_patch,
1508 bool is_compact,
1509 bool load_input)
1510 {
1511 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1512 LLVMValueRef buf_addr;
1513 LLVMValueRef result;
1514 unsigned param = shader_io_get_unique_index(location);
1515
1516 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1517 const_index -= 3;
1518 param++;
1519 }
1520
1521 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1522 is_compact, vertex_index, param_index);
1523
1524 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1525 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1526
1527 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1528 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1529 result = ac_trim_vector(&ctx->ac, result, num_components);
1530 return result;
1531 }
1532
1533 static LLVMValueRef
1534 load_gs_input(struct ac_shader_abi *abi,
1535 unsigned location,
1536 unsigned driver_location,
1537 unsigned component,
1538 unsigned num_components,
1539 unsigned vertex_index,
1540 unsigned const_index,
1541 LLVMTypeRef type)
1542 {
1543 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1544 LLVMValueRef vtx_offset;
1545 unsigned param, vtx_offset_param;
1546 LLVMValueRef value[4], result;
1547
1548 vtx_offset_param = vertex_index;
1549 assert(vtx_offset_param < 6);
1550 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1551 LLVMConstInt(ctx->ac.i32, 4, false), "");
1552
1553 param = shader_io_get_unique_index(location);
1554
1555 for (unsigned i = component; i < num_components + component; i++) {
1556 if (ctx->ac.chip_class >= GFX9) {
1557 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1558 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1559 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1560 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1561 } else {
1562 LLVMValueRef soffset =
1563 LLVMConstInt(ctx->ac.i32,
1564 (param * 4 + i + const_index) * 256,
1565 false);
1566
1567 value[i] = ac_build_buffer_load(&ctx->ac,
1568 ctx->esgs_ring, 1,
1569 ctx->ac.i32_0,
1570 vtx_offset, soffset,
1571 0, 1, 0, true, false);
1572 }
1573
1574 if (ac_get_type_size(type) == 2) {
1575 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
1576 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
1577 }
1578 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
1579 }
1580 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1581 result = ac_to_integer(&ctx->ac, result);
1582 return result;
1583 }
1584
1585
1586 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1587 {
1588 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1589 ac_build_kill_if_false(&ctx->ac, visible);
1590 }
1591
1592 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1593 enum glsl_interp_mode interp, unsigned location)
1594 {
1595 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1596
1597 switch (interp) {
1598 case INTERP_MODE_FLAT:
1599 default:
1600 return NULL;
1601 case INTERP_MODE_SMOOTH:
1602 case INTERP_MODE_NONE:
1603 if (location == INTERP_CENTER)
1604 return ctx->persp_center;
1605 else if (location == INTERP_CENTROID)
1606 return ctx->persp_centroid;
1607 else if (location == INTERP_SAMPLE)
1608 return ctx->persp_sample;
1609 break;
1610 case INTERP_MODE_NOPERSPECTIVE:
1611 if (location == INTERP_CENTER)
1612 return ctx->linear_center;
1613 else if (location == INTERP_CENTROID)
1614 return ctx->linear_centroid;
1615 else if (location == INTERP_SAMPLE)
1616 return ctx->linear_sample;
1617 break;
1618 }
1619 return NULL;
1620 }
1621
1622 static uint32_t
1623 radv_get_sample_pos_offset(uint32_t num_samples)
1624 {
1625 uint32_t sample_pos_offset = 0;
1626
1627 switch (num_samples) {
1628 case 2:
1629 sample_pos_offset = 1;
1630 break;
1631 case 4:
1632 sample_pos_offset = 3;
1633 break;
1634 case 8:
1635 sample_pos_offset = 7;
1636 break;
1637 case 16:
1638 sample_pos_offset = 15;
1639 break;
1640 default:
1641 break;
1642 }
1643 return sample_pos_offset;
1644 }
1645
1646 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1647 LLVMValueRef sample_id)
1648 {
1649 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1650
1651 LLVMValueRef result;
1652 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1653
1654 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1655 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1656
1657 uint32_t sample_pos_offset =
1658 radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
1659
1660 sample_id =
1661 LLVMBuildAdd(ctx->ac.builder, sample_id,
1662 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
1663 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1664
1665 return result;
1666 }
1667
1668
1669 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1670 {
1671 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1672 uint8_t log2_ps_iter_samples;
1673
1674 if (ctx->shader_info->info.ps.force_persample) {
1675 log2_ps_iter_samples =
1676 util_logbase2(ctx->options->key.fs.num_samples);
1677 } else {
1678 log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
1679 }
1680
1681 /* The bit pattern matches that used by fixed function fragment
1682 * processing. */
1683 static const uint16_t ps_iter_masks[] = {
1684 0xffff, /* not used */
1685 0x5555,
1686 0x1111,
1687 0x0101,
1688 0x0001,
1689 };
1690 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1691
1692 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1693
1694 LLVMValueRef result, sample_id;
1695 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1696 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1697 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1698 return result;
1699 }
1700
1701
1702 static void
1703 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1704 {
1705 LLVMValueRef gs_next_vertex;
1706 LLVMValueRef can_emit;
1707 int idx;
1708 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1709
1710 assert(stream == 0);
1711
1712 /* Write vertex attribute values to GSVS ring */
1713 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1714 ctx->gs_next_vertex,
1715 "");
1716
1717 /* If this thread has already emitted the declared maximum number of
1718 * vertices, kill it: excessive vertex emissions are not supposed to
1719 * have any effect, and GS threads have no externally observable
1720 * effects other than emitting vertices.
1721 */
1722 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1723 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1724 ac_build_kill_if_false(&ctx->ac, can_emit);
1725
1726 /* loop num outputs */
1727 idx = 0;
1728 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1729 unsigned output_usage_mask =
1730 ctx->shader_info->info.gs.output_usage_mask[i];
1731 LLVMValueRef *out_ptr = &addrs[i * 4];
1732 int length = 4;
1733 int slot = idx;
1734 int slot_inc = 1;
1735
1736 if (!(ctx->output_mask & (1ull << i)))
1737 continue;
1738
1739 if (i == VARYING_SLOT_CLIP_DIST0) {
1740 /* pack clip and cull into a single set of slots */
1741 length = util_last_bit(output_usage_mask);
1742 if (length > 4)
1743 slot_inc = 2;
1744 }
1745
1746 for (unsigned j = 0; j < length; j++) {
1747 if (!(output_usage_mask & (1 << j)))
1748 continue;
1749
1750 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1751 out_ptr[j], "");
1752 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1753 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1754 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1755
1756 out_val = ac_to_integer(&ctx->ac, out_val);
1757 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1758
1759 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1760 out_val, 1,
1761 voffset, ctx->gs2vs_offset, 0,
1762 1, 1, true, true);
1763 }
1764 idx += slot_inc;
1765 }
1766
1767 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1768 ctx->ac.i32_1, "");
1769 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1770
1771 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1772 }
1773
1774 static void
1775 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1776 {
1777 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1778 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1779 }
1780
1781 static LLVMValueRef
1782 load_tess_coord(struct ac_shader_abi *abi)
1783 {
1784 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1785
1786 LLVMValueRef coord[4] = {
1787 ctx->tes_u,
1788 ctx->tes_v,
1789 ctx->ac.f32_0,
1790 ctx->ac.f32_0,
1791 };
1792
1793 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1794 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1795 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1796
1797 return ac_build_gather_values(&ctx->ac, coord, 3);
1798 }
1799
1800 static LLVMValueRef
1801 load_patch_vertices_in(struct ac_shader_abi *abi)
1802 {
1803 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1804 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1805 }
1806
1807
1808 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1809 {
1810 return abi->base_vertex;
1811 }
1812
1813 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1814 LLVMValueRef buffer_ptr, bool write)
1815 {
1816 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1817 LLVMValueRef result;
1818
1819 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1820
1821 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1822 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1823
1824 return result;
1825 }
1826
1827 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1828 {
1829 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1830 LLVMValueRef result;
1831
1832 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1833
1834 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1835 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1836
1837 return result;
1838 }
1839
1840 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1841 unsigned descriptor_set,
1842 unsigned base_index,
1843 unsigned constant_index,
1844 LLVMValueRef index,
1845 enum ac_descriptor_type desc_type,
1846 bool image, bool write,
1847 bool bindless)
1848 {
1849 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1850 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1851 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1852 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1853 unsigned offset = binding->offset;
1854 unsigned stride = binding->size;
1855 unsigned type_size;
1856 LLVMBuilderRef builder = ctx->ac.builder;
1857 LLVMTypeRef type;
1858
1859 assert(base_index < layout->binding_count);
1860
1861 switch (desc_type) {
1862 case AC_DESC_IMAGE:
1863 type = ctx->ac.v8i32;
1864 type_size = 32;
1865 break;
1866 case AC_DESC_FMASK:
1867 type = ctx->ac.v8i32;
1868 offset += 32;
1869 type_size = 32;
1870 break;
1871 case AC_DESC_SAMPLER:
1872 type = ctx->ac.v4i32;
1873 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1874 offset += 64;
1875
1876 type_size = 16;
1877 break;
1878 case AC_DESC_BUFFER:
1879 type = ctx->ac.v4i32;
1880 type_size = 16;
1881 break;
1882 default:
1883 unreachable("invalid desc_type\n");
1884 }
1885
1886 offset += constant_index * stride;
1887
1888 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1889 (!index || binding->immutable_samplers_equal)) {
1890 if (binding->immutable_samplers_equal)
1891 constant_index = 0;
1892
1893 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1894
1895 LLVMValueRef constants[] = {
1896 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1897 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1898 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1899 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1900 };
1901 return ac_build_gather_values(&ctx->ac, constants, 4);
1902 }
1903
1904 assert(stride % type_size == 0);
1905
1906 if (!index)
1907 index = ctx->ac.i32_0;
1908
1909 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1910
1911 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1912 list = LLVMBuildPointerCast(builder, list,
1913 ac_array_in_const32_addr_space(type), "");
1914
1915 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1916 }
1917
1918 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1919 * so we may need to fix it up. */
1920 static LLVMValueRef
1921 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1922 unsigned adjustment,
1923 LLVMValueRef alpha)
1924 {
1925 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1926 return alpha;
1927
1928 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1929
1930 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1931 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1932 else
1933 alpha = ac_to_integer(&ctx->ac, alpha);
1934
1935 /* For the integer-like cases, do a natural sign extension.
1936 *
1937 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1938 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1939 * exponent.
1940 */
1941 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1942 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1943 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1944 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1945
1946 /* Convert back to the right type. */
1947 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1948 LLVMValueRef clamp;
1949 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1950 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1951 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1952 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1953 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1954 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1955 }
1956
1957 return alpha;
1958 }
1959
1960 static void
1961 handle_vs_input_decl(struct radv_shader_context *ctx,
1962 struct nir_variable *variable)
1963 {
1964 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1965 LLVMValueRef t_offset;
1966 LLVMValueRef t_list;
1967 LLVMValueRef input;
1968 LLVMValueRef buffer_index;
1969 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1970 uint8_t input_usage_mask =
1971 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1972 unsigned num_channels = util_last_bit(input_usage_mask);
1973
1974 variable->data.driver_location = variable->data.location * 4;
1975
1976 enum glsl_base_type type = glsl_get_base_type(variable->type);
1977 for (unsigned i = 0; i < attrib_count; ++i) {
1978 LLVMValueRef output[4];
1979 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1980
1981 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1982 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
1983
1984 if (divisor) {
1985 buffer_index = ctx->abi.instance_id;
1986
1987 if (divisor != 1) {
1988 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1989 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1990 }
1991
1992 if (ctx->options->key.vs.as_ls) {
1993 ctx->shader_info->vs.vgpr_comp_cnt =
1994 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1995 } else {
1996 ctx->shader_info->vs.vgpr_comp_cnt =
1997 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1998 }
1999 } else {
2000 buffer_index = ctx->ac.i32_0;
2001 }
2002
2003 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index, "");
2004 } else
2005 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
2006 ctx->abi.base_vertex, "");
2007 t_offset = LLVMConstInt(ctx->ac.i32, attrib_index, false);
2008
2009 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
2010
2011 input = ac_build_buffer_load_format(&ctx->ac, t_list,
2012 buffer_index,
2013 ctx->ac.i32_0,
2014 num_channels, false, true);
2015
2016 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
2017
2018 for (unsigned chan = 0; chan < 4; chan++) {
2019 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2020 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
2021 if (type == GLSL_TYPE_FLOAT16) {
2022 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
2023 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
2024 }
2025 }
2026
2027 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
2028 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
2029
2030 for (unsigned chan = 0; chan < 4; chan++) {
2031 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
2032 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
2033 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
2034
2035 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
2036 }
2037 }
2038 }
2039
2040 static void interp_fs_input(struct radv_shader_context *ctx,
2041 unsigned attr,
2042 LLVMValueRef interp_param,
2043 LLVMValueRef prim_mask,
2044 LLVMValueRef result[4])
2045 {
2046 LLVMValueRef attr_number;
2047 unsigned chan;
2048 LLVMValueRef i, j;
2049 bool interp = !LLVMIsUndef(interp_param);
2050
2051 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
2052
2053 /* fs.constant returns the param from the middle vertex, so it's not
2054 * really useful for flat shading. It's meant to be used for custom
2055 * interpolation (but the intrinsic can't fetch from the other two
2056 * vertices).
2057 *
2058 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2059 * to do the right thing. The only reason we use fs.constant is that
2060 * fs.interp cannot be used on integers, because they can be equal
2061 * to NaN.
2062 */
2063 if (interp) {
2064 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
2065 ctx->ac.v2f32, "");
2066
2067 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2068 ctx->ac.i32_0, "");
2069 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2070 ctx->ac.i32_1, "");
2071 }
2072
2073 for (chan = 0; chan < 4; chan++) {
2074 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2075
2076 if (interp) {
2077 result[chan] = ac_build_fs_interp(&ctx->ac,
2078 llvm_chan,
2079 attr_number,
2080 prim_mask, i, j);
2081 } else {
2082 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2083 LLVMConstInt(ctx->ac.i32, 2, false),
2084 llvm_chan,
2085 attr_number,
2086 prim_mask);
2087 result[chan] = LLVMBuildBitCast(ctx->ac.builder, result[chan], ctx->ac.i32, "");
2088 result[chan] = LLVMBuildTruncOrBitCast(ctx->ac.builder, result[chan], LLVMTypeOf(interp_param), "");
2089 }
2090 }
2091 }
2092
2093 static void
2094 handle_fs_input_decl(struct radv_shader_context *ctx,
2095 struct nir_variable *variable)
2096 {
2097 int idx = variable->data.location;
2098 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2099 LLVMValueRef interp = NULL;
2100 uint64_t mask;
2101
2102 variable->data.driver_location = idx * 4;
2103 mask = ((1ull << attrib_count) - 1) << variable->data.location;
2104
2105 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
2106 unsigned interp_type;
2107 if (variable->data.sample)
2108 interp_type = INTERP_SAMPLE;
2109 else if (variable->data.centroid)
2110 interp_type = INTERP_CENTROID;
2111 else
2112 interp_type = INTERP_CENTER;
2113
2114 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
2115 }
2116 bool is_16bit = glsl_type_is_16bit(variable->type);
2117 LLVMTypeRef type = is_16bit ? ctx->ac.i16 : ctx->ac.i32;
2118 if (interp == NULL)
2119 interp = LLVMGetUndef(type);
2120
2121 for (unsigned i = 0; i < attrib_count; ++i)
2122 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
2123
2124 if (idx == VARYING_SLOT_CLIP_DIST0) {
2125 /* Do not account for the number of components inside the array
2126 * of clip/cull distances because this might wrongly set other
2127 * bits like primitive ID or layer.
2128 */
2129 mask = 1ull << VARYING_SLOT_CLIP_DIST0;
2130 }
2131
2132 ctx->input_mask |= mask;
2133 }
2134
2135 static void
2136 handle_vs_inputs(struct radv_shader_context *ctx,
2137 struct nir_shader *nir) {
2138 nir_foreach_variable(variable, &nir->inputs)
2139 handle_vs_input_decl(ctx, variable);
2140 }
2141
2142 static void
2143 prepare_interp_optimize(struct radv_shader_context *ctx,
2144 struct nir_shader *nir)
2145 {
2146 bool uses_center = false;
2147 bool uses_centroid = false;
2148 nir_foreach_variable(variable, &nir->inputs) {
2149 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2150 variable->data.sample)
2151 continue;
2152
2153 if (variable->data.centroid)
2154 uses_centroid = true;
2155 else
2156 uses_center = true;
2157 }
2158
2159 if (uses_center && uses_centroid) {
2160 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2161 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
2162 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
2163 }
2164 }
2165
2166 static void
2167 handle_fs_inputs(struct radv_shader_context *ctx,
2168 struct nir_shader *nir)
2169 {
2170 prepare_interp_optimize(ctx, nir);
2171
2172 nir_foreach_variable(variable, &nir->inputs)
2173 handle_fs_input_decl(ctx, variable);
2174
2175 unsigned index = 0;
2176
2177 if (ctx->shader_info->info.ps.uses_input_attachments ||
2178 ctx->shader_info->info.needs_multiview_view_index) {
2179 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
2180 ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)] = LLVMGetUndef(ctx->ac.i32);
2181 }
2182
2183 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
2184 LLVMValueRef interp_param;
2185 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
2186
2187 if (!(ctx->input_mask & (1ull << i)))
2188 continue;
2189
2190 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
2191 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
2192 interp_param = *inputs;
2193 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
2194 inputs);
2195
2196 if (LLVMIsUndef(interp_param))
2197 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
2198 ++index;
2199 } else if (i == VARYING_SLOT_CLIP_DIST0) {
2200 int length = ctx->shader_info->info.ps.num_input_clips_culls;
2201
2202 for (unsigned j = 0; j < length; j += 4) {
2203 inputs = ctx->inputs + ac_llvm_reg_index_soa(i, j);
2204
2205 interp_param = *inputs;
2206 interp_fs_input(ctx, index, interp_param,
2207 ctx->abi.prim_mask, inputs);
2208 ++index;
2209 }
2210 } else if (i == VARYING_SLOT_POS) {
2211 for(int i = 0; i < 3; ++i)
2212 inputs[i] = ctx->abi.frag_pos[i];
2213
2214 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2215 ctx->abi.frag_pos[3]);
2216 }
2217 }
2218 ctx->shader_info->fs.num_interp = index;
2219 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
2220
2221 if (ctx->shader_info->info.needs_multiview_view_index)
2222 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2223 }
2224
2225 static void
2226 scan_shader_output_decl(struct radv_shader_context *ctx,
2227 struct nir_variable *variable,
2228 struct nir_shader *shader,
2229 gl_shader_stage stage)
2230 {
2231 int idx = variable->data.location + variable->data.index;
2232 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2233 uint64_t mask_attribs;
2234
2235 variable->data.driver_location = idx * 4;
2236
2237 /* tess ctrl has it's own load/store paths for outputs */
2238 if (stage == MESA_SHADER_TESS_CTRL)
2239 return;
2240
2241 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2242 if (stage == MESA_SHADER_VERTEX ||
2243 stage == MESA_SHADER_TESS_EVAL ||
2244 stage == MESA_SHADER_GEOMETRY) {
2245 if (idx == VARYING_SLOT_CLIP_DIST0) {
2246 int length = shader->info.clip_distance_array_size +
2247 shader->info.cull_distance_array_size;
2248 if (stage == MESA_SHADER_VERTEX) {
2249 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2250 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2251 }
2252 if (stage == MESA_SHADER_TESS_EVAL) {
2253 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2254 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2255 }
2256
2257 if (length > 4)
2258 attrib_count = 2;
2259 else
2260 attrib_count = 1;
2261 mask_attribs = 1ull << idx;
2262 }
2263 }
2264
2265 ctx->output_mask |= mask_attribs;
2266 }
2267
2268
2269 /* Initialize arguments for the shader export intrinsic */
2270 static void
2271 si_llvm_init_export_args(struct radv_shader_context *ctx,
2272 LLVMValueRef *values,
2273 unsigned enabled_channels,
2274 unsigned target,
2275 struct ac_export_args *args)
2276 {
2277 /* Specify the channels that are enabled. */
2278 args->enabled_channels = enabled_channels;
2279
2280 /* Specify whether the EXEC mask represents the valid mask */
2281 args->valid_mask = 0;
2282
2283 /* Specify whether this is the last export */
2284 args->done = 0;
2285
2286 /* Specify the target we are exporting */
2287 args->target = target;
2288
2289 args->compr = false;
2290 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2291 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2292 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2293 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2294
2295 if (!values)
2296 return;
2297
2298 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
2299 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2300 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2301 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2302 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2303 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2304 unsigned chan;
2305
2306 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2307 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2308 unsigned bits, bool hi) = NULL;
2309
2310 switch(col_format) {
2311 case V_028714_SPI_SHADER_ZERO:
2312 args->enabled_channels = 0; /* writemask */
2313 args->target = V_008DFC_SQ_EXP_NULL;
2314 break;
2315
2316 case V_028714_SPI_SHADER_32_R:
2317 args->enabled_channels = 1;
2318 args->out[0] = values[0];
2319 break;
2320
2321 case V_028714_SPI_SHADER_32_GR:
2322 args->enabled_channels = 0x3;
2323 args->out[0] = values[0];
2324 args->out[1] = values[1];
2325 break;
2326
2327 case V_028714_SPI_SHADER_32_AR:
2328 args->enabled_channels = 0x9;
2329 args->out[0] = values[0];
2330 args->out[3] = values[3];
2331 break;
2332
2333 case V_028714_SPI_SHADER_FP16_ABGR:
2334 args->enabled_channels = 0x5;
2335 packf = ac_build_cvt_pkrtz_f16;
2336 if (is_16bit) {
2337 for (unsigned chan = 0; chan < 4; chan++)
2338 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
2339 values[chan],
2340 ctx->ac.f32, "");
2341 }
2342 break;
2343
2344 case V_028714_SPI_SHADER_UNORM16_ABGR:
2345 args->enabled_channels = 0x5;
2346 packf = ac_build_cvt_pknorm_u16;
2347 break;
2348
2349 case V_028714_SPI_SHADER_SNORM16_ABGR:
2350 args->enabled_channels = 0x5;
2351 packf = ac_build_cvt_pknorm_i16;
2352 break;
2353
2354 case V_028714_SPI_SHADER_UINT16_ABGR:
2355 args->enabled_channels = 0x5;
2356 packi = ac_build_cvt_pk_u16;
2357 if (is_16bit) {
2358 for (unsigned chan = 0; chan < 4; chan++)
2359 values[chan] = LLVMBuildZExt(ctx->ac.builder,
2360 values[chan],
2361 ctx->ac.i32, "");
2362 }
2363 break;
2364
2365 case V_028714_SPI_SHADER_SINT16_ABGR:
2366 args->enabled_channels = 0x5;
2367 packi = ac_build_cvt_pk_i16;
2368 if (is_16bit) {
2369 for (unsigned chan = 0; chan < 4; chan++)
2370 values[chan] = LLVMBuildSExt(ctx->ac.builder,
2371 values[chan],
2372 ctx->ac.i32, "");
2373 }
2374 break;
2375
2376 default:
2377 case V_028714_SPI_SHADER_32_ABGR:
2378 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2379 break;
2380 }
2381
2382 /* Pack f16 or norm_i16/u16. */
2383 if (packf) {
2384 for (chan = 0; chan < 2; chan++) {
2385 LLVMValueRef pack_args[2] = {
2386 values[2 * chan],
2387 values[2 * chan + 1]
2388 };
2389 LLVMValueRef packed;
2390
2391 packed = packf(&ctx->ac, pack_args);
2392 args->out[chan] = ac_to_float(&ctx->ac, packed);
2393 }
2394 args->compr = 1; /* COMPR flag */
2395 }
2396
2397 /* Pack i16/u16. */
2398 if (packi) {
2399 for (chan = 0; chan < 2; chan++) {
2400 LLVMValueRef pack_args[2] = {
2401 ac_to_integer(&ctx->ac, values[2 * chan]),
2402 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2403 };
2404 LLVMValueRef packed;
2405
2406 packed = packi(&ctx->ac, pack_args,
2407 is_int8 ? 8 : is_int10 ? 10 : 16,
2408 chan == 1);
2409 args->out[chan] = ac_to_float(&ctx->ac, packed);
2410 }
2411 args->compr = 1; /* COMPR flag */
2412 }
2413 return;
2414 }
2415
2416 if (is_16bit) {
2417 for (unsigned chan = 0; chan < 4; chan++) {
2418 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
2419 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
2420 }
2421 } else
2422 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2423
2424 for (unsigned i = 0; i < 4; ++i) {
2425 if (!(args->enabled_channels & (1 << i)))
2426 continue;
2427
2428 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2429 }
2430 }
2431
2432 static void
2433 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2434 LLVMValueRef *values, unsigned enabled_channels)
2435 {
2436 struct ac_export_args args;
2437
2438 si_llvm_init_export_args(ctx, values, enabled_channels,
2439 V_008DFC_SQ_EXP_PARAM + index, &args);
2440 ac_build_export(&ctx->ac, &args);
2441 }
2442
2443 static LLVMValueRef
2444 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2445 {
2446 LLVMValueRef output =
2447 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2448
2449 return LLVMBuildLoad(ctx->ac.builder, output, "");
2450 }
2451
2452 static void
2453 handle_vs_outputs_post(struct radv_shader_context *ctx,
2454 bool export_prim_id, bool export_layer_id,
2455 struct radv_vs_output_info *outinfo)
2456 {
2457 uint32_t param_count = 0;
2458 unsigned target;
2459 unsigned pos_idx, num_pos_exports = 0;
2460 struct ac_export_args args, pos_args[4] = {};
2461 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2462 int i;
2463
2464 if (ctx->options->key.has_multiview_view_index) {
2465 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2466 if(!*tmp_out) {
2467 for(unsigned i = 0; i < 4; ++i)
2468 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2469 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2470 }
2471
2472 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2473 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2474 }
2475
2476 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2477 sizeof(outinfo->vs_output_param_offset));
2478
2479 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2480 unsigned output_usage_mask, length;
2481 LLVMValueRef slots[8];
2482 unsigned j;
2483
2484 if (ctx->stage == MESA_SHADER_VERTEX &&
2485 !ctx->is_gs_copy_shader) {
2486 output_usage_mask =
2487 ctx->shader_info->info.vs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2488 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2489 output_usage_mask =
2490 ctx->shader_info->info.tes.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2491 } else {
2492 assert(ctx->is_gs_copy_shader);
2493 output_usage_mask =
2494 ctx->shader_info->info.gs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2495 }
2496
2497 length = util_last_bit(output_usage_mask);
2498
2499 if (outinfo->cull_dist_mask)
2500 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2501
2502 i = VARYING_SLOT_CLIP_DIST0;
2503 for (j = 0; j < length; j++)
2504 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2505
2506 for (i = length; i < 8; i++)
2507 slots[i] = LLVMGetUndef(ctx->ac.f32);
2508
2509 if (length > 4) {
2510 target = V_008DFC_SQ_EXP_POS + 3;
2511 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2512 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2513 &args, sizeof(args));
2514 }
2515
2516 target = V_008DFC_SQ_EXP_POS + 2;
2517 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2518 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2519 &args, sizeof(args));
2520
2521 /* Export the clip/cull distances values to the next stage. */
2522 radv_export_param(ctx, param_count, &slots[0], 0xf);
2523 outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0] = param_count++;
2524 if (length > 4) {
2525 radv_export_param(ctx, param_count, &slots[4], 0xf);
2526 outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1] = param_count++;
2527 }
2528 }
2529
2530 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2531 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2532 for (unsigned j = 0; j < 4; j++)
2533 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2534 }
2535 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2536
2537 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2538 outinfo->writes_pointsize = true;
2539 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2540 }
2541
2542 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2543 outinfo->writes_layer = true;
2544 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2545 }
2546
2547 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2548 outinfo->writes_viewport_index = true;
2549 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2550 }
2551
2552 if (outinfo->writes_pointsize ||
2553 outinfo->writes_layer ||
2554 outinfo->writes_viewport_index) {
2555 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2556 (outinfo->writes_layer == true ? 4 : 0));
2557 pos_args[1].valid_mask = 0;
2558 pos_args[1].done = 0;
2559 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2560 pos_args[1].compr = 0;
2561 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2562 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2563 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2564 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2565
2566 if (outinfo->writes_pointsize == true)
2567 pos_args[1].out[0] = psize_value;
2568 if (outinfo->writes_layer == true)
2569 pos_args[1].out[2] = layer_value;
2570 if (outinfo->writes_viewport_index == true) {
2571 if (ctx->options->chip_class >= GFX9) {
2572 /* GFX9 has the layer in out.z[10:0] and the viewport
2573 * index in out.z[19:16].
2574 */
2575 LLVMValueRef v = viewport_index_value;
2576 v = ac_to_integer(&ctx->ac, v);
2577 v = LLVMBuildShl(ctx->ac.builder, v,
2578 LLVMConstInt(ctx->ac.i32, 16, false),
2579 "");
2580 v = LLVMBuildOr(ctx->ac.builder, v,
2581 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2582
2583 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2584 pos_args[1].enabled_channels |= 1 << 2;
2585 } else {
2586 pos_args[1].out[3] = viewport_index_value;
2587 pos_args[1].enabled_channels |= 1 << 3;
2588 }
2589 }
2590 }
2591 for (i = 0; i < 4; i++) {
2592 if (pos_args[i].out[0])
2593 num_pos_exports++;
2594 }
2595
2596 pos_idx = 0;
2597 for (i = 0; i < 4; i++) {
2598 if (!pos_args[i].out[0])
2599 continue;
2600
2601 /* Specify the target we are exporting */
2602 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2603 if (pos_idx == num_pos_exports)
2604 pos_args[i].done = 1;
2605 ac_build_export(&ctx->ac, &pos_args[i]);
2606 }
2607
2608 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2609 LLVMValueRef values[4];
2610 if (!(ctx->output_mask & (1ull << i)))
2611 continue;
2612
2613 if (i != VARYING_SLOT_LAYER &&
2614 i != VARYING_SLOT_PRIMITIVE_ID &&
2615 i < VARYING_SLOT_VAR0)
2616 continue;
2617
2618 for (unsigned j = 0; j < 4; j++)
2619 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2620
2621 unsigned output_usage_mask;
2622
2623 if (ctx->stage == MESA_SHADER_VERTEX &&
2624 !ctx->is_gs_copy_shader) {
2625 output_usage_mask =
2626 ctx->shader_info->info.vs.output_usage_mask[i];
2627 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2628 output_usage_mask =
2629 ctx->shader_info->info.tes.output_usage_mask[i];
2630 } else {
2631 assert(ctx->is_gs_copy_shader);
2632 output_usage_mask =
2633 ctx->shader_info->info.gs.output_usage_mask[i];
2634 }
2635
2636 radv_export_param(ctx, param_count, values, output_usage_mask);
2637
2638 outinfo->vs_output_param_offset[i] = param_count++;
2639 }
2640
2641 if (export_prim_id) {
2642 LLVMValueRef values[4];
2643
2644 values[0] = ctx->vs_prim_id;
2645 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2646 ctx->shader_info->vs.vgpr_comp_cnt);
2647 for (unsigned j = 1; j < 4; j++)
2648 values[j] = ctx->ac.f32_0;
2649
2650 radv_export_param(ctx, param_count, values, 0x1);
2651
2652 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2653 outinfo->export_prim_id = true;
2654 }
2655
2656 if (export_layer_id && layer_value) {
2657 LLVMValueRef values[4];
2658
2659 values[0] = layer_value;
2660 for (unsigned j = 1; j < 4; j++)
2661 values[j] = ctx->ac.f32_0;
2662
2663 radv_export_param(ctx, param_count, values, 0x1);
2664
2665 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2666 }
2667
2668 outinfo->pos_exports = num_pos_exports;
2669 outinfo->param_exports = param_count;
2670 }
2671
2672 static void
2673 handle_es_outputs_post(struct radv_shader_context *ctx,
2674 struct radv_es_output_info *outinfo)
2675 {
2676 int j;
2677 uint64_t max_output_written = 0;
2678 LLVMValueRef lds_base = NULL;
2679
2680 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2681 unsigned output_usage_mask;
2682 int param_index;
2683 int length = 4;
2684
2685 if (!(ctx->output_mask & (1ull << i)))
2686 continue;
2687
2688 if (ctx->stage == MESA_SHADER_VERTEX) {
2689 output_usage_mask =
2690 ctx->shader_info->info.vs.output_usage_mask[i];
2691 } else {
2692 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2693 output_usage_mask =
2694 ctx->shader_info->info.tes.output_usage_mask[i];
2695 }
2696
2697 if (i == VARYING_SLOT_CLIP_DIST0)
2698 length = util_last_bit(output_usage_mask);
2699
2700 param_index = shader_io_get_unique_index(i);
2701
2702 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2703 }
2704
2705 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2706
2707 if (ctx->ac.chip_class >= GFX9) {
2708 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2709 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2710 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2711 LLVMConstInt(ctx->ac.i32, 24, false),
2712 LLVMConstInt(ctx->ac.i32, 4, false), false);
2713 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2714 LLVMBuildMul(ctx->ac.builder, wave_idx,
2715 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2716 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2717 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2718 }
2719
2720 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2721 LLVMValueRef dw_addr = NULL;
2722 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2723 unsigned output_usage_mask;
2724 int param_index;
2725 int length = 4;
2726
2727 if (!(ctx->output_mask & (1ull << i)))
2728 continue;
2729
2730 if (ctx->stage == MESA_SHADER_VERTEX) {
2731 output_usage_mask =
2732 ctx->shader_info->info.vs.output_usage_mask[i];
2733 } else {
2734 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2735 output_usage_mask =
2736 ctx->shader_info->info.tes.output_usage_mask[i];
2737 }
2738
2739 if (i == VARYING_SLOT_CLIP_DIST0)
2740 length = util_last_bit(output_usage_mask);
2741
2742 param_index = shader_io_get_unique_index(i);
2743
2744 if (lds_base) {
2745 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2746 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2747 "");
2748 }
2749
2750 for (j = 0; j < length; j++) {
2751 if (!(output_usage_mask & (1 << j)))
2752 continue;
2753
2754 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2755 out_val = ac_to_integer(&ctx->ac, out_val);
2756 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2757
2758 if (ctx->ac.chip_class >= GFX9) {
2759 LLVMValueRef dw_addr_offset =
2760 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2761 LLVMConstInt(ctx->ac.i32,
2762 j, false), "");
2763
2764 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2765 } else {
2766 ac_build_buffer_store_dword(&ctx->ac,
2767 ctx->esgs_ring,
2768 out_val, 1,
2769 NULL, ctx->es2gs_offset,
2770 (4 * param_index + j) * 4,
2771 1, 1, true, true);
2772 }
2773 }
2774 }
2775 }
2776
2777 static void
2778 handle_ls_outputs_post(struct radv_shader_context *ctx)
2779 {
2780 LLVMValueRef vertex_id = ctx->rel_auto_id;
2781 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2782 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2783 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2784 vertex_dw_stride, "");
2785
2786 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2787 unsigned output_usage_mask =
2788 ctx->shader_info->info.vs.output_usage_mask[i];
2789 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2790 int length = 4;
2791
2792 if (!(ctx->output_mask & (1ull << i)))
2793 continue;
2794
2795 if (i == VARYING_SLOT_CLIP_DIST0)
2796 length = util_last_bit(output_usage_mask);
2797
2798 int param = shader_io_get_unique_index(i);
2799 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2800 LLVMConstInt(ctx->ac.i32, param * 4, false),
2801 "");
2802 for (unsigned j = 0; j < length; j++) {
2803 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2804 value = ac_to_integer(&ctx->ac, value);
2805 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2806 ac_lds_store(&ctx->ac, dw_addr, value);
2807 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2808 }
2809 }
2810 }
2811
2812 static void
2813 write_tess_factors(struct radv_shader_context *ctx)
2814 {
2815 unsigned stride, outer_comps, inner_comps;
2816 struct ac_build_if_state if_ctx, inner_if_ctx;
2817 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2818 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2819 unsigned tess_inner_index = 0, tess_outer_index;
2820 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2821 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2822 int i;
2823 ac_emit_barrier(&ctx->ac, ctx->stage);
2824
2825 switch (ctx->options->key.tcs.primitive_mode) {
2826 case GL_ISOLINES:
2827 stride = 2;
2828 outer_comps = 2;
2829 inner_comps = 0;
2830 break;
2831 case GL_TRIANGLES:
2832 stride = 4;
2833 outer_comps = 3;
2834 inner_comps = 1;
2835 break;
2836 case GL_QUADS:
2837 stride = 6;
2838 outer_comps = 4;
2839 inner_comps = 2;
2840 break;
2841 default:
2842 return;
2843 }
2844
2845 ac_nir_build_if(&if_ctx, ctx,
2846 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2847 invocation_id, ctx->ac.i32_0, ""));
2848
2849 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2850
2851 if (inner_comps) {
2852 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2853 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2854 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2855 }
2856
2857 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2858 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2859 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2860
2861 for (i = 0; i < 4; i++) {
2862 inner[i] = LLVMGetUndef(ctx->ac.i32);
2863 outer[i] = LLVMGetUndef(ctx->ac.i32);
2864 }
2865
2866 // LINES reversal
2867 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2868 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2869 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2870 ctx->ac.i32_1, "");
2871 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2872 } else {
2873 for (i = 0; i < outer_comps; i++) {
2874 outer[i] = out[i] =
2875 ac_lds_load(&ctx->ac, lds_outer);
2876 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2877 ctx->ac.i32_1, "");
2878 }
2879 for (i = 0; i < inner_comps; i++) {
2880 inner[i] = out[outer_comps+i] =
2881 ac_lds_load(&ctx->ac, lds_inner);
2882 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2883 ctx->ac.i32_1, "");
2884 }
2885 }
2886
2887 /* Convert the outputs to vectors for stores. */
2888 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2889 vec1 = NULL;
2890
2891 if (stride > 4)
2892 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2893
2894
2895 buffer = ctx->hs_ring_tess_factor;
2896 tf_base = ctx->tess_factor_offset;
2897 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2898 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2899 unsigned tf_offset = 0;
2900
2901 if (ctx->options->chip_class <= VI) {
2902 ac_nir_build_if(&inner_if_ctx, ctx,
2903 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2904 rel_patch_id, ctx->ac.i32_0, ""));
2905
2906 /* Store the dynamic HS control word. */
2907 ac_build_buffer_store_dword(&ctx->ac, buffer,
2908 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2909 1, ctx->ac.i32_0, tf_base,
2910 0, 1, 0, true, false);
2911 tf_offset += 4;
2912
2913 ac_nir_build_endif(&inner_if_ctx);
2914 }
2915
2916 /* Store the tessellation factors. */
2917 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2918 MIN2(stride, 4), byteoffset, tf_base,
2919 tf_offset, 1, 0, true, false);
2920 if (vec1)
2921 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2922 stride - 4, byteoffset, tf_base,
2923 16 + tf_offset, 1, 0, true, false);
2924
2925 //store to offchip for TES to read - only if TES reads them
2926 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2927 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2928 LLVMValueRef tf_inner_offset;
2929 unsigned param_outer, param_inner;
2930
2931 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2932 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2933 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2934
2935 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2936 util_next_power_of_two(outer_comps));
2937
2938 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2939 outer_comps, tf_outer_offset,
2940 ctx->oc_lds, 0, 1, 0, true, false);
2941 if (inner_comps) {
2942 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2943 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2944 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2945
2946 inner_vec = inner_comps == 1 ? inner[0] :
2947 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2948 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2949 inner_comps, tf_inner_offset,
2950 ctx->oc_lds, 0, 1, 0, true, false);
2951 }
2952 }
2953 ac_nir_build_endif(&if_ctx);
2954 }
2955
2956 static void
2957 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2958 {
2959 write_tess_factors(ctx);
2960 }
2961
2962 static bool
2963 si_export_mrt_color(struct radv_shader_context *ctx,
2964 LLVMValueRef *color, unsigned index,
2965 struct ac_export_args *args)
2966 {
2967 /* Export */
2968 si_llvm_init_export_args(ctx, color, 0xf,
2969 V_008DFC_SQ_EXP_MRT + index, args);
2970 if (!args->enabled_channels)
2971 return false; /* unnecessary NULL export */
2972
2973 return true;
2974 }
2975
2976 static void
2977 radv_export_mrt_z(struct radv_shader_context *ctx,
2978 LLVMValueRef depth, LLVMValueRef stencil,
2979 LLVMValueRef samplemask)
2980 {
2981 struct ac_export_args args;
2982
2983 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2984
2985 ac_build_export(&ctx->ac, &args);
2986 }
2987
2988 static void
2989 handle_fs_outputs_post(struct radv_shader_context *ctx)
2990 {
2991 unsigned index = 0;
2992 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2993 struct ac_export_args color_args[8];
2994
2995 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2996 LLVMValueRef values[4];
2997
2998 if (!(ctx->output_mask & (1ull << i)))
2999 continue;
3000
3001 if (i < FRAG_RESULT_DATA0)
3002 continue;
3003
3004 for (unsigned j = 0; j < 4; j++)
3005 values[j] = ac_to_float(&ctx->ac,
3006 radv_load_output(ctx, i, j));
3007
3008 bool ret = si_export_mrt_color(ctx, values,
3009 i - FRAG_RESULT_DATA0,
3010 &color_args[index]);
3011 if (ret)
3012 index++;
3013 }
3014
3015 /* Process depth, stencil, samplemask. */
3016 if (ctx->shader_info->info.ps.writes_z) {
3017 depth = ac_to_float(&ctx->ac,
3018 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3019 }
3020 if (ctx->shader_info->info.ps.writes_stencil) {
3021 stencil = ac_to_float(&ctx->ac,
3022 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3023 }
3024 if (ctx->shader_info->info.ps.writes_sample_mask) {
3025 samplemask = ac_to_float(&ctx->ac,
3026 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3027 }
3028
3029 /* Set the DONE bit on last non-null color export only if Z isn't
3030 * exported.
3031 */
3032 if (index > 0 &&
3033 !ctx->shader_info->info.ps.writes_z &&
3034 !ctx->shader_info->info.ps.writes_stencil &&
3035 !ctx->shader_info->info.ps.writes_sample_mask) {
3036 unsigned last = index - 1;
3037
3038 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3039 color_args[last].done = 1; /* DONE bit */
3040 }
3041
3042 /* Export PS outputs. */
3043 for (unsigned i = 0; i < index; i++)
3044 ac_build_export(&ctx->ac, &color_args[i]);
3045
3046 if (depth || stencil || samplemask)
3047 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3048 else if (!index)
3049 ac_build_export_null(&ctx->ac);
3050 }
3051
3052 static void
3053 emit_gs_epilogue(struct radv_shader_context *ctx)
3054 {
3055 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3056 }
3057
3058 static void
3059 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3060 LLVMValueRef *addrs)
3061 {
3062 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3063
3064 switch (ctx->stage) {
3065 case MESA_SHADER_VERTEX:
3066 if (ctx->options->key.vs.as_ls)
3067 handle_ls_outputs_post(ctx);
3068 else if (ctx->options->key.vs.as_es)
3069 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
3070 else
3071 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
3072 ctx->options->key.vs.export_layer_id,
3073 &ctx->shader_info->vs.outinfo);
3074 break;
3075 case MESA_SHADER_FRAGMENT:
3076 handle_fs_outputs_post(ctx);
3077 break;
3078 case MESA_SHADER_GEOMETRY:
3079 emit_gs_epilogue(ctx);
3080 break;
3081 case MESA_SHADER_TESS_CTRL:
3082 handle_tcs_outputs_post(ctx);
3083 break;
3084 case MESA_SHADER_TESS_EVAL:
3085 if (ctx->options->key.tes.as_es)
3086 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
3087 else
3088 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
3089 ctx->options->key.tes.export_layer_id,
3090 &ctx->shader_info->tes.outinfo);
3091 break;
3092 default:
3093 break;
3094 }
3095 }
3096
3097 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3098 LLVMPassManagerRef passmgr,
3099 const struct radv_nir_compiler_options *options)
3100 {
3101 LLVMRunPassManager(passmgr, ctx->ac.module);
3102 LLVMDisposeBuilder(ctx->ac.builder);
3103
3104 ac_llvm_context_dispose(&ctx->ac);
3105 }
3106
3107 static void
3108 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3109 {
3110 struct radv_vs_output_info *outinfo;
3111
3112 switch (ctx->stage) {
3113 case MESA_SHADER_FRAGMENT:
3114 case MESA_SHADER_COMPUTE:
3115 case MESA_SHADER_TESS_CTRL:
3116 case MESA_SHADER_GEOMETRY:
3117 return;
3118 case MESA_SHADER_VERTEX:
3119 if (ctx->options->key.vs.as_ls ||
3120 ctx->options->key.vs.as_es)
3121 return;
3122 outinfo = &ctx->shader_info->vs.outinfo;
3123 break;
3124 case MESA_SHADER_TESS_EVAL:
3125 if (ctx->options->key.vs.as_es)
3126 return;
3127 outinfo = &ctx->shader_info->tes.outinfo;
3128 break;
3129 default:
3130 unreachable("Unhandled shader type");
3131 }
3132
3133 ac_optimize_vs_outputs(&ctx->ac,
3134 ctx->main_function,
3135 outinfo->vs_output_param_offset,
3136 VARYING_SLOT_MAX,
3137 &outinfo->param_exports);
3138 }
3139
3140 static void
3141 ac_setup_rings(struct radv_shader_context *ctx)
3142 {
3143 if (ctx->options->chip_class <= VI &&
3144 (ctx->stage == MESA_SHADER_GEOMETRY ||
3145 ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
3146 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3147 : RING_ESGS_VS;
3148 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3149
3150 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3151 ctx->ring_offsets,
3152 offset);
3153 }
3154
3155 if (ctx->is_gs_copy_shader) {
3156 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
3157 }
3158 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3159 LLVMValueRef tmp;
3160 uint32_t num_entries = 64;
3161 LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size, false);
3162 LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size << 16, false);
3163 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
3164
3165 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
3166
3167 tmp = LLVMConstInt(ctx->ac.i32, num_entries, false);
3168 if (ctx->options->chip_class >= VI)
3169 tmp = LLVMBuildMul(ctx->ac.builder, gsvs_ring_stride, tmp, "");
3170 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
3171 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
3172 tmp = LLVMBuildOr(ctx->ac.builder, tmp, gsvs_ring_desc, "");
3173 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
3174 }
3175
3176 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3177 ctx->stage == MESA_SHADER_TESS_EVAL) {
3178 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3179 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3180 }
3181 }
3182
3183 static unsigned
3184 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
3185 const struct nir_shader *nir)
3186 {
3187 switch (nir->info.stage) {
3188 case MESA_SHADER_TESS_CTRL:
3189 return chip_class >= CIK ? 128 : 64;
3190 case MESA_SHADER_GEOMETRY:
3191 return chip_class >= GFX9 ? 128 : 64;
3192 case MESA_SHADER_COMPUTE:
3193 break;
3194 default:
3195 return 0;
3196 }
3197
3198 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
3199 nir->info.cs.local_size[1] *
3200 nir->info.cs.local_size[2];
3201 return max_workgroup_size;
3202 }
3203
3204 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3205 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3206 {
3207 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3208 LLVMConstInt(ctx->ac.i32, 8, false),
3209 LLVMConstInt(ctx->ac.i32, 8, false), false);
3210 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3211 ctx->ac.i32_0, "");
3212 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
3213 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
3214 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3215 }
3216
3217 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3218 {
3219 for(int i = 5; i >= 0; --i) {
3220 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3221 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
3222 LLVMConstInt(ctx->ac.i32, 16, false), false);
3223 }
3224
3225 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3226 LLVMConstInt(ctx->ac.i32, 16, false),
3227 LLVMConstInt(ctx->ac.i32, 8, false), false);
3228 }
3229
3230
3231 static
3232 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
3233 struct nir_shader *const *shaders,
3234 int shader_count,
3235 struct radv_shader_variant_info *shader_info,
3236 const struct radv_nir_compiler_options *options)
3237 {
3238 struct radv_shader_context ctx = {0};
3239 unsigned i;
3240 ctx.options = options;
3241 ctx.shader_info = shader_info;
3242
3243 ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
3244 ctx.context = ctx.ac.context;
3245 ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
3246
3247 enum ac_float_mode float_mode =
3248 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3249 AC_FLOAT_MODE_DEFAULT;
3250
3251 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3252
3253 memset(shader_info, 0, sizeof(*shader_info));
3254
3255 for(int i = 0; i < shader_count; ++i)
3256 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3257
3258 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3259 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3260 for (i = 0; i < AC_UD_MAX_UD; i++)
3261 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3262
3263 ctx.max_workgroup_size = 0;
3264 for (int i = 0; i < shader_count; ++i) {
3265 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3266 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3267 shaders[i]));
3268 }
3269
3270 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3271 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3272
3273 ctx.abi.inputs = &ctx.inputs[0];
3274 ctx.abi.emit_outputs = handle_shader_outputs_post;
3275 ctx.abi.emit_vertex = visit_emit_vertex;
3276 ctx.abi.load_ubo = radv_load_ubo;
3277 ctx.abi.load_ssbo = radv_load_ssbo;
3278 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3279 ctx.abi.load_resource = radv_load_resource;
3280 ctx.abi.clamp_shadow_reference = false;
3281 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9;
3282
3283 if (shader_count >= 2)
3284 ac_init_exec_full_mask(&ctx.ac);
3285
3286 if (ctx.ac.chip_class == GFX9 &&
3287 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3288 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3289
3290 for(int i = 0; i < shader_count; ++i) {
3291 ctx.stage = shaders[i]->info.stage;
3292 ctx.output_mask = 0;
3293 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3294 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3295
3296 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3297 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3298 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3299 ctx.abi.load_inputs = load_gs_input;
3300 ctx.abi.emit_primitive = visit_end_primitive;
3301 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3302 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3303 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3304 ctx.abi.load_tess_varyings = load_tcs_varyings;
3305 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3306 ctx.abi.store_tcs_outputs = store_tcs_output;
3307 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3308 if (shader_count == 1)
3309 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3310 else
3311 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3312 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3313 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3314 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3315 ctx.abi.load_tess_varyings = load_tes_input;
3316 ctx.abi.load_tess_coord = load_tess_coord;
3317 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3318 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3319 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3320 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3321 if (shader_info->info.vs.needs_instance_id) {
3322 if (ctx.options->key.vs.as_ls) {
3323 ctx.shader_info->vs.vgpr_comp_cnt =
3324 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3325 } else {
3326 ctx.shader_info->vs.vgpr_comp_cnt =
3327 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3328 }
3329 }
3330 ctx.abi.load_base_vertex = radv_load_base_vertex;
3331 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3332 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3333 ctx.abi.lookup_interp_param = lookup_interp_param;
3334 ctx.abi.load_sample_position = load_sample_position;
3335 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3336 ctx.abi.emit_kill = radv_emit_kill;
3337 }
3338
3339 if (i)
3340 ac_emit_barrier(&ctx.ac, ctx.stage);
3341
3342 nir_foreach_variable(variable, &shaders[i]->outputs)
3343 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3344
3345 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3346 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3347 shaders[i]->info.cull_distance_array_size > 4;
3348 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3349 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3350 shaders[i]->info.gs.vertices_out;
3351 }
3352
3353 ac_setup_rings(&ctx);
3354
3355 LLVMBasicBlockRef merge_block;
3356 if (shader_count >= 2) {
3357 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3358 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3359 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3360
3361 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3362 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3363 LLVMConstInt(ctx.ac.i32, 8, false), false);
3364 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3365 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3366 thread_id, count, "");
3367 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3368
3369 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3370 }
3371
3372 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3373 handle_fs_inputs(&ctx, shaders[i]);
3374 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3375 handle_vs_inputs(&ctx, shaders[i]);
3376 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3377 prepare_gs_input_vgprs(&ctx);
3378
3379 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3380
3381 if (shader_count >= 2) {
3382 LLVMBuildBr(ctx.ac.builder, merge_block);
3383 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3384 }
3385
3386 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3387 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3388 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3389 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3390 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3391 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3392 }
3393 }
3394
3395 LLVMBuildRetVoid(ctx.ac.builder);
3396
3397 if (options->dump_preoptir)
3398 ac_dump_module(ctx.ac.module);
3399
3400 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
3401
3402 if (shader_count == 1)
3403 ac_nir_eliminate_const_vs_outputs(&ctx);
3404
3405 if (options->dump_shader) {
3406 ctx.shader_info->private_mem_vgprs =
3407 ac_count_scratch_private_memory(ctx.main_function);
3408 }
3409
3410 return ctx.ac.module;
3411 }
3412
3413 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3414 {
3415 unsigned *retval = (unsigned *)context;
3416 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3417 char *description = LLVMGetDiagInfoDescription(di);
3418
3419 if (severity == LLVMDSError) {
3420 *retval = 1;
3421 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3422 description);
3423 }
3424
3425 LLVMDisposeMessage(description);
3426 }
3427
3428 static unsigned ac_llvm_compile(LLVMModuleRef M,
3429 struct ac_shader_binary *binary,
3430 struct ac_llvm_compiler *ac_llvm)
3431 {
3432 unsigned retval = 0;
3433 LLVMContextRef llvm_ctx;
3434
3435 /* Setup Diagnostic Handler*/
3436 llvm_ctx = LLVMGetModuleContext(M);
3437
3438 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3439 &retval);
3440
3441 /* Compile IR*/
3442 if (!radv_compile_to_binary(ac_llvm, M, binary))
3443 retval = 1;
3444 return retval;
3445 }
3446
3447 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
3448 LLVMModuleRef llvm_module,
3449 struct ac_shader_binary *binary,
3450 struct ac_shader_config *config,
3451 struct radv_shader_variant_info *shader_info,
3452 gl_shader_stage stage,
3453 const struct radv_nir_compiler_options *options)
3454 {
3455 if (options->dump_shader)
3456 ac_dump_module(llvm_module);
3457
3458 memset(binary, 0, sizeof(*binary));
3459
3460 if (options->record_llvm_ir) {
3461 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3462 binary->llvm_ir_string = strdup(llvm_ir);
3463 LLVMDisposeMessage(llvm_ir);
3464 }
3465
3466 int v = ac_llvm_compile(llvm_module, binary, ac_llvm);
3467 if (v) {
3468 fprintf(stderr, "compile failed\n");
3469 }
3470
3471 if (options->dump_shader)
3472 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3473
3474 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3475
3476 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3477 LLVMDisposeModule(llvm_module);
3478 LLVMContextDispose(ctx);
3479
3480 if (stage == MESA_SHADER_FRAGMENT) {
3481 shader_info->num_input_vgprs = 0;
3482 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3483 shader_info->num_input_vgprs += 2;
3484 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3485 shader_info->num_input_vgprs += 2;
3486 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3487 shader_info->num_input_vgprs += 2;
3488 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3489 shader_info->num_input_vgprs += 3;
3490 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3491 shader_info->num_input_vgprs += 2;
3492 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3493 shader_info->num_input_vgprs += 2;
3494 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3495 shader_info->num_input_vgprs += 2;
3496 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3497 shader_info->num_input_vgprs += 1;
3498 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3499 shader_info->num_input_vgprs += 1;
3500 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3501 shader_info->num_input_vgprs += 1;
3502 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3503 shader_info->num_input_vgprs += 1;
3504 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3505 shader_info->num_input_vgprs += 1;
3506 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3507 shader_info->num_input_vgprs += 1;
3508 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3509 shader_info->num_input_vgprs += 1;
3510 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3511 shader_info->num_input_vgprs += 1;
3512 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3513 shader_info->num_input_vgprs += 1;
3514 }
3515 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3516
3517 /* +3 for scratch wave offset and VCC */
3518 config->num_sgprs = MAX2(config->num_sgprs,
3519 shader_info->num_input_sgprs + 3);
3520
3521 /* Enable 64-bit and 16-bit denormals, because there is no performance
3522 * cost.
3523 *
3524 * If denormals are enabled, all floating-point output modifiers are
3525 * ignored.
3526 *
3527 * Don't enable denormals for 32-bit floats, because:
3528 * - Floating-point output modifiers would be ignored by the hw.
3529 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3530 * have to stop using those.
3531 * - SI & CI would be very slow.
3532 */
3533 config->float_mode |= V_00B028_FP_64_DENORMS;
3534 }
3535
3536 static void
3537 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3538 {
3539 switch (nir->info.stage) {
3540 case MESA_SHADER_COMPUTE:
3541 for (int i = 0; i < 3; ++i)
3542 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3543 break;
3544 case MESA_SHADER_FRAGMENT:
3545 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3546 break;
3547 case MESA_SHADER_GEOMETRY:
3548 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3549 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3550 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3551 shader_info->gs.invocations = nir->info.gs.invocations;
3552 break;
3553 case MESA_SHADER_TESS_EVAL:
3554 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3555 shader_info->tes.spacing = nir->info.tess.spacing;
3556 shader_info->tes.ccw = nir->info.tess.ccw;
3557 shader_info->tes.point_mode = nir->info.tess.point_mode;
3558 shader_info->tes.as_es = options->key.tes.as_es;
3559 break;
3560 case MESA_SHADER_TESS_CTRL:
3561 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3562 break;
3563 case MESA_SHADER_VERTEX:
3564 shader_info->vs.as_es = options->key.vs.as_es;
3565 shader_info->vs.as_ls = options->key.vs.as_ls;
3566 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3567 if (options->key.vs.as_ls)
3568 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3569 break;
3570 default:
3571 break;
3572 }
3573 }
3574
3575 void
3576 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
3577 struct ac_shader_binary *binary,
3578 struct ac_shader_config *config,
3579 struct radv_shader_variant_info *shader_info,
3580 struct nir_shader *const *nir,
3581 int nir_count,
3582 const struct radv_nir_compiler_options *options)
3583 {
3584
3585 LLVMModuleRef llvm_module;
3586
3587 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, shader_info,
3588 options);
3589
3590 ac_compile_llvm_module(ac_llvm, llvm_module, binary, config, shader_info,
3591 nir[0]->info.stage, options);
3592
3593 for (int i = 0; i < nir_count; ++i)
3594 ac_fill_shader_info(shader_info, nir[i], options);
3595
3596 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3597 if (options->chip_class == GFX9) {
3598 if (nir_count == 2 &&
3599 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3600 shader_info->gs.es_type = nir[0]->info.stage;
3601 }
3602 }
3603 }
3604
3605 static void
3606 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3607 {
3608 LLVMValueRef vtx_offset =
3609 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3610 LLVMConstInt(ctx->ac.i32, 4, false), "");
3611 int idx = 0;
3612
3613 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3614 unsigned output_usage_mask =
3615 ctx->shader_info->info.gs.output_usage_mask[i];
3616 int length = 4;
3617 int slot = idx;
3618 int slot_inc = 1;
3619 if (!(ctx->output_mask & (1ull << i)))
3620 continue;
3621
3622 if (i == VARYING_SLOT_CLIP_DIST0) {
3623 /* unpack clip and cull from a single set of slots */
3624 length = util_last_bit(output_usage_mask);
3625 if (length > 4)
3626 slot_inc = 2;
3627 }
3628
3629 for (unsigned j = 0; j < length; j++) {
3630 LLVMValueRef value, soffset;
3631
3632 soffset = LLVMConstInt(ctx->ac.i32,
3633 (slot * 4 + j) *
3634 ctx->gs_max_out_vertices * 16 * 4, false);
3635
3636 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3637 1, ctx->ac.i32_0,
3638 vtx_offset, soffset,
3639 0, 1, 1, true, false);
3640
3641 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3642 if (ac_get_type_size(type) == 2) {
3643 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
3644 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
3645 }
3646
3647 LLVMBuildStore(ctx->ac.builder,
3648 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3649 }
3650 idx += slot_inc;
3651 }
3652 handle_vs_outputs_post(ctx, false, false, &ctx->shader_info->vs.outinfo);
3653 }
3654
3655 void
3656 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
3657 struct nir_shader *geom_shader,
3658 struct ac_shader_binary *binary,
3659 struct ac_shader_config *config,
3660 struct radv_shader_variant_info *shader_info,
3661 const struct radv_nir_compiler_options *options)
3662 {
3663 struct radv_shader_context ctx = {0};
3664 ctx.options = options;
3665 ctx.shader_info = shader_info;
3666
3667 ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
3668 ctx.context = ctx.ac.context;
3669 ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
3670
3671 ctx.is_gs_copy_shader = true;
3672
3673 enum ac_float_mode float_mode =
3674 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3675 AC_FLOAT_MODE_DEFAULT;
3676
3677 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3678 ctx.stage = MESA_SHADER_VERTEX;
3679
3680 radv_nir_shader_info_pass(geom_shader, options, &shader_info->info);
3681
3682 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3683
3684 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3685 ac_setup_rings(&ctx);
3686
3687 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3688 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3689
3690 nir_foreach_variable(variable, &geom_shader->outputs) {
3691 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3692 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3693 variable, MESA_SHADER_VERTEX);
3694 }
3695
3696 ac_gs_copy_shader_emit(&ctx);
3697
3698 LLVMBuildRetVoid(ctx.ac.builder);
3699
3700 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
3701
3702 ac_compile_llvm_module(ac_llvm, ctx.ac.module, binary, config, shader_info,
3703 MESA_SHADER_VERTEX, options);
3704 }