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radv: add multiple streams support for the GS copy shader
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "nir/nir.h"
32
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #if HAVE_LLVM >= 0x0700
37 #include <llvm-c/Transforms/Utils.h>
38 #endif
39
40 #include "sid.h"
41 #include "gfx9d.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_llvm_build.h"
45 #include "ac_shader_abi.h"
46 #include "ac_shader_util.h"
47 #include "ac_exp_param.h"
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct radv_shader_context {
52 struct ac_llvm_context ac;
53 const struct radv_nir_compiler_options *options;
54 struct radv_shader_variant_info *shader_info;
55 struct ac_shader_abi abi;
56
57 unsigned max_workgroup_size;
58 LLVMContextRef context;
59 LLVMValueRef main_function;
60
61 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
62 LLVMValueRef ring_offsets;
63
64 LLVMValueRef vertex_buffers;
65 LLVMValueRef rel_auto_id;
66 LLVMValueRef vs_prim_id;
67 LLVMValueRef es2gs_offset;
68
69 LLVMValueRef oc_lds;
70 LLVMValueRef merged_wave_info;
71 LLVMValueRef tess_factor_offset;
72 LLVMValueRef tes_rel_patch_id;
73 LLVMValueRef tes_u;
74 LLVMValueRef tes_v;
75
76 LLVMValueRef gs2vs_offset;
77 LLVMValueRef gs_wave_id;
78 LLVMValueRef gs_vtx_offset[6];
79
80 LLVMValueRef esgs_ring;
81 LLVMValueRef gsvs_ring[4];
82 LLVMValueRef hs_ring_tess_offchip;
83 LLVMValueRef hs_ring_tess_factor;
84
85 LLVMValueRef persp_sample, persp_center, persp_centroid;
86 LLVMValueRef linear_sample, linear_center, linear_centroid;
87
88 /* Streamout */
89 LLVMValueRef streamout_buffers;
90 LLVMValueRef streamout_write_idx;
91 LLVMValueRef streamout_config;
92 LLVMValueRef streamout_offset[4];
93
94 gl_shader_stage stage;
95
96 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
97
98 uint64_t input_mask;
99 uint64_t output_mask;
100
101 bool is_gs_copy_shader;
102 LLVMValueRef gs_next_vertex[4];
103 unsigned gs_max_out_vertices;
104
105 unsigned tes_primitive_mode;
106
107 uint32_t tcs_patch_outputs_read;
108 uint64_t tcs_outputs_read;
109 uint32_t tcs_vertices_per_patch;
110 uint32_t tcs_num_inputs;
111 uint32_t tcs_num_patches;
112 uint32_t max_gsvs_emit_size;
113 uint32_t gsvs_vertex_size;
114 };
115
116 enum radeon_llvm_calling_convention {
117 RADEON_LLVM_AMDGPU_VS = 87,
118 RADEON_LLVM_AMDGPU_GS = 88,
119 RADEON_LLVM_AMDGPU_PS = 89,
120 RADEON_LLVM_AMDGPU_CS = 90,
121 RADEON_LLVM_AMDGPU_HS = 93,
122 };
123
124 static inline struct radv_shader_context *
125 radv_shader_context_from_abi(struct ac_shader_abi *abi)
126 {
127 struct radv_shader_context *ctx = NULL;
128 return container_of(abi, ctx, abi);
129 }
130
131 struct ac_build_if_state
132 {
133 struct radv_shader_context *ctx;
134 LLVMValueRef condition;
135 LLVMBasicBlockRef entry_block;
136 LLVMBasicBlockRef true_block;
137 LLVMBasicBlockRef false_block;
138 LLVMBasicBlockRef merge_block;
139 };
140
141 static LLVMBasicBlockRef
142 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
143 {
144 LLVMBasicBlockRef current_block;
145 LLVMBasicBlockRef next_block;
146 LLVMBasicBlockRef new_block;
147
148 /* get current basic block */
149 current_block = LLVMGetInsertBlock(ctx->ac.builder);
150
151 /* chqeck if there's another block after this one */
152 next_block = LLVMGetNextBasicBlock(current_block);
153 if (next_block) {
154 /* insert the new block before the next block */
155 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
156 }
157 else {
158 /* append new block after current block */
159 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
160 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
161 }
162 return new_block;
163 }
164
165 static void
166 ac_nir_build_if(struct ac_build_if_state *ifthen,
167 struct radv_shader_context *ctx,
168 LLVMValueRef condition)
169 {
170 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
171
172 memset(ifthen, 0, sizeof *ifthen);
173 ifthen->ctx = ctx;
174 ifthen->condition = condition;
175 ifthen->entry_block = block;
176
177 /* create endif/merge basic block for the phi functions */
178 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
179
180 /* create/insert true_block before merge_block */
181 ifthen->true_block =
182 LLVMInsertBasicBlockInContext(ctx->context,
183 ifthen->merge_block,
184 "if-true-block");
185
186 /* successive code goes into the true block */
187 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
188 }
189
190 /**
191 * End a conditional.
192 */
193 static void
194 ac_nir_build_endif(struct ac_build_if_state *ifthen)
195 {
196 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
197
198 /* Insert branch to the merge block from current block */
199 LLVMBuildBr(builder, ifthen->merge_block);
200
201 /*
202 * Now patch in the various branch instructions.
203 */
204
205 /* Insert the conditional branch instruction at the end of entry_block */
206 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
207 if (ifthen->false_block) {
208 /* we have an else clause */
209 LLVMBuildCondBr(builder, ifthen->condition,
210 ifthen->true_block, ifthen->false_block);
211 }
212 else {
213 /* no else clause */
214 LLVMBuildCondBr(builder, ifthen->condition,
215 ifthen->true_block, ifthen->merge_block);
216 }
217
218 /* Resume building code at end of the ifthen->merge_block */
219 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
220 }
221
222
223 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
224 {
225 switch (ctx->stage) {
226 case MESA_SHADER_TESS_CTRL:
227 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
228 case MESA_SHADER_TESS_EVAL:
229 return ctx->tes_rel_patch_id;
230 break;
231 default:
232 unreachable("Illegal stage");
233 }
234 }
235
236 static unsigned
237 get_tcs_num_patches(struct radv_shader_context *ctx)
238 {
239 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
240 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
241 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
242 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
243 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
244 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
245 uint32_t output_vertex_size = num_tcs_outputs * 16;
246 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
247 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
248 unsigned num_patches;
249 unsigned hardware_lds_size;
250
251 /* Ensure that we only need one wave per SIMD so we don't need to check
252 * resource usage. Also ensures that the number of tcs in and out
253 * vertices per threadgroup are at most 256.
254 */
255 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
256 /* Make sure that the data fits in LDS. This assumes the shaders only
257 * use LDS for the inputs and outputs.
258 */
259 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
260 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
261 /* Make sure the output data fits in the offchip buffer */
262 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
263 /* Not necessary for correctness, but improves performance. The
264 * specific value is taken from the proprietary driver.
265 */
266 num_patches = MIN2(num_patches, 40);
267
268 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
269 if (ctx->options->chip_class == SI) {
270 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
271 num_patches = MIN2(num_patches, one_wave);
272 }
273 return num_patches;
274 }
275
276 static unsigned
277 calculate_tess_lds_size(struct radv_shader_context *ctx)
278 {
279 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
280 unsigned num_tcs_output_cp;
281 unsigned num_tcs_outputs, num_tcs_patch_outputs;
282 unsigned input_vertex_size, output_vertex_size;
283 unsigned input_patch_size, output_patch_size;
284 unsigned pervertex_output_patch_size;
285 unsigned output_patch0_offset;
286 unsigned num_patches;
287 unsigned lds_size;
288
289 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
290 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
291 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
292
293 input_vertex_size = ctx->tcs_num_inputs * 16;
294 output_vertex_size = num_tcs_outputs * 16;
295
296 input_patch_size = num_tcs_input_cp * input_vertex_size;
297
298 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
299 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
300
301 num_patches = ctx->tcs_num_patches;
302 output_patch0_offset = input_patch_size * num_patches;
303
304 lds_size = output_patch0_offset + output_patch_size * num_patches;
305 return lds_size;
306 }
307
308 /* Tessellation shaders pass outputs to the next shader using LDS.
309 *
310 * LS outputs = TCS inputs
311 * TCS outputs = TES inputs
312 *
313 * The LDS layout is:
314 * - TCS inputs for patch 0
315 * - TCS inputs for patch 1
316 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
317 * - ...
318 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
319 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
320 * - TCS outputs for patch 1
321 * - Per-patch TCS outputs for patch 1
322 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
323 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
324 * - ...
325 *
326 * All three shaders VS(LS), TCS, TES share the same LDS space.
327 */
328 static LLVMValueRef
329 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
330 {
331 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
332 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
333 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
334
335 input_patch_size /= 4;
336 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
337 }
338
339 static LLVMValueRef
340 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
341 {
342 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
343 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
344 uint32_t output_vertex_size = num_tcs_outputs * 16;
345 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
346 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
347 output_patch_size /= 4;
348 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
349 }
350
351 static LLVMValueRef
352 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
353 {
354 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
355 uint32_t output_vertex_size = num_tcs_outputs * 16;
356 output_vertex_size /= 4;
357 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
358 }
359
360 static LLVMValueRef
361 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
362 {
363 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
364 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
365 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
366 uint32_t output_patch0_offset = input_patch_size;
367 unsigned num_patches = ctx->tcs_num_patches;
368
369 output_patch0_offset *= num_patches;
370 output_patch0_offset /= 4;
371 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
372 }
373
374 static LLVMValueRef
375 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
376 {
377 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
378 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
379 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
380 uint32_t output_patch0_offset = input_patch_size;
381
382 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
383 uint32_t output_vertex_size = num_tcs_outputs * 16;
384 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
385 unsigned num_patches = ctx->tcs_num_patches;
386
387 output_patch0_offset *= num_patches;
388 output_patch0_offset += pervertex_output_patch_size;
389 output_patch0_offset /= 4;
390 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
391 }
392
393 static LLVMValueRef
394 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
395 {
396 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
397 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
398
399 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
400 }
401
402 static LLVMValueRef
403 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
404 {
405 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
406 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
407 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
408
409 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
410 patch0_offset);
411 }
412
413 static LLVMValueRef
414 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
415 {
416 LLVMValueRef patch0_patch_data_offset =
417 get_tcs_out_patch0_patch_data_offset(ctx);
418 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
419 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
420
421 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
422 patch0_patch_data_offset);
423 }
424
425 #define MAX_ARGS 64
426 struct arg_info {
427 LLVMTypeRef types[MAX_ARGS];
428 LLVMValueRef *assign[MAX_ARGS];
429 unsigned array_params_mask;
430 uint8_t count;
431 uint8_t sgpr_count;
432 uint8_t num_sgprs_used;
433 uint8_t num_vgprs_used;
434 };
435
436 enum ac_arg_regfile {
437 ARG_SGPR,
438 ARG_VGPR,
439 };
440
441 static void
442 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
443 LLVMValueRef *param_ptr)
444 {
445 assert(info->count < MAX_ARGS);
446
447 info->assign[info->count] = param_ptr;
448 info->types[info->count] = type;
449 info->count++;
450
451 if (regfile == ARG_SGPR) {
452 info->num_sgprs_used += ac_get_type_size(type) / 4;
453 info->sgpr_count++;
454 } else {
455 assert(regfile == ARG_VGPR);
456 info->num_vgprs_used += ac_get_type_size(type) / 4;
457 }
458 }
459
460 static inline void
461 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
462 {
463 info->array_params_mask |= (1 << info->count);
464 add_arg(info, ARG_SGPR, type, param_ptr);
465 }
466
467 static void assign_arguments(LLVMValueRef main_function,
468 struct arg_info *info)
469 {
470 unsigned i;
471 for (i = 0; i < info->count; i++) {
472 if (info->assign[i])
473 *info->assign[i] = LLVMGetParam(main_function, i);
474 }
475 }
476
477 static LLVMValueRef
478 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
479 LLVMBuilderRef builder, LLVMTypeRef *return_types,
480 unsigned num_return_elems,
481 struct arg_info *args,
482 unsigned max_workgroup_size,
483 const struct radv_nir_compiler_options *options)
484 {
485 LLVMTypeRef main_function_type, ret_type;
486 LLVMBasicBlockRef main_function_body;
487
488 if (num_return_elems)
489 ret_type = LLVMStructTypeInContext(ctx, return_types,
490 num_return_elems, true);
491 else
492 ret_type = LLVMVoidTypeInContext(ctx);
493
494 /* Setup the function */
495 main_function_type =
496 LLVMFunctionType(ret_type, args->types, args->count, 0);
497 LLVMValueRef main_function =
498 LLVMAddFunction(module, "main", main_function_type);
499 main_function_body =
500 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
501 LLVMPositionBuilderAtEnd(builder, main_function_body);
502
503 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
504 for (unsigned i = 0; i < args->sgpr_count; ++i) {
505 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
506
507 if (args->array_params_mask & (1 << i)) {
508 LLVMValueRef P = LLVMGetParam(main_function, i);
509 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
510 ac_add_attr_dereferenceable(P, UINT64_MAX);
511 }
512 }
513
514 if (options->address32_hi) {
515 ac_llvm_add_target_dep_function_attr(main_function,
516 "amdgpu-32bit-address-high-bits",
517 options->address32_hi);
518 }
519
520 if (max_workgroup_size) {
521 ac_llvm_add_target_dep_function_attr(main_function,
522 "amdgpu-max-work-group-size",
523 max_workgroup_size);
524 }
525 if (options->unsafe_math) {
526 /* These were copied from some LLVM test. */
527 LLVMAddTargetDependentFunctionAttr(main_function,
528 "less-precise-fpmad",
529 "true");
530 LLVMAddTargetDependentFunctionAttr(main_function,
531 "no-infs-fp-math",
532 "true");
533 LLVMAddTargetDependentFunctionAttr(main_function,
534 "no-nans-fp-math",
535 "true");
536 LLVMAddTargetDependentFunctionAttr(main_function,
537 "unsafe-fp-math",
538 "true");
539 LLVMAddTargetDependentFunctionAttr(main_function,
540 "no-signed-zeros-fp-math",
541 "true");
542 }
543 return main_function;
544 }
545
546
547 static void
548 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx,
549 uint8_t num_sgprs, bool indirect)
550 {
551 ud_info->sgpr_idx = *sgpr_idx;
552 ud_info->num_sgprs = num_sgprs;
553 ud_info->indirect = indirect;
554 *sgpr_idx += num_sgprs;
555 }
556
557 static void
558 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
559 uint8_t num_sgprs)
560 {
561 struct radv_userdata_info *ud_info =
562 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
563 assert(ud_info);
564
565 set_loc(ud_info, sgpr_idx, num_sgprs, false);
566 }
567
568 static void
569 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
570 {
571 bool use_32bit_pointers = HAVE_32BIT_POINTERS &&
572 idx != AC_UD_SCRATCH_RING_OFFSETS;
573
574 set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
575 }
576
577 static void
578 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
579 bool indirect)
580 {
581 struct radv_userdata_locations *locs =
582 &ctx->shader_info->user_sgprs_locs;
583 struct radv_userdata_info *ud_info = &locs->descriptor_sets[idx];
584 assert(ud_info);
585
586 set_loc(ud_info, sgpr_idx, HAVE_32BIT_POINTERS ? 1 : 2, indirect);
587
588 if (!indirect)
589 locs->descriptor_sets_enabled |= 1 << idx;
590 }
591
592 struct user_sgpr_info {
593 bool need_ring_offsets;
594 bool indirect_all_descriptor_sets;
595 };
596
597 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
598 gl_shader_stage stage)
599 {
600 switch (stage) {
601 case MESA_SHADER_VERTEX:
602 if (ctx->shader_info->info.needs_multiview_view_index ||
603 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
604 return true;
605 break;
606 case MESA_SHADER_TESS_EVAL:
607 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
608 return true;
609 break;
610 case MESA_SHADER_GEOMETRY:
611 case MESA_SHADER_TESS_CTRL:
612 if (ctx->shader_info->info.needs_multiview_view_index)
613 return true;
614 break;
615 default:
616 break;
617 }
618 return false;
619 }
620
621 static uint8_t
622 count_vs_user_sgprs(struct radv_shader_context *ctx)
623 {
624 uint8_t count = 0;
625
626 if (ctx->shader_info->info.vs.has_vertex_buffers)
627 count += HAVE_32BIT_POINTERS ? 1 : 2;
628 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
629
630 return count;
631 }
632
633 static void allocate_user_sgprs(struct radv_shader_context *ctx,
634 gl_shader_stage stage,
635 bool has_previous_stage,
636 gl_shader_stage previous_stage,
637 bool needs_view_index,
638 struct user_sgpr_info *user_sgpr_info)
639 {
640 uint8_t user_sgpr_count = 0;
641
642 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
643
644 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
645 if (stage == MESA_SHADER_GEOMETRY ||
646 stage == MESA_SHADER_VERTEX ||
647 stage == MESA_SHADER_TESS_CTRL ||
648 stage == MESA_SHADER_TESS_EVAL ||
649 ctx->is_gs_copy_shader)
650 user_sgpr_info->need_ring_offsets = true;
651
652 if (stage == MESA_SHADER_FRAGMENT &&
653 ctx->shader_info->info.ps.needs_sample_positions)
654 user_sgpr_info->need_ring_offsets = true;
655
656 /* 2 user sgprs will nearly always be allocated for scratch/rings */
657 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
658 user_sgpr_count += 2;
659 }
660
661 switch (stage) {
662 case MESA_SHADER_COMPUTE:
663 if (ctx->shader_info->info.cs.uses_grid_size)
664 user_sgpr_count += 3;
665 break;
666 case MESA_SHADER_FRAGMENT:
667 user_sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
668 break;
669 case MESA_SHADER_VERTEX:
670 if (!ctx->is_gs_copy_shader)
671 user_sgpr_count += count_vs_user_sgprs(ctx);
672 break;
673 case MESA_SHADER_TESS_CTRL:
674 if (has_previous_stage) {
675 if (previous_stage == MESA_SHADER_VERTEX)
676 user_sgpr_count += count_vs_user_sgprs(ctx);
677 }
678 break;
679 case MESA_SHADER_TESS_EVAL:
680 break;
681 case MESA_SHADER_GEOMETRY:
682 if (has_previous_stage) {
683 if (previous_stage == MESA_SHADER_VERTEX) {
684 user_sgpr_count += count_vs_user_sgprs(ctx);
685 }
686 }
687 break;
688 default:
689 break;
690 }
691
692 if (needs_view_index)
693 user_sgpr_count++;
694
695 if (ctx->shader_info->info.loads_push_constants)
696 user_sgpr_count += HAVE_32BIT_POINTERS ? 1 : 2;
697
698 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
699 uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
700 uint32_t num_desc_set =
701 util_bitcount(ctx->shader_info->info.desc_set_used_mask);
702
703 if (remaining_sgprs / (HAVE_32BIT_POINTERS ? 1 : 2) < num_desc_set) {
704 user_sgpr_info->indirect_all_descriptor_sets = true;
705 }
706 }
707
708 static void
709 declare_global_input_sgprs(struct radv_shader_context *ctx,
710 gl_shader_stage stage,
711 bool has_previous_stage,
712 gl_shader_stage previous_stage,
713 const struct user_sgpr_info *user_sgpr_info,
714 struct arg_info *args,
715 LLVMValueRef *desc_sets)
716 {
717 LLVMTypeRef type = ac_array_in_const32_addr_space(ctx->ac.i8);
718 unsigned num_sets = ctx->options->layout ?
719 ctx->options->layout->num_sets : 0;
720 unsigned stage_mask = 1 << stage;
721
722 if (has_previous_stage)
723 stage_mask |= 1 << previous_stage;
724
725 /* 1 for each descriptor set */
726 if (!user_sgpr_info->indirect_all_descriptor_sets) {
727 for (unsigned i = 0; i < num_sets; ++i) {
728 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
729 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
730 add_array_arg(args, type,
731 &ctx->descriptor_sets[i]);
732 }
733 }
734 } else {
735 add_array_arg(args, ac_array_in_const32_addr_space(type), desc_sets);
736 }
737
738 if (ctx->shader_info->info.loads_push_constants) {
739 /* 1 for push constants and dynamic descriptors */
740 add_array_arg(args, type, &ctx->abi.push_constants);
741 }
742
743 if (ctx->shader_info->info.so.num_outputs) {
744 add_arg(args, ARG_SGPR,
745 ac_array_in_const32_addr_space(ctx->ac.v4i32),
746 &ctx->streamout_buffers);
747 }
748 }
749
750 static void
751 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
752 gl_shader_stage stage,
753 bool has_previous_stage,
754 gl_shader_stage previous_stage,
755 struct arg_info *args)
756 {
757 if (!ctx->is_gs_copy_shader &&
758 (stage == MESA_SHADER_VERTEX ||
759 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
760 if (ctx->shader_info->info.vs.has_vertex_buffers) {
761 add_arg(args, ARG_SGPR,
762 ac_array_in_const32_addr_space(ctx->ac.v4i32),
763 &ctx->vertex_buffers);
764 }
765 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
766 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
767 if (ctx->shader_info->info.vs.needs_draw_id) {
768 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
769 }
770 }
771 }
772
773 static void
774 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
775 {
776 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
777 if (!ctx->is_gs_copy_shader) {
778 if (ctx->options->key.vs.as_ls) {
779 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
780 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
781 } else {
782 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
783 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
784 }
785 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
786 }
787 }
788
789 static void
790 declare_streamout_sgprs(struct radv_shader_context *ctx, gl_shader_stage stage,
791 struct arg_info *args)
792 {
793 int i;
794
795 /* Streamout SGPRs. */
796 if (ctx->shader_info->info.so.num_outputs) {
797 assert(stage == MESA_SHADER_VERTEX ||
798 stage == MESA_SHADER_TESS_EVAL);
799
800 if (stage != MESA_SHADER_TESS_EVAL) {
801 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_config);
802 } else {
803 args->assign[args->count - 1] = &ctx->streamout_config;
804 args->types[args->count - 1] = ctx->ac.i32;
805 }
806
807 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_write_idx);
808 }
809
810 /* A streamout buffer offset is loaded if the stride is non-zero. */
811 for (i = 0; i < 4; i++) {
812 if (!ctx->shader_info->info.so.strides[i])
813 continue;
814
815 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_offset[i]);
816 }
817 }
818
819 static void
820 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
821 {
822 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
823 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
824 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
825 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
826 }
827
828 static void
829 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
830 bool has_previous_stage, gl_shader_stage previous_stage,
831 const struct user_sgpr_info *user_sgpr_info,
832 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
833 {
834 unsigned num_sets = ctx->options->layout ?
835 ctx->options->layout->num_sets : 0;
836 unsigned stage_mask = 1 << stage;
837
838 if (has_previous_stage)
839 stage_mask |= 1 << previous_stage;
840
841 if (!user_sgpr_info->indirect_all_descriptor_sets) {
842 for (unsigned i = 0; i < num_sets; ++i) {
843 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
844 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
845 set_loc_desc(ctx, i, user_sgpr_idx, false);
846 } else
847 ctx->descriptor_sets[i] = NULL;
848 }
849 } else {
850 set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
851 user_sgpr_idx);
852
853 for (unsigned i = 0; i < num_sets; ++i) {
854 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
855 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
856 ctx->descriptor_sets[i] =
857 ac_build_load_to_sgpr(&ctx->ac,
858 desc_sets,
859 LLVMConstInt(ctx->ac.i32, i, false));
860
861 } else
862 ctx->descriptor_sets[i] = NULL;
863 }
864 ctx->shader_info->need_indirect_descriptor_sets = true;
865 }
866
867 if (ctx->shader_info->info.loads_push_constants) {
868 set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
869 }
870
871 if (ctx->streamout_buffers) {
872 set_loc_shader_ptr(ctx, AC_UD_STREAMOUT_BUFFERS,
873 user_sgpr_idx);
874 }
875 }
876
877 static void
878 set_vs_specific_input_locs(struct radv_shader_context *ctx,
879 gl_shader_stage stage, bool has_previous_stage,
880 gl_shader_stage previous_stage,
881 uint8_t *user_sgpr_idx)
882 {
883 if (!ctx->is_gs_copy_shader &&
884 (stage == MESA_SHADER_VERTEX ||
885 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
886 if (ctx->shader_info->info.vs.has_vertex_buffers) {
887 set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
888 user_sgpr_idx);
889 }
890
891 unsigned vs_num = 2;
892 if (ctx->shader_info->info.vs.needs_draw_id)
893 vs_num++;
894
895 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
896 user_sgpr_idx, vs_num);
897 }
898 }
899
900 static void set_llvm_calling_convention(LLVMValueRef func,
901 gl_shader_stage stage)
902 {
903 enum radeon_llvm_calling_convention calling_conv;
904
905 switch (stage) {
906 case MESA_SHADER_VERTEX:
907 case MESA_SHADER_TESS_EVAL:
908 calling_conv = RADEON_LLVM_AMDGPU_VS;
909 break;
910 case MESA_SHADER_GEOMETRY:
911 calling_conv = RADEON_LLVM_AMDGPU_GS;
912 break;
913 case MESA_SHADER_TESS_CTRL:
914 calling_conv = RADEON_LLVM_AMDGPU_HS;
915 break;
916 case MESA_SHADER_FRAGMENT:
917 calling_conv = RADEON_LLVM_AMDGPU_PS;
918 break;
919 case MESA_SHADER_COMPUTE:
920 calling_conv = RADEON_LLVM_AMDGPU_CS;
921 break;
922 default:
923 unreachable("Unhandle shader type");
924 }
925
926 LLVMSetFunctionCallConv(func, calling_conv);
927 }
928
929 static void create_function(struct radv_shader_context *ctx,
930 gl_shader_stage stage,
931 bool has_previous_stage,
932 gl_shader_stage previous_stage)
933 {
934 uint8_t user_sgpr_idx;
935 struct user_sgpr_info user_sgpr_info;
936 struct arg_info args = {};
937 LLVMValueRef desc_sets;
938 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
939 allocate_user_sgprs(ctx, stage, has_previous_stage,
940 previous_stage, needs_view_index, &user_sgpr_info);
941
942 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
943 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
944 &ctx->ring_offsets);
945 }
946
947 switch (stage) {
948 case MESA_SHADER_COMPUTE:
949 declare_global_input_sgprs(ctx, stage, has_previous_stage,
950 previous_stage, &user_sgpr_info,
951 &args, &desc_sets);
952
953 if (ctx->shader_info->info.cs.uses_grid_size) {
954 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
955 &ctx->abi.num_work_groups);
956 }
957
958 for (int i = 0; i < 3; i++) {
959 ctx->abi.workgroup_ids[i] = NULL;
960 if (ctx->shader_info->info.cs.uses_block_id[i]) {
961 add_arg(&args, ARG_SGPR, ctx->ac.i32,
962 &ctx->abi.workgroup_ids[i]);
963 }
964 }
965
966 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
967 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
968 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
969 &ctx->abi.local_invocation_ids);
970 break;
971 case MESA_SHADER_VERTEX:
972 declare_global_input_sgprs(ctx, stage, has_previous_stage,
973 previous_stage, &user_sgpr_info,
974 &args, &desc_sets);
975 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
976 previous_stage, &args);
977
978 if (needs_view_index)
979 add_arg(&args, ARG_SGPR, ctx->ac.i32,
980 &ctx->abi.view_index);
981 if (ctx->options->key.vs.as_es) {
982 add_arg(&args, ARG_SGPR, ctx->ac.i32,
983 &ctx->es2gs_offset);
984 } else if (ctx->options->key.vs.as_ls) {
985 /* no extra parameters */
986 } else {
987 declare_streamout_sgprs(ctx, stage, &args);
988 }
989
990 declare_vs_input_vgprs(ctx, &args);
991 break;
992 case MESA_SHADER_TESS_CTRL:
993 if (has_previous_stage) {
994 // First 6 system regs
995 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
996 add_arg(&args, ARG_SGPR, ctx->ac.i32,
997 &ctx->merged_wave_info);
998 add_arg(&args, ARG_SGPR, ctx->ac.i32,
999 &ctx->tess_factor_offset);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1002 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1003 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1004
1005 declare_global_input_sgprs(ctx, stage,
1006 has_previous_stage,
1007 previous_stage,
1008 &user_sgpr_info, &args,
1009 &desc_sets);
1010 declare_vs_specific_input_sgprs(ctx, stage,
1011 has_previous_stage,
1012 previous_stage, &args);
1013
1014 if (needs_view_index)
1015 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1016 &ctx->abi.view_index);
1017
1018 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1019 &ctx->abi.tcs_patch_id);
1020 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1021 &ctx->abi.tcs_rel_ids);
1022
1023 declare_vs_input_vgprs(ctx, &args);
1024 } else {
1025 declare_global_input_sgprs(ctx, stage,
1026 has_previous_stage,
1027 previous_stage,
1028 &user_sgpr_info, &args,
1029 &desc_sets);
1030
1031 if (needs_view_index)
1032 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1033 &ctx->abi.view_index);
1034
1035 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1036 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1037 &ctx->tess_factor_offset);
1038 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1039 &ctx->abi.tcs_patch_id);
1040 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1041 &ctx->abi.tcs_rel_ids);
1042 }
1043 break;
1044 case MESA_SHADER_TESS_EVAL:
1045 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1046 previous_stage, &user_sgpr_info,
1047 &args, &desc_sets);
1048
1049 if (needs_view_index)
1050 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1051 &ctx->abi.view_index);
1052
1053 if (ctx->options->key.tes.as_es) {
1054 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1055 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1056 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1057 &ctx->es2gs_offset);
1058 } else {
1059 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1060 declare_streamout_sgprs(ctx, stage, &args);
1061 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1062 }
1063 declare_tes_input_vgprs(ctx, &args);
1064 break;
1065 case MESA_SHADER_GEOMETRY:
1066 if (has_previous_stage) {
1067 // First 6 system regs
1068 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1069 &ctx->gs2vs_offset);
1070 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1071 &ctx->merged_wave_info);
1072 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1073
1074 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1075 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1076 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1077
1078 declare_global_input_sgprs(ctx, stage,
1079 has_previous_stage,
1080 previous_stage,
1081 &user_sgpr_info, &args,
1082 &desc_sets);
1083
1084 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1085 declare_vs_specific_input_sgprs(ctx, stage,
1086 has_previous_stage,
1087 previous_stage,
1088 &args);
1089 }
1090
1091 if (needs_view_index)
1092 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1093 &ctx->abi.view_index);
1094
1095 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1096 &ctx->gs_vtx_offset[0]);
1097 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1098 &ctx->gs_vtx_offset[2]);
1099 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1100 &ctx->abi.gs_prim_id);
1101 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1102 &ctx->abi.gs_invocation_id);
1103 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1104 &ctx->gs_vtx_offset[4]);
1105
1106 if (previous_stage == MESA_SHADER_VERTEX) {
1107 declare_vs_input_vgprs(ctx, &args);
1108 } else {
1109 declare_tes_input_vgprs(ctx, &args);
1110 }
1111 } else {
1112 declare_global_input_sgprs(ctx, stage,
1113 has_previous_stage,
1114 previous_stage,
1115 &user_sgpr_info, &args,
1116 &desc_sets);
1117
1118 if (needs_view_index)
1119 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1120 &ctx->abi.view_index);
1121
1122 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1123 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1124 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1125 &ctx->gs_vtx_offset[0]);
1126 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1127 &ctx->gs_vtx_offset[1]);
1128 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1129 &ctx->abi.gs_prim_id);
1130 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1131 &ctx->gs_vtx_offset[2]);
1132 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1133 &ctx->gs_vtx_offset[3]);
1134 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1135 &ctx->gs_vtx_offset[4]);
1136 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1137 &ctx->gs_vtx_offset[5]);
1138 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1139 &ctx->abi.gs_invocation_id);
1140 }
1141 break;
1142 case MESA_SHADER_FRAGMENT:
1143 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1144 previous_stage, &user_sgpr_info,
1145 &args, &desc_sets);
1146
1147 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1148 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1149 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1150 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1151 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1152 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1153 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1154 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1155 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1156 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1157 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1158 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1159 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1160 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1161 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1162 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1163 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1164 break;
1165 default:
1166 unreachable("Shader stage not implemented");
1167 }
1168
1169 ctx->main_function = create_llvm_function(
1170 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1171 ctx->max_workgroup_size, ctx->options);
1172 set_llvm_calling_convention(ctx->main_function, stage);
1173
1174
1175 ctx->shader_info->num_input_vgprs = 0;
1176 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1177
1178 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1179
1180 if (ctx->stage != MESA_SHADER_FRAGMENT)
1181 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1182
1183 assign_arguments(ctx->main_function, &args);
1184
1185 user_sgpr_idx = 0;
1186
1187 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1188 set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1189 &user_sgpr_idx);
1190 if (ctx->options->supports_spill) {
1191 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1192 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
1193 NULL, 0, AC_FUNC_ATTR_READNONE);
1194 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1195 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1196 }
1197 }
1198
1199 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1200 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1201 if (has_previous_stage)
1202 user_sgpr_idx = 0;
1203
1204 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1205 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1206
1207 switch (stage) {
1208 case MESA_SHADER_COMPUTE:
1209 if (ctx->shader_info->info.cs.uses_grid_size) {
1210 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1211 &user_sgpr_idx, 3);
1212 }
1213 break;
1214 case MESA_SHADER_VERTEX:
1215 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1216 previous_stage, &user_sgpr_idx);
1217 if (ctx->abi.view_index)
1218 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1219 break;
1220 case MESA_SHADER_TESS_CTRL:
1221 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1222 previous_stage, &user_sgpr_idx);
1223 if (ctx->abi.view_index)
1224 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1225 break;
1226 case MESA_SHADER_TESS_EVAL:
1227 if (ctx->abi.view_index)
1228 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1229 break;
1230 case MESA_SHADER_GEOMETRY:
1231 if (has_previous_stage) {
1232 if (previous_stage == MESA_SHADER_VERTEX)
1233 set_vs_specific_input_locs(ctx, stage,
1234 has_previous_stage,
1235 previous_stage,
1236 &user_sgpr_idx);
1237 }
1238 if (ctx->abi.view_index)
1239 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1240 break;
1241 case MESA_SHADER_FRAGMENT:
1242 break;
1243 default:
1244 unreachable("Shader stage not implemented");
1245 }
1246
1247 if (stage == MESA_SHADER_TESS_CTRL ||
1248 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1249 /* GFX9 has the ESGS ring buffer in LDS. */
1250 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1251 ac_declare_lds_as_pointer(&ctx->ac);
1252 }
1253
1254 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1255 }
1256
1257
1258 static LLVMValueRef
1259 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1260 unsigned desc_set, unsigned binding)
1261 {
1262 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1263 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1264 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1265 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1266 unsigned base_offset = layout->binding[binding].offset;
1267 LLVMValueRef offset, stride;
1268
1269 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1270 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1271 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1272 layout->binding[binding].dynamic_offset_offset;
1273 desc_ptr = ctx->abi.push_constants;
1274 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1275 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1276 } else
1277 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1278
1279 offset = ac_build_imad(&ctx->ac, index, stride,
1280 LLVMConstInt(ctx->ac.i32, base_offset, false));
1281
1282 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1283 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1284 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1285
1286 return desc_ptr;
1287 }
1288
1289
1290 /* The offchip buffer layout for TCS->TES is
1291 *
1292 * - attribute 0 of patch 0 vertex 0
1293 * - attribute 0 of patch 0 vertex 1
1294 * - attribute 0 of patch 0 vertex 2
1295 * ...
1296 * - attribute 0 of patch 1 vertex 0
1297 * - attribute 0 of patch 1 vertex 1
1298 * ...
1299 * - attribute 1 of patch 0 vertex 0
1300 * - attribute 1 of patch 0 vertex 1
1301 * ...
1302 * - per patch attribute 0 of patch 0
1303 * - per patch attribute 0 of patch 1
1304 * ...
1305 *
1306 * Note that every attribute has 4 components.
1307 */
1308 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1309 {
1310 uint32_t num_patches = ctx->tcs_num_patches;
1311 uint32_t num_tcs_outputs;
1312 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1313 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1314 else
1315 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1316
1317 uint32_t output_vertex_size = num_tcs_outputs * 16;
1318 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1319
1320 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1321 }
1322
1323 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1324 LLVMValueRef vertex_index)
1325 {
1326 LLVMValueRef param_stride;
1327 if (vertex_index)
1328 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1329 else
1330 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1331 return param_stride;
1332 }
1333
1334 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1335 LLVMValueRef vertex_index,
1336 LLVMValueRef param_index)
1337 {
1338 LLVMValueRef base_addr;
1339 LLVMValueRef param_stride, constant16;
1340 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1341 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1342 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1343 param_stride = calc_param_stride(ctx, vertex_index);
1344 if (vertex_index) {
1345 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
1346 vertices_per_patch, vertex_index);
1347 } else {
1348 base_addr = rel_patch_id;
1349 }
1350
1351 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1352 LLVMBuildMul(ctx->ac.builder, param_index,
1353 param_stride, ""), "");
1354
1355 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1356
1357 if (!vertex_index) {
1358 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1359
1360 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1361 patch_data_offset, "");
1362 }
1363 return base_addr;
1364 }
1365
1366 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1367 unsigned param,
1368 unsigned const_index,
1369 bool is_compact,
1370 LLVMValueRef vertex_index,
1371 LLVMValueRef indir_index)
1372 {
1373 LLVMValueRef param_index;
1374
1375 if (indir_index)
1376 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1377 indir_index, "");
1378 else {
1379 if (const_index && !is_compact)
1380 param += const_index;
1381 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1382 }
1383 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1384 }
1385
1386 static LLVMValueRef
1387 get_dw_address(struct radv_shader_context *ctx,
1388 LLVMValueRef dw_addr,
1389 unsigned param,
1390 unsigned const_index,
1391 bool compact_const_index,
1392 LLVMValueRef vertex_index,
1393 LLVMValueRef stride,
1394 LLVMValueRef indir_index)
1395
1396 {
1397
1398 if (vertex_index) {
1399 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1400 LLVMBuildMul(ctx->ac.builder,
1401 vertex_index,
1402 stride, ""), "");
1403 }
1404
1405 if (indir_index)
1406 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1407 LLVMBuildMul(ctx->ac.builder, indir_index,
1408 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1409 else if (const_index && !compact_const_index)
1410 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1411 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1412
1413 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1414 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1415
1416 if (const_index && compact_const_index)
1417 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1418 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1419 return dw_addr;
1420 }
1421
1422 static LLVMValueRef
1423 load_tcs_varyings(struct ac_shader_abi *abi,
1424 LLVMTypeRef type,
1425 LLVMValueRef vertex_index,
1426 LLVMValueRef indir_index,
1427 unsigned const_index,
1428 unsigned location,
1429 unsigned driver_location,
1430 unsigned component,
1431 unsigned num_components,
1432 bool is_patch,
1433 bool is_compact,
1434 bool load_input)
1435 {
1436 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1437 LLVMValueRef dw_addr, stride;
1438 LLVMValueRef value[4], result;
1439 unsigned param = shader_io_get_unique_index(location);
1440
1441 if (load_input) {
1442 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1443 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1444 dw_addr = get_tcs_in_current_patch_offset(ctx);
1445 } else {
1446 if (!is_patch) {
1447 stride = get_tcs_out_vertex_stride(ctx);
1448 dw_addr = get_tcs_out_current_patch_offset(ctx);
1449 } else {
1450 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1451 stride = NULL;
1452 }
1453 }
1454
1455 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1456 indir_index);
1457
1458 for (unsigned i = 0; i < num_components + component; i++) {
1459 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1460 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1461 ctx->ac.i32_1, "");
1462 }
1463 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1464 return result;
1465 }
1466
1467 static void
1468 store_tcs_output(struct ac_shader_abi *abi,
1469 const nir_variable *var,
1470 LLVMValueRef vertex_index,
1471 LLVMValueRef param_index,
1472 unsigned const_index,
1473 LLVMValueRef src,
1474 unsigned writemask)
1475 {
1476 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1477 const unsigned location = var->data.location;
1478 const unsigned component = var->data.location_frac;
1479 const bool is_patch = var->data.patch;
1480 const bool is_compact = var->data.compact;
1481 LLVMValueRef dw_addr;
1482 LLVMValueRef stride = NULL;
1483 LLVMValueRef buf_addr = NULL;
1484 unsigned param;
1485 bool store_lds = true;
1486
1487 if (is_patch) {
1488 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1489 store_lds = false;
1490 } else {
1491 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1492 store_lds = false;
1493 }
1494
1495 param = shader_io_get_unique_index(location);
1496 if (location == VARYING_SLOT_CLIP_DIST0 &&
1497 is_compact && const_index > 3) {
1498 const_index -= 3;
1499 param++;
1500 }
1501
1502 if (!is_patch) {
1503 stride = get_tcs_out_vertex_stride(ctx);
1504 dw_addr = get_tcs_out_current_patch_offset(ctx);
1505 } else {
1506 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1507 }
1508
1509 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1510 param_index);
1511 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1512 vertex_index, param_index);
1513
1514 bool is_tess_factor = false;
1515 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1516 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1517 is_tess_factor = true;
1518
1519 unsigned base = is_compact ? const_index : 0;
1520 for (unsigned chan = 0; chan < 8; chan++) {
1521 if (!(writemask & (1 << chan)))
1522 continue;
1523 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1524 value = ac_to_integer(&ctx->ac, value);
1525 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
1526
1527 if (store_lds || is_tess_factor) {
1528 LLVMValueRef dw_addr_chan =
1529 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1530 LLVMConstInt(ctx->ac.i32, chan, false), "");
1531 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1532 }
1533
1534 if (!is_tess_factor && writemask != 0xF)
1535 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1536 buf_addr, ctx->oc_lds,
1537 4 * (base + chan), 1, 0, true, false);
1538 }
1539
1540 if (writemask == 0xF) {
1541 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1542 buf_addr, ctx->oc_lds,
1543 (base * 4), 1, 0, true, false);
1544 }
1545 }
1546
1547 static LLVMValueRef
1548 load_tes_input(struct ac_shader_abi *abi,
1549 LLVMTypeRef type,
1550 LLVMValueRef vertex_index,
1551 LLVMValueRef param_index,
1552 unsigned const_index,
1553 unsigned location,
1554 unsigned driver_location,
1555 unsigned component,
1556 unsigned num_components,
1557 bool is_patch,
1558 bool is_compact,
1559 bool load_input)
1560 {
1561 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1562 LLVMValueRef buf_addr;
1563 LLVMValueRef result;
1564 unsigned param = shader_io_get_unique_index(location);
1565
1566 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1567 const_index -= 3;
1568 param++;
1569 }
1570
1571 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1572 is_compact, vertex_index, param_index);
1573
1574 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1575 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1576
1577 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1578 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1579 result = ac_trim_vector(&ctx->ac, result, num_components);
1580 return result;
1581 }
1582
1583 static LLVMValueRef
1584 load_gs_input(struct ac_shader_abi *abi,
1585 unsigned location,
1586 unsigned driver_location,
1587 unsigned component,
1588 unsigned num_components,
1589 unsigned vertex_index,
1590 unsigned const_index,
1591 LLVMTypeRef type)
1592 {
1593 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1594 LLVMValueRef vtx_offset;
1595 unsigned param, vtx_offset_param;
1596 LLVMValueRef value[4], result;
1597
1598 vtx_offset_param = vertex_index;
1599 assert(vtx_offset_param < 6);
1600 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1601 LLVMConstInt(ctx->ac.i32, 4, false), "");
1602
1603 param = shader_io_get_unique_index(location);
1604
1605 for (unsigned i = component; i < num_components + component; i++) {
1606 if (ctx->ac.chip_class >= GFX9) {
1607 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1608 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1609 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1610 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1611 } else {
1612 LLVMValueRef soffset =
1613 LLVMConstInt(ctx->ac.i32,
1614 (param * 4 + i + const_index) * 256,
1615 false);
1616
1617 value[i] = ac_build_buffer_load(&ctx->ac,
1618 ctx->esgs_ring, 1,
1619 ctx->ac.i32_0,
1620 vtx_offset, soffset,
1621 0, 1, 0, true, false);
1622 }
1623
1624 if (ac_get_type_size(type) == 2) {
1625 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
1626 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
1627 }
1628 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
1629 }
1630 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1631 result = ac_to_integer(&ctx->ac, result);
1632 return result;
1633 }
1634
1635
1636 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1637 {
1638 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1639 ac_build_kill_if_false(&ctx->ac, visible);
1640 }
1641
1642 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1643 enum glsl_interp_mode interp, unsigned location)
1644 {
1645 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1646
1647 switch (interp) {
1648 case INTERP_MODE_FLAT:
1649 default:
1650 return NULL;
1651 case INTERP_MODE_SMOOTH:
1652 case INTERP_MODE_NONE:
1653 if (location == INTERP_CENTER)
1654 return ctx->persp_center;
1655 else if (location == INTERP_CENTROID)
1656 return ctx->persp_centroid;
1657 else if (location == INTERP_SAMPLE)
1658 return ctx->persp_sample;
1659 break;
1660 case INTERP_MODE_NOPERSPECTIVE:
1661 if (location == INTERP_CENTER)
1662 return ctx->linear_center;
1663 else if (location == INTERP_CENTROID)
1664 return ctx->linear_centroid;
1665 else if (location == INTERP_SAMPLE)
1666 return ctx->linear_sample;
1667 break;
1668 }
1669 return NULL;
1670 }
1671
1672 static uint32_t
1673 radv_get_sample_pos_offset(uint32_t num_samples)
1674 {
1675 uint32_t sample_pos_offset = 0;
1676
1677 switch (num_samples) {
1678 case 2:
1679 sample_pos_offset = 1;
1680 break;
1681 case 4:
1682 sample_pos_offset = 3;
1683 break;
1684 case 8:
1685 sample_pos_offset = 7;
1686 break;
1687 case 16:
1688 sample_pos_offset = 15;
1689 break;
1690 default:
1691 break;
1692 }
1693 return sample_pos_offset;
1694 }
1695
1696 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1697 LLVMValueRef sample_id)
1698 {
1699 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1700
1701 LLVMValueRef result;
1702 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1703
1704 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1705 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1706
1707 uint32_t sample_pos_offset =
1708 radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
1709
1710 sample_id =
1711 LLVMBuildAdd(ctx->ac.builder, sample_id,
1712 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
1713 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1714
1715 return result;
1716 }
1717
1718
1719 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1720 {
1721 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1722 uint8_t log2_ps_iter_samples;
1723
1724 if (ctx->shader_info->info.ps.force_persample) {
1725 log2_ps_iter_samples =
1726 util_logbase2(ctx->options->key.fs.num_samples);
1727 } else {
1728 log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
1729 }
1730
1731 /* The bit pattern matches that used by fixed function fragment
1732 * processing. */
1733 static const uint16_t ps_iter_masks[] = {
1734 0xffff, /* not used */
1735 0x5555,
1736 0x1111,
1737 0x0101,
1738 0x0001,
1739 };
1740 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1741
1742 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1743
1744 LLVMValueRef result, sample_id;
1745 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1746 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1747 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1748 return result;
1749 }
1750
1751
1752 static void
1753 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1754 {
1755 LLVMValueRef gs_next_vertex;
1756 LLVMValueRef can_emit;
1757 unsigned offset = 0;
1758 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1759
1760 /* Write vertex attribute values to GSVS ring */
1761 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1762 ctx->gs_next_vertex[stream],
1763 "");
1764
1765 /* If this thread has already emitted the declared maximum number of
1766 * vertices, kill it: excessive vertex emissions are not supposed to
1767 * have any effect, and GS threads have no externally observable
1768 * effects other than emitting vertices.
1769 */
1770 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1771 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1772 ac_build_kill_if_false(&ctx->ac, can_emit);
1773
1774 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1775 unsigned output_usage_mask =
1776 ctx->shader_info->info.gs.output_usage_mask[i];
1777 uint8_t output_stream =
1778 ctx->shader_info->info.gs.output_streams[i];
1779 LLVMValueRef *out_ptr = &addrs[i * 4];
1780 int length = util_last_bit(output_usage_mask);
1781
1782 if (!(ctx->output_mask & (1ull << i)) ||
1783 output_stream != stream)
1784 continue;
1785
1786 for (unsigned j = 0; j < length; j++) {
1787 if (!(output_usage_mask & (1 << j)))
1788 continue;
1789
1790 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1791 out_ptr[j], "");
1792 LLVMValueRef voffset =
1793 LLVMConstInt(ctx->ac.i32, offset *
1794 ctx->gs_max_out_vertices, false);
1795
1796 offset++;
1797
1798 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1799 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1800
1801 out_val = ac_to_integer(&ctx->ac, out_val);
1802 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1803
1804 ac_build_buffer_store_dword(&ctx->ac,
1805 ctx->gsvs_ring[stream],
1806 out_val, 1,
1807 voffset, ctx->gs2vs_offset, 0,
1808 1, 1, true, true);
1809 }
1810 }
1811
1812 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1813 ctx->ac.i32_1, "");
1814 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
1815
1816 ac_build_sendmsg(&ctx->ac,
1817 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
1818 ctx->gs_wave_id);
1819 }
1820
1821 static void
1822 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1823 {
1824 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1825 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1826 }
1827
1828 static LLVMValueRef
1829 load_tess_coord(struct ac_shader_abi *abi)
1830 {
1831 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1832
1833 LLVMValueRef coord[4] = {
1834 ctx->tes_u,
1835 ctx->tes_v,
1836 ctx->ac.f32_0,
1837 ctx->ac.f32_0,
1838 };
1839
1840 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1841 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1842 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1843
1844 return ac_build_gather_values(&ctx->ac, coord, 3);
1845 }
1846
1847 static LLVMValueRef
1848 load_patch_vertices_in(struct ac_shader_abi *abi)
1849 {
1850 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1851 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1852 }
1853
1854
1855 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1856 {
1857 return abi->base_vertex;
1858 }
1859
1860 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1861 LLVMValueRef buffer_ptr, bool write)
1862 {
1863 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1864 LLVMValueRef result;
1865
1866 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1867
1868 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1869 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1870
1871 return result;
1872 }
1873
1874 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1875 {
1876 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1877 LLVMValueRef result;
1878
1879 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1880
1881 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1882 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1883
1884 return result;
1885 }
1886
1887 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1888 unsigned descriptor_set,
1889 unsigned base_index,
1890 unsigned constant_index,
1891 LLVMValueRef index,
1892 enum ac_descriptor_type desc_type,
1893 bool image, bool write,
1894 bool bindless)
1895 {
1896 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1897 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1898 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1899 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1900 unsigned offset = binding->offset;
1901 unsigned stride = binding->size;
1902 unsigned type_size;
1903 LLVMBuilderRef builder = ctx->ac.builder;
1904 LLVMTypeRef type;
1905
1906 assert(base_index < layout->binding_count);
1907
1908 switch (desc_type) {
1909 case AC_DESC_IMAGE:
1910 type = ctx->ac.v8i32;
1911 type_size = 32;
1912 break;
1913 case AC_DESC_FMASK:
1914 type = ctx->ac.v8i32;
1915 offset += 32;
1916 type_size = 32;
1917 break;
1918 case AC_DESC_SAMPLER:
1919 type = ctx->ac.v4i32;
1920 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1921 offset += 64;
1922
1923 type_size = 16;
1924 break;
1925 case AC_DESC_BUFFER:
1926 type = ctx->ac.v4i32;
1927 type_size = 16;
1928 break;
1929 default:
1930 unreachable("invalid desc_type\n");
1931 }
1932
1933 offset += constant_index * stride;
1934
1935 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1936 (!index || binding->immutable_samplers_equal)) {
1937 if (binding->immutable_samplers_equal)
1938 constant_index = 0;
1939
1940 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1941
1942 LLVMValueRef constants[] = {
1943 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1944 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1945 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1946 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1947 };
1948 return ac_build_gather_values(&ctx->ac, constants, 4);
1949 }
1950
1951 assert(stride % type_size == 0);
1952
1953 if (!index)
1954 index = ctx->ac.i32_0;
1955
1956 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1957
1958 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1959 list = LLVMBuildPointerCast(builder, list,
1960 ac_array_in_const32_addr_space(type), "");
1961
1962 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1963 }
1964
1965 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1966 * so we may need to fix it up. */
1967 static LLVMValueRef
1968 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1969 unsigned adjustment,
1970 LLVMValueRef alpha)
1971 {
1972 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1973 return alpha;
1974
1975 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1976
1977 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1978 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1979 else
1980 alpha = ac_to_integer(&ctx->ac, alpha);
1981
1982 /* For the integer-like cases, do a natural sign extension.
1983 *
1984 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1985 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1986 * exponent.
1987 */
1988 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1989 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1990 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1991 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1992
1993 /* Convert back to the right type. */
1994 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1995 LLVMValueRef clamp;
1996 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1997 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1998 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1999 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
2000 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
2001 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
2002 }
2003
2004 return alpha;
2005 }
2006
2007 static void
2008 handle_vs_input_decl(struct radv_shader_context *ctx,
2009 struct nir_variable *variable)
2010 {
2011 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
2012 LLVMValueRef t_offset;
2013 LLVMValueRef t_list;
2014 LLVMValueRef input;
2015 LLVMValueRef buffer_index;
2016 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
2017 uint8_t input_usage_mask =
2018 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
2019 unsigned num_channels = util_last_bit(input_usage_mask);
2020
2021 variable->data.driver_location = variable->data.location * 4;
2022
2023 enum glsl_base_type type = glsl_get_base_type(variable->type);
2024 for (unsigned i = 0; i < attrib_count; ++i) {
2025 LLVMValueRef output[4];
2026 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
2027
2028 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
2029 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
2030
2031 if (divisor) {
2032 buffer_index = ctx->abi.instance_id;
2033
2034 if (divisor != 1) {
2035 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
2036 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
2037 }
2038
2039 if (ctx->options->key.vs.as_ls) {
2040 ctx->shader_info->vs.vgpr_comp_cnt =
2041 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
2042 } else {
2043 ctx->shader_info->vs.vgpr_comp_cnt =
2044 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
2045 }
2046 } else {
2047 buffer_index = ctx->ac.i32_0;
2048 }
2049
2050 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index, "");
2051 } else
2052 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
2053 ctx->abi.base_vertex, "");
2054 t_offset = LLVMConstInt(ctx->ac.i32, attrib_index, false);
2055
2056 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
2057
2058 input = ac_build_buffer_load_format(&ctx->ac, t_list,
2059 buffer_index,
2060 ctx->ac.i32_0,
2061 num_channels, false, true);
2062
2063 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
2064
2065 for (unsigned chan = 0; chan < 4; chan++) {
2066 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2067 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
2068 if (type == GLSL_TYPE_FLOAT16) {
2069 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
2070 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
2071 }
2072 }
2073
2074 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
2075 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
2076
2077 for (unsigned chan = 0; chan < 4; chan++) {
2078 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
2079 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
2080 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
2081
2082 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
2083 }
2084 }
2085 }
2086
2087 static void interp_fs_input(struct radv_shader_context *ctx,
2088 unsigned attr,
2089 LLVMValueRef interp_param,
2090 LLVMValueRef prim_mask,
2091 LLVMValueRef result[4])
2092 {
2093 LLVMValueRef attr_number;
2094 unsigned chan;
2095 LLVMValueRef i, j;
2096 bool interp = !LLVMIsUndef(interp_param);
2097
2098 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
2099
2100 /* fs.constant returns the param from the middle vertex, so it's not
2101 * really useful for flat shading. It's meant to be used for custom
2102 * interpolation (but the intrinsic can't fetch from the other two
2103 * vertices).
2104 *
2105 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2106 * to do the right thing. The only reason we use fs.constant is that
2107 * fs.interp cannot be used on integers, because they can be equal
2108 * to NaN.
2109 */
2110 if (interp) {
2111 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
2112 ctx->ac.v2f32, "");
2113
2114 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2115 ctx->ac.i32_0, "");
2116 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2117 ctx->ac.i32_1, "");
2118 }
2119
2120 for (chan = 0; chan < 4; chan++) {
2121 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2122
2123 if (interp) {
2124 result[chan] = ac_build_fs_interp(&ctx->ac,
2125 llvm_chan,
2126 attr_number,
2127 prim_mask, i, j);
2128 } else {
2129 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2130 LLVMConstInt(ctx->ac.i32, 2, false),
2131 llvm_chan,
2132 attr_number,
2133 prim_mask);
2134 result[chan] = LLVMBuildBitCast(ctx->ac.builder, result[chan], ctx->ac.i32, "");
2135 result[chan] = LLVMBuildTruncOrBitCast(ctx->ac.builder, result[chan], LLVMTypeOf(interp_param), "");
2136 }
2137 }
2138 }
2139
2140 static void
2141 handle_fs_input_decl(struct radv_shader_context *ctx,
2142 struct nir_variable *variable)
2143 {
2144 int idx = variable->data.location;
2145 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2146 LLVMValueRef interp = NULL;
2147 uint64_t mask;
2148
2149 variable->data.driver_location = idx * 4;
2150 mask = ((1ull << attrib_count) - 1) << variable->data.location;
2151
2152 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
2153 unsigned interp_type;
2154 if (variable->data.sample)
2155 interp_type = INTERP_SAMPLE;
2156 else if (variable->data.centroid)
2157 interp_type = INTERP_CENTROID;
2158 else
2159 interp_type = INTERP_CENTER;
2160
2161 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
2162 }
2163 bool is_16bit = glsl_type_is_16bit(variable->type);
2164 LLVMTypeRef type = is_16bit ? ctx->ac.i16 : ctx->ac.i32;
2165 if (interp == NULL)
2166 interp = LLVMGetUndef(type);
2167
2168 for (unsigned i = 0; i < attrib_count; ++i)
2169 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
2170
2171 if (idx == VARYING_SLOT_CLIP_DIST0) {
2172 /* Do not account for the number of components inside the array
2173 * of clip/cull distances because this might wrongly set other
2174 * bits like primitive ID or layer.
2175 */
2176 mask = 1ull << VARYING_SLOT_CLIP_DIST0;
2177 }
2178
2179 ctx->input_mask |= mask;
2180 }
2181
2182 static void
2183 handle_vs_inputs(struct radv_shader_context *ctx,
2184 struct nir_shader *nir) {
2185 nir_foreach_variable(variable, &nir->inputs)
2186 handle_vs_input_decl(ctx, variable);
2187 }
2188
2189 static void
2190 prepare_interp_optimize(struct radv_shader_context *ctx,
2191 struct nir_shader *nir)
2192 {
2193 bool uses_center = false;
2194 bool uses_centroid = false;
2195 nir_foreach_variable(variable, &nir->inputs) {
2196 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2197 variable->data.sample)
2198 continue;
2199
2200 if (variable->data.centroid)
2201 uses_centroid = true;
2202 else
2203 uses_center = true;
2204 }
2205
2206 if (uses_center && uses_centroid) {
2207 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2208 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
2209 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
2210 }
2211 }
2212
2213 static void
2214 handle_fs_inputs(struct radv_shader_context *ctx,
2215 struct nir_shader *nir)
2216 {
2217 prepare_interp_optimize(ctx, nir);
2218
2219 nir_foreach_variable(variable, &nir->inputs)
2220 handle_fs_input_decl(ctx, variable);
2221
2222 unsigned index = 0;
2223
2224 if (ctx->shader_info->info.ps.uses_input_attachments ||
2225 ctx->shader_info->info.needs_multiview_view_index) {
2226 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
2227 ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)] = LLVMGetUndef(ctx->ac.i32);
2228 }
2229
2230 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
2231 LLVMValueRef interp_param;
2232 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
2233
2234 if (!(ctx->input_mask & (1ull << i)))
2235 continue;
2236
2237 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
2238 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
2239 interp_param = *inputs;
2240 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
2241 inputs);
2242
2243 if (LLVMIsUndef(interp_param))
2244 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
2245 ++index;
2246 } else if (i == VARYING_SLOT_CLIP_DIST0) {
2247 int length = ctx->shader_info->info.ps.num_input_clips_culls;
2248
2249 for (unsigned j = 0; j < length; j += 4) {
2250 inputs = ctx->inputs + ac_llvm_reg_index_soa(i, j);
2251
2252 interp_param = *inputs;
2253 interp_fs_input(ctx, index, interp_param,
2254 ctx->abi.prim_mask, inputs);
2255 ++index;
2256 }
2257 } else if (i == VARYING_SLOT_POS) {
2258 for(int i = 0; i < 3; ++i)
2259 inputs[i] = ctx->abi.frag_pos[i];
2260
2261 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2262 ctx->abi.frag_pos[3]);
2263 }
2264 }
2265 ctx->shader_info->fs.num_interp = index;
2266 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
2267
2268 if (ctx->shader_info->info.needs_multiview_view_index)
2269 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2270 }
2271
2272 static void
2273 scan_shader_output_decl(struct radv_shader_context *ctx,
2274 struct nir_variable *variable,
2275 struct nir_shader *shader,
2276 gl_shader_stage stage)
2277 {
2278 int idx = variable->data.location + variable->data.index;
2279 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2280 uint64_t mask_attribs;
2281
2282 variable->data.driver_location = idx * 4;
2283
2284 /* tess ctrl has it's own load/store paths for outputs */
2285 if (stage == MESA_SHADER_TESS_CTRL)
2286 return;
2287
2288 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2289 if (stage == MESA_SHADER_VERTEX ||
2290 stage == MESA_SHADER_TESS_EVAL ||
2291 stage == MESA_SHADER_GEOMETRY) {
2292 if (idx == VARYING_SLOT_CLIP_DIST0) {
2293 if (stage == MESA_SHADER_VERTEX) {
2294 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2295 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2296 ctx->shader_info->vs.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
2297 }
2298 if (stage == MESA_SHADER_TESS_EVAL) {
2299 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2300 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2301 ctx->shader_info->tes.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
2302 }
2303
2304 mask_attribs = 1ull << idx;
2305 }
2306 }
2307
2308 ctx->output_mask |= mask_attribs;
2309 }
2310
2311
2312 /* Initialize arguments for the shader export intrinsic */
2313 static void
2314 si_llvm_init_export_args(struct radv_shader_context *ctx,
2315 LLVMValueRef *values,
2316 unsigned enabled_channels,
2317 unsigned target,
2318 struct ac_export_args *args)
2319 {
2320 /* Specify the channels that are enabled. */
2321 args->enabled_channels = enabled_channels;
2322
2323 /* Specify whether the EXEC mask represents the valid mask */
2324 args->valid_mask = 0;
2325
2326 /* Specify whether this is the last export */
2327 args->done = 0;
2328
2329 /* Specify the target we are exporting */
2330 args->target = target;
2331
2332 args->compr = false;
2333 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2334 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2335 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2336 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2337
2338 if (!values)
2339 return;
2340
2341 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
2342 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2343 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2344 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2345 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2346 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2347 unsigned chan;
2348
2349 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2350 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2351 unsigned bits, bool hi) = NULL;
2352
2353 switch(col_format) {
2354 case V_028714_SPI_SHADER_ZERO:
2355 args->enabled_channels = 0; /* writemask */
2356 args->target = V_008DFC_SQ_EXP_NULL;
2357 break;
2358
2359 case V_028714_SPI_SHADER_32_R:
2360 args->enabled_channels = 1;
2361 args->out[0] = values[0];
2362 break;
2363
2364 case V_028714_SPI_SHADER_32_GR:
2365 args->enabled_channels = 0x3;
2366 args->out[0] = values[0];
2367 args->out[1] = values[1];
2368 break;
2369
2370 case V_028714_SPI_SHADER_32_AR:
2371 args->enabled_channels = 0x9;
2372 args->out[0] = values[0];
2373 args->out[3] = values[3];
2374 break;
2375
2376 case V_028714_SPI_SHADER_FP16_ABGR:
2377 args->enabled_channels = 0x5;
2378 packf = ac_build_cvt_pkrtz_f16;
2379 if (is_16bit) {
2380 for (unsigned chan = 0; chan < 4; chan++)
2381 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
2382 values[chan],
2383 ctx->ac.f32, "");
2384 }
2385 break;
2386
2387 case V_028714_SPI_SHADER_UNORM16_ABGR:
2388 args->enabled_channels = 0x5;
2389 packf = ac_build_cvt_pknorm_u16;
2390 break;
2391
2392 case V_028714_SPI_SHADER_SNORM16_ABGR:
2393 args->enabled_channels = 0x5;
2394 packf = ac_build_cvt_pknorm_i16;
2395 break;
2396
2397 case V_028714_SPI_SHADER_UINT16_ABGR:
2398 args->enabled_channels = 0x5;
2399 packi = ac_build_cvt_pk_u16;
2400 if (is_16bit) {
2401 for (unsigned chan = 0; chan < 4; chan++)
2402 values[chan] = LLVMBuildZExt(ctx->ac.builder,
2403 values[chan],
2404 ctx->ac.i32, "");
2405 }
2406 break;
2407
2408 case V_028714_SPI_SHADER_SINT16_ABGR:
2409 args->enabled_channels = 0x5;
2410 packi = ac_build_cvt_pk_i16;
2411 if (is_16bit) {
2412 for (unsigned chan = 0; chan < 4; chan++)
2413 values[chan] = LLVMBuildSExt(ctx->ac.builder,
2414 values[chan],
2415 ctx->ac.i32, "");
2416 }
2417 break;
2418
2419 default:
2420 case V_028714_SPI_SHADER_32_ABGR:
2421 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2422 break;
2423 }
2424
2425 /* Pack f16 or norm_i16/u16. */
2426 if (packf) {
2427 for (chan = 0; chan < 2; chan++) {
2428 LLVMValueRef pack_args[2] = {
2429 values[2 * chan],
2430 values[2 * chan + 1]
2431 };
2432 LLVMValueRef packed;
2433
2434 packed = packf(&ctx->ac, pack_args);
2435 args->out[chan] = ac_to_float(&ctx->ac, packed);
2436 }
2437 args->compr = 1; /* COMPR flag */
2438 }
2439
2440 /* Pack i16/u16. */
2441 if (packi) {
2442 for (chan = 0; chan < 2; chan++) {
2443 LLVMValueRef pack_args[2] = {
2444 ac_to_integer(&ctx->ac, values[2 * chan]),
2445 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2446 };
2447 LLVMValueRef packed;
2448
2449 packed = packi(&ctx->ac, pack_args,
2450 is_int8 ? 8 : is_int10 ? 10 : 16,
2451 chan == 1);
2452 args->out[chan] = ac_to_float(&ctx->ac, packed);
2453 }
2454 args->compr = 1; /* COMPR flag */
2455 }
2456 return;
2457 }
2458
2459 if (is_16bit) {
2460 for (unsigned chan = 0; chan < 4; chan++) {
2461 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
2462 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
2463 }
2464 } else
2465 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2466
2467 for (unsigned i = 0; i < 4; ++i) {
2468 if (!(args->enabled_channels & (1 << i)))
2469 continue;
2470
2471 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2472 }
2473 }
2474
2475 static void
2476 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2477 LLVMValueRef *values, unsigned enabled_channels)
2478 {
2479 struct ac_export_args args;
2480
2481 si_llvm_init_export_args(ctx, values, enabled_channels,
2482 V_008DFC_SQ_EXP_PARAM + index, &args);
2483 ac_build_export(&ctx->ac, &args);
2484 }
2485
2486 static LLVMValueRef
2487 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2488 {
2489 LLVMValueRef output =
2490 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2491
2492 return LLVMBuildLoad(ctx->ac.builder, output, "");
2493 }
2494
2495 static void
2496 radv_emit_stream_output(struct radv_shader_context *ctx,
2497 LLVMValueRef const *so_buffers,
2498 LLVMValueRef const *so_write_offsets,
2499 const struct radv_stream_output *output)
2500 {
2501 unsigned num_comps = util_bitcount(output->component_mask);
2502 unsigned loc = output->location;
2503 unsigned buf = output->buffer;
2504 unsigned offset = output->offset;
2505 unsigned start;
2506 LLVMValueRef out[4];
2507
2508 assert(num_comps && num_comps <= 4);
2509 if (!num_comps || num_comps > 4)
2510 return;
2511
2512 /* Get the first component. */
2513 start = ffs(output->component_mask) - 1;
2514
2515 /* Adjust the destination offset. */
2516 offset += start * 4;
2517
2518 /* Load the output as int. */
2519 for (int i = 0; i < num_comps; i++) {
2520 out[i] = ac_to_integer(&ctx->ac,
2521 radv_load_output(ctx, loc, start + i));
2522 }
2523
2524 /* Pack the output. */
2525 LLVMValueRef vdata = NULL;
2526
2527 switch (num_comps) {
2528 case 1: /* as i32 */
2529 vdata = out[0];
2530 break;
2531 case 2: /* as v2i32 */
2532 case 3: /* as v4i32 (aligned to 4) */
2533 out[3] = LLVMGetUndef(ctx->ac.i32);
2534 /* fall through */
2535 case 4: /* as v4i32 */
2536 vdata = ac_build_gather_values(&ctx->ac, out,
2537 util_next_power_of_two(num_comps));
2538 break;
2539 }
2540
2541 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
2542 vdata, num_comps, so_write_offsets[buf],
2543 ctx->ac.i32_0, offset,
2544 1, 1, true, false);
2545 }
2546
2547 static void
2548 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
2549 {
2550 struct ac_build_if_state if_ctx;
2551 int i;
2552
2553 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2554 assert(ctx->streamout_config);
2555 LLVMValueRef so_vtx_count =
2556 ac_build_bfe(&ctx->ac, ctx->streamout_config,
2557 LLVMConstInt(ctx->ac.i32, 16, false),
2558 LLVMConstInt(ctx->ac.i32, 7, false), false);
2559
2560 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2561
2562 /* can_emit = tid < so_vtx_count; */
2563 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
2564 tid, so_vtx_count, "");
2565
2566 /* Emit the streamout code conditionally. This actually avoids
2567 * out-of-bounds buffer access. The hw tells us via the SGPR
2568 * (so_vtx_count) which threads are allowed to emit streamout data.
2569 */
2570 ac_nir_build_if(&if_ctx, ctx, can_emit);
2571 {
2572 /* The buffer offset is computed as follows:
2573 * ByteOffset = streamout_offset[buffer_id]*4 +
2574 * (streamout_write_index + thread_id)*stride[buffer_id] +
2575 * attrib_offset
2576 */
2577 LLVMValueRef so_write_index = ctx->streamout_write_idx;
2578
2579 /* Compute (streamout_write_index + thread_id). */
2580 so_write_index =
2581 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
2582
2583 /* Load the descriptor and compute the write offset for each
2584 * enabled buffer.
2585 */
2586 LLVMValueRef so_write_offset[4] = {};
2587 LLVMValueRef so_buffers[4] = {};
2588 LLVMValueRef buf_ptr = ctx->streamout_buffers;
2589
2590 for (i = 0; i < 4; i++) {
2591 uint16_t stride = ctx->shader_info->info.so.strides[i];
2592
2593 if (!stride)
2594 continue;
2595
2596 LLVMValueRef offset =
2597 LLVMConstInt(ctx->ac.i32, i, false);
2598
2599 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
2600 buf_ptr, offset);
2601
2602 LLVMValueRef so_offset = ctx->streamout_offset[i];
2603
2604 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
2605 LLVMConstInt(ctx->ac.i32, 4, false), "");
2606
2607 so_write_offset[i] =
2608 ac_build_imad(&ctx->ac, so_write_index,
2609 LLVMConstInt(ctx->ac.i32,
2610 stride * 4, false),
2611 so_offset);
2612 }
2613
2614 /* Write streamout data. */
2615 for (i = 0; i < ctx->shader_info->info.so.num_outputs; i++) {
2616 struct radv_stream_output *output =
2617 &ctx->shader_info->info.so.outputs[i];
2618
2619 if (stream != output->stream)
2620 continue;
2621
2622 radv_emit_stream_output(ctx, so_buffers,
2623 so_write_offset, output);
2624 }
2625 }
2626 ac_nir_build_endif(&if_ctx);
2627 }
2628
2629 static void
2630 handle_vs_outputs_post(struct radv_shader_context *ctx,
2631 bool export_prim_id, bool export_layer_id,
2632 struct radv_vs_output_info *outinfo)
2633 {
2634 uint32_t param_count = 0;
2635 unsigned target;
2636 unsigned pos_idx, num_pos_exports = 0;
2637 struct ac_export_args args, pos_args[4] = {};
2638 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2639 int i;
2640
2641 if (ctx->options->key.has_multiview_view_index) {
2642 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2643 if(!*tmp_out) {
2644 for(unsigned i = 0; i < 4; ++i)
2645 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2646 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2647 }
2648
2649 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2650 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2651 }
2652
2653 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2654 sizeof(outinfo->vs_output_param_offset));
2655
2656 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2657 unsigned output_usage_mask, length;
2658 LLVMValueRef slots[8];
2659 unsigned j;
2660
2661 if (ctx->stage == MESA_SHADER_VERTEX &&
2662 !ctx->is_gs_copy_shader) {
2663 output_usage_mask =
2664 ctx->shader_info->info.vs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2665 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2666 output_usage_mask =
2667 ctx->shader_info->info.tes.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2668 } else {
2669 assert(ctx->is_gs_copy_shader);
2670 output_usage_mask =
2671 ctx->shader_info->info.gs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2672 }
2673
2674 length = util_last_bit(output_usage_mask);
2675
2676 i = VARYING_SLOT_CLIP_DIST0;
2677 for (j = 0; j < length; j++)
2678 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2679
2680 for (i = length; i < 8; i++)
2681 slots[i] = LLVMGetUndef(ctx->ac.f32);
2682
2683 if (length > 4) {
2684 target = V_008DFC_SQ_EXP_POS + 3;
2685 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2686 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2687 &args, sizeof(args));
2688 }
2689
2690 target = V_008DFC_SQ_EXP_POS + 2;
2691 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2692 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2693 &args, sizeof(args));
2694
2695 /* Export the clip/cull distances values to the next stage. */
2696 radv_export_param(ctx, param_count, &slots[0], 0xf);
2697 outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0] = param_count++;
2698 if (length > 4) {
2699 radv_export_param(ctx, param_count, &slots[4], 0xf);
2700 outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1] = param_count++;
2701 }
2702 }
2703
2704 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2705 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2706 for (unsigned j = 0; j < 4; j++)
2707 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2708 }
2709 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2710
2711 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2712 outinfo->writes_pointsize = true;
2713 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2714 }
2715
2716 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2717 outinfo->writes_layer = true;
2718 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2719 }
2720
2721 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2722 outinfo->writes_viewport_index = true;
2723 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2724 }
2725
2726 if (ctx->shader_info->info.so.num_outputs &&
2727 !ctx->is_gs_copy_shader) {
2728 /* The GS copy shader emission already emits streamout. */
2729 radv_emit_streamout(ctx, 0);
2730 }
2731
2732 if (outinfo->writes_pointsize ||
2733 outinfo->writes_layer ||
2734 outinfo->writes_viewport_index) {
2735 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2736 (outinfo->writes_layer == true ? 4 : 0));
2737 pos_args[1].valid_mask = 0;
2738 pos_args[1].done = 0;
2739 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2740 pos_args[1].compr = 0;
2741 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2742 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2743 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2744 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2745
2746 if (outinfo->writes_pointsize == true)
2747 pos_args[1].out[0] = psize_value;
2748 if (outinfo->writes_layer == true)
2749 pos_args[1].out[2] = layer_value;
2750 if (outinfo->writes_viewport_index == true) {
2751 if (ctx->options->chip_class >= GFX9) {
2752 /* GFX9 has the layer in out.z[10:0] and the viewport
2753 * index in out.z[19:16].
2754 */
2755 LLVMValueRef v = viewport_index_value;
2756 v = ac_to_integer(&ctx->ac, v);
2757 v = LLVMBuildShl(ctx->ac.builder, v,
2758 LLVMConstInt(ctx->ac.i32, 16, false),
2759 "");
2760 v = LLVMBuildOr(ctx->ac.builder, v,
2761 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2762
2763 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2764 pos_args[1].enabled_channels |= 1 << 2;
2765 } else {
2766 pos_args[1].out[3] = viewport_index_value;
2767 pos_args[1].enabled_channels |= 1 << 3;
2768 }
2769 }
2770 }
2771 for (i = 0; i < 4; i++) {
2772 if (pos_args[i].out[0])
2773 num_pos_exports++;
2774 }
2775
2776 pos_idx = 0;
2777 for (i = 0; i < 4; i++) {
2778 if (!pos_args[i].out[0])
2779 continue;
2780
2781 /* Specify the target we are exporting */
2782 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2783 if (pos_idx == num_pos_exports)
2784 pos_args[i].done = 1;
2785 ac_build_export(&ctx->ac, &pos_args[i]);
2786 }
2787
2788 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2789 LLVMValueRef values[4];
2790 if (!(ctx->output_mask & (1ull << i)))
2791 continue;
2792
2793 if (i != VARYING_SLOT_LAYER &&
2794 i != VARYING_SLOT_PRIMITIVE_ID &&
2795 i < VARYING_SLOT_VAR0)
2796 continue;
2797
2798 for (unsigned j = 0; j < 4; j++)
2799 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2800
2801 unsigned output_usage_mask;
2802
2803 if (ctx->stage == MESA_SHADER_VERTEX &&
2804 !ctx->is_gs_copy_shader) {
2805 output_usage_mask =
2806 ctx->shader_info->info.vs.output_usage_mask[i];
2807 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2808 output_usage_mask =
2809 ctx->shader_info->info.tes.output_usage_mask[i];
2810 } else {
2811 assert(ctx->is_gs_copy_shader);
2812 output_usage_mask =
2813 ctx->shader_info->info.gs.output_usage_mask[i];
2814 }
2815
2816 radv_export_param(ctx, param_count, values, output_usage_mask);
2817
2818 outinfo->vs_output_param_offset[i] = param_count++;
2819 }
2820
2821 if (export_prim_id) {
2822 LLVMValueRef values[4];
2823
2824 values[0] = ctx->vs_prim_id;
2825 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2826 ctx->shader_info->vs.vgpr_comp_cnt);
2827 for (unsigned j = 1; j < 4; j++)
2828 values[j] = ctx->ac.f32_0;
2829
2830 radv_export_param(ctx, param_count, values, 0x1);
2831
2832 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2833 outinfo->export_prim_id = true;
2834 }
2835
2836 if (export_layer_id && layer_value) {
2837 LLVMValueRef values[4];
2838
2839 values[0] = layer_value;
2840 for (unsigned j = 1; j < 4; j++)
2841 values[j] = ctx->ac.f32_0;
2842
2843 radv_export_param(ctx, param_count, values, 0x1);
2844
2845 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2846 }
2847
2848 outinfo->pos_exports = num_pos_exports;
2849 outinfo->param_exports = param_count;
2850 }
2851
2852 static void
2853 handle_es_outputs_post(struct radv_shader_context *ctx,
2854 struct radv_es_output_info *outinfo)
2855 {
2856 int j;
2857 uint64_t max_output_written = 0;
2858 LLVMValueRef lds_base = NULL;
2859
2860 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2861 unsigned output_usage_mask;
2862 int param_index;
2863 int length = 4;
2864
2865 if (!(ctx->output_mask & (1ull << i)))
2866 continue;
2867
2868 if (ctx->stage == MESA_SHADER_VERTEX) {
2869 output_usage_mask =
2870 ctx->shader_info->info.vs.output_usage_mask[i];
2871 } else {
2872 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2873 output_usage_mask =
2874 ctx->shader_info->info.tes.output_usage_mask[i];
2875 }
2876
2877 if (i == VARYING_SLOT_CLIP_DIST0)
2878 length = util_last_bit(output_usage_mask);
2879
2880 param_index = shader_io_get_unique_index(i);
2881
2882 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2883 }
2884
2885 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2886
2887 if (ctx->ac.chip_class >= GFX9) {
2888 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2889 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2890 LLVMValueRef wave_idx = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
2891 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2892 LLVMBuildMul(ctx->ac.builder, wave_idx,
2893 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2894 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2895 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2896 }
2897
2898 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2899 LLVMValueRef dw_addr = NULL;
2900 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2901 unsigned output_usage_mask;
2902 int param_index;
2903 int length = 4;
2904
2905 if (!(ctx->output_mask & (1ull << i)))
2906 continue;
2907
2908 if (ctx->stage == MESA_SHADER_VERTEX) {
2909 output_usage_mask =
2910 ctx->shader_info->info.vs.output_usage_mask[i];
2911 } else {
2912 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2913 output_usage_mask =
2914 ctx->shader_info->info.tes.output_usage_mask[i];
2915 }
2916
2917 if (i == VARYING_SLOT_CLIP_DIST0)
2918 length = util_last_bit(output_usage_mask);
2919
2920 param_index = shader_io_get_unique_index(i);
2921
2922 if (lds_base) {
2923 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2924 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2925 "");
2926 }
2927
2928 for (j = 0; j < length; j++) {
2929 if (!(output_usage_mask & (1 << j)))
2930 continue;
2931
2932 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2933 out_val = ac_to_integer(&ctx->ac, out_val);
2934 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2935
2936 if (ctx->ac.chip_class >= GFX9) {
2937 LLVMValueRef dw_addr_offset =
2938 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2939 LLVMConstInt(ctx->ac.i32,
2940 j, false), "");
2941
2942 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2943 } else {
2944 ac_build_buffer_store_dword(&ctx->ac,
2945 ctx->esgs_ring,
2946 out_val, 1,
2947 NULL, ctx->es2gs_offset,
2948 (4 * param_index + j) * 4,
2949 1, 1, true, true);
2950 }
2951 }
2952 }
2953 }
2954
2955 static void
2956 handle_ls_outputs_post(struct radv_shader_context *ctx)
2957 {
2958 LLVMValueRef vertex_id = ctx->rel_auto_id;
2959 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2960 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2961 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2962 vertex_dw_stride, "");
2963
2964 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2965 unsigned output_usage_mask =
2966 ctx->shader_info->info.vs.output_usage_mask[i];
2967 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2968 int length = 4;
2969
2970 if (!(ctx->output_mask & (1ull << i)))
2971 continue;
2972
2973 if (i == VARYING_SLOT_CLIP_DIST0)
2974 length = util_last_bit(output_usage_mask);
2975
2976 int param = shader_io_get_unique_index(i);
2977 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2978 LLVMConstInt(ctx->ac.i32, param * 4, false),
2979 "");
2980 for (unsigned j = 0; j < length; j++) {
2981 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2982 value = ac_to_integer(&ctx->ac, value);
2983 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2984 ac_lds_store(&ctx->ac, dw_addr, value);
2985 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2986 }
2987 }
2988 }
2989
2990 static void
2991 write_tess_factors(struct radv_shader_context *ctx)
2992 {
2993 unsigned stride, outer_comps, inner_comps;
2994 struct ac_build_if_state if_ctx, inner_if_ctx;
2995 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2996 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2997 unsigned tess_inner_index = 0, tess_outer_index;
2998 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2999 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3000 int i;
3001 ac_emit_barrier(&ctx->ac, ctx->stage);
3002
3003 switch (ctx->options->key.tcs.primitive_mode) {
3004 case GL_ISOLINES:
3005 stride = 2;
3006 outer_comps = 2;
3007 inner_comps = 0;
3008 break;
3009 case GL_TRIANGLES:
3010 stride = 4;
3011 outer_comps = 3;
3012 inner_comps = 1;
3013 break;
3014 case GL_QUADS:
3015 stride = 6;
3016 outer_comps = 4;
3017 inner_comps = 2;
3018 break;
3019 default:
3020 return;
3021 }
3022
3023 ac_nir_build_if(&if_ctx, ctx,
3024 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3025 invocation_id, ctx->ac.i32_0, ""));
3026
3027 lds_base = get_tcs_out_current_patch_data_offset(ctx);
3028
3029 if (inner_comps) {
3030 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3031 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3032 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3033 }
3034
3035 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3036 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3037 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3038
3039 for (i = 0; i < 4; i++) {
3040 inner[i] = LLVMGetUndef(ctx->ac.i32);
3041 outer[i] = LLVMGetUndef(ctx->ac.i32);
3042 }
3043
3044 // LINES reversal
3045 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
3046 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3047 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3048 ctx->ac.i32_1, "");
3049 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3050 } else {
3051 for (i = 0; i < outer_comps; i++) {
3052 outer[i] = out[i] =
3053 ac_lds_load(&ctx->ac, lds_outer);
3054 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3055 ctx->ac.i32_1, "");
3056 }
3057 for (i = 0; i < inner_comps; i++) {
3058 inner[i] = out[outer_comps+i] =
3059 ac_lds_load(&ctx->ac, lds_inner);
3060 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3061 ctx->ac.i32_1, "");
3062 }
3063 }
3064
3065 /* Convert the outputs to vectors for stores. */
3066 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3067 vec1 = NULL;
3068
3069 if (stride > 4)
3070 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3071
3072
3073 buffer = ctx->hs_ring_tess_factor;
3074 tf_base = ctx->tess_factor_offset;
3075 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3076 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3077 unsigned tf_offset = 0;
3078
3079 if (ctx->options->chip_class <= VI) {
3080 ac_nir_build_if(&inner_if_ctx, ctx,
3081 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3082 rel_patch_id, ctx->ac.i32_0, ""));
3083
3084 /* Store the dynamic HS control word. */
3085 ac_build_buffer_store_dword(&ctx->ac, buffer,
3086 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3087 1, ctx->ac.i32_0, tf_base,
3088 0, 1, 0, true, false);
3089 tf_offset += 4;
3090
3091 ac_nir_build_endif(&inner_if_ctx);
3092 }
3093
3094 /* Store the tessellation factors. */
3095 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3096 MIN2(stride, 4), byteoffset, tf_base,
3097 tf_offset, 1, 0, true, false);
3098 if (vec1)
3099 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3100 stride - 4, byteoffset, tf_base,
3101 16 + tf_offset, 1, 0, true, false);
3102
3103 //store to offchip for TES to read - only if TES reads them
3104 if (ctx->options->key.tcs.tes_reads_tess_factors) {
3105 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3106 LLVMValueRef tf_inner_offset;
3107 unsigned param_outer, param_inner;
3108
3109 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3110 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3111 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3112
3113 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3114 util_next_power_of_two(outer_comps));
3115
3116 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3117 outer_comps, tf_outer_offset,
3118 ctx->oc_lds, 0, 1, 0, true, false);
3119 if (inner_comps) {
3120 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3121 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3122 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3123
3124 inner_vec = inner_comps == 1 ? inner[0] :
3125 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3126 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3127 inner_comps, tf_inner_offset,
3128 ctx->oc_lds, 0, 1, 0, true, false);
3129 }
3130 }
3131 ac_nir_build_endif(&if_ctx);
3132 }
3133
3134 static void
3135 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3136 {
3137 write_tess_factors(ctx);
3138 }
3139
3140 static bool
3141 si_export_mrt_color(struct radv_shader_context *ctx,
3142 LLVMValueRef *color, unsigned index,
3143 struct ac_export_args *args)
3144 {
3145 /* Export */
3146 si_llvm_init_export_args(ctx, color, 0xf,
3147 V_008DFC_SQ_EXP_MRT + index, args);
3148 if (!args->enabled_channels)
3149 return false; /* unnecessary NULL export */
3150
3151 return true;
3152 }
3153
3154 static void
3155 radv_export_mrt_z(struct radv_shader_context *ctx,
3156 LLVMValueRef depth, LLVMValueRef stencil,
3157 LLVMValueRef samplemask)
3158 {
3159 struct ac_export_args args;
3160
3161 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3162
3163 ac_build_export(&ctx->ac, &args);
3164 }
3165
3166 static void
3167 handle_fs_outputs_post(struct radv_shader_context *ctx)
3168 {
3169 unsigned index = 0;
3170 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3171 struct ac_export_args color_args[8];
3172
3173 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3174 LLVMValueRef values[4];
3175
3176 if (!(ctx->output_mask & (1ull << i)))
3177 continue;
3178
3179 if (i < FRAG_RESULT_DATA0)
3180 continue;
3181
3182 for (unsigned j = 0; j < 4; j++)
3183 values[j] = ac_to_float(&ctx->ac,
3184 radv_load_output(ctx, i, j));
3185
3186 bool ret = si_export_mrt_color(ctx, values,
3187 i - FRAG_RESULT_DATA0,
3188 &color_args[index]);
3189 if (ret)
3190 index++;
3191 }
3192
3193 /* Process depth, stencil, samplemask. */
3194 if (ctx->shader_info->info.ps.writes_z) {
3195 depth = ac_to_float(&ctx->ac,
3196 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3197 }
3198 if (ctx->shader_info->info.ps.writes_stencil) {
3199 stencil = ac_to_float(&ctx->ac,
3200 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3201 }
3202 if (ctx->shader_info->info.ps.writes_sample_mask) {
3203 samplemask = ac_to_float(&ctx->ac,
3204 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3205 }
3206
3207 /* Set the DONE bit on last non-null color export only if Z isn't
3208 * exported.
3209 */
3210 if (index > 0 &&
3211 !ctx->shader_info->info.ps.writes_z &&
3212 !ctx->shader_info->info.ps.writes_stencil &&
3213 !ctx->shader_info->info.ps.writes_sample_mask) {
3214 unsigned last = index - 1;
3215
3216 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3217 color_args[last].done = 1; /* DONE bit */
3218 }
3219
3220 /* Export PS outputs. */
3221 for (unsigned i = 0; i < index; i++)
3222 ac_build_export(&ctx->ac, &color_args[i]);
3223
3224 if (depth || stencil || samplemask)
3225 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3226 else if (!index)
3227 ac_build_export_null(&ctx->ac);
3228 }
3229
3230 static void
3231 emit_gs_epilogue(struct radv_shader_context *ctx)
3232 {
3233 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3234 }
3235
3236 static void
3237 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3238 LLVMValueRef *addrs)
3239 {
3240 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3241
3242 switch (ctx->stage) {
3243 case MESA_SHADER_VERTEX:
3244 if (ctx->options->key.vs.as_ls)
3245 handle_ls_outputs_post(ctx);
3246 else if (ctx->options->key.vs.as_es)
3247 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
3248 else
3249 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
3250 ctx->options->key.vs.export_layer_id,
3251 &ctx->shader_info->vs.outinfo);
3252 break;
3253 case MESA_SHADER_FRAGMENT:
3254 handle_fs_outputs_post(ctx);
3255 break;
3256 case MESA_SHADER_GEOMETRY:
3257 emit_gs_epilogue(ctx);
3258 break;
3259 case MESA_SHADER_TESS_CTRL:
3260 handle_tcs_outputs_post(ctx);
3261 break;
3262 case MESA_SHADER_TESS_EVAL:
3263 if (ctx->options->key.tes.as_es)
3264 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
3265 else
3266 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
3267 ctx->options->key.tes.export_layer_id,
3268 &ctx->shader_info->tes.outinfo);
3269 break;
3270 default:
3271 break;
3272 }
3273 }
3274
3275 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3276 LLVMPassManagerRef passmgr,
3277 const struct radv_nir_compiler_options *options)
3278 {
3279 LLVMRunPassManager(passmgr, ctx->ac.module);
3280 LLVMDisposeBuilder(ctx->ac.builder);
3281
3282 ac_llvm_context_dispose(&ctx->ac);
3283 }
3284
3285 static void
3286 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3287 {
3288 struct radv_vs_output_info *outinfo;
3289
3290 switch (ctx->stage) {
3291 case MESA_SHADER_FRAGMENT:
3292 case MESA_SHADER_COMPUTE:
3293 case MESA_SHADER_TESS_CTRL:
3294 case MESA_SHADER_GEOMETRY:
3295 return;
3296 case MESA_SHADER_VERTEX:
3297 if (ctx->options->key.vs.as_ls ||
3298 ctx->options->key.vs.as_es)
3299 return;
3300 outinfo = &ctx->shader_info->vs.outinfo;
3301 break;
3302 case MESA_SHADER_TESS_EVAL:
3303 if (ctx->options->key.vs.as_es)
3304 return;
3305 outinfo = &ctx->shader_info->tes.outinfo;
3306 break;
3307 default:
3308 unreachable("Unhandled shader type");
3309 }
3310
3311 ac_optimize_vs_outputs(&ctx->ac,
3312 ctx->main_function,
3313 outinfo->vs_output_param_offset,
3314 VARYING_SLOT_MAX,
3315 &outinfo->param_exports);
3316 }
3317
3318 static void
3319 ac_setup_rings(struct radv_shader_context *ctx)
3320 {
3321 if (ctx->options->chip_class <= VI &&
3322 (ctx->stage == MESA_SHADER_GEOMETRY ||
3323 ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
3324 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3325 : RING_ESGS_VS;
3326 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3327
3328 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3329 ctx->ring_offsets,
3330 offset);
3331 }
3332
3333 if (ctx->is_gs_copy_shader) {
3334 ctx->gsvs_ring[0] =
3335 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3336 LLVMConstInt(ctx->ac.i32,
3337 RING_GSVS_VS, false));
3338 }
3339
3340 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3341 /* The conceptual layout of the GSVS ring is
3342 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3343 * but the real memory layout is swizzled across
3344 * threads:
3345 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3346 * t16v0c0 ..
3347 * Override the buffer descriptor accordingly.
3348 */
3349 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3350 uint64_t stream_offset = 0;
3351 unsigned num_records = 64;
3352 LLVMValueRef base_ring;
3353
3354 base_ring =
3355 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3356 LLVMConstInt(ctx->ac.i32,
3357 RING_GSVS_GS, false));
3358
3359 for (unsigned stream = 0; stream < 4; stream++) {
3360 unsigned num_components, stride;
3361 LLVMValueRef ring, tmp;
3362
3363 num_components =
3364 ctx->shader_info->info.gs.num_stream_output_components[stream];
3365
3366 if (!num_components)
3367 continue;
3368
3369 stride = 4 * num_components * ctx->gs_max_out_vertices;
3370
3371 /* Limit on the stride field for <= CIK. */
3372 assert(stride < (1 << 14));
3373
3374 ring = LLVMBuildBitCast(ctx->ac.builder,
3375 base_ring, v2i64, "");
3376 tmp = LLVMBuildExtractElement(ctx->ac.builder,
3377 ring, ctx->ac.i32_0, "");
3378 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
3379 LLVMConstInt(ctx->ac.i64,
3380 stream_offset, 0), "");
3381 ring = LLVMBuildInsertElement(ctx->ac.builder,
3382 ring, tmp, ctx->ac.i32_0, "");
3383
3384 stream_offset += stride * 64;
3385
3386 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
3387 ctx->ac.v4i32, "");
3388
3389 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3390 ctx->ac.i32_1, "");
3391 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3392 LLVMConstInt(ctx->ac.i32,
3393 S_008F04_STRIDE(stride), false), "");
3394 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3395 ctx->ac.i32_1, "");
3396
3397 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3398 LLVMConstInt(ctx->ac.i32,
3399 num_records, false),
3400 LLVMConstInt(ctx->ac.i32, 2, false), "");
3401
3402 ctx->gsvs_ring[stream] = ring;
3403 }
3404 }
3405
3406 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3407 ctx->stage == MESA_SHADER_TESS_EVAL) {
3408 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3409 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3410 }
3411 }
3412
3413 static unsigned
3414 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
3415 const struct nir_shader *nir)
3416 {
3417 switch (nir->info.stage) {
3418 case MESA_SHADER_TESS_CTRL:
3419 return chip_class >= CIK ? 128 : 64;
3420 case MESA_SHADER_GEOMETRY:
3421 return chip_class >= GFX9 ? 128 : 64;
3422 case MESA_SHADER_COMPUTE:
3423 break;
3424 default:
3425 return 0;
3426 }
3427
3428 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
3429 nir->info.cs.local_size[1] *
3430 nir->info.cs.local_size[2];
3431 return max_workgroup_size;
3432 }
3433
3434 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3435 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3436 {
3437 LLVMValueRef count = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
3438 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3439 ctx->ac.i32_0, "");
3440 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
3441 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
3442 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3443 }
3444
3445 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3446 {
3447 for(int i = 5; i >= 0; --i) {
3448 ctx->gs_vtx_offset[i] = ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3449 (i & 1) * 16, 16);
3450 }
3451
3452 ctx->gs_wave_id = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 16, 8);
3453 }
3454
3455
3456 static
3457 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
3458 struct nir_shader *const *shaders,
3459 int shader_count,
3460 struct radv_shader_variant_info *shader_info,
3461 const struct radv_nir_compiler_options *options)
3462 {
3463 struct radv_shader_context ctx = {0};
3464 unsigned i;
3465 ctx.options = options;
3466 ctx.shader_info = shader_info;
3467
3468 ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
3469 ctx.context = ctx.ac.context;
3470 ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
3471
3472 enum ac_float_mode float_mode =
3473 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3474 AC_FLOAT_MODE_DEFAULT;
3475
3476 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3477
3478 memset(shader_info, 0, sizeof(*shader_info));
3479
3480 for(int i = 0; i < shader_count; ++i)
3481 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3482
3483 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3484 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3485 for (i = 0; i < AC_UD_MAX_UD; i++)
3486 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3487
3488 ctx.max_workgroup_size = 0;
3489 for (int i = 0; i < shader_count; ++i) {
3490 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3491 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3492 shaders[i]));
3493 }
3494
3495 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3496 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3497
3498 ctx.abi.inputs = &ctx.inputs[0];
3499 ctx.abi.emit_outputs = handle_shader_outputs_post;
3500 ctx.abi.emit_vertex = visit_emit_vertex;
3501 ctx.abi.load_ubo = radv_load_ubo;
3502 ctx.abi.load_ssbo = radv_load_ssbo;
3503 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3504 ctx.abi.load_resource = radv_load_resource;
3505 ctx.abi.clamp_shadow_reference = false;
3506 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9;
3507
3508 if (shader_count >= 2)
3509 ac_init_exec_full_mask(&ctx.ac);
3510
3511 if (ctx.ac.chip_class == GFX9 &&
3512 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3513 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3514
3515 for(int i = 0; i < shader_count; ++i) {
3516 ctx.stage = shaders[i]->info.stage;
3517 ctx.output_mask = 0;
3518
3519 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3520 for (int i = 0; i < 4; i++) {
3521 ctx.gs_next_vertex[i] =
3522 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
3523 }
3524 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3525 ctx.abi.load_inputs = load_gs_input;
3526 ctx.abi.emit_primitive = visit_end_primitive;
3527 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3528 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3529 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3530 ctx.abi.load_tess_varyings = load_tcs_varyings;
3531 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3532 ctx.abi.store_tcs_outputs = store_tcs_output;
3533 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3534 if (shader_count == 1)
3535 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3536 else
3537 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3538 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3539 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3540 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3541 ctx.abi.load_tess_varyings = load_tes_input;
3542 ctx.abi.load_tess_coord = load_tess_coord;
3543 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3544 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3545 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3546 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3547 if (shader_info->info.vs.needs_instance_id) {
3548 if (ctx.options->key.vs.as_ls) {
3549 ctx.shader_info->vs.vgpr_comp_cnt =
3550 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3551 } else {
3552 ctx.shader_info->vs.vgpr_comp_cnt =
3553 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3554 }
3555 }
3556 ctx.abi.load_base_vertex = radv_load_base_vertex;
3557 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3558 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3559 ctx.abi.lookup_interp_param = lookup_interp_param;
3560 ctx.abi.load_sample_position = load_sample_position;
3561 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3562 ctx.abi.emit_kill = radv_emit_kill;
3563 }
3564
3565 if (i)
3566 ac_emit_barrier(&ctx.ac, ctx.stage);
3567
3568 nir_foreach_variable(variable, &shaders[i]->outputs)
3569 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3570
3571 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3572 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3573 shaders[i]->info.cull_distance_array_size > 4;
3574 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3575 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3576 shaders[i]->info.gs.vertices_out;
3577 }
3578
3579 ac_setup_rings(&ctx);
3580
3581 LLVMBasicBlockRef merge_block;
3582 if (shader_count >= 2) {
3583 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3584 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3585 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3586
3587 LLVMValueRef count = ac_unpack_param(&ctx.ac, ctx.merged_wave_info, 8 * i, 8);
3588 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3589 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3590 thread_id, count, "");
3591 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3592
3593 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3594 }
3595
3596 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3597 handle_fs_inputs(&ctx, shaders[i]);
3598 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3599 handle_vs_inputs(&ctx, shaders[i]);
3600 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3601 prepare_gs_input_vgprs(&ctx);
3602
3603 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3604
3605 if (shader_count >= 2) {
3606 LLVMBuildBr(ctx.ac.builder, merge_block);
3607 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3608 }
3609
3610 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3611 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3612 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3613 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3614 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3615 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3616 }
3617 }
3618
3619 LLVMBuildRetVoid(ctx.ac.builder);
3620
3621 if (options->dump_preoptir)
3622 ac_dump_module(ctx.ac.module);
3623
3624 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
3625
3626 if (shader_count == 1)
3627 ac_nir_eliminate_const_vs_outputs(&ctx);
3628
3629 if (options->dump_shader) {
3630 ctx.shader_info->private_mem_vgprs =
3631 ac_count_scratch_private_memory(ctx.main_function);
3632 }
3633
3634 return ctx.ac.module;
3635 }
3636
3637 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3638 {
3639 unsigned *retval = (unsigned *)context;
3640 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3641 char *description = LLVMGetDiagInfoDescription(di);
3642
3643 if (severity == LLVMDSError) {
3644 *retval = 1;
3645 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3646 description);
3647 }
3648
3649 LLVMDisposeMessage(description);
3650 }
3651
3652 static unsigned ac_llvm_compile(LLVMModuleRef M,
3653 struct ac_shader_binary *binary,
3654 struct ac_llvm_compiler *ac_llvm)
3655 {
3656 unsigned retval = 0;
3657 LLVMContextRef llvm_ctx;
3658
3659 /* Setup Diagnostic Handler*/
3660 llvm_ctx = LLVMGetModuleContext(M);
3661
3662 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3663 &retval);
3664
3665 /* Compile IR*/
3666 if (!radv_compile_to_binary(ac_llvm, M, binary))
3667 retval = 1;
3668 return retval;
3669 }
3670
3671 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
3672 LLVMModuleRef llvm_module,
3673 struct ac_shader_binary *binary,
3674 struct ac_shader_config *config,
3675 struct radv_shader_variant_info *shader_info,
3676 gl_shader_stage stage,
3677 const struct radv_nir_compiler_options *options)
3678 {
3679 if (options->dump_shader)
3680 ac_dump_module(llvm_module);
3681
3682 memset(binary, 0, sizeof(*binary));
3683
3684 if (options->record_llvm_ir) {
3685 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3686 binary->llvm_ir_string = strdup(llvm_ir);
3687 LLVMDisposeMessage(llvm_ir);
3688 }
3689
3690 int v = ac_llvm_compile(llvm_module, binary, ac_llvm);
3691 if (v) {
3692 fprintf(stderr, "compile failed\n");
3693 }
3694
3695 if (options->dump_shader)
3696 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3697
3698 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3699
3700 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3701 LLVMDisposeModule(llvm_module);
3702 LLVMContextDispose(ctx);
3703
3704 if (stage == MESA_SHADER_FRAGMENT) {
3705 shader_info->num_input_vgprs = 0;
3706 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3707 shader_info->num_input_vgprs += 2;
3708 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3709 shader_info->num_input_vgprs += 2;
3710 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3711 shader_info->num_input_vgprs += 2;
3712 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3713 shader_info->num_input_vgprs += 3;
3714 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3715 shader_info->num_input_vgprs += 2;
3716 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3717 shader_info->num_input_vgprs += 2;
3718 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3719 shader_info->num_input_vgprs += 2;
3720 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3721 shader_info->num_input_vgprs += 1;
3722 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3723 shader_info->num_input_vgprs += 1;
3724 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3725 shader_info->num_input_vgprs += 1;
3726 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3727 shader_info->num_input_vgprs += 1;
3728 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3729 shader_info->num_input_vgprs += 1;
3730 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3731 shader_info->num_input_vgprs += 1;
3732 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3733 shader_info->num_input_vgprs += 1;
3734 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3735 shader_info->num_input_vgprs += 1;
3736 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3737 shader_info->num_input_vgprs += 1;
3738 }
3739 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3740
3741 /* +3 for scratch wave offset and VCC */
3742 config->num_sgprs = MAX2(config->num_sgprs,
3743 shader_info->num_input_sgprs + 3);
3744
3745 /* Enable 64-bit and 16-bit denormals, because there is no performance
3746 * cost.
3747 *
3748 * If denormals are enabled, all floating-point output modifiers are
3749 * ignored.
3750 *
3751 * Don't enable denormals for 32-bit floats, because:
3752 * - Floating-point output modifiers would be ignored by the hw.
3753 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3754 * have to stop using those.
3755 * - SI & CI would be very slow.
3756 */
3757 config->float_mode |= V_00B028_FP_64_DENORMS;
3758 }
3759
3760 static void
3761 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3762 {
3763 switch (nir->info.stage) {
3764 case MESA_SHADER_COMPUTE:
3765 for (int i = 0; i < 3; ++i)
3766 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3767 break;
3768 case MESA_SHADER_FRAGMENT:
3769 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3770 break;
3771 case MESA_SHADER_GEOMETRY:
3772 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3773 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3774 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3775 shader_info->gs.invocations = nir->info.gs.invocations;
3776 break;
3777 case MESA_SHADER_TESS_EVAL:
3778 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3779 shader_info->tes.spacing = nir->info.tess.spacing;
3780 shader_info->tes.ccw = nir->info.tess.ccw;
3781 shader_info->tes.point_mode = nir->info.tess.point_mode;
3782 shader_info->tes.as_es = options->key.tes.as_es;
3783 break;
3784 case MESA_SHADER_TESS_CTRL:
3785 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3786 break;
3787 case MESA_SHADER_VERTEX:
3788 shader_info->vs.as_es = options->key.vs.as_es;
3789 shader_info->vs.as_ls = options->key.vs.as_ls;
3790 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3791 if (options->key.vs.as_ls)
3792 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3793 break;
3794 default:
3795 break;
3796 }
3797 }
3798
3799 void
3800 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
3801 struct ac_shader_binary *binary,
3802 struct ac_shader_config *config,
3803 struct radv_shader_variant_info *shader_info,
3804 struct nir_shader *const *nir,
3805 int nir_count,
3806 const struct radv_nir_compiler_options *options)
3807 {
3808
3809 LLVMModuleRef llvm_module;
3810
3811 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, shader_info,
3812 options);
3813
3814 ac_compile_llvm_module(ac_llvm, llvm_module, binary, config, shader_info,
3815 nir[0]->info.stage, options);
3816
3817 for (int i = 0; i < nir_count; ++i)
3818 ac_fill_shader_info(shader_info, nir[i], options);
3819
3820 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3821 if (options->chip_class == GFX9) {
3822 if (nir_count == 2 &&
3823 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3824 shader_info->gs.es_type = nir[0]->info.stage;
3825 }
3826 }
3827 }
3828
3829 static void
3830 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3831 {
3832 LLVMValueRef vtx_offset =
3833 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3834 LLVMConstInt(ctx->ac.i32, 4, false), "");
3835 LLVMValueRef stream_id;
3836
3837 /* Fetch the vertex stream ID. */
3838 if (ctx->shader_info->info.so.num_outputs) {
3839 stream_id =
3840 ac_unpack_param(&ctx->ac, ctx->streamout_config, 24, 2);
3841 } else {
3842 stream_id = ctx->ac.i32_0;
3843 }
3844
3845 LLVMBasicBlockRef end_bb;
3846 LLVMValueRef switch_inst;
3847
3848 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
3849 ctx->main_function, "end");
3850 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
3851
3852 for (unsigned stream = 0; stream < 4; stream++) {
3853 unsigned num_components =
3854 ctx->shader_info->info.gs.num_stream_output_components[stream];
3855 LLVMBasicBlockRef bb;
3856 unsigned offset;
3857
3858 if (!num_components)
3859 continue;
3860
3861 if (stream > 0 && !ctx->shader_info->info.so.num_outputs)
3862 continue;
3863
3864 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
3865 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
3866 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
3867
3868 offset = 0;
3869 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3870 unsigned output_usage_mask =
3871 ctx->shader_info->info.gs.output_usage_mask[i];
3872 unsigned output_stream =
3873 ctx->shader_info->info.gs.output_streams[i];
3874 int length = util_last_bit(output_usage_mask);
3875
3876 if (!(ctx->output_mask & (1ull << i)) ||
3877 output_stream != stream)
3878 continue;
3879
3880 for (unsigned j = 0; j < length; j++) {
3881 LLVMValueRef value, soffset;
3882
3883 if (!(output_usage_mask & (1 << j)))
3884 continue;
3885
3886 soffset = LLVMConstInt(ctx->ac.i32,
3887 offset *
3888 ctx->gs_max_out_vertices * 16 * 4, false);
3889
3890 offset++;
3891
3892 value = ac_build_buffer_load(&ctx->ac,
3893 ctx->gsvs_ring[0],
3894 1, ctx->ac.i32_0,
3895 vtx_offset, soffset,
3896 0, 1, 1, true, false);
3897
3898 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3899 if (ac_get_type_size(type) == 2) {
3900 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
3901 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
3902 }
3903
3904 LLVMBuildStore(ctx->ac.builder,
3905 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3906 }
3907 }
3908
3909 if (ctx->shader_info->info.so.num_outputs)
3910 radv_emit_streamout(ctx, stream);
3911
3912 if (stream == 0) {
3913 handle_vs_outputs_post(ctx, false, false,
3914 &ctx->shader_info->vs.outinfo);
3915 }
3916
3917 LLVMBuildBr(ctx->ac.builder, end_bb);
3918 }
3919
3920 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
3921 }
3922
3923 void
3924 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
3925 struct nir_shader *geom_shader,
3926 struct ac_shader_binary *binary,
3927 struct ac_shader_config *config,
3928 struct radv_shader_variant_info *shader_info,
3929 const struct radv_nir_compiler_options *options)
3930 {
3931 struct radv_shader_context ctx = {0};
3932 ctx.options = options;
3933 ctx.shader_info = shader_info;
3934
3935 ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
3936 ctx.context = ctx.ac.context;
3937 ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
3938
3939 ctx.is_gs_copy_shader = true;
3940
3941 enum ac_float_mode float_mode =
3942 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3943 AC_FLOAT_MODE_DEFAULT;
3944
3945 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3946 ctx.stage = MESA_SHADER_VERTEX;
3947
3948 radv_nir_shader_info_pass(geom_shader, options, &shader_info->info);
3949
3950 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3951
3952 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3953 ac_setup_rings(&ctx);
3954
3955 nir_foreach_variable(variable, &geom_shader->outputs) {
3956 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3957 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3958 variable, MESA_SHADER_VERTEX);
3959 }
3960
3961 ac_gs_copy_shader_emit(&ctx);
3962
3963 LLVMBuildRetVoid(ctx.ac.builder);
3964
3965 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
3966
3967 ac_compile_llvm_module(ac_llvm, ctx.ac.module, binary, config, shader_info,
3968 MESA_SHADER_VERTEX, options);
3969 }