2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
50 struct radv_blend_state
{
51 uint32_t blend_enable_4bit
;
52 uint32_t need_src_alpha
;
54 uint32_t cb_color_control
;
55 uint32_t cb_target_mask
;
56 uint32_t cb_target_enabled_4bit
;
57 uint32_t sx_mrt_blend_opt
[8];
58 uint32_t cb_blend_control
[8];
60 uint32_t spi_shader_col_format
;
61 uint32_t col_format_is_int8
;
62 uint32_t col_format_is_int10
;
63 uint32_t cb_shader_mask
;
64 uint32_t db_alpha_to_mask
;
66 uint32_t commutative_4bit
;
68 bool single_cb_enable
;
69 bool mrt0_is_dual_src
;
72 struct radv_dsa_order_invariance
{
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
85 struct radv_tessellation_state
{
86 uint32_t ls_hs_config
;
92 static const VkPipelineMultisampleStateCreateInfo
*
93 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
95 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
96 return pCreateInfo
->pMultisampleState
;
100 static const VkPipelineTessellationStateCreateInfo
*
101 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
103 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
104 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
105 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
106 return pCreateInfo
->pTessellationState
;
112 static const VkPipelineDepthStencilStateCreateInfo
*
113 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
115 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
116 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
118 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
119 subpass
->depth_stencil_attachment
)
120 return pCreateInfo
->pDepthStencilState
;
124 static const VkPipelineColorBlendStateCreateInfo
*
125 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
127 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
128 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
130 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
131 subpass
->has_color_att
)
132 return pCreateInfo
->pColorBlendState
;
136 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
138 struct radv_shader_variant
*variant
= NULL
;
139 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
140 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
141 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
142 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
143 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
144 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
147 return variant
->info
.is_ngg
;
150 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
152 assert(radv_pipeline_has_ngg(pipeline
));
154 struct radv_shader_variant
*variant
= NULL
;
155 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
156 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
157 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
158 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
159 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
160 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
163 return variant
->info
.is_ngg_passthrough
;
166 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
168 if (!radv_pipeline_has_gs(pipeline
))
171 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
172 * On GFX10, it might be required in rare cases if it's not possible to
175 if (radv_pipeline_has_ngg(pipeline
))
178 assert(pipeline
->gs_copy_shader
);
183 radv_pipeline_destroy(struct radv_device
*device
,
184 struct radv_pipeline
*pipeline
,
185 const VkAllocationCallbacks
* allocator
)
187 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
188 if (pipeline
->shaders
[i
])
189 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
191 if (pipeline
->gs_copy_shader
)
192 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
195 free(pipeline
->cs
.buf
);
197 vk_object_base_finish(&pipeline
->base
);
198 vk_free2(&device
->vk
.alloc
, allocator
, pipeline
);
201 void radv_DestroyPipeline(
203 VkPipeline _pipeline
,
204 const VkAllocationCallbacks
* pAllocator
)
206 RADV_FROM_HANDLE(radv_device
, device
, _device
);
207 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
212 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
215 static uint32_t get_hash_flags(struct radv_device
*device
)
217 uint32_t hash_flags
= 0;
219 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
220 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
221 if (device
->physical_device
->cs_wave_size
== 32)
222 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
223 if (device
->physical_device
->ps_wave_size
== 32)
224 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
225 if (device
->physical_device
->ge_wave_size
== 32)
226 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
227 if (device
->physical_device
->use_llvm
)
228 hash_flags
|= RADV_HASH_SHADER_LLVM
;
233 radv_pipeline_scratch_init(struct radv_device
*device
,
234 struct radv_pipeline
*pipeline
)
236 unsigned scratch_bytes_per_wave
= 0;
237 unsigned max_waves
= 0;
238 unsigned min_waves
= 1;
240 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
241 if (pipeline
->shaders
[i
] &&
242 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
243 unsigned max_stage_waves
= device
->scratch_waves
;
245 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
246 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
248 max_stage_waves
= MIN2(max_stage_waves
,
249 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
250 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
251 max_waves
= MAX2(max_waves
, max_stage_waves
);
255 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
256 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
257 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
258 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
259 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
262 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
263 pipeline
->max_waves
= max_waves
;
267 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
270 case VK_LOGIC_OP_CLEAR
:
271 return V_028808_ROP3_CLEAR
;
272 case VK_LOGIC_OP_AND
:
273 return V_028808_ROP3_AND
;
274 case VK_LOGIC_OP_AND_REVERSE
:
275 return V_028808_ROP3_AND_REVERSE
;
276 case VK_LOGIC_OP_COPY
:
277 return V_028808_ROP3_COPY
;
278 case VK_LOGIC_OP_AND_INVERTED
:
279 return V_028808_ROP3_AND_INVERTED
;
280 case VK_LOGIC_OP_NO_OP
:
281 return V_028808_ROP3_NO_OP
;
282 case VK_LOGIC_OP_XOR
:
283 return V_028808_ROP3_XOR
;
285 return V_028808_ROP3_OR
;
286 case VK_LOGIC_OP_NOR
:
287 return V_028808_ROP3_NOR
;
288 case VK_LOGIC_OP_EQUIVALENT
:
289 return V_028808_ROP3_EQUIVALENT
;
290 case VK_LOGIC_OP_INVERT
:
291 return V_028808_ROP3_INVERT
;
292 case VK_LOGIC_OP_OR_REVERSE
:
293 return V_028808_ROP3_OR_REVERSE
;
294 case VK_LOGIC_OP_COPY_INVERTED
:
295 return V_028808_ROP3_COPY_INVERTED
;
296 case VK_LOGIC_OP_OR_INVERTED
:
297 return V_028808_ROP3_OR_INVERTED
;
298 case VK_LOGIC_OP_NAND
:
299 return V_028808_ROP3_NAND
;
300 case VK_LOGIC_OP_SET
:
301 return V_028808_ROP3_SET
;
303 unreachable("Unhandled logic op");
308 static uint32_t si_translate_blend_function(VkBlendOp op
)
311 case VK_BLEND_OP_ADD
:
312 return V_028780_COMB_DST_PLUS_SRC
;
313 case VK_BLEND_OP_SUBTRACT
:
314 return V_028780_COMB_SRC_MINUS_DST
;
315 case VK_BLEND_OP_REVERSE_SUBTRACT
:
316 return V_028780_COMB_DST_MINUS_SRC
;
317 case VK_BLEND_OP_MIN
:
318 return V_028780_COMB_MIN_DST_SRC
;
319 case VK_BLEND_OP_MAX
:
320 return V_028780_COMB_MAX_DST_SRC
;
326 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
329 case VK_BLEND_FACTOR_ZERO
:
330 return V_028780_BLEND_ZERO
;
331 case VK_BLEND_FACTOR_ONE
:
332 return V_028780_BLEND_ONE
;
333 case VK_BLEND_FACTOR_SRC_COLOR
:
334 return V_028780_BLEND_SRC_COLOR
;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
336 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
337 case VK_BLEND_FACTOR_DST_COLOR
:
338 return V_028780_BLEND_DST_COLOR
;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
340 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
341 case VK_BLEND_FACTOR_SRC_ALPHA
:
342 return V_028780_BLEND_SRC_ALPHA
;
343 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
344 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
345 case VK_BLEND_FACTOR_DST_ALPHA
:
346 return V_028780_BLEND_DST_ALPHA
;
347 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
348 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
349 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
350 return V_028780_BLEND_CONSTANT_COLOR
;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
353 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
354 return V_028780_BLEND_CONSTANT_ALPHA
;
355 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
356 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
358 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
359 case VK_BLEND_FACTOR_SRC1_COLOR
:
360 return V_028780_BLEND_SRC1_COLOR
;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
362 return V_028780_BLEND_INV_SRC1_COLOR
;
363 case VK_BLEND_FACTOR_SRC1_ALPHA
:
364 return V_028780_BLEND_SRC1_ALPHA
;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
366 return V_028780_BLEND_INV_SRC1_ALPHA
;
372 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
375 case VK_BLEND_OP_ADD
:
376 return V_028760_OPT_COMB_ADD
;
377 case VK_BLEND_OP_SUBTRACT
:
378 return V_028760_OPT_COMB_SUBTRACT
;
379 case VK_BLEND_OP_REVERSE_SUBTRACT
:
380 return V_028760_OPT_COMB_REVSUBTRACT
;
381 case VK_BLEND_OP_MIN
:
382 return V_028760_OPT_COMB_MIN
;
383 case VK_BLEND_OP_MAX
:
384 return V_028760_OPT_COMB_MAX
;
386 return V_028760_OPT_COMB_BLEND_DISABLED
;
390 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
393 case VK_BLEND_FACTOR_ZERO
:
394 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
395 case VK_BLEND_FACTOR_ONE
:
396 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
397 case VK_BLEND_FACTOR_SRC_COLOR
:
398 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
399 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
400 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
401 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
402 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
403 case VK_BLEND_FACTOR_SRC_ALPHA
:
404 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
405 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
406 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
407 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
408 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
409 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
411 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
419 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
420 unsigned *dst_factor
, unsigned expected_dst
,
421 unsigned replacement_src
)
423 if (*src_factor
== expected_dst
&&
424 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
425 *src_factor
= VK_BLEND_FACTOR_ZERO
;
426 *dst_factor
= replacement_src
;
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func
== VK_BLEND_OP_SUBTRACT
)
430 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
431 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
432 *func
= VK_BLEND_OP_SUBTRACT
;
436 static bool si_blend_factor_uses_dst(unsigned factor
)
438 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
439 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
440 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
441 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
442 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
445 static bool is_dual_src(VkBlendFactor factor
)
448 case VK_BLEND_FACTOR_SRC1_COLOR
:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
450 case VK_BLEND_FACTOR_SRC1_ALPHA
:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
458 static unsigned radv_choose_spi_color_format(VkFormat vk_format
,
460 bool blend_need_alpha
)
462 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
463 struct ac_spi_color_formats formats
= {};
464 unsigned format
, ntype
, swap
;
466 format
= radv_translate_colorformat(vk_format
);
467 ntype
= radv_translate_color_numformat(vk_format
, desc
,
468 vk_format_get_first_non_void_channel(vk_format
));
469 swap
= radv_translate_colorswap(vk_format
, false);
471 ac_choose_spi_color_formats(format
, swap
, ntype
, false, &formats
);
473 if (blend_enable
&& blend_need_alpha
)
474 return formats
.blend_alpha
;
475 else if(blend_need_alpha
)
476 return formats
.alpha
;
477 else if(blend_enable
)
478 return formats
.blend
;
480 return formats
.normal
;
484 format_is_int8(VkFormat format
)
486 const struct vk_format_description
*desc
= vk_format_description(format
);
487 int channel
= vk_format_get_first_non_void_channel(format
);
489 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
490 desc
->channel
[channel
].size
== 8;
494 format_is_int10(VkFormat format
)
496 const struct vk_format_description
*desc
= vk_format_description(format
);
498 if (desc
->nr_channels
!= 4)
500 for (unsigned i
= 0; i
< 4; i
++) {
501 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
508 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
509 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
510 struct radv_blend_state
*blend
)
512 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
513 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
514 unsigned col_format
= 0, is_int8
= 0, is_int10
= 0;
515 unsigned num_targets
;
517 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
520 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
||
521 !(blend
->cb_target_mask
& (0xfu
<< (i
* 4)))) {
522 cf
= V_028714_SPI_SHADER_ZERO
;
524 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
526 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
528 cf
= radv_choose_spi_color_format(attachment
->format
,
530 blend
->need_src_alpha
& (1 << i
));
532 if (format_is_int8(attachment
->format
))
534 if (format_is_int10(attachment
->format
))
538 col_format
|= cf
<< (4 * i
);
541 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
542 /* When a subpass doesn't have any color attachments, write the
543 * alpha channel of MRT0 when alpha coverage is enabled because
544 * the depth attachment needs it.
546 col_format
|= V_028714_SPI_SHADER_32_AR
;
549 /* If the i-th target format is set, all previous target formats must
550 * be non-zero to avoid hangs.
552 num_targets
= (util_last_bit(col_format
) + 3) / 4;
553 for (unsigned i
= 0; i
< num_targets
; i
++) {
554 if (!(col_format
& (0xf << (i
* 4)))) {
555 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
559 /* The output for dual source blending should have the same format as
562 if (blend
->mrt0_is_dual_src
)
563 col_format
|= (col_format
& 0xf) << 4;
565 blend
->spi_shader_col_format
= col_format
;
566 blend
->col_format_is_int8
= is_int8
;
567 blend
->col_format_is_int10
= is_int10
;
571 * Ordered so that for each i,
572 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
574 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
575 VK_FORMAT_R32_SFLOAT
,
576 VK_FORMAT_R32G32_SFLOAT
,
577 VK_FORMAT_R8G8B8A8_UNORM
,
578 VK_FORMAT_R16G16B16A16_UNORM
,
579 VK_FORMAT_R16G16B16A16_SNORM
,
580 VK_FORMAT_R16G16B16A16_UINT
,
581 VK_FORMAT_R16G16B16A16_SINT
,
582 VK_FORMAT_R32G32B32A32_SFLOAT
,
583 VK_FORMAT_R8G8B8A8_UINT
,
584 VK_FORMAT_R8G8B8A8_SINT
,
585 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
586 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
589 unsigned radv_format_meta_fs_key(VkFormat format
)
591 unsigned col_format
= radv_choose_spi_color_format(format
, false, false);
593 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
594 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
595 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
597 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
598 bool is_int8
= format_is_int8(format
);
599 bool is_int10
= format_is_int10(format
);
601 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
605 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
606 VkBlendOp op
, VkBlendFactor src
,
607 VkBlendFactor dst
, unsigned chanmask
)
609 /* Src factor is allowed when it does not depend on Dst. */
610 static const uint32_t src_allowed
=
611 (1u << VK_BLEND_FACTOR_ONE
) |
612 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
613 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
614 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
615 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
616 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
617 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
618 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
619 (1u << VK_BLEND_FACTOR_ZERO
) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
623 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
624 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
625 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
627 if (dst
== VK_BLEND_FACTOR_ONE
&&
628 (src_allowed
& (1u << src
))) {
629 /* Addition is commutative, but floating point addition isn't
630 * associative: subtle changes can be introduced via different
631 * rounding. Be conservative, only enable for min and max.
633 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
634 blend
->commutative_4bit
|= chanmask
;
638 static struct radv_blend_state
639 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
640 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
641 const struct radv_graphics_pipeline_create_info
*extra
)
643 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
644 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
645 struct radv_blend_state blend
= {0};
646 unsigned mode
= V_028808_CB_NORMAL
;
649 if (extra
&& extra
->custom_blend_mode
) {
650 blend
.single_cb_enable
= true;
651 mode
= extra
->custom_blend_mode
;
654 blend
.cb_color_control
= 0;
656 if (vkblend
->logicOpEnable
)
657 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
659 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
662 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
663 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
664 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
665 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
666 S_028B70_OFFSET_ROUND(1);
668 if (vkms
&& vkms
->alphaToCoverageEnable
) {
669 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
670 blend
.need_src_alpha
|= 0x1;
673 blend
.cb_target_mask
= 0;
675 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
676 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
677 unsigned blend_cntl
= 0;
678 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
679 VkBlendOp eqRGB
= att
->colorBlendOp
;
680 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
681 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
682 VkBlendOp eqA
= att
->alphaBlendOp
;
683 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
684 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
686 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
688 if (!att
->colorWriteMask
)
691 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
692 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
693 if (!att
->blendEnable
) {
694 blend
.cb_blend_control
[i
] = blend_cntl
;
698 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
700 blend
.mrt0_is_dual_src
= true;
702 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
703 srcRGB
= VK_BLEND_FACTOR_ONE
;
704 dstRGB
= VK_BLEND_FACTOR_ONE
;
706 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
707 srcA
= VK_BLEND_FACTOR_ONE
;
708 dstA
= VK_BLEND_FACTOR_ONE
;
711 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
713 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
716 /* Blending optimizations for RB+.
717 * These transformations don't change the behavior.
719 * First, get rid of DST in the blend factors:
720 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
722 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
723 VK_BLEND_FACTOR_DST_COLOR
,
724 VK_BLEND_FACTOR_SRC_COLOR
);
726 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
727 VK_BLEND_FACTOR_DST_COLOR
,
728 VK_BLEND_FACTOR_SRC_COLOR
);
730 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
731 VK_BLEND_FACTOR_DST_ALPHA
,
732 VK_BLEND_FACTOR_SRC_ALPHA
);
734 /* Look up the ideal settings from tables. */
735 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
736 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
737 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
738 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
740 /* Handle interdependencies. */
741 if (si_blend_factor_uses_dst(srcRGB
))
742 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
743 if (si_blend_factor_uses_dst(srcA
))
744 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
746 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
747 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
748 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
749 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
750 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
752 /* Set the final value. */
753 blend
.sx_mrt_blend_opt
[i
] =
754 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
755 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
756 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
757 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
758 S_028760_ALPHA_DST_OPT(dstA_opt
) |
759 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
760 blend_cntl
|= S_028780_ENABLE(1);
762 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
763 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
764 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
765 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
766 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
767 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
768 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
769 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
771 blend
.cb_blend_control
[i
] = blend_cntl
;
773 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
775 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
776 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
777 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
778 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
779 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
780 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
781 blend
.need_src_alpha
|= 1 << i
;
783 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
784 blend
.cb_blend_control
[i
] = 0;
785 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
789 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
790 /* Disable RB+ blend optimizations for dual source blending. */
791 if (blend
.mrt0_is_dual_src
) {
792 for (i
= 0; i
< 8; i
++) {
793 blend
.sx_mrt_blend_opt
[i
] =
794 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
795 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
799 /* RB+ doesn't work with dual source blending, logic op and
802 if (blend
.mrt0_is_dual_src
||
803 (vkblend
&& vkblend
->logicOpEnable
) ||
804 mode
== V_028808_CB_RESOLVE
)
805 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
808 if (blend
.cb_target_mask
)
809 blend
.cb_color_control
|= S_028808_MODE(mode
);
811 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
813 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
817 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
820 case VK_STENCIL_OP_KEEP
:
821 return V_02842C_STENCIL_KEEP
;
822 case VK_STENCIL_OP_ZERO
:
823 return V_02842C_STENCIL_ZERO
;
824 case VK_STENCIL_OP_REPLACE
:
825 return V_02842C_STENCIL_REPLACE_TEST
;
826 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
827 return V_02842C_STENCIL_ADD_CLAMP
;
828 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
829 return V_02842C_STENCIL_SUB_CLAMP
;
830 case VK_STENCIL_OP_INVERT
:
831 return V_02842C_STENCIL_INVERT
;
832 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
833 return V_02842C_STENCIL_ADD_WRAP
;
834 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
835 return V_02842C_STENCIL_SUB_WRAP
;
841 static uint32_t si_translate_fill(VkPolygonMode func
)
844 case VK_POLYGON_MODE_FILL
:
845 return V_028814_X_DRAW_TRIANGLES
;
846 case VK_POLYGON_MODE_LINE
:
847 return V_028814_X_DRAW_LINES
;
848 case VK_POLYGON_MODE_POINT
:
849 return V_028814_X_DRAW_POINTS
;
852 return V_028814_X_DRAW_POINTS
;
856 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
858 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
859 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
860 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
861 uint32_t ps_iter_samples
= 1;
862 uint32_t num_samples
;
864 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
866 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
867 * subpass uses color attachments, totalSamples is the number of
868 * samples of the color attachments. Otherwise, totalSamples is the
869 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
870 * specified at pipeline creation time."
872 if (subpass
->has_color_att
) {
873 num_samples
= subpass
->color_sample_count
;
875 num_samples
= vkms
->rasterizationSamples
;
878 if (vkms
->sampleShadingEnable
) {
879 ps_iter_samples
= ceilf(vkms
->minSampleShading
* num_samples
);
880 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
882 return ps_iter_samples
;
886 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
888 return pCreateInfo
->depthTestEnable
&&
889 pCreateInfo
->depthWriteEnable
&&
890 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
894 radv_writes_stencil(const VkStencilOpState
*state
)
896 return state
->writeMask
&&
897 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
898 state
->passOp
!= VK_STENCIL_OP_KEEP
||
899 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
903 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
905 return pCreateInfo
->stencilTestEnable
&&
906 (radv_writes_stencil(&pCreateInfo
->front
) ||
907 radv_writes_stencil(&pCreateInfo
->back
));
911 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
913 return radv_is_depth_write_enabled(pCreateInfo
) ||
914 radv_is_stencil_write_enabled(pCreateInfo
);
918 radv_order_invariant_stencil_op(VkStencilOp op
)
920 /* REPLACE is normally order invariant, except when the stencil
921 * reference value is written by the fragment shader. Tracking this
922 * interaction does not seem worth the effort, so be conservative.
924 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
925 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
926 op
!= VK_STENCIL_OP_REPLACE
;
930 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
932 /* Compute whether, assuming Z writes are disabled, this stencil state
933 * is order invariant in the sense that the set of passing fragments as
934 * well as the final stencil buffer result does not depend on the order
937 return !state
->writeMask
||
938 /* The following assumes that Z writes are disabled. */
939 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
940 radv_order_invariant_stencil_op(state
->passOp
) &&
941 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
942 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
943 radv_order_invariant_stencil_op(state
->failOp
));
947 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
948 struct radv_blend_state
*blend
,
949 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
951 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
952 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
953 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
954 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
955 unsigned colormask
= blend
->cb_target_enabled_4bit
;
957 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
960 /* Be conservative if a logic operation is enabled with color buffers. */
961 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
964 /* Default depth/stencil invariance when no attachment is bound. */
965 struct radv_dsa_order_invariance dsa_order_invariant
= {
966 .zs
= true, .pass_set
= true
970 struct radv_render_pass_attachment
*attachment
=
971 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
972 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
973 struct radv_dsa_order_invariance order_invariance
[2];
974 struct radv_shader_variant
*ps
=
975 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
977 /* Compute depth/stencil order invariance in order to know if
978 * it's safe to enable out-of-order.
980 bool zfunc_is_ordered
=
981 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
982 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
983 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
984 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
985 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
987 bool nozwrite_and_order_invariant_stencil
=
988 !radv_is_ds_write_enabled(vkds
) ||
989 (!radv_is_depth_write_enabled(vkds
) &&
990 radv_order_invariant_stencil_state(&vkds
->front
) &&
991 radv_order_invariant_stencil_state(&vkds
->back
));
993 order_invariance
[1].zs
=
994 nozwrite_and_order_invariant_stencil
||
995 (!radv_is_stencil_write_enabled(vkds
) &&
997 order_invariance
[0].zs
=
998 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1000 order_invariance
[1].pass_set
=
1001 nozwrite_and_order_invariant_stencil
||
1002 (!radv_is_stencil_write_enabled(vkds
) &&
1003 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1004 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1005 order_invariance
[0].pass_set
=
1006 !radv_is_depth_write_enabled(vkds
) ||
1007 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1008 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1010 dsa_order_invariant
= order_invariance
[has_stencil
];
1011 if (!dsa_order_invariant
.zs
)
1014 /* The set of PS invocations is always order invariant,
1015 * except when early Z/S tests are requested.
1018 ps
->info
.ps
.writes_memory
&&
1019 ps
->info
.ps
.early_fragment_test
&&
1020 !dsa_order_invariant
.pass_set
)
1023 /* Determine if out-of-order rasterization should be disabled
1024 * when occlusion queries are used.
1026 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1027 !dsa_order_invariant
.pass_set
;
1030 /* No color buffers are enabled for writing. */
1034 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1037 /* Only commutative blending. */
1038 if (blendmask
& ~blend
->commutative_4bit
)
1041 if (!dsa_order_invariant
.pass_set
)
1045 if (colormask
& ~blendmask
)
1052 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1053 struct radv_blend_state
*blend
,
1054 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1056 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1057 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1058 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1059 bool out_of_order_rast
= false;
1060 int ps_iter_samples
= 1;
1061 uint32_t mask
= 0xffff;
1064 ms
->num_samples
= vkms
->rasterizationSamples
;
1066 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1068 * "Sample shading is enabled for a graphics pipeline:
1070 * - If the interface of the fragment shader entry point of the
1071 * graphics pipeline includes an input variable decorated
1072 * with SampleId or SamplePosition. In this case
1073 * minSampleShadingFactor takes the value 1.0.
1074 * - Else if the sampleShadingEnable member of the
1075 * VkPipelineMultisampleStateCreateInfo structure specified
1076 * when creating the graphics pipeline is set to VK_TRUE. In
1077 * this case minSampleShadingFactor takes the value of
1078 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1080 * Otherwise, sample shading is considered disabled."
1082 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1083 ps_iter_samples
= ms
->num_samples
;
1085 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1088 ms
->num_samples
= 1;
1091 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1092 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1093 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1094 /* Out-of-order rasterization is explicitly enabled by the
1097 out_of_order_rast
= true;
1099 /* Determine if the driver can enable out-of-order
1100 * rasterization internally.
1103 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1106 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1107 ms
->pa_sc_aa_config
= 0;
1108 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1109 S_028804_INCOHERENT_EQAA_READS(1) |
1110 S_028804_INTERPOLATE_COMP_Z(1) |
1111 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1112 ms
->pa_sc_mode_cntl_1
=
1113 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1114 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1115 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1116 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1118 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1119 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1120 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1121 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1122 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1123 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1124 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1125 S_028A48_VPORT_SCISSOR_ENABLE(1);
1127 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1128 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1129 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1131 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1132 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1133 /* From the Vulkan spec 1.1.129:
1135 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1136 * are being rasterized, sample locations may all be
1137 * treated as being at the pixel center (this may
1138 * affect attribute and depth interpolation)."
1140 ms
->num_samples
= 1;
1144 if (ms
->num_samples
> 1) {
1145 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1146 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1147 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1148 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1149 unsigned log_z_samples
= util_logbase2(z_samples
);
1150 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1151 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1152 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1153 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1154 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1155 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1156 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1157 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1158 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1159 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
);
1160 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1161 if (ps_iter_samples
> 1)
1162 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1165 if (vkms
&& vkms
->pSampleMask
) {
1166 mask
= vkms
->pSampleMask
[0] & 0xffff;
1169 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1170 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1174 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1177 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1178 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1179 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1180 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1181 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1183 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1184 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1185 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1186 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1188 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1191 unreachable("unhandled primitive type");
1196 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1199 case 0: /* GL_POINTS */
1200 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1201 case 1: /* GL_LINES */
1202 case 3: /* GL_LINE_STRIP */
1203 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1204 case 0x8E7A: /* GL_ISOLINES */
1205 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1207 case 4: /* GL_TRIANGLES */
1208 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1209 case 5: /* GL_TRIANGLE_STRIP */
1210 case 7: /* GL_QUADS */
1211 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1219 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1222 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1223 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1224 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1225 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1226 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1227 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1228 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1229 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1230 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1231 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1232 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1234 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1235 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1242 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1245 case VK_DYNAMIC_STATE_VIEWPORT
:
1246 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT
:
1247 return RADV_DYNAMIC_VIEWPORT
;
1248 case VK_DYNAMIC_STATE_SCISSOR
:
1249 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT
:
1250 return RADV_DYNAMIC_SCISSOR
;
1251 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1252 return RADV_DYNAMIC_LINE_WIDTH
;
1253 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1254 return RADV_DYNAMIC_DEPTH_BIAS
;
1255 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1256 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1257 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1258 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1259 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1260 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1261 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1262 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1263 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1264 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1265 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1266 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1267 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1268 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1269 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1270 return RADV_DYNAMIC_LINE_STIPPLE
;
1271 case VK_DYNAMIC_STATE_CULL_MODE_EXT
:
1272 return RADV_DYNAMIC_CULL_MODE
;
1273 case VK_DYNAMIC_STATE_FRONT_FACE_EXT
:
1274 return RADV_DYNAMIC_FRONT_FACE
;
1275 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT
:
1276 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
;
1278 unreachable("Unhandled dynamic state");
1282 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1284 uint32_t states
= RADV_DYNAMIC_ALL
;
1286 /* If rasterization is disabled we do not care about any of the
1287 * dynamic states, since they are all rasterization related only,
1288 * except primitive topology.
1290 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1291 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
;
1293 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1294 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1296 if (!pCreateInfo
->pDepthStencilState
||
1297 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1298 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1300 if (!pCreateInfo
->pDepthStencilState
||
1301 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1302 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1303 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1304 RADV_DYNAMIC_STENCIL_REFERENCE
);
1306 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1307 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1309 if (!pCreateInfo
->pMultisampleState
||
1310 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1311 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1312 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1314 if (!pCreateInfo
->pRasterizationState
||
1315 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1316 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1317 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1319 /* TODO: blend constants & line width. */
1326 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1327 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1328 const struct radv_graphics_pipeline_create_info
*extra
)
1330 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1331 uint32_t states
= needed_states
;
1332 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1333 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1335 pipeline
->dynamic_state
= default_dynamic_state
;
1336 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1338 if (pCreateInfo
->pDynamicState
) {
1339 /* Remove all of the states that are marked as dynamic */
1340 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1341 for (uint32_t s
= 0; s
< count
; s
++)
1342 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1345 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1347 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1348 assert(pCreateInfo
->pViewportState
);
1350 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1351 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1352 typed_memcpy(dynamic
->viewport
.viewports
,
1353 pCreateInfo
->pViewportState
->pViewports
,
1354 pCreateInfo
->pViewportState
->viewportCount
);
1358 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1359 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1360 if (states
& RADV_DYNAMIC_SCISSOR
) {
1361 typed_memcpy(dynamic
->scissor
.scissors
,
1362 pCreateInfo
->pViewportState
->pScissors
,
1363 pCreateInfo
->pViewportState
->scissorCount
);
1367 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1368 assert(pCreateInfo
->pRasterizationState
);
1369 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1372 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1373 assert(pCreateInfo
->pRasterizationState
);
1374 dynamic
->depth_bias
.bias
=
1375 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1376 dynamic
->depth_bias
.clamp
=
1377 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1378 dynamic
->depth_bias
.slope
=
1379 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1382 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1384 * pColorBlendState is [...] NULL if the pipeline has rasterization
1385 * disabled or if the subpass of the render pass the pipeline is
1386 * created against does not use any color attachments.
1388 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1389 assert(pCreateInfo
->pColorBlendState
);
1390 typed_memcpy(dynamic
->blend_constants
,
1391 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1394 if (states
& RADV_DYNAMIC_CULL_MODE
) {
1395 dynamic
->cull_mode
=
1396 pCreateInfo
->pRasterizationState
->cullMode
;
1399 if (states
& RADV_DYNAMIC_FRONT_FACE
) {
1400 dynamic
->front_face
=
1401 pCreateInfo
->pRasterizationState
->frontFace
;
1404 if (states
& RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
) {
1405 dynamic
->primitive_topology
=
1406 si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
1407 if (extra
&& extra
->use_rectlist
) {
1408 dynamic
->primitive_topology
= V_008958_DI_PT_RECTLIST
;
1412 /* If there is no depthstencil attachment, then don't read
1413 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1414 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1415 * no need to override the depthstencil defaults in
1416 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1418 * Section 9.2 of the Vulkan 1.0.15 spec says:
1420 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1421 * disabled or if the subpass of the render pass the pipeline is created
1422 * against does not use a depth/stencil attachment.
1424 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1425 assert(pCreateInfo
->pDepthStencilState
);
1427 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1428 dynamic
->depth_bounds
.min
=
1429 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1430 dynamic
->depth_bounds
.max
=
1431 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1434 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1435 dynamic
->stencil_compare_mask
.front
=
1436 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1437 dynamic
->stencil_compare_mask
.back
=
1438 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1441 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1442 dynamic
->stencil_write_mask
.front
=
1443 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1444 dynamic
->stencil_write_mask
.back
=
1445 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1448 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1449 dynamic
->stencil_reference
.front
=
1450 pCreateInfo
->pDepthStencilState
->front
.reference
;
1451 dynamic
->stencil_reference
.back
=
1452 pCreateInfo
->pDepthStencilState
->back
.reference
;
1456 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1457 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1458 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1459 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1460 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1461 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1462 discard_rectangle_info
->pDiscardRectangles
,
1463 discard_rectangle_info
->discardRectangleCount
);
1467 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1468 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1469 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1470 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1471 /* If sampleLocationsEnable is VK_FALSE, the default sample
1472 * locations are used and the values specified in
1473 * sampleLocationsInfo are ignored.
1475 if (sample_location_info
->sampleLocationsEnable
) {
1476 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1477 &sample_location_info
->sampleLocationsInfo
;
1479 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1481 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1482 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1483 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1484 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1485 pSampleLocationsInfo
->pSampleLocations
,
1486 pSampleLocationsInfo
->sampleLocationsCount
);
1490 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1491 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1492 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1493 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1494 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1495 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1498 pipeline
->dynamic_state
.mask
= states
;
1502 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1503 const struct radv_pipeline
*pipeline
,
1505 struct radv_shader_info
*infos
,
1506 struct gfx9_gs_info
*out
)
1508 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1509 struct radv_es_output_info
*es_info
;
1510 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1511 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1513 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1514 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1515 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1517 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1518 bool uses_adjacency
;
1519 switch(key
->topology
) {
1520 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1521 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1522 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1523 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1524 uses_adjacency
= true;
1527 uses_adjacency
= false;
1531 /* All these are in dwords: */
1532 /* We can't allow using the whole LDS, because GS waves compete with
1533 * other shader stages for LDS space. */
1534 const unsigned max_lds_size
= 8 * 1024;
1535 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1536 unsigned esgs_lds_size
;
1538 /* All these are per subgroup: */
1539 const unsigned max_out_prims
= 32 * 1024;
1540 const unsigned max_es_verts
= 255;
1541 const unsigned ideal_gs_prims
= 64;
1542 unsigned max_gs_prims
, gs_prims
;
1543 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1545 if (uses_adjacency
|| gs_num_invocations
> 1)
1546 max_gs_prims
= 127 / gs_num_invocations
;
1550 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1551 * Make sure we don't go over the maximum value.
1553 if (gs_info
->gs
.vertices_out
> 0) {
1554 max_gs_prims
= MIN2(max_gs_prims
,
1556 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1558 assert(max_gs_prims
> 0);
1560 /* If the primitive has adjacency, halve the number of vertices
1561 * that will be reused in multiple primitives.
1563 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1565 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1566 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1568 /* Compute ESGS LDS size based on the worst case number of ES vertices
1569 * needed to create the target number of GS prims per subgroup.
1571 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1573 /* If total LDS usage is too big, refactor partitions based on ratio
1574 * of ESGS item sizes.
1576 if (esgs_lds_size
> max_lds_size
) {
1577 /* Our target GS Prims Per Subgroup was too large. Calculate
1578 * the maximum number of GS Prims Per Subgroup that will fit
1579 * into LDS, capped by the maximum that the hardware can support.
1581 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1583 assert(gs_prims
> 0);
1584 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1587 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1588 assert(esgs_lds_size
<= max_lds_size
);
1591 /* Now calculate remaining ESGS information. */
1593 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1595 es_verts
= max_es_verts
;
1597 /* Vertices for adjacency primitives are not always reused, so restore
1598 * it for ES_VERTS_PER_SUBGRP.
1600 min_es_verts
= gs_info
->gs
.vertices_in
;
1602 /* For normal primitives, the VGT only checks if they are past the ES
1603 * verts per subgroup after allocating a full GS primitive and if they
1604 * are, kick off a new subgroup. But if those additional ES verts are
1605 * unique (e.g. not reused) we need to make sure there is enough LDS
1606 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1608 es_verts
-= min_es_verts
- 1;
1610 uint32_t es_verts_per_subgroup
= es_verts
;
1611 uint32_t gs_prims_per_subgroup
= gs_prims
;
1612 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1613 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1614 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1615 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1616 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1617 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1618 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1619 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1620 assert(max_prims_per_subgroup
<= max_out_prims
);
1623 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1624 unsigned min_verts_per_prim
, bool use_adjacency
)
1626 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1629 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1633 radv_get_num_input_vertices(nir_shader
**nir
)
1635 if (nir
[MESA_SHADER_GEOMETRY
]) {
1636 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1638 return gs
->info
.gs
.vertices_in
;
1641 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1642 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1644 if (tes
->info
.tess
.point_mode
)
1646 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1655 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1656 struct radv_pipeline
*pipeline
,
1658 struct radv_shader_info
*infos
,
1659 struct gfx10_ngg_info
*ngg
)
1661 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1662 struct radv_es_output_info
*es_info
=
1663 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1664 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1665 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1666 unsigned min_verts_per_prim
=
1667 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1668 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1669 bool uses_adjacency
;
1670 switch(key
->topology
) {
1671 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1672 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1673 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1674 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1675 uses_adjacency
= true;
1678 uses_adjacency
= false;
1682 /* All these are in dwords: */
1683 /* We can't allow using the whole LDS, because GS waves compete with
1684 * other shader stages for LDS space.
1686 * TODO: We should really take the shader's internal LDS use into
1687 * account. The linker will fail if the size is greater than
1690 const unsigned max_lds_size
= 8 * 1024 - 768;
1691 const unsigned target_lds_size
= max_lds_size
;
1692 unsigned esvert_lds_size
= 0;
1693 unsigned gsprim_lds_size
= 0;
1695 /* All these are per subgroup: */
1696 bool max_vert_out_per_gs_instance
= false;
1697 unsigned max_esverts_base
= 256;
1698 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1700 /* Hardware has the following non-natural restrictions on the value
1701 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1703 * - at most 252 for any line input primitive type
1704 * - at most 251 for any quad input primitive type
1705 * - at most 251 for triangle strips with adjacency (this happens to
1706 * be the natural limit for triangle *lists* with adjacency)
1708 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1710 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1711 unsigned max_out_verts_per_gsprim
=
1712 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1714 if (max_out_verts_per_gsprim
<= 256) {
1715 if (max_out_verts_per_gsprim
) {
1716 max_gsprims_base
= MIN2(max_gsprims_base
,
1717 256 / max_out_verts_per_gsprim
);
1720 /* Use special multi-cycling mode in which each GS
1721 * instance gets its own subgroup. Does not work with
1723 max_vert_out_per_gs_instance
= true;
1724 max_gsprims_base
= 1;
1725 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1728 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1729 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1732 /* LDS size for passing data from GS to ES. */
1733 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1734 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1735 : &infos
[MESA_SHADER_VERTEX
].so
;
1737 if (so_info
->num_outputs
)
1738 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1740 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1741 * corresponding to the ES thread of the provoking vertex. All
1742 * ES threads load and export PrimitiveID for their thread.
1744 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1745 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1746 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1749 unsigned max_gsprims
= max_gsprims_base
;
1750 unsigned max_esverts
= max_esverts_base
;
1752 if (esvert_lds_size
)
1753 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1754 if (gsprim_lds_size
)
1755 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1757 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1758 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1759 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1761 if (esvert_lds_size
|| gsprim_lds_size
) {
1762 /* Now that we have a rough proportionality between esverts
1763 * and gsprims based on the primitive type, scale both of them
1764 * down simultaneously based on required LDS space.
1766 * We could be smarter about this if we knew how much vertex
1769 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1770 max_gsprims
* gsprim_lds_size
;
1771 if (lds_total
> target_lds_size
) {
1772 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1773 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1775 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1776 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1777 min_verts_per_prim
, uses_adjacency
);
1778 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1782 /* Round up towards full wave sizes for better ALU utilization. */
1783 if (!max_vert_out_per_gs_instance
) {
1784 unsigned orig_max_esverts
;
1785 unsigned orig_max_gsprims
;
1788 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1789 wavesize
= gs_info
->wave_size
;
1791 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1792 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1793 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1797 orig_max_esverts
= max_esverts
;
1798 orig_max_gsprims
= max_gsprims
;
1800 max_esverts
= align(max_esverts
, wavesize
);
1801 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1802 if (esvert_lds_size
)
1803 max_esverts
= MIN2(max_esverts
,
1804 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1806 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1808 max_gsprims
= align(max_gsprims
, wavesize
);
1809 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1810 if (gsprim_lds_size
)
1811 max_gsprims
= MIN2(max_gsprims
,
1812 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1814 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1815 min_verts_per_prim
, uses_adjacency
);
1816 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1817 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1820 /* Hardware restriction: minimum value of max_esverts */
1821 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1823 unsigned max_out_vertices
=
1824 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1825 gs_type
== MESA_SHADER_GEOMETRY
?
1826 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1828 assert(max_out_vertices
<= 256);
1830 unsigned prim_amp_factor
= 1;
1831 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1832 /* Number of output primitives per GS input primitive after
1834 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1837 /* The GE only checks against the maximum number of ES verts after
1838 * allocating a full GS primitive. So we need to ensure that whenever
1839 * this check passes, there is enough space for a full primitive without
1842 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1843 ngg
->max_gsprims
= max_gsprims
;
1844 ngg
->max_out_verts
= max_out_vertices
;
1845 ngg
->prim_amp_factor
= prim_amp_factor
;
1846 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1847 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1848 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1850 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1851 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1853 ngg
->vgt_esgs_ring_itemsize
= 1;
1856 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1858 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1862 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1863 const struct gfx9_gs_info
*gs
)
1865 struct radv_device
*device
= pipeline
->device
;
1866 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1867 unsigned wave_size
= 64;
1868 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1869 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1870 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1872 unsigned gs_vertex_reuse
=
1873 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1874 unsigned alignment
= 256 * num_se
;
1875 /* The maximum size is 63.999 MB per SE. */
1876 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1877 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1879 /* Calculate the minimum size. */
1880 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1881 wave_size
, alignment
);
1882 /* These are recommended sizes, not minimum sizes. */
1883 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1884 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1885 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1886 gs_info
->gs
.max_gsvs_emit_size
;
1888 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1889 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1890 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1892 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1893 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1895 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1898 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1901 /* If tessellation is all offchip and on-chip GS isn't used, this
1902 * workaround is not needed.
1906 /* SPI barrier management bug:
1907 * Make sure we have at least 4k of LDS in use to avoid the bug.
1908 * It applies to workgroup sizes of more than one wavefront.
1910 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1911 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1912 *lds_size
= MAX2(*lds_size
, 8);
1915 struct radv_shader_variant
*
1916 radv_get_shader(struct radv_pipeline
*pipeline
,
1917 gl_shader_stage stage
)
1919 if (stage
== MESA_SHADER_VERTEX
) {
1920 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1921 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1922 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1923 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1924 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1925 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1926 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1927 if (!radv_pipeline_has_tess(pipeline
))
1929 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1930 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1931 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1932 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1934 return pipeline
->shaders
[stage
];
1937 static struct radv_tessellation_state
1938 calculate_tess_state(struct radv_pipeline
*pipeline
,
1939 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1941 unsigned num_tcs_input_cp
;
1942 unsigned num_tcs_output_cp
;
1944 unsigned num_patches
;
1945 struct radv_tessellation_state tess
= {0};
1947 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1948 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1949 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1951 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1953 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1954 assert(lds_size
<= 65536);
1955 lds_size
= align(lds_size
, 512) / 512;
1957 assert(lds_size
<= 32768);
1958 lds_size
= align(lds_size
, 256) / 256;
1960 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1962 tess
.lds_size
= lds_size
;
1964 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1965 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1966 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1967 tess
.num_patches
= num_patches
;
1969 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1970 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1972 switch (tes
->info
.tes
.primitive_mode
) {
1974 type
= V_028B6C_TESS_TRIANGLE
;
1977 type
= V_028B6C_TESS_QUAD
;
1980 type
= V_028B6C_TESS_ISOLINE
;
1984 switch (tes
->info
.tes
.spacing
) {
1985 case TESS_SPACING_EQUAL
:
1986 partitioning
= V_028B6C_PART_INTEGER
;
1988 case TESS_SPACING_FRACTIONAL_ODD
:
1989 partitioning
= V_028B6C_PART_FRAC_ODD
;
1991 case TESS_SPACING_FRACTIONAL_EVEN
:
1992 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1998 bool ccw
= tes
->info
.tes
.ccw
;
1999 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2000 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2001 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2003 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2006 if (tes
->info
.tes
.point_mode
)
2007 topology
= V_028B6C_OUTPUT_POINT
;
2008 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2009 topology
= V_028B6C_OUTPUT_LINE
;
2011 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2013 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2015 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2016 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2017 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2018 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2020 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2022 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2024 tess
.tf_param
= S_028B6C_TYPE(type
) |
2025 S_028B6C_PARTITIONING(partitioning
) |
2026 S_028B6C_TOPOLOGY(topology
) |
2027 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2032 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2034 if (radv_pipeline_has_gs(pipeline
))
2035 if (radv_pipeline_has_ngg(pipeline
))
2036 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2038 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2039 else if (radv_pipeline_has_tess(pipeline
))
2040 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2042 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2046 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2048 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2049 int shader_count
= 0;
2051 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2052 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2054 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2055 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2057 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2058 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2060 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2061 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2063 if(shaders
[MESA_SHADER_VERTEX
]) {
2064 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2067 if (shader_count
> 1) {
2068 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2069 unsigned last
= ordered_shaders
[0]->info
.stage
;
2071 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2072 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2073 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2075 for (int i
= 0; i
< shader_count
; ++i
) {
2076 nir_variable_mode mask
= 0;
2078 if (ordered_shaders
[i
]->info
.stage
!= first
)
2079 mask
= mask
| nir_var_shader_in
;
2081 if (ordered_shaders
[i
]->info
.stage
!= last
)
2082 mask
= mask
| nir_var_shader_out
;
2084 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2085 radv_optimize_nir(ordered_shaders
[i
], false, false);
2089 for (int i
= 1; i
< shader_count
; ++i
) {
2090 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2091 ordered_shaders
[i
- 1]);
2093 if (nir_link_opt_varyings(ordered_shaders
[i
],
2094 ordered_shaders
[i
- 1]))
2095 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2097 nir_remove_dead_variables(ordered_shaders
[i
],
2098 nir_var_shader_out
, NULL
);
2099 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2100 nir_var_shader_in
, NULL
);
2102 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2103 ordered_shaders
[i
- 1]);
2105 nir_compact_varyings(ordered_shaders
[i
],
2106 ordered_shaders
[i
- 1], true);
2109 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2110 ac_lower_indirect_derefs(ordered_shaders
[i
],
2111 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2113 radv_optimize_nir(ordered_shaders
[i
], false, false);
2115 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2116 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2117 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2119 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2125 radv_set_linked_driver_locations(struct radv_pipeline
*pipeline
, nir_shader
**shaders
,
2126 struct radv_shader_info infos
[MESA_SHADER_STAGES
])
2128 bool has_tess
= shaders
[MESA_SHADER_TESS_CTRL
];
2129 bool has_gs
= shaders
[MESA_SHADER_GEOMETRY
];
2131 if (!has_tess
&& !has_gs
)
2134 unsigned vs_info_idx
= MESA_SHADER_VERTEX
;
2135 unsigned tes_info_idx
= MESA_SHADER_TESS_EVAL
;
2137 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2138 /* These are merged into the next stage */
2139 vs_info_idx
= has_tess
? MESA_SHADER_TESS_CTRL
: MESA_SHADER_GEOMETRY
;
2140 tes_info_idx
= has_gs
? MESA_SHADER_GEOMETRY
: MESA_SHADER_TESS_EVAL
;
2144 nir_linked_io_var_info vs2tcs
=
2145 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_TESS_CTRL
]);
2146 nir_linked_io_var_info tcs2tes
=
2147 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_CTRL
], shaders
[MESA_SHADER_TESS_EVAL
]);
2149 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2tcs
.num_linked_io_vars
;
2150 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_inputs
= vs2tcs
.num_linked_io_vars
;
2151 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_outputs
= tcs2tes
.num_linked_io_vars
;
2152 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_patch_outputs
= tcs2tes
.num_linked_patch_io_vars
;
2153 infos
[tes_info_idx
].tes
.num_linked_inputs
= tcs2tes
.num_linked_io_vars
;
2154 infos
[tes_info_idx
].tes
.num_linked_patch_inputs
= tcs2tes
.num_linked_patch_io_vars
;
2157 nir_linked_io_var_info tes2gs
=
2158 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_EVAL
], shaders
[MESA_SHADER_GEOMETRY
]);
2160 infos
[tes_info_idx
].tes
.num_linked_outputs
= tes2gs
.num_linked_io_vars
;
2161 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= tes2gs
.num_linked_io_vars
;
2163 } else if (has_gs
) {
2164 nir_linked_io_var_info vs2gs
=
2165 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_GEOMETRY
]);
2167 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2gs
.num_linked_io_vars
;
2168 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= vs2gs
.num_linked_io_vars
;
2173 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2174 uint32_t attrib_binding
)
2176 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2177 const VkVertexInputBindingDescription
*input_binding
=
2178 &input_state
->pVertexBindingDescriptions
[i
];
2180 if (input_binding
->binding
== attrib_binding
)
2181 return input_binding
->stride
;
2187 static struct radv_pipeline_key
2188 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2189 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2190 const struct radv_blend_state
*blend
,
2191 bool has_view_index
)
2193 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2194 pCreateInfo
->pVertexInputState
;
2195 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2196 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2198 struct radv_pipeline_key key
;
2199 memset(&key
, 0, sizeof(key
));
2201 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2202 key
.optimisations_disabled
= 1;
2204 key
.has_multiview_view_index
= has_view_index
;
2206 uint32_t binding_input_rate
= 0;
2207 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2208 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2209 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2210 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2211 binding_input_rate
|= 1u << binding
;
2212 instance_rate_divisors
[binding
] = 1;
2215 if (divisor_state
) {
2216 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2217 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2218 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2222 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2223 const VkVertexInputAttributeDescription
*desc
=
2224 &input_state
->pVertexAttributeDescriptions
[i
];
2225 const struct vk_format_description
*format_desc
;
2226 unsigned location
= desc
->location
;
2227 unsigned binding
= desc
->binding
;
2228 unsigned num_format
, data_format
;
2231 if (binding_input_rate
& (1u << binding
)) {
2232 key
.instance_rate_inputs
|= 1u << location
;
2233 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2236 format_desc
= vk_format_description(desc
->format
);
2237 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2239 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2240 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2242 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2243 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2244 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2245 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2247 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2248 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2249 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2252 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2253 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2254 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2256 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2257 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2258 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2260 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2261 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2262 adjust
= RADV_ALPHA_ADJUST_SINT
;
2268 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2271 switch (desc
->format
) {
2272 case VK_FORMAT_B8G8R8A8_UNORM
:
2273 case VK_FORMAT_B8G8R8A8_SNORM
:
2274 case VK_FORMAT_B8G8R8A8_USCALED
:
2275 case VK_FORMAT_B8G8R8A8_SSCALED
:
2276 case VK_FORMAT_B8G8R8A8_UINT
:
2277 case VK_FORMAT_B8G8R8A8_SINT
:
2278 case VK_FORMAT_B8G8R8A8_SRGB
:
2279 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2280 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2281 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2282 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2283 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2284 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2285 key
.vertex_post_shuffle
|= 1 << location
;
2292 const VkPipelineTessellationStateCreateInfo
*tess
=
2293 radv_pipeline_get_tessellation_state(pCreateInfo
);
2295 key
.tess_input_vertices
= tess
->patchControlPoints
;
2297 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2298 radv_pipeline_get_multisample_state(pCreateInfo
);
2299 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2300 uint32_t num_samples
= vkms
->rasterizationSamples
;
2301 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2302 key
.num_samples
= num_samples
;
2303 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2306 key
.col_format
= blend
->spi_shader_col_format
;
2307 key
.is_dual_src
= blend
->mrt0_is_dual_src
;
2308 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
) {
2309 key
.is_int8
= blend
->col_format_is_int8
;
2310 key
.is_int10
= blend
->col_format_is_int10
;
2313 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2314 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2320 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2322 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2323 bool uses_xfb
= !!xfb
;
2330 radv_fill_shader_keys(struct radv_device
*device
,
2331 struct radv_shader_variant_key
*keys
,
2332 const struct radv_pipeline_key
*key
,
2335 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2336 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2337 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2338 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2339 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2340 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2341 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2342 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2343 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2345 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2347 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2348 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2349 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2350 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2351 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2353 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2356 if (nir
[MESA_SHADER_GEOMETRY
]) {
2357 if (nir
[MESA_SHADER_TESS_CTRL
])
2358 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2360 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2363 if (device
->physical_device
->use_ngg
) {
2364 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2365 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2367 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2370 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2371 nir
[MESA_SHADER_GEOMETRY
] &&
2372 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2373 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2374 /* Fallback to the legacy path if tessellation is
2375 * enabled with extreme geometry because
2376 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2379 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2382 if (!device
->physical_device
->use_ngg_gs
) {
2383 if (nir
[MESA_SHADER_GEOMETRY
]) {
2384 if (nir
[MESA_SHADER_TESS_CTRL
])
2385 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2387 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2391 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2393 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2398 bool uses_xfb
= nir
[last_xfb_stage
] &&
2399 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2401 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2402 if (nir
[MESA_SHADER_TESS_CTRL
])
2403 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2405 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2408 /* Determine if the pipeline is eligible for the NGG passthrough
2409 * mode. It can't be enabled for geometry shaders, for NGG
2410 * streamout or for vertex shaders that export the primitive ID
2411 * (this is checked later because we don't have the info here.)
2413 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2414 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2415 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2416 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2417 } else if (nir
[MESA_SHADER_VERTEX
] &&
2418 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2419 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2424 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2425 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2427 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2428 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2429 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2430 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2431 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2432 keys
[MESA_SHADER_FRAGMENT
].fs
.is_dual_src
= key
->is_dual_src
;
2434 if (nir
[MESA_SHADER_COMPUTE
]) {
2435 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2440 radv_get_wave_size(struct radv_device
*device
,
2441 const VkPipelineShaderStageCreateInfo
*pStage
,
2442 gl_shader_stage stage
,
2443 const struct radv_shader_variant_key
*key
)
2445 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2447 else if (stage
== MESA_SHADER_COMPUTE
) {
2448 if (key
->cs
.subgroup_size
) {
2449 /* Return the required subgroup size if specified. */
2450 return key
->cs
.subgroup_size
;
2452 return device
->physical_device
->cs_wave_size
;
2454 else if (stage
== MESA_SHADER_FRAGMENT
)
2455 return device
->physical_device
->ps_wave_size
;
2457 return device
->physical_device
->ge_wave_size
;
2461 radv_get_ballot_bit_size(struct radv_device
*device
,
2462 const VkPipelineShaderStageCreateInfo
*pStage
,
2463 gl_shader_stage stage
,
2464 const struct radv_shader_variant_key
*key
)
2466 if (stage
== MESA_SHADER_COMPUTE
&& key
->cs
.subgroup_size
)
2467 return key
->cs
.subgroup_size
;
2472 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2473 const VkPipelineShaderStageCreateInfo
**pStages
,
2474 struct radv_shader_variant_key
*keys
,
2475 struct radv_shader_info
*infos
,
2478 unsigned active_stages
= 0;
2479 unsigned filled_stages
= 0;
2481 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2483 active_stages
|= (1 << i
);
2486 if (nir
[MESA_SHADER_FRAGMENT
]) {
2487 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2488 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2490 &keys
[MESA_SHADER_FRAGMENT
],
2491 &infos
[MESA_SHADER_FRAGMENT
],
2492 pipeline
->device
->physical_device
->use_llvm
);
2494 /* TODO: These are no longer used as keys we should refactor this */
2495 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2496 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2497 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2498 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2499 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2500 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2501 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_viewport_index
=
2502 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2503 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2504 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2505 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2506 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2507 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2508 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2509 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_viewport_index
=
2510 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2512 /* NGG passthrough mode can't be enabled for vertex shaders
2513 * that export the primitive ID.
2515 * TODO: I should really refactor the keys logic.
2517 if (nir
[MESA_SHADER_VERTEX
] &&
2518 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2519 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2522 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2525 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2526 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_inputs_read
=
2527 nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
;
2528 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_patch_inputs_read
=
2529 nir
[MESA_SHADER_TESS_EVAL
]->info
.patch_inputs_read
;
2532 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2533 nir
[MESA_SHADER_TESS_CTRL
]) {
2534 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2535 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2536 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2538 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2540 for (int i
= 0; i
< 2; i
++) {
2541 radv_nir_shader_info_pass(combined_nir
[i
],
2542 pipeline
->layout
, &key
,
2543 &infos
[MESA_SHADER_TESS_CTRL
],
2544 pipeline
->device
->physical_device
->use_llvm
);
2547 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2548 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2549 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2550 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2552 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2553 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2556 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2557 nir
[MESA_SHADER_GEOMETRY
]) {
2558 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2559 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2561 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2563 for (int i
= 0; i
< 2; i
++) {
2564 radv_nir_shader_info_pass(combined_nir
[i
],
2567 &infos
[MESA_SHADER_GEOMETRY
],
2568 pipeline
->device
->physical_device
->use_llvm
);
2571 filled_stages
|= (1 << pre_stage
);
2572 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2575 active_stages
^= filled_stages
;
2576 while (active_stages
) {
2577 int i
= u_bit_scan(&active_stages
);
2579 if (i
== MESA_SHADER_TESS_CTRL
) {
2580 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2581 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2584 if (i
== MESA_SHADER_TESS_EVAL
) {
2585 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2586 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2587 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2588 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2591 radv_nir_shader_info_init(&infos
[i
]);
2592 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2593 &keys
[i
], &infos
[i
], pipeline
->device
->physical_device
->use_llvm
);
2596 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2598 infos
[i
].wave_size
=
2599 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2601 infos
[i
].ballot_bit_size
=
2602 radv_get_ballot_bit_size(pipeline
->device
,
2610 merge_tess_info(struct shader_info
*tes_info
,
2611 const struct shader_info
*tcs_info
)
2613 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2615 * "PointMode. Controls generation of points rather than triangles
2616 * or lines. This functionality defaults to disabled, and is
2617 * enabled if either shader stage includes the execution mode.
2619 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2620 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2621 * and OutputVertices, it says:
2623 * "One mode must be set in at least one of the tessellation
2626 * So, the fields can be set in either the TCS or TES, but they must
2627 * agree if set in both. Our backend looks at TES, so bitwise-or in
2628 * the values from the TCS.
2630 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2631 tes_info
->tess
.tcs_vertices_out
== 0 ||
2632 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2633 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2635 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2636 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2637 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2638 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2640 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2641 tes_info
->tess
.primitive_mode
== 0 ||
2642 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2643 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2644 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2645 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2649 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2654 if (ext
->pPipelineCreationFeedback
) {
2655 ext
->pPipelineCreationFeedback
->flags
= 0;
2656 ext
->pPipelineCreationFeedback
->duration
= 0;
2659 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2660 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2661 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2666 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2671 feedback
->duration
-= radv_get_current_time();
2672 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2676 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2681 feedback
->duration
+= radv_get_current_time();
2682 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2683 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2686 VkResult
radv_create_shaders(struct radv_pipeline
*pipeline
,
2687 struct radv_device
*device
,
2688 struct radv_pipeline_cache
*cache
,
2689 const struct radv_pipeline_key
*key
,
2690 const VkPipelineShaderStageCreateInfo
**pStages
,
2691 const VkPipelineCreateFlags flags
,
2692 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2693 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2695 struct radv_shader_module fs_m
= {0};
2696 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2697 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2698 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2699 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2700 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2701 unsigned char hash
[20], gs_copy_hash
[20];
2702 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2703 bool keep_statistic_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR
) ||
2704 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) ||
2705 device
->keep_shader_info
;
2707 radv_start_feedback(pipeline_feedback
);
2709 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2711 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2712 if (modules
[i
]->nir
)
2713 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2714 strlen(modules
[i
]->nir
->info
.name
),
2717 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2721 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2722 memcpy(gs_copy_hash
, hash
, 20);
2723 gs_copy_hash
[0] ^= 1;
2725 bool found_in_application_cache
= true;
2726 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
&& !keep_statistic_info
) {
2727 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2728 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2729 &found_in_application_cache
);
2730 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2733 if (!keep_executable_info
&& !keep_statistic_info
&&
2734 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2735 &found_in_application_cache
) &&
2736 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2737 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2741 if (flags
& VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT
) {
2742 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2743 return VK_PIPELINE_COMPILE_REQUIRED_EXT
;
2746 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2748 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2749 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2750 fs_m
.nir
= fs_b
.shader
;
2751 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2754 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2755 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2756 unsigned subgroup_size
= 64, ballot_bit_size
= 64;
2761 radv_start_feedback(stage_feedbacks
[i
]);
2763 if (key
->compute_subgroup_size
) {
2764 /* Only compute shaders currently support requiring a
2765 * specific subgroup size.
2767 assert(i
== MESA_SHADER_COMPUTE
);
2768 subgroup_size
= key
->compute_subgroup_size
;
2769 ballot_bit_size
= key
->compute_subgroup_size
;
2772 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2773 stage
? stage
->pName
: "main", i
,
2774 stage
? stage
->pSpecializationInfo
: NULL
,
2775 flags
, pipeline
->layout
,
2776 subgroup_size
, ballot_bit_size
);
2778 /* We don't want to alter meta shaders IR directly so clone it
2781 if (nir
[i
]->info
.name
) {
2782 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2785 radv_stop_feedback(stage_feedbacks
[i
], false);
2788 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2789 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2790 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2793 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2794 radv_link_shaders(pipeline
, nir
);
2796 radv_set_linked_driver_locations(pipeline
, nir
, infos
);
2798 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2800 /* do this again since information such as outputs_read can be out-of-date */
2801 nir_shader_gather_info(nir
[i
], nir_shader_get_entrypoint(nir
[i
]));
2803 if (device
->physical_device
->use_llvm
) {
2804 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2806 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2807 nir_lower_non_uniform_ubo_access
|
2808 nir_lower_non_uniform_ssbo_access
|
2809 nir_lower_non_uniform_texture_access
|
2810 nir_lower_non_uniform_image_access
);
2815 if (nir
[MESA_SHADER_FRAGMENT
])
2816 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2818 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2819 if (radv_can_dump_shader(device
, modules
[i
], false))
2820 nir_print_shader(nir
[i
], stderr
);
2823 radv_fill_shader_keys(device
, keys
, key
, nir
);
2825 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2827 if ((nir
[MESA_SHADER_VERTEX
] &&
2828 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2829 (nir
[MESA_SHADER_TESS_EVAL
] &&
2830 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2831 struct gfx10_ngg_info
*ngg_info
;
2833 if (nir
[MESA_SHADER_GEOMETRY
])
2834 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2835 else if (nir
[MESA_SHADER_TESS_CTRL
])
2836 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2838 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2840 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2841 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2842 struct gfx9_gs_info
*gs_info
=
2843 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2845 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2848 if(modules
[MESA_SHADER_GEOMETRY
]) {
2849 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2850 if (!pipeline
->gs_copy_shader
&&
2851 !radv_pipeline_has_ngg(pipeline
)) {
2852 struct radv_shader_info info
= {};
2853 struct radv_shader_variant_key key
= {};
2855 key
.has_multiview_view_index
=
2856 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2858 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2859 pipeline
->layout
, &key
,
2860 &info
, pipeline
->device
->physical_device
->use_llvm
);
2861 info
.wave_size
= 64; /* Wave32 not supported. */
2862 info
.ballot_bit_size
= 64;
2864 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2865 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2866 &gs_copy_binary
, keep_executable_info
, keep_statistic_info
,
2867 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2870 if (!keep_executable_info
&& !keep_statistic_info
&& pipeline
->gs_copy_shader
) {
2871 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2872 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2874 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2875 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2877 radv_pipeline_cache_insert_shaders(device
, cache
,
2882 free(gs_copy_binary
);
2885 if (nir
[MESA_SHADER_FRAGMENT
]) {
2886 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2887 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2889 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2890 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2891 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2892 infos
+ MESA_SHADER_FRAGMENT
,
2893 keep_executable_info
, keep_statistic_info
,
2894 &binaries
[MESA_SHADER_FRAGMENT
]);
2896 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2900 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2901 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2902 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2903 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2904 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2906 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2908 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2910 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2911 keep_statistic_info
, &binaries
[MESA_SHADER_TESS_CTRL
]);
2913 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2915 modules
[MESA_SHADER_VERTEX
] = NULL
;
2916 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2917 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2920 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2921 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2922 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2923 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2925 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2927 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2929 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2930 keep_statistic_info
, &binaries
[MESA_SHADER_GEOMETRY
]);
2932 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2934 modules
[pre_stage
] = NULL
;
2937 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2938 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2939 if (i
== MESA_SHADER_TESS_CTRL
) {
2940 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2942 if (i
== MESA_SHADER_TESS_EVAL
) {
2943 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2944 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2947 radv_start_feedback(stage_feedbacks
[i
]);
2949 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2951 keys
+ i
, infos
+ i
, keep_executable_info
,
2952 keep_statistic_info
, &binaries
[i
]);
2954 radv_stop_feedback(stage_feedbacks
[i
], false);
2958 if (!keep_executable_info
&& !keep_statistic_info
) {
2959 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2963 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2966 ralloc_free(nir
[i
]);
2968 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2969 radv_shader_dump_stats(device
,
2970 pipeline
->shaders
[i
],
2976 ralloc_free(fs_m
.nir
);
2978 radv_stop_feedback(pipeline_feedback
, false);
2983 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2984 gl_shader_stage stage
, enum chip_class chip_class
)
2986 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2987 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2988 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
2991 case MESA_SHADER_FRAGMENT
:
2992 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2993 case MESA_SHADER_VERTEX
:
2995 if (chip_class
>= GFX10
) {
2996 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2997 } else if (chip_class
== GFX9
) {
2998 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3000 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3006 if (chip_class
>= GFX10
) {
3007 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3009 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3014 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3016 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3017 case MESA_SHADER_GEOMETRY
:
3018 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3019 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3020 case MESA_SHADER_COMPUTE
:
3021 return R_00B900_COMPUTE_USER_DATA_0
;
3022 case MESA_SHADER_TESS_CTRL
:
3023 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3024 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3025 case MESA_SHADER_TESS_EVAL
:
3027 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3028 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3029 } else if (has_ngg
) {
3030 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3032 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3035 unreachable("unknown shader");
3039 struct radv_bin_size_entry
{
3045 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3047 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3051 /* One shader engine */
3057 { UINT_MAX
, { 0, 0}},
3060 /* Two shader engines */
3066 { UINT_MAX
, { 0, 0}},
3069 /* Four shader engines */
3074 { UINT_MAX
, { 0, 0}},
3080 /* One shader engine */
3086 { UINT_MAX
, { 0, 0}},
3089 /* Two shader engines */
3095 { UINT_MAX
, { 0, 0}},
3098 /* Four shader engines */
3105 { UINT_MAX
, { 0, 0}},
3111 /* One shader engine */
3118 { UINT_MAX
, { 0, 0}},
3121 /* Two shader engines */
3129 { UINT_MAX
, { 0, 0}},
3132 /* Four shader engines */
3140 { UINT_MAX
, { 0, 0}},
3144 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3148 // One shader engine
3155 { UINT_MAX
, { 0, 0}},
3158 // Two shader engines
3166 { UINT_MAX
, { 0, 0}},
3169 // Four shader engines
3177 { UINT_MAX
, { 0, 0}},
3183 // One shader engine
3191 { UINT_MAX
, { 0, 0}},
3194 // Two shader engines
3203 { UINT_MAX
, { 0, 0}},
3206 // Four shader engines
3215 { UINT_MAX
, { 0, 0}},
3221 // One shader engine
3229 { UINT_MAX
, { 0, 0}},
3232 // Two shader engines
3241 { UINT_MAX
, { 0, 0}},
3244 // Four shader engines
3252 { UINT_MAX
, { 0, 0}},
3257 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3258 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3259 VkExtent2D extent
= {512, 512};
3261 unsigned log_num_rb_per_se
=
3262 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3263 pipeline
->device
->physical_device
->rad_info
.max_se
);
3264 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3266 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3267 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3268 unsigned effective_samples
= total_samples
;
3269 unsigned color_bytes_per_pixel
= 0;
3271 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3272 radv_pipeline_get_color_blend_state(pCreateInfo
);
3274 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3275 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3278 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3281 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3282 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3285 /* MSAA images typically don't use all samples all the time. */
3286 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3287 effective_samples
= 2;
3288 color_bytes_per_pixel
*= effective_samples
;
3291 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3292 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3295 extent
= color_entry
->extent
;
3297 if (subpass
->depth_stencil_attachment
) {
3298 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3300 /* Coefficients taken from AMDVLK */
3301 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3302 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3303 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3305 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3306 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3309 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3310 extent
= ds_entry
->extent
;
3317 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3319 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3320 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3321 VkExtent2D extent
= {512, 512};
3323 const unsigned db_tag_size
= 64;
3324 const unsigned db_tag_count
= 312;
3325 const unsigned color_tag_size
= 1024;
3326 const unsigned color_tag_count
= 31;
3327 const unsigned fmask_tag_size
= 256;
3328 const unsigned fmask_tag_count
= 44;
3330 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3331 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3333 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3334 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3335 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3337 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3338 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3340 unsigned color_bytes_per_pixel
= 0;
3341 unsigned fmask_bytes_per_pixel
= 0;
3343 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3344 radv_pipeline_get_color_blend_state(pCreateInfo
);
3346 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3347 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3350 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3353 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3354 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3356 if (total_samples
> 1) {
3357 assert(samples_log
<= 3);
3358 const unsigned fmask_array
[] = {0, 1, 1, 4};
3359 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3363 color_bytes_per_pixel
*= total_samples
;
3365 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3367 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3368 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3369 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3371 if (fmask_bytes_per_pixel
) {
3372 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3374 const VkExtent2D fmask_extent
= (VkExtent2D
){
3375 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3376 .height
= 1ull << (color_pixel_count_log
/ 2)
3379 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3380 extent
= fmask_extent
;
3383 if (subpass
->depth_stencil_attachment
) {
3384 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3386 /* Coefficients taken from AMDVLK */
3387 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3388 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3389 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3391 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3393 const VkExtent2D db_extent
= (VkExtent2D
){
3394 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3395 .height
= 1ull << (color_pixel_count_log
/ 2)
3398 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3402 extent
.width
= MAX2(extent
.width
, 128);
3403 extent
.height
= MAX2(extent
.width
, 64);
3409 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3410 struct radv_pipeline
*pipeline
,
3411 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3413 uint32_t pa_sc_binner_cntl_0
=
3414 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3415 S_028C44_DISABLE_START_OF_PRIM(1);
3416 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3418 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3419 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3420 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3421 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3422 radv_pipeline_get_color_blend_state(pCreateInfo
);
3423 unsigned min_bytes_per_pixel
= 0;
3426 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3427 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3430 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3433 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3434 unsigned bytes
= vk_format_get_blocksize(format
);
3435 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3436 min_bytes_per_pixel
= bytes
;
3440 pa_sc_binner_cntl_0
=
3441 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3442 S_028C44_BIN_SIZE_X(0) |
3443 S_028C44_BIN_SIZE_Y(0) |
3444 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3445 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3446 S_028C44_DISABLE_START_OF_PRIM(1);
3449 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3450 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3453 struct radv_binning_settings
3454 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3456 struct radv_binning_settings settings
;
3457 if (pdev
->rad_info
.has_dedicated_vram
) {
3458 if (pdev
->rad_info
.num_render_backends
> 4) {
3459 settings
.context_states_per_bin
= 1;
3460 settings
.persistent_states_per_bin
= 1;
3462 settings
.context_states_per_bin
= 3;
3463 settings
.persistent_states_per_bin
= 8;
3465 settings
.fpovs_per_batch
= 63;
3467 /* The context states are affected by the scissor bug. */
3468 settings
.context_states_per_bin
= 6;
3469 /* 32 causes hangs for RAVEN. */
3470 settings
.persistent_states_per_bin
= 16;
3471 settings
.fpovs_per_batch
= 63;
3474 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3475 settings
.context_states_per_bin
= 1;
3481 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3482 struct radv_pipeline
*pipeline
,
3483 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3484 const struct radv_blend_state
*blend
)
3486 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3489 VkExtent2D bin_size
;
3490 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3491 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3492 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3493 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3495 unreachable("Unhandled generation for binning bin size calculation");
3497 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3498 struct radv_binning_settings settings
=
3499 radv_get_binning_settings(pipeline
->device
->physical_device
);
3501 bool disable_start_of_prim
= true;
3502 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3504 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3506 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3507 !ps
->info
.ps
.can_discard
&&
3508 !ps
->info
.ps
.writes_memory
&&
3509 blend
->cb_target_enabled_4bit
) {
3510 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3511 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3514 const uint32_t pa_sc_binner_cntl_0
=
3515 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3516 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3517 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3518 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3519 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3520 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3521 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3522 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3523 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3524 S_028C44_OPTIMAL_BIN_SELECTION(1);
3526 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3527 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3529 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3534 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3535 struct radv_pipeline
*pipeline
,
3536 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3537 const struct radv_graphics_pipeline_create_info
*extra
)
3539 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3540 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3541 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3542 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3543 struct radv_render_pass_attachment
*attachment
= NULL
;
3544 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3545 uint32_t db_render_control
= 0, db_render_override2
= 0;
3546 uint32_t db_render_override
= 0;
3548 if (subpass
->depth_stencil_attachment
)
3549 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3551 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3552 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3554 if (vkds
&& has_depth_attachment
) {
3555 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3556 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3557 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3558 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3560 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3561 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3563 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
)
3564 db_render_override2
|= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3567 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3568 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3569 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3570 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3571 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3572 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3574 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3575 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3576 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3577 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3580 if (attachment
&& extra
) {
3581 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3582 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3584 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->resummarize_enable
);
3585 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->depth_compress_disable
);
3586 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->stencil_compress_disable
);
3587 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3588 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3591 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3592 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3594 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3595 ps
->info
.ps
.writes_z
) {
3596 /* From VK_EXT_depth_range_unrestricted spec:
3598 * "The behavior described in Primitive Clipping still applies.
3599 * If depth clamping is disabled the depth values are still
3600 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3601 * depth clamping is enabled the above equation is ignored and
3602 * the depth values are instead clamped to the VkViewport
3603 * minDepth and maxDepth values, which in the case of this
3604 * extension can be outside of the 0.0 to 1.0 range."
3606 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3609 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3610 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3612 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3613 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3614 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3618 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3619 struct radv_pipeline
*pipeline
,
3620 const struct radv_blend_state
*blend
)
3622 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3623 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3625 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3626 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3628 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3630 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3631 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3634 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3636 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3637 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3639 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3640 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3643 static const VkConservativeRasterizationModeEXT
3644 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3646 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3647 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3649 if (!conservative_raster
)
3650 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3651 return conservative_raster
->conservativeRasterizationMode
;
3655 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3656 struct radv_pipeline
*pipeline
,
3657 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3659 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3660 const VkConservativeRasterizationModeEXT mode
=
3661 radv_get_conservative_raster_mode(vkraster
);
3662 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3663 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3665 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3666 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3667 if (depth_clip_state
) {
3668 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3671 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3672 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3673 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3674 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3675 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3676 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3678 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3679 S_0286D4_FLAT_SHADE_ENA(1) |
3680 S_0286D4_PNT_SPRITE_ENA(1) |
3681 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3682 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3683 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3684 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3685 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3687 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3688 S_028BE4_PIX_CENTER(1) | // TODO verify
3689 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3690 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3692 pipeline
->graphics
.pa_su_sc_mode_cntl
=
3693 S_028814_FACE(vkraster
->frontFace
) |
3694 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3695 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3696 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3697 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3698 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3699 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3700 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3701 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0);
3703 /* Conservative rasterization. */
3704 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3705 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3707 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3708 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3709 S_028804_OVERRASTERIZATION_AMOUNT(4);
3711 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3712 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3713 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3715 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3716 pa_sc_conservative_rast
|=
3717 S_028C4C_OVER_RAST_ENABLE(1) |
3718 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3719 S_028C4C_UNDER_RAST_ENABLE(0) |
3720 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3721 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3723 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3724 pa_sc_conservative_rast
|=
3725 S_028C4C_OVER_RAST_ENABLE(0) |
3726 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3727 S_028C4C_UNDER_RAST_ENABLE(1) |
3728 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3729 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3733 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3734 pa_sc_conservative_rast
);
3739 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3740 struct radv_pipeline
*pipeline
)
3742 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3744 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3745 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3746 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3748 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3749 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3750 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3751 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3752 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3754 /* The exclusion bits can be set to improve rasterization efficiency
3755 * if no sample lies on the pixel boundary (-8 sample offset). It's
3756 * currently always TRUE because the driver doesn't support 16 samples.
3758 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3759 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3760 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3761 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3763 /* GFX9: Flush DFSM when the AA mode changes. */
3764 if (pipeline
->device
->dfsm_allowed
) {
3765 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3766 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3771 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3772 struct radv_pipeline
*pipeline
)
3774 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3775 const struct radv_shader_variant
*vs
=
3776 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3777 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3778 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3779 unsigned vgt_primitiveid_en
= 0;
3780 uint32_t vgt_gs_mode
= 0;
3782 if (radv_pipeline_has_ngg(pipeline
))
3785 if (radv_pipeline_has_gs(pipeline
)) {
3786 const struct radv_shader_variant
*gs
=
3787 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3789 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3790 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3791 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3792 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3793 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3796 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3797 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3801 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3802 struct radeon_cmdbuf
*cs
,
3803 struct radv_pipeline
*pipeline
,
3804 struct radv_shader_variant
*shader
)
3806 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3808 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3809 radeon_emit(cs
, va
>> 8);
3810 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3811 radeon_emit(cs
, shader
->config
.rsrc1
);
3812 radeon_emit(cs
, shader
->config
.rsrc2
);
3814 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3815 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3816 clip_dist_mask
= outinfo
->clip_dist_mask
;
3817 cull_dist_mask
= outinfo
->cull_dist_mask
;
3818 total_mask
= clip_dist_mask
| cull_dist_mask
;
3819 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3820 outinfo
->writes_layer
||
3821 outinfo
->writes_viewport_index
;
3822 unsigned spi_vs_out_config
, nparams
;
3824 /* VS is required to export at least one param. */
3825 nparams
= MAX2(outinfo
->param_exports
, 1);
3826 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3828 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3829 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3832 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3834 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3835 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3836 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3837 V_02870C_SPI_SHADER_4COMP
:
3838 V_02870C_SPI_SHADER_NONE
) |
3839 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3840 V_02870C_SPI_SHADER_4COMP
:
3841 V_02870C_SPI_SHADER_NONE
) |
3842 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3843 V_02870C_SPI_SHADER_4COMP
:
3844 V_02870C_SPI_SHADER_NONE
));
3846 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3847 S_028818_VTX_W0_FMT(1) |
3848 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3849 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3850 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3852 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3853 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3854 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3855 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3856 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3857 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3858 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3859 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3860 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3861 cull_dist_mask
<< 8 |
3864 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3865 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3866 outinfo
->writes_viewport_index
);
3870 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3871 struct radv_pipeline
*pipeline
,
3872 struct radv_shader_variant
*shader
)
3874 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3876 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3877 radeon_emit(cs
, va
>> 8);
3878 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3879 radeon_emit(cs
, shader
->config
.rsrc1
);
3880 radeon_emit(cs
, shader
->config
.rsrc2
);
3884 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3885 struct radv_pipeline
*pipeline
,
3886 struct radv_shader_variant
*shader
,
3887 const struct radv_tessellation_state
*tess
)
3889 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3890 uint32_t rsrc2
= shader
->config
.rsrc2
;
3892 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3893 radeon_emit(cs
, va
>> 8);
3894 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3896 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3897 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3898 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3899 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3901 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3902 radeon_emit(cs
, shader
->config
.rsrc1
);
3903 radeon_emit(cs
, rsrc2
);
3907 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3908 struct radeon_cmdbuf
*cs
,
3909 struct radv_pipeline
*pipeline
,
3910 struct radv_shader_variant
*shader
)
3912 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3913 gl_shader_stage es_type
=
3914 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3915 struct radv_shader_variant
*es
=
3916 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3917 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3919 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3920 radeon_emit(cs
, va
>> 8);
3921 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3922 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3923 radeon_emit(cs
, shader
->config
.rsrc1
);
3924 radeon_emit(cs
, shader
->config
.rsrc2
);
3926 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3927 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3928 clip_dist_mask
= outinfo
->clip_dist_mask
;
3929 cull_dist_mask
= outinfo
->cull_dist_mask
;
3930 total_mask
= clip_dist_mask
| cull_dist_mask
;
3931 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3932 outinfo
->writes_layer
||
3933 outinfo
->writes_viewport_index
;
3934 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3935 (es
&& es
->info
.uses_prim_id
);
3936 bool break_wave_at_eoi
= false;
3940 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3941 struct radv_shader_variant
*gs
=
3942 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3944 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3945 break_wave_at_eoi
= true;
3948 nparams
= MAX2(outinfo
->param_exports
, 1);
3949 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3950 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3951 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3953 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3954 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3955 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3956 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3957 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3958 V_02870C_SPI_SHADER_4COMP
:
3959 V_02870C_SPI_SHADER_NONE
) |
3960 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3961 V_02870C_SPI_SHADER_4COMP
:
3962 V_02870C_SPI_SHADER_NONE
) |
3963 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3964 V_02870C_SPI_SHADER_4COMP
:
3965 V_02870C_SPI_SHADER_NONE
));
3967 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3968 S_028818_VTX_W0_FMT(1) |
3969 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3970 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3971 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3972 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3973 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3974 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3975 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3976 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3977 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3978 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3979 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3980 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3981 cull_dist_mask
<< 8 |
3984 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3985 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3986 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
3988 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3989 ngg_state
->vgt_esgs_ring_itemsize
);
3991 /* NGG specific registers. */
3992 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3993 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
3995 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3996 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
3997 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
3998 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
3999 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
4000 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
4001 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4002 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4003 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4004 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4005 S_028B90_CNT(gs_num_invocations
) |
4006 S_028B90_ENABLE(gs_num_invocations
> 1) |
4007 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4009 /* User edge flags are set by the pos exports. If user edge flags are
4010 * not used, we must use hw-generated edge flags and pass them via
4011 * the prim export to prevent drawing lines on internal edges of
4012 * decomposed primitives (such as quads) with polygon mode = lines.
4014 * TODO: We should combine hw-generated edge flags with user edge
4015 * flags in the shader.
4017 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4018 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4019 !radv_pipeline_has_gs(pipeline
)) |
4020 /* Reuse for NGG. */
4021 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
? 30 : 0));
4023 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4024 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4025 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4027 /* Bug workaround for a possible hang with non-tessellation cases.
4028 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4030 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4032 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
4033 !radv_pipeline_has_tess(pipeline
) &&
4034 ngg_state
->hw_max_esverts
!= 256) {
4035 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4037 if (ngg_state
->hw_max_esverts
> 5) {
4038 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4042 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4046 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4047 struct radv_pipeline
*pipeline
,
4048 struct radv_shader_variant
*shader
,
4049 const struct radv_tessellation_state
*tess
)
4051 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4053 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4054 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4056 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4057 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
4059 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
4062 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4063 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4064 radeon_emit(cs
, va
>> 8);
4065 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4067 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4068 radeon_emit(cs
, va
>> 8);
4069 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4072 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4073 radeon_emit(cs
, shader
->config
.rsrc1
);
4074 radeon_emit(cs
, hs_rsrc2
);
4076 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4077 radeon_emit(cs
, va
>> 8);
4078 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4079 radeon_emit(cs
, shader
->config
.rsrc1
);
4080 radeon_emit(cs
, shader
->config
.rsrc2
);
4085 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4086 struct radeon_cmdbuf
*cs
,
4087 struct radv_pipeline
*pipeline
,
4088 const struct radv_tessellation_state
*tess
)
4090 struct radv_shader_variant
*vs
;
4092 /* Skip shaders merged into HS/GS */
4093 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4097 if (vs
->info
.vs
.as_ls
)
4098 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4099 else if (vs
->info
.vs
.as_es
)
4100 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4101 else if (vs
->info
.is_ngg
)
4102 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4104 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4108 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4109 struct radeon_cmdbuf
*cs
,
4110 struct radv_pipeline
*pipeline
,
4111 const struct radv_tessellation_state
*tess
)
4113 if (!radv_pipeline_has_tess(pipeline
))
4116 struct radv_shader_variant
*tes
, *tcs
;
4118 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4119 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4122 if (tes
->info
.is_ngg
) {
4123 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4124 } else if (tes
->info
.tes
.as_es
)
4125 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4127 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4130 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4132 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4135 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4136 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4137 tess
->ls_hs_config
);
4139 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4140 tess
->ls_hs_config
);
4142 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4143 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4144 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4145 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4146 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4147 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4152 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4153 struct radeon_cmdbuf
*cs
,
4154 struct radv_pipeline
*pipeline
,
4155 struct radv_shader_variant
*gs
)
4157 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4158 unsigned gs_max_out_vertices
;
4159 uint8_t *num_components
;
4164 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4165 max_stream
= gs
->info
.gs
.max_stream
;
4166 num_components
= gs
->info
.gs
.num_stream_output_components
;
4168 offset
= num_components
[0] * gs_max_out_vertices
;
4170 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4171 radeon_emit(ctx_cs
, offset
);
4172 if (max_stream
>= 1)
4173 offset
+= num_components
[1] * gs_max_out_vertices
;
4174 radeon_emit(ctx_cs
, offset
);
4175 if (max_stream
>= 2)
4176 offset
+= num_components
[2] * gs_max_out_vertices
;
4177 radeon_emit(ctx_cs
, offset
);
4178 if (max_stream
>= 3)
4179 offset
+= num_components
[3] * gs_max_out_vertices
;
4180 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4182 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4183 radeon_emit(ctx_cs
, num_components
[0]);
4184 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4185 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4186 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4188 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4189 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4190 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4191 S_028B90_ENABLE(gs_num_invocations
> 0));
4193 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4194 gs_state
->vgt_esgs_ring_itemsize
);
4196 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4198 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4199 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4200 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4201 radeon_emit(cs
, va
>> 8);
4202 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4204 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4205 radeon_emit(cs
, va
>> 8);
4206 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4209 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4210 radeon_emit(cs
, gs
->config
.rsrc1
);
4211 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4213 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4214 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4216 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4217 radeon_emit(cs
, va
>> 8);
4218 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4219 radeon_emit(cs
, gs
->config
.rsrc1
);
4220 radeon_emit(cs
, gs
->config
.rsrc2
);
4223 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4227 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4228 struct radeon_cmdbuf
*cs
,
4229 struct radv_pipeline
*pipeline
)
4231 struct radv_shader_variant
*gs
;
4233 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4237 if (gs
->info
.is_ngg
)
4238 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4240 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4242 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4243 gs
->info
.gs
.vertices_out
);
4246 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4247 bool explicit, bool float16
)
4249 uint32_t ps_input_cntl
;
4250 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4251 ps_input_cntl
= S_028644_OFFSET(offset
);
4252 if (flat_shade
|| explicit)
4253 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4255 /* Force parameter cache to be read in passthrough
4258 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4261 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4262 S_028644_ATTR0_VALID(1);
4265 /* The input is a DEFAULT_VAL constant. */
4266 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4267 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4268 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4269 ps_input_cntl
= S_028644_OFFSET(0x20) |
4270 S_028644_DEFAULT_VAL(offset
);
4272 return ps_input_cntl
;
4276 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4277 struct radv_pipeline
*pipeline
)
4279 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4280 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4281 uint32_t ps_input_cntl
[32];
4283 unsigned ps_offset
= 0;
4285 if (ps
->info
.ps
.prim_id_input
) {
4286 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4287 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4288 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4293 if (ps
->info
.ps
.layer_input
||
4294 ps
->info
.needs_multiview_view_index
) {
4295 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4296 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4297 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4299 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4303 if (ps
->info
.ps
.viewport_index_input
) {
4304 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VIEWPORT
];
4305 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4306 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4308 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4312 if (ps
->info
.ps
.has_pcoord
) {
4314 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4315 ps_input_cntl
[ps_offset
] = val
;
4319 if (ps
->info
.ps
.num_input_clips_culls
) {
4322 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4323 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4324 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4328 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4329 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4330 ps
->info
.ps
.num_input_clips_culls
> 4) {
4331 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4336 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4341 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4344 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4345 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4346 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4351 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4352 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4353 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4355 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4360 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4361 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4362 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4368 radv_compute_db_shader_control(const struct radv_device
*device
,
4369 const struct radv_pipeline
*pipeline
,
4370 const struct radv_shader_variant
*ps
)
4372 unsigned conservative_z_export
= V_02880C_EXPORT_ANY_Z
;
4374 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4375 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4377 z_order
= V_02880C_LATE_Z
;
4379 if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_GREATER
)
4380 conservative_z_export
= V_02880C_EXPORT_GREATER_THAN_Z
;
4381 else if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_LESS
)
4382 conservative_z_export
= V_02880C_EXPORT_LESS_THAN_Z
;
4384 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4385 !device
->physical_device
->rad_info
.rbplus_allowed
;
4387 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4388 * but this appears to break Project Cars (DXVK). See
4389 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4391 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4393 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4394 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4395 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4396 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4397 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export
) |
4398 S_02880C_Z_ORDER(z_order
) |
4399 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4400 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4401 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4402 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4403 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4407 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4408 struct radeon_cmdbuf
*cs
,
4409 struct radv_pipeline
*pipeline
)
4411 struct radv_shader_variant
*ps
;
4413 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4415 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4416 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4418 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4419 radeon_emit(cs
, va
>> 8);
4420 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4421 radeon_emit(cs
, ps
->config
.rsrc1
);
4422 radeon_emit(cs
, ps
->config
.rsrc2
);
4424 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4425 radv_compute_db_shader_control(pipeline
->device
,
4428 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4429 ps
->config
.spi_ps_input_ena
);
4431 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4432 ps
->config
.spi_ps_input_addr
);
4434 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4435 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4436 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4438 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4440 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4441 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4442 ps
->info
.ps
.writes_stencil
,
4443 ps
->info
.ps
.writes_sample_mask
));
4445 if (pipeline
->device
->dfsm_allowed
) {
4446 /* optimise this? */
4447 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4448 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4453 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4454 struct radv_pipeline
*pipeline
)
4456 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4457 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4460 unsigned vtx_reuse_depth
= 30;
4461 if (radv_pipeline_has_tess(pipeline
) &&
4462 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4463 vtx_reuse_depth
= 14;
4465 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4466 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4470 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4472 uint32_t stages
= 0;
4473 if (radv_pipeline_has_tess(pipeline
)) {
4474 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4475 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4477 if (radv_pipeline_has_gs(pipeline
))
4478 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4480 else if (radv_pipeline_has_ngg(pipeline
))
4481 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4483 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4484 } else if (radv_pipeline_has_gs(pipeline
)) {
4485 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4487 } else if (radv_pipeline_has_ngg(pipeline
)) {
4488 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4491 if (radv_pipeline_has_ngg(pipeline
)) {
4492 stages
|= S_028B54_PRIMGEN_EN(1);
4493 if (pipeline
->streamout_shader
)
4494 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4495 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4496 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4497 } else if (radv_pipeline_has_gs(pipeline
)) {
4498 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4501 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4502 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4504 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4505 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4507 if (radv_pipeline_has_tess(pipeline
))
4508 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4510 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4511 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4512 if (pipeline
->gs_copy_shader
)
4513 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4514 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4515 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4516 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4517 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4519 if (radv_pipeline_has_ngg(pipeline
))
4522 /* legacy GS only supports Wave64 */
4523 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4524 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4525 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4532 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4534 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4535 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4537 if (!discard_rectangle_info
)
4542 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4543 /* Interpret i as a bitmask, and then set the bit in the mask if
4544 * that combination of rectangles in which the pixel is contained
4545 * should pass the cliprect test. */
4546 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4548 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4552 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4563 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4564 struct radv_pipeline
*pipeline
,
4565 const struct radv_tessellation_state
*tess
)
4567 bool break_wave_at_eoi
= false;
4568 unsigned primgroup_size
;
4569 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4571 if (radv_pipeline_has_tess(pipeline
)) {
4572 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4573 } else if (radv_pipeline_has_gs(pipeline
)) {
4574 const struct gfx9_gs_info
*gs_state
=
4575 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4576 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4577 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4579 primgroup_size
= 128; /* recommended without a GS and tess */
4582 if (radv_pipeline_has_tess(pipeline
)) {
4583 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4584 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4585 break_wave_at_eoi
= true;
4588 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4589 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4590 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4591 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4592 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4596 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4597 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4598 const struct radv_graphics_pipeline_create_info
*extra
,
4599 const struct radv_blend_state
*blend
,
4600 const struct radv_tessellation_state
*tess
,
4603 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4604 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4607 ctx_cs
->max_dw
= 256;
4608 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4609 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4611 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4612 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4613 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4614 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4615 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4616 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4617 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4618 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4619 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4620 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4621 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4622 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4624 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4625 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4627 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4628 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4630 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4632 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4634 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4635 assert(cs
->cdw
<= cs
->max_dw
);
4638 static struct radv_ia_multi_vgt_param_helpers
4639 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4640 const struct radv_tessellation_state
*tess
)
4642 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4643 const struct radv_device
*device
= pipeline
->device
;
4645 if (radv_pipeline_has_tess(pipeline
))
4646 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4647 else if (radv_pipeline_has_gs(pipeline
))
4648 ia_multi_vgt_param
.primgroup_size
= 64;
4650 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4652 /* GS requirement. */
4653 ia_multi_vgt_param
.partial_es_wave
= false;
4654 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4655 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4656 ia_multi_vgt_param
.partial_es_wave
= true;
4658 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4659 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4660 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4661 if (radv_pipeline_has_gs(pipeline
) &&
4662 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4663 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4664 if (radv_pipeline_has_tess(pipeline
)) {
4665 /* SWITCH_ON_EOI must be set if PrimID is used. */
4666 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4667 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4668 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4671 ia_multi_vgt_param
.partial_vs_wave
= false;
4672 if (radv_pipeline_has_tess(pipeline
)) {
4673 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4674 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4675 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4676 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4677 radv_pipeline_has_gs(pipeline
))
4678 ia_multi_vgt_param
.partial_vs_wave
= true;
4679 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4680 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4681 if (radv_pipeline_has_gs(pipeline
)) {
4682 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4683 ia_multi_vgt_param
.partial_es_wave
= true;
4685 ia_multi_vgt_param
.partial_vs_wave
= true;
4690 if (radv_pipeline_has_gs(pipeline
)) {
4691 /* On these chips there is the possibility of a hang if the
4692 * pipeline uses a GS and partial_vs_wave is not set.
4694 * This mostly does not hit 4-SE chips, as those typically set
4695 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4696 * with GS due to another workaround.
4698 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4700 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4701 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4702 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4703 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4704 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4705 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4706 ia_multi_vgt_param
.partial_vs_wave
= true;
4710 ia_multi_vgt_param
.base
=
4711 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4712 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4713 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4714 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4715 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4717 return ia_multi_vgt_param
;
4722 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4723 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4725 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4726 pCreateInfo
->pVertexInputState
;
4727 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4729 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4730 const VkVertexInputAttributeDescription
*desc
=
4731 &vi_info
->pVertexAttributeDescriptions
[i
];
4732 unsigned loc
= desc
->location
;
4733 const struct vk_format_description
*format_desc
;
4735 format_desc
= vk_format_description(desc
->format
);
4737 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4740 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4741 const VkVertexInputBindingDescription
*desc
=
4742 &vi_info
->pVertexBindingDescriptions
[i
];
4744 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4745 pipeline
->num_vertex_bindings
=
4746 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4750 static struct radv_shader_variant
*
4751 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4755 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4756 struct radv_shader_variant
*shader
=
4757 radv_get_shader(pipeline
, i
);
4759 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4767 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4768 struct radv_device
*device
,
4769 struct radv_pipeline_cache
*cache
,
4770 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4771 const struct radv_graphics_pipeline_create_info
*extra
)
4774 bool has_view_index
= false;
4776 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
4777 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
4778 if (subpass
->view_mask
)
4779 has_view_index
= true;
4781 pipeline
->device
= device
;
4782 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4783 assert(pipeline
->layout
);
4785 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4787 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4788 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4789 radv_init_feedback(creation_feedback
);
4791 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4793 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4794 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4795 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4796 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4797 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4798 if(creation_feedback
)
4799 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4802 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
4804 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
4805 pCreateInfo
->flags
, pipeline_feedback
,
4807 if (result
!= VK_SUCCESS
)
4810 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4811 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4814 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
4816 if (radv_pipeline_has_gs(pipeline
)) {
4817 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4818 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4819 } else if (radv_pipeline_has_tess(pipeline
)) {
4820 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
4821 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4823 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4824 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4826 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4828 if (extra
&& extra
->use_rectlist
) {
4829 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4830 pipeline
->graphics
.can_use_guardband
= true;
4831 if (radv_pipeline_has_ngg(pipeline
))
4832 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4834 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
4836 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
, extra
);
4838 /* Ensure that some export memory is always allocated, for two reasons:
4840 * 1) Correctness: The hardware ignores the EXEC mask if no export
4841 * memory is allocated, so KILL and alpha test do not work correctly
4843 * 2) Performance: Every shader needs at least a NULL export, even when
4844 * it writes no color/depth output. The NULL export instruction
4845 * stalls without this setting.
4847 * Don't add this to CB_SHADER_MASK.
4849 * GFX10 supports pixel shaders without exports by setting both the
4850 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4851 * instructions if any are present.
4853 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4854 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
4855 ps
->info
.ps
.can_discard
) &&
4856 !blend
.spi_shader_col_format
) {
4857 if (!ps
->info
.ps
.writes_z
&&
4858 !ps
->info
.ps
.writes_stencil
&&
4859 !ps
->info
.ps
.writes_sample_mask
)
4860 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
4863 blend
.cb_shader_mask
= ps
->info
.ps
.cb_shader_mask
;
4866 (extra
->custom_blend_mode
== V_028808_CB_ELIMINATE_FAST_CLEAR
||
4867 extra
->custom_blend_mode
== V_028808_CB_FMASK_DECOMPRESS
||
4868 extra
->custom_blend_mode
== V_028808_CB_DCC_DECOMPRESS
||
4869 extra
->custom_blend_mode
== V_028808_CB_RESOLVE
)) {
4870 /* According to the CB spec states, CB_SHADER_MASK should be
4871 * set to enable writes to all four channels of MRT0.
4873 blend
.cb_shader_mask
= 0xf;
4876 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4877 if (pipeline
->shaders
[i
]) {
4878 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
4882 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4883 struct radv_shader_variant
*gs
=
4884 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4886 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
4889 struct radv_tessellation_state tess
= {0};
4890 if (radv_pipeline_has_tess(pipeline
)) {
4891 pipeline
->graphics
.tess_patch_control_points
=
4892 pCreateInfo
->pTessellationState
->patchControlPoints
;
4893 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
4896 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
);
4898 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
4900 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
4901 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
4903 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
4904 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
4905 if (loc
->sgpr_idx
!= -1) {
4906 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
4907 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
4908 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
4909 pipeline
->graphics
.vtx_emit_num
= 3;
4911 pipeline
->graphics
.vtx_emit_num
= 2;
4914 /* Find the last vertex shader stage that eventually uses streamout. */
4915 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
4917 result
= radv_pipeline_scratch_init(device
, pipeline
);
4918 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, gs_out
);
4924 radv_graphics_pipeline_create(
4926 VkPipelineCache _cache
,
4927 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4928 const struct radv_graphics_pipeline_create_info
*extra
,
4929 const VkAllocationCallbacks
*pAllocator
,
4930 VkPipeline
*pPipeline
)
4932 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4933 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4934 struct radv_pipeline
*pipeline
;
4937 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
4938 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4939 if (pipeline
== NULL
)
4940 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4942 vk_object_base_init(&device
->vk
, &pipeline
->base
,
4943 VK_OBJECT_TYPE_PIPELINE
);
4945 result
= radv_pipeline_init(pipeline
, device
, cache
,
4946 pCreateInfo
, extra
);
4947 if (result
!= VK_SUCCESS
) {
4948 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
4952 *pPipeline
= radv_pipeline_to_handle(pipeline
);
4957 VkResult
radv_CreateGraphicsPipelines(
4959 VkPipelineCache pipelineCache
,
4961 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
4962 const VkAllocationCallbacks
* pAllocator
,
4963 VkPipeline
* pPipelines
)
4965 VkResult result
= VK_SUCCESS
;
4968 for (; i
< count
; i
++) {
4970 r
= radv_graphics_pipeline_create(_device
,
4973 NULL
, pAllocator
, &pPipelines
[i
]);
4974 if (r
!= VK_SUCCESS
) {
4976 pPipelines
[i
] = VK_NULL_HANDLE
;
4978 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
4983 for (; i
< count
; ++i
)
4984 pPipelines
[i
] = VK_NULL_HANDLE
;
4991 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
4993 struct radv_shader_variant
*compute_shader
;
4994 struct radv_device
*device
= pipeline
->device
;
4995 unsigned threads_per_threadgroup
;
4996 unsigned threadgroups_per_cu
= 1;
4997 unsigned waves_per_threadgroup
;
4998 unsigned max_waves_per_sh
= 0;
5001 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5002 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5004 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5005 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5007 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5008 radeon_emit(&pipeline
->cs
, va
>> 8);
5009 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5011 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5012 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5013 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5014 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5015 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5018 /* Calculate best compute resource limits. */
5019 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5020 compute_shader
->info
.cs
.block_size
[1] *
5021 compute_shader
->info
.cs
.block_size
[2];
5022 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5023 compute_shader
->info
.wave_size
);
5025 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5026 waves_per_threadgroup
== 1)
5027 threadgroups_per_cu
= 2;
5029 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5030 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5031 waves_per_threadgroup
,
5033 threadgroups_per_cu
));
5035 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5036 radeon_emit(&pipeline
->cs
,
5037 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5038 radeon_emit(&pipeline
->cs
,
5039 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5040 radeon_emit(&pipeline
->cs
,
5041 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5043 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5046 static struct radv_pipeline_key
5047 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5048 const VkComputePipelineCreateInfo
*pCreateInfo
)
5050 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5051 struct radv_pipeline_key key
;
5052 memset(&key
, 0, sizeof(key
));
5054 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5055 key
.optimisations_disabled
= 1;
5057 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5058 vk_find_struct_const(stage
->pNext
,
5059 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5061 if (subgroup_size
) {
5062 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5063 subgroup_size
->requiredSubgroupSize
== 64);
5064 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5070 static VkResult
radv_compute_pipeline_create(
5072 VkPipelineCache _cache
,
5073 const VkComputePipelineCreateInfo
* pCreateInfo
,
5074 const VkAllocationCallbacks
* pAllocator
,
5075 VkPipeline
* pPipeline
)
5077 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5078 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5079 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5080 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5081 struct radv_pipeline
*pipeline
;
5084 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5085 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5086 if (pipeline
== NULL
)
5087 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5089 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5090 VK_OBJECT_TYPE_PIPELINE
);
5092 pipeline
->device
= device
;
5093 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5094 assert(pipeline
->layout
);
5096 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5097 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5098 radv_init_feedback(creation_feedback
);
5100 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5101 if (creation_feedback
)
5102 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5104 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5106 struct radv_pipeline_key key
=
5107 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5109 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5110 pCreateInfo
->flags
, pipeline_feedback
,
5112 if (result
!= VK_SUCCESS
) {
5113 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5117 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5118 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5119 result
= radv_pipeline_scratch_init(device
, pipeline
);
5120 if (result
!= VK_SUCCESS
) {
5121 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5125 radv_compute_generate_pm4(pipeline
);
5127 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5132 VkResult
radv_CreateComputePipelines(
5134 VkPipelineCache pipelineCache
,
5136 const VkComputePipelineCreateInfo
* pCreateInfos
,
5137 const VkAllocationCallbacks
* pAllocator
,
5138 VkPipeline
* pPipelines
)
5140 VkResult result
= VK_SUCCESS
;
5143 for (; i
< count
; i
++) {
5145 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5147 pAllocator
, &pPipelines
[i
]);
5148 if (r
!= VK_SUCCESS
) {
5150 pPipelines
[i
] = VK_NULL_HANDLE
;
5152 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5157 for (; i
< count
; ++i
)
5158 pPipelines
[i
] = VK_NULL_HANDLE
;
5164 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5167 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5168 if (!pipeline
->shaders
[i
])
5171 if (i
== MESA_SHADER_GEOMETRY
&&
5172 !radv_pipeline_has_ngg(pipeline
)) {
5182 static struct radv_shader_variant
*
5183 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5185 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5186 if (!pipeline
->shaders
[i
])
5190 return pipeline
->shaders
[i
];
5195 if (i
== MESA_SHADER_GEOMETRY
&&
5196 !radv_pipeline_has_ngg(pipeline
)) {
5199 return pipeline
->gs_copy_shader
;
5209 /* Basically strlcpy (which does not exist on linux) specialized for
5211 static void desc_copy(char *desc
, const char *src
) {
5212 int len
= strlen(src
);
5213 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5214 memcpy(desc
, src
, len
);
5215 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5218 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5220 const VkPipelineInfoKHR
* pPipelineInfo
,
5221 uint32_t* pExecutableCount
,
5222 VkPipelineExecutablePropertiesKHR
* pProperties
)
5224 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5225 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5228 *pExecutableCount
= total_count
;
5232 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5233 for (unsigned i
= 0, executable_idx
= 0;
5234 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5235 if (!pipeline
->shaders
[i
])
5237 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5238 const char *name
= NULL
;
5239 const char *description
= NULL
;
5241 case MESA_SHADER_VERTEX
:
5242 name
= "Vertex Shader";
5243 description
= "Vulkan Vertex Shader";
5245 case MESA_SHADER_TESS_CTRL
:
5246 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5247 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5248 name
= "Vertex + Tessellation Control Shaders";
5249 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5251 name
= "Tessellation Control Shader";
5252 description
= "Vulkan Tessellation Control Shader";
5255 case MESA_SHADER_TESS_EVAL
:
5256 name
= "Tessellation Evaluation Shader";
5257 description
= "Vulkan Tessellation Evaluation Shader";
5259 case MESA_SHADER_GEOMETRY
:
5260 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5261 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5262 name
= "Tessellation Evaluation + Geometry Shaders";
5263 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5264 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5265 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5266 name
= "Vertex + Geometry Shader";
5267 description
= "Combined Vulkan Vertex and Geometry Shaders";
5269 name
= "Geometry Shader";
5270 description
= "Vulkan Geometry Shader";
5273 case MESA_SHADER_FRAGMENT
:
5274 name
= "Fragment Shader";
5275 description
= "Vulkan Fragment Shader";
5277 case MESA_SHADER_COMPUTE
:
5278 name
= "Compute Shader";
5279 description
= "Vulkan Compute Shader";
5283 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5284 desc_copy(pProperties
[executable_idx
].name
, name
);
5285 desc_copy(pProperties
[executable_idx
].description
, description
);
5288 if (i
== MESA_SHADER_GEOMETRY
&&
5289 !radv_pipeline_has_ngg(pipeline
)) {
5290 assert(pipeline
->gs_copy_shader
);
5291 if (executable_idx
>= count
)
5294 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5295 pProperties
[executable_idx
].subgroupSize
= 64;
5296 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5297 desc_copy(pProperties
[executable_idx
].description
,
5298 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5304 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5305 *pExecutableCount
= count
;
5309 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5311 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5312 uint32_t* pStatisticCount
,
5313 VkPipelineExecutableStatisticKHR
* pStatistics
)
5315 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5316 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5317 gl_shader_stage stage
;
5318 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5320 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5321 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5322 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5324 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5325 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5326 VkResult result
= VK_SUCCESS
;
5329 desc_copy(s
->name
, "SGPRs");
5330 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5331 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5332 s
->value
.u64
= shader
->config
.num_sgprs
;
5337 desc_copy(s
->name
, "VGPRs");
5338 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5339 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5340 s
->value
.u64
= shader
->config
.num_vgprs
;
5345 desc_copy(s
->name
, "Spilled SGPRs");
5346 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5347 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5348 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5353 desc_copy(s
->name
, "Spilled VGPRs");
5354 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5355 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5356 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5361 desc_copy(s
->name
, "PrivMem VGPRs");
5362 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5363 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5364 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5369 desc_copy(s
->name
, "Code size");
5370 desc_copy(s
->description
, "Code size in bytes");
5371 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5372 s
->value
.u64
= shader
->exec_size
;
5377 desc_copy(s
->name
, "LDS size");
5378 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5379 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5380 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5385 desc_copy(s
->name
, "Scratch size");
5386 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5387 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5388 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5393 desc_copy(s
->name
, "Subgroups per SIMD");
5394 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5395 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5396 s
->value
.u64
= max_waves
;
5400 if (shader
->statistics
) {
5401 for (unsigned i
= 0; i
< shader
->statistics
->count
; i
++) {
5402 struct radv_compiler_statistic_info
*info
= &shader
->statistics
->infos
[i
];
5403 uint32_t value
= shader
->statistics
->values
[i
];
5405 desc_copy(s
->name
, info
->name
);
5406 desc_copy(s
->description
, info
->desc
);
5407 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5408 s
->value
.u64
= value
;
5415 *pStatisticCount
= s
- pStatistics
;
5417 *pStatisticCount
= end
- pStatistics
;
5418 result
= VK_INCOMPLETE
;
5420 *pStatisticCount
= s
- pStatistics
;
5426 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5428 size_t total_size
= strlen(src
) + 1;
5431 *data_size
= total_size
;
5435 size_t size
= MIN2(total_size
, *data_size
);
5437 memcpy(data
, src
, size
);
5439 *((char*)data
+ size
- 1) = 0;
5440 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5443 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5445 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5446 uint32_t* pInternalRepresentationCount
,
5447 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5449 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5450 gl_shader_stage stage
;
5451 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5453 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5454 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5455 VkResult result
= VK_SUCCESS
;
5459 desc_copy(p
->name
, "NIR Shader(s)");
5460 desc_copy(p
->description
, "The optimized NIR shader(s)");
5461 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5462 result
= VK_INCOMPLETE
;
5469 if (pipeline
->device
->physical_device
->use_llvm
) {
5470 desc_copy(p
->name
, "LLVM IR");
5471 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5473 desc_copy(p
->name
, "ACO IR");
5474 desc_copy(p
->description
, "The ACO IR after some optimizations");
5476 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5477 result
= VK_INCOMPLETE
;
5484 desc_copy(p
->name
, "Assembly");
5485 desc_copy(p
->description
, "Final Assembly");
5486 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5487 result
= VK_INCOMPLETE
;
5491 if (!pInternalRepresentations
)
5492 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5494 result
= VK_INCOMPLETE
;
5495 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5497 *pInternalRepresentationCount
= p
- pInternalRepresentations
;