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vulkan/wsi: Do image creation in common code
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36 #include "vk_util.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40
41 #include "sid.h"
42 #include "gfx9d.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
49
50 static void
51 radv_pipeline_destroy(struct radv_device *device,
52 struct radv_pipeline *pipeline,
53 const VkAllocationCallbacks* allocator)
54 {
55 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
56 if (pipeline->shaders[i])
57 radv_shader_variant_destroy(device, pipeline->shaders[i]);
58
59 if (pipeline->gs_copy_shader)
60 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
61
62 vk_free2(&device->alloc, allocator, pipeline);
63 }
64
65 void radv_DestroyPipeline(
66 VkDevice _device,
67 VkPipeline _pipeline,
68 const VkAllocationCallbacks* pAllocator)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
72
73 if (!_pipeline)
74 return;
75
76 radv_pipeline_destroy(device, pipeline, pAllocator);
77 }
78
79 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
80 {
81 int i;
82
83 for (i = 0; i < MESA_SHADER_STAGES; i++) {
84 if (!pipeline->shaders[i])
85 continue;
86
87 radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr);
88 }
89 }
90
91 static uint32_t get_hash_flags(struct radv_device *device)
92 {
93 uint32_t hash_flags = 0;
94
95 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
96 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
97 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
98 hash_flags |= RADV_HASH_SHADER_SISCHED;
99 return hash_flags;
100 }
101
102 static VkResult
103 radv_pipeline_scratch_init(struct radv_device *device,
104 struct radv_pipeline *pipeline)
105 {
106 unsigned scratch_bytes_per_wave = 0;
107 unsigned max_waves = 0;
108 unsigned min_waves = 1;
109
110 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
111 if (pipeline->shaders[i]) {
112 unsigned max_stage_waves = device->scratch_waves;
113
114 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
115 pipeline->shaders[i]->config.scratch_bytes_per_wave);
116
117 max_stage_waves = MIN2(max_stage_waves,
118 4 * device->physical_device->rad_info.num_good_compute_units *
119 (256 / pipeline->shaders[i]->config.num_vgprs));
120 max_waves = MAX2(max_waves, max_stage_waves);
121 }
122 }
123
124 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
125 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
126 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
127 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
128 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
129 }
130
131 if (scratch_bytes_per_wave)
132 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
133
134 if (scratch_bytes_per_wave && max_waves < min_waves) {
135 /* Not really true at this moment, but will be true on first
136 * execution. Avoid having hanging shaders. */
137 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
138 }
139 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
140 pipeline->max_waves = max_waves;
141 return VK_SUCCESS;
142 }
143
144 static uint32_t si_translate_blend_function(VkBlendOp op)
145 {
146 switch (op) {
147 case VK_BLEND_OP_ADD:
148 return V_028780_COMB_DST_PLUS_SRC;
149 case VK_BLEND_OP_SUBTRACT:
150 return V_028780_COMB_SRC_MINUS_DST;
151 case VK_BLEND_OP_REVERSE_SUBTRACT:
152 return V_028780_COMB_DST_MINUS_SRC;
153 case VK_BLEND_OP_MIN:
154 return V_028780_COMB_MIN_DST_SRC;
155 case VK_BLEND_OP_MAX:
156 return V_028780_COMB_MAX_DST_SRC;
157 default:
158 return 0;
159 }
160 }
161
162 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
163 {
164 switch (factor) {
165 case VK_BLEND_FACTOR_ZERO:
166 return V_028780_BLEND_ZERO;
167 case VK_BLEND_FACTOR_ONE:
168 return V_028780_BLEND_ONE;
169 case VK_BLEND_FACTOR_SRC_COLOR:
170 return V_028780_BLEND_SRC_COLOR;
171 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
172 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
173 case VK_BLEND_FACTOR_DST_COLOR:
174 return V_028780_BLEND_DST_COLOR;
175 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
176 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
177 case VK_BLEND_FACTOR_SRC_ALPHA:
178 return V_028780_BLEND_SRC_ALPHA;
179 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
180 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
181 case VK_BLEND_FACTOR_DST_ALPHA:
182 return V_028780_BLEND_DST_ALPHA;
183 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
184 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
185 case VK_BLEND_FACTOR_CONSTANT_COLOR:
186 return V_028780_BLEND_CONSTANT_COLOR;
187 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
188 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
189 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
190 return V_028780_BLEND_CONSTANT_ALPHA;
191 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
192 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
193 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
194 return V_028780_BLEND_SRC_ALPHA_SATURATE;
195 case VK_BLEND_FACTOR_SRC1_COLOR:
196 return V_028780_BLEND_SRC1_COLOR;
197 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
198 return V_028780_BLEND_INV_SRC1_COLOR;
199 case VK_BLEND_FACTOR_SRC1_ALPHA:
200 return V_028780_BLEND_SRC1_ALPHA;
201 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
202 return V_028780_BLEND_INV_SRC1_ALPHA;
203 default:
204 return 0;
205 }
206 }
207
208 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
209 {
210 switch (op) {
211 case VK_BLEND_OP_ADD:
212 return V_028760_OPT_COMB_ADD;
213 case VK_BLEND_OP_SUBTRACT:
214 return V_028760_OPT_COMB_SUBTRACT;
215 case VK_BLEND_OP_REVERSE_SUBTRACT:
216 return V_028760_OPT_COMB_REVSUBTRACT;
217 case VK_BLEND_OP_MIN:
218 return V_028760_OPT_COMB_MIN;
219 case VK_BLEND_OP_MAX:
220 return V_028760_OPT_COMB_MAX;
221 default:
222 return V_028760_OPT_COMB_BLEND_DISABLED;
223 }
224 }
225
226 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
227 {
228 switch (factor) {
229 case VK_BLEND_FACTOR_ZERO:
230 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
231 case VK_BLEND_FACTOR_ONE:
232 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
233 case VK_BLEND_FACTOR_SRC_COLOR:
234 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
235 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
236 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
237 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
238 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
239 case VK_BLEND_FACTOR_SRC_ALPHA:
240 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
241 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
242 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
243 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
244 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
245 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
246 default:
247 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
248 }
249 }
250
251 /**
252 * Get rid of DST in the blend factors by commuting the operands:
253 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
254 */
255 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
256 unsigned *dst_factor, unsigned expected_dst,
257 unsigned replacement_src)
258 {
259 if (*src_factor == expected_dst &&
260 *dst_factor == VK_BLEND_FACTOR_ZERO) {
261 *src_factor = VK_BLEND_FACTOR_ZERO;
262 *dst_factor = replacement_src;
263
264 /* Commuting the operands requires reversing subtractions. */
265 if (*func == VK_BLEND_OP_SUBTRACT)
266 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
267 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
268 *func = VK_BLEND_OP_SUBTRACT;
269 }
270 }
271
272 static bool si_blend_factor_uses_dst(unsigned factor)
273 {
274 return factor == VK_BLEND_FACTOR_DST_COLOR ||
275 factor == VK_BLEND_FACTOR_DST_ALPHA ||
276 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
277 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
278 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
279 }
280
281 static bool is_dual_src(VkBlendFactor factor)
282 {
283 switch (factor) {
284 case VK_BLEND_FACTOR_SRC1_COLOR:
285 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
286 case VK_BLEND_FACTOR_SRC1_ALPHA:
287 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
288 return true;
289 default:
290 return false;
291 }
292 }
293
294 static unsigned si_choose_spi_color_format(VkFormat vk_format,
295 bool blend_enable,
296 bool blend_need_alpha)
297 {
298 const struct vk_format_description *desc = vk_format_description(vk_format);
299 unsigned format, ntype, swap;
300
301 /* Alpha is needed for alpha-to-coverage.
302 * Blending may be with or without alpha.
303 */
304 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
305 unsigned alpha = 0; /* exports alpha, but may not support blending */
306 unsigned blend = 0; /* supports blending, but may not export alpha */
307 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
308
309 format = radv_translate_colorformat(vk_format);
310 ntype = radv_translate_color_numformat(vk_format, desc,
311 vk_format_get_first_non_void_channel(vk_format));
312 swap = radv_translate_colorswap(vk_format, false);
313
314 /* Choose the SPI color formats. These are required values for Stoney/RB+.
315 * Other chips have multiple choices, though they are not necessarily better.
316 */
317 switch (format) {
318 case V_028C70_COLOR_5_6_5:
319 case V_028C70_COLOR_1_5_5_5:
320 case V_028C70_COLOR_5_5_5_1:
321 case V_028C70_COLOR_4_4_4_4:
322 case V_028C70_COLOR_10_11_11:
323 case V_028C70_COLOR_11_11_10:
324 case V_028C70_COLOR_8:
325 case V_028C70_COLOR_8_8:
326 case V_028C70_COLOR_8_8_8_8:
327 case V_028C70_COLOR_10_10_10_2:
328 case V_028C70_COLOR_2_10_10_10:
329 if (ntype == V_028C70_NUMBER_UINT)
330 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
331 else if (ntype == V_028C70_NUMBER_SINT)
332 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
333 else
334 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
335 break;
336
337 case V_028C70_COLOR_16:
338 case V_028C70_COLOR_16_16:
339 case V_028C70_COLOR_16_16_16_16:
340 if (ntype == V_028C70_NUMBER_UNORM ||
341 ntype == V_028C70_NUMBER_SNORM) {
342 /* UNORM16 and SNORM16 don't support blending */
343 if (ntype == V_028C70_NUMBER_UNORM)
344 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
345 else
346 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
347
348 /* Use 32 bits per channel for blending. */
349 if (format == V_028C70_COLOR_16) {
350 if (swap == V_028C70_SWAP_STD) { /* R */
351 blend = V_028714_SPI_SHADER_32_R;
352 blend_alpha = V_028714_SPI_SHADER_32_AR;
353 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
354 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
355 else
356 assert(0);
357 } else if (format == V_028C70_COLOR_16_16) {
358 if (swap == V_028C70_SWAP_STD) { /* RG */
359 blend = V_028714_SPI_SHADER_32_GR;
360 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
361 } else if (swap == V_028C70_SWAP_ALT) /* RA */
362 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
363 else
364 assert(0);
365 } else /* 16_16_16_16 */
366 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
367 } else if (ntype == V_028C70_NUMBER_UINT)
368 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
369 else if (ntype == V_028C70_NUMBER_SINT)
370 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
371 else if (ntype == V_028C70_NUMBER_FLOAT)
372 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
373 else
374 assert(0);
375 break;
376
377 case V_028C70_COLOR_32:
378 if (swap == V_028C70_SWAP_STD) { /* R */
379 blend = normal = V_028714_SPI_SHADER_32_R;
380 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
381 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
382 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
383 else
384 assert(0);
385 break;
386
387 case V_028C70_COLOR_32_32:
388 if (swap == V_028C70_SWAP_STD) { /* RG */
389 blend = normal = V_028714_SPI_SHADER_32_GR;
390 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
391 } else if (swap == V_028C70_SWAP_ALT) /* RA */
392 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
393 else
394 assert(0);
395 break;
396
397 case V_028C70_COLOR_32_32_32_32:
398 case V_028C70_COLOR_8_24:
399 case V_028C70_COLOR_24_8:
400 case V_028C70_COLOR_X24_8_32_FLOAT:
401 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
402 break;
403
404 default:
405 unreachable("unhandled blend format");
406 }
407
408 if (blend_enable && blend_need_alpha)
409 return blend_alpha;
410 else if(blend_need_alpha)
411 return alpha;
412 else if(blend_enable)
413 return blend;
414 else
415 return normal;
416 }
417
418 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
419 {
420 unsigned i, cb_shader_mask = 0;
421
422 for (i = 0; i < 8; i++) {
423 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
424 case V_028714_SPI_SHADER_ZERO:
425 break;
426 case V_028714_SPI_SHADER_32_R:
427 cb_shader_mask |= 0x1 << (i * 4);
428 break;
429 case V_028714_SPI_SHADER_32_GR:
430 cb_shader_mask |= 0x3 << (i * 4);
431 break;
432 case V_028714_SPI_SHADER_32_AR:
433 cb_shader_mask |= 0x9 << (i * 4);
434 break;
435 case V_028714_SPI_SHADER_FP16_ABGR:
436 case V_028714_SPI_SHADER_UNORM16_ABGR:
437 case V_028714_SPI_SHADER_SNORM16_ABGR:
438 case V_028714_SPI_SHADER_UINT16_ABGR:
439 case V_028714_SPI_SHADER_SINT16_ABGR:
440 case V_028714_SPI_SHADER_32_ABGR:
441 cb_shader_mask |= 0xf << (i * 4);
442 break;
443 default:
444 assert(0);
445 }
446 }
447 return cb_shader_mask;
448 }
449
450 static void
451 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
452 const VkGraphicsPipelineCreateInfo *pCreateInfo,
453 uint32_t blend_enable,
454 uint32_t blend_need_alpha,
455 bool single_cb_enable,
456 bool blend_mrt0_is_dual_src)
457 {
458 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
459 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
460 struct radv_blend_state *blend = &pipeline->graphics.blend;
461 unsigned col_format = 0;
462
463 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
464 unsigned cf;
465
466 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
467 cf = V_028714_SPI_SHADER_ZERO;
468 } else {
469 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
470
471 cf = si_choose_spi_color_format(attachment->format,
472 blend_enable & (1 << i),
473 blend_need_alpha & (1 << i));
474 }
475
476 col_format |= cf << (4 * i);
477 }
478
479 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
480
481 if (blend_mrt0_is_dual_src)
482 col_format |= (col_format & 0xf) << 4;
483 blend->spi_shader_col_format = col_format;
484 }
485
486 static bool
487 format_is_int8(VkFormat format)
488 {
489 const struct vk_format_description *desc = vk_format_description(format);
490 int channel = vk_format_get_first_non_void_channel(format);
491
492 return channel >= 0 && desc->channel[channel].pure_integer &&
493 desc->channel[channel].size == 8;
494 }
495
496 static bool
497 format_is_int10(VkFormat format)
498 {
499 const struct vk_format_description *desc = vk_format_description(format);
500
501 if (desc->nr_channels != 4)
502 return false;
503 for (unsigned i = 0; i < 4; i++) {
504 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
505 return true;
506 }
507 return false;
508 }
509
510 unsigned radv_format_meta_fs_key(VkFormat format)
511 {
512 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
513 bool is_int8 = format_is_int8(format);
514 bool is_int10 = format_is_int10(format);
515
516 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
517 }
518
519 static void
520 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
521 unsigned *is_int8, unsigned *is_int10)
522 {
523 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
524 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
525 *is_int8 = 0;
526 *is_int10 = 0;
527
528 for (unsigned i = 0; i < subpass->color_count; ++i) {
529 struct radv_render_pass_attachment *attachment;
530
531 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
532 continue;
533
534 attachment = pass->attachments + subpass->color_attachments[i].attachment;
535
536 if (format_is_int8(attachment->format))
537 *is_int8 |= 1 << i;
538 if (format_is_int10(attachment->format))
539 *is_int10 |= 1 << i;
540 }
541 }
542
543 static void
544 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
545 const VkGraphicsPipelineCreateInfo *pCreateInfo,
546 const struct radv_graphics_pipeline_create_info *extra)
547 {
548 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
549 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
550 struct radv_blend_state *blend = &pipeline->graphics.blend;
551 unsigned mode = V_028808_CB_NORMAL;
552 uint32_t blend_enable = 0, blend_need_alpha = 0;
553 bool blend_mrt0_is_dual_src = false;
554 int i;
555 bool single_cb_enable = false;
556
557 if (!vkblend)
558 return;
559
560 if (extra && extra->custom_blend_mode) {
561 single_cb_enable = true;
562 mode = extra->custom_blend_mode;
563 }
564 blend->cb_color_control = 0;
565 if (vkblend->logicOpEnable)
566 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
567 else
568 blend->cb_color_control |= S_028808_ROP3(0xcc);
569
570 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
571 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
572 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
573 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
574
575 if (vkms && vkms->alphaToCoverageEnable) {
576 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
577 }
578
579 blend->cb_target_mask = 0;
580 for (i = 0; i < vkblend->attachmentCount; i++) {
581 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
582 unsigned blend_cntl = 0;
583 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
584 VkBlendOp eqRGB = att->colorBlendOp;
585 VkBlendFactor srcRGB = att->srcColorBlendFactor;
586 VkBlendFactor dstRGB = att->dstColorBlendFactor;
587 VkBlendOp eqA = att->alphaBlendOp;
588 VkBlendFactor srcA = att->srcAlphaBlendFactor;
589 VkBlendFactor dstA = att->dstAlphaBlendFactor;
590
591 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
592
593 if (!att->colorWriteMask)
594 continue;
595
596 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
597 if (!att->blendEnable) {
598 blend->cb_blend_control[i] = blend_cntl;
599 continue;
600 }
601
602 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
603 if (i == 0)
604 blend_mrt0_is_dual_src = true;
605
606 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
607 srcRGB = VK_BLEND_FACTOR_ONE;
608 dstRGB = VK_BLEND_FACTOR_ONE;
609 }
610 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
611 srcA = VK_BLEND_FACTOR_ONE;
612 dstA = VK_BLEND_FACTOR_ONE;
613 }
614
615 /* Blending optimizations for RB+.
616 * These transformations don't change the behavior.
617 *
618 * First, get rid of DST in the blend factors:
619 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
620 */
621 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
622 VK_BLEND_FACTOR_DST_COLOR,
623 VK_BLEND_FACTOR_SRC_COLOR);
624
625 si_blend_remove_dst(&eqA, &srcA, &dstA,
626 VK_BLEND_FACTOR_DST_COLOR,
627 VK_BLEND_FACTOR_SRC_COLOR);
628
629 si_blend_remove_dst(&eqA, &srcA, &dstA,
630 VK_BLEND_FACTOR_DST_ALPHA,
631 VK_BLEND_FACTOR_SRC_ALPHA);
632
633 /* Look up the ideal settings from tables. */
634 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
635 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
636 srcA_opt = si_translate_blend_opt_factor(srcA, true);
637 dstA_opt = si_translate_blend_opt_factor(dstA, true);
638
639 /* Handle interdependencies. */
640 if (si_blend_factor_uses_dst(srcRGB))
641 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
642 if (si_blend_factor_uses_dst(srcA))
643 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
644
645 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
646 (dstRGB == VK_BLEND_FACTOR_ZERO ||
647 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
648 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
649 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
650
651 /* Set the final value. */
652 blend->sx_mrt_blend_opt[i] =
653 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
654 S_028760_COLOR_DST_OPT(dstRGB_opt) |
655 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
656 S_028760_ALPHA_SRC_OPT(srcA_opt) |
657 S_028760_ALPHA_DST_OPT(dstA_opt) |
658 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
659 blend_cntl |= S_028780_ENABLE(1);
660
661 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
662 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
663 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
664 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
665 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
666 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
667 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
668 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
669 }
670 blend->cb_blend_control[i] = blend_cntl;
671
672 blend_enable |= 1 << i;
673
674 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
675 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
676 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
677 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
678 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
679 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
680 blend_need_alpha |= 1 << i;
681 }
682 for (i = vkblend->attachmentCount; i < 8; i++) {
683 blend->cb_blend_control[i] = 0;
684 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
685 }
686
687 /* disable RB+ for now */
688 if (pipeline->device->physical_device->has_rbplus)
689 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
690
691 if (blend->cb_target_mask)
692 blend->cb_color_control |= S_028808_MODE(mode);
693 else
694 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
695
696 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
697 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
698 }
699
700 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
701 {
702 switch (op) {
703 case VK_STENCIL_OP_KEEP:
704 return V_02842C_STENCIL_KEEP;
705 case VK_STENCIL_OP_ZERO:
706 return V_02842C_STENCIL_ZERO;
707 case VK_STENCIL_OP_REPLACE:
708 return V_02842C_STENCIL_REPLACE_TEST;
709 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
710 return V_02842C_STENCIL_ADD_CLAMP;
711 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
712 return V_02842C_STENCIL_SUB_CLAMP;
713 case VK_STENCIL_OP_INVERT:
714 return V_02842C_STENCIL_INVERT;
715 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
716 return V_02842C_STENCIL_ADD_WRAP;
717 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
718 return V_02842C_STENCIL_SUB_WRAP;
719 default:
720 return 0;
721 }
722 }
723 static void
724 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
725 const VkGraphicsPipelineCreateInfo *pCreateInfo,
726 const struct radv_graphics_pipeline_create_info *extra)
727 {
728 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
729 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
730
731 if (!vkds)
732 return;
733
734 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
735 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
736 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
737 return;
738
739 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
740 bool has_depth_attachment = vk_format_is_depth(attachment->format);
741 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
742
743 if (has_depth_attachment) {
744 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
745 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
746 S_028800_ZFUNC(vkds->depthCompareOp) |
747 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
748 }
749
750 if (has_stencil_attachment && vkds->stencilTestEnable) {
751 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
752 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
753 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
754 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
755 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
756
757 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
758 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
759 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
760 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
761 }
762
763 if (extra) {
764
765 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
766 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
767
768 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
769 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
770 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
771 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
772 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
773 }
774 }
775
776 static uint32_t si_translate_fill(VkPolygonMode func)
777 {
778 switch(func) {
779 case VK_POLYGON_MODE_FILL:
780 return V_028814_X_DRAW_TRIANGLES;
781 case VK_POLYGON_MODE_LINE:
782 return V_028814_X_DRAW_LINES;
783 case VK_POLYGON_MODE_POINT:
784 return V_028814_X_DRAW_POINTS;
785 default:
786 assert(0);
787 return V_028814_X_DRAW_POINTS;
788 }
789 }
790 static void
791 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
792 const VkGraphicsPipelineCreateInfo *pCreateInfo)
793 {
794 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
795 struct radv_raster_state *raster = &pipeline->graphics.raster;
796
797 raster->spi_interp_control =
798 S_0286D4_FLAT_SHADE_ENA(1) |
799 S_0286D4_PNT_SPRITE_ENA(1) |
800 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
801 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
802 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
803 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
804 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
805
806
807 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
808 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
809 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
810 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
811 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
812 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
813
814 raster->pa_su_vtx_cntl =
815 S_028BE4_PIX_CENTER(1) | // TODO verify
816 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
817 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
818
819 raster->pa_su_sc_mode_cntl =
820 S_028814_FACE(vkraster->frontFace) |
821 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
822 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
823 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
824 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
825 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
826 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
827 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
828 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
829
830 }
831
832 static void
833 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
834 const VkGraphicsPipelineCreateInfo *pCreateInfo)
835 {
836 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
837 struct radv_multisample_state *ms = &pipeline->graphics.ms;
838 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
839 int ps_iter_samples = 1;
840 uint32_t mask = 0xffff;
841
842 if (vkms)
843 ms->num_samples = vkms->rasterizationSamples;
844 else
845 ms->num_samples = 1;
846
847 if (vkms && vkms->sampleShadingEnable) {
848 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
849 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
850 ps_iter_samples = ms->num_samples;
851 }
852
853 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
854 ms->pa_sc_aa_config = 0;
855 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
856 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
857 ms->pa_sc_mode_cntl_1 =
858 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
859 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
860 /* always 1: */
861 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
862 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
863 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
864 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
865 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
866 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
867 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
868
869 if (ms->num_samples > 1) {
870 unsigned log_samples = util_logbase2(ms->num_samples);
871 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
872 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
873 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
874 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
875 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
876 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
877 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
878 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
879 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
880 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
881 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
882 }
883
884 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
885 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
886 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
887 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
888 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
889 }
890
891 if (vkms && vkms->pSampleMask) {
892 mask = vkms->pSampleMask[0] & 0xffff;
893 }
894
895 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
896 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
897 }
898
899 static bool
900 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
901 {
902 switch (topology) {
903 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
904 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
905 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
906 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
907 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
908 return false;
909 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
910 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
911 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
912 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
913 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
914 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
915 return true;
916 default:
917 unreachable("unhandled primitive type");
918 }
919 }
920
921 static uint32_t
922 si_translate_prim(enum VkPrimitiveTopology topology)
923 {
924 switch (topology) {
925 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
926 return V_008958_DI_PT_POINTLIST;
927 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
928 return V_008958_DI_PT_LINELIST;
929 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
930 return V_008958_DI_PT_LINESTRIP;
931 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
932 return V_008958_DI_PT_TRILIST;
933 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
934 return V_008958_DI_PT_TRISTRIP;
935 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
936 return V_008958_DI_PT_TRIFAN;
937 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
938 return V_008958_DI_PT_LINELIST_ADJ;
939 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
940 return V_008958_DI_PT_LINESTRIP_ADJ;
941 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
942 return V_008958_DI_PT_TRILIST_ADJ;
943 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
944 return V_008958_DI_PT_TRISTRIP_ADJ;
945 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
946 return V_008958_DI_PT_PATCH;
947 default:
948 assert(0);
949 return 0;
950 }
951 }
952
953 static uint32_t
954 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
955 {
956 switch (gl_prim) {
957 case 0: /* GL_POINTS */
958 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
959 case 1: /* GL_LINES */
960 case 3: /* GL_LINE_STRIP */
961 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
962 case 0x8E7A: /* GL_ISOLINES */
963 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
964
965 case 4: /* GL_TRIANGLES */
966 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
967 case 5: /* GL_TRIANGLE_STRIP */
968 case 7: /* GL_QUADS */
969 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
970 default:
971 assert(0);
972 return 0;
973 }
974 }
975
976 static uint32_t
977 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
978 {
979 switch (topology) {
980 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
981 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
982 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
983 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
984 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
985 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
986 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
987 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
988 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
989 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
990 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
991 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
992 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
993 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
994 default:
995 assert(0);
996 return 0;
997 }
998 }
999
1000 static unsigned si_map_swizzle(unsigned swizzle)
1001 {
1002 switch (swizzle) {
1003 case VK_SWIZZLE_Y:
1004 return V_008F0C_SQ_SEL_Y;
1005 case VK_SWIZZLE_Z:
1006 return V_008F0C_SQ_SEL_Z;
1007 case VK_SWIZZLE_W:
1008 return V_008F0C_SQ_SEL_W;
1009 case VK_SWIZZLE_0:
1010 return V_008F0C_SQ_SEL_0;
1011 case VK_SWIZZLE_1:
1012 return V_008F0C_SQ_SEL_1;
1013 default: /* VK_SWIZZLE_X */
1014 return V_008F0C_SQ_SEL_X;
1015 }
1016 }
1017
1018 static void
1019 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1020 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1021 {
1022 uint32_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1023 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1024 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1025
1026 pipeline->dynamic_state = default_dynamic_state;
1027
1028 if (pCreateInfo->pDynamicState) {
1029 /* Remove all of the states that are marked as dynamic */
1030 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1031 for (uint32_t s = 0; s < count; s++)
1032 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1033 }
1034
1035 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1036
1037 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1038 *
1039 * pViewportState is [...] NULL if the pipeline
1040 * has rasterization disabled.
1041 */
1042 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1043 assert(pCreateInfo->pViewportState);
1044
1045 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1046 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1047 typed_memcpy(dynamic->viewport.viewports,
1048 pCreateInfo->pViewportState->pViewports,
1049 pCreateInfo->pViewportState->viewportCount);
1050 }
1051
1052 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1053 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1054 typed_memcpy(dynamic->scissor.scissors,
1055 pCreateInfo->pViewportState->pScissors,
1056 pCreateInfo->pViewportState->scissorCount);
1057 }
1058 }
1059
1060 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1061 assert(pCreateInfo->pRasterizationState);
1062 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1063 }
1064
1065 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1066 assert(pCreateInfo->pRasterizationState);
1067 dynamic->depth_bias.bias =
1068 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1069 dynamic->depth_bias.clamp =
1070 pCreateInfo->pRasterizationState->depthBiasClamp;
1071 dynamic->depth_bias.slope =
1072 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1073 }
1074
1075 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1076 *
1077 * pColorBlendState is [...] NULL if the pipeline has rasterization
1078 * disabled or if the subpass of the render pass the pipeline is
1079 * created against does not use any color attachments.
1080 */
1081 bool uses_color_att = false;
1082 for (unsigned i = 0; i < subpass->color_count; ++i) {
1083 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1084 uses_color_att = true;
1085 break;
1086 }
1087 }
1088
1089 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1090 assert(pCreateInfo->pColorBlendState);
1091 typed_memcpy(dynamic->blend_constants,
1092 pCreateInfo->pColorBlendState->blendConstants, 4);
1093 }
1094
1095 /* If there is no depthstencil attachment, then don't read
1096 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1097 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1098 * no need to override the depthstencil defaults in
1099 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1100 *
1101 * Section 9.2 of the Vulkan 1.0.15 spec says:
1102 *
1103 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1104 * disabled or if the subpass of the render pass the pipeline is created
1105 * against does not use a depth/stencil attachment.
1106 */
1107 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1108 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1109 assert(pCreateInfo->pDepthStencilState);
1110
1111 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1112 dynamic->depth_bounds.min =
1113 pCreateInfo->pDepthStencilState->minDepthBounds;
1114 dynamic->depth_bounds.max =
1115 pCreateInfo->pDepthStencilState->maxDepthBounds;
1116 }
1117
1118 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1119 dynamic->stencil_compare_mask.front =
1120 pCreateInfo->pDepthStencilState->front.compareMask;
1121 dynamic->stencil_compare_mask.back =
1122 pCreateInfo->pDepthStencilState->back.compareMask;
1123 }
1124
1125 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1126 dynamic->stencil_write_mask.front =
1127 pCreateInfo->pDepthStencilState->front.writeMask;
1128 dynamic->stencil_write_mask.back =
1129 pCreateInfo->pDepthStencilState->back.writeMask;
1130 }
1131
1132 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1133 dynamic->stencil_reference.front =
1134 pCreateInfo->pDepthStencilState->front.reference;
1135 dynamic->stencil_reference.back =
1136 pCreateInfo->pDepthStencilState->back.reference;
1137 }
1138 }
1139
1140 pipeline->dynamic_state.mask = states;
1141 }
1142
1143 static void calculate_gfx9_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1144 struct radv_pipeline *pipeline)
1145 {
1146 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1147 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1148 &gs_info->tes.es_info : &gs_info->vs.es_info;
1149 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1150 bool uses_adjacency;
1151 switch(pCreateInfo->pInputAssemblyState->topology) {
1152 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1153 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1154 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1155 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1156 uses_adjacency = false;
1157 break;
1158 default:
1159 uses_adjacency = false;
1160 break;
1161 }
1162
1163 /* All these are in dwords: */
1164 /* We can't allow using the whole LDS, because GS waves compete with
1165 * other shader stages for LDS space. */
1166 const unsigned max_lds_size = 8 * 1024;
1167 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1168 unsigned esgs_lds_size;
1169
1170 /* All these are per subgroup: */
1171 const unsigned max_out_prims = 32 * 1024;
1172 const unsigned max_es_verts = 255;
1173 const unsigned ideal_gs_prims = 64;
1174 unsigned max_gs_prims, gs_prims;
1175 unsigned min_es_verts, es_verts, worst_case_es_verts;
1176
1177 if (uses_adjacency || gs_num_invocations > 1)
1178 max_gs_prims = 127 / gs_num_invocations;
1179 else
1180 max_gs_prims = 255;
1181
1182 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1183 * Make sure we don't go over the maximum value.
1184 */
1185 if (gs_info->gs.vertices_out > 0) {
1186 max_gs_prims = MIN2(max_gs_prims,
1187 max_out_prims /
1188 (gs_info->gs.vertices_out * gs_num_invocations));
1189 }
1190 assert(max_gs_prims > 0);
1191
1192 /* If the primitive has adjacency, halve the number of vertices
1193 * that will be reused in multiple primitives.
1194 */
1195 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1196
1197 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1198 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1199
1200 /* Compute ESGS LDS size based on the worst case number of ES vertices
1201 * needed to create the target number of GS prims per subgroup.
1202 */
1203 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1204
1205 /* If total LDS usage is too big, refactor partitions based on ratio
1206 * of ESGS item sizes.
1207 */
1208 if (esgs_lds_size > max_lds_size) {
1209 /* Our target GS Prims Per Subgroup was too large. Calculate
1210 * the maximum number of GS Prims Per Subgroup that will fit
1211 * into LDS, capped by the maximum that the hardware can support.
1212 */
1213 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1214 max_gs_prims);
1215 assert(gs_prims > 0);
1216 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1217 max_es_verts);
1218
1219 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1220 assert(esgs_lds_size <= max_lds_size);
1221 }
1222
1223 /* Now calculate remaining ESGS information. */
1224 if (esgs_lds_size)
1225 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1226 else
1227 es_verts = max_es_verts;
1228
1229 /* Vertices for adjacency primitives are not always reused, so restore
1230 * it for ES_VERTS_PER_SUBGRP.
1231 */
1232 min_es_verts = gs_info->gs.vertices_in;
1233
1234 /* For normal primitives, the VGT only checks if they are past the ES
1235 * verts per subgroup after allocating a full GS primitive and if they
1236 * are, kick off a new subgroup. But if those additional ES verts are
1237 * unique (e.g. not reused) we need to make sure there is enough LDS
1238 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1239 */
1240 es_verts -= min_es_verts - 1;
1241
1242 uint32_t es_verts_per_subgroup = es_verts;
1243 uint32_t gs_prims_per_subgroup = gs_prims;
1244 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1245 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1246 pipeline->graphics.gs.lds_size = align(esgs_lds_size, 128) / 128;
1247 pipeline->graphics.gs.vgt_gs_onchip_cntl =
1248 S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1249 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1250 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1251 pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup =
1252 S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1253 pipeline->graphics.gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1254 assert(max_prims_per_subgroup <= max_out_prims);
1255 }
1256
1257 static void
1258 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1259 {
1260 struct radv_device *device = pipeline->device;
1261 unsigned num_se = device->physical_device->rad_info.max_se;
1262 unsigned wave_size = 64;
1263 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1264 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1265 unsigned alignment = 256 * num_se;
1266 /* The maximum size is 63.999 MB per SE. */
1267 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1268 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1269 struct ac_es_output_info *es_info;
1270 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1271 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1272 else
1273 es_info = radv_pipeline_has_tess(pipeline) ?
1274 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1275 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1276
1277 /* Calculate the minimum size. */
1278 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1279 wave_size, alignment);
1280 /* These are recommended sizes, not minimum sizes. */
1281 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1282 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1283 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1284 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1285
1286 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1287 esgs_ring_size = align(esgs_ring_size, alignment);
1288 gsvs_ring_size = align(gsvs_ring_size, alignment);
1289
1290 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1291 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1292
1293 pipeline->graphics.gs.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1294 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1295 }
1296
1297 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1298 unsigned *lds_size)
1299 {
1300 /* SPI barrier management bug:
1301 * Make sure we have at least 4k of LDS in use to avoid the bug.
1302 * It applies to workgroup sizes of more than one wavefront.
1303 */
1304 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1305 device->physical_device->rad_info.family == CHIP_KABINI ||
1306 device->physical_device->rad_info.family == CHIP_MULLINS)
1307 *lds_size = MAX2(*lds_size, 8);
1308 }
1309
1310 struct radv_shader_variant *
1311 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1312 {
1313 if (pipeline->shaders[MESA_SHADER_VERTEX])
1314 return pipeline->shaders[MESA_SHADER_VERTEX];
1315 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1316 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1317 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1318 }
1319
1320 static struct radv_shader_variant *
1321 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1322 {
1323 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1324 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1325 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1326 }
1327
1328 static void
1329 calculate_tess_state(struct radv_pipeline *pipeline,
1330 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1331 {
1332 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1333 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1334 unsigned num_tcs_patch_outputs;
1335 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1336 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1337 unsigned lds_size, hardware_lds_size;
1338 unsigned perpatch_output_offset;
1339 unsigned num_patches;
1340 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1341
1342 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1343 * are laid out in LDS. */
1344 num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
1345
1346 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1347 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1348 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1349
1350 /* Ensure that we only need one wave per SIMD so we don't need to check
1351 * resource usage. Also ensures that the number of tcs in and out
1352 * vertices per threadgroup are at most 256.
1353 */
1354 input_vertex_size = num_tcs_inputs * 16;
1355 output_vertex_size = num_tcs_outputs * 16;
1356
1357 input_patch_size = num_tcs_input_cp * input_vertex_size;
1358
1359 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1360 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1361 /* Ensure that we only need one wave per SIMD so we don't need to check
1362 * resource usage. Also ensures that the number of tcs in and out
1363 * vertices per threadgroup are at most 256.
1364 */
1365 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1366
1367 /* Make sure that the data fits in LDS. This assumes the shaders only
1368 * use LDS for the inputs and outputs.
1369 */
1370 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1371 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1372
1373 /* Make sure the output data fits in the offchip buffer */
1374 num_patches = MIN2(num_patches,
1375 (pipeline->device->tess_offchip_block_dw_size * 4) /
1376 output_patch_size);
1377
1378 /* Not necessary for correctness, but improves performance. The
1379 * specific value is taken from the proprietary driver.
1380 */
1381 num_patches = MIN2(num_patches, 40);
1382
1383 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1384 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1385 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1386 num_patches = MIN2(num_patches, one_wave);
1387 }
1388
1389 output_patch0_offset = input_patch_size * num_patches;
1390 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1391
1392 lds_size = output_patch0_offset + output_patch_size * num_patches;
1393
1394 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1395 assert(lds_size <= 65536);
1396 lds_size = align(lds_size, 512) / 512;
1397 } else {
1398 assert(lds_size <= 32768);
1399 lds_size = align(lds_size, 256) / 256;
1400 }
1401 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1402
1403 tess->lds_size = lds_size;
1404
1405 tess->tcs_in_layout = (input_patch_size / 4) |
1406 ((input_vertex_size / 4) << 13);
1407 tess->tcs_out_layout = (output_patch_size / 4) |
1408 ((output_vertex_size / 4) << 13);
1409 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1410 ((perpatch_output_offset / 16) << 16);
1411 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1412 (num_tcs_output_cp << 9) | num_patches;
1413
1414 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1415 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1416 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1417 tess->num_patches = num_patches;
1418 tess->num_tcs_input_cp = num_tcs_input_cp;
1419
1420 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1421 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1422
1423 switch (tes->info.tes.primitive_mode) {
1424 case GL_TRIANGLES:
1425 type = V_028B6C_TESS_TRIANGLE;
1426 break;
1427 case GL_QUADS:
1428 type = V_028B6C_TESS_QUAD;
1429 break;
1430 case GL_ISOLINES:
1431 type = V_028B6C_TESS_ISOLINE;
1432 break;
1433 }
1434
1435 switch (tes->info.tes.spacing) {
1436 case TESS_SPACING_EQUAL:
1437 partitioning = V_028B6C_PART_INTEGER;
1438 break;
1439 case TESS_SPACING_FRACTIONAL_ODD:
1440 partitioning = V_028B6C_PART_FRAC_ODD;
1441 break;
1442 case TESS_SPACING_FRACTIONAL_EVEN:
1443 partitioning = V_028B6C_PART_FRAC_EVEN;
1444 break;
1445 default:
1446 break;
1447 }
1448
1449 bool ccw = tes->info.tes.ccw;
1450 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1451 vk_find_struct_const(pCreateInfo->pTessellationState,
1452 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1453
1454 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1455 ccw = !ccw;
1456
1457 if (tes->info.tes.point_mode)
1458 topology = V_028B6C_OUTPUT_POINT;
1459 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1460 topology = V_028B6C_OUTPUT_LINE;
1461 else if (ccw)
1462 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1463 else
1464 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1465
1466 if (pipeline->device->has_distributed_tess) {
1467 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1468 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1469 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1470 else
1471 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1472 } else
1473 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1474
1475 tess->tf_param = S_028B6C_TYPE(type) |
1476 S_028B6C_PARTITIONING(partitioning) |
1477 S_028B6C_TOPOLOGY(topology) |
1478 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1479 }
1480
1481 static const struct radv_prim_vertex_count prim_size_table[] = {
1482 [V_008958_DI_PT_NONE] = {0, 0},
1483 [V_008958_DI_PT_POINTLIST] = {1, 1},
1484 [V_008958_DI_PT_LINELIST] = {2, 2},
1485 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1486 [V_008958_DI_PT_TRILIST] = {3, 3},
1487 [V_008958_DI_PT_TRIFAN] = {3, 1},
1488 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1489 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1490 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1491 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1492 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1493 [V_008958_DI_PT_RECTLIST] = {3, 3},
1494 [V_008958_DI_PT_LINELOOP] = {2, 1},
1495 [V_008958_DI_PT_POLYGON] = {3, 1},
1496 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1497 };
1498
1499 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs,
1500 enum chip_class chip_class)
1501 {
1502 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1503 unsigned cut_mode;
1504
1505 if (gs_max_vert_out <= 128) {
1506 cut_mode = V_028A40_GS_CUT_128;
1507 } else if (gs_max_vert_out <= 256) {
1508 cut_mode = V_028A40_GS_CUT_256;
1509 } else if (gs_max_vert_out <= 512) {
1510 cut_mode = V_028A40_GS_CUT_512;
1511 } else {
1512 assert(gs_max_vert_out <= 1024);
1513 cut_mode = V_028A40_GS_CUT_1024;
1514 }
1515
1516 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1517 S_028A40_CUT_MODE(cut_mode)|
1518 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
1519 S_028A40_GS_WRITE_OPTIMIZE(1) |
1520 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
1521 }
1522
1523 static struct ac_vs_output_info *get_vs_output_info(struct radv_pipeline *pipeline)
1524 {
1525 if (radv_pipeline_has_gs(pipeline))
1526 return &pipeline->gs_copy_shader->info.vs.outinfo;
1527 else if (radv_pipeline_has_tess(pipeline))
1528 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1529 else
1530 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1531 }
1532
1533 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1534 {
1535 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1536
1537 pipeline->graphics.vgt_primitiveid_en = false;
1538 pipeline->graphics.vgt_gs_mode = 0;
1539
1540 if (radv_pipeline_has_gs(pipeline)) {
1541 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY],
1542 pipeline->device->physical_device->rad_info.chip_class);
1543 } else if (outinfo->export_prim_id) {
1544 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1545 pipeline->graphics.vgt_primitiveid_en = true;
1546 }
1547 }
1548
1549 static void calculate_vs_outinfo(struct radv_pipeline *pipeline)
1550 {
1551 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1552
1553 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1554 clip_dist_mask = outinfo->clip_dist_mask;
1555 cull_dist_mask = outinfo->cull_dist_mask;
1556 total_mask = clip_dist_mask | cull_dist_mask;
1557
1558 bool misc_vec_ena = outinfo->writes_pointsize ||
1559 outinfo->writes_layer ||
1560 outinfo->writes_viewport_index;
1561 pipeline->graphics.vs.pa_cl_vs_out_cntl =
1562 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1563 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1564 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1565 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1566 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1567 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1568 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1569 cull_dist_mask << 8 |
1570 clip_dist_mask;
1571
1572 pipeline->graphics.vs.spi_shader_pos_format =
1573 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1574 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
1575 V_02870C_SPI_SHADER_4COMP :
1576 V_02870C_SPI_SHADER_NONE) |
1577 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
1578 V_02870C_SPI_SHADER_4COMP :
1579 V_02870C_SPI_SHADER_NONE) |
1580 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
1581 V_02870C_SPI_SHADER_4COMP :
1582 V_02870C_SPI_SHADER_NONE);
1583
1584 pipeline->graphics.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1);
1585 /* only emitted on pre-VI */
1586 pipeline->graphics.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(outinfo->writes_viewport_index);
1587 }
1588
1589 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1590 {
1591 uint32_t ps_input_cntl;
1592 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1593 ps_input_cntl = S_028644_OFFSET(offset);
1594 if (flat_shade)
1595 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1596 } else {
1597 /* The input is a DEFAULT_VAL constant. */
1598 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1599 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1600 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1601 ps_input_cntl = S_028644_OFFSET(0x20) |
1602 S_028644_DEFAULT_VAL(offset);
1603 }
1604 return ps_input_cntl;
1605 }
1606
1607 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1608 {
1609 struct radv_shader_variant *ps;
1610 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1611
1612 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1613
1614 unsigned ps_offset = 0;
1615
1616 if (ps->info.fs.prim_id_input) {
1617 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1618 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1619 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1620 ++ps_offset;
1621 }
1622 }
1623
1624 if (ps->info.fs.layer_input) {
1625 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1626 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
1627 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1628 else
1629 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
1630 ++ps_offset;
1631 }
1632
1633 if (ps->info.fs.has_pcoord) {
1634 unsigned val;
1635 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1636 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1637 ps_offset++;
1638 }
1639
1640 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1641 unsigned vs_offset;
1642 bool flat_shade;
1643 if (!(ps->info.fs.input_mask & (1u << i)))
1644 continue;
1645
1646 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1647 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1648 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1649 ++ps_offset;
1650 continue;
1651 }
1652
1653 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1654
1655 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1656 ++ps_offset;
1657 }
1658
1659 pipeline->graphics.ps_input_cntl_num = ps_offset;
1660 }
1661
1662 static void
1663 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1664 {
1665 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1666 int shader_count = 0;
1667
1668 if(shaders[MESA_SHADER_FRAGMENT]) {
1669 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1670 }
1671 if(shaders[MESA_SHADER_GEOMETRY]) {
1672 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1673 }
1674 if(shaders[MESA_SHADER_TESS_EVAL]) {
1675 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1676 }
1677 if(shaders[MESA_SHADER_TESS_CTRL]) {
1678 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1679 }
1680 if(shaders[MESA_SHADER_VERTEX]) {
1681 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1682 }
1683
1684 for (int i = 1; i < shader_count; ++i) {
1685 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1686 ordered_shaders[i - 1]);
1687
1688 nir_remove_dead_variables(ordered_shaders[i],
1689 nir_var_shader_out);
1690 nir_remove_dead_variables(ordered_shaders[i - 1],
1691 nir_var_shader_in);
1692
1693 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1694 ordered_shaders[i - 1]);
1695
1696 if (progress) {
1697 nir_lower_global_vars_to_local(ordered_shaders[i]);
1698 radv_optimize_nir(ordered_shaders[i]);
1699 nir_lower_global_vars_to_local(ordered_shaders[i - 1]);
1700 radv_optimize_nir(ordered_shaders[i - 1]);
1701 }
1702 }
1703 }
1704
1705
1706 static struct radv_pipeline_key
1707 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1708 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1709 bool has_view_index)
1710 {
1711 const VkPipelineVertexInputStateCreateInfo *input_state =
1712 pCreateInfo->pVertexInputState;
1713 struct radv_pipeline_key key;
1714 memset(&key, 0, sizeof(key));
1715
1716 key.has_multiview_view_index = has_view_index;
1717
1718 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1719 unsigned binding;
1720 binding = input_state->pVertexAttributeDescriptions[i].binding;
1721 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1722 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1723 }
1724
1725 if (pCreateInfo->pTessellationState)
1726 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1727
1728
1729 if (pCreateInfo->pMultisampleState &&
1730 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
1731 key.multisample = true;
1732
1733 key.col_format = pipeline->graphics.blend.spi_shader_col_format;
1734 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1735 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1736
1737 return key;
1738 }
1739
1740 static void
1741 radv_fill_shader_keys(struct ac_shader_variant_key *keys,
1742 const struct radv_pipeline_key *key,
1743 nir_shader **nir)
1744 {
1745 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1746
1747 if (nir[MESA_SHADER_TESS_CTRL]) {
1748 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1749 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1750 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1751
1752 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1753 }
1754
1755 if (nir[MESA_SHADER_GEOMETRY]) {
1756 if (nir[MESA_SHADER_TESS_CTRL])
1757 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1758 else
1759 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1760 }
1761
1762 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1763 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1764
1765 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1766 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1767 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1768 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1769 }
1770
1771 static
1772 void radv_create_shaders(struct radv_pipeline *pipeline,
1773 struct radv_device *device,
1774 struct radv_pipeline_cache *cache,
1775 struct radv_pipeline_key key,
1776 const VkPipelineShaderStageCreateInfo **pStages)
1777 {
1778 struct radv_shader_module fs_m = {0};
1779 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1780 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1781 void *codes[MESA_SHADER_STAGES] = {0};
1782 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1783 struct ac_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1784 unsigned char hash[20], gs_copy_hash[20];
1785
1786 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1787 if (pStages[i]) {
1788 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1789 if (modules[i]->nir)
1790 _mesa_sha1_compute(modules[i]->nir->info.name,
1791 strlen(modules[i]->nir->info.name),
1792 modules[i]->sha1);
1793 }
1794 }
1795
1796 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1797 memcpy(gs_copy_hash, hash, 20);
1798 gs_copy_hash[0] ^= 1;
1799
1800 if (modules[MESA_SHADER_GEOMETRY]) {
1801 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1802 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1803 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1804 }
1805
1806 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1807 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1808 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1809 if (pipeline->shaders[i])
1810 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1811 }
1812 return;
1813 }
1814
1815 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1816 nir_builder fs_b;
1817 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1818 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1819 fs_m.nir = fs_b.shader;
1820 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1821 }
1822
1823 /* Determine first and last stage. */
1824 unsigned first = MESA_SHADER_STAGES;
1825 unsigned last = 0;
1826 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1827 if (!pStages[i])
1828 continue;
1829 if (first == MESA_SHADER_STAGES)
1830 first = i;
1831 last = i;
1832 }
1833
1834 int prev = -1;
1835 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1836 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1837
1838 if (!modules[i])
1839 continue;
1840
1841 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1842 stage ? stage->pName : "main", i,
1843 stage ? stage->pSpecializationInfo : NULL);
1844 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1845
1846 /* We don't want to alter meta shaders IR directly so clone it
1847 * first.
1848 */
1849 if (nir[i]->info.name) {
1850 nir[i] = nir_shader_clone(NULL, nir[i]);
1851 }
1852
1853 if (first != last) {
1854 nir_variable_mode mask = 0;
1855
1856 if (i != first)
1857 mask = mask | nir_var_shader_in;
1858
1859 if (i != last)
1860 mask = mask | nir_var_shader_out;
1861
1862 nir_lower_io_to_scalar_early(nir[i], mask);
1863 radv_optimize_nir(nir[i]);
1864 }
1865
1866 if (prev != -1) {
1867 nir_compact_varyings(nir[prev], nir[i], true);
1868 }
1869 prev = i;
1870 }
1871
1872 if (nir[MESA_SHADER_TESS_CTRL]) {
1873 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1874 }
1875
1876 radv_link_shaders(pipeline, nir);
1877
1878 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1879 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1880 nir_print_shader(nir[i], stderr);
1881 }
1882
1883 radv_fill_shader_keys(keys, &key, nir);
1884
1885 if (nir[MESA_SHADER_FRAGMENT]) {
1886 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1887 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1888 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1889 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1890 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1891 }
1892
1893 /* TODO: These are no longer used as keys we should refactor this */
1894 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1895 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1896 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1897 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1898 }
1899
1900 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1901 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1902 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1903 struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1904 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1905 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1906 pipeline->layout,
1907 &key, &codes[MESA_SHADER_TESS_CTRL],
1908 &code_sizes[MESA_SHADER_TESS_CTRL]);
1909 }
1910 modules[MESA_SHADER_VERTEX] = NULL;
1911 }
1912
1913 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1914 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1915 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1916 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1917 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1918 pipeline->layout,
1919 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1920 &code_sizes[MESA_SHADER_GEOMETRY]);
1921 }
1922 modules[pre_stage] = NULL;
1923 }
1924
1925 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1926 if(modules[i] && !pipeline->shaders[i]) {
1927 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
1928 pipeline->layout,
1929 keys + i, &codes[i],
1930 &code_sizes[i]);
1931 }
1932 }
1933
1934 if(modules[MESA_SHADER_GEOMETRY]) {
1935 void *gs_copy_code = NULL;
1936 unsigned gs_copy_code_size = 0;
1937 if (!pipeline->gs_copy_shader) {
1938 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
1939 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
1940 &gs_copy_code_size,
1941 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
1942 }
1943
1944 if (pipeline->gs_copy_shader) {
1945 void *code[MESA_SHADER_STAGES] = {0};
1946 unsigned code_size[MESA_SHADER_STAGES] = {0};
1947 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1948
1949 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
1950 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
1951 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
1952
1953 radv_pipeline_cache_insert_shaders(device, cache,
1954 gs_copy_hash,
1955 variants,
1956 (const void**)code,
1957 code_size);
1958 }
1959 free(gs_copy_code);
1960 }
1961
1962 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
1963 (const void**)codes, code_sizes);
1964
1965 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1966 free(codes[i]);
1967 if (modules[i] && !pipeline->device->keep_shader_info)
1968 ralloc_free(nir[i]);
1969 }
1970
1971 if (fs_m.nir)
1972 ralloc_free(fs_m.nir);
1973 }
1974
1975 static uint32_t
1976 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
1977 gl_shader_stage stage, enum chip_class chip_class)
1978 {
1979 bool has_gs = radv_pipeline_has_gs(pipeline);
1980 bool has_tess = radv_pipeline_has_tess(pipeline);
1981 switch (stage) {
1982 case MESA_SHADER_FRAGMENT:
1983 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
1984 case MESA_SHADER_VERTEX:
1985 if (chip_class >= GFX9) {
1986 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1987 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1988 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1989 }
1990 if (has_tess)
1991 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
1992 else
1993 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
1994 case MESA_SHADER_GEOMETRY:
1995 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1996 R_00B230_SPI_SHADER_USER_DATA_GS_0;
1997 case MESA_SHADER_COMPUTE:
1998 return R_00B900_COMPUTE_USER_DATA_0;
1999 case MESA_SHADER_TESS_CTRL:
2000 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2001 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2002 case MESA_SHADER_TESS_EVAL:
2003 if (chip_class >= GFX9) {
2004 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2005 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2006 }
2007 if (has_gs)
2008 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2009 else
2010 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2011 default:
2012 unreachable("unknown shader");
2013 }
2014 }
2015
2016
2017 static VkResult
2018 radv_pipeline_init(struct radv_pipeline *pipeline,
2019 struct radv_device *device,
2020 struct radv_pipeline_cache *cache,
2021 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2022 const struct radv_graphics_pipeline_create_info *extra,
2023 const VkAllocationCallbacks *alloc)
2024 {
2025 VkResult result;
2026 bool has_view_index = false;
2027
2028 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2029 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2030 if (subpass->view_mask)
2031 has_view_index = true;
2032 if (alloc == NULL)
2033 alloc = &device->alloc;
2034
2035 pipeline->device = device;
2036 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2037
2038 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2039 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2040
2041 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2042 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2043 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2044 pStages[stage] = &pCreateInfo->pStages[i];
2045 }
2046
2047 radv_create_shaders(pipeline, device, cache,
2048 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, has_view_index),
2049 pStages);
2050
2051 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2052 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2053 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2054 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2055 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2056
2057 if (radv_pipeline_has_gs(pipeline)) {
2058 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2059 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2060 } else {
2061 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2062 }
2063 if (extra && extra->use_rectlist) {
2064 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2065 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2066 pipeline->graphics.can_use_guardband = true;
2067 }
2068 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2069 /* prim vertex count will need TESS changes */
2070 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2071
2072 /* Ensure that some export memory is always allocated, for two reasons:
2073 *
2074 * 1) Correctness: The hardware ignores the EXEC mask if no export
2075 * memory is allocated, so KILL and alpha test do not work correctly
2076 * without this.
2077 * 2) Performance: Every shader needs at least a NULL export, even when
2078 * it writes no color/depth output. The NULL export instruction
2079 * stalls without this setting.
2080 *
2081 * Don't add this to CB_SHADER_MASK.
2082 */
2083 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2084 if (!pipeline->graphics.blend.spi_shader_col_format) {
2085 if (!ps->info.fs.writes_z &&
2086 !ps->info.fs.writes_stencil &&
2087 !ps->info.fs.writes_sample_mask)
2088 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2089 }
2090
2091 unsigned z_order;
2092 pipeline->graphics.db_shader_control = 0;
2093 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2094 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2095 else
2096 z_order = V_02880C_LATE_Z;
2097
2098 pipeline->graphics.db_shader_control =
2099 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2100 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2101 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2102 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2103 S_02880C_Z_ORDER(z_order) |
2104 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2105 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2106 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2107
2108 if (pipeline->device->physical_device->has_rbplus)
2109 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
2110
2111 pipeline->graphics.shader_z_format =
2112 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2113 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2114 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2115 V_028710_SPI_SHADER_ZERO;
2116
2117 calculate_vgt_gs_mode(pipeline);
2118 calculate_vs_outinfo(pipeline);
2119 calculate_ps_inputs(pipeline);
2120
2121 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2122 if (pipeline->shaders[i]) {
2123 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2124 }
2125 }
2126
2127 uint32_t stages = 0;
2128 if (radv_pipeline_has_tess(pipeline)) {
2129 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2130 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2131
2132 if (radv_pipeline_has_gs(pipeline))
2133 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2134 S_028B54_GS_EN(1) |
2135 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2136 else
2137 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2138
2139 } else if (radv_pipeline_has_gs(pipeline))
2140 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2141 S_028B54_GS_EN(1) |
2142 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2143
2144 if (device->physical_device->rad_info.chip_class >= GFX9)
2145 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2146
2147 pipeline->graphics.vgt_shader_stages_en = stages;
2148
2149 if (radv_pipeline_has_gs(pipeline)) {
2150 calculate_gs_ring_sizes(pipeline);
2151 if (device->physical_device->rad_info.chip_class >= GFX9)
2152 calculate_gfx9_gs_info(pCreateInfo, pipeline);
2153 }
2154
2155 if (radv_pipeline_has_tess(pipeline)) {
2156 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2157 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2158 pipeline->graphics.prim_vertex_count.incr = 1;
2159 }
2160 calculate_tess_state(pipeline, pCreateInfo);
2161 }
2162
2163 if (radv_pipeline_has_tess(pipeline))
2164 pipeline->graphics.primgroup_size = pipeline->graphics.tess.num_patches;
2165 else if (radv_pipeline_has_gs(pipeline))
2166 pipeline->graphics.primgroup_size = 64;
2167 else
2168 pipeline->graphics.primgroup_size = 128; /* recommended without a GS */
2169
2170 pipeline->graphics.partial_es_wave = false;
2171 if (pipeline->device->has_distributed_tess) {
2172 if (radv_pipeline_has_gs(pipeline)) {
2173 if (device->physical_device->rad_info.chip_class <= VI)
2174 pipeline->graphics.partial_es_wave = true;
2175 }
2176 }
2177 /* GS requirement. */
2178 if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= pipeline->device->gs_table_depth - 3)
2179 pipeline->graphics.partial_es_wave = true;
2180
2181 pipeline->graphics.wd_switch_on_eop = false;
2182 if (device->physical_device->rad_info.chip_class >= CIK) {
2183 unsigned prim = pipeline->graphics.prim;
2184 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
2185 * 4 shader engines. Set 1 to pass the assertion below.
2186 * The other cases are hardware requirements. */
2187 if (device->physical_device->rad_info.max_se < 4 ||
2188 prim == V_008958_DI_PT_POLYGON ||
2189 prim == V_008958_DI_PT_LINELOOP ||
2190 prim == V_008958_DI_PT_TRIFAN ||
2191 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
2192 (pipeline->graphics.prim_restart_enable &&
2193 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
2194 (prim != V_008958_DI_PT_POINTLIST &&
2195 prim != V_008958_DI_PT_LINESTRIP &&
2196 prim != V_008958_DI_PT_TRISTRIP))))
2197 pipeline->graphics.wd_switch_on_eop = true;
2198 }
2199
2200 pipeline->graphics.ia_switch_on_eoi = false;
2201 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2202 pipeline->graphics.ia_switch_on_eoi = true;
2203 if (radv_pipeline_has_gs(pipeline) &&
2204 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.uses_prim_id)
2205 pipeline->graphics.ia_switch_on_eoi = true;
2206 if (radv_pipeline_has_tess(pipeline)) {
2207 /* SWITCH_ON_EOI must be set if PrimID is used. */
2208 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
2209 radv_get_tess_eval_shader(pipeline)->info.tes.uses_prim_id)
2210 pipeline->graphics.ia_switch_on_eoi = true;
2211 }
2212
2213 pipeline->graphics.partial_vs_wave = false;
2214 if (radv_pipeline_has_tess(pipeline)) {
2215 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
2216 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
2217 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
2218 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
2219 radv_pipeline_has_gs(pipeline))
2220 pipeline->graphics.partial_vs_wave = true;
2221 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
2222 if (device->has_distributed_tess) {
2223 if (radv_pipeline_has_gs(pipeline)) {
2224 if (device->physical_device->rad_info.family == CHIP_TONGA ||
2225 device->physical_device->rad_info.family == CHIP_FIJI ||
2226 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
2227 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
2228 device->physical_device->rad_info.family == CHIP_POLARIS12)
2229 pipeline->graphics.partial_vs_wave = true;
2230 } else {
2231 pipeline->graphics.partial_vs_wave = true;
2232 }
2233 }
2234 }
2235
2236 pipeline->graphics.base_ia_multi_vgt_param =
2237 S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
2238 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
2239 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
2240 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
2241 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
2242
2243 const VkPipelineVertexInputStateCreateInfo *vi_info =
2244 pCreateInfo->pVertexInputState;
2245 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
2246
2247 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2248 const VkVertexInputAttributeDescription *desc =
2249 &vi_info->pVertexAttributeDescriptions[i];
2250 unsigned loc = desc->location;
2251 const struct vk_format_description *format_desc;
2252 int first_non_void;
2253 uint32_t num_format, data_format;
2254 format_desc = vk_format_description(desc->format);
2255 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2256
2257 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2258 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2259
2260 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2261 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2262 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2263 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2264 S_008F0C_NUM_FORMAT(num_format) |
2265 S_008F0C_DATA_FORMAT(data_format);
2266 velems->format_size[loc] = format_desc->block.bits / 8;
2267 velems->offset[loc] = desc->offset;
2268 velems->binding[loc] = desc->binding;
2269 velems->count = MAX2(velems->count, loc + 1);
2270 }
2271
2272 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2273 const VkVertexInputBindingDescription *desc =
2274 &vi_info->pVertexBindingDescriptions[i];
2275
2276 pipeline->binding_stride[desc->binding] = desc->stride;
2277 }
2278
2279 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
2280 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
2281
2282 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2283 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2284 if (loc->sgpr_idx != -1) {
2285 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
2286 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2287 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
2288 pipeline->graphics.vtx_emit_num = 3;
2289 else
2290 pipeline->graphics.vtx_emit_num = 2;
2291 }
2292
2293 pipeline->graphics.vtx_reuse_depth = 30;
2294 if (radv_pipeline_has_tess(pipeline) &&
2295 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2296 pipeline->graphics.vtx_reuse_depth = 14;
2297 }
2298
2299 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2300 radv_dump_pipeline_stats(device, pipeline);
2301 }
2302
2303 result = radv_pipeline_scratch_init(device, pipeline);
2304 return result;
2305 }
2306
2307 VkResult
2308 radv_graphics_pipeline_create(
2309 VkDevice _device,
2310 VkPipelineCache _cache,
2311 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2312 const struct radv_graphics_pipeline_create_info *extra,
2313 const VkAllocationCallbacks *pAllocator,
2314 VkPipeline *pPipeline)
2315 {
2316 RADV_FROM_HANDLE(radv_device, device, _device);
2317 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2318 struct radv_pipeline *pipeline;
2319 VkResult result;
2320
2321 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2322 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2323 if (pipeline == NULL)
2324 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2325
2326 result = radv_pipeline_init(pipeline, device, cache,
2327 pCreateInfo, extra, pAllocator);
2328 if (result != VK_SUCCESS) {
2329 radv_pipeline_destroy(device, pipeline, pAllocator);
2330 return result;
2331 }
2332
2333 *pPipeline = radv_pipeline_to_handle(pipeline);
2334
2335 return VK_SUCCESS;
2336 }
2337
2338 VkResult radv_CreateGraphicsPipelines(
2339 VkDevice _device,
2340 VkPipelineCache pipelineCache,
2341 uint32_t count,
2342 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2343 const VkAllocationCallbacks* pAllocator,
2344 VkPipeline* pPipelines)
2345 {
2346 VkResult result = VK_SUCCESS;
2347 unsigned i = 0;
2348
2349 for (; i < count; i++) {
2350 VkResult r;
2351 r = radv_graphics_pipeline_create(_device,
2352 pipelineCache,
2353 &pCreateInfos[i],
2354 NULL, pAllocator, &pPipelines[i]);
2355 if (r != VK_SUCCESS) {
2356 result = r;
2357 pPipelines[i] = VK_NULL_HANDLE;
2358 }
2359 }
2360
2361 return result;
2362 }
2363
2364 static VkResult radv_compute_pipeline_create(
2365 VkDevice _device,
2366 VkPipelineCache _cache,
2367 const VkComputePipelineCreateInfo* pCreateInfo,
2368 const VkAllocationCallbacks* pAllocator,
2369 VkPipeline* pPipeline)
2370 {
2371 RADV_FROM_HANDLE(radv_device, device, _device);
2372 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2373 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2374 struct radv_pipeline *pipeline;
2375 VkResult result;
2376
2377 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2378 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2379 if (pipeline == NULL)
2380 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2381
2382 pipeline->device = device;
2383 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2384
2385 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
2386 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
2387
2388 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
2389 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2390 result = radv_pipeline_scratch_init(device, pipeline);
2391 if (result != VK_SUCCESS) {
2392 radv_pipeline_destroy(device, pipeline, pAllocator);
2393 return result;
2394 }
2395
2396 *pPipeline = radv_pipeline_to_handle(pipeline);
2397
2398 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2399 radv_dump_pipeline_stats(device, pipeline);
2400 }
2401 return VK_SUCCESS;
2402 }
2403 VkResult radv_CreateComputePipelines(
2404 VkDevice _device,
2405 VkPipelineCache pipelineCache,
2406 uint32_t count,
2407 const VkComputePipelineCreateInfo* pCreateInfos,
2408 const VkAllocationCallbacks* pAllocator,
2409 VkPipeline* pPipelines)
2410 {
2411 VkResult result = VK_SUCCESS;
2412
2413 unsigned i = 0;
2414 for (; i < count; i++) {
2415 VkResult r;
2416 r = radv_compute_pipeline_create(_device, pipelineCache,
2417 &pCreateInfos[i],
2418 pAllocator, &pPipelines[i]);
2419 if (r != VK_SUCCESS) {
2420 result = r;
2421 pPipelines[i] = VK_NULL_HANDLE;
2422 }
2423 }
2424
2425 return result;
2426 }