2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
51 radv_pipeline_destroy(struct radv_device
*device
,
52 struct radv_pipeline
*pipeline
,
53 const VkAllocationCallbacks
* allocator
)
55 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
56 if (pipeline
->shaders
[i
])
57 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
59 if (pipeline
->gs_copy_shader
)
60 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
62 vk_free2(&device
->alloc
, allocator
, pipeline
);
65 void radv_DestroyPipeline(
68 const VkAllocationCallbacks
* pAllocator
)
70 RADV_FROM_HANDLE(radv_device
, device
, _device
);
71 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
76 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
79 static void radv_dump_pipeline_stats(struct radv_device
*device
, struct radv_pipeline
*pipeline
)
83 for (i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
84 if (!pipeline
->shaders
[i
])
87 radv_shader_dump_stats(device
, pipeline
->shaders
[i
], i
, stderr
);
91 static uint32_t get_hash_flags(struct radv_device
*device
)
93 uint32_t hash_flags
= 0;
95 if (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
)
96 hash_flags
|= RADV_HASH_SHADER_UNSAFE_MATH
;
97 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
98 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
103 radv_pipeline_scratch_init(struct radv_device
*device
,
104 struct radv_pipeline
*pipeline
)
106 unsigned scratch_bytes_per_wave
= 0;
107 unsigned max_waves
= 0;
108 unsigned min_waves
= 1;
110 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
111 if (pipeline
->shaders
[i
]) {
112 unsigned max_stage_waves
= device
->scratch_waves
;
114 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
115 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
117 max_stage_waves
= MIN2(max_stage_waves
,
118 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
119 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
120 max_waves
= MAX2(max_waves
, max_stage_waves
);
124 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
125 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
126 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
127 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
128 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
131 if (scratch_bytes_per_wave
)
132 max_waves
= MIN2(max_waves
, 0xffffffffu
/ scratch_bytes_per_wave
);
134 if (scratch_bytes_per_wave
&& max_waves
< min_waves
) {
135 /* Not really true at this moment, but will be true on first
136 * execution. Avoid having hanging shaders. */
137 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
139 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
140 pipeline
->max_waves
= max_waves
;
144 static uint32_t si_translate_blend_function(VkBlendOp op
)
147 case VK_BLEND_OP_ADD
:
148 return V_028780_COMB_DST_PLUS_SRC
;
149 case VK_BLEND_OP_SUBTRACT
:
150 return V_028780_COMB_SRC_MINUS_DST
;
151 case VK_BLEND_OP_REVERSE_SUBTRACT
:
152 return V_028780_COMB_DST_MINUS_SRC
;
153 case VK_BLEND_OP_MIN
:
154 return V_028780_COMB_MIN_DST_SRC
;
155 case VK_BLEND_OP_MAX
:
156 return V_028780_COMB_MAX_DST_SRC
;
162 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
165 case VK_BLEND_FACTOR_ZERO
:
166 return V_028780_BLEND_ZERO
;
167 case VK_BLEND_FACTOR_ONE
:
168 return V_028780_BLEND_ONE
;
169 case VK_BLEND_FACTOR_SRC_COLOR
:
170 return V_028780_BLEND_SRC_COLOR
;
171 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
172 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
173 case VK_BLEND_FACTOR_DST_COLOR
:
174 return V_028780_BLEND_DST_COLOR
;
175 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
176 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
177 case VK_BLEND_FACTOR_SRC_ALPHA
:
178 return V_028780_BLEND_SRC_ALPHA
;
179 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
180 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
181 case VK_BLEND_FACTOR_DST_ALPHA
:
182 return V_028780_BLEND_DST_ALPHA
;
183 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
184 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
185 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
186 return V_028780_BLEND_CONSTANT_COLOR
;
187 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
188 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
189 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
190 return V_028780_BLEND_CONSTANT_ALPHA
;
191 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
192 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
193 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
194 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
195 case VK_BLEND_FACTOR_SRC1_COLOR
:
196 return V_028780_BLEND_SRC1_COLOR
;
197 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
198 return V_028780_BLEND_INV_SRC1_COLOR
;
199 case VK_BLEND_FACTOR_SRC1_ALPHA
:
200 return V_028780_BLEND_SRC1_ALPHA
;
201 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
202 return V_028780_BLEND_INV_SRC1_ALPHA
;
208 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
211 case VK_BLEND_OP_ADD
:
212 return V_028760_OPT_COMB_ADD
;
213 case VK_BLEND_OP_SUBTRACT
:
214 return V_028760_OPT_COMB_SUBTRACT
;
215 case VK_BLEND_OP_REVERSE_SUBTRACT
:
216 return V_028760_OPT_COMB_REVSUBTRACT
;
217 case VK_BLEND_OP_MIN
:
218 return V_028760_OPT_COMB_MIN
;
219 case VK_BLEND_OP_MAX
:
220 return V_028760_OPT_COMB_MAX
;
222 return V_028760_OPT_COMB_BLEND_DISABLED
;
226 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
229 case VK_BLEND_FACTOR_ZERO
:
230 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
231 case VK_BLEND_FACTOR_ONE
:
232 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
233 case VK_BLEND_FACTOR_SRC_COLOR
:
234 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
235 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
236 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
237 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
238 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
239 case VK_BLEND_FACTOR_SRC_ALPHA
:
240 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
241 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
242 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
243 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
244 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
245 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
247 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
252 * Get rid of DST in the blend factors by commuting the operands:
253 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
255 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
256 unsigned *dst_factor
, unsigned expected_dst
,
257 unsigned replacement_src
)
259 if (*src_factor
== expected_dst
&&
260 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
261 *src_factor
= VK_BLEND_FACTOR_ZERO
;
262 *dst_factor
= replacement_src
;
264 /* Commuting the operands requires reversing subtractions. */
265 if (*func
== VK_BLEND_OP_SUBTRACT
)
266 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
267 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
268 *func
= VK_BLEND_OP_SUBTRACT
;
272 static bool si_blend_factor_uses_dst(unsigned factor
)
274 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
275 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
276 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
277 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
278 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
281 static bool is_dual_src(VkBlendFactor factor
)
284 case VK_BLEND_FACTOR_SRC1_COLOR
:
285 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
286 case VK_BLEND_FACTOR_SRC1_ALPHA
:
287 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
294 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
296 bool blend_need_alpha
)
298 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
299 unsigned format
, ntype
, swap
;
301 /* Alpha is needed for alpha-to-coverage.
302 * Blending may be with or without alpha.
304 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
305 unsigned alpha
= 0; /* exports alpha, but may not support blending */
306 unsigned blend
= 0; /* supports blending, but may not export alpha */
307 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
309 format
= radv_translate_colorformat(vk_format
);
310 ntype
= radv_translate_color_numformat(vk_format
, desc
,
311 vk_format_get_first_non_void_channel(vk_format
));
312 swap
= radv_translate_colorswap(vk_format
, false);
314 /* Choose the SPI color formats. These are required values for Stoney/RB+.
315 * Other chips have multiple choices, though they are not necessarily better.
318 case V_028C70_COLOR_5_6_5
:
319 case V_028C70_COLOR_1_5_5_5
:
320 case V_028C70_COLOR_5_5_5_1
:
321 case V_028C70_COLOR_4_4_4_4
:
322 case V_028C70_COLOR_10_11_11
:
323 case V_028C70_COLOR_11_11_10
:
324 case V_028C70_COLOR_8
:
325 case V_028C70_COLOR_8_8
:
326 case V_028C70_COLOR_8_8_8_8
:
327 case V_028C70_COLOR_10_10_10_2
:
328 case V_028C70_COLOR_2_10_10_10
:
329 if (ntype
== V_028C70_NUMBER_UINT
)
330 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
331 else if (ntype
== V_028C70_NUMBER_SINT
)
332 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
334 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
337 case V_028C70_COLOR_16
:
338 case V_028C70_COLOR_16_16
:
339 case V_028C70_COLOR_16_16_16_16
:
340 if (ntype
== V_028C70_NUMBER_UNORM
||
341 ntype
== V_028C70_NUMBER_SNORM
) {
342 /* UNORM16 and SNORM16 don't support blending */
343 if (ntype
== V_028C70_NUMBER_UNORM
)
344 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
346 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
348 /* Use 32 bits per channel for blending. */
349 if (format
== V_028C70_COLOR_16
) {
350 if (swap
== V_028C70_SWAP_STD
) { /* R */
351 blend
= V_028714_SPI_SHADER_32_R
;
352 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
353 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
354 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
357 } else if (format
== V_028C70_COLOR_16_16
) {
358 if (swap
== V_028C70_SWAP_STD
) { /* RG */
359 blend
= V_028714_SPI_SHADER_32_GR
;
360 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
361 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
362 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
365 } else /* 16_16_16_16 */
366 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
367 } else if (ntype
== V_028C70_NUMBER_UINT
)
368 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
369 else if (ntype
== V_028C70_NUMBER_SINT
)
370 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
371 else if (ntype
== V_028C70_NUMBER_FLOAT
)
372 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
377 case V_028C70_COLOR_32
:
378 if (swap
== V_028C70_SWAP_STD
) { /* R */
379 blend
= normal
= V_028714_SPI_SHADER_32_R
;
380 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
381 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
382 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
387 case V_028C70_COLOR_32_32
:
388 if (swap
== V_028C70_SWAP_STD
) { /* RG */
389 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
390 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
391 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
392 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
397 case V_028C70_COLOR_32_32_32_32
:
398 case V_028C70_COLOR_8_24
:
399 case V_028C70_COLOR_24_8
:
400 case V_028C70_COLOR_X24_8_32_FLOAT
:
401 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
405 unreachable("unhandled blend format");
408 if (blend_enable
&& blend_need_alpha
)
410 else if(blend_need_alpha
)
412 else if(blend_enable
)
418 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
420 unsigned i
, cb_shader_mask
= 0;
422 for (i
= 0; i
< 8; i
++) {
423 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
424 case V_028714_SPI_SHADER_ZERO
:
426 case V_028714_SPI_SHADER_32_R
:
427 cb_shader_mask
|= 0x1 << (i
* 4);
429 case V_028714_SPI_SHADER_32_GR
:
430 cb_shader_mask
|= 0x3 << (i
* 4);
432 case V_028714_SPI_SHADER_32_AR
:
433 cb_shader_mask
|= 0x9 << (i
* 4);
435 case V_028714_SPI_SHADER_FP16_ABGR
:
436 case V_028714_SPI_SHADER_UNORM16_ABGR
:
437 case V_028714_SPI_SHADER_SNORM16_ABGR
:
438 case V_028714_SPI_SHADER_UINT16_ABGR
:
439 case V_028714_SPI_SHADER_SINT16_ABGR
:
440 case V_028714_SPI_SHADER_32_ABGR
:
441 cb_shader_mask
|= 0xf << (i
* 4);
447 return cb_shader_mask
;
451 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
452 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
453 uint32_t blend_enable
,
454 uint32_t blend_need_alpha
,
455 bool single_cb_enable
,
456 bool blend_mrt0_is_dual_src
)
458 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
459 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
460 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
461 unsigned col_format
= 0;
463 for (unsigned i
= 0; i
< (single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
466 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
467 cf
= V_028714_SPI_SHADER_ZERO
;
469 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
471 cf
= si_choose_spi_color_format(attachment
->format
,
472 blend_enable
& (1 << i
),
473 blend_need_alpha
& (1 << i
));
476 col_format
|= cf
<< (4 * i
);
479 blend
->cb_shader_mask
= si_get_cb_shader_mask(col_format
);
481 if (blend_mrt0_is_dual_src
)
482 col_format
|= (col_format
& 0xf) << 4;
483 blend
->spi_shader_col_format
= col_format
;
487 format_is_int8(VkFormat format
)
489 const struct vk_format_description
*desc
= vk_format_description(format
);
490 int channel
= vk_format_get_first_non_void_channel(format
);
492 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
493 desc
->channel
[channel
].size
== 8;
497 format_is_int10(VkFormat format
)
499 const struct vk_format_description
*desc
= vk_format_description(format
);
501 if (desc
->nr_channels
!= 4)
503 for (unsigned i
= 0; i
< 4; i
++) {
504 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
510 unsigned radv_format_meta_fs_key(VkFormat format
)
512 unsigned col_format
= si_choose_spi_color_format(format
, false, false) - 1;
513 bool is_int8
= format_is_int8(format
);
514 bool is_int10
= format_is_int10(format
);
516 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
520 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
521 unsigned *is_int8
, unsigned *is_int10
)
523 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
524 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
528 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
529 struct radv_render_pass_attachment
*attachment
;
531 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
534 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
536 if (format_is_int8(attachment
->format
))
538 if (format_is_int10(attachment
->format
))
544 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
545 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
546 const struct radv_graphics_pipeline_create_info
*extra
)
548 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
549 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
550 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
551 unsigned mode
= V_028808_CB_NORMAL
;
552 uint32_t blend_enable
= 0, blend_need_alpha
= 0;
553 bool blend_mrt0_is_dual_src
= false;
555 bool single_cb_enable
= false;
560 if (extra
&& extra
->custom_blend_mode
) {
561 single_cb_enable
= true;
562 mode
= extra
->custom_blend_mode
;
564 blend
->cb_color_control
= 0;
565 if (vkblend
->logicOpEnable
)
566 blend
->cb_color_control
|= S_028808_ROP3(vkblend
->logicOp
| (vkblend
->logicOp
<< 4));
568 blend
->cb_color_control
|= S_028808_ROP3(0xcc);
570 blend
->db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
571 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
572 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
573 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
575 if (vkms
&& vkms
->alphaToCoverageEnable
) {
576 blend
->db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
579 blend
->cb_target_mask
= 0;
580 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
581 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
582 unsigned blend_cntl
= 0;
583 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
584 VkBlendOp eqRGB
= att
->colorBlendOp
;
585 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
586 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
587 VkBlendOp eqA
= att
->alphaBlendOp
;
588 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
589 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
591 blend
->sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
593 if (!att
->colorWriteMask
)
596 blend
->cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
597 if (!att
->blendEnable
) {
598 blend
->cb_blend_control
[i
] = blend_cntl
;
602 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
604 blend_mrt0_is_dual_src
= true;
606 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
607 srcRGB
= VK_BLEND_FACTOR_ONE
;
608 dstRGB
= VK_BLEND_FACTOR_ONE
;
610 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
611 srcA
= VK_BLEND_FACTOR_ONE
;
612 dstA
= VK_BLEND_FACTOR_ONE
;
615 /* Blending optimizations for RB+.
616 * These transformations don't change the behavior.
618 * First, get rid of DST in the blend factors:
619 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
621 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
622 VK_BLEND_FACTOR_DST_COLOR
,
623 VK_BLEND_FACTOR_SRC_COLOR
);
625 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
626 VK_BLEND_FACTOR_DST_COLOR
,
627 VK_BLEND_FACTOR_SRC_COLOR
);
629 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
630 VK_BLEND_FACTOR_DST_ALPHA
,
631 VK_BLEND_FACTOR_SRC_ALPHA
);
633 /* Look up the ideal settings from tables. */
634 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
635 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
636 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
637 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
639 /* Handle interdependencies. */
640 if (si_blend_factor_uses_dst(srcRGB
))
641 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
642 if (si_blend_factor_uses_dst(srcA
))
643 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
645 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
646 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
647 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
648 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
649 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
651 /* Set the final value. */
652 blend
->sx_mrt_blend_opt
[i
] =
653 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
654 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
655 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
656 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
657 S_028760_ALPHA_DST_OPT(dstA_opt
) |
658 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
659 blend_cntl
|= S_028780_ENABLE(1);
661 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
662 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
663 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
664 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
665 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
666 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
667 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
668 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
670 blend
->cb_blend_control
[i
] = blend_cntl
;
672 blend_enable
|= 1 << i
;
674 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
675 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
676 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
677 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
678 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
679 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
680 blend_need_alpha
|= 1 << i
;
682 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
683 blend
->cb_blend_control
[i
] = 0;
684 blend
->sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
687 /* disable RB+ for now */
688 if (pipeline
->device
->physical_device
->has_rbplus
)
689 blend
->cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
691 if (blend
->cb_target_mask
)
692 blend
->cb_color_control
|= S_028808_MODE(mode
);
694 blend
->cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
696 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
,
697 blend_enable
, blend_need_alpha
, single_cb_enable
, blend_mrt0_is_dual_src
);
700 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
703 case VK_STENCIL_OP_KEEP
:
704 return V_02842C_STENCIL_KEEP
;
705 case VK_STENCIL_OP_ZERO
:
706 return V_02842C_STENCIL_ZERO
;
707 case VK_STENCIL_OP_REPLACE
:
708 return V_02842C_STENCIL_REPLACE_TEST
;
709 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
710 return V_02842C_STENCIL_ADD_CLAMP
;
711 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
712 return V_02842C_STENCIL_SUB_CLAMP
;
713 case VK_STENCIL_OP_INVERT
:
714 return V_02842C_STENCIL_INVERT
;
715 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
716 return V_02842C_STENCIL_ADD_WRAP
;
717 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
718 return V_02842C_STENCIL_SUB_WRAP
;
724 radv_pipeline_init_depth_stencil_state(struct radv_pipeline
*pipeline
,
725 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
726 const struct radv_graphics_pipeline_create_info
*extra
)
728 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
729 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
734 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
735 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
736 if (subpass
->depth_stencil_attachment
.attachment
== VK_ATTACHMENT_UNUSED
)
739 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
.attachment
;
740 bool has_depth_attachment
= vk_format_is_depth(attachment
->format
);
741 bool has_stencil_attachment
= vk_format_is_stencil(attachment
->format
);
743 if (has_depth_attachment
) {
744 ds
->db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
745 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
746 S_028800_ZFUNC(vkds
->depthCompareOp
) |
747 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
750 if (has_stencil_attachment
&& vkds
->stencilTestEnable
) {
751 ds
->db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
752 ds
->db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
753 ds
->db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
754 ds
->db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
755 ds
->db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
757 ds
->db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
758 ds
->db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
759 ds
->db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
760 ds
->db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
765 ds
->db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
766 ds
->db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
768 ds
->db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
769 ds
->db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
770 ds
->db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
771 ds
->db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
772 ds
->db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
776 static uint32_t si_translate_fill(VkPolygonMode func
)
779 case VK_POLYGON_MODE_FILL
:
780 return V_028814_X_DRAW_TRIANGLES
;
781 case VK_POLYGON_MODE_LINE
:
782 return V_028814_X_DRAW_LINES
;
783 case VK_POLYGON_MODE_POINT
:
784 return V_028814_X_DRAW_POINTS
;
787 return V_028814_X_DRAW_POINTS
;
791 radv_pipeline_init_raster_state(struct radv_pipeline
*pipeline
,
792 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
794 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
795 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
797 raster
->spi_interp_control
=
798 S_0286D4_FLAT_SHADE_ENA(1) |
799 S_0286D4_PNT_SPRITE_ENA(1) |
800 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
801 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
802 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
803 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
804 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
807 raster
->pa_cl_clip_cntl
= S_028810_PS_UCP_MODE(3) |
808 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
809 S_028810_ZCLIP_NEAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
810 S_028810_ZCLIP_FAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
811 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
812 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
814 raster
->pa_su_vtx_cntl
=
815 S_028BE4_PIX_CENTER(1) | // TODO verify
816 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
817 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
);
819 raster
->pa_su_sc_mode_cntl
=
820 S_028814_FACE(vkraster
->frontFace
) |
821 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
822 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
823 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
824 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
825 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
826 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
827 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
828 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0);
833 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
834 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
836 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
837 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
838 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
839 int ps_iter_samples
= 1;
840 uint32_t mask
= 0xffff;
843 ms
->num_samples
= vkms
->rasterizationSamples
;
847 if (vkms
&& vkms
->sampleShadingEnable
) {
848 ps_iter_samples
= ceil(vkms
->minSampleShading
* ms
->num_samples
);
849 } else if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.force_persample
) {
850 ps_iter_samples
= ms
->num_samples
;
853 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
854 ms
->pa_sc_aa_config
= 0;
855 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
856 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
857 ms
->pa_sc_mode_cntl_1
=
858 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
859 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
861 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
862 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
863 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
864 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
865 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
866 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
867 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
);
869 if (ms
->num_samples
> 1) {
870 unsigned log_samples
= util_logbase2(ms
->num_samples
);
871 unsigned log_ps_iter_samples
= util_logbase2(util_next_power_of_two(ps_iter_samples
));
872 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
873 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
874 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
875 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
876 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
877 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
878 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
879 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples
)) |
880 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
881 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
884 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
885 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
886 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
887 ms
->pa_sc_mode_cntl_1
|= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
888 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
891 if (vkms
&& vkms
->pSampleMask
) {
892 mask
= vkms
->pSampleMask
[0] & 0xffff;
895 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
896 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
900 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
903 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
904 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
905 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
906 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
907 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
909 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
910 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
911 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
912 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
913 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
914 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
917 unreachable("unhandled primitive type");
922 si_translate_prim(enum VkPrimitiveTopology topology
)
925 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
926 return V_008958_DI_PT_POINTLIST
;
927 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
928 return V_008958_DI_PT_LINELIST
;
929 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
930 return V_008958_DI_PT_LINESTRIP
;
931 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
932 return V_008958_DI_PT_TRILIST
;
933 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
934 return V_008958_DI_PT_TRISTRIP
;
935 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
936 return V_008958_DI_PT_TRIFAN
;
937 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
938 return V_008958_DI_PT_LINELIST_ADJ
;
939 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
940 return V_008958_DI_PT_LINESTRIP_ADJ
;
941 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
942 return V_008958_DI_PT_TRILIST_ADJ
;
943 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
944 return V_008958_DI_PT_TRISTRIP_ADJ
;
945 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
946 return V_008958_DI_PT_PATCH
;
954 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
957 case 0: /* GL_POINTS */
958 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
959 case 1: /* GL_LINES */
960 case 3: /* GL_LINE_STRIP */
961 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
962 case 0x8E7A: /* GL_ISOLINES */
963 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
965 case 4: /* GL_TRIANGLES */
966 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
967 case 5: /* GL_TRIANGLE_STRIP */
968 case 7: /* GL_QUADS */
969 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
977 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
980 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
981 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
982 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
983 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
984 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
985 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
986 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
987 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
988 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
989 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
990 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
991 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
992 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
993 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1000 static unsigned si_map_swizzle(unsigned swizzle
)
1004 return V_008F0C_SQ_SEL_Y
;
1006 return V_008F0C_SQ_SEL_Z
;
1008 return V_008F0C_SQ_SEL_W
;
1010 return V_008F0C_SQ_SEL_0
;
1012 return V_008F0C_SQ_SEL_1
;
1013 default: /* VK_SWIZZLE_X */
1014 return V_008F0C_SQ_SEL_X
;
1019 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1020 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1022 radv_cmd_dirty_mask_t states
= RADV_CMD_DIRTY_DYNAMIC_ALL
;
1023 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1024 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1026 pipeline
->dynamic_state
= default_dynamic_state
;
1028 if (pCreateInfo
->pDynamicState
) {
1029 /* Remove all of the states that are marked as dynamic */
1030 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1031 for (uint32_t s
= 0; s
< count
; s
++)
1032 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1035 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1037 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1039 * pViewportState is [...] NULL if the pipeline
1040 * has rasterization disabled.
1042 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1043 assert(pCreateInfo
->pViewportState
);
1045 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1046 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1047 typed_memcpy(dynamic
->viewport
.viewports
,
1048 pCreateInfo
->pViewportState
->pViewports
,
1049 pCreateInfo
->pViewportState
->viewportCount
);
1052 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1053 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1054 typed_memcpy(dynamic
->scissor
.scissors
,
1055 pCreateInfo
->pViewportState
->pScissors
,
1056 pCreateInfo
->pViewportState
->scissorCount
);
1060 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1061 assert(pCreateInfo
->pRasterizationState
);
1062 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1065 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1066 assert(pCreateInfo
->pRasterizationState
);
1067 dynamic
->depth_bias
.bias
=
1068 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1069 dynamic
->depth_bias
.clamp
=
1070 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1071 dynamic
->depth_bias
.slope
=
1072 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1075 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1077 * pColorBlendState is [...] NULL if the pipeline has rasterization
1078 * disabled or if the subpass of the render pass the pipeline is
1079 * created against does not use any color attachments.
1081 bool uses_color_att
= false;
1082 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1083 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1084 uses_color_att
= true;
1089 if (uses_color_att
&& states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
1090 assert(pCreateInfo
->pColorBlendState
);
1091 typed_memcpy(dynamic
->blend_constants
,
1092 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1095 /* If there is no depthstencil attachment, then don't read
1096 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1097 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1098 * no need to override the depthstencil defaults in
1099 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1101 * Section 9.2 of the Vulkan 1.0.15 spec says:
1103 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1104 * disabled or if the subpass of the render pass the pipeline is created
1105 * against does not use a depth/stencil attachment.
1107 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1108 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1109 assert(pCreateInfo
->pDepthStencilState
);
1111 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1112 dynamic
->depth_bounds
.min
=
1113 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1114 dynamic
->depth_bounds
.max
=
1115 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1118 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1119 dynamic
->stencil_compare_mask
.front
=
1120 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1121 dynamic
->stencil_compare_mask
.back
=
1122 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1125 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1126 dynamic
->stencil_write_mask
.front
=
1127 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1128 dynamic
->stencil_write_mask
.back
=
1129 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1132 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1133 dynamic
->stencil_reference
.front
=
1134 pCreateInfo
->pDepthStencilState
->front
.reference
;
1135 dynamic
->stencil_reference
.back
=
1136 pCreateInfo
->pDepthStencilState
->back
.reference
;
1140 pipeline
->dynamic_state_mask
= states
;
1143 static struct ac_shader_variant_key
1144 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo
*pCreateInfo
, bool as_es
, bool as_ls
)
1146 struct ac_shader_variant_key key
;
1147 const VkPipelineVertexInputStateCreateInfo
*input_state
=
1148 pCreateInfo
->pVertexInputState
;
1150 memset(&key
, 0, sizeof(key
));
1151 key
.vs
.instance_rate_inputs
= 0;
1152 key
.vs
.as_es
= as_es
;
1153 key
.vs
.as_ls
= as_ls
;
1155 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
1157 binding
= input_state
->pVertexAttributeDescriptions
[i
].binding
;
1158 if (input_state
->pVertexBindingDescriptions
[binding
].inputRate
)
1159 key
.vs
.instance_rate_inputs
|= 1u << input_state
->pVertexAttributeDescriptions
[i
].location
;
1165 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
)
1167 struct radv_device
*device
= pipeline
->device
;
1168 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1169 unsigned wave_size
= 64;
1170 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1171 unsigned gs_vertex_reuse
= 16 * num_se
; /* GS_VERTEX_REUSE register (per SE) */
1172 unsigned alignment
= 256 * num_se
;
1173 /* The maximum size is 63.999 MB per SE. */
1174 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1175 struct ac_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1176 struct ac_es_output_info
*es_info
= radv_pipeline_has_tess(pipeline
) ?
1177 &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.es_info
:
1178 &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.es_info
;
1180 /* Calculate the minimum size. */
1181 unsigned min_esgs_ring_size
= align(es_info
->esgs_itemsize
* gs_vertex_reuse
*
1182 wave_size
, alignment
);
1183 /* These are recommended sizes, not minimum sizes. */
1184 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1185 es_info
->esgs_itemsize
* gs_info
->gs
.vertices_in
;
1186 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1187 gs_info
->gs
.max_gsvs_emit_size
* 1; // no streams in VK (gs->max_gs_stream + 1);
1189 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1190 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1191 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1193 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1194 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1197 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1200 /* SPI barrier management bug:
1201 * Make sure we have at least 4k of LDS in use to avoid the bug.
1202 * It applies to workgroup sizes of more than one wavefront.
1204 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1205 device
->physical_device
->rad_info
.family
== CHIP_KABINI
||
1206 device
->physical_device
->rad_info
.family
== CHIP_MULLINS
)
1207 *lds_size
= MAX2(*lds_size
, 8);
1211 calculate_tess_state(struct radv_pipeline
*pipeline
,
1212 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1214 unsigned num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1215 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
1216 unsigned num_tcs_patch_outputs
;
1217 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
1218 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
1219 unsigned lds_size
, hardware_lds_size
;
1220 unsigned perpatch_output_offset
;
1221 unsigned num_patches
;
1222 struct radv_tessellation_state
*tess
= &pipeline
->graphics
.tess
;
1224 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1225 * are laid out in LDS. */
1226 num_tcs_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outputs_written
);
1228 num_tcs_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
); //tcs->outputs_written
1229 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1230 num_tcs_patch_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.patch_outputs_written
);
1232 /* Ensure that we only need one wave per SIMD so we don't need to check
1233 * resource usage. Also ensures that the number of tcs in and out
1234 * vertices per threadgroup are at most 256.
1236 input_vertex_size
= num_tcs_inputs
* 16;
1237 output_vertex_size
= num_tcs_outputs
* 16;
1239 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
1241 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
1242 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
1243 /* Ensure that we only need one wave per SIMD so we don't need to check
1244 * resource usage. Also ensures that the number of tcs in and out
1245 * vertices per threadgroup are at most 256.
1247 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
1249 /* Make sure that the data fits in LDS. This assumes the shaders only
1250 * use LDS for the inputs and outputs.
1252 hardware_lds_size
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
? 65536 : 32768;
1253 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
1255 /* Make sure the output data fits in the offchip buffer */
1256 num_patches
= MIN2(num_patches
,
1257 (pipeline
->device
->tess_offchip_block_dw_size
* 4) /
1260 /* Not necessary for correctness, but improves performance. The
1261 * specific value is taken from the proprietary driver.
1263 num_patches
= MIN2(num_patches
, 40);
1265 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1266 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== SI
) {
1267 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
1268 num_patches
= MIN2(num_patches
, one_wave
);
1271 output_patch0_offset
= input_patch_size
* num_patches
;
1272 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
1274 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
1276 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1277 assert(lds_size
<= 65536);
1278 lds_size
= align(lds_size
, 512) / 512;
1280 assert(lds_size
<= 32768);
1281 lds_size
= align(lds_size
, 256) / 256;
1283 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1285 tess
->lds_size
= lds_size
;
1287 tess
->tcs_in_layout
= (input_patch_size
/ 4) |
1288 ((input_vertex_size
/ 4) << 13);
1289 tess
->tcs_out_layout
= (output_patch_size
/ 4) |
1290 ((output_vertex_size
/ 4) << 13);
1291 tess
->tcs_out_offsets
= (output_patch0_offset
/ 16) |
1292 ((perpatch_output_offset
/ 16) << 16);
1293 tess
->offchip_layout
= (pervertex_output_patch_size
* num_patches
<< 16) |
1294 (num_tcs_output_cp
<< 9) | num_patches
;
1296 tess
->ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1297 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1298 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1299 tess
->num_patches
= num_patches
;
1300 tess
->num_tcs_input_cp
= num_tcs_input_cp
;
1302 struct radv_shader_variant
*tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1303 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1305 switch (tes
->info
.tes
.primitive_mode
) {
1307 type
= V_028B6C_TESS_TRIANGLE
;
1310 type
= V_028B6C_TESS_QUAD
;
1313 type
= V_028B6C_TESS_ISOLINE
;
1317 switch (tes
->info
.tes
.spacing
) {
1318 case TESS_SPACING_EQUAL
:
1319 partitioning
= V_028B6C_PART_INTEGER
;
1321 case TESS_SPACING_FRACTIONAL_ODD
:
1322 partitioning
= V_028B6C_PART_FRAC_ODD
;
1324 case TESS_SPACING_FRACTIONAL_EVEN
:
1325 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1331 bool ccw
= tes
->info
.tes
.ccw
;
1332 const VkPipelineTessellationDomainOriginStateCreateInfoKHR
*domain_origin_state
=
1333 vk_find_struct_const(pCreateInfo
->pTessellationState
,
1334 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR
);
1336 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR
)
1339 if (tes
->info
.tes
.point_mode
)
1340 topology
= V_028B6C_OUTPUT_POINT
;
1341 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
1342 topology
= V_028B6C_OUTPUT_LINE
;
1344 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
1346 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
1348 if (pipeline
->device
->has_distributed_tess
) {
1349 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
1350 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
1351 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
1353 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
1355 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
1357 tess
->tf_param
= S_028B6C_TYPE(type
) |
1358 S_028B6C_PARTITIONING(partitioning
) |
1359 S_028B6C_TOPOLOGY(topology
) |
1360 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
1363 static const struct radv_prim_vertex_count prim_size_table
[] = {
1364 [V_008958_DI_PT_NONE
] = {0, 0},
1365 [V_008958_DI_PT_POINTLIST
] = {1, 1},
1366 [V_008958_DI_PT_LINELIST
] = {2, 2},
1367 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
1368 [V_008958_DI_PT_TRILIST
] = {3, 3},
1369 [V_008958_DI_PT_TRIFAN
] = {3, 1},
1370 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
1371 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
1372 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
1373 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
1374 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
1375 [V_008958_DI_PT_RECTLIST
] = {3, 3},
1376 [V_008958_DI_PT_LINELOOP
] = {2, 1},
1377 [V_008958_DI_PT_POLYGON
] = {3, 1},
1378 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
1381 static uint32_t si_vgt_gs_mode(struct radv_shader_variant
*gs
)
1383 unsigned gs_max_vert_out
= gs
->info
.gs
.vertices_out
;
1386 if (gs_max_vert_out
<= 128) {
1387 cut_mode
= V_028A40_GS_CUT_128
;
1388 } else if (gs_max_vert_out
<= 256) {
1389 cut_mode
= V_028A40_GS_CUT_256
;
1390 } else if (gs_max_vert_out
<= 512) {
1391 cut_mode
= V_028A40_GS_CUT_512
;
1393 assert(gs_max_vert_out
<= 1024);
1394 cut_mode
= V_028A40_GS_CUT_1024
;
1397 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
1398 S_028A40_CUT_MODE(cut_mode
)|
1399 S_028A40_ES_WRITE_OPTIMIZE(1) |
1400 S_028A40_GS_WRITE_OPTIMIZE(1);
1403 static void calculate_vgt_gs_mode(struct radv_pipeline
*pipeline
)
1405 struct radv_shader_variant
*vs
;
1406 vs
= radv_pipeline_has_gs(pipeline
) ? pipeline
->gs_copy_shader
: (radv_pipeline_has_tess(pipeline
) ? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1408 struct ac_vs_output_info
*outinfo
= &vs
->info
.vs
.outinfo
;
1410 pipeline
->graphics
.vgt_primitiveid_en
= false;
1411 pipeline
->graphics
.vgt_gs_mode
= 0;
1413 if (radv_pipeline_has_gs(pipeline
)) {
1414 pipeline
->graphics
.vgt_gs_mode
= si_vgt_gs_mode(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
1415 } else if (outinfo
->export_prim_id
) {
1416 pipeline
->graphics
.vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
1417 pipeline
->graphics
.vgt_primitiveid_en
= true;
1421 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline
*pipeline
)
1423 struct radv_shader_variant
*vs
;
1424 vs
= radv_pipeline_has_gs(pipeline
) ? pipeline
->gs_copy_shader
: (radv_pipeline_has_tess(pipeline
) ? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1426 struct ac_vs_output_info
*outinfo
= &vs
->info
.vs
.outinfo
;
1428 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
1429 clip_dist_mask
= outinfo
->clip_dist_mask
;
1430 cull_dist_mask
= outinfo
->cull_dist_mask
;
1431 total_mask
= clip_dist_mask
| cull_dist_mask
;
1433 bool misc_vec_ena
= outinfo
->writes_pointsize
||
1434 outinfo
->writes_layer
||
1435 outinfo
->writes_viewport_index
;
1436 pipeline
->graphics
.pa_cl_vs_out_cntl
=
1437 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
1438 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
1439 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
1440 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
1441 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
1442 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
1443 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
1444 cull_dist_mask
<< 8 |
1449 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
)
1451 uint32_t ps_input_cntl
;
1452 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
1453 ps_input_cntl
= S_028644_OFFSET(offset
);
1455 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
1457 /* The input is a DEFAULT_VAL constant. */
1458 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
1459 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
1460 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
1461 ps_input_cntl
= S_028644_OFFSET(0x20) |
1462 S_028644_DEFAULT_VAL(offset
);
1464 return ps_input_cntl
;
1467 static void calculate_ps_inputs(struct radv_pipeline
*pipeline
)
1469 struct radv_shader_variant
*ps
, *vs
;
1470 struct ac_vs_output_info
*outinfo
;
1472 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1473 vs
= radv_pipeline_has_gs(pipeline
) ? pipeline
->gs_copy_shader
: (radv_pipeline_has_tess(pipeline
) ? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1475 outinfo
= &vs
->info
.vs
.outinfo
;
1477 unsigned ps_offset
= 0;
1479 if (ps
->info
.fs
.prim_id_input
) {
1480 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
1481 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
1482 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true);
1487 if (ps
->info
.fs
.layer_input
) {
1488 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
1489 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
1490 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true);
1492 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true);
1496 if (ps
->info
.fs
.has_pcoord
) {
1498 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1499 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = val
;
1503 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.fs
.input_mask
; ++i
) {
1506 if (!(ps
->info
.fs
.input_mask
& (1u << i
)))
1509 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
1510 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
1511 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
1516 flat_shade
= !!(ps
->info
.fs
.flat_shaded_mask
& (1u << ps_offset
));
1518 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
);
1522 pipeline
->graphics
.ps_input_cntl_num
= ps_offset
;
1526 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
1528 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
1529 int shader_count
= 0;
1531 if(shaders
[MESA_SHADER_FRAGMENT
]) {
1532 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
1534 if(shaders
[MESA_SHADER_GEOMETRY
]) {
1535 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
1537 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
1538 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
1540 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
1541 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
1543 if(shaders
[MESA_SHADER_VERTEX
]) {
1544 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
1547 for (int i
= 1; i
< shader_count
; ++i
) {
1548 nir_remove_dead_variables(ordered_shaders
[i
],
1549 nir_var_shader_out
);
1550 nir_remove_dead_variables(ordered_shaders
[i
- 1],
1553 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
1554 ordered_shaders
[i
- 1]);
1557 nir_lower_global_vars_to_local(ordered_shaders
[i
]);
1558 radv_optimize_nir(ordered_shaders
[i
]);
1559 nir_lower_global_vars_to_local(ordered_shaders
[i
- 1]);
1560 radv_optimize_nir(ordered_shaders
[i
- 1]);
1566 void radv_create_shaders(struct radv_pipeline
*pipeline
,
1567 struct radv_device
*device
,
1568 struct radv_pipeline_cache
*cache
,
1569 struct ac_shader_variant_key
*keys
,
1570 const VkPipelineShaderStageCreateInfo
**pStages
)
1572 struct radv_shader_module fs_m
= {0};
1573 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1574 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
1575 void *codes
[MESA_SHADER_STAGES
] = {0};
1576 unsigned code_sizes
[MESA_SHADER_STAGES
] = {0};
1577 unsigned char hash
[20], gs_copy_hash
[20];
1579 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
1581 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
1582 if (modules
[i
]->nir
)
1583 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
1584 strlen(modules
[i
]->nir
->info
.name
),
1589 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, keys
, get_hash_flags(device
));
1590 memcpy(gs_copy_hash
, hash
, 20);
1591 gs_copy_hash
[0] ^= 1;
1593 if (modules
[MESA_SHADER_GEOMETRY
]) {
1594 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
1595 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
);
1596 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
1599 if (radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
) &&
1600 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
))
1603 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
1605 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
1606 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
1607 fs_m
.nir
= fs_b
.shader
;
1608 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
1611 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
1612 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
1617 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
1618 stage
? stage
->pName
: "main", i
,
1619 stage
? stage
->pSpecializationInfo
: NULL
);
1620 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
1623 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1624 /* TODO: This is no longer used as a key we should refactor this */
1626 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
1628 nir_lower_tes_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
);
1631 radv_link_shaders(pipeline
, nir
);
1633 if (nir
[MESA_SHADER_FRAGMENT
]) {
1634 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
1635 radv_shader_variant_create(device
, modules
[MESA_SHADER_FRAGMENT
], nir
[MESA_SHADER_FRAGMENT
],
1636 pipeline
->layout
, keys
? keys
+ MESA_SHADER_FRAGMENT
: 0,
1637 &codes
[MESA_SHADER_FRAGMENT
], &code_sizes
[MESA_SHADER_FRAGMENT
]);
1639 /* TODO: These are no longer used as keys we should refactor this */
1641 keys
[MESA_SHADER_VERTEX
].vs
.export_prim_id
=
1642 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.fs
.prim_id_input
;
1643 keys
[MESA_SHADER_TESS_EVAL
].tes
.export_prim_id
=
1644 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.fs
.prim_id_input
;
1647 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT
);
1650 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
1651 if(modules
[i
] && !pipeline
->shaders
[i
]) {
1652 pipeline
->shaders
[i
] = radv_shader_variant_create(device
, modules
[i
], nir
[i
],
1654 keys
? keys
+ i
: 0, &codes
[i
],
1657 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
1661 if(modules
[MESA_SHADER_GEOMETRY
]) {
1662 void *gs_copy_code
= NULL
;
1663 unsigned gs_copy_code_size
= 0;
1664 if (!pipeline
->gs_copy_shader
) {
1665 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
1666 device
, nir
[MESA_SHADER_GEOMETRY
], &gs_copy_code
,
1668 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
1671 if (pipeline
->gs_copy_shader
) {
1672 void *code
[MESA_SHADER_STAGES
] = {0};
1673 unsigned code_size
[MESA_SHADER_STAGES
] = {0};
1674 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
1676 code
[MESA_SHADER_GEOMETRY
] = gs_copy_code
;
1677 code_size
[MESA_SHADER_GEOMETRY
] = gs_copy_code_size
;
1678 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
1680 radv_pipeline_cache_insert_shaders(device
, cache
,
1689 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
1690 (const void**)codes
, code_sizes
);
1692 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
1694 if (modules
[i
] && !modules
[i
]->nir
)
1695 ralloc_free(nir
[i
]);
1699 ralloc_free(fs_m
.nir
);
1703 radv_pipeline_init(struct radv_pipeline
*pipeline
,
1704 struct radv_device
*device
,
1705 struct radv_pipeline_cache
*cache
,
1706 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1707 const struct radv_graphics_pipeline_create_info
*extra
,
1708 const VkAllocationCallbacks
*alloc
)
1711 bool has_view_index
= false;
1713 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1714 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1715 if (subpass
->view_mask
)
1716 has_view_index
= true;
1718 alloc
= &device
->alloc
;
1720 pipeline
->device
= device
;
1721 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1723 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
1724 radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
1726 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1727 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1728 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1729 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1732 struct ac_shader_variant_key keys
[MESA_SHADER_STAGES
];
1733 memset(keys
, 0, sizeof(keys
));
1735 if (pStages
[MESA_SHADER_VERTEX
]) {
1738 if (pStages
[MESA_SHADER_TESS_CTRL
])
1740 else if (pStages
[MESA_SHADER_GEOMETRY
])
1743 keys
[MESA_SHADER_VERTEX
] = radv_compute_vs_key(pCreateInfo
, as_es
, as_ls
);
1744 keys
[MESA_SHADER_VERTEX
].has_multiview_view_index
= has_view_index
;
1747 if (pStages
[MESA_SHADER_TESS_EVAL
]) {
1748 keys
[MESA_SHADER_TESS_EVAL
].has_multiview_view_index
= has_view_index
;
1749 if (pStages
[MESA_SHADER_GEOMETRY
])
1750 keys
[MESA_SHADER_TESS_EVAL
].tes
.as_es
= true;
1753 if (pCreateInfo
->pTessellationState
)
1754 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1756 if (pStages
[MESA_SHADER_GEOMETRY
]) {
1757 keys
[MESA_SHADER_GEOMETRY
] = radv_compute_vs_key(pCreateInfo
, false, false);
1758 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
= has_view_index
;
1761 if (pCreateInfo
->pMultisampleState
&&
1762 pCreateInfo
->pMultisampleState
->rasterizationSamples
> 1)
1763 keys
[MESA_SHADER_FRAGMENT
].fs
.multisample
= true;
1765 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= pipeline
->graphics
.blend
.spi_shader_col_format
;
1766 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< VI
)
1767 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
, &keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
);
1769 radv_create_shaders(pipeline
, device
, cache
, keys
, pStages
);
1771 radv_pipeline_init_depth_stencil_state(pipeline
, pCreateInfo
, extra
);
1772 radv_pipeline_init_raster_state(pipeline
, pCreateInfo
);
1773 radv_pipeline_init_multisample_state(pipeline
, pCreateInfo
);
1774 pipeline
->graphics
.prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
1775 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
1777 if (radv_pipeline_has_gs(pipeline
)) {
1778 pipeline
->graphics
.gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
1779 pipeline
->graphics
.can_use_guardband
= pipeline
->graphics
.gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1781 pipeline
->graphics
.gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
1783 if (extra
&& extra
->use_rectlist
) {
1784 pipeline
->graphics
.prim
= V_008958_DI_PT_RECTLIST
;
1785 pipeline
->graphics
.gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1786 pipeline
->graphics
.can_use_guardband
= true;
1788 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
1789 /* prim vertex count will need TESS changes */
1790 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[pipeline
->graphics
.prim
];
1792 /* Ensure that some export memory is always allocated, for two reasons:
1794 * 1) Correctness: The hardware ignores the EXEC mask if no export
1795 * memory is allocated, so KILL and alpha test do not work correctly
1797 * 2) Performance: Every shader needs at least a NULL export, even when
1798 * it writes no color/depth output. The NULL export instruction
1799 * stalls without this setting.
1801 * Don't add this to CB_SHADER_MASK.
1803 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1804 if (!pipeline
->graphics
.blend
.spi_shader_col_format
) {
1805 if (!ps
->info
.fs
.writes_z
&&
1806 !ps
->info
.fs
.writes_stencil
&&
1807 !ps
->info
.fs
.writes_sample_mask
)
1808 pipeline
->graphics
.blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1812 pipeline
->graphics
.db_shader_control
= 0;
1813 if (ps
->info
.fs
.early_fragment_test
|| !ps
->info
.fs
.writes_memory
)
1814 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
1816 z_order
= V_02880C_LATE_Z
;
1818 pipeline
->graphics
.db_shader_control
=
1819 S_02880C_Z_EXPORT_ENABLE(ps
->info
.fs
.writes_z
) |
1820 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.fs
.writes_stencil
) |
1821 S_02880C_KILL_ENABLE(!!ps
->info
.fs
.can_discard
) |
1822 S_02880C_MASK_EXPORT_ENABLE(ps
->info
.fs
.writes_sample_mask
) |
1823 S_02880C_Z_ORDER(z_order
) |
1824 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.fs
.early_fragment_test
) |
1825 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.fs
.writes_memory
) |
1826 S_02880C_EXEC_ON_NOOP(ps
->info
.fs
.writes_memory
);
1828 if (pipeline
->device
->physical_device
->has_rbplus
)
1829 pipeline
->graphics
.db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1831 pipeline
->graphics
.shader_z_format
=
1832 ps
->info
.fs
.writes_sample_mask
? V_028710_SPI_SHADER_32_ABGR
:
1833 ps
->info
.fs
.writes_stencil
? V_028710_SPI_SHADER_32_GR
:
1834 ps
->info
.fs
.writes_z
? V_028710_SPI_SHADER_32_R
:
1835 V_028710_SPI_SHADER_ZERO
;
1837 calculate_vgt_gs_mode(pipeline
);
1838 calculate_pa_cl_vs_out_cntl(pipeline
);
1839 calculate_ps_inputs(pipeline
);
1841 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1842 if (pipeline
->shaders
[i
]) {
1843 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
1847 uint32_t stages
= 0;
1848 if (radv_pipeline_has_tess(pipeline
)) {
1849 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
1850 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
1852 if (radv_pipeline_has_gs(pipeline
))
1853 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
1855 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
1857 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
1859 } else if (radv_pipeline_has_gs(pipeline
))
1860 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
1862 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
1864 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1865 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
1867 pipeline
->graphics
.vgt_shader_stages_en
= stages
;
1869 if (radv_pipeline_has_gs(pipeline
))
1870 calculate_gs_ring_sizes(pipeline
);
1872 if (radv_pipeline_has_tess(pipeline
)) {
1873 if (pipeline
->graphics
.prim
== V_008958_DI_PT_PATCH
) {
1874 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1875 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
1877 calculate_tess_state(pipeline
, pCreateInfo
);
1880 if (radv_pipeline_has_tess(pipeline
))
1881 pipeline
->graphics
.primgroup_size
= pipeline
->graphics
.tess
.num_patches
;
1882 else if (radv_pipeline_has_gs(pipeline
))
1883 pipeline
->graphics
.primgroup_size
= 64;
1885 pipeline
->graphics
.primgroup_size
= 128; /* recommended without a GS */
1887 pipeline
->graphics
.partial_es_wave
= false;
1888 if (pipeline
->device
->has_distributed_tess
) {
1889 if (radv_pipeline_has_gs(pipeline
)) {
1890 if (device
->physical_device
->rad_info
.chip_class
<= VI
)
1891 pipeline
->graphics
.partial_es_wave
= true;
1894 /* GS requirement. */
1895 if (SI_GS_PER_ES
/ pipeline
->graphics
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
1896 pipeline
->graphics
.partial_es_wave
= true;
1898 pipeline
->graphics
.wd_switch_on_eop
= false;
1899 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1900 unsigned prim
= pipeline
->graphics
.prim
;
1901 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
1902 * 4 shader engines. Set 1 to pass the assertion below.
1903 * The other cases are hardware requirements. */
1904 if (device
->physical_device
->rad_info
.max_se
< 4 ||
1905 prim
== V_008958_DI_PT_POLYGON
||
1906 prim
== V_008958_DI_PT_LINELOOP
||
1907 prim
== V_008958_DI_PT_TRIFAN
||
1908 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
1909 (pipeline
->graphics
.prim_restart_enable
&&
1910 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
1911 (prim
!= V_008958_DI_PT_POINTLIST
&&
1912 prim
!= V_008958_DI_PT_LINESTRIP
&&
1913 prim
!= V_008958_DI_PT_TRISTRIP
))))
1914 pipeline
->graphics
.wd_switch_on_eop
= true;
1917 pipeline
->graphics
.ia_switch_on_eoi
= false;
1918 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.fs
.prim_id_input
)
1919 pipeline
->graphics
.ia_switch_on_eoi
= true;
1920 if (radv_pipeline_has_gs(pipeline
) &&
1921 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.uses_prim_id
)
1922 pipeline
->graphics
.ia_switch_on_eoi
= true;
1923 if (radv_pipeline_has_tess(pipeline
)) {
1924 /* SWITCH_ON_EOI must be set if PrimID is used. */
1925 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.uses_prim_id
||
1926 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.uses_prim_id
)
1927 pipeline
->graphics
.ia_switch_on_eoi
= true;
1930 pipeline
->graphics
.partial_vs_wave
= false;
1931 if (radv_pipeline_has_tess(pipeline
)) {
1932 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
1933 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
1934 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
1935 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
1936 radv_pipeline_has_gs(pipeline
))
1937 pipeline
->graphics
.partial_vs_wave
= true;
1938 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
1939 if (device
->has_distributed_tess
) {
1940 if (radv_pipeline_has_gs(pipeline
)) {
1941 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
1942 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
1943 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
1944 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
1945 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
)
1946 pipeline
->graphics
.partial_vs_wave
= true;
1948 pipeline
->graphics
.partial_vs_wave
= true;
1953 pipeline
->graphics
.base_ia_multi_vgt_param
=
1954 S_028AA8_PRIMGROUP_SIZE(pipeline
->graphics
.primgroup_size
- 1) |
1955 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
1956 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== VI
? 2 : 0) |
1957 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1958 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
1960 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1961 pCreateInfo
->pVertexInputState
;
1962 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
1964 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1965 const VkVertexInputAttributeDescription
*desc
=
1966 &vi_info
->pVertexAttributeDescriptions
[i
];
1967 unsigned loc
= desc
->location
;
1968 const struct vk_format_description
*format_desc
;
1970 uint32_t num_format
, data_format
;
1971 format_desc
= vk_format_description(desc
->format
);
1972 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
1974 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
1975 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
1977 velems
->rsrc_word3
[loc
] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc
->swizzle
[0])) |
1978 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc
->swizzle
[1])) |
1979 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc
->swizzle
[2])) |
1980 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc
->swizzle
[3])) |
1981 S_008F0C_NUM_FORMAT(num_format
) |
1982 S_008F0C_DATA_FORMAT(data_format
);
1983 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
1984 velems
->offset
[loc
] = desc
->offset
;
1985 velems
->binding
[loc
] = desc
->binding
;
1986 velems
->count
= MAX2(velems
->count
, loc
+ 1);
1989 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1990 const VkVertexInputBindingDescription
*desc
=
1991 &vi_info
->pVertexBindingDescriptions
[i
];
1993 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1996 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
1997 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
1998 if (loc
->sgpr_idx
!= -1) {
1999 pipeline
->graphics
.vtx_base_sgpr
= radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
2000 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
2001 if (pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.needs_draw_id
)
2002 pipeline
->graphics
.vtx_emit_num
= 3;
2004 pipeline
->graphics
.vtx_emit_num
= 2;
2007 pipeline
->graphics
.vtx_reuse_depth
= 30;
2008 if (radv_pipeline_has_tess(pipeline
) &&
2009 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
2010 pipeline
->graphics
.vtx_reuse_depth
= 14;
2013 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) {
2014 radv_dump_pipeline_stats(device
, pipeline
);
2017 result
= radv_pipeline_scratch_init(device
, pipeline
);
2022 radv_graphics_pipeline_create(
2024 VkPipelineCache _cache
,
2025 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2026 const struct radv_graphics_pipeline_create_info
*extra
,
2027 const VkAllocationCallbacks
*pAllocator
,
2028 VkPipeline
*pPipeline
)
2030 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2031 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
2032 struct radv_pipeline
*pipeline
;
2035 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
2036 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2037 if (pipeline
== NULL
)
2038 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2040 memset(pipeline
, 0, sizeof(*pipeline
));
2041 result
= radv_pipeline_init(pipeline
, device
, cache
,
2042 pCreateInfo
, extra
, pAllocator
);
2043 if (result
!= VK_SUCCESS
) {
2044 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
2048 *pPipeline
= radv_pipeline_to_handle(pipeline
);
2053 VkResult
radv_CreateGraphicsPipelines(
2055 VkPipelineCache pipelineCache
,
2057 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
2058 const VkAllocationCallbacks
* pAllocator
,
2059 VkPipeline
* pPipelines
)
2061 VkResult result
= VK_SUCCESS
;
2064 for (; i
< count
; i
++) {
2066 r
= radv_graphics_pipeline_create(_device
,
2069 NULL
, pAllocator
, &pPipelines
[i
]);
2070 if (r
!= VK_SUCCESS
) {
2072 pPipelines
[i
] = VK_NULL_HANDLE
;
2079 static VkResult
radv_compute_pipeline_create(
2081 VkPipelineCache _cache
,
2082 const VkComputePipelineCreateInfo
* pCreateInfo
,
2083 const VkAllocationCallbacks
* pAllocator
,
2084 VkPipeline
* pPipeline
)
2086 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2087 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
2088 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
2089 struct radv_pipeline
*pipeline
;
2092 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
2093 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2094 if (pipeline
== NULL
)
2095 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2097 memset(pipeline
, 0, sizeof(*pipeline
));
2098 pipeline
->device
= device
;
2099 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
2101 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
2102 radv_create_shaders(pipeline
, device
, cache
, NULL
, pStages
);
2105 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
2106 result
= radv_pipeline_scratch_init(device
, pipeline
);
2107 if (result
!= VK_SUCCESS
) {
2108 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
2112 *pPipeline
= radv_pipeline_to_handle(pipeline
);
2114 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) {
2115 radv_dump_pipeline_stats(device
, pipeline
);
2119 VkResult
radv_CreateComputePipelines(
2121 VkPipelineCache pipelineCache
,
2123 const VkComputePipelineCreateInfo
* pCreateInfos
,
2124 const VkAllocationCallbacks
* pAllocator
,
2125 VkPipeline
* pPipelines
)
2127 VkResult result
= VK_SUCCESS
;
2130 for (; i
< count
; i
++) {
2132 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
2134 pAllocator
, &pPipelines
[i
]);
2135 if (r
!= VK_SUCCESS
) {
2137 pPipelines
[i
] = VK_NULL_HANDLE
;