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0bb1cd9dff3fc02fe056be1605248cfe2372247d
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36 #include "vk_util.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40
41 #include "sid.h"
42 #include "gfx9d.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
49 #include "ac_shader_util.h"
50
51 static void
52 radv_pipeline_destroy(struct radv_device *device,
53 struct radv_pipeline *pipeline,
54 const VkAllocationCallbacks* allocator)
55 {
56 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
57 if (pipeline->shaders[i])
58 radv_shader_variant_destroy(device, pipeline->shaders[i]);
59
60 if (pipeline->gs_copy_shader)
61 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
62
63 vk_free2(&device->alloc, allocator, pipeline);
64 }
65
66 void radv_DestroyPipeline(
67 VkDevice _device,
68 VkPipeline _pipeline,
69 const VkAllocationCallbacks* pAllocator)
70 {
71 RADV_FROM_HANDLE(radv_device, device, _device);
72 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
73
74 if (!_pipeline)
75 return;
76
77 radv_pipeline_destroy(device, pipeline, pAllocator);
78 }
79
80 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
81 {
82 int i;
83
84 for (i = 0; i < MESA_SHADER_STAGES; i++) {
85 if (!pipeline->shaders[i])
86 continue;
87
88 radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr);
89 }
90 }
91
92 static uint32_t get_hash_flags(struct radv_device *device)
93 {
94 uint32_t hash_flags = 0;
95
96 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
97 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
98 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
99 hash_flags |= RADV_HASH_SHADER_SISCHED;
100 return hash_flags;
101 }
102
103 static VkResult
104 radv_pipeline_scratch_init(struct radv_device *device,
105 struct radv_pipeline *pipeline)
106 {
107 unsigned scratch_bytes_per_wave = 0;
108 unsigned max_waves = 0;
109 unsigned min_waves = 1;
110
111 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
112 if (pipeline->shaders[i]) {
113 unsigned max_stage_waves = device->scratch_waves;
114
115 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
116 pipeline->shaders[i]->config.scratch_bytes_per_wave);
117
118 max_stage_waves = MIN2(max_stage_waves,
119 4 * device->physical_device->rad_info.num_good_compute_units *
120 (256 / pipeline->shaders[i]->config.num_vgprs));
121 max_waves = MAX2(max_waves, max_stage_waves);
122 }
123 }
124
125 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
126 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
127 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
128 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
129 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
130 }
131
132 if (scratch_bytes_per_wave)
133 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
134
135 if (scratch_bytes_per_wave && max_waves < min_waves) {
136 /* Not really true at this moment, but will be true on first
137 * execution. Avoid having hanging shaders. */
138 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
139 }
140 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
141 pipeline->max_waves = max_waves;
142 return VK_SUCCESS;
143 }
144
145 static uint32_t si_translate_blend_function(VkBlendOp op)
146 {
147 switch (op) {
148 case VK_BLEND_OP_ADD:
149 return V_028780_COMB_DST_PLUS_SRC;
150 case VK_BLEND_OP_SUBTRACT:
151 return V_028780_COMB_SRC_MINUS_DST;
152 case VK_BLEND_OP_REVERSE_SUBTRACT:
153 return V_028780_COMB_DST_MINUS_SRC;
154 case VK_BLEND_OP_MIN:
155 return V_028780_COMB_MIN_DST_SRC;
156 case VK_BLEND_OP_MAX:
157 return V_028780_COMB_MAX_DST_SRC;
158 default:
159 return 0;
160 }
161 }
162
163 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
164 {
165 switch (factor) {
166 case VK_BLEND_FACTOR_ZERO:
167 return V_028780_BLEND_ZERO;
168 case VK_BLEND_FACTOR_ONE:
169 return V_028780_BLEND_ONE;
170 case VK_BLEND_FACTOR_SRC_COLOR:
171 return V_028780_BLEND_SRC_COLOR;
172 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
173 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
174 case VK_BLEND_FACTOR_DST_COLOR:
175 return V_028780_BLEND_DST_COLOR;
176 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
177 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
178 case VK_BLEND_FACTOR_SRC_ALPHA:
179 return V_028780_BLEND_SRC_ALPHA;
180 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
181 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
182 case VK_BLEND_FACTOR_DST_ALPHA:
183 return V_028780_BLEND_DST_ALPHA;
184 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
185 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
186 case VK_BLEND_FACTOR_CONSTANT_COLOR:
187 return V_028780_BLEND_CONSTANT_COLOR;
188 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
189 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
190 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
191 return V_028780_BLEND_CONSTANT_ALPHA;
192 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
193 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
194 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
195 return V_028780_BLEND_SRC_ALPHA_SATURATE;
196 case VK_BLEND_FACTOR_SRC1_COLOR:
197 return V_028780_BLEND_SRC1_COLOR;
198 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
199 return V_028780_BLEND_INV_SRC1_COLOR;
200 case VK_BLEND_FACTOR_SRC1_ALPHA:
201 return V_028780_BLEND_SRC1_ALPHA;
202 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
203 return V_028780_BLEND_INV_SRC1_ALPHA;
204 default:
205 return 0;
206 }
207 }
208
209 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
210 {
211 switch (op) {
212 case VK_BLEND_OP_ADD:
213 return V_028760_OPT_COMB_ADD;
214 case VK_BLEND_OP_SUBTRACT:
215 return V_028760_OPT_COMB_SUBTRACT;
216 case VK_BLEND_OP_REVERSE_SUBTRACT:
217 return V_028760_OPT_COMB_REVSUBTRACT;
218 case VK_BLEND_OP_MIN:
219 return V_028760_OPT_COMB_MIN;
220 case VK_BLEND_OP_MAX:
221 return V_028760_OPT_COMB_MAX;
222 default:
223 return V_028760_OPT_COMB_BLEND_DISABLED;
224 }
225 }
226
227 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
228 {
229 switch (factor) {
230 case VK_BLEND_FACTOR_ZERO:
231 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
232 case VK_BLEND_FACTOR_ONE:
233 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
234 case VK_BLEND_FACTOR_SRC_COLOR:
235 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
236 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
237 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
238 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
239 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
240 case VK_BLEND_FACTOR_SRC_ALPHA:
241 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
242 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
243 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
244 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
245 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
246 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
247 default:
248 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
249 }
250 }
251
252 /**
253 * Get rid of DST in the blend factors by commuting the operands:
254 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
255 */
256 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
257 unsigned *dst_factor, unsigned expected_dst,
258 unsigned replacement_src)
259 {
260 if (*src_factor == expected_dst &&
261 *dst_factor == VK_BLEND_FACTOR_ZERO) {
262 *src_factor = VK_BLEND_FACTOR_ZERO;
263 *dst_factor = replacement_src;
264
265 /* Commuting the operands requires reversing subtractions. */
266 if (*func == VK_BLEND_OP_SUBTRACT)
267 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
268 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
269 *func = VK_BLEND_OP_SUBTRACT;
270 }
271 }
272
273 static bool si_blend_factor_uses_dst(unsigned factor)
274 {
275 return factor == VK_BLEND_FACTOR_DST_COLOR ||
276 factor == VK_BLEND_FACTOR_DST_ALPHA ||
277 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
278 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
279 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
280 }
281
282 static bool is_dual_src(VkBlendFactor factor)
283 {
284 switch (factor) {
285 case VK_BLEND_FACTOR_SRC1_COLOR:
286 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
287 case VK_BLEND_FACTOR_SRC1_ALPHA:
288 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
289 return true;
290 default:
291 return false;
292 }
293 }
294
295 static unsigned si_choose_spi_color_format(VkFormat vk_format,
296 bool blend_enable,
297 bool blend_need_alpha)
298 {
299 const struct vk_format_description *desc = vk_format_description(vk_format);
300 unsigned format, ntype, swap;
301
302 /* Alpha is needed for alpha-to-coverage.
303 * Blending may be with or without alpha.
304 */
305 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
306 unsigned alpha = 0; /* exports alpha, but may not support blending */
307 unsigned blend = 0; /* supports blending, but may not export alpha */
308 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
309
310 format = radv_translate_colorformat(vk_format);
311 ntype = radv_translate_color_numformat(vk_format, desc,
312 vk_format_get_first_non_void_channel(vk_format));
313 swap = radv_translate_colorswap(vk_format, false);
314
315 /* Choose the SPI color formats. These are required values for Stoney/RB+.
316 * Other chips have multiple choices, though they are not necessarily better.
317 */
318 switch (format) {
319 case V_028C70_COLOR_5_6_5:
320 case V_028C70_COLOR_1_5_5_5:
321 case V_028C70_COLOR_5_5_5_1:
322 case V_028C70_COLOR_4_4_4_4:
323 case V_028C70_COLOR_10_11_11:
324 case V_028C70_COLOR_11_11_10:
325 case V_028C70_COLOR_8:
326 case V_028C70_COLOR_8_8:
327 case V_028C70_COLOR_8_8_8_8:
328 case V_028C70_COLOR_10_10_10_2:
329 case V_028C70_COLOR_2_10_10_10:
330 if (ntype == V_028C70_NUMBER_UINT)
331 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
332 else if (ntype == V_028C70_NUMBER_SINT)
333 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
334 else
335 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
336 break;
337
338 case V_028C70_COLOR_16:
339 case V_028C70_COLOR_16_16:
340 case V_028C70_COLOR_16_16_16_16:
341 if (ntype == V_028C70_NUMBER_UNORM ||
342 ntype == V_028C70_NUMBER_SNORM) {
343 /* UNORM16 and SNORM16 don't support blending */
344 if (ntype == V_028C70_NUMBER_UNORM)
345 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
346 else
347 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
348
349 /* Use 32 bits per channel for blending. */
350 if (format == V_028C70_COLOR_16) {
351 if (swap == V_028C70_SWAP_STD) { /* R */
352 blend = V_028714_SPI_SHADER_32_R;
353 blend_alpha = V_028714_SPI_SHADER_32_AR;
354 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
355 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
356 else
357 assert(0);
358 } else if (format == V_028C70_COLOR_16_16) {
359 if (swap == V_028C70_SWAP_STD) { /* RG */
360 blend = V_028714_SPI_SHADER_32_GR;
361 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
362 } else if (swap == V_028C70_SWAP_ALT) /* RA */
363 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
364 else
365 assert(0);
366 } else /* 16_16_16_16 */
367 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
368 } else if (ntype == V_028C70_NUMBER_UINT)
369 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
370 else if (ntype == V_028C70_NUMBER_SINT)
371 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
372 else if (ntype == V_028C70_NUMBER_FLOAT)
373 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
374 else
375 assert(0);
376 break;
377
378 case V_028C70_COLOR_32:
379 if (swap == V_028C70_SWAP_STD) { /* R */
380 blend = normal = V_028714_SPI_SHADER_32_R;
381 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
382 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
383 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
384 else
385 assert(0);
386 break;
387
388 case V_028C70_COLOR_32_32:
389 if (swap == V_028C70_SWAP_STD) { /* RG */
390 blend = normal = V_028714_SPI_SHADER_32_GR;
391 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
392 } else if (swap == V_028C70_SWAP_ALT) /* RA */
393 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
394 else
395 assert(0);
396 break;
397
398 case V_028C70_COLOR_32_32_32_32:
399 case V_028C70_COLOR_8_24:
400 case V_028C70_COLOR_24_8:
401 case V_028C70_COLOR_X24_8_32_FLOAT:
402 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
403 break;
404
405 default:
406 unreachable("unhandled blend format");
407 }
408
409 if (blend_enable && blend_need_alpha)
410 return blend_alpha;
411 else if(blend_need_alpha)
412 return alpha;
413 else if(blend_enable)
414 return blend;
415 else
416 return normal;
417 }
418
419 static void
420 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
421 const VkGraphicsPipelineCreateInfo *pCreateInfo,
422 uint32_t blend_enable,
423 uint32_t blend_need_alpha,
424 bool single_cb_enable,
425 bool blend_mrt0_is_dual_src)
426 {
427 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
428 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
429 struct radv_blend_state *blend = &pipeline->graphics.blend;
430 unsigned col_format = 0;
431
432 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
433 unsigned cf;
434
435 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
436 cf = V_028714_SPI_SHADER_ZERO;
437 } else {
438 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
439
440 cf = si_choose_spi_color_format(attachment->format,
441 blend_enable & (1 << i),
442 blend_need_alpha & (1 << i));
443 }
444
445 col_format |= cf << (4 * i);
446 }
447
448 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
449
450 if (blend_mrt0_is_dual_src)
451 col_format |= (col_format & 0xf) << 4;
452 blend->spi_shader_col_format = col_format;
453 }
454
455 static bool
456 format_is_int8(VkFormat format)
457 {
458 const struct vk_format_description *desc = vk_format_description(format);
459 int channel = vk_format_get_first_non_void_channel(format);
460
461 return channel >= 0 && desc->channel[channel].pure_integer &&
462 desc->channel[channel].size == 8;
463 }
464
465 static bool
466 format_is_int10(VkFormat format)
467 {
468 const struct vk_format_description *desc = vk_format_description(format);
469
470 if (desc->nr_channels != 4)
471 return false;
472 for (unsigned i = 0; i < 4; i++) {
473 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
474 return true;
475 }
476 return false;
477 }
478
479 unsigned radv_format_meta_fs_key(VkFormat format)
480 {
481 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
482 bool is_int8 = format_is_int8(format);
483 bool is_int10 = format_is_int10(format);
484
485 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
486 }
487
488 static void
489 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
490 unsigned *is_int8, unsigned *is_int10)
491 {
492 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
493 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
494 *is_int8 = 0;
495 *is_int10 = 0;
496
497 for (unsigned i = 0; i < subpass->color_count; ++i) {
498 struct radv_render_pass_attachment *attachment;
499
500 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
501 continue;
502
503 attachment = pass->attachments + subpass->color_attachments[i].attachment;
504
505 if (format_is_int8(attachment->format))
506 *is_int8 |= 1 << i;
507 if (format_is_int10(attachment->format))
508 *is_int10 |= 1 << i;
509 }
510 }
511
512 static void
513 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
514 const VkGraphicsPipelineCreateInfo *pCreateInfo,
515 const struct radv_graphics_pipeline_create_info *extra)
516 {
517 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
518 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
519 struct radv_blend_state *blend = &pipeline->graphics.blend;
520 unsigned mode = V_028808_CB_NORMAL;
521 uint32_t blend_enable = 0, blend_need_alpha = 0;
522 bool blend_mrt0_is_dual_src = false;
523 int i;
524 bool single_cb_enable = false;
525
526 if (!vkblend)
527 return;
528
529 if (extra && extra->custom_blend_mode) {
530 single_cb_enable = true;
531 mode = extra->custom_blend_mode;
532 }
533 blend->cb_color_control = 0;
534 if (vkblend->logicOpEnable)
535 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
536 else
537 blend->cb_color_control |= S_028808_ROP3(0xcc);
538
539 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
540 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
541 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
542 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
543
544 if (vkms && vkms->alphaToCoverageEnable) {
545 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
546 }
547
548 blend->cb_target_mask = 0;
549 for (i = 0; i < vkblend->attachmentCount; i++) {
550 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
551 unsigned blend_cntl = 0;
552 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
553 VkBlendOp eqRGB = att->colorBlendOp;
554 VkBlendFactor srcRGB = att->srcColorBlendFactor;
555 VkBlendFactor dstRGB = att->dstColorBlendFactor;
556 VkBlendOp eqA = att->alphaBlendOp;
557 VkBlendFactor srcA = att->srcAlphaBlendFactor;
558 VkBlendFactor dstA = att->dstAlphaBlendFactor;
559
560 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
561
562 if (!att->colorWriteMask)
563 continue;
564
565 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
566 if (!att->blendEnable) {
567 blend->cb_blend_control[i] = blend_cntl;
568 continue;
569 }
570
571 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
572 if (i == 0)
573 blend_mrt0_is_dual_src = true;
574
575 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
576 srcRGB = VK_BLEND_FACTOR_ONE;
577 dstRGB = VK_BLEND_FACTOR_ONE;
578 }
579 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
580 srcA = VK_BLEND_FACTOR_ONE;
581 dstA = VK_BLEND_FACTOR_ONE;
582 }
583
584 /* Blending optimizations for RB+.
585 * These transformations don't change the behavior.
586 *
587 * First, get rid of DST in the blend factors:
588 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
589 */
590 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
591 VK_BLEND_FACTOR_DST_COLOR,
592 VK_BLEND_FACTOR_SRC_COLOR);
593
594 si_blend_remove_dst(&eqA, &srcA, &dstA,
595 VK_BLEND_FACTOR_DST_COLOR,
596 VK_BLEND_FACTOR_SRC_COLOR);
597
598 si_blend_remove_dst(&eqA, &srcA, &dstA,
599 VK_BLEND_FACTOR_DST_ALPHA,
600 VK_BLEND_FACTOR_SRC_ALPHA);
601
602 /* Look up the ideal settings from tables. */
603 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
604 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
605 srcA_opt = si_translate_blend_opt_factor(srcA, true);
606 dstA_opt = si_translate_blend_opt_factor(dstA, true);
607
608 /* Handle interdependencies. */
609 if (si_blend_factor_uses_dst(srcRGB))
610 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
611 if (si_blend_factor_uses_dst(srcA))
612 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
613
614 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
615 (dstRGB == VK_BLEND_FACTOR_ZERO ||
616 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
617 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
618 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
619
620 /* Set the final value. */
621 blend->sx_mrt_blend_opt[i] =
622 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
623 S_028760_COLOR_DST_OPT(dstRGB_opt) |
624 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
625 S_028760_ALPHA_SRC_OPT(srcA_opt) |
626 S_028760_ALPHA_DST_OPT(dstA_opt) |
627 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
628 blend_cntl |= S_028780_ENABLE(1);
629
630 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
631 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
632 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
633 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
634 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
635 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
636 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
637 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
638 }
639 blend->cb_blend_control[i] = blend_cntl;
640
641 blend_enable |= 1 << i;
642
643 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
644 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
645 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
646 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
647 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
648 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
649 blend_need_alpha |= 1 << i;
650 }
651 for (i = vkblend->attachmentCount; i < 8; i++) {
652 blend->cb_blend_control[i] = 0;
653 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
654 }
655
656 /* disable RB+ for now */
657 if (pipeline->device->physical_device->has_rbplus)
658 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
659
660 if (blend->cb_target_mask)
661 blend->cb_color_control |= S_028808_MODE(mode);
662 else
663 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
664
665 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
666 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
667 }
668
669 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
670 {
671 switch (op) {
672 case VK_STENCIL_OP_KEEP:
673 return V_02842C_STENCIL_KEEP;
674 case VK_STENCIL_OP_ZERO:
675 return V_02842C_STENCIL_ZERO;
676 case VK_STENCIL_OP_REPLACE:
677 return V_02842C_STENCIL_REPLACE_TEST;
678 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
679 return V_02842C_STENCIL_ADD_CLAMP;
680 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
681 return V_02842C_STENCIL_SUB_CLAMP;
682 case VK_STENCIL_OP_INVERT:
683 return V_02842C_STENCIL_INVERT;
684 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
685 return V_02842C_STENCIL_ADD_WRAP;
686 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
687 return V_02842C_STENCIL_SUB_WRAP;
688 default:
689 return 0;
690 }
691 }
692 static void
693 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
694 const VkGraphicsPipelineCreateInfo *pCreateInfo,
695 const struct radv_graphics_pipeline_create_info *extra)
696 {
697 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
698 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
699
700 if (!vkds)
701 return;
702
703 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
704 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
705 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
706 return;
707
708 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
709 bool has_depth_attachment = vk_format_is_depth(attachment->format);
710 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
711
712 if (has_depth_attachment) {
713 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
714 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
715 S_028800_ZFUNC(vkds->depthCompareOp) |
716 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
717 }
718
719 if (has_stencil_attachment && vkds->stencilTestEnable) {
720 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
721 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
722 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
723 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
724 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
725
726 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
727 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
728 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
729 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
730 }
731
732 if (extra) {
733
734 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
735 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
736
737 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
738 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
739 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
740 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
741 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
742 }
743 }
744
745 static uint32_t si_translate_fill(VkPolygonMode func)
746 {
747 switch(func) {
748 case VK_POLYGON_MODE_FILL:
749 return V_028814_X_DRAW_TRIANGLES;
750 case VK_POLYGON_MODE_LINE:
751 return V_028814_X_DRAW_LINES;
752 case VK_POLYGON_MODE_POINT:
753 return V_028814_X_DRAW_POINTS;
754 default:
755 assert(0);
756 return V_028814_X_DRAW_POINTS;
757 }
758 }
759 static void
760 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
761 const VkGraphicsPipelineCreateInfo *pCreateInfo)
762 {
763 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
764 struct radv_raster_state *raster = &pipeline->graphics.raster;
765
766 raster->spi_interp_control =
767 S_0286D4_FLAT_SHADE_ENA(1) |
768 S_0286D4_PNT_SPRITE_ENA(1) |
769 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
770 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
771 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
772 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
773 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
774
775
776 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
777 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
778 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
779 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
780 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
781 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
782
783 raster->pa_su_vtx_cntl =
784 S_028BE4_PIX_CENTER(1) | // TODO verify
785 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
786 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
787
788 raster->pa_su_sc_mode_cntl =
789 S_028814_FACE(vkraster->frontFace) |
790 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
791 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
792 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
793 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
794 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
795 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
796 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
797 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
798
799 }
800
801 static void
802 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
803 const VkGraphicsPipelineCreateInfo *pCreateInfo)
804 {
805 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
806 struct radv_multisample_state *ms = &pipeline->graphics.ms;
807 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
808 int ps_iter_samples = 1;
809 uint32_t mask = 0xffff;
810
811 if (vkms)
812 ms->num_samples = vkms->rasterizationSamples;
813 else
814 ms->num_samples = 1;
815
816 if (vkms && vkms->sampleShadingEnable) {
817 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
818 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
819 ps_iter_samples = ms->num_samples;
820 }
821
822 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
823 ms->pa_sc_aa_config = 0;
824 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
825 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
826 ms->pa_sc_mode_cntl_1 =
827 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
828 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
829 /* always 1: */
830 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
831 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
832 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
833 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
834 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
835 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
836 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
837
838 if (ms->num_samples > 1) {
839 unsigned log_samples = util_logbase2(ms->num_samples);
840 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
841 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
842 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
843 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
844 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
845 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
846 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
847 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
848 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
849 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
850 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
851 }
852
853 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
854 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
855 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
856 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
857 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
858 }
859
860 if (vkms && vkms->pSampleMask) {
861 mask = vkms->pSampleMask[0] & 0xffff;
862 }
863
864 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
865 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
866 }
867
868 static bool
869 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
870 {
871 switch (topology) {
872 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
873 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
874 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
875 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
876 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
877 return false;
878 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
879 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
880 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
881 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
882 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
883 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
884 return true;
885 default:
886 unreachable("unhandled primitive type");
887 }
888 }
889
890 static uint32_t
891 si_translate_prim(enum VkPrimitiveTopology topology)
892 {
893 switch (topology) {
894 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
895 return V_008958_DI_PT_POINTLIST;
896 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
897 return V_008958_DI_PT_LINELIST;
898 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
899 return V_008958_DI_PT_LINESTRIP;
900 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
901 return V_008958_DI_PT_TRILIST;
902 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
903 return V_008958_DI_PT_TRISTRIP;
904 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
905 return V_008958_DI_PT_TRIFAN;
906 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
907 return V_008958_DI_PT_LINELIST_ADJ;
908 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
909 return V_008958_DI_PT_LINESTRIP_ADJ;
910 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
911 return V_008958_DI_PT_TRILIST_ADJ;
912 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
913 return V_008958_DI_PT_TRISTRIP_ADJ;
914 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
915 return V_008958_DI_PT_PATCH;
916 default:
917 assert(0);
918 return 0;
919 }
920 }
921
922 static uint32_t
923 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
924 {
925 switch (gl_prim) {
926 case 0: /* GL_POINTS */
927 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
928 case 1: /* GL_LINES */
929 case 3: /* GL_LINE_STRIP */
930 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
931 case 0x8E7A: /* GL_ISOLINES */
932 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
933
934 case 4: /* GL_TRIANGLES */
935 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
936 case 5: /* GL_TRIANGLE_STRIP */
937 case 7: /* GL_QUADS */
938 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
939 default:
940 assert(0);
941 return 0;
942 }
943 }
944
945 static uint32_t
946 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
947 {
948 switch (topology) {
949 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
950 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
951 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
952 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
953 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
954 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
955 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
956 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
957 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
958 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
959 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
960 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
961 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
962 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
963 default:
964 assert(0);
965 return 0;
966 }
967 }
968
969 static unsigned si_map_swizzle(unsigned swizzle)
970 {
971 switch (swizzle) {
972 case VK_SWIZZLE_Y:
973 return V_008F0C_SQ_SEL_Y;
974 case VK_SWIZZLE_Z:
975 return V_008F0C_SQ_SEL_Z;
976 case VK_SWIZZLE_W:
977 return V_008F0C_SQ_SEL_W;
978 case VK_SWIZZLE_0:
979 return V_008F0C_SQ_SEL_0;
980 case VK_SWIZZLE_1:
981 return V_008F0C_SQ_SEL_1;
982 default: /* VK_SWIZZLE_X */
983 return V_008F0C_SQ_SEL_X;
984 }
985 }
986
987
988 static unsigned radv_dynamic_state_mask(VkDynamicState state)
989 {
990 switch(state) {
991 case VK_DYNAMIC_STATE_VIEWPORT:
992 return RADV_DYNAMIC_VIEWPORT;
993 case VK_DYNAMIC_STATE_SCISSOR:
994 return RADV_DYNAMIC_SCISSOR;
995 case VK_DYNAMIC_STATE_LINE_WIDTH:
996 return RADV_DYNAMIC_LINE_WIDTH;
997 case VK_DYNAMIC_STATE_DEPTH_BIAS:
998 return RADV_DYNAMIC_DEPTH_BIAS;
999 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1000 return RADV_DYNAMIC_BLEND_CONSTANTS;
1001 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1002 return RADV_DYNAMIC_DEPTH_BOUNDS;
1003 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1004 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1005 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1006 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1007 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1008 return RADV_DYNAMIC_STENCIL_REFERENCE;
1009 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1010 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1011 default:
1012 unreachable("Unhandled dynamic state");
1013 }
1014 }
1015
1016 static void
1017 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1018 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1019 {
1020 uint32_t states = RADV_DYNAMIC_ALL;
1021 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1022 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1023
1024 pipeline->dynamic_state = default_dynamic_state;
1025
1026 if (pCreateInfo->pDynamicState) {
1027 /* Remove all of the states that are marked as dynamic */
1028 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1029 for (uint32_t s = 0; s < count; s++)
1030 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1031 }
1032
1033 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1034
1035 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1036 *
1037 * pViewportState is [...] NULL if the pipeline
1038 * has rasterization disabled.
1039 */
1040 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1041 assert(pCreateInfo->pViewportState);
1042
1043 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1044 if (states & RADV_DYNAMIC_VIEWPORT) {
1045 typed_memcpy(dynamic->viewport.viewports,
1046 pCreateInfo->pViewportState->pViewports,
1047 pCreateInfo->pViewportState->viewportCount);
1048 }
1049
1050 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1051 if (states & RADV_DYNAMIC_SCISSOR) {
1052 typed_memcpy(dynamic->scissor.scissors,
1053 pCreateInfo->pViewportState->pScissors,
1054 pCreateInfo->pViewportState->scissorCount);
1055 }
1056 }
1057
1058 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1059 assert(pCreateInfo->pRasterizationState);
1060 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1061 }
1062
1063 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1064 assert(pCreateInfo->pRasterizationState);
1065 dynamic->depth_bias.bias =
1066 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1067 dynamic->depth_bias.clamp =
1068 pCreateInfo->pRasterizationState->depthBiasClamp;
1069 dynamic->depth_bias.slope =
1070 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1071 }
1072
1073 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1074 *
1075 * pColorBlendState is [...] NULL if the pipeline has rasterization
1076 * disabled or if the subpass of the render pass the pipeline is
1077 * created against does not use any color attachments.
1078 */
1079 bool uses_color_att = false;
1080 for (unsigned i = 0; i < subpass->color_count; ++i) {
1081 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1082 uses_color_att = true;
1083 break;
1084 }
1085 }
1086
1087 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1088 assert(pCreateInfo->pColorBlendState);
1089 typed_memcpy(dynamic->blend_constants,
1090 pCreateInfo->pColorBlendState->blendConstants, 4);
1091 }
1092
1093 /* If there is no depthstencil attachment, then don't read
1094 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1095 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1096 * no need to override the depthstencil defaults in
1097 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1098 *
1099 * Section 9.2 of the Vulkan 1.0.15 spec says:
1100 *
1101 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1102 * disabled or if the subpass of the render pass the pipeline is created
1103 * against does not use a depth/stencil attachment.
1104 */
1105 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1106 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1107 assert(pCreateInfo->pDepthStencilState);
1108
1109 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1110 dynamic->depth_bounds.min =
1111 pCreateInfo->pDepthStencilState->minDepthBounds;
1112 dynamic->depth_bounds.max =
1113 pCreateInfo->pDepthStencilState->maxDepthBounds;
1114 }
1115
1116 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1117 dynamic->stencil_compare_mask.front =
1118 pCreateInfo->pDepthStencilState->front.compareMask;
1119 dynamic->stencil_compare_mask.back =
1120 pCreateInfo->pDepthStencilState->back.compareMask;
1121 }
1122
1123 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1124 dynamic->stencil_write_mask.front =
1125 pCreateInfo->pDepthStencilState->front.writeMask;
1126 dynamic->stencil_write_mask.back =
1127 pCreateInfo->pDepthStencilState->back.writeMask;
1128 }
1129
1130 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1131 dynamic->stencil_reference.front =
1132 pCreateInfo->pDepthStencilState->front.reference;
1133 dynamic->stencil_reference.back =
1134 pCreateInfo->pDepthStencilState->back.reference;
1135 }
1136 }
1137
1138 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1139 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1140 if (discard_rectangle_info) {
1141 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1142 typed_memcpy(dynamic->discard_rectangle.rectangles,
1143 discard_rectangle_info->pDiscardRectangles,
1144 discard_rectangle_info->discardRectangleCount);
1145
1146 unsigned mask = 0;
1147
1148 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
1149 /* Interpret i as a bitmask, and then set the bit in the mask if
1150 * that combination of rectangles in which the pixel is contained
1151 * should pass the cliprect test. */
1152 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
1153
1154 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
1155 !relevant_subset)
1156 continue;
1157
1158 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
1159 relevant_subset)
1160 continue;
1161
1162 mask |= 1u << i;
1163 }
1164 pipeline->graphics.pa_sc_cliprect_rule = mask;
1165 } else {
1166 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1167
1168 /* Allow from all rectangle combinations */
1169 pipeline->graphics.pa_sc_cliprect_rule = 0xffff;
1170 }
1171 pipeline->dynamic_state.mask = states;
1172 }
1173
1174 static void calculate_gfx9_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1175 struct radv_pipeline *pipeline)
1176 {
1177 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1178 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1179 &gs_info->tes.es_info : &gs_info->vs.es_info;
1180 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1181 bool uses_adjacency;
1182 switch(pCreateInfo->pInputAssemblyState->topology) {
1183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1184 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1185 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1186 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1187 uses_adjacency = true;
1188 break;
1189 default:
1190 uses_adjacency = false;
1191 break;
1192 }
1193
1194 /* All these are in dwords: */
1195 /* We can't allow using the whole LDS, because GS waves compete with
1196 * other shader stages for LDS space. */
1197 const unsigned max_lds_size = 8 * 1024;
1198 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1199 unsigned esgs_lds_size;
1200
1201 /* All these are per subgroup: */
1202 const unsigned max_out_prims = 32 * 1024;
1203 const unsigned max_es_verts = 255;
1204 const unsigned ideal_gs_prims = 64;
1205 unsigned max_gs_prims, gs_prims;
1206 unsigned min_es_verts, es_verts, worst_case_es_verts;
1207
1208 if (uses_adjacency || gs_num_invocations > 1)
1209 max_gs_prims = 127 / gs_num_invocations;
1210 else
1211 max_gs_prims = 255;
1212
1213 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1214 * Make sure we don't go over the maximum value.
1215 */
1216 if (gs_info->gs.vertices_out > 0) {
1217 max_gs_prims = MIN2(max_gs_prims,
1218 max_out_prims /
1219 (gs_info->gs.vertices_out * gs_num_invocations));
1220 }
1221 assert(max_gs_prims > 0);
1222
1223 /* If the primitive has adjacency, halve the number of vertices
1224 * that will be reused in multiple primitives.
1225 */
1226 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1227
1228 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1229 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1230
1231 /* Compute ESGS LDS size based on the worst case number of ES vertices
1232 * needed to create the target number of GS prims per subgroup.
1233 */
1234 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1235
1236 /* If total LDS usage is too big, refactor partitions based on ratio
1237 * of ESGS item sizes.
1238 */
1239 if (esgs_lds_size > max_lds_size) {
1240 /* Our target GS Prims Per Subgroup was too large. Calculate
1241 * the maximum number of GS Prims Per Subgroup that will fit
1242 * into LDS, capped by the maximum that the hardware can support.
1243 */
1244 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1245 max_gs_prims);
1246 assert(gs_prims > 0);
1247 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1248 max_es_verts);
1249
1250 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1251 assert(esgs_lds_size <= max_lds_size);
1252 }
1253
1254 /* Now calculate remaining ESGS information. */
1255 if (esgs_lds_size)
1256 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1257 else
1258 es_verts = max_es_verts;
1259
1260 /* Vertices for adjacency primitives are not always reused, so restore
1261 * it for ES_VERTS_PER_SUBGRP.
1262 */
1263 min_es_verts = gs_info->gs.vertices_in;
1264
1265 /* For normal primitives, the VGT only checks if they are past the ES
1266 * verts per subgroup after allocating a full GS primitive and if they
1267 * are, kick off a new subgroup. But if those additional ES verts are
1268 * unique (e.g. not reused) we need to make sure there is enough LDS
1269 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1270 */
1271 es_verts -= min_es_verts - 1;
1272
1273 uint32_t es_verts_per_subgroup = es_verts;
1274 uint32_t gs_prims_per_subgroup = gs_prims;
1275 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1276 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1277 pipeline->graphics.gs.lds_size = align(esgs_lds_size, 128) / 128;
1278 pipeline->graphics.gs.vgt_gs_onchip_cntl =
1279 S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1280 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1281 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1282 pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup =
1283 S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1284 pipeline->graphics.gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1285 assert(max_prims_per_subgroup <= max_out_prims);
1286 }
1287
1288 static void
1289 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1290 {
1291 struct radv_device *device = pipeline->device;
1292 unsigned num_se = device->physical_device->rad_info.max_se;
1293 unsigned wave_size = 64;
1294 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1295 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1296 unsigned alignment = 256 * num_se;
1297 /* The maximum size is 63.999 MB per SE. */
1298 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1299 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1300 struct ac_es_output_info *es_info;
1301 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1302 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1303 else
1304 es_info = radv_pipeline_has_tess(pipeline) ?
1305 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1306 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1307
1308 /* Calculate the minimum size. */
1309 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1310 wave_size, alignment);
1311 /* These are recommended sizes, not minimum sizes. */
1312 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1313 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1314 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1315 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1316
1317 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1318 esgs_ring_size = align(esgs_ring_size, alignment);
1319 gsvs_ring_size = align(gsvs_ring_size, alignment);
1320
1321 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1322 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1323
1324 pipeline->graphics.gs.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1325 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1326 }
1327
1328 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1329 unsigned *lds_size)
1330 {
1331 /* SPI barrier management bug:
1332 * Make sure we have at least 4k of LDS in use to avoid the bug.
1333 * It applies to workgroup sizes of more than one wavefront.
1334 */
1335 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1336 device->physical_device->rad_info.family == CHIP_KABINI ||
1337 device->physical_device->rad_info.family == CHIP_MULLINS)
1338 *lds_size = MAX2(*lds_size, 8);
1339 }
1340
1341 struct radv_shader_variant *
1342 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1343 {
1344 if (pipeline->shaders[MESA_SHADER_VERTEX])
1345 return pipeline->shaders[MESA_SHADER_VERTEX];
1346 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1347 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1348 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1349 }
1350
1351 static struct radv_shader_variant *
1352 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1353 {
1354 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1355 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1356 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1357 }
1358
1359 static void
1360 calculate_tess_state(struct radv_pipeline *pipeline,
1361 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1362 {
1363 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1364 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1365 unsigned num_tcs_patch_outputs;
1366 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1367 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1368 unsigned lds_size, hardware_lds_size;
1369 unsigned perpatch_output_offset;
1370 unsigned num_patches;
1371 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1372
1373 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1374 * are laid out in LDS. */
1375 num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
1376
1377 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1378 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1379 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1380
1381 /* Ensure that we only need one wave per SIMD so we don't need to check
1382 * resource usage. Also ensures that the number of tcs in and out
1383 * vertices per threadgroup are at most 256.
1384 */
1385 input_vertex_size = num_tcs_inputs * 16;
1386 output_vertex_size = num_tcs_outputs * 16;
1387
1388 input_patch_size = num_tcs_input_cp * input_vertex_size;
1389
1390 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1391 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1392 /* Ensure that we only need one wave per SIMD so we don't need to check
1393 * resource usage. Also ensures that the number of tcs in and out
1394 * vertices per threadgroup are at most 256.
1395 */
1396 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1397
1398 /* Make sure that the data fits in LDS. This assumes the shaders only
1399 * use LDS for the inputs and outputs.
1400 */
1401 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1402 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1403
1404 /* Make sure the output data fits in the offchip buffer */
1405 num_patches = MIN2(num_patches,
1406 (pipeline->device->tess_offchip_block_dw_size * 4) /
1407 output_patch_size);
1408
1409 /* Not necessary for correctness, but improves performance. The
1410 * specific value is taken from the proprietary driver.
1411 */
1412 num_patches = MIN2(num_patches, 40);
1413
1414 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1415 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1416 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1417 num_patches = MIN2(num_patches, one_wave);
1418 }
1419
1420 output_patch0_offset = input_patch_size * num_patches;
1421 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1422
1423 lds_size = output_patch0_offset + output_patch_size * num_patches;
1424
1425 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1426 assert(lds_size <= 65536);
1427 lds_size = align(lds_size, 512) / 512;
1428 } else {
1429 assert(lds_size <= 32768);
1430 lds_size = align(lds_size, 256) / 256;
1431 }
1432 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1433
1434 tess->lds_size = lds_size;
1435
1436 tess->tcs_in_layout = (input_patch_size / 4) |
1437 ((input_vertex_size / 4) << 13);
1438 tess->tcs_out_layout = (output_patch_size / 4) |
1439 ((output_vertex_size / 4) << 13);
1440 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1441 ((perpatch_output_offset / 16) << 16);
1442 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1443 (num_tcs_output_cp << 9) | num_patches;
1444
1445 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1446 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1447 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1448 tess->num_patches = num_patches;
1449 tess->num_tcs_input_cp = num_tcs_input_cp;
1450
1451 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1452 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1453
1454 switch (tes->info.tes.primitive_mode) {
1455 case GL_TRIANGLES:
1456 type = V_028B6C_TESS_TRIANGLE;
1457 break;
1458 case GL_QUADS:
1459 type = V_028B6C_TESS_QUAD;
1460 break;
1461 case GL_ISOLINES:
1462 type = V_028B6C_TESS_ISOLINE;
1463 break;
1464 }
1465
1466 switch (tes->info.tes.spacing) {
1467 case TESS_SPACING_EQUAL:
1468 partitioning = V_028B6C_PART_INTEGER;
1469 break;
1470 case TESS_SPACING_FRACTIONAL_ODD:
1471 partitioning = V_028B6C_PART_FRAC_ODD;
1472 break;
1473 case TESS_SPACING_FRACTIONAL_EVEN:
1474 partitioning = V_028B6C_PART_FRAC_EVEN;
1475 break;
1476 default:
1477 break;
1478 }
1479
1480 bool ccw = tes->info.tes.ccw;
1481 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1482 vk_find_struct_const(pCreateInfo->pTessellationState,
1483 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1484
1485 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1486 ccw = !ccw;
1487
1488 if (tes->info.tes.point_mode)
1489 topology = V_028B6C_OUTPUT_POINT;
1490 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1491 topology = V_028B6C_OUTPUT_LINE;
1492 else if (ccw)
1493 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1494 else
1495 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1496
1497 if (pipeline->device->has_distributed_tess) {
1498 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1499 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1500 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1501 else
1502 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1503 } else
1504 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1505
1506 tess->tf_param = S_028B6C_TYPE(type) |
1507 S_028B6C_PARTITIONING(partitioning) |
1508 S_028B6C_TOPOLOGY(topology) |
1509 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1510 }
1511
1512 static const struct radv_prim_vertex_count prim_size_table[] = {
1513 [V_008958_DI_PT_NONE] = {0, 0},
1514 [V_008958_DI_PT_POINTLIST] = {1, 1},
1515 [V_008958_DI_PT_LINELIST] = {2, 2},
1516 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1517 [V_008958_DI_PT_TRILIST] = {3, 3},
1518 [V_008958_DI_PT_TRIFAN] = {3, 1},
1519 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1520 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1521 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1522 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1523 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1524 [V_008958_DI_PT_RECTLIST] = {3, 3},
1525 [V_008958_DI_PT_LINELOOP] = {2, 1},
1526 [V_008958_DI_PT_POLYGON] = {3, 1},
1527 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1528 };
1529
1530 static struct ac_vs_output_info *get_vs_output_info(struct radv_pipeline *pipeline)
1531 {
1532 if (radv_pipeline_has_gs(pipeline))
1533 return &pipeline->gs_copy_shader->info.vs.outinfo;
1534 else if (radv_pipeline_has_tess(pipeline))
1535 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1536 else
1537 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1538 }
1539
1540 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1541 {
1542 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1543
1544 pipeline->graphics.vgt_primitiveid_en = false;
1545 pipeline->graphics.vgt_gs_mode = 0;
1546
1547 if (radv_pipeline_has_gs(pipeline)) {
1548 struct radv_shader_variant *gs =
1549 pipeline->shaders[MESA_SHADER_GEOMETRY];
1550
1551 pipeline->graphics.vgt_gs_mode =
1552 ac_vgt_gs_mode(gs->info.gs.vertices_out,
1553 pipeline->device->physical_device->rad_info.chip_class);
1554 } else if (outinfo->export_prim_id) {
1555 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1556 pipeline->graphics.vgt_primitiveid_en = true;
1557 }
1558 }
1559
1560 static void calculate_vs_outinfo(struct radv_pipeline *pipeline)
1561 {
1562 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1563
1564 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1565 clip_dist_mask = outinfo->clip_dist_mask;
1566 cull_dist_mask = outinfo->cull_dist_mask;
1567 total_mask = clip_dist_mask | cull_dist_mask;
1568
1569 bool misc_vec_ena = outinfo->writes_pointsize ||
1570 outinfo->writes_layer ||
1571 outinfo->writes_viewport_index;
1572 pipeline->graphics.vs.pa_cl_vs_out_cntl =
1573 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1574 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1575 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1576 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1577 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1578 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1579 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1580 cull_dist_mask << 8 |
1581 clip_dist_mask;
1582
1583 pipeline->graphics.vs.spi_shader_pos_format =
1584 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1585 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
1586 V_02870C_SPI_SHADER_4COMP :
1587 V_02870C_SPI_SHADER_NONE) |
1588 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
1589 V_02870C_SPI_SHADER_4COMP :
1590 V_02870C_SPI_SHADER_NONE) |
1591 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
1592 V_02870C_SPI_SHADER_4COMP :
1593 V_02870C_SPI_SHADER_NONE);
1594
1595 pipeline->graphics.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1);
1596 /* only emitted on pre-VI */
1597 pipeline->graphics.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(outinfo->writes_viewport_index);
1598 }
1599
1600 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1601 {
1602 uint32_t ps_input_cntl;
1603 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1604 ps_input_cntl = S_028644_OFFSET(offset);
1605 if (flat_shade)
1606 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1607 } else {
1608 /* The input is a DEFAULT_VAL constant. */
1609 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1610 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1611 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1612 ps_input_cntl = S_028644_OFFSET(0x20) |
1613 S_028644_DEFAULT_VAL(offset);
1614 }
1615 return ps_input_cntl;
1616 }
1617
1618 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1619 {
1620 struct radv_shader_variant *ps;
1621 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1622
1623 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1624
1625 unsigned ps_offset = 0;
1626
1627 if (ps->info.fs.prim_id_input) {
1628 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1629 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1630 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1631 ++ps_offset;
1632 }
1633 }
1634
1635 if (ps->info.fs.layer_input) {
1636 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1637 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
1638 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1639 else
1640 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
1641 ++ps_offset;
1642 }
1643
1644 if (ps->info.fs.has_pcoord) {
1645 unsigned val;
1646 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1647 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1648 ps_offset++;
1649 }
1650
1651 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1652 unsigned vs_offset;
1653 bool flat_shade;
1654 if (!(ps->info.fs.input_mask & (1u << i)))
1655 continue;
1656
1657 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1658 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1659 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1660 ++ps_offset;
1661 continue;
1662 }
1663
1664 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1665
1666 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1667 ++ps_offset;
1668 }
1669
1670 pipeline->graphics.ps_input_cntl_num = ps_offset;
1671 }
1672
1673 static void
1674 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1675 {
1676 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1677 int shader_count = 0;
1678
1679 if(shaders[MESA_SHADER_FRAGMENT]) {
1680 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1681 }
1682 if(shaders[MESA_SHADER_GEOMETRY]) {
1683 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1684 }
1685 if(shaders[MESA_SHADER_TESS_EVAL]) {
1686 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1687 }
1688 if(shaders[MESA_SHADER_TESS_CTRL]) {
1689 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1690 }
1691 if(shaders[MESA_SHADER_VERTEX]) {
1692 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1693 }
1694
1695 for (int i = 1; i < shader_count; ++i) {
1696 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1697 ordered_shaders[i - 1]);
1698
1699 nir_remove_dead_variables(ordered_shaders[i],
1700 nir_var_shader_out);
1701 nir_remove_dead_variables(ordered_shaders[i - 1],
1702 nir_var_shader_in);
1703
1704 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1705 ordered_shaders[i - 1]);
1706
1707 if (progress) {
1708 nir_lower_global_vars_to_local(ordered_shaders[i]);
1709 radv_optimize_nir(ordered_shaders[i]);
1710 nir_lower_global_vars_to_local(ordered_shaders[i - 1]);
1711 radv_optimize_nir(ordered_shaders[i - 1]);
1712 }
1713 }
1714 }
1715
1716
1717 static struct radv_pipeline_key
1718 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1719 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1720 bool has_view_index)
1721 {
1722 const VkPipelineVertexInputStateCreateInfo *input_state =
1723 pCreateInfo->pVertexInputState;
1724 struct radv_pipeline_key key;
1725 memset(&key, 0, sizeof(key));
1726
1727 key.has_multiview_view_index = has_view_index;
1728
1729 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1730 unsigned binding;
1731 binding = input_state->pVertexAttributeDescriptions[i].binding;
1732 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1733 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1734 }
1735
1736 if (pCreateInfo->pTessellationState)
1737 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1738
1739
1740 if (pCreateInfo->pMultisampleState &&
1741 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
1742 key.multisample = true;
1743
1744 key.col_format = pipeline->graphics.blend.spi_shader_col_format;
1745 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1746 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1747
1748 return key;
1749 }
1750
1751 static void
1752 radv_fill_shader_keys(struct ac_shader_variant_key *keys,
1753 const struct radv_pipeline_key *key,
1754 nir_shader **nir)
1755 {
1756 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1757
1758 if (nir[MESA_SHADER_TESS_CTRL]) {
1759 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1760 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1761 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1762 }
1763
1764 if (nir[MESA_SHADER_GEOMETRY]) {
1765 if (nir[MESA_SHADER_TESS_CTRL])
1766 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1767 else
1768 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1769 }
1770
1771 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1772 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1773
1774 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1775 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1776 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1777 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1778 }
1779
1780 static void
1781 merge_tess_info(struct shader_info *tes_info,
1782 const struct shader_info *tcs_info)
1783 {
1784 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1785 *
1786 * "PointMode. Controls generation of points rather than triangles
1787 * or lines. This functionality defaults to disabled, and is
1788 * enabled if either shader stage includes the execution mode.
1789 *
1790 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1791 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1792 * and OutputVertices, it says:
1793 *
1794 * "One mode must be set in at least one of the tessellation
1795 * shader stages."
1796 *
1797 * So, the fields can be set in either the TCS or TES, but they must
1798 * agree if set in both. Our backend looks at TES, so bitwise-or in
1799 * the values from the TCS.
1800 */
1801 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1802 tes_info->tess.tcs_vertices_out == 0 ||
1803 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1804 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1805
1806 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1807 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1808 tcs_info->tess.spacing == tes_info->tess.spacing);
1809 tes_info->tess.spacing |= tcs_info->tess.spacing;
1810
1811 assert(tcs_info->tess.primitive_mode == 0 ||
1812 tes_info->tess.primitive_mode == 0 ||
1813 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1814 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1815 tes_info->tess.ccw |= tcs_info->tess.ccw;
1816 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1817 }
1818
1819 static
1820 void radv_create_shaders(struct radv_pipeline *pipeline,
1821 struct radv_device *device,
1822 struct radv_pipeline_cache *cache,
1823 struct radv_pipeline_key key,
1824 const VkPipelineShaderStageCreateInfo **pStages)
1825 {
1826 struct radv_shader_module fs_m = {0};
1827 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1828 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1829 void *codes[MESA_SHADER_STAGES] = {0};
1830 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1831 struct ac_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1832 unsigned char hash[20], gs_copy_hash[20];
1833
1834 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1835 if (pStages[i]) {
1836 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1837 if (modules[i]->nir)
1838 _mesa_sha1_compute(modules[i]->nir->info.name,
1839 strlen(modules[i]->nir->info.name),
1840 modules[i]->sha1);
1841 }
1842 }
1843
1844 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1845 memcpy(gs_copy_hash, hash, 20);
1846 gs_copy_hash[0] ^= 1;
1847
1848 if (modules[MESA_SHADER_GEOMETRY]) {
1849 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1850 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1851 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1852 }
1853
1854 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1855 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1856 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1857 if (pipeline->shaders[i])
1858 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1859 }
1860 return;
1861 }
1862
1863 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1864 nir_builder fs_b;
1865 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1866 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1867 fs_m.nir = fs_b.shader;
1868 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1869 }
1870
1871 /* Determine first and last stage. */
1872 unsigned first = MESA_SHADER_STAGES;
1873 unsigned last = 0;
1874 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1875 if (!pStages[i])
1876 continue;
1877 if (first == MESA_SHADER_STAGES)
1878 first = i;
1879 last = i;
1880 }
1881
1882 int prev = -1;
1883 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1884 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1885
1886 if (!modules[i])
1887 continue;
1888
1889 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1890 stage ? stage->pName : "main", i,
1891 stage ? stage->pSpecializationInfo : NULL);
1892 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1893
1894 /* We don't want to alter meta shaders IR directly so clone it
1895 * first.
1896 */
1897 if (nir[i]->info.name) {
1898 nir[i] = nir_shader_clone(NULL, nir[i]);
1899 }
1900
1901 if (first != last) {
1902 nir_variable_mode mask = 0;
1903
1904 if (i != first)
1905 mask = mask | nir_var_shader_in;
1906
1907 if (i != last)
1908 mask = mask | nir_var_shader_out;
1909
1910 nir_lower_io_to_scalar_early(nir[i], mask);
1911 radv_optimize_nir(nir[i]);
1912 }
1913
1914 if (prev != -1) {
1915 nir_compact_varyings(nir[prev], nir[i], true);
1916 }
1917 prev = i;
1918 }
1919
1920 if (nir[MESA_SHADER_TESS_CTRL]) {
1921 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1922 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1923 }
1924
1925 radv_link_shaders(pipeline, nir);
1926
1927 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1928 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1929 nir_print_shader(nir[i], stderr);
1930 }
1931
1932 radv_fill_shader_keys(keys, &key, nir);
1933
1934 if (nir[MESA_SHADER_FRAGMENT]) {
1935 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1936 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1937 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1938 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1939 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1940 }
1941
1942 /* TODO: These are no longer used as keys we should refactor this */
1943 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1944 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1945 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1946 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1947 }
1948
1949 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1950 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1951 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1952 struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1953 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1954 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1955 pipeline->layout,
1956 &key, &codes[MESA_SHADER_TESS_CTRL],
1957 &code_sizes[MESA_SHADER_TESS_CTRL]);
1958 }
1959 modules[MESA_SHADER_VERTEX] = NULL;
1960 }
1961
1962 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1963 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1964 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1965 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1966 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1967 pipeline->layout,
1968 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1969 &code_sizes[MESA_SHADER_GEOMETRY]);
1970 }
1971 modules[pre_stage] = NULL;
1972 }
1973
1974 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1975 if(modules[i] && !pipeline->shaders[i]) {
1976 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
1977 pipeline->layout,
1978 keys + i, &codes[i],
1979 &code_sizes[i]);
1980 }
1981 }
1982
1983 if(modules[MESA_SHADER_GEOMETRY]) {
1984 void *gs_copy_code = NULL;
1985 unsigned gs_copy_code_size = 0;
1986 if (!pipeline->gs_copy_shader) {
1987 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
1988 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
1989 &gs_copy_code_size,
1990 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
1991 }
1992
1993 if (pipeline->gs_copy_shader) {
1994 void *code[MESA_SHADER_STAGES] = {0};
1995 unsigned code_size[MESA_SHADER_STAGES] = {0};
1996 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1997
1998 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
1999 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
2000 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2001
2002 radv_pipeline_cache_insert_shaders(device, cache,
2003 gs_copy_hash,
2004 variants,
2005 (const void**)code,
2006 code_size);
2007 }
2008 free(gs_copy_code);
2009 }
2010
2011 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2012 (const void**)codes, code_sizes);
2013
2014 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2015 free(codes[i]);
2016 if (modules[i] && !pipeline->device->keep_shader_info)
2017 ralloc_free(nir[i]);
2018 }
2019
2020 if (fs_m.nir)
2021 ralloc_free(fs_m.nir);
2022 }
2023
2024 static uint32_t
2025 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2026 gl_shader_stage stage, enum chip_class chip_class)
2027 {
2028 bool has_gs = radv_pipeline_has_gs(pipeline);
2029 bool has_tess = radv_pipeline_has_tess(pipeline);
2030 switch (stage) {
2031 case MESA_SHADER_FRAGMENT:
2032 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2033 case MESA_SHADER_VERTEX:
2034 if (chip_class >= GFX9) {
2035 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2036 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2037 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2038 }
2039 if (has_tess)
2040 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2041 else
2042 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
2043 case MESA_SHADER_GEOMETRY:
2044 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2045 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2046 case MESA_SHADER_COMPUTE:
2047 return R_00B900_COMPUTE_USER_DATA_0;
2048 case MESA_SHADER_TESS_CTRL:
2049 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2050 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2051 case MESA_SHADER_TESS_EVAL:
2052 if (chip_class >= GFX9) {
2053 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2054 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2055 }
2056 if (has_gs)
2057 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2058 else
2059 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2060 default:
2061 unreachable("unknown shader");
2062 }
2063 }
2064
2065 struct radv_bin_size_entry {
2066 unsigned bpp;
2067 VkExtent2D extent;
2068 };
2069
2070 static VkExtent2D
2071 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2072 {
2073 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2074 {
2075 /* One RB / SE */
2076 {
2077 /* One shader engine */
2078 { 0, {128, 128}},
2079 { 1, { 64, 128}},
2080 { 2, { 32, 128}},
2081 { 3, { 16, 128}},
2082 { 17, { 0, 0}},
2083 { UINT_MAX, { 0, 0}},
2084 },
2085 {
2086 /* Two shader engines */
2087 { 0, {128, 128}},
2088 { 2, { 64, 128}},
2089 { 3, { 32, 128}},
2090 { 5, { 16, 128}},
2091 { 17, { 0, 0}},
2092 { UINT_MAX, { 0, 0}},
2093 },
2094 {
2095 /* Four shader engines */
2096 { 0, {128, 128}},
2097 { 3, { 64, 128}},
2098 { 5, { 16, 128}},
2099 { 17, { 0, 0}},
2100 { UINT_MAX, { 0, 0}},
2101 },
2102 },
2103 {
2104 /* Two RB / SE */
2105 {
2106 /* One shader engine */
2107 { 0, {128, 128}},
2108 { 2, { 64, 128}},
2109 { 3, { 32, 128}},
2110 { 5, { 16, 128}},
2111 { 33, { 0, 0}},
2112 { UINT_MAX, { 0, 0}},
2113 },
2114 {
2115 /* Two shader engines */
2116 { 0, {128, 128}},
2117 { 3, { 64, 128}},
2118 { 5, { 32, 128}},
2119 { 9, { 16, 128}},
2120 { 33, { 0, 0}},
2121 { UINT_MAX, { 0, 0}},
2122 },
2123 {
2124 /* Four shader engines */
2125 { 0, {256, 256}},
2126 { 2, {128, 256}},
2127 { 3, {128, 128}},
2128 { 5, { 64, 128}},
2129 { 9, { 16, 128}},
2130 { 33, { 0, 0}},
2131 { UINT_MAX, { 0, 0}},
2132 },
2133 },
2134 {
2135 /* Four RB / SE */
2136 {
2137 /* One shader engine */
2138 { 0, {128, 256}},
2139 { 2, {128, 128}},
2140 { 3, { 64, 128}},
2141 { 5, { 32, 128}},
2142 { 9, { 16, 128}},
2143 { 33, { 0, 0}},
2144 { UINT_MAX, { 0, 0}},
2145 },
2146 {
2147 /* Two shader engines */
2148 { 0, {256, 256}},
2149 { 2, {128, 256}},
2150 { 3, {128, 128}},
2151 { 5, { 64, 128}},
2152 { 9, { 32, 128}},
2153 { 17, { 16, 128}},
2154 { 33, { 0, 0}},
2155 { UINT_MAX, { 0, 0}},
2156 },
2157 {
2158 /* Four shader engines */
2159 { 0, {256, 512}},
2160 { 2, {256, 256}},
2161 { 3, {128, 256}},
2162 { 5, {128, 128}},
2163 { 9, { 64, 128}},
2164 { 17, { 16, 128}},
2165 { 33, { 0, 0}},
2166 { UINT_MAX, { 0, 0}},
2167 },
2168 },
2169 };
2170 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2171 {
2172 // One RB / SE
2173 {
2174 // One shader engine
2175 { 0, {128, 256}},
2176 { 2, {128, 128}},
2177 { 4, { 64, 128}},
2178 { 7, { 32, 128}},
2179 { 13, { 16, 128}},
2180 { 49, { 0, 0}},
2181 { UINT_MAX, { 0, 0}},
2182 },
2183 {
2184 // Two shader engines
2185 { 0, {256, 256}},
2186 { 2, {128, 256}},
2187 { 4, {128, 128}},
2188 { 7, { 64, 128}},
2189 { 13, { 32, 128}},
2190 { 25, { 16, 128}},
2191 { 49, { 0, 0}},
2192 { UINT_MAX, { 0, 0}},
2193 },
2194 {
2195 // Four shader engines
2196 { 0, {256, 512}},
2197 { 2, {256, 256}},
2198 { 4, {128, 256}},
2199 { 7, {128, 128}},
2200 { 13, { 64, 128}},
2201 { 25, { 16, 128}},
2202 { 49, { 0, 0}},
2203 { UINT_MAX, { 0, 0}},
2204 },
2205 },
2206 {
2207 // Two RB / SE
2208 {
2209 // One shader engine
2210 { 0, {256, 256}},
2211 { 2, {128, 256}},
2212 { 4, {128, 128}},
2213 { 7, { 64, 128}},
2214 { 13, { 32, 128}},
2215 { 25, { 16, 128}},
2216 { 97, { 0, 0}},
2217 { UINT_MAX, { 0, 0}},
2218 },
2219 {
2220 // Two shader engines
2221 { 0, {256, 512}},
2222 { 2, {256, 256}},
2223 { 4, {128, 256}},
2224 { 7, {128, 128}},
2225 { 13, { 64, 128}},
2226 { 25, { 32, 128}},
2227 { 49, { 16, 128}},
2228 { 97, { 0, 0}},
2229 { UINT_MAX, { 0, 0}},
2230 },
2231 {
2232 // Four shader engines
2233 { 0, {512, 512}},
2234 { 2, {256, 512}},
2235 { 4, {256, 256}},
2236 { 7, {128, 256}},
2237 { 13, {128, 128}},
2238 { 25, { 64, 128}},
2239 { 49, { 16, 128}},
2240 { 97, { 0, 0}},
2241 { UINT_MAX, { 0, 0}},
2242 },
2243 },
2244 {
2245 // Four RB / SE
2246 {
2247 // One shader engine
2248 { 0, {256, 512}},
2249 { 2, {256, 256}},
2250 { 4, {128, 256}},
2251 { 7, {128, 128}},
2252 { 13, { 64, 128}},
2253 { 25, { 32, 128}},
2254 { 49, { 16, 128}},
2255 { UINT_MAX, { 0, 0}},
2256 },
2257 {
2258 // Two shader engines
2259 { 0, {512, 512}},
2260 { 2, {256, 512}},
2261 { 4, {256, 256}},
2262 { 7, {128, 256}},
2263 { 13, {128, 128}},
2264 { 25, { 64, 128}},
2265 { 49, { 32, 128}},
2266 { 97, { 16, 128}},
2267 { UINT_MAX, { 0, 0}},
2268 },
2269 {
2270 // Four shader engines
2271 { 0, {512, 512}},
2272 { 4, {256, 512}},
2273 { 7, {256, 256}},
2274 { 13, {128, 256}},
2275 { 25, {128, 128}},
2276 { 49, { 64, 128}},
2277 { 97, { 16, 128}},
2278 { UINT_MAX, { 0, 0}},
2279 },
2280 },
2281 };
2282
2283 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2284 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2285 VkExtent2D extent = {512, 512};
2286
2287 unsigned log_num_rb_per_se =
2288 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2289 pipeline->device->physical_device->rad_info.max_se);
2290 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2291
2292 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2293 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2294 unsigned effective_samples = total_samples;
2295 unsigned cb_target_mask = pipeline->graphics.blend.cb_target_mask;
2296 unsigned color_bytes_per_pixel = 0;
2297
2298 for (unsigned i = 0; i < subpass->color_count; i++) {
2299 if (!(cb_target_mask & (0xf << (i * 4))))
2300 continue;
2301
2302 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2303 continue;
2304
2305 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2306 color_bytes_per_pixel += vk_format_get_blocksize(format);
2307 }
2308
2309 /* MSAA images typically don't use all samples all the time. */
2310 if (effective_samples >= 2 && ps_iter_samples <= 1)
2311 effective_samples = 2;
2312 color_bytes_per_pixel *= effective_samples;
2313
2314 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2315 while(color_entry->bpp <= color_bytes_per_pixel)
2316 ++color_entry;
2317
2318 extent = color_entry->extent;
2319
2320 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2321 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2322
2323 /* Coefficients taken from AMDVLK */
2324 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2325 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2326 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2327
2328 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2329 while(ds_entry->bpp <= ds_bytes_per_pixel)
2330 ++ds_entry;
2331
2332 extent.width = MIN2(extent.width, ds_entry->extent.width);
2333 extent.height = MIN2(extent.height, ds_entry->extent.height);
2334 }
2335
2336 return extent;
2337 }
2338
2339 static void
2340 radv_compute_binning_state(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2341 {
2342 pipeline->graphics.bin.pa_sc_binner_cntl_0 =
2343 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2344 S_028C44_DISABLE_START_OF_PRIM(1);
2345 pipeline->graphics.bin.db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2346
2347 if (!pipeline->device->pbb_allowed)
2348 return;
2349
2350 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2351 if (!bin_size.width || !bin_size.height)
2352 return;
2353
2354 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2355 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2356 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2357
2358 switch (pipeline->device->physical_device->rad_info.family) {
2359 case CHIP_VEGA10:
2360 context_states_per_bin = 1;
2361 persistent_states_per_bin = 1;
2362 fpovs_per_batch = 63;
2363 break;
2364 case CHIP_RAVEN:
2365 context_states_per_bin = 6;
2366 persistent_states_per_bin = 32;
2367 fpovs_per_batch = 63;
2368 break;
2369 default:
2370 unreachable("unhandled family while determining binning state.");
2371 }
2372
2373 pipeline->graphics.bin.pa_sc_binner_cntl_0 =
2374 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2375 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2376 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2377 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2378 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2379 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2380 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2381 S_028C44_DISABLE_START_OF_PRIM(1) |
2382 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2383 S_028C44_OPTIMAL_BIN_SELECTION(1);
2384
2385 /* DFSM is not implemented yet */
2386 assert(!pipeline->device->dfsm_allowed);
2387 }
2388
2389 static VkResult
2390 radv_pipeline_init(struct radv_pipeline *pipeline,
2391 struct radv_device *device,
2392 struct radv_pipeline_cache *cache,
2393 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2394 const struct radv_graphics_pipeline_create_info *extra,
2395 const VkAllocationCallbacks *alloc)
2396 {
2397 VkResult result;
2398 bool has_view_index = false;
2399
2400 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2401 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2402 if (subpass->view_mask)
2403 has_view_index = true;
2404 if (alloc == NULL)
2405 alloc = &device->alloc;
2406
2407 pipeline->device = device;
2408 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2409 assert(pipeline->layout);
2410
2411 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2412 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2413
2414 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2415 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2416 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2417 pStages[stage] = &pCreateInfo->pStages[i];
2418 }
2419
2420 radv_create_shaders(pipeline, device, cache,
2421 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, has_view_index),
2422 pStages);
2423
2424 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2425 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2426 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2427 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2428 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2429
2430 if (radv_pipeline_has_gs(pipeline)) {
2431 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2432 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2433 } else {
2434 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2435 }
2436 if (extra && extra->use_rectlist) {
2437 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2438 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2439 pipeline->graphics.can_use_guardband = true;
2440 }
2441 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2442 /* prim vertex count will need TESS changes */
2443 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2444
2445 /* Ensure that some export memory is always allocated, for two reasons:
2446 *
2447 * 1) Correctness: The hardware ignores the EXEC mask if no export
2448 * memory is allocated, so KILL and alpha test do not work correctly
2449 * without this.
2450 * 2) Performance: Every shader needs at least a NULL export, even when
2451 * it writes no color/depth output. The NULL export instruction
2452 * stalls without this setting.
2453 *
2454 * Don't add this to CB_SHADER_MASK.
2455 */
2456 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2457 if (!pipeline->graphics.blend.spi_shader_col_format) {
2458 if (!ps->info.fs.writes_z &&
2459 !ps->info.fs.writes_stencil &&
2460 !ps->info.fs.writes_sample_mask)
2461 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2462 }
2463
2464 unsigned z_order;
2465 pipeline->graphics.db_shader_control = 0;
2466 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2467 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2468 else
2469 z_order = V_02880C_LATE_Z;
2470
2471 pipeline->graphics.db_shader_control =
2472 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2473 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2474 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2475 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2476 S_02880C_Z_ORDER(z_order) |
2477 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2478 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2479 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2480
2481 if (pipeline->device->physical_device->has_rbplus)
2482 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
2483
2484 unsigned shader_z_format =
2485 ac_get_spi_shader_z_format(ps->info.fs.writes_z,
2486 ps->info.fs.writes_stencil,
2487 ps->info.fs.writes_sample_mask);
2488 pipeline->graphics.shader_z_format = shader_z_format;
2489
2490 calculate_vgt_gs_mode(pipeline);
2491 calculate_vs_outinfo(pipeline);
2492 calculate_ps_inputs(pipeline);
2493
2494 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2495 if (pipeline->shaders[i]) {
2496 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2497 }
2498 }
2499
2500 uint32_t stages = 0;
2501 if (radv_pipeline_has_tess(pipeline)) {
2502 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2503 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2504
2505 if (radv_pipeline_has_gs(pipeline))
2506 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2507 S_028B54_GS_EN(1) |
2508 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2509 else
2510 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2511
2512 } else if (radv_pipeline_has_gs(pipeline))
2513 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2514 S_028B54_GS_EN(1) |
2515 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2516
2517 if (device->physical_device->rad_info.chip_class >= GFX9)
2518 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2519
2520 pipeline->graphics.vgt_shader_stages_en = stages;
2521
2522 if (radv_pipeline_has_gs(pipeline)) {
2523 calculate_gs_ring_sizes(pipeline);
2524 if (device->physical_device->rad_info.chip_class >= GFX9)
2525 calculate_gfx9_gs_info(pCreateInfo, pipeline);
2526 }
2527
2528 if (radv_pipeline_has_tess(pipeline)) {
2529 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2530 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2531 pipeline->graphics.prim_vertex_count.incr = 1;
2532 }
2533 calculate_tess_state(pipeline, pCreateInfo);
2534 }
2535
2536 if (radv_pipeline_has_tess(pipeline))
2537 pipeline->graphics.primgroup_size = pipeline->graphics.tess.num_patches;
2538 else if (radv_pipeline_has_gs(pipeline))
2539 pipeline->graphics.primgroup_size = 64;
2540 else
2541 pipeline->graphics.primgroup_size = 128; /* recommended without a GS */
2542
2543 pipeline->graphics.partial_es_wave = false;
2544 if (pipeline->device->has_distributed_tess) {
2545 if (radv_pipeline_has_gs(pipeline)) {
2546 if (device->physical_device->rad_info.chip_class <= VI)
2547 pipeline->graphics.partial_es_wave = true;
2548 }
2549 }
2550 /* GS requirement. */
2551 if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= pipeline->device->gs_table_depth - 3)
2552 pipeline->graphics.partial_es_wave = true;
2553
2554 pipeline->graphics.wd_switch_on_eop = false;
2555 if (device->physical_device->rad_info.chip_class >= CIK) {
2556 unsigned prim = pipeline->graphics.prim;
2557 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
2558 * 4 shader engines. Set 1 to pass the assertion below.
2559 * The other cases are hardware requirements. */
2560 if (device->physical_device->rad_info.max_se < 4 ||
2561 prim == V_008958_DI_PT_POLYGON ||
2562 prim == V_008958_DI_PT_LINELOOP ||
2563 prim == V_008958_DI_PT_TRIFAN ||
2564 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
2565 (pipeline->graphics.prim_restart_enable &&
2566 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
2567 (prim != V_008958_DI_PT_POINTLIST &&
2568 prim != V_008958_DI_PT_LINESTRIP &&
2569 prim != V_008958_DI_PT_TRISTRIP))))
2570 pipeline->graphics.wd_switch_on_eop = true;
2571 }
2572
2573 pipeline->graphics.ia_switch_on_eoi = false;
2574 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2575 pipeline->graphics.ia_switch_on_eoi = true;
2576 if (radv_pipeline_has_gs(pipeline) &&
2577 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
2578 pipeline->graphics.ia_switch_on_eoi = true;
2579 if (radv_pipeline_has_tess(pipeline)) {
2580 /* SWITCH_ON_EOI must be set if PrimID is used. */
2581 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
2582 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
2583 pipeline->graphics.ia_switch_on_eoi = true;
2584 }
2585
2586 pipeline->graphics.partial_vs_wave = false;
2587 if (radv_pipeline_has_tess(pipeline)) {
2588 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
2589 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
2590 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
2591 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
2592 radv_pipeline_has_gs(pipeline))
2593 pipeline->graphics.partial_vs_wave = true;
2594 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
2595 if (device->has_distributed_tess) {
2596 if (radv_pipeline_has_gs(pipeline)) {
2597 if (device->physical_device->rad_info.family == CHIP_TONGA ||
2598 device->physical_device->rad_info.family == CHIP_FIJI ||
2599 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
2600 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
2601 device->physical_device->rad_info.family == CHIP_POLARIS12)
2602 pipeline->graphics.partial_vs_wave = true;
2603 } else {
2604 pipeline->graphics.partial_vs_wave = true;
2605 }
2606 }
2607 }
2608
2609 pipeline->graphics.base_ia_multi_vgt_param =
2610 S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
2611 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
2612 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
2613 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
2614 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
2615
2616 const VkPipelineVertexInputStateCreateInfo *vi_info =
2617 pCreateInfo->pVertexInputState;
2618 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
2619
2620 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2621 const VkVertexInputAttributeDescription *desc =
2622 &vi_info->pVertexAttributeDescriptions[i];
2623 unsigned loc = desc->location;
2624 const struct vk_format_description *format_desc;
2625 int first_non_void;
2626 uint32_t num_format, data_format;
2627 format_desc = vk_format_description(desc->format);
2628 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2629
2630 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2631 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2632
2633 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2634 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2635 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2636 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2637 S_008F0C_NUM_FORMAT(num_format) |
2638 S_008F0C_DATA_FORMAT(data_format);
2639 velems->format_size[loc] = format_desc->block.bits / 8;
2640 velems->offset[loc] = desc->offset;
2641 velems->binding[loc] = desc->binding;
2642 velems->count = MAX2(velems->count, loc + 1);
2643 }
2644
2645 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2646 const VkVertexInputBindingDescription *desc =
2647 &vi_info->pVertexBindingDescriptions[i];
2648
2649 pipeline->binding_stride[desc->binding] = desc->stride;
2650 }
2651
2652 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
2653 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
2654
2655 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2656 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2657 if (loc->sgpr_idx != -1) {
2658 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
2659 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2660 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
2661 pipeline->graphics.vtx_emit_num = 3;
2662 else
2663 pipeline->graphics.vtx_emit_num = 2;
2664 }
2665
2666 pipeline->graphics.vtx_reuse_depth = 30;
2667 if (radv_pipeline_has_tess(pipeline) &&
2668 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2669 pipeline->graphics.vtx_reuse_depth = 14;
2670 }
2671
2672 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2673 radv_dump_pipeline_stats(device, pipeline);
2674 }
2675
2676 radv_compute_binning_state(pipeline, pCreateInfo);
2677
2678 result = radv_pipeline_scratch_init(device, pipeline);
2679 return result;
2680 }
2681
2682 VkResult
2683 radv_graphics_pipeline_create(
2684 VkDevice _device,
2685 VkPipelineCache _cache,
2686 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2687 const struct radv_graphics_pipeline_create_info *extra,
2688 const VkAllocationCallbacks *pAllocator,
2689 VkPipeline *pPipeline)
2690 {
2691 RADV_FROM_HANDLE(radv_device, device, _device);
2692 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2693 struct radv_pipeline *pipeline;
2694 VkResult result;
2695
2696 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2697 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2698 if (pipeline == NULL)
2699 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2700
2701 result = radv_pipeline_init(pipeline, device, cache,
2702 pCreateInfo, extra, pAllocator);
2703 if (result != VK_SUCCESS) {
2704 radv_pipeline_destroy(device, pipeline, pAllocator);
2705 return result;
2706 }
2707
2708 *pPipeline = radv_pipeline_to_handle(pipeline);
2709
2710 return VK_SUCCESS;
2711 }
2712
2713 VkResult radv_CreateGraphicsPipelines(
2714 VkDevice _device,
2715 VkPipelineCache pipelineCache,
2716 uint32_t count,
2717 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2718 const VkAllocationCallbacks* pAllocator,
2719 VkPipeline* pPipelines)
2720 {
2721 VkResult result = VK_SUCCESS;
2722 unsigned i = 0;
2723
2724 for (; i < count; i++) {
2725 VkResult r;
2726 r = radv_graphics_pipeline_create(_device,
2727 pipelineCache,
2728 &pCreateInfos[i],
2729 NULL, pAllocator, &pPipelines[i]);
2730 if (r != VK_SUCCESS) {
2731 result = r;
2732 pPipelines[i] = VK_NULL_HANDLE;
2733 }
2734 }
2735
2736 return result;
2737 }
2738
2739 static VkResult radv_compute_pipeline_create(
2740 VkDevice _device,
2741 VkPipelineCache _cache,
2742 const VkComputePipelineCreateInfo* pCreateInfo,
2743 const VkAllocationCallbacks* pAllocator,
2744 VkPipeline* pPipeline)
2745 {
2746 RADV_FROM_HANDLE(radv_device, device, _device);
2747 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2748 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2749 struct radv_pipeline *pipeline;
2750 VkResult result;
2751
2752 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2753 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2754 if (pipeline == NULL)
2755 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2756
2757 pipeline->device = device;
2758 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2759 assert(pipeline->layout);
2760
2761 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
2762 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
2763
2764 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
2765 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2766 result = radv_pipeline_scratch_init(device, pipeline);
2767 if (result != VK_SUCCESS) {
2768 radv_pipeline_destroy(device, pipeline, pAllocator);
2769 return result;
2770 }
2771
2772 *pPipeline = radv_pipeline_to_handle(pipeline);
2773
2774 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2775 radv_dump_pipeline_stats(device, pipeline);
2776 }
2777 return VK_SUCCESS;
2778 }
2779 VkResult radv_CreateComputePipelines(
2780 VkDevice _device,
2781 VkPipelineCache pipelineCache,
2782 uint32_t count,
2783 const VkComputePipelineCreateInfo* pCreateInfos,
2784 const VkAllocationCallbacks* pAllocator,
2785 VkPipeline* pPipelines)
2786 {
2787 VkResult result = VK_SUCCESS;
2788
2789 unsigned i = 0;
2790 for (; i < count; i++) {
2791 VkResult r;
2792 r = radv_compute_pipeline_create(_device, pipelineCache,
2793 &pCreateInfos[i],
2794 pAllocator, &pPipelines[i]);
2795 if (r != VK_SUCCESS) {
2796 result = r;
2797 pPipelines[i] = VK_NULL_HANDLE;
2798 }
2799 }
2800
2801 return result;
2802 }