2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
50 struct radv_blend_state
{
51 uint32_t blend_enable_4bit
;
52 uint32_t need_src_alpha
;
54 uint32_t cb_color_control
;
55 uint32_t cb_target_mask
;
56 uint32_t cb_target_enabled_4bit
;
57 uint32_t sx_mrt_blend_opt
[8];
58 uint32_t cb_blend_control
[8];
60 uint32_t spi_shader_col_format
;
61 uint32_t col_format_is_int8
;
62 uint32_t col_format_is_int10
;
63 uint32_t cb_shader_mask
;
64 uint32_t db_alpha_to_mask
;
66 uint32_t commutative_4bit
;
68 bool single_cb_enable
;
69 bool mrt0_is_dual_src
;
72 struct radv_dsa_order_invariance
{
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
85 struct radv_tessellation_state
{
86 uint32_t ls_hs_config
;
92 static const VkPipelineMultisampleStateCreateInfo
*
93 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
95 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
96 return pCreateInfo
->pMultisampleState
;
100 static const VkPipelineTessellationStateCreateInfo
*
101 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
103 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
104 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
105 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
106 return pCreateInfo
->pTessellationState
;
112 static const VkPipelineDepthStencilStateCreateInfo
*
113 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
115 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
116 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
118 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
119 subpass
->depth_stencil_attachment
)
120 return pCreateInfo
->pDepthStencilState
;
124 static const VkPipelineColorBlendStateCreateInfo
*
125 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
127 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
128 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
130 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
131 subpass
->has_color_att
)
132 return pCreateInfo
->pColorBlendState
;
136 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
138 struct radv_shader_variant
*variant
= NULL
;
139 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
140 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
141 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
142 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
143 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
144 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
147 return variant
->info
.is_ngg
;
150 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
152 assert(radv_pipeline_has_ngg(pipeline
));
154 struct radv_shader_variant
*variant
= NULL
;
155 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
156 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
157 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
158 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
159 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
160 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
163 return variant
->info
.is_ngg_passthrough
;
166 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
168 if (!radv_pipeline_has_gs(pipeline
))
171 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
172 * On GFX10, it might be required in rare cases if it's not possible to
175 if (radv_pipeline_has_ngg(pipeline
))
178 assert(pipeline
->gs_copy_shader
);
183 radv_pipeline_destroy(struct radv_device
*device
,
184 struct radv_pipeline
*pipeline
,
185 const VkAllocationCallbacks
* allocator
)
187 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
188 if (pipeline
->shaders
[i
])
189 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
191 if (pipeline
->gs_copy_shader
)
192 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
195 free(pipeline
->cs
.buf
);
197 vk_object_base_finish(&pipeline
->base
);
198 vk_free2(&device
->vk
.alloc
, allocator
, pipeline
);
201 void radv_DestroyPipeline(
203 VkPipeline _pipeline
,
204 const VkAllocationCallbacks
* pAllocator
)
206 RADV_FROM_HANDLE(radv_device
, device
, _device
);
207 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
212 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
215 static uint32_t get_hash_flags(struct radv_device
*device
)
217 uint32_t hash_flags
= 0;
219 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
220 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
221 if (device
->physical_device
->cs_wave_size
== 32)
222 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
223 if (device
->physical_device
->ps_wave_size
== 32)
224 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
225 if (device
->physical_device
->ge_wave_size
== 32)
226 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
227 if (device
->physical_device
->use_llvm
)
228 hash_flags
|= RADV_HASH_SHADER_LLVM
;
233 radv_pipeline_scratch_init(struct radv_device
*device
,
234 struct radv_pipeline
*pipeline
)
236 unsigned scratch_bytes_per_wave
= 0;
237 unsigned max_waves
= 0;
238 unsigned min_waves
= 1;
240 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
241 if (pipeline
->shaders
[i
] &&
242 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
243 unsigned max_stage_waves
= device
->scratch_waves
;
245 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
246 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
248 max_stage_waves
= MIN2(max_stage_waves
,
249 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
250 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
251 max_waves
= MAX2(max_waves
, max_stage_waves
);
255 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
256 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
257 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
258 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
259 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
262 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
263 pipeline
->max_waves
= max_waves
;
267 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
270 case VK_LOGIC_OP_CLEAR
:
271 return V_028808_ROP3_CLEAR
;
272 case VK_LOGIC_OP_AND
:
273 return V_028808_ROP3_AND
;
274 case VK_LOGIC_OP_AND_REVERSE
:
275 return V_028808_ROP3_AND_REVERSE
;
276 case VK_LOGIC_OP_COPY
:
277 return V_028808_ROP3_COPY
;
278 case VK_LOGIC_OP_AND_INVERTED
:
279 return V_028808_ROP3_AND_INVERTED
;
280 case VK_LOGIC_OP_NO_OP
:
281 return V_028808_ROP3_NO_OP
;
282 case VK_LOGIC_OP_XOR
:
283 return V_028808_ROP3_XOR
;
285 return V_028808_ROP3_OR
;
286 case VK_LOGIC_OP_NOR
:
287 return V_028808_ROP3_NOR
;
288 case VK_LOGIC_OP_EQUIVALENT
:
289 return V_028808_ROP3_EQUIVALENT
;
290 case VK_LOGIC_OP_INVERT
:
291 return V_028808_ROP3_INVERT
;
292 case VK_LOGIC_OP_OR_REVERSE
:
293 return V_028808_ROP3_OR_REVERSE
;
294 case VK_LOGIC_OP_COPY_INVERTED
:
295 return V_028808_ROP3_COPY_INVERTED
;
296 case VK_LOGIC_OP_OR_INVERTED
:
297 return V_028808_ROP3_OR_INVERTED
;
298 case VK_LOGIC_OP_NAND
:
299 return V_028808_ROP3_NAND
;
300 case VK_LOGIC_OP_SET
:
301 return V_028808_ROP3_SET
;
303 unreachable("Unhandled logic op");
308 static uint32_t si_translate_blend_function(VkBlendOp op
)
311 case VK_BLEND_OP_ADD
:
312 return V_028780_COMB_DST_PLUS_SRC
;
313 case VK_BLEND_OP_SUBTRACT
:
314 return V_028780_COMB_SRC_MINUS_DST
;
315 case VK_BLEND_OP_REVERSE_SUBTRACT
:
316 return V_028780_COMB_DST_MINUS_SRC
;
317 case VK_BLEND_OP_MIN
:
318 return V_028780_COMB_MIN_DST_SRC
;
319 case VK_BLEND_OP_MAX
:
320 return V_028780_COMB_MAX_DST_SRC
;
326 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
329 case VK_BLEND_FACTOR_ZERO
:
330 return V_028780_BLEND_ZERO
;
331 case VK_BLEND_FACTOR_ONE
:
332 return V_028780_BLEND_ONE
;
333 case VK_BLEND_FACTOR_SRC_COLOR
:
334 return V_028780_BLEND_SRC_COLOR
;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
336 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
337 case VK_BLEND_FACTOR_DST_COLOR
:
338 return V_028780_BLEND_DST_COLOR
;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
340 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
341 case VK_BLEND_FACTOR_SRC_ALPHA
:
342 return V_028780_BLEND_SRC_ALPHA
;
343 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
344 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
345 case VK_BLEND_FACTOR_DST_ALPHA
:
346 return V_028780_BLEND_DST_ALPHA
;
347 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
348 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
349 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
350 return V_028780_BLEND_CONSTANT_COLOR
;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
353 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
354 return V_028780_BLEND_CONSTANT_ALPHA
;
355 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
356 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
358 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
359 case VK_BLEND_FACTOR_SRC1_COLOR
:
360 return V_028780_BLEND_SRC1_COLOR
;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
362 return V_028780_BLEND_INV_SRC1_COLOR
;
363 case VK_BLEND_FACTOR_SRC1_ALPHA
:
364 return V_028780_BLEND_SRC1_ALPHA
;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
366 return V_028780_BLEND_INV_SRC1_ALPHA
;
372 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
375 case VK_BLEND_OP_ADD
:
376 return V_028760_OPT_COMB_ADD
;
377 case VK_BLEND_OP_SUBTRACT
:
378 return V_028760_OPT_COMB_SUBTRACT
;
379 case VK_BLEND_OP_REVERSE_SUBTRACT
:
380 return V_028760_OPT_COMB_REVSUBTRACT
;
381 case VK_BLEND_OP_MIN
:
382 return V_028760_OPT_COMB_MIN
;
383 case VK_BLEND_OP_MAX
:
384 return V_028760_OPT_COMB_MAX
;
386 return V_028760_OPT_COMB_BLEND_DISABLED
;
390 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
393 case VK_BLEND_FACTOR_ZERO
:
394 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
395 case VK_BLEND_FACTOR_ONE
:
396 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
397 case VK_BLEND_FACTOR_SRC_COLOR
:
398 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
399 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
400 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
401 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
402 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
403 case VK_BLEND_FACTOR_SRC_ALPHA
:
404 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
405 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
406 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
407 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
408 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
409 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
411 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
419 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
420 unsigned *dst_factor
, unsigned expected_dst
,
421 unsigned replacement_src
)
423 if (*src_factor
== expected_dst
&&
424 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
425 *src_factor
= VK_BLEND_FACTOR_ZERO
;
426 *dst_factor
= replacement_src
;
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func
== VK_BLEND_OP_SUBTRACT
)
430 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
431 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
432 *func
= VK_BLEND_OP_SUBTRACT
;
436 static bool si_blend_factor_uses_dst(unsigned factor
)
438 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
439 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
440 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
441 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
442 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
445 static bool is_dual_src(VkBlendFactor factor
)
448 case VK_BLEND_FACTOR_SRC1_COLOR
:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
450 case VK_BLEND_FACTOR_SRC1_ALPHA
:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
458 static unsigned radv_choose_spi_color_format(VkFormat vk_format
,
460 bool blend_need_alpha
)
462 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
463 struct ac_spi_color_formats formats
= {};
464 unsigned format
, ntype
, swap
;
466 format
= radv_translate_colorformat(vk_format
);
467 ntype
= radv_translate_color_numformat(vk_format
, desc
,
468 vk_format_get_first_non_void_channel(vk_format
));
469 swap
= radv_translate_colorswap(vk_format
, false);
471 ac_choose_spi_color_formats(format
, swap
, ntype
, false, &formats
);
473 if (blend_enable
&& blend_need_alpha
)
474 return formats
.blend_alpha
;
475 else if(blend_need_alpha
)
476 return formats
.alpha
;
477 else if(blend_enable
)
478 return formats
.blend
;
480 return formats
.normal
;
484 format_is_int8(VkFormat format
)
486 const struct vk_format_description
*desc
= vk_format_description(format
);
487 int channel
= vk_format_get_first_non_void_channel(format
);
489 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
490 desc
->channel
[channel
].size
== 8;
494 format_is_int10(VkFormat format
)
496 const struct vk_format_description
*desc
= vk_format_description(format
);
498 if (desc
->nr_channels
!= 4)
500 for (unsigned i
= 0; i
< 4; i
++) {
501 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
508 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
509 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
510 struct radv_blend_state
*blend
)
512 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
513 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
514 unsigned exp_fmt
[MAX_RTS
] = {0};
515 unsigned is_int8
[MAX_RTS
] = {0}, is_int10
[MAX_RTS
] = {0};
516 unsigned col_format
= 0;
517 unsigned col_format_is_int8
= 0, col_format_is_int10
= 0;
519 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
522 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
||
523 !(blend
->cb_target_mask
& (0xfu
<< (i
* 4)))) {
524 cf
= V_028714_SPI_SHADER_ZERO
;
526 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
528 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
530 cf
= radv_choose_spi_color_format(attachment
->format
,
532 blend
->need_src_alpha
& (1 << i
));
534 is_int8
[i
] = format_is_int8(attachment
->format
);
535 is_int10
[i
] = format_is_int10(attachment
->format
);
541 if (!exp_fmt
[0] && blend
->need_src_alpha
& (1 << 0)) {
542 /* When a subpass doesn't have any color attachments, write the
543 * alpha channel of MRT0 when alpha coverage is enabled because
544 * the depth attachment needs it.
546 exp_fmt
[0] = V_028714_SPI_SHADER_32_AR
;
549 /* The output for dual source blending should have the same format as
552 if (blend
->mrt0_is_dual_src
) {
553 col_format
|= (exp_fmt
[0] << 4) | exp_fmt
[0];
554 col_format_is_int8
|= (is_int8
[0] << 1) | is_int8
[0];
555 col_format_is_int10
|= (is_int10
[0] << 1) | is_int10
[0];
557 /* Remove holes in SPI_SHADER_COL_FORMAT. */
558 unsigned num_color_targets
= 0;
559 for (unsigned i
= 0; i
< MAX_RTS
; i
++) {
563 col_format
|= exp_fmt
[i
] << (4 * num_color_targets
);
564 col_format_is_int8
|= is_int8
[i
] << num_color_targets
;
565 col_format_is_int10
|= is_int10
[i
] << num_color_targets
;
570 blend
->spi_shader_col_format
= col_format
;
571 blend
->col_format_is_int8
= col_format_is_int8
;
572 blend
->col_format_is_int10
= col_format_is_int10
;
576 * Ordered so that for each i,
577 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
579 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
580 VK_FORMAT_R32_SFLOAT
,
581 VK_FORMAT_R32G32_SFLOAT
,
582 VK_FORMAT_R8G8B8A8_UNORM
,
583 VK_FORMAT_R16G16B16A16_UNORM
,
584 VK_FORMAT_R16G16B16A16_SNORM
,
585 VK_FORMAT_R16G16B16A16_UINT
,
586 VK_FORMAT_R16G16B16A16_SINT
,
587 VK_FORMAT_R32G32B32A32_SFLOAT
,
588 VK_FORMAT_R8G8B8A8_UINT
,
589 VK_FORMAT_R8G8B8A8_SINT
,
590 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
591 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
594 unsigned radv_format_meta_fs_key(VkFormat format
)
596 unsigned col_format
= radv_choose_spi_color_format(format
, false, false);
598 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
599 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
600 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
602 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
603 bool is_int8
= format_is_int8(format
);
604 bool is_int10
= format_is_int10(format
);
606 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
610 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
611 VkBlendOp op
, VkBlendFactor src
,
612 VkBlendFactor dst
, unsigned chanmask
)
614 /* Src factor is allowed when it does not depend on Dst. */
615 static const uint32_t src_allowed
=
616 (1u << VK_BLEND_FACTOR_ONE
) |
617 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
618 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
619 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
620 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
621 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
622 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
623 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
624 (1u << VK_BLEND_FACTOR_ZERO
) |
625 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
626 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
627 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
628 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
629 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
630 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
632 if (dst
== VK_BLEND_FACTOR_ONE
&&
633 (src_allowed
& (1u << src
))) {
634 /* Addition is commutative, but floating point addition isn't
635 * associative: subtle changes can be introduced via different
636 * rounding. Be conservative, only enable for min and max.
638 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
639 blend
->commutative_4bit
|= chanmask
;
643 static struct radv_blend_state
644 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
645 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
646 const struct radv_graphics_pipeline_create_info
*extra
)
648 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
649 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
650 struct radv_blend_state blend
= {0};
651 unsigned mode
= V_028808_CB_NORMAL
;
654 if (extra
&& extra
->custom_blend_mode
) {
655 blend
.single_cb_enable
= true;
656 mode
= extra
->custom_blend_mode
;
659 blend
.cb_color_control
= 0;
661 if (vkblend
->logicOpEnable
)
662 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
664 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
667 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
668 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
669 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
670 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
671 S_028B70_OFFSET_ROUND(1);
673 if (vkms
&& vkms
->alphaToCoverageEnable
) {
674 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
675 blend
.need_src_alpha
|= 0x1;
678 blend
.cb_target_mask
= 0;
680 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
681 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
682 unsigned blend_cntl
= 0;
683 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
684 VkBlendOp eqRGB
= att
->colorBlendOp
;
685 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
686 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
687 VkBlendOp eqA
= att
->alphaBlendOp
;
688 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
689 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
691 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
693 if (!att
->colorWriteMask
)
696 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
697 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
698 if (!att
->blendEnable
) {
699 blend
.cb_blend_control
[i
] = blend_cntl
;
703 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
705 blend
.mrt0_is_dual_src
= true;
707 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
708 srcRGB
= VK_BLEND_FACTOR_ONE
;
709 dstRGB
= VK_BLEND_FACTOR_ONE
;
711 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
712 srcA
= VK_BLEND_FACTOR_ONE
;
713 dstA
= VK_BLEND_FACTOR_ONE
;
716 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
718 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
721 /* Blending optimizations for RB+.
722 * These transformations don't change the behavior.
724 * First, get rid of DST in the blend factors:
725 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
727 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
728 VK_BLEND_FACTOR_DST_COLOR
,
729 VK_BLEND_FACTOR_SRC_COLOR
);
731 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
732 VK_BLEND_FACTOR_DST_COLOR
,
733 VK_BLEND_FACTOR_SRC_COLOR
);
735 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
736 VK_BLEND_FACTOR_DST_ALPHA
,
737 VK_BLEND_FACTOR_SRC_ALPHA
);
739 /* Look up the ideal settings from tables. */
740 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
741 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
742 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
743 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
745 /* Handle interdependencies. */
746 if (si_blend_factor_uses_dst(srcRGB
))
747 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
748 if (si_blend_factor_uses_dst(srcA
))
749 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
751 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
752 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
753 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
754 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
755 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
757 /* Set the final value. */
758 blend
.sx_mrt_blend_opt
[i
] =
759 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
760 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
761 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
762 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
763 S_028760_ALPHA_DST_OPT(dstA_opt
) |
764 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
765 blend_cntl
|= S_028780_ENABLE(1);
767 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
768 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
769 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
770 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
771 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
772 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
773 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
774 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
776 blend
.cb_blend_control
[i
] = blend_cntl
;
778 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
780 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
781 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
782 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
783 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
784 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
785 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
786 blend
.need_src_alpha
|= 1 << i
;
788 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
789 blend
.cb_blend_control
[i
] = 0;
790 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
794 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
795 /* Disable RB+ blend optimizations for dual source blending. */
796 if (blend
.mrt0_is_dual_src
) {
797 for (i
= 0; i
< 8; i
++) {
798 blend
.sx_mrt_blend_opt
[i
] =
799 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
800 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
804 /* RB+ doesn't work with dual source blending, logic op and
807 if (blend
.mrt0_is_dual_src
||
808 (vkblend
&& vkblend
->logicOpEnable
) ||
809 mode
== V_028808_CB_RESOLVE
)
810 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
813 if (blend
.cb_target_mask
)
814 blend
.cb_color_control
|= S_028808_MODE(mode
);
816 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
818 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
822 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
825 case VK_STENCIL_OP_KEEP
:
826 return V_02842C_STENCIL_KEEP
;
827 case VK_STENCIL_OP_ZERO
:
828 return V_02842C_STENCIL_ZERO
;
829 case VK_STENCIL_OP_REPLACE
:
830 return V_02842C_STENCIL_REPLACE_TEST
;
831 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
832 return V_02842C_STENCIL_ADD_CLAMP
;
833 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
834 return V_02842C_STENCIL_SUB_CLAMP
;
835 case VK_STENCIL_OP_INVERT
:
836 return V_02842C_STENCIL_INVERT
;
837 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
838 return V_02842C_STENCIL_ADD_WRAP
;
839 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
840 return V_02842C_STENCIL_SUB_WRAP
;
846 static uint32_t si_translate_fill(VkPolygonMode func
)
849 case VK_POLYGON_MODE_FILL
:
850 return V_028814_X_DRAW_TRIANGLES
;
851 case VK_POLYGON_MODE_LINE
:
852 return V_028814_X_DRAW_LINES
;
853 case VK_POLYGON_MODE_POINT
:
854 return V_028814_X_DRAW_POINTS
;
857 return V_028814_X_DRAW_POINTS
;
861 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
863 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
864 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
865 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
866 uint32_t ps_iter_samples
= 1;
867 uint32_t num_samples
;
869 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
871 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
872 * subpass uses color attachments, totalSamples is the number of
873 * samples of the color attachments. Otherwise, totalSamples is the
874 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
875 * specified at pipeline creation time."
877 if (subpass
->has_color_att
) {
878 num_samples
= subpass
->color_sample_count
;
880 num_samples
= vkms
->rasterizationSamples
;
883 if (vkms
->sampleShadingEnable
) {
884 ps_iter_samples
= ceilf(vkms
->minSampleShading
* num_samples
);
885 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
887 return ps_iter_samples
;
891 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
893 return pCreateInfo
->depthTestEnable
&&
894 pCreateInfo
->depthWriteEnable
&&
895 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
899 radv_writes_stencil(const VkStencilOpState
*state
)
901 return state
->writeMask
&&
902 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
903 state
->passOp
!= VK_STENCIL_OP_KEEP
||
904 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
908 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
910 return pCreateInfo
->stencilTestEnable
&&
911 (radv_writes_stencil(&pCreateInfo
->front
) ||
912 radv_writes_stencil(&pCreateInfo
->back
));
916 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
918 return radv_is_depth_write_enabled(pCreateInfo
) ||
919 radv_is_stencil_write_enabled(pCreateInfo
);
923 radv_order_invariant_stencil_op(VkStencilOp op
)
925 /* REPLACE is normally order invariant, except when the stencil
926 * reference value is written by the fragment shader. Tracking this
927 * interaction does not seem worth the effort, so be conservative.
929 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
930 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
931 op
!= VK_STENCIL_OP_REPLACE
;
935 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
937 /* Compute whether, assuming Z writes are disabled, this stencil state
938 * is order invariant in the sense that the set of passing fragments as
939 * well as the final stencil buffer result does not depend on the order
942 return !state
->writeMask
||
943 /* The following assumes that Z writes are disabled. */
944 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
945 radv_order_invariant_stencil_op(state
->passOp
) &&
946 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
947 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
948 radv_order_invariant_stencil_op(state
->failOp
));
952 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
953 struct radv_blend_state
*blend
,
954 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
956 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
957 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
958 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
959 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
960 unsigned colormask
= blend
->cb_target_enabled_4bit
;
962 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
965 /* Be conservative if a logic operation is enabled with color buffers. */
966 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
969 /* Default depth/stencil invariance when no attachment is bound. */
970 struct radv_dsa_order_invariance dsa_order_invariant
= {
971 .zs
= true, .pass_set
= true
975 struct radv_render_pass_attachment
*attachment
=
976 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
977 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
978 struct radv_dsa_order_invariance order_invariance
[2];
979 struct radv_shader_variant
*ps
=
980 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
982 /* Compute depth/stencil order invariance in order to know if
983 * it's safe to enable out-of-order.
985 bool zfunc_is_ordered
=
986 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
987 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
988 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
989 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
990 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
992 bool nozwrite_and_order_invariant_stencil
=
993 !radv_is_ds_write_enabled(vkds
) ||
994 (!radv_is_depth_write_enabled(vkds
) &&
995 radv_order_invariant_stencil_state(&vkds
->front
) &&
996 radv_order_invariant_stencil_state(&vkds
->back
));
998 order_invariance
[1].zs
=
999 nozwrite_and_order_invariant_stencil
||
1000 (!radv_is_stencil_write_enabled(vkds
) &&
1002 order_invariance
[0].zs
=
1003 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1005 order_invariance
[1].pass_set
=
1006 nozwrite_and_order_invariant_stencil
||
1007 (!radv_is_stencil_write_enabled(vkds
) &&
1008 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1009 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1010 order_invariance
[0].pass_set
=
1011 !radv_is_depth_write_enabled(vkds
) ||
1012 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1013 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1015 dsa_order_invariant
= order_invariance
[has_stencil
];
1016 if (!dsa_order_invariant
.zs
)
1019 /* The set of PS invocations is always order invariant,
1020 * except when early Z/S tests are requested.
1023 ps
->info
.ps
.writes_memory
&&
1024 ps
->info
.ps
.early_fragment_test
&&
1025 !dsa_order_invariant
.pass_set
)
1028 /* Determine if out-of-order rasterization should be disabled
1029 * when occlusion queries are used.
1031 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1032 !dsa_order_invariant
.pass_set
;
1035 /* No color buffers are enabled for writing. */
1039 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1042 /* Only commutative blending. */
1043 if (blendmask
& ~blend
->commutative_4bit
)
1046 if (!dsa_order_invariant
.pass_set
)
1050 if (colormask
& ~blendmask
)
1057 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1058 struct radv_blend_state
*blend
,
1059 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1061 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1062 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1063 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1064 bool out_of_order_rast
= false;
1065 int ps_iter_samples
= 1;
1066 uint32_t mask
= 0xffff;
1069 ms
->num_samples
= vkms
->rasterizationSamples
;
1071 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1073 * "Sample shading is enabled for a graphics pipeline:
1075 * - If the interface of the fragment shader entry point of the
1076 * graphics pipeline includes an input variable decorated
1077 * with SampleId or SamplePosition. In this case
1078 * minSampleShadingFactor takes the value 1.0.
1079 * - Else if the sampleShadingEnable member of the
1080 * VkPipelineMultisampleStateCreateInfo structure specified
1081 * when creating the graphics pipeline is set to VK_TRUE. In
1082 * this case minSampleShadingFactor takes the value of
1083 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1085 * Otherwise, sample shading is considered disabled."
1087 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1088 ps_iter_samples
= ms
->num_samples
;
1090 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1093 ms
->num_samples
= 1;
1096 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1097 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1098 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1099 /* Out-of-order rasterization is explicitly enabled by the
1102 out_of_order_rast
= true;
1104 /* Determine if the driver can enable out-of-order
1105 * rasterization internally.
1108 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1111 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1112 ms
->pa_sc_aa_config
= 0;
1113 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1114 S_028804_INCOHERENT_EQAA_READS(1) |
1115 S_028804_INTERPOLATE_COMP_Z(1) |
1116 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1117 ms
->pa_sc_mode_cntl_1
=
1118 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1119 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1120 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1121 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1123 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1124 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1125 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1126 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1127 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1128 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1129 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1130 S_028A48_VPORT_SCISSOR_ENABLE(1);
1132 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1133 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1134 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1136 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1137 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1138 /* From the Vulkan spec 1.1.129:
1140 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1141 * are being rasterized, sample locations may all be
1142 * treated as being at the pixel center (this may
1143 * affect attribute and depth interpolation)."
1145 ms
->num_samples
= 1;
1149 if (ms
->num_samples
> 1) {
1150 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1151 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1152 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1153 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1154 unsigned log_z_samples
= util_logbase2(z_samples
);
1155 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1156 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1157 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1158 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1159 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1160 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1161 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1162 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1163 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1164 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
);
1165 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1166 if (ps_iter_samples
> 1)
1167 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1170 if (vkms
&& vkms
->pSampleMask
) {
1171 mask
= vkms
->pSampleMask
[0] & 0xffff;
1174 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1175 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1179 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1182 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1184 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1193 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1196 unreachable("unhandled primitive type");
1201 si_translate_prim(enum VkPrimitiveTopology topology
)
1204 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1205 return V_008958_DI_PT_POINTLIST
;
1206 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1207 return V_008958_DI_PT_LINELIST
;
1208 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1209 return V_008958_DI_PT_LINESTRIP
;
1210 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1211 return V_008958_DI_PT_TRILIST
;
1212 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1213 return V_008958_DI_PT_TRISTRIP
;
1214 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1215 return V_008958_DI_PT_TRIFAN
;
1216 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1217 return V_008958_DI_PT_LINELIST_ADJ
;
1218 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1219 return V_008958_DI_PT_LINESTRIP_ADJ
;
1220 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1221 return V_008958_DI_PT_TRILIST_ADJ
;
1222 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1223 return V_008958_DI_PT_TRISTRIP_ADJ
;
1224 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1225 return V_008958_DI_PT_PATCH
;
1233 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1236 case 0: /* GL_POINTS */
1237 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1238 case 1: /* GL_LINES */
1239 case 3: /* GL_LINE_STRIP */
1240 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1241 case 0x8E7A: /* GL_ISOLINES */
1242 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1244 case 4: /* GL_TRIANGLES */
1245 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1246 case 5: /* GL_TRIANGLE_STRIP */
1247 case 7: /* GL_QUADS */
1248 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1256 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1259 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1260 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1261 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1262 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1263 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1264 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1265 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1266 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1267 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1268 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1269 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1270 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1271 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1272 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1279 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1282 case VK_DYNAMIC_STATE_VIEWPORT
:
1283 return RADV_DYNAMIC_VIEWPORT
;
1284 case VK_DYNAMIC_STATE_SCISSOR
:
1285 return RADV_DYNAMIC_SCISSOR
;
1286 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1287 return RADV_DYNAMIC_LINE_WIDTH
;
1288 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1289 return RADV_DYNAMIC_DEPTH_BIAS
;
1290 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1291 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1292 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1293 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1294 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1295 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1296 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1297 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1298 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1299 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1300 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1301 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1302 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1303 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1304 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1305 return RADV_DYNAMIC_LINE_STIPPLE
;
1307 unreachable("Unhandled dynamic state");
1311 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1313 uint32_t states
= RADV_DYNAMIC_ALL
;
1315 /* If rasterization is disabled we do not care about any of the dynamic states,
1316 * since they are all rasterization related only. */
1317 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1320 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1321 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1323 if (!pCreateInfo
->pDepthStencilState
||
1324 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1325 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1327 if (!pCreateInfo
->pDepthStencilState
||
1328 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1329 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1330 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1331 RADV_DYNAMIC_STENCIL_REFERENCE
);
1333 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1334 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1336 if (!pCreateInfo
->pMultisampleState
||
1337 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1338 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1339 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1341 if (!pCreateInfo
->pRasterizationState
||
1342 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1343 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1344 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1346 /* TODO: blend constants & line width. */
1353 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1354 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1356 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1357 uint32_t states
= needed_states
;
1358 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1359 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1361 pipeline
->dynamic_state
= default_dynamic_state
;
1362 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1364 if (pCreateInfo
->pDynamicState
) {
1365 /* Remove all of the states that are marked as dynamic */
1366 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1367 for (uint32_t s
= 0; s
< count
; s
++)
1368 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1371 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1373 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1374 assert(pCreateInfo
->pViewportState
);
1376 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1377 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1378 typed_memcpy(dynamic
->viewport
.viewports
,
1379 pCreateInfo
->pViewportState
->pViewports
,
1380 pCreateInfo
->pViewportState
->viewportCount
);
1384 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1385 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1386 if (states
& RADV_DYNAMIC_SCISSOR
) {
1387 typed_memcpy(dynamic
->scissor
.scissors
,
1388 pCreateInfo
->pViewportState
->pScissors
,
1389 pCreateInfo
->pViewportState
->scissorCount
);
1393 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1394 assert(pCreateInfo
->pRasterizationState
);
1395 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1398 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1399 assert(pCreateInfo
->pRasterizationState
);
1400 dynamic
->depth_bias
.bias
=
1401 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1402 dynamic
->depth_bias
.clamp
=
1403 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1404 dynamic
->depth_bias
.slope
=
1405 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1408 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1410 * pColorBlendState is [...] NULL if the pipeline has rasterization
1411 * disabled or if the subpass of the render pass the pipeline is
1412 * created against does not use any color attachments.
1414 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1415 assert(pCreateInfo
->pColorBlendState
);
1416 typed_memcpy(dynamic
->blend_constants
,
1417 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1420 /* If there is no depthstencil attachment, then don't read
1421 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1422 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1423 * no need to override the depthstencil defaults in
1424 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1426 * Section 9.2 of the Vulkan 1.0.15 spec says:
1428 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1429 * disabled or if the subpass of the render pass the pipeline is created
1430 * against does not use a depth/stencil attachment.
1432 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1433 assert(pCreateInfo
->pDepthStencilState
);
1435 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1436 dynamic
->depth_bounds
.min
=
1437 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1438 dynamic
->depth_bounds
.max
=
1439 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1442 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1443 dynamic
->stencil_compare_mask
.front
=
1444 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1445 dynamic
->stencil_compare_mask
.back
=
1446 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1449 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1450 dynamic
->stencil_write_mask
.front
=
1451 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1452 dynamic
->stencil_write_mask
.back
=
1453 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1456 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1457 dynamic
->stencil_reference
.front
=
1458 pCreateInfo
->pDepthStencilState
->front
.reference
;
1459 dynamic
->stencil_reference
.back
=
1460 pCreateInfo
->pDepthStencilState
->back
.reference
;
1464 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1465 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1466 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1467 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1468 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1469 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1470 discard_rectangle_info
->pDiscardRectangles
,
1471 discard_rectangle_info
->discardRectangleCount
);
1475 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1476 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1477 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1478 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1479 /* If sampleLocationsEnable is VK_FALSE, the default sample
1480 * locations are used and the values specified in
1481 * sampleLocationsInfo are ignored.
1483 if (sample_location_info
->sampleLocationsEnable
) {
1484 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1485 &sample_location_info
->sampleLocationsInfo
;
1487 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1489 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1490 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1491 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1492 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1493 pSampleLocationsInfo
->pSampleLocations
,
1494 pSampleLocationsInfo
->sampleLocationsCount
);
1498 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1499 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1500 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1501 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1502 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1503 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1506 pipeline
->dynamic_state
.mask
= states
;
1510 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1511 const struct radv_pipeline
*pipeline
,
1513 struct radv_shader_info
*infos
,
1514 struct gfx9_gs_info
*out
)
1516 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1517 struct radv_es_output_info
*es_info
;
1518 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1519 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1521 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1522 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1523 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1525 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1526 bool uses_adjacency
;
1527 switch(key
->topology
) {
1528 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1529 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1530 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1531 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1532 uses_adjacency
= true;
1535 uses_adjacency
= false;
1539 /* All these are in dwords: */
1540 /* We can't allow using the whole LDS, because GS waves compete with
1541 * other shader stages for LDS space. */
1542 const unsigned max_lds_size
= 8 * 1024;
1543 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1544 unsigned esgs_lds_size
;
1546 /* All these are per subgroup: */
1547 const unsigned max_out_prims
= 32 * 1024;
1548 const unsigned max_es_verts
= 255;
1549 const unsigned ideal_gs_prims
= 64;
1550 unsigned max_gs_prims
, gs_prims
;
1551 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1553 if (uses_adjacency
|| gs_num_invocations
> 1)
1554 max_gs_prims
= 127 / gs_num_invocations
;
1558 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1559 * Make sure we don't go over the maximum value.
1561 if (gs_info
->gs
.vertices_out
> 0) {
1562 max_gs_prims
= MIN2(max_gs_prims
,
1564 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1566 assert(max_gs_prims
> 0);
1568 /* If the primitive has adjacency, halve the number of vertices
1569 * that will be reused in multiple primitives.
1571 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1573 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1574 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1576 /* Compute ESGS LDS size based on the worst case number of ES vertices
1577 * needed to create the target number of GS prims per subgroup.
1579 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1581 /* If total LDS usage is too big, refactor partitions based on ratio
1582 * of ESGS item sizes.
1584 if (esgs_lds_size
> max_lds_size
) {
1585 /* Our target GS Prims Per Subgroup was too large. Calculate
1586 * the maximum number of GS Prims Per Subgroup that will fit
1587 * into LDS, capped by the maximum that the hardware can support.
1589 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1591 assert(gs_prims
> 0);
1592 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1595 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1596 assert(esgs_lds_size
<= max_lds_size
);
1599 /* Now calculate remaining ESGS information. */
1601 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1603 es_verts
= max_es_verts
;
1605 /* Vertices for adjacency primitives are not always reused, so restore
1606 * it for ES_VERTS_PER_SUBGRP.
1608 min_es_verts
= gs_info
->gs
.vertices_in
;
1610 /* For normal primitives, the VGT only checks if they are past the ES
1611 * verts per subgroup after allocating a full GS primitive and if they
1612 * are, kick off a new subgroup. But if those additional ES verts are
1613 * unique (e.g. not reused) we need to make sure there is enough LDS
1614 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1616 es_verts
-= min_es_verts
- 1;
1618 uint32_t es_verts_per_subgroup
= es_verts
;
1619 uint32_t gs_prims_per_subgroup
= gs_prims
;
1620 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1621 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1622 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1623 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1624 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1625 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1626 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1627 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1628 assert(max_prims_per_subgroup
<= max_out_prims
);
1631 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1632 unsigned min_verts_per_prim
, bool use_adjacency
)
1634 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1637 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1641 radv_get_num_input_vertices(nir_shader
**nir
)
1643 if (nir
[MESA_SHADER_GEOMETRY
]) {
1644 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1646 return gs
->info
.gs
.vertices_in
;
1649 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1650 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1652 if (tes
->info
.tess
.point_mode
)
1654 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1663 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1664 struct radv_pipeline
*pipeline
,
1666 struct radv_shader_info
*infos
,
1667 struct gfx10_ngg_info
*ngg
)
1669 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1670 struct radv_es_output_info
*es_info
=
1671 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1672 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1673 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1674 unsigned min_verts_per_prim
=
1675 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1676 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1677 bool uses_adjacency
;
1678 switch(key
->topology
) {
1679 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1680 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1681 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1682 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1683 uses_adjacency
= true;
1686 uses_adjacency
= false;
1690 /* All these are in dwords: */
1691 /* We can't allow using the whole LDS, because GS waves compete with
1692 * other shader stages for LDS space.
1694 * TODO: We should really take the shader's internal LDS use into
1695 * account. The linker will fail if the size is greater than
1698 const unsigned max_lds_size
= 8 * 1024 - 768;
1699 const unsigned target_lds_size
= max_lds_size
;
1700 unsigned esvert_lds_size
= 0;
1701 unsigned gsprim_lds_size
= 0;
1703 /* All these are per subgroup: */
1704 bool max_vert_out_per_gs_instance
= false;
1705 unsigned max_esverts_base
= 256;
1706 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1708 /* Hardware has the following non-natural restrictions on the value
1709 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1711 * - at most 252 for any line input primitive type
1712 * - at most 251 for any quad input primitive type
1713 * - at most 251 for triangle strips with adjacency (this happens to
1714 * be the natural limit for triangle *lists* with adjacency)
1716 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1718 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1719 unsigned max_out_verts_per_gsprim
=
1720 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1722 if (max_out_verts_per_gsprim
<= 256) {
1723 if (max_out_verts_per_gsprim
) {
1724 max_gsprims_base
= MIN2(max_gsprims_base
,
1725 256 / max_out_verts_per_gsprim
);
1728 /* Use special multi-cycling mode in which each GS
1729 * instance gets its own subgroup. Does not work with
1731 max_vert_out_per_gs_instance
= true;
1732 max_gsprims_base
= 1;
1733 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1736 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1737 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1740 /* LDS size for passing data from GS to ES. */
1741 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1742 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1743 : &infos
[MESA_SHADER_VERTEX
].so
;
1745 if (so_info
->num_outputs
)
1746 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1748 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1749 * corresponding to the ES thread of the provoking vertex. All
1750 * ES threads load and export PrimitiveID for their thread.
1752 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1753 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1754 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1757 unsigned max_gsprims
= max_gsprims_base
;
1758 unsigned max_esverts
= max_esverts_base
;
1760 if (esvert_lds_size
)
1761 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1762 if (gsprim_lds_size
)
1763 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1765 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1766 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1767 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1769 if (esvert_lds_size
|| gsprim_lds_size
) {
1770 /* Now that we have a rough proportionality between esverts
1771 * and gsprims based on the primitive type, scale both of them
1772 * down simultaneously based on required LDS space.
1774 * We could be smarter about this if we knew how much vertex
1777 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1778 max_gsprims
* gsprim_lds_size
;
1779 if (lds_total
> target_lds_size
) {
1780 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1781 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1783 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1784 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1785 min_verts_per_prim
, uses_adjacency
);
1786 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1790 /* Round up towards full wave sizes for better ALU utilization. */
1791 if (!max_vert_out_per_gs_instance
) {
1792 unsigned orig_max_esverts
;
1793 unsigned orig_max_gsprims
;
1796 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1797 wavesize
= gs_info
->wave_size
;
1799 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1800 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1801 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1805 orig_max_esverts
= max_esverts
;
1806 orig_max_gsprims
= max_gsprims
;
1808 max_esverts
= align(max_esverts
, wavesize
);
1809 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1810 if (esvert_lds_size
)
1811 max_esverts
= MIN2(max_esverts
,
1812 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1814 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1816 max_gsprims
= align(max_gsprims
, wavesize
);
1817 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1818 if (gsprim_lds_size
)
1819 max_gsprims
= MIN2(max_gsprims
,
1820 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1822 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1823 min_verts_per_prim
, uses_adjacency
);
1824 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1825 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1828 /* Hardware restriction: minimum value of max_esverts */
1829 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1831 unsigned max_out_vertices
=
1832 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1833 gs_type
== MESA_SHADER_GEOMETRY
?
1834 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1836 assert(max_out_vertices
<= 256);
1838 unsigned prim_amp_factor
= 1;
1839 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1840 /* Number of output primitives per GS input primitive after
1842 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1845 /* The GE only checks against the maximum number of ES verts after
1846 * allocating a full GS primitive. So we need to ensure that whenever
1847 * this check passes, there is enough space for a full primitive without
1850 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1851 ngg
->max_gsprims
= max_gsprims
;
1852 ngg
->max_out_verts
= max_out_vertices
;
1853 ngg
->prim_amp_factor
= prim_amp_factor
;
1854 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1855 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1856 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1858 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1859 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1861 ngg
->vgt_esgs_ring_itemsize
= 1;
1864 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1866 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1870 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1871 const struct gfx9_gs_info
*gs
)
1873 struct radv_device
*device
= pipeline
->device
;
1874 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1875 unsigned wave_size
= 64;
1876 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1877 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1878 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1880 unsigned gs_vertex_reuse
=
1881 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1882 unsigned alignment
= 256 * num_se
;
1883 /* The maximum size is 63.999 MB per SE. */
1884 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1885 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1887 /* Calculate the minimum size. */
1888 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1889 wave_size
, alignment
);
1890 /* These are recommended sizes, not minimum sizes. */
1891 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1892 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1893 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1894 gs_info
->gs
.max_gsvs_emit_size
;
1896 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1897 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1898 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1900 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1901 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1903 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1906 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1909 /* If tessellation is all offchip and on-chip GS isn't used, this
1910 * workaround is not needed.
1914 /* SPI barrier management bug:
1915 * Make sure we have at least 4k of LDS in use to avoid the bug.
1916 * It applies to workgroup sizes of more than one wavefront.
1918 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1919 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1920 *lds_size
= MAX2(*lds_size
, 8);
1923 struct radv_shader_variant
*
1924 radv_get_shader(struct radv_pipeline
*pipeline
,
1925 gl_shader_stage stage
)
1927 if (stage
== MESA_SHADER_VERTEX
) {
1928 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1929 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1930 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1931 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1932 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1933 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1934 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1935 if (!radv_pipeline_has_tess(pipeline
))
1937 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1938 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1939 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1940 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1942 return pipeline
->shaders
[stage
];
1945 static struct radv_tessellation_state
1946 calculate_tess_state(struct radv_pipeline
*pipeline
,
1947 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1949 unsigned num_tcs_input_cp
;
1950 unsigned num_tcs_output_cp
;
1952 unsigned num_patches
;
1953 struct radv_tessellation_state tess
= {0};
1955 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1956 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1957 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1959 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1961 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1962 assert(lds_size
<= 65536);
1963 lds_size
= align(lds_size
, 512) / 512;
1965 assert(lds_size
<= 32768);
1966 lds_size
= align(lds_size
, 256) / 256;
1968 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1970 tess
.lds_size
= lds_size
;
1972 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1973 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1974 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1975 tess
.num_patches
= num_patches
;
1977 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1978 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1980 switch (tes
->info
.tes
.primitive_mode
) {
1982 type
= V_028B6C_TESS_TRIANGLE
;
1985 type
= V_028B6C_TESS_QUAD
;
1988 type
= V_028B6C_TESS_ISOLINE
;
1992 switch (tes
->info
.tes
.spacing
) {
1993 case TESS_SPACING_EQUAL
:
1994 partitioning
= V_028B6C_PART_INTEGER
;
1996 case TESS_SPACING_FRACTIONAL_ODD
:
1997 partitioning
= V_028B6C_PART_FRAC_ODD
;
1999 case TESS_SPACING_FRACTIONAL_EVEN
:
2000 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2006 bool ccw
= tes
->info
.tes
.ccw
;
2007 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2008 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2009 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2011 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2014 if (tes
->info
.tes
.point_mode
)
2015 topology
= V_028B6C_OUTPUT_POINT
;
2016 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2017 topology
= V_028B6C_OUTPUT_LINE
;
2019 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2021 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2023 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2024 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2025 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2026 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2028 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2030 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2032 tess
.tf_param
= S_028B6C_TYPE(type
) |
2033 S_028B6C_PARTITIONING(partitioning
) |
2034 S_028B6C_TOPOLOGY(topology
) |
2035 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2040 static const struct radv_prim_vertex_count prim_size_table
[] = {
2041 [V_008958_DI_PT_NONE
] = {0, 0},
2042 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2043 [V_008958_DI_PT_LINELIST
] = {2, 2},
2044 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2045 [V_008958_DI_PT_TRILIST
] = {3, 3},
2046 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2047 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2048 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2049 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2050 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2051 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2052 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2053 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2054 [V_008958_DI_PT_POLYGON
] = {3, 1},
2055 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2058 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2060 if (radv_pipeline_has_gs(pipeline
))
2061 if (radv_pipeline_has_ngg(pipeline
))
2062 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2064 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2065 else if (radv_pipeline_has_tess(pipeline
))
2066 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2068 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2072 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2074 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2075 int shader_count
= 0;
2077 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2078 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2080 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2081 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2083 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2084 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2086 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2087 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2089 if(shaders
[MESA_SHADER_VERTEX
]) {
2090 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2093 if (shader_count
> 1) {
2094 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2095 unsigned last
= ordered_shaders
[0]->info
.stage
;
2097 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2098 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2099 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2101 for (int i
= 0; i
< shader_count
; ++i
) {
2102 nir_variable_mode mask
= 0;
2104 if (ordered_shaders
[i
]->info
.stage
!= first
)
2105 mask
= mask
| nir_var_shader_in
;
2107 if (ordered_shaders
[i
]->info
.stage
!= last
)
2108 mask
= mask
| nir_var_shader_out
;
2110 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2111 radv_optimize_nir(ordered_shaders
[i
], false, false);
2115 for (int i
= 1; i
< shader_count
; ++i
) {
2116 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2117 ordered_shaders
[i
- 1]);
2119 if (nir_link_opt_varyings(ordered_shaders
[i
],
2120 ordered_shaders
[i
- 1]))
2121 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2123 nir_remove_dead_variables(ordered_shaders
[i
],
2124 nir_var_shader_out
, NULL
);
2125 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2126 nir_var_shader_in
, NULL
);
2128 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2129 ordered_shaders
[i
- 1]);
2131 nir_compact_varyings(ordered_shaders
[i
],
2132 ordered_shaders
[i
- 1], true);
2135 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2136 ac_lower_indirect_derefs(ordered_shaders
[i
],
2137 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2139 radv_optimize_nir(ordered_shaders
[i
], false, false);
2141 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2142 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2143 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2145 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2151 radv_set_linked_driver_locations(struct radv_pipeline
*pipeline
, nir_shader
**shaders
,
2152 struct radv_shader_info infos
[MESA_SHADER_STAGES
])
2154 bool has_tess
= shaders
[MESA_SHADER_TESS_CTRL
];
2155 bool has_gs
= shaders
[MESA_SHADER_GEOMETRY
];
2157 if (!has_tess
&& !has_gs
)
2160 unsigned vs_info_idx
= MESA_SHADER_VERTEX
;
2161 unsigned tes_info_idx
= MESA_SHADER_TESS_EVAL
;
2163 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2164 /* These are merged into the next stage */
2165 vs_info_idx
= has_tess
? MESA_SHADER_TESS_CTRL
: MESA_SHADER_GEOMETRY
;
2166 tes_info_idx
= has_gs
? MESA_SHADER_GEOMETRY
: MESA_SHADER_TESS_EVAL
;
2170 nir_linked_io_var_info vs2tcs
=
2171 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_TESS_CTRL
]);
2172 nir_linked_io_var_info tcs2tes
=
2173 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_CTRL
], shaders
[MESA_SHADER_TESS_EVAL
]);
2175 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2tcs
.num_linked_io_vars
;
2176 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_inputs
= vs2tcs
.num_linked_io_vars
;
2177 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_outputs
= tcs2tes
.num_linked_io_vars
;
2178 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_patch_outputs
= tcs2tes
.num_linked_patch_io_vars
;
2179 infos
[tes_info_idx
].tes
.num_linked_inputs
= tcs2tes
.num_linked_io_vars
;
2180 infos
[tes_info_idx
].tes
.num_linked_patch_inputs
= tcs2tes
.num_linked_patch_io_vars
;
2183 nir_linked_io_var_info tes2gs
=
2184 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_EVAL
], shaders
[MESA_SHADER_GEOMETRY
]);
2186 infos
[tes_info_idx
].tes
.num_linked_outputs
= tes2gs
.num_linked_io_vars
;
2187 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= tes2gs
.num_linked_io_vars
;
2189 } else if (has_gs
) {
2190 nir_linked_io_var_info vs2gs
=
2191 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_GEOMETRY
]);
2193 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2gs
.num_linked_io_vars
;
2194 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= vs2gs
.num_linked_io_vars
;
2199 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2200 uint32_t attrib_binding
)
2202 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2203 const VkVertexInputBindingDescription
*input_binding
=
2204 &input_state
->pVertexBindingDescriptions
[i
];
2206 if (input_binding
->binding
== attrib_binding
)
2207 return input_binding
->stride
;
2213 static struct radv_pipeline_key
2214 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2215 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2216 const struct radv_blend_state
*blend
,
2217 bool has_view_index
)
2219 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2220 pCreateInfo
->pVertexInputState
;
2221 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2222 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2224 struct radv_pipeline_key key
;
2225 memset(&key
, 0, sizeof(key
));
2227 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2228 key
.optimisations_disabled
= 1;
2230 key
.has_multiview_view_index
= has_view_index
;
2232 uint32_t binding_input_rate
= 0;
2233 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2234 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2235 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2236 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2237 binding_input_rate
|= 1u << binding
;
2238 instance_rate_divisors
[binding
] = 1;
2241 if (divisor_state
) {
2242 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2243 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2244 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2248 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2249 const VkVertexInputAttributeDescription
*desc
=
2250 &input_state
->pVertexAttributeDescriptions
[i
];
2251 const struct vk_format_description
*format_desc
;
2252 unsigned location
= desc
->location
;
2253 unsigned binding
= desc
->binding
;
2254 unsigned num_format
, data_format
;
2257 if (binding_input_rate
& (1u << binding
)) {
2258 key
.instance_rate_inputs
|= 1u << location
;
2259 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2262 format_desc
= vk_format_description(desc
->format
);
2263 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2265 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2266 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2268 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2269 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2270 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2271 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2273 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2274 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2275 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2278 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2279 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2280 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2282 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2283 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2284 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2286 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2287 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2288 adjust
= RADV_ALPHA_ADJUST_SINT
;
2294 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2297 switch (desc
->format
) {
2298 case VK_FORMAT_B8G8R8A8_UNORM
:
2299 case VK_FORMAT_B8G8R8A8_SNORM
:
2300 case VK_FORMAT_B8G8R8A8_USCALED
:
2301 case VK_FORMAT_B8G8R8A8_SSCALED
:
2302 case VK_FORMAT_B8G8R8A8_UINT
:
2303 case VK_FORMAT_B8G8R8A8_SINT
:
2304 case VK_FORMAT_B8G8R8A8_SRGB
:
2305 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2306 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2307 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2308 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2309 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2310 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2311 key
.vertex_post_shuffle
|= 1 << location
;
2318 const VkPipelineTessellationStateCreateInfo
*tess
=
2319 radv_pipeline_get_tessellation_state(pCreateInfo
);
2321 key
.tess_input_vertices
= tess
->patchControlPoints
;
2323 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2324 radv_pipeline_get_multisample_state(pCreateInfo
);
2325 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2326 uint32_t num_samples
= vkms
->rasterizationSamples
;
2327 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2328 key
.num_samples
= num_samples
;
2329 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2332 key
.col_format
= blend
->spi_shader_col_format
;
2333 key
.is_dual_src
= blend
->mrt0_is_dual_src
;
2334 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
) {
2335 key
.is_int8
= blend
->col_format_is_int8
;
2336 key
.is_int10
= blend
->col_format_is_int10
;
2339 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2340 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2346 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2348 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2349 bool uses_xfb
= !!xfb
;
2356 radv_fill_shader_keys(struct radv_device
*device
,
2357 struct radv_shader_variant_key
*keys
,
2358 const struct radv_pipeline_key
*key
,
2361 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2362 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2363 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2364 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2365 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2366 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2367 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2368 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2369 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2371 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2373 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2374 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2375 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2376 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2377 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2379 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2382 if (nir
[MESA_SHADER_GEOMETRY
]) {
2383 if (nir
[MESA_SHADER_TESS_CTRL
])
2384 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2386 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2389 if (device
->physical_device
->use_ngg
) {
2390 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2391 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2393 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2396 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2397 nir
[MESA_SHADER_GEOMETRY
] &&
2398 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2399 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2400 /* Fallback to the legacy path if tessellation is
2401 * enabled with extreme geometry because
2402 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2405 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2408 if (!device
->physical_device
->use_ngg_gs
) {
2409 if (nir
[MESA_SHADER_GEOMETRY
]) {
2410 if (nir
[MESA_SHADER_TESS_CTRL
])
2411 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2413 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2417 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2419 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2424 bool uses_xfb
= nir
[last_xfb_stage
] &&
2425 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2427 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2428 if (nir
[MESA_SHADER_TESS_CTRL
])
2429 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2431 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2434 /* Determine if the pipeline is eligible for the NGG passthrough
2435 * mode. It can't be enabled for geometry shaders, for NGG
2436 * streamout or for vertex shaders that export the primitive ID
2437 * (this is checked later because we don't have the info here.)
2439 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2440 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2441 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2442 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2443 } else if (nir
[MESA_SHADER_VERTEX
] &&
2444 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2445 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2450 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2451 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2453 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2454 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2455 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2456 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2457 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2458 keys
[MESA_SHADER_FRAGMENT
].fs
.is_dual_src
= key
->is_dual_src
;
2460 if (nir
[MESA_SHADER_COMPUTE
]) {
2461 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2466 radv_get_wave_size(struct radv_device
*device
,
2467 const VkPipelineShaderStageCreateInfo
*pStage
,
2468 gl_shader_stage stage
,
2469 const struct radv_shader_variant_key
*key
)
2471 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2473 else if (stage
== MESA_SHADER_COMPUTE
) {
2474 if (key
->cs
.subgroup_size
) {
2475 /* Return the required subgroup size if specified. */
2476 return key
->cs
.subgroup_size
;
2478 return device
->physical_device
->cs_wave_size
;
2480 else if (stage
== MESA_SHADER_FRAGMENT
)
2481 return device
->physical_device
->ps_wave_size
;
2483 return device
->physical_device
->ge_wave_size
;
2487 radv_get_ballot_bit_size(struct radv_device
*device
,
2488 const VkPipelineShaderStageCreateInfo
*pStage
,
2489 gl_shader_stage stage
,
2490 const struct radv_shader_variant_key
*key
)
2492 if (stage
== MESA_SHADER_COMPUTE
&& key
->cs
.subgroup_size
)
2493 return key
->cs
.subgroup_size
;
2498 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2499 const VkPipelineShaderStageCreateInfo
**pStages
,
2500 struct radv_shader_variant_key
*keys
,
2501 struct radv_shader_info
*infos
,
2504 unsigned active_stages
= 0;
2505 unsigned filled_stages
= 0;
2507 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2509 active_stages
|= (1 << i
);
2512 if (nir
[MESA_SHADER_FRAGMENT
]) {
2513 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2514 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2516 &keys
[MESA_SHADER_FRAGMENT
],
2517 &infos
[MESA_SHADER_FRAGMENT
],
2518 pipeline
->device
->physical_device
->use_llvm
);
2520 /* TODO: These are no longer used as keys we should refactor this */
2521 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2522 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2523 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2524 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2525 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2526 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2527 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_viewport_index
=
2528 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2529 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2530 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2531 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2532 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2533 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2534 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2535 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_viewport_index
=
2536 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2538 /* NGG passthrough mode can't be enabled for vertex shaders
2539 * that export the primitive ID.
2541 * TODO: I should really refactor the keys logic.
2543 if (nir
[MESA_SHADER_VERTEX
] &&
2544 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2545 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2548 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2551 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2552 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_inputs_read
=
2553 nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
;
2554 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_patch_inputs_read
=
2555 nir
[MESA_SHADER_TESS_EVAL
]->info
.patch_inputs_read
;
2558 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2559 nir
[MESA_SHADER_TESS_CTRL
]) {
2560 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2561 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2562 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2564 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2566 for (int i
= 0; i
< 2; i
++) {
2567 radv_nir_shader_info_pass(combined_nir
[i
],
2568 pipeline
->layout
, &key
,
2569 &infos
[MESA_SHADER_TESS_CTRL
],
2570 pipeline
->device
->physical_device
->use_llvm
);
2573 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2574 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2575 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2576 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2578 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2579 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2582 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2583 nir
[MESA_SHADER_GEOMETRY
]) {
2584 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2585 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2587 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2589 for (int i
= 0; i
< 2; i
++) {
2590 radv_nir_shader_info_pass(combined_nir
[i
],
2593 &infos
[MESA_SHADER_GEOMETRY
],
2594 pipeline
->device
->physical_device
->use_llvm
);
2597 filled_stages
|= (1 << pre_stage
);
2598 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2601 active_stages
^= filled_stages
;
2602 while (active_stages
) {
2603 int i
= u_bit_scan(&active_stages
);
2605 if (i
== MESA_SHADER_TESS_CTRL
) {
2606 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2607 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2610 if (i
== MESA_SHADER_TESS_EVAL
) {
2611 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2612 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2613 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2614 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2617 radv_nir_shader_info_init(&infos
[i
]);
2618 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2619 &keys
[i
], &infos
[i
], pipeline
->device
->physical_device
->use_llvm
);
2622 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2624 infos
[i
].wave_size
=
2625 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2627 infos
[i
].ballot_bit_size
=
2628 radv_get_ballot_bit_size(pipeline
->device
,
2636 merge_tess_info(struct shader_info
*tes_info
,
2637 const struct shader_info
*tcs_info
)
2639 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2641 * "PointMode. Controls generation of points rather than triangles
2642 * or lines. This functionality defaults to disabled, and is
2643 * enabled if either shader stage includes the execution mode.
2645 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2646 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2647 * and OutputVertices, it says:
2649 * "One mode must be set in at least one of the tessellation
2652 * So, the fields can be set in either the TCS or TES, but they must
2653 * agree if set in both. Our backend looks at TES, so bitwise-or in
2654 * the values from the TCS.
2656 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2657 tes_info
->tess
.tcs_vertices_out
== 0 ||
2658 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2659 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2661 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2662 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2663 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2664 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2666 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2667 tes_info
->tess
.primitive_mode
== 0 ||
2668 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2669 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2670 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2671 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2675 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2680 if (ext
->pPipelineCreationFeedback
) {
2681 ext
->pPipelineCreationFeedback
->flags
= 0;
2682 ext
->pPipelineCreationFeedback
->duration
= 0;
2685 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2686 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2687 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2692 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2697 feedback
->duration
-= radv_get_current_time();
2698 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2702 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2707 feedback
->duration
+= radv_get_current_time();
2708 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2709 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2712 VkResult
radv_create_shaders(struct radv_pipeline
*pipeline
,
2713 struct radv_device
*device
,
2714 struct radv_pipeline_cache
*cache
,
2715 const struct radv_pipeline_key
*key
,
2716 const VkPipelineShaderStageCreateInfo
**pStages
,
2717 const VkPipelineCreateFlags flags
,
2718 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2719 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2721 struct radv_shader_module fs_m
= {0};
2722 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2723 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2724 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2725 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2726 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2727 unsigned char hash
[20], gs_copy_hash
[20];
2728 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2729 bool keep_statistic_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR
) ||
2730 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) ||
2731 device
->keep_shader_info
;
2733 radv_start_feedback(pipeline_feedback
);
2735 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2737 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2738 if (modules
[i
]->nir
)
2739 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2740 strlen(modules
[i
]->nir
->info
.name
),
2743 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2747 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2748 memcpy(gs_copy_hash
, hash
, 20);
2749 gs_copy_hash
[0] ^= 1;
2751 bool found_in_application_cache
= true;
2752 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
&& !keep_statistic_info
) {
2753 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2754 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2755 &found_in_application_cache
);
2756 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2759 if (!keep_executable_info
&& !keep_statistic_info
&&
2760 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2761 &found_in_application_cache
) &&
2762 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2763 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2767 if (flags
& VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT
) {
2768 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2769 return VK_PIPELINE_COMPILE_REQUIRED_EXT
;
2772 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2774 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2775 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2776 fs_m
.nir
= fs_b
.shader
;
2777 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2780 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2781 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2782 unsigned subgroup_size
= 64, ballot_bit_size
= 64;
2787 radv_start_feedback(stage_feedbacks
[i
]);
2789 if (key
->compute_subgroup_size
) {
2790 /* Only compute shaders currently support requiring a
2791 * specific subgroup size.
2793 assert(i
== MESA_SHADER_COMPUTE
);
2794 subgroup_size
= key
->compute_subgroup_size
;
2795 ballot_bit_size
= key
->compute_subgroup_size
;
2798 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2799 stage
? stage
->pName
: "main", i
,
2800 stage
? stage
->pSpecializationInfo
: NULL
,
2801 flags
, pipeline
->layout
,
2802 subgroup_size
, ballot_bit_size
);
2804 /* We don't want to alter meta shaders IR directly so clone it
2807 if (nir
[i
]->info
.name
) {
2808 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2811 radv_stop_feedback(stage_feedbacks
[i
], false);
2814 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2815 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2816 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2819 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2820 radv_link_shaders(pipeline
, nir
);
2822 radv_set_linked_driver_locations(pipeline
, nir
, infos
);
2824 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2826 /* do this again since information such as outputs_read can be out-of-date */
2827 nir_shader_gather_info(nir
[i
], nir_shader_get_entrypoint(nir
[i
]));
2829 if (device
->physical_device
->use_llvm
) {
2830 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2832 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2833 nir_lower_non_uniform_ubo_access
|
2834 nir_lower_non_uniform_ssbo_access
|
2835 nir_lower_non_uniform_texture_access
|
2836 nir_lower_non_uniform_image_access
);
2841 if (nir
[MESA_SHADER_FRAGMENT
])
2842 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2844 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2845 if (radv_can_dump_shader(device
, modules
[i
], false))
2846 nir_print_shader(nir
[i
], stderr
);
2849 radv_fill_shader_keys(device
, keys
, key
, nir
);
2851 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2853 if ((nir
[MESA_SHADER_VERTEX
] &&
2854 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2855 (nir
[MESA_SHADER_TESS_EVAL
] &&
2856 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2857 struct gfx10_ngg_info
*ngg_info
;
2859 if (nir
[MESA_SHADER_GEOMETRY
])
2860 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2861 else if (nir
[MESA_SHADER_TESS_CTRL
])
2862 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2864 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2866 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2867 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2868 struct gfx9_gs_info
*gs_info
=
2869 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2871 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2874 if(modules
[MESA_SHADER_GEOMETRY
]) {
2875 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2876 if (!pipeline
->gs_copy_shader
&&
2877 !radv_pipeline_has_ngg(pipeline
)) {
2878 struct radv_shader_info info
= {};
2879 struct radv_shader_variant_key key
= {};
2881 key
.has_multiview_view_index
=
2882 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2884 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2885 pipeline
->layout
, &key
,
2886 &info
, pipeline
->device
->physical_device
->use_llvm
);
2887 info
.wave_size
= 64; /* Wave32 not supported. */
2888 info
.ballot_bit_size
= 64;
2890 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2891 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2892 &gs_copy_binary
, keep_executable_info
, keep_statistic_info
,
2893 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2896 if (!keep_executable_info
&& !keep_statistic_info
&& pipeline
->gs_copy_shader
) {
2897 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2898 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2900 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2901 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2903 radv_pipeline_cache_insert_shaders(device
, cache
,
2908 free(gs_copy_binary
);
2911 if (nir
[MESA_SHADER_FRAGMENT
]) {
2912 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2913 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2915 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2916 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2917 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2918 infos
+ MESA_SHADER_FRAGMENT
,
2919 keep_executable_info
, keep_statistic_info
,
2920 &binaries
[MESA_SHADER_FRAGMENT
]);
2922 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2926 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2927 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2928 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2929 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2930 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2932 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2934 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2936 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2937 keep_statistic_info
, &binaries
[MESA_SHADER_TESS_CTRL
]);
2939 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2941 modules
[MESA_SHADER_VERTEX
] = NULL
;
2942 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2943 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2946 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2947 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2948 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2949 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2951 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2953 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2955 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2956 keep_statistic_info
, &binaries
[MESA_SHADER_GEOMETRY
]);
2958 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2960 modules
[pre_stage
] = NULL
;
2963 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2964 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2965 if (i
== MESA_SHADER_TESS_CTRL
) {
2966 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2968 if (i
== MESA_SHADER_TESS_EVAL
) {
2969 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2970 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2973 radv_start_feedback(stage_feedbacks
[i
]);
2975 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2977 keys
+ i
, infos
+ i
, keep_executable_info
,
2978 keep_statistic_info
, &binaries
[i
]);
2980 radv_stop_feedback(stage_feedbacks
[i
], false);
2984 if (!keep_executable_info
&& !keep_statistic_info
) {
2985 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2989 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2992 ralloc_free(nir
[i
]);
2994 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2995 radv_shader_dump_stats(device
,
2996 pipeline
->shaders
[i
],
3002 ralloc_free(fs_m
.nir
);
3004 radv_stop_feedback(pipeline_feedback
, false);
3009 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
3010 gl_shader_stage stage
, enum chip_class chip_class
)
3012 bool has_gs
= radv_pipeline_has_gs(pipeline
);
3013 bool has_tess
= radv_pipeline_has_tess(pipeline
);
3014 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
3017 case MESA_SHADER_FRAGMENT
:
3018 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
3019 case MESA_SHADER_VERTEX
:
3021 if (chip_class
>= GFX10
) {
3022 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3023 } else if (chip_class
== GFX9
) {
3024 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3026 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3032 if (chip_class
>= GFX10
) {
3033 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3035 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3040 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3042 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3043 case MESA_SHADER_GEOMETRY
:
3044 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3045 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3046 case MESA_SHADER_COMPUTE
:
3047 return R_00B900_COMPUTE_USER_DATA_0
;
3048 case MESA_SHADER_TESS_CTRL
:
3049 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3050 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3051 case MESA_SHADER_TESS_EVAL
:
3053 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3054 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3055 } else if (has_ngg
) {
3056 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3058 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3061 unreachable("unknown shader");
3065 struct radv_bin_size_entry
{
3071 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3073 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3077 /* One shader engine */
3083 { UINT_MAX
, { 0, 0}},
3086 /* Two shader engines */
3092 { UINT_MAX
, { 0, 0}},
3095 /* Four shader engines */
3100 { UINT_MAX
, { 0, 0}},
3106 /* One shader engine */
3112 { UINT_MAX
, { 0, 0}},
3115 /* Two shader engines */
3121 { UINT_MAX
, { 0, 0}},
3124 /* Four shader engines */
3131 { UINT_MAX
, { 0, 0}},
3137 /* One shader engine */
3144 { UINT_MAX
, { 0, 0}},
3147 /* Two shader engines */
3155 { UINT_MAX
, { 0, 0}},
3158 /* Four shader engines */
3166 { UINT_MAX
, { 0, 0}},
3170 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3174 // One shader engine
3181 { UINT_MAX
, { 0, 0}},
3184 // Two shader engines
3192 { UINT_MAX
, { 0, 0}},
3195 // Four shader engines
3203 { UINT_MAX
, { 0, 0}},
3209 // One shader engine
3217 { UINT_MAX
, { 0, 0}},
3220 // Two shader engines
3229 { UINT_MAX
, { 0, 0}},
3232 // Four shader engines
3241 { UINT_MAX
, { 0, 0}},
3247 // One shader engine
3255 { UINT_MAX
, { 0, 0}},
3258 // Two shader engines
3267 { UINT_MAX
, { 0, 0}},
3270 // Four shader engines
3278 { UINT_MAX
, { 0, 0}},
3283 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3284 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3285 VkExtent2D extent
= {512, 512};
3287 unsigned log_num_rb_per_se
=
3288 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3289 pipeline
->device
->physical_device
->rad_info
.max_se
);
3290 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3292 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3293 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3294 unsigned effective_samples
= total_samples
;
3295 unsigned color_bytes_per_pixel
= 0;
3297 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3298 radv_pipeline_get_color_blend_state(pCreateInfo
);
3300 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3301 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3304 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3307 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3308 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3311 /* MSAA images typically don't use all samples all the time. */
3312 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3313 effective_samples
= 2;
3314 color_bytes_per_pixel
*= effective_samples
;
3317 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3318 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3321 extent
= color_entry
->extent
;
3323 if (subpass
->depth_stencil_attachment
) {
3324 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3326 /* Coefficients taken from AMDVLK */
3327 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3328 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3329 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3331 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3332 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3335 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3336 extent
= ds_entry
->extent
;
3343 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3345 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3346 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3347 VkExtent2D extent
= {512, 512};
3349 const unsigned db_tag_size
= 64;
3350 const unsigned db_tag_count
= 312;
3351 const unsigned color_tag_size
= 1024;
3352 const unsigned color_tag_count
= 31;
3353 const unsigned fmask_tag_size
= 256;
3354 const unsigned fmask_tag_count
= 44;
3356 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3357 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3359 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3360 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3361 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3363 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3364 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3366 unsigned color_bytes_per_pixel
= 0;
3367 unsigned fmask_bytes_per_pixel
= 0;
3369 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3370 radv_pipeline_get_color_blend_state(pCreateInfo
);
3372 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3373 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3376 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3379 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3380 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3382 if (total_samples
> 1) {
3383 assert(samples_log
<= 3);
3384 const unsigned fmask_array
[] = {0, 1, 1, 4};
3385 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3389 color_bytes_per_pixel
*= total_samples
;
3391 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3393 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3394 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3395 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3397 if (fmask_bytes_per_pixel
) {
3398 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3400 const VkExtent2D fmask_extent
= (VkExtent2D
){
3401 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3402 .height
= 1ull << (color_pixel_count_log
/ 2)
3405 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3406 extent
= fmask_extent
;
3409 if (subpass
->depth_stencil_attachment
) {
3410 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3412 /* Coefficients taken from AMDVLK */
3413 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3414 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3415 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3417 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3419 const VkExtent2D db_extent
= (VkExtent2D
){
3420 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3421 .height
= 1ull << (color_pixel_count_log
/ 2)
3424 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3428 extent
.width
= MAX2(extent
.width
, 128);
3429 extent
.height
= MAX2(extent
.width
, 64);
3435 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3436 struct radv_pipeline
*pipeline
,
3437 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3439 uint32_t pa_sc_binner_cntl_0
=
3440 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3441 S_028C44_DISABLE_START_OF_PRIM(1);
3442 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3444 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3445 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3446 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3447 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3448 radv_pipeline_get_color_blend_state(pCreateInfo
);
3449 unsigned min_bytes_per_pixel
= 0;
3452 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3453 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3456 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3459 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3460 unsigned bytes
= vk_format_get_blocksize(format
);
3461 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3462 min_bytes_per_pixel
= bytes
;
3466 pa_sc_binner_cntl_0
=
3467 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3468 S_028C44_BIN_SIZE_X(0) |
3469 S_028C44_BIN_SIZE_Y(0) |
3470 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3471 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3472 S_028C44_DISABLE_START_OF_PRIM(1);
3475 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3476 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3479 struct radv_binning_settings
3480 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3482 struct radv_binning_settings settings
;
3483 if (pdev
->rad_info
.has_dedicated_vram
) {
3484 if (pdev
->rad_info
.num_render_backends
> 4) {
3485 settings
.context_states_per_bin
= 1;
3486 settings
.persistent_states_per_bin
= 1;
3488 settings
.context_states_per_bin
= 3;
3489 settings
.persistent_states_per_bin
= 8;
3491 settings
.fpovs_per_batch
= 63;
3493 /* The context states are affected by the scissor bug. */
3494 settings
.context_states_per_bin
= 6;
3495 /* 32 causes hangs for RAVEN. */
3496 settings
.persistent_states_per_bin
= 16;
3497 settings
.fpovs_per_batch
= 63;
3500 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3501 settings
.context_states_per_bin
= 1;
3507 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3508 struct radv_pipeline
*pipeline
,
3509 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3510 const struct radv_blend_state
*blend
)
3512 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3515 VkExtent2D bin_size
;
3516 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3517 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3518 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3519 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3521 unreachable("Unhandled generation for binning bin size calculation");
3523 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3524 struct radv_binning_settings settings
=
3525 radv_get_binning_settings(pipeline
->device
->physical_device
);
3527 bool disable_start_of_prim
= true;
3528 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3530 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3532 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3533 !ps
->info
.ps
.can_discard
&&
3534 !ps
->info
.ps
.writes_memory
&&
3535 blend
->cb_target_enabled_4bit
) {
3536 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3537 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3540 const uint32_t pa_sc_binner_cntl_0
=
3541 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3542 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3543 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3544 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3545 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3546 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3547 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3548 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3549 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3550 S_028C44_OPTIMAL_BIN_SELECTION(1);
3552 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3553 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3555 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3560 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3561 struct radv_pipeline
*pipeline
,
3562 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3563 const struct radv_graphics_pipeline_create_info
*extra
)
3565 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3566 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3567 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3568 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3569 struct radv_render_pass_attachment
*attachment
= NULL
;
3570 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3571 uint32_t db_render_control
= 0, db_render_override2
= 0;
3572 uint32_t db_render_override
= 0;
3574 if (subpass
->depth_stencil_attachment
)
3575 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3577 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3578 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3580 if (vkds
&& has_depth_attachment
) {
3581 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3582 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3583 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3584 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3586 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3587 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3589 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
)
3590 db_render_override2
|= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3593 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3594 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3595 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3596 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3597 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3598 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3600 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3601 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3602 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3603 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3606 if (attachment
&& extra
) {
3607 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3608 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3610 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->resummarize_enable
);
3611 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->depth_compress_disable
);
3612 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->stencil_compress_disable
);
3613 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3614 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3617 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3618 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3620 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3621 ps
->info
.ps
.writes_z
) {
3622 /* From VK_EXT_depth_range_unrestricted spec:
3624 * "The behavior described in Primitive Clipping still applies.
3625 * If depth clamping is disabled the depth values are still
3626 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3627 * depth clamping is enabled the above equation is ignored and
3628 * the depth values are instead clamped to the VkViewport
3629 * minDepth and maxDepth values, which in the case of this
3630 * extension can be outside of the 0.0 to 1.0 range."
3632 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3635 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3636 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3638 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3639 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3640 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3644 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3645 struct radv_pipeline
*pipeline
,
3646 const struct radv_blend_state
*blend
)
3648 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3649 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3651 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3652 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3654 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3656 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3657 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3660 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3662 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3663 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3665 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3666 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3669 static const VkConservativeRasterizationModeEXT
3670 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3672 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3673 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3675 if (!conservative_raster
)
3676 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3677 return conservative_raster
->conservativeRasterizationMode
;
3681 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3682 struct radv_pipeline
*pipeline
,
3683 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3685 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3686 const VkConservativeRasterizationModeEXT mode
=
3687 radv_get_conservative_raster_mode(vkraster
);
3688 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3689 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3691 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3692 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3693 if (depth_clip_state
) {
3694 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3697 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3698 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3699 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3700 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3701 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3702 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3704 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3705 S_0286D4_FLAT_SHADE_ENA(1) |
3706 S_0286D4_PNT_SPRITE_ENA(1) |
3707 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3708 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3709 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3710 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3711 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3713 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3714 S_028BE4_PIX_CENTER(1) | // TODO verify
3715 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3716 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3718 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3719 S_028814_FACE(vkraster
->frontFace
) |
3720 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3721 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3722 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3723 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3724 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3725 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3726 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3727 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3729 /* Conservative rasterization. */
3730 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3731 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3733 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3734 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3735 S_028804_OVERRASTERIZATION_AMOUNT(4);
3737 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3738 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3739 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3741 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3742 pa_sc_conservative_rast
|=
3743 S_028C4C_OVER_RAST_ENABLE(1) |
3744 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3745 S_028C4C_UNDER_RAST_ENABLE(0) |
3746 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3747 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3749 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3750 pa_sc_conservative_rast
|=
3751 S_028C4C_OVER_RAST_ENABLE(0) |
3752 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3753 S_028C4C_UNDER_RAST_ENABLE(1) |
3754 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3755 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3759 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3760 pa_sc_conservative_rast
);
3765 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3766 struct radv_pipeline
*pipeline
)
3768 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3770 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3771 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3772 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3774 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3775 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3776 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3777 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3778 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3780 /* The exclusion bits can be set to improve rasterization efficiency
3781 * if no sample lies on the pixel boundary (-8 sample offset). It's
3782 * currently always TRUE because the driver doesn't support 16 samples.
3784 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3785 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3786 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3787 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3789 /* GFX9: Flush DFSM when the AA mode changes. */
3790 if (pipeline
->device
->dfsm_allowed
) {
3791 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3792 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3797 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3798 struct radv_pipeline
*pipeline
)
3800 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3801 const struct radv_shader_variant
*vs
=
3802 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3803 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3804 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3805 unsigned vgt_primitiveid_en
= 0;
3806 uint32_t vgt_gs_mode
= 0;
3808 if (radv_pipeline_has_ngg(pipeline
))
3811 if (radv_pipeline_has_gs(pipeline
)) {
3812 const struct radv_shader_variant
*gs
=
3813 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3815 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3816 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3817 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3818 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3819 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3822 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3823 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3827 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3828 struct radeon_cmdbuf
*cs
,
3829 struct radv_pipeline
*pipeline
,
3830 struct radv_shader_variant
*shader
)
3832 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3834 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3835 radeon_emit(cs
, va
>> 8);
3836 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3837 radeon_emit(cs
, shader
->config
.rsrc1
);
3838 radeon_emit(cs
, shader
->config
.rsrc2
);
3840 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3841 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3842 clip_dist_mask
= outinfo
->clip_dist_mask
;
3843 cull_dist_mask
= outinfo
->cull_dist_mask
;
3844 total_mask
= clip_dist_mask
| cull_dist_mask
;
3845 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3846 outinfo
->writes_layer
||
3847 outinfo
->writes_viewport_index
;
3848 unsigned spi_vs_out_config
, nparams
;
3850 /* VS is required to export at least one param. */
3851 nparams
= MAX2(outinfo
->param_exports
, 1);
3852 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3854 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3855 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3858 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3860 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3861 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3862 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3863 V_02870C_SPI_SHADER_4COMP
:
3864 V_02870C_SPI_SHADER_NONE
) |
3865 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3866 V_02870C_SPI_SHADER_4COMP
:
3867 V_02870C_SPI_SHADER_NONE
) |
3868 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3869 V_02870C_SPI_SHADER_4COMP
:
3870 V_02870C_SPI_SHADER_NONE
));
3872 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3873 S_028818_VTX_W0_FMT(1) |
3874 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3875 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3876 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3878 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3879 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3880 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3881 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3882 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3883 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3884 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3885 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3886 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3887 cull_dist_mask
<< 8 |
3890 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3891 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3892 outinfo
->writes_viewport_index
);
3896 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3897 struct radv_pipeline
*pipeline
,
3898 struct radv_shader_variant
*shader
)
3900 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3902 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3903 radeon_emit(cs
, va
>> 8);
3904 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3905 radeon_emit(cs
, shader
->config
.rsrc1
);
3906 radeon_emit(cs
, shader
->config
.rsrc2
);
3910 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3911 struct radv_pipeline
*pipeline
,
3912 struct radv_shader_variant
*shader
,
3913 const struct radv_tessellation_state
*tess
)
3915 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3916 uint32_t rsrc2
= shader
->config
.rsrc2
;
3918 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3919 radeon_emit(cs
, va
>> 8);
3920 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3922 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3923 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3924 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3925 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3927 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3928 radeon_emit(cs
, shader
->config
.rsrc1
);
3929 radeon_emit(cs
, rsrc2
);
3933 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3934 struct radeon_cmdbuf
*cs
,
3935 struct radv_pipeline
*pipeline
,
3936 struct radv_shader_variant
*shader
)
3938 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3939 gl_shader_stage es_type
=
3940 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3941 struct radv_shader_variant
*es
=
3942 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3943 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3945 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3946 radeon_emit(cs
, va
>> 8);
3947 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3948 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3949 radeon_emit(cs
, shader
->config
.rsrc1
);
3950 radeon_emit(cs
, shader
->config
.rsrc2
);
3952 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3953 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3954 clip_dist_mask
= outinfo
->clip_dist_mask
;
3955 cull_dist_mask
= outinfo
->cull_dist_mask
;
3956 total_mask
= clip_dist_mask
| cull_dist_mask
;
3957 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3958 outinfo
->writes_layer
||
3959 outinfo
->writes_viewport_index
;
3960 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3961 (es
&& es
->info
.uses_prim_id
);
3962 bool break_wave_at_eoi
= false;
3966 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3967 struct radv_shader_variant
*gs
=
3968 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3970 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3971 break_wave_at_eoi
= true;
3974 nparams
= MAX2(outinfo
->param_exports
, 1);
3975 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3976 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3977 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3979 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3980 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3981 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3982 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3983 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3984 V_02870C_SPI_SHADER_4COMP
:
3985 V_02870C_SPI_SHADER_NONE
) |
3986 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3987 V_02870C_SPI_SHADER_4COMP
:
3988 V_02870C_SPI_SHADER_NONE
) |
3989 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3990 V_02870C_SPI_SHADER_4COMP
:
3991 V_02870C_SPI_SHADER_NONE
));
3993 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3994 S_028818_VTX_W0_FMT(1) |
3995 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3996 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3997 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3998 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3999 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
4000 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
4001 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
4002 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
4003 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
4004 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
4005 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
4006 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
4007 cull_dist_mask
<< 8 |
4010 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
4011 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
4012 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
4014 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4015 ngg_state
->vgt_esgs_ring_itemsize
);
4017 /* NGG specific registers. */
4018 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4019 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
4021 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4022 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
4023 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
4024 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
4025 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
4026 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
4027 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4028 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4029 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4030 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4031 S_028B90_CNT(gs_num_invocations
) |
4032 S_028B90_ENABLE(gs_num_invocations
> 1) |
4033 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4035 /* User edge flags are set by the pos exports. If user edge flags are
4036 * not used, we must use hw-generated edge flags and pass them via
4037 * the prim export to prevent drawing lines on internal edges of
4038 * decomposed primitives (such as quads) with polygon mode = lines.
4040 * TODO: We should combine hw-generated edge flags with user edge
4041 * flags in the shader.
4043 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4044 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4045 !radv_pipeline_has_gs(pipeline
)) |
4046 /* Reuse for NGG. */
4047 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
? 30 : 0));
4049 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4050 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4051 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4053 /* Bug workaround for a possible hang with non-tessellation cases.
4054 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4056 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4058 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
4059 !radv_pipeline_has_tess(pipeline
) &&
4060 ngg_state
->hw_max_esverts
!= 256) {
4061 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4063 if (ngg_state
->hw_max_esverts
> 5) {
4064 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4068 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4072 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4073 struct radv_pipeline
*pipeline
,
4074 struct radv_shader_variant
*shader
,
4075 const struct radv_tessellation_state
*tess
)
4077 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4079 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4080 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4082 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4083 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
4085 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
4088 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4089 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4090 radeon_emit(cs
, va
>> 8);
4091 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4093 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4094 radeon_emit(cs
, va
>> 8);
4095 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4098 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4099 radeon_emit(cs
, shader
->config
.rsrc1
);
4100 radeon_emit(cs
, hs_rsrc2
);
4102 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4103 radeon_emit(cs
, va
>> 8);
4104 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4105 radeon_emit(cs
, shader
->config
.rsrc1
);
4106 radeon_emit(cs
, shader
->config
.rsrc2
);
4111 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4112 struct radeon_cmdbuf
*cs
,
4113 struct radv_pipeline
*pipeline
,
4114 const struct radv_tessellation_state
*tess
)
4116 struct radv_shader_variant
*vs
;
4118 /* Skip shaders merged into HS/GS */
4119 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4123 if (vs
->info
.vs
.as_ls
)
4124 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4125 else if (vs
->info
.vs
.as_es
)
4126 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4127 else if (vs
->info
.is_ngg
)
4128 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4130 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4134 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4135 struct radeon_cmdbuf
*cs
,
4136 struct radv_pipeline
*pipeline
,
4137 const struct radv_tessellation_state
*tess
)
4139 if (!radv_pipeline_has_tess(pipeline
))
4142 struct radv_shader_variant
*tes
, *tcs
;
4144 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4145 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4148 if (tes
->info
.is_ngg
) {
4149 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4150 } else if (tes
->info
.tes
.as_es
)
4151 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4153 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4156 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4158 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4161 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4162 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4163 tess
->ls_hs_config
);
4165 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4166 tess
->ls_hs_config
);
4168 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4169 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4170 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4171 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4172 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4173 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4178 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4179 struct radeon_cmdbuf
*cs
,
4180 struct radv_pipeline
*pipeline
,
4181 struct radv_shader_variant
*gs
)
4183 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4184 unsigned gs_max_out_vertices
;
4185 uint8_t *num_components
;
4190 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4191 max_stream
= gs
->info
.gs
.max_stream
;
4192 num_components
= gs
->info
.gs
.num_stream_output_components
;
4194 offset
= num_components
[0] * gs_max_out_vertices
;
4196 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4197 radeon_emit(ctx_cs
, offset
);
4198 if (max_stream
>= 1)
4199 offset
+= num_components
[1] * gs_max_out_vertices
;
4200 radeon_emit(ctx_cs
, offset
);
4201 if (max_stream
>= 2)
4202 offset
+= num_components
[2] * gs_max_out_vertices
;
4203 radeon_emit(ctx_cs
, offset
);
4204 if (max_stream
>= 3)
4205 offset
+= num_components
[3] * gs_max_out_vertices
;
4206 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4208 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4209 radeon_emit(ctx_cs
, num_components
[0]);
4210 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4211 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4212 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4214 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4215 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4216 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4217 S_028B90_ENABLE(gs_num_invocations
> 0));
4219 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4220 gs_state
->vgt_esgs_ring_itemsize
);
4222 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4224 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4225 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4226 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4227 radeon_emit(cs
, va
>> 8);
4228 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4230 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4231 radeon_emit(cs
, va
>> 8);
4232 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4235 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4236 radeon_emit(cs
, gs
->config
.rsrc1
);
4237 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4239 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4240 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4242 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4243 radeon_emit(cs
, va
>> 8);
4244 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4245 radeon_emit(cs
, gs
->config
.rsrc1
);
4246 radeon_emit(cs
, gs
->config
.rsrc2
);
4249 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4253 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4254 struct radeon_cmdbuf
*cs
,
4255 struct radv_pipeline
*pipeline
)
4257 struct radv_shader_variant
*gs
;
4259 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4263 if (gs
->info
.is_ngg
)
4264 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4266 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4268 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4269 gs
->info
.gs
.vertices_out
);
4272 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4273 bool explicit, bool float16
)
4275 uint32_t ps_input_cntl
;
4276 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4277 ps_input_cntl
= S_028644_OFFSET(offset
);
4278 if (flat_shade
|| explicit)
4279 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4281 /* Force parameter cache to be read in passthrough
4284 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4287 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4288 S_028644_ATTR0_VALID(1);
4291 /* The input is a DEFAULT_VAL constant. */
4292 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4293 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4294 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4295 ps_input_cntl
= S_028644_OFFSET(0x20) |
4296 S_028644_DEFAULT_VAL(offset
);
4298 return ps_input_cntl
;
4302 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4303 struct radv_pipeline
*pipeline
)
4305 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4306 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4307 uint32_t ps_input_cntl
[32];
4309 unsigned ps_offset
= 0;
4311 if (ps
->info
.ps
.prim_id_input
) {
4312 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4313 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4314 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4319 if (ps
->info
.ps
.layer_input
||
4320 ps
->info
.needs_multiview_view_index
) {
4321 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4322 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4323 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4325 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4329 if (ps
->info
.ps
.viewport_index_input
) {
4330 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VIEWPORT
];
4331 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4332 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4334 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4338 if (ps
->info
.ps
.has_pcoord
) {
4340 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4341 ps_input_cntl
[ps_offset
] = val
;
4345 if (ps
->info
.ps
.num_input_clips_culls
) {
4348 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4349 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4350 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4354 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4355 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4356 ps
->info
.ps
.num_input_clips_culls
> 4) {
4357 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4362 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4367 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4370 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4371 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4372 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4377 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4378 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4379 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4381 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4386 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4387 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4388 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4394 radv_compute_db_shader_control(const struct radv_device
*device
,
4395 const struct radv_pipeline
*pipeline
,
4396 const struct radv_shader_variant
*ps
)
4398 unsigned conservative_z_export
= V_02880C_EXPORT_ANY_Z
;
4400 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4401 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4403 z_order
= V_02880C_LATE_Z
;
4405 if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_GREATER
)
4406 conservative_z_export
= V_02880C_EXPORT_GREATER_THAN_Z
;
4407 else if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_LESS
)
4408 conservative_z_export
= V_02880C_EXPORT_LESS_THAN_Z
;
4410 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4411 !device
->physical_device
->rad_info
.rbplus_allowed
;
4413 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4414 * but this appears to break Project Cars (DXVK). See
4415 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4417 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4419 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4420 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4421 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4422 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4423 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export
) |
4424 S_02880C_Z_ORDER(z_order
) |
4425 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4426 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4427 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4428 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4429 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4433 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4434 struct radeon_cmdbuf
*cs
,
4435 struct radv_pipeline
*pipeline
)
4437 struct radv_shader_variant
*ps
;
4439 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4441 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4442 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4444 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4445 radeon_emit(cs
, va
>> 8);
4446 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4447 radeon_emit(cs
, ps
->config
.rsrc1
);
4448 radeon_emit(cs
, ps
->config
.rsrc2
);
4450 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4451 radv_compute_db_shader_control(pipeline
->device
,
4454 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4455 ps
->config
.spi_ps_input_ena
);
4457 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4458 ps
->config
.spi_ps_input_addr
);
4460 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4461 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4462 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4464 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4466 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4467 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4468 ps
->info
.ps
.writes_stencil
,
4469 ps
->info
.ps
.writes_sample_mask
));
4471 if (pipeline
->device
->dfsm_allowed
) {
4472 /* optimise this? */
4473 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4474 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4479 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4480 struct radv_pipeline
*pipeline
)
4482 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4483 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4486 unsigned vtx_reuse_depth
= 30;
4487 if (radv_pipeline_has_tess(pipeline
) &&
4488 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4489 vtx_reuse_depth
= 14;
4491 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4492 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4496 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4498 uint32_t stages
= 0;
4499 if (radv_pipeline_has_tess(pipeline
)) {
4500 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4501 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4503 if (radv_pipeline_has_gs(pipeline
))
4504 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4506 else if (radv_pipeline_has_ngg(pipeline
))
4507 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4509 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4510 } else if (radv_pipeline_has_gs(pipeline
)) {
4511 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4513 } else if (radv_pipeline_has_ngg(pipeline
)) {
4514 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4517 if (radv_pipeline_has_ngg(pipeline
)) {
4518 stages
|= S_028B54_PRIMGEN_EN(1);
4519 if (pipeline
->streamout_shader
)
4520 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4521 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4522 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4523 } else if (radv_pipeline_has_gs(pipeline
)) {
4524 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4527 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4528 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4530 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4531 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4533 if (radv_pipeline_has_tess(pipeline
))
4534 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4536 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4537 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4538 if (pipeline
->gs_copy_shader
)
4539 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4540 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4541 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4542 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4543 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4545 if (radv_pipeline_has_ngg(pipeline
))
4548 /* legacy GS only supports Wave64 */
4549 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4550 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4551 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4558 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4560 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4561 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4563 if (!discard_rectangle_info
)
4568 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4569 /* Interpret i as a bitmask, and then set the bit in the mask if
4570 * that combination of rectangles in which the pixel is contained
4571 * should pass the cliprect test. */
4572 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4574 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4578 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4589 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4590 struct radv_pipeline
*pipeline
,
4591 const struct radv_tessellation_state
*tess
)
4593 bool break_wave_at_eoi
= false;
4594 unsigned primgroup_size
;
4595 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4597 if (radv_pipeline_has_tess(pipeline
)) {
4598 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4599 } else if (radv_pipeline_has_gs(pipeline
)) {
4600 const struct gfx9_gs_info
*gs_state
=
4601 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4602 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4603 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4605 primgroup_size
= 128; /* recommended without a GS and tess */
4608 if (radv_pipeline_has_tess(pipeline
)) {
4609 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4610 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4611 break_wave_at_eoi
= true;
4614 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4615 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4616 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4617 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4618 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4622 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4623 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4624 const struct radv_graphics_pipeline_create_info
*extra
,
4625 const struct radv_blend_state
*blend
,
4626 const struct radv_tessellation_state
*tess
,
4627 unsigned prim
, unsigned gs_out
)
4629 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4630 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4633 ctx_cs
->max_dw
= 256;
4634 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4635 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4637 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4638 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4639 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4640 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4641 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4642 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4643 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4644 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4645 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4646 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4647 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4648 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4650 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4651 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4653 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4655 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4656 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4657 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4659 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4661 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4663 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4665 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4667 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4668 assert(cs
->cdw
<= cs
->max_dw
);
4671 static struct radv_ia_multi_vgt_param_helpers
4672 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4673 const struct radv_tessellation_state
*tess
,
4676 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4677 const struct radv_device
*device
= pipeline
->device
;
4679 if (radv_pipeline_has_tess(pipeline
))
4680 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4681 else if (radv_pipeline_has_gs(pipeline
))
4682 ia_multi_vgt_param
.primgroup_size
= 64;
4684 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4686 /* GS requirement. */
4687 ia_multi_vgt_param
.partial_es_wave
= false;
4688 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4689 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4690 ia_multi_vgt_param
.partial_es_wave
= true;
4692 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4693 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4694 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4695 * 4 shader engines. Set 1 to pass the assertion below.
4696 * The other cases are hardware requirements. */
4697 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4698 prim
== V_008958_DI_PT_POLYGON
||
4699 prim
== V_008958_DI_PT_LINELOOP
||
4700 prim
== V_008958_DI_PT_TRIFAN
||
4701 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4702 (pipeline
->graphics
.prim_restart_enable
&&
4703 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4704 (prim
!= V_008958_DI_PT_POINTLIST
&&
4705 prim
!= V_008958_DI_PT_LINESTRIP
))))
4706 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4709 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4710 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4711 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4712 if (radv_pipeline_has_gs(pipeline
) &&
4713 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4714 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4715 if (radv_pipeline_has_tess(pipeline
)) {
4716 /* SWITCH_ON_EOI must be set if PrimID is used. */
4717 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4718 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4719 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4722 ia_multi_vgt_param
.partial_vs_wave
= false;
4723 if (radv_pipeline_has_tess(pipeline
)) {
4724 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4725 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4726 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4727 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4728 radv_pipeline_has_gs(pipeline
))
4729 ia_multi_vgt_param
.partial_vs_wave
= true;
4730 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4731 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4732 if (radv_pipeline_has_gs(pipeline
)) {
4733 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4734 ia_multi_vgt_param
.partial_es_wave
= true;
4736 ia_multi_vgt_param
.partial_vs_wave
= true;
4741 /* Workaround for a VGT hang when strip primitive types are used with
4742 * primitive restart.
4744 if (pipeline
->graphics
.prim_restart_enable
&&
4745 (prim
== V_008958_DI_PT_LINESTRIP
||
4746 prim
== V_008958_DI_PT_TRISTRIP
||
4747 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4748 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4749 ia_multi_vgt_param
.partial_vs_wave
= true;
4752 if (radv_pipeline_has_gs(pipeline
)) {
4753 /* On these chips there is the possibility of a hang if the
4754 * pipeline uses a GS and partial_vs_wave is not set.
4756 * This mostly does not hit 4-SE chips, as those typically set
4757 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4758 * with GS due to another workaround.
4760 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4762 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4763 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4764 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4765 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4766 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4767 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4768 ia_multi_vgt_param
.partial_vs_wave
= true;
4772 ia_multi_vgt_param
.base
=
4773 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4774 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4775 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4776 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4777 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4779 return ia_multi_vgt_param
;
4784 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4785 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4787 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4788 pCreateInfo
->pVertexInputState
;
4789 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4791 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4792 const VkVertexInputAttributeDescription
*desc
=
4793 &vi_info
->pVertexAttributeDescriptions
[i
];
4794 unsigned loc
= desc
->location
;
4795 const struct vk_format_description
*format_desc
;
4797 format_desc
= vk_format_description(desc
->format
);
4799 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4802 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4803 const VkVertexInputBindingDescription
*desc
=
4804 &vi_info
->pVertexBindingDescriptions
[i
];
4806 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4807 pipeline
->num_vertex_bindings
=
4808 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4812 static struct radv_shader_variant
*
4813 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4817 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4818 struct radv_shader_variant
*shader
=
4819 radv_get_shader(pipeline
, i
);
4821 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4829 radv_secure_compile(struct radv_pipeline
*pipeline
,
4830 struct radv_device
*device
,
4831 const struct radv_pipeline_key
*key
,
4832 const VkPipelineShaderStageCreateInfo
**pStages
,
4833 const VkPipelineCreateFlags flags
,
4834 unsigned num_stages
)
4836 uint8_t allowed_pipeline_hashes
[2][20];
4837 radv_hash_shaders(allowed_pipeline_hashes
[0], pStages
,
4838 pipeline
->layout
, key
, get_hash_flags(device
));
4840 /* Generate the GC copy hash */
4841 memcpy(allowed_pipeline_hashes
[1], allowed_pipeline_hashes
[0], 20);
4842 allowed_pipeline_hashes
[1][0] ^= 1;
4844 uint8_t allowed_hashes
[2][20];
4845 for (unsigned i
= 0; i
< 2; ++i
) {
4846 disk_cache_compute_key(device
->physical_device
->disk_cache
,
4847 allowed_pipeline_hashes
[i
], 20,
4851 /* Do an early exit if all cache entries are already there. */
4852 bool may_need_copy_shader
= pStages
[MESA_SHADER_GEOMETRY
];
4853 void *main_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[0], NULL
);
4854 void *copy_entry
= NULL
;
4855 if (may_need_copy_shader
)
4856 copy_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[1], NULL
);
4858 bool has_all_cache_entries
= main_entry
&& (!may_need_copy_shader
|| copy_entry
);
4862 if(has_all_cache_entries
)
4865 unsigned process
= 0;
4866 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
4868 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4869 if (device
->sc_state
->secure_compile_thread_counter
< sc_threads
) {
4870 device
->sc_state
->secure_compile_thread_counter
++;
4871 for (unsigned i
= 0; i
< sc_threads
; i
++) {
4872 if (!device
->sc_state
->secure_compile_processes
[i
].in_use
) {
4873 device
->sc_state
->secure_compile_processes
[i
].in_use
= true;
4878 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4881 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4884 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
4885 int fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
;
4887 /* Fork a copy of the slim untainted secure compile process */
4888 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_FORK_DEVICE
;
4889 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4891 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true) ||
4892 sc_type
!= RADV_SC_TYPE_INIT_SUCCESS
)
4893 return VK_ERROR_DEVICE_LOST
;
4895 fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_server
;
4896 fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_client
;
4898 /* Write pipeline / shader module out to secure process via pipe */
4899 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE
;
4900 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4902 /* Write pipeline layout out to secure process */
4903 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
4904 write(fd_secure_input
, layout
, sizeof(struct radv_pipeline_layout
));
4905 write(fd_secure_input
, &layout
->num_sets
, sizeof(uint32_t));
4906 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
4907 write(fd_secure_input
, &layout
->set
[set
].layout
->layout_size
, sizeof(uint32_t));
4908 write(fd_secure_input
, layout
->set
[set
].layout
, layout
->set
[set
].layout
->layout_size
);
4911 /* Write pipeline key out to secure process */
4912 write(fd_secure_input
, key
, sizeof(struct radv_pipeline_key
));
4914 /* Write pipeline create flags out to secure process */
4915 write(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
));
4917 /* Write stage and shader information out to secure process */
4918 write(fd_secure_input
, &num_stages
, sizeof(uint32_t));
4919 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4923 /* Write stage out to secure process */
4924 gl_shader_stage stage
= ffs(pStages
[i
]->stage
) - 1;
4925 write(fd_secure_input
, &stage
, sizeof(gl_shader_stage
));
4927 /* Write entry point name out to secure process */
4928 size_t name_size
= strlen(pStages
[i
]->pName
) + 1;
4929 write(fd_secure_input
, &name_size
, sizeof(size_t));
4930 write(fd_secure_input
, pStages
[i
]->pName
, name_size
);
4932 /* Write shader module out to secure process */
4933 struct radv_shader_module
*module
= radv_shader_module_from_handle(pStages
[i
]->module
);
4934 assert(!module
->nir
);
4935 size_t module_size
= sizeof(struct radv_shader_module
) + module
->size
;
4936 write(fd_secure_input
, &module_size
, sizeof(size_t));
4937 write(fd_secure_input
, module
, module_size
);
4939 /* Write specialization info out to secure process */
4940 const VkSpecializationInfo
*specInfo
= pStages
[i
]->pSpecializationInfo
;
4941 bool has_spec_info
= specInfo
? true : false;
4942 write(fd_secure_input
, &has_spec_info
, sizeof(bool));
4944 write(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t));
4945 write(fd_secure_input
, specInfo
->pData
, specInfo
->dataSize
);
4947 write(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t));
4948 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++)
4949 write(fd_secure_input
, &specInfo
->pMapEntries
[j
], sizeof(VkSpecializationMapEntry
));
4953 /* Read the data returned from the secure process */
4954 while (sc_type
!= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
) {
4955 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true))
4956 return VK_ERROR_DEVICE_LOST
;
4958 if (sc_type
== RADV_SC_TYPE_WRITE_DISK_CACHE
) {
4959 assert(device
->physical_device
->disk_cache
);
4961 uint8_t disk_sha1
[20];
4962 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4963 return VK_ERROR_DEVICE_LOST
;
4965 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4966 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4967 return VK_ERROR_DEVICE_LOST
;
4969 uint32_t entry_size
;
4970 if (!radv_sc_read(fd_secure_output
, &entry_size
, sizeof(uint32_t), true))
4971 return VK_ERROR_DEVICE_LOST
;
4973 struct cache_entry
*entry
= malloc(entry_size
);
4974 if (!radv_sc_read(fd_secure_output
, entry
, entry_size
, true))
4975 return VK_ERROR_DEVICE_LOST
;
4977 disk_cache_put(device
->physical_device
->disk_cache
,
4978 disk_sha1
, entry
, entry_size
,
4982 } else if (sc_type
== RADV_SC_TYPE_READ_DISK_CACHE
) {
4983 uint8_t disk_sha1
[20];
4984 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4985 return VK_ERROR_DEVICE_LOST
;
4987 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4988 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4989 return VK_ERROR_DEVICE_LOST
;
4992 struct cache_entry
*entry
= (struct cache_entry
*)
4993 disk_cache_get(device
->physical_device
->disk_cache
,
4996 uint8_t found
= entry
? 1 : 0;
4997 write(fd_secure_input
, &found
, sizeof(uint8_t));
5000 write(fd_secure_input
, &size
, sizeof(size_t));
5001 write(fd_secure_input
, entry
, size
);
5008 sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
5009 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
5011 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
5012 device
->sc_state
->secure_compile_thread_counter
--;
5013 device
->sc_state
->secure_compile_processes
[process
].in_use
= false;
5014 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
5020 radv_pipeline_init(struct radv_pipeline
*pipeline
,
5021 struct radv_device
*device
,
5022 struct radv_pipeline_cache
*cache
,
5023 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5024 const struct radv_graphics_pipeline_create_info
*extra
)
5027 bool has_view_index
= false;
5029 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
5030 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
5031 if (subpass
->view_mask
)
5032 has_view_index
= true;
5034 pipeline
->device
= device
;
5035 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5036 assert(pipeline
->layout
);
5038 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
5040 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5041 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5042 radv_init_feedback(creation_feedback
);
5044 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5046 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5047 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5048 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
5049 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
5050 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
5051 if(creation_feedback
)
5052 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
5055 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
5056 if (radv_device_use_secure_compile(device
->instance
)) {
5057 return radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
->stageCount
);
5059 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5060 pCreateInfo
->flags
, pipeline_feedback
,
5062 if (result
!= VK_SUCCESS
)
5066 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
5067 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
5069 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
5071 pipeline
->graphics
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
5072 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
5074 if (radv_pipeline_has_gs(pipeline
)) {
5075 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
5076 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5077 } else if (radv_pipeline_has_tess(pipeline
)) {
5078 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
5079 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
5081 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
5082 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5084 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
5086 if (extra
&& extra
->use_rectlist
) {
5087 prim
= V_008958_DI_PT_RECTLIST
;
5088 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5089 pipeline
->graphics
.can_use_guardband
= true;
5090 if (radv_pipeline_has_ngg(pipeline
))
5091 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
5093 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
5094 /* prim vertex count will need TESS changes */
5095 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
5097 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
5099 /* Ensure that some export memory is always allocated, for two reasons:
5101 * 1) Correctness: The hardware ignores the EXEC mask if no export
5102 * memory is allocated, so KILL and alpha test do not work correctly
5104 * 2) Performance: Every shader needs at least a NULL export, even when
5105 * it writes no color/depth output. The NULL export instruction
5106 * stalls without this setting.
5108 * Don't add this to CB_SHADER_MASK.
5110 * GFX10 supports pixel shaders without exports by setting both the
5111 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5112 * instructions if any are present.
5114 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
5115 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
5116 ps
->info
.ps
.can_discard
) &&
5117 !blend
.spi_shader_col_format
) {
5118 if (!ps
->info
.ps
.writes_z
&&
5119 !ps
->info
.ps
.writes_stencil
&&
5120 !ps
->info
.ps
.writes_sample_mask
)
5121 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
5124 blend
.cb_shader_mask
= ps
->info
.ps
.cb_shader_mask
;
5127 (extra
->custom_blend_mode
== V_028808_CB_ELIMINATE_FAST_CLEAR
||
5128 extra
->custom_blend_mode
== V_028808_CB_FMASK_DECOMPRESS
||
5129 extra
->custom_blend_mode
== V_028808_CB_DCC_DECOMPRESS
||
5130 extra
->custom_blend_mode
== V_028808_CB_RESOLVE
)) {
5131 /* According to the CB spec states, CB_SHADER_MASK should be
5132 * set to enable writes to all four channels of MRT0.
5134 blend
.cb_shader_mask
= 0xf;
5137 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5138 if (pipeline
->shaders
[i
]) {
5139 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
5143 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
5144 struct radv_shader_variant
*gs
=
5145 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
5147 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
5150 struct radv_tessellation_state tess
= {0};
5151 if (radv_pipeline_has_tess(pipeline
)) {
5152 if (prim
== V_008958_DI_PT_PATCH
) {
5153 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
5154 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
5156 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
5159 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
5161 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
5163 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
5164 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
5166 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
5167 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
5168 if (loc
->sgpr_idx
!= -1) {
5169 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
5170 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
5171 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
5172 pipeline
->graphics
.vtx_emit_num
= 3;
5174 pipeline
->graphics
.vtx_emit_num
= 2;
5177 /* Find the last vertex shader stage that eventually uses streamout. */
5178 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
5180 result
= radv_pipeline_scratch_init(device
, pipeline
);
5181 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
5187 radv_graphics_pipeline_create(
5189 VkPipelineCache _cache
,
5190 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5191 const struct radv_graphics_pipeline_create_info
*extra
,
5192 const VkAllocationCallbacks
*pAllocator
,
5193 VkPipeline
*pPipeline
)
5195 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5196 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5197 struct radv_pipeline
*pipeline
;
5200 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5201 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5202 if (pipeline
== NULL
)
5203 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5205 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5206 VK_OBJECT_TYPE_PIPELINE
);
5208 result
= radv_pipeline_init(pipeline
, device
, cache
,
5209 pCreateInfo
, extra
);
5210 if (result
!= VK_SUCCESS
) {
5211 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5215 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5220 VkResult
radv_CreateGraphicsPipelines(
5222 VkPipelineCache pipelineCache
,
5224 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
5225 const VkAllocationCallbacks
* pAllocator
,
5226 VkPipeline
* pPipelines
)
5228 VkResult result
= VK_SUCCESS
;
5231 for (; i
< count
; i
++) {
5233 r
= radv_graphics_pipeline_create(_device
,
5236 NULL
, pAllocator
, &pPipelines
[i
]);
5237 if (r
!= VK_SUCCESS
) {
5239 pPipelines
[i
] = VK_NULL_HANDLE
;
5241 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5246 for (; i
< count
; ++i
)
5247 pPipelines
[i
] = VK_NULL_HANDLE
;
5254 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5256 struct radv_shader_variant
*compute_shader
;
5257 struct radv_device
*device
= pipeline
->device
;
5258 unsigned threads_per_threadgroup
;
5259 unsigned threadgroups_per_cu
= 1;
5260 unsigned waves_per_threadgroup
;
5261 unsigned max_waves_per_sh
= 0;
5264 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5265 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5267 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5268 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5270 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5271 radeon_emit(&pipeline
->cs
, va
>> 8);
5272 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5274 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5275 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5276 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5277 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5278 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5281 /* Calculate best compute resource limits. */
5282 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5283 compute_shader
->info
.cs
.block_size
[1] *
5284 compute_shader
->info
.cs
.block_size
[2];
5285 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5286 compute_shader
->info
.wave_size
);
5288 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5289 waves_per_threadgroup
== 1)
5290 threadgroups_per_cu
= 2;
5292 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5293 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5294 waves_per_threadgroup
,
5296 threadgroups_per_cu
));
5298 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5299 radeon_emit(&pipeline
->cs
,
5300 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5301 radeon_emit(&pipeline
->cs
,
5302 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5303 radeon_emit(&pipeline
->cs
,
5304 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5306 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5309 static struct radv_pipeline_key
5310 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5311 const VkComputePipelineCreateInfo
*pCreateInfo
)
5313 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5314 struct radv_pipeline_key key
;
5315 memset(&key
, 0, sizeof(key
));
5317 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5318 key
.optimisations_disabled
= 1;
5320 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5321 vk_find_struct_const(stage
->pNext
,
5322 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5324 if (subgroup_size
) {
5325 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5326 subgroup_size
->requiredSubgroupSize
== 64);
5327 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5333 static VkResult
radv_compute_pipeline_create(
5335 VkPipelineCache _cache
,
5336 const VkComputePipelineCreateInfo
* pCreateInfo
,
5337 const VkAllocationCallbacks
* pAllocator
,
5338 VkPipeline
* pPipeline
)
5340 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5341 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5342 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5343 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5344 struct radv_pipeline
*pipeline
;
5347 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5348 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5349 if (pipeline
== NULL
)
5350 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5352 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5353 VK_OBJECT_TYPE_PIPELINE
);
5355 pipeline
->device
= device
;
5356 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5357 assert(pipeline
->layout
);
5359 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5360 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5361 radv_init_feedback(creation_feedback
);
5363 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5364 if (creation_feedback
)
5365 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5367 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5369 struct radv_pipeline_key key
=
5370 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5372 if (radv_device_use_secure_compile(device
->instance
)) {
5373 result
= radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, 1);
5374 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5378 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5379 pCreateInfo
->flags
, pipeline_feedback
,
5381 if (result
!= VK_SUCCESS
) {
5382 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5387 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5388 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5389 result
= radv_pipeline_scratch_init(device
, pipeline
);
5390 if (result
!= VK_SUCCESS
) {
5391 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5395 radv_compute_generate_pm4(pipeline
);
5397 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5402 VkResult
radv_CreateComputePipelines(
5404 VkPipelineCache pipelineCache
,
5406 const VkComputePipelineCreateInfo
* pCreateInfos
,
5407 const VkAllocationCallbacks
* pAllocator
,
5408 VkPipeline
* pPipelines
)
5410 VkResult result
= VK_SUCCESS
;
5413 for (; i
< count
; i
++) {
5415 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5417 pAllocator
, &pPipelines
[i
]);
5418 if (r
!= VK_SUCCESS
) {
5420 pPipelines
[i
] = VK_NULL_HANDLE
;
5422 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5427 for (; i
< count
; ++i
)
5428 pPipelines
[i
] = VK_NULL_HANDLE
;
5434 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5437 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5438 if (!pipeline
->shaders
[i
])
5441 if (i
== MESA_SHADER_GEOMETRY
&&
5442 !radv_pipeline_has_ngg(pipeline
)) {
5452 static struct radv_shader_variant
*
5453 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5455 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5456 if (!pipeline
->shaders
[i
])
5460 return pipeline
->shaders
[i
];
5465 if (i
== MESA_SHADER_GEOMETRY
&&
5466 !radv_pipeline_has_ngg(pipeline
)) {
5469 return pipeline
->gs_copy_shader
;
5479 /* Basically strlcpy (which does not exist on linux) specialized for
5481 static void desc_copy(char *desc
, const char *src
) {
5482 int len
= strlen(src
);
5483 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5484 memcpy(desc
, src
, len
);
5485 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5488 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5490 const VkPipelineInfoKHR
* pPipelineInfo
,
5491 uint32_t* pExecutableCount
,
5492 VkPipelineExecutablePropertiesKHR
* pProperties
)
5494 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5495 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5498 *pExecutableCount
= total_count
;
5502 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5503 for (unsigned i
= 0, executable_idx
= 0;
5504 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5505 if (!pipeline
->shaders
[i
])
5507 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5508 const char *name
= NULL
;
5509 const char *description
= NULL
;
5511 case MESA_SHADER_VERTEX
:
5512 name
= "Vertex Shader";
5513 description
= "Vulkan Vertex Shader";
5515 case MESA_SHADER_TESS_CTRL
:
5516 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5517 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5518 name
= "Vertex + Tessellation Control Shaders";
5519 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5521 name
= "Tessellation Control Shader";
5522 description
= "Vulkan Tessellation Control Shader";
5525 case MESA_SHADER_TESS_EVAL
:
5526 name
= "Tessellation Evaluation Shader";
5527 description
= "Vulkan Tessellation Evaluation Shader";
5529 case MESA_SHADER_GEOMETRY
:
5530 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5531 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5532 name
= "Tessellation Evaluation + Geometry Shaders";
5533 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5534 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5535 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5536 name
= "Vertex + Geometry Shader";
5537 description
= "Combined Vulkan Vertex and Geometry Shaders";
5539 name
= "Geometry Shader";
5540 description
= "Vulkan Geometry Shader";
5543 case MESA_SHADER_FRAGMENT
:
5544 name
= "Fragment Shader";
5545 description
= "Vulkan Fragment Shader";
5547 case MESA_SHADER_COMPUTE
:
5548 name
= "Compute Shader";
5549 description
= "Vulkan Compute Shader";
5553 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5554 desc_copy(pProperties
[executable_idx
].name
, name
);
5555 desc_copy(pProperties
[executable_idx
].description
, description
);
5558 if (i
== MESA_SHADER_GEOMETRY
&&
5559 !radv_pipeline_has_ngg(pipeline
)) {
5560 assert(pipeline
->gs_copy_shader
);
5561 if (executable_idx
>= count
)
5564 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5565 pProperties
[executable_idx
].subgroupSize
= 64;
5566 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5567 desc_copy(pProperties
[executable_idx
].description
,
5568 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5574 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5575 *pExecutableCount
= count
;
5579 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5581 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5582 uint32_t* pStatisticCount
,
5583 VkPipelineExecutableStatisticKHR
* pStatistics
)
5585 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5586 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5587 gl_shader_stage stage
;
5588 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5590 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5591 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5592 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5594 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5595 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5596 VkResult result
= VK_SUCCESS
;
5599 desc_copy(s
->name
, "SGPRs");
5600 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5601 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5602 s
->value
.u64
= shader
->config
.num_sgprs
;
5607 desc_copy(s
->name
, "VGPRs");
5608 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5609 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5610 s
->value
.u64
= shader
->config
.num_vgprs
;
5615 desc_copy(s
->name
, "Spilled SGPRs");
5616 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5617 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5618 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5623 desc_copy(s
->name
, "Spilled VGPRs");
5624 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5625 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5626 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5631 desc_copy(s
->name
, "PrivMem VGPRs");
5632 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5633 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5634 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5639 desc_copy(s
->name
, "Code size");
5640 desc_copy(s
->description
, "Code size in bytes");
5641 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5642 s
->value
.u64
= shader
->exec_size
;
5647 desc_copy(s
->name
, "LDS size");
5648 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5649 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5650 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5655 desc_copy(s
->name
, "Scratch size");
5656 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5657 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5658 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5663 desc_copy(s
->name
, "Subgroups per SIMD");
5664 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5665 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5666 s
->value
.u64
= max_waves
;
5670 if (shader
->statistics
) {
5671 for (unsigned i
= 0; i
< shader
->statistics
->count
; i
++) {
5672 struct radv_compiler_statistic_info
*info
= &shader
->statistics
->infos
[i
];
5673 uint32_t value
= shader
->statistics
->values
[i
];
5675 desc_copy(s
->name
, info
->name
);
5676 desc_copy(s
->description
, info
->desc
);
5677 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5678 s
->value
.u64
= value
;
5685 *pStatisticCount
= s
- pStatistics
;
5687 *pStatisticCount
= end
- pStatistics
;
5688 result
= VK_INCOMPLETE
;
5690 *pStatisticCount
= s
- pStatistics
;
5696 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5698 size_t total_size
= strlen(src
) + 1;
5701 *data_size
= total_size
;
5705 size_t size
= MIN2(total_size
, *data_size
);
5707 memcpy(data
, src
, size
);
5709 *((char*)data
+ size
- 1) = 0;
5710 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5713 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5715 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5716 uint32_t* pInternalRepresentationCount
,
5717 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5719 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5720 gl_shader_stage stage
;
5721 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5723 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5724 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5725 VkResult result
= VK_SUCCESS
;
5729 desc_copy(p
->name
, "NIR Shader(s)");
5730 desc_copy(p
->description
, "The optimized NIR shader(s)");
5731 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5732 result
= VK_INCOMPLETE
;
5739 if (pipeline
->device
->physical_device
->use_llvm
) {
5740 desc_copy(p
->name
, "LLVM IR");
5741 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5743 desc_copy(p
->name
, "ACO IR");
5744 desc_copy(p
->description
, "The ACO IR after some optimizations");
5746 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5747 result
= VK_INCOMPLETE
;
5754 desc_copy(p
->name
, "Assembly");
5755 desc_copy(p
->description
, "Final Assembly");
5756 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5757 result
= VK_INCOMPLETE
;
5761 if (!pInternalRepresentations
)
5762 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5764 result
= VK_INCOMPLETE
;
5765 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5767 *pInternalRepresentationCount
= p
- pInternalRepresentations
;