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31bdc8c46437cd48ae9dee1823053f84794d63c5
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_private.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34
35 #include <llvm-c/Core.h>
36 #include <llvm-c/TargetMachine.h>
37
38 #include "sid.h"
39 #include "gfx9d.h"
40 #include "r600d_common.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_nir_to_llvm.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 void radv_shader_variant_destroy(struct radv_device *device,
49 struct radv_shader_variant *variant);
50
51 static const struct nir_shader_compiler_options nir_options = {
52 .vertex_id_zero_based = true,
53 .lower_scmp = true,
54 .lower_flrp32 = true,
55 .lower_fsat = true,
56 .lower_fdiv = true,
57 .lower_sub = true,
58 .lower_pack_snorm_2x16 = true,
59 .lower_pack_snorm_4x8 = true,
60 .lower_pack_unorm_2x16 = true,
61 .lower_pack_unorm_4x8 = true,
62 .lower_unpack_snorm_2x16 = true,
63 .lower_unpack_snorm_4x8 = true,
64 .lower_unpack_unorm_2x16 = true,
65 .lower_unpack_unorm_4x8 = true,
66 .lower_extract_byte = true,
67 .lower_extract_word = true,
68 .max_unroll_iterations = 32
69 };
70
71 VkResult radv_CreateShaderModule(
72 VkDevice _device,
73 const VkShaderModuleCreateInfo* pCreateInfo,
74 const VkAllocationCallbacks* pAllocator,
75 VkShaderModule* pShaderModule)
76 {
77 RADV_FROM_HANDLE(radv_device, device, _device);
78 struct radv_shader_module *module;
79
80 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
81 assert(pCreateInfo->flags == 0);
82
83 module = vk_alloc2(&device->alloc, pAllocator,
84 sizeof(*module) + pCreateInfo->codeSize, 8,
85 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
86 if (module == NULL)
87 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
88
89 module->nir = NULL;
90 module->size = pCreateInfo->codeSize;
91 memcpy(module->data, pCreateInfo->pCode, module->size);
92
93 _mesa_sha1_compute(module->data, module->size, module->sha1);
94
95 *pShaderModule = radv_shader_module_to_handle(module);
96
97 return VK_SUCCESS;
98 }
99
100 void radv_DestroyShaderModule(
101 VkDevice _device,
102 VkShaderModule _module,
103 const VkAllocationCallbacks* pAllocator)
104 {
105 RADV_FROM_HANDLE(radv_device, device, _device);
106 RADV_FROM_HANDLE(radv_shader_module, module, _module);
107
108 if (!module)
109 return;
110
111 vk_free2(&device->alloc, pAllocator, module);
112 }
113
114
115 static void
116 radv_pipeline_destroy(struct radv_device *device,
117 struct radv_pipeline *pipeline,
118 const VkAllocationCallbacks* allocator)
119 {
120 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
121 if (pipeline->shaders[i])
122 radv_shader_variant_destroy(device, pipeline->shaders[i]);
123
124 if (pipeline->gs_copy_shader)
125 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
126
127 vk_free2(&device->alloc, allocator, pipeline);
128 }
129
130 void radv_DestroyPipeline(
131 VkDevice _device,
132 VkPipeline _pipeline,
133 const VkAllocationCallbacks* pAllocator)
134 {
135 RADV_FROM_HANDLE(radv_device, device, _device);
136 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
137
138 if (!_pipeline)
139 return;
140
141 radv_pipeline_destroy(device, pipeline, pAllocator);
142 }
143
144
145 static void
146 radv_optimize_nir(struct nir_shader *shader)
147 {
148 bool progress;
149
150 do {
151 progress = false;
152
153 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
154 NIR_PASS_V(shader, nir_lower_64bit_pack);
155 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
156 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
157
158 NIR_PASS(progress, shader, nir_copy_prop);
159 NIR_PASS(progress, shader, nir_opt_remove_phis);
160 NIR_PASS(progress, shader, nir_opt_dce);
161 if (nir_opt_trivial_continues(shader)) {
162 progress = true;
163 NIR_PASS(progress, shader, nir_copy_prop);
164 NIR_PASS(progress, shader, nir_opt_dce);
165 }
166 NIR_PASS(progress, shader, nir_opt_if);
167 NIR_PASS(progress, shader, nir_opt_dead_cf);
168 NIR_PASS(progress, shader, nir_opt_cse);
169 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
170 NIR_PASS(progress, shader, nir_opt_algebraic);
171 NIR_PASS(progress, shader, nir_opt_constant_folding);
172 NIR_PASS(progress, shader, nir_opt_undef);
173 NIR_PASS(progress, shader, nir_opt_conditional_discard);
174 if (shader->options->max_unroll_iterations) {
175 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
176 }
177 } while (progress);
178 }
179
180 static nir_shader *
181 radv_shader_compile_to_nir(struct radv_device *device,
182 struct radv_shader_module *module,
183 const char *entrypoint_name,
184 gl_shader_stage stage,
185 const VkSpecializationInfo *spec_info,
186 bool dump)
187 {
188 if (strcmp(entrypoint_name, "main") != 0) {
189 radv_finishme("Multiple shaders per module not really supported");
190 }
191
192 nir_shader *nir;
193 nir_function *entry_point;
194 if (module->nir) {
195 /* Some things such as our meta clear/blit code will give us a NIR
196 * shader directly. In that case, we just ignore the SPIR-V entirely
197 * and just use the NIR shader */
198 nir = module->nir;
199 nir->options = &nir_options;
200 nir_validate_shader(nir);
201
202 assert(exec_list_length(&nir->functions) == 1);
203 struct exec_node *node = exec_list_get_head(&nir->functions);
204 entry_point = exec_node_data(nir_function, node, node);
205 } else {
206 uint32_t *spirv = (uint32_t *) module->data;
207 assert(module->size % 4 == 0);
208
209 uint32_t num_spec_entries = 0;
210 struct nir_spirv_specialization *spec_entries = NULL;
211 if (spec_info && spec_info->mapEntryCount > 0) {
212 num_spec_entries = spec_info->mapEntryCount;
213 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
214 for (uint32_t i = 0; i < num_spec_entries; i++) {
215 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
216 const void *data = spec_info->pData + entry.offset;
217 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
218
219 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
220 if (spec_info->dataSize == 8)
221 spec_entries[i].data64 = *(const uint64_t *)data;
222 else
223 spec_entries[i].data32 = *(const uint32_t *)data;
224 }
225 }
226 const struct nir_spirv_supported_extensions supported_ext = {
227 .draw_parameters = true,
228 .float64 = true,
229 .image_read_without_format = true,
230 .image_write_without_format = true,
231 .tessellation = true,
232 .int64 = true,
233 .variable_pointers = true,
234 };
235 entry_point = spirv_to_nir(spirv, module->size / 4,
236 spec_entries, num_spec_entries,
237 stage, entrypoint_name, &supported_ext, &nir_options);
238 nir = entry_point->shader;
239 assert(nir->stage == stage);
240 nir_validate_shader(nir);
241
242 free(spec_entries);
243
244 /* We have to lower away local constant initializers right before we
245 * inline functions. That way they get properly initialized at the top
246 * of the function and not at the top of its caller.
247 */
248 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
249 NIR_PASS_V(nir, nir_lower_returns);
250 NIR_PASS_V(nir, nir_inline_functions);
251
252 /* Pick off the single entrypoint that we want */
253 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
254 if (func != entry_point)
255 exec_node_remove(&func->node);
256 }
257 assert(exec_list_length(&nir->functions) == 1);
258 entry_point->name = ralloc_strdup(entry_point, "main");
259
260 NIR_PASS_V(nir, nir_remove_dead_variables,
261 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
262
263 /* Now that we've deleted all but the main function, we can go ahead and
264 * lower the rest of the constant initializers.
265 */
266 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
267 NIR_PASS_V(nir, nir_lower_system_values);
268 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
269 }
270
271 /* Vulkan uses the separate-shader linking model */
272 nir->info.separate_shader = true;
273
274 nir_shader_gather_info(nir, entry_point->impl);
275
276 nir_variable_mode indirect_mask = 0;
277 indirect_mask |= nir_var_shader_in;
278 indirect_mask |= nir_var_local;
279
280 nir_lower_indirect_derefs(nir, indirect_mask);
281
282 static const nir_lower_tex_options tex_options = {
283 .lower_txp = ~0,
284 };
285
286 nir_lower_tex(nir, &tex_options);
287
288 nir_lower_vars_to_ssa(nir);
289 nir_lower_var_copies(nir);
290 nir_lower_global_vars_to_local(nir);
291 nir_remove_dead_variables(nir, nir_var_local);
292 radv_optimize_nir(nir);
293
294 if (dump)
295 nir_print_shader(nir, stderr);
296
297 return nir;
298 }
299
300 static const char *radv_get_shader_name(struct radv_shader_variant *var,
301 gl_shader_stage stage)
302 {
303 switch (stage) {
304 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
305 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
306 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
307 case MESA_SHADER_COMPUTE: return "Compute Shader";
308 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
309 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
310 default:
311 return "Unknown shader";
312 };
313
314 }
315 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
316 {
317 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
318 struct radv_shader_variant *var;
319 struct ac_shader_config *conf;
320 int i;
321 FILE *file = stderr;
322 unsigned max_simd_waves = 10;
323 unsigned lds_per_wave = 0;
324
325 for (i = 0; i < MESA_SHADER_STAGES; i++) {
326 if (!pipeline->shaders[i])
327 continue;
328 var = pipeline->shaders[i];
329
330 conf = &var->config;
331
332 if (i == MESA_SHADER_FRAGMENT) {
333 lds_per_wave = conf->lds_size * lds_increment +
334 align(var->info.fs.num_interp * 48, lds_increment);
335 }
336
337 if (conf->num_sgprs) {
338 if (device->physical_device->rad_info.chip_class >= VI)
339 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
340 else
341 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
342 }
343
344 if (conf->num_vgprs)
345 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
346
347 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
348 * that PS can use.
349 */
350 if (lds_per_wave)
351 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
352
353 fprintf(file, "\n%s:\n",
354 radv_get_shader_name(var, i));
355 if (i == MESA_SHADER_FRAGMENT) {
356 fprintf(file, "*** SHADER CONFIG ***\n"
357 "SPI_PS_INPUT_ADDR = 0x%04x\n"
358 "SPI_PS_INPUT_ENA = 0x%04x\n",
359 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
360 }
361 fprintf(file, "*** SHADER STATS ***\n"
362 "SGPRS: %d\n"
363 "VGPRS: %d\n"
364 "Spilled SGPRs: %d\n"
365 "Spilled VGPRs: %d\n"
366 "Code Size: %d bytes\n"
367 "LDS: %d blocks\n"
368 "Scratch: %d bytes per wave\n"
369 "Max Waves: %d\n"
370 "********************\n\n\n",
371 conf->num_sgprs, conf->num_vgprs,
372 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
373 conf->lds_size, conf->scratch_bytes_per_wave,
374 max_simd_waves);
375 }
376 }
377
378 void radv_shader_variant_destroy(struct radv_device *device,
379 struct radv_shader_variant *variant)
380 {
381 if (!p_atomic_dec_zero(&variant->ref_count))
382 return;
383
384 mtx_lock(&device->shader_slab_mutex);
385 list_del(&variant->slab_list);
386 mtx_unlock(&device->shader_slab_mutex);
387
388 free(variant);
389 }
390
391 static void radv_fill_shader_variant(struct radv_device *device,
392 struct radv_shader_variant *variant,
393 struct ac_shader_binary *binary,
394 gl_shader_stage stage)
395 {
396 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
397 unsigned vgpr_comp_cnt = 0;
398
399 if (scratch_enabled && !device->llvm_supports_spill)
400 radv_finishme("shader scratch support only available with LLVM 4.0");
401
402 variant->code_size = binary->code_size;
403 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
404 S_00B12C_SCRATCH_EN(scratch_enabled);
405
406 switch (stage) {
407 case MESA_SHADER_TESS_EVAL:
408 vgpr_comp_cnt = 3;
409 /* fallthrough */
410 case MESA_SHADER_TESS_CTRL:
411 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
412 break;
413 case MESA_SHADER_VERTEX:
414 case MESA_SHADER_GEOMETRY:
415 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
416 break;
417 case MESA_SHADER_FRAGMENT:
418 break;
419 case MESA_SHADER_COMPUTE:
420 variant->rsrc2 |=
421 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
422 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
423 S_00B84C_TG_SIZE_EN(1) |
424 S_00B84C_LDS_SIZE(variant->config.lds_size);
425 break;
426 default:
427 unreachable("unsupported shader type");
428 break;
429 }
430
431 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
432 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
433 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
434 S_00B848_DX10_CLAMP(1) |
435 S_00B848_FLOAT_MODE(variant->config.float_mode);
436
437 void *ptr = radv_alloc_shader_memory(device, variant);
438 memcpy(ptr, binary->code, binary->code_size);
439 }
440
441 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
442 struct nir_shader *shader,
443 struct radv_pipeline_layout *layout,
444 const struct ac_shader_variant_key *key,
445 void** code_out,
446 unsigned *code_size_out,
447 bool dump)
448 {
449 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
450 enum radeon_family chip_family = device->physical_device->rad_info.family;
451 LLVMTargetMachineRef tm;
452 if (!variant)
453 return NULL;
454
455 struct ac_nir_compiler_options options = {0};
456 options.layout = layout;
457 if (key)
458 options.key = *key;
459
460 struct ac_shader_binary binary;
461 enum ac_target_machine_options tm_options = 0;
462 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
463 options.family = chip_family;
464 options.chip_class = device->physical_device->rad_info.chip_class;
465 options.supports_spill = device->llvm_supports_spill;
466 if (options.supports_spill)
467 tm_options |= AC_TM_SUPPORTS_SPILL;
468 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
469 tm_options |= AC_TM_SISCHED;
470 tm = ac_create_target_machine(chip_family, tm_options);
471 ac_compile_nir_shader(tm, &binary, &variant->config,
472 &variant->info, shader, &options, dump);
473 LLVMDisposeTargetMachine(tm);
474
475 radv_fill_shader_variant(device, variant, &binary, shader->stage);
476
477 if (code_out) {
478 *code_out = binary.code;
479 *code_size_out = binary.code_size;
480 } else
481 free(binary.code);
482 free(binary.config);
483 free(binary.rodata);
484 free(binary.global_symbol_offsets);
485 free(binary.relocs);
486 free(binary.disasm_string);
487 variant->ref_count = 1;
488 return variant;
489 }
490
491 static struct radv_shader_variant *
492 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
493 struct nir_shader *nir,
494 void** code_out,
495 unsigned *code_size_out,
496 bool dump_shader,
497 bool multiview)
498 {
499 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
500 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
501 LLVMTargetMachineRef tm;
502 if (!variant)
503 return NULL;
504
505 struct ac_nir_compiler_options options = {0};
506 struct ac_shader_binary binary;
507 enum ac_target_machine_options tm_options = 0;
508 options.family = chip_family;
509 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
510 options.key.has_multiview_view_index = multiview;
511 if (options.supports_spill)
512 tm_options |= AC_TM_SUPPORTS_SPILL;
513 if (pipeline->device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
514 tm_options |= AC_TM_SISCHED;
515 tm = ac_create_target_machine(chip_family, tm_options);
516 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
517 LLVMDisposeTargetMachine(tm);
518
519 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
520
521 if (code_out) {
522 *code_out = binary.code;
523 *code_size_out = binary.code_size;
524 } else
525 free(binary.code);
526 free(binary.config);
527 free(binary.rodata);
528 free(binary.global_symbol_offsets);
529 free(binary.relocs);
530 free(binary.disasm_string);
531 variant->ref_count = 1;
532 return variant;
533 }
534
535 static struct radv_shader_variant *
536 radv_pipeline_compile(struct radv_pipeline *pipeline,
537 struct radv_pipeline_cache *cache,
538 struct radv_shader_module *module,
539 const char *entrypoint,
540 gl_shader_stage stage,
541 const VkSpecializationInfo *spec_info,
542 struct radv_pipeline_layout *layout,
543 const struct ac_shader_variant_key *key)
544 {
545 unsigned char sha1[20];
546 unsigned char gs_copy_sha1[20];
547 struct radv_shader_variant *variant;
548 nir_shader *nir;
549 void *code = NULL;
550 unsigned code_size = 0;
551 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
552
553 if (module->nir)
554 _mesa_sha1_compute(module->nir->info.name,
555 strlen(module->nir->info.name),
556 module->sha1);
557
558 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
559 if (stage == MESA_SHADER_GEOMETRY)
560 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
561 layout, key, 1);
562
563 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
564 cache,
565 sha1);
566
567 if (stage == MESA_SHADER_GEOMETRY) {
568 pipeline->gs_copy_shader =
569 radv_create_shader_variant_from_pipeline_cache(
570 pipeline->device,
571 cache,
572 gs_copy_sha1);
573 }
574
575 if (variant &&
576 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
577 return variant;
578
579 nir = radv_shader_compile_to_nir(pipeline->device,
580 module, entrypoint, stage,
581 spec_info, dump);
582 if (nir == NULL)
583 return NULL;
584
585 if (!variant) {
586 variant = radv_shader_variant_create(pipeline->device, nir,
587 layout, key, &code,
588 &code_size, dump);
589 }
590
591 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
592 void *gs_copy_code = NULL;
593 unsigned gs_copy_code_size = 0;
594 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
595 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump, key->has_multiview_view_index);
596
597 if (pipeline->gs_copy_shader) {
598 pipeline->gs_copy_shader =
599 radv_pipeline_cache_insert_shader(cache,
600 gs_copy_sha1,
601 pipeline->gs_copy_shader,
602 gs_copy_code,
603 gs_copy_code_size);
604 }
605 }
606 if (!module->nir)
607 ralloc_free(nir);
608
609 if (variant)
610 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
611 code, code_size);
612
613 if (code)
614 free(code);
615 return variant;
616 }
617
618 static struct ac_shader_variant_key
619 radv_compute_tes_key(bool as_es, bool export_prim_id)
620 {
621 struct ac_shader_variant_key key;
622 memset(&key, 0, sizeof(key));
623 key.tes.as_es = as_es;
624 /* export prim id only happens when no geom shader */
625 if (!as_es)
626 key.tes.export_prim_id = export_prim_id;
627 return key;
628 }
629
630 static struct ac_shader_variant_key
631 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
632 {
633 struct ac_shader_variant_key key;
634 memset(&key, 0, sizeof(key));
635 key.tcs.primitive_mode = primitive_mode;
636 key.tcs.input_vertices = input_vertices;
637 return key;
638 }
639
640 static void
641 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
642 struct radv_pipeline_cache *cache,
643 struct radv_shader_module *tcs_module,
644 struct radv_shader_module *tes_module,
645 const char *tcs_entrypoint,
646 const char *tes_entrypoint,
647 const VkSpecializationInfo *tcs_spec_info,
648 const VkSpecializationInfo *tes_spec_info,
649 struct radv_pipeline_layout *layout,
650 unsigned input_vertices,
651 bool has_view_index)
652 {
653 unsigned char tcs_sha1[20], tes_sha1[20];
654 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
655 nir_shader *tes_nir, *tcs_nir;
656 void *tes_code = NULL, *tcs_code = NULL;
657 unsigned tes_code_size = 0, tcs_code_size = 0;
658 struct ac_shader_variant_key tes_key;
659 struct ac_shader_variant_key tcs_key;
660 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
661
662 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
663 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
664 tes_key.has_multiview_view_index = has_view_index;
665 if (tes_module->nir)
666 _mesa_sha1_compute(tes_module->nir->info.name,
667 strlen(tes_module->nir->info.name),
668 tes_module->sha1);
669 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
670
671 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
672 cache,
673 tes_sha1);
674
675 if (tes_variant) {
676 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
677
678 if (tcs_module->nir)
679 _mesa_sha1_compute(tcs_module->nir->info.name,
680 strlen(tcs_module->nir->info.name),
681 tcs_module->sha1);
682
683 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
684
685 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
686 cache,
687 tcs_sha1);
688 }
689
690 if (tcs_variant && tes_variant) {
691 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
692 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
693 return;
694 }
695
696 tes_nir = radv_shader_compile_to_nir(pipeline->device,
697 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
698 tes_spec_info, dump);
699 if (tes_nir == NULL)
700 return;
701
702 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
703 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
704 tcs_spec_info, dump);
705 if (tcs_nir == NULL)
706 return;
707
708 nir_lower_tes_patch_vertices(tes_nir,
709 tcs_nir->info.tess.tcs_vertices_out);
710
711 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
712 layout, &tes_key, &tes_code,
713 &tes_code_size, dump);
714
715 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
716 if (tcs_module->nir)
717 _mesa_sha1_compute(tcs_module->nir->info.name,
718 strlen(tcs_module->nir->info.name),
719 tcs_module->sha1);
720
721 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
722
723 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
724 layout, &tcs_key, &tcs_code,
725 &tcs_code_size, dump);
726
727 if (!tes_module->nir)
728 ralloc_free(tes_nir);
729
730 if (!tcs_module->nir)
731 ralloc_free(tcs_nir);
732
733 if (tes_variant)
734 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
735 tes_code, tes_code_size);
736
737 if (tcs_variant)
738 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
739 tcs_code, tcs_code_size);
740
741 if (tes_code)
742 free(tes_code);
743 if (tcs_code)
744 free(tcs_code);
745 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
746 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
747 return;
748 }
749
750 static VkResult
751 radv_pipeline_scratch_init(struct radv_device *device,
752 struct radv_pipeline *pipeline)
753 {
754 unsigned scratch_bytes_per_wave = 0;
755 unsigned max_waves = 0;
756 unsigned min_waves = 1;
757
758 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
759 if (pipeline->shaders[i]) {
760 unsigned max_stage_waves = device->scratch_waves;
761
762 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
763 pipeline->shaders[i]->config.scratch_bytes_per_wave);
764
765 max_stage_waves = MIN2(max_stage_waves,
766 4 * device->physical_device->rad_info.num_good_compute_units *
767 (256 / pipeline->shaders[i]->config.num_vgprs));
768 max_waves = MAX2(max_waves, max_stage_waves);
769 }
770 }
771
772 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
773 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
774 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
775 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
776 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
777 }
778
779 if (scratch_bytes_per_wave)
780 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
781
782 if (scratch_bytes_per_wave && max_waves < min_waves) {
783 /* Not really true at this moment, but will be true on first
784 * execution. Avoid having hanging shaders. */
785 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
786 }
787 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
788 pipeline->max_waves = max_waves;
789 return VK_SUCCESS;
790 }
791
792 static uint32_t si_translate_blend_function(VkBlendOp op)
793 {
794 switch (op) {
795 case VK_BLEND_OP_ADD:
796 return V_028780_COMB_DST_PLUS_SRC;
797 case VK_BLEND_OP_SUBTRACT:
798 return V_028780_COMB_SRC_MINUS_DST;
799 case VK_BLEND_OP_REVERSE_SUBTRACT:
800 return V_028780_COMB_DST_MINUS_SRC;
801 case VK_BLEND_OP_MIN:
802 return V_028780_COMB_MIN_DST_SRC;
803 case VK_BLEND_OP_MAX:
804 return V_028780_COMB_MAX_DST_SRC;
805 default:
806 return 0;
807 }
808 }
809
810 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
811 {
812 switch (factor) {
813 case VK_BLEND_FACTOR_ZERO:
814 return V_028780_BLEND_ZERO;
815 case VK_BLEND_FACTOR_ONE:
816 return V_028780_BLEND_ONE;
817 case VK_BLEND_FACTOR_SRC_COLOR:
818 return V_028780_BLEND_SRC_COLOR;
819 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
820 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
821 case VK_BLEND_FACTOR_DST_COLOR:
822 return V_028780_BLEND_DST_COLOR;
823 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
824 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
825 case VK_BLEND_FACTOR_SRC_ALPHA:
826 return V_028780_BLEND_SRC_ALPHA;
827 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
828 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
829 case VK_BLEND_FACTOR_DST_ALPHA:
830 return V_028780_BLEND_DST_ALPHA;
831 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
832 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
833 case VK_BLEND_FACTOR_CONSTANT_COLOR:
834 return V_028780_BLEND_CONSTANT_COLOR;
835 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
836 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
837 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
838 return V_028780_BLEND_CONSTANT_ALPHA;
839 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
840 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
841 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
842 return V_028780_BLEND_SRC_ALPHA_SATURATE;
843 case VK_BLEND_FACTOR_SRC1_COLOR:
844 return V_028780_BLEND_SRC1_COLOR;
845 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
846 return V_028780_BLEND_INV_SRC1_COLOR;
847 case VK_BLEND_FACTOR_SRC1_ALPHA:
848 return V_028780_BLEND_SRC1_ALPHA;
849 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
850 return V_028780_BLEND_INV_SRC1_ALPHA;
851 default:
852 return 0;
853 }
854 }
855
856 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
857 {
858 switch (op) {
859 case VK_BLEND_OP_ADD:
860 return V_028760_OPT_COMB_ADD;
861 case VK_BLEND_OP_SUBTRACT:
862 return V_028760_OPT_COMB_SUBTRACT;
863 case VK_BLEND_OP_REVERSE_SUBTRACT:
864 return V_028760_OPT_COMB_REVSUBTRACT;
865 case VK_BLEND_OP_MIN:
866 return V_028760_OPT_COMB_MIN;
867 case VK_BLEND_OP_MAX:
868 return V_028760_OPT_COMB_MAX;
869 default:
870 return V_028760_OPT_COMB_BLEND_DISABLED;
871 }
872 }
873
874 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
875 {
876 switch (factor) {
877 case VK_BLEND_FACTOR_ZERO:
878 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
879 case VK_BLEND_FACTOR_ONE:
880 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
881 case VK_BLEND_FACTOR_SRC_COLOR:
882 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
883 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
884 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
885 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
886 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
887 case VK_BLEND_FACTOR_SRC_ALPHA:
888 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
889 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
890 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
891 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
892 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
893 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
894 default:
895 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
896 }
897 }
898
899 /**
900 * Get rid of DST in the blend factors by commuting the operands:
901 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
902 */
903 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
904 unsigned *dst_factor, unsigned expected_dst,
905 unsigned replacement_src)
906 {
907 if (*src_factor == expected_dst &&
908 *dst_factor == VK_BLEND_FACTOR_ZERO) {
909 *src_factor = VK_BLEND_FACTOR_ZERO;
910 *dst_factor = replacement_src;
911
912 /* Commuting the operands requires reversing subtractions. */
913 if (*func == VK_BLEND_OP_SUBTRACT)
914 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
915 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
916 *func = VK_BLEND_OP_SUBTRACT;
917 }
918 }
919
920 static bool si_blend_factor_uses_dst(unsigned factor)
921 {
922 return factor == VK_BLEND_FACTOR_DST_COLOR ||
923 factor == VK_BLEND_FACTOR_DST_ALPHA ||
924 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
925 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
926 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
927 }
928
929 static bool is_dual_src(VkBlendFactor factor)
930 {
931 switch (factor) {
932 case VK_BLEND_FACTOR_SRC1_COLOR:
933 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
934 case VK_BLEND_FACTOR_SRC1_ALPHA:
935 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
936 return true;
937 default:
938 return false;
939 }
940 }
941
942 static unsigned si_choose_spi_color_format(VkFormat vk_format,
943 bool blend_enable,
944 bool blend_need_alpha)
945 {
946 const struct vk_format_description *desc = vk_format_description(vk_format);
947 unsigned format, ntype, swap;
948
949 /* Alpha is needed for alpha-to-coverage.
950 * Blending may be with or without alpha.
951 */
952 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
953 unsigned alpha = 0; /* exports alpha, but may not support blending */
954 unsigned blend = 0; /* supports blending, but may not export alpha */
955 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
956
957 format = radv_translate_colorformat(vk_format);
958 ntype = radv_translate_color_numformat(vk_format, desc,
959 vk_format_get_first_non_void_channel(vk_format));
960 swap = radv_translate_colorswap(vk_format, false);
961
962 /* Choose the SPI color formats. These are required values for Stoney/RB+.
963 * Other chips have multiple choices, though they are not necessarily better.
964 */
965 switch (format) {
966 case V_028C70_COLOR_5_6_5:
967 case V_028C70_COLOR_1_5_5_5:
968 case V_028C70_COLOR_5_5_5_1:
969 case V_028C70_COLOR_4_4_4_4:
970 case V_028C70_COLOR_10_11_11:
971 case V_028C70_COLOR_11_11_10:
972 case V_028C70_COLOR_8:
973 case V_028C70_COLOR_8_8:
974 case V_028C70_COLOR_8_8_8_8:
975 case V_028C70_COLOR_10_10_10_2:
976 case V_028C70_COLOR_2_10_10_10:
977 if (ntype == V_028C70_NUMBER_UINT)
978 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
979 else if (ntype == V_028C70_NUMBER_SINT)
980 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
981 else
982 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
983 break;
984
985 case V_028C70_COLOR_16:
986 case V_028C70_COLOR_16_16:
987 case V_028C70_COLOR_16_16_16_16:
988 if (ntype == V_028C70_NUMBER_UNORM ||
989 ntype == V_028C70_NUMBER_SNORM) {
990 /* UNORM16 and SNORM16 don't support blending */
991 if (ntype == V_028C70_NUMBER_UNORM)
992 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
993 else
994 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
995
996 /* Use 32 bits per channel for blending. */
997 if (format == V_028C70_COLOR_16) {
998 if (swap == V_028C70_SWAP_STD) { /* R */
999 blend = V_028714_SPI_SHADER_32_R;
1000 blend_alpha = V_028714_SPI_SHADER_32_AR;
1001 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1002 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1003 else
1004 assert(0);
1005 } else if (format == V_028C70_COLOR_16_16) {
1006 if (swap == V_028C70_SWAP_STD) { /* RG */
1007 blend = V_028714_SPI_SHADER_32_GR;
1008 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1009 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1010 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1011 else
1012 assert(0);
1013 } else /* 16_16_16_16 */
1014 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1015 } else if (ntype == V_028C70_NUMBER_UINT)
1016 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1017 else if (ntype == V_028C70_NUMBER_SINT)
1018 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1019 else if (ntype == V_028C70_NUMBER_FLOAT)
1020 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1021 else
1022 assert(0);
1023 break;
1024
1025 case V_028C70_COLOR_32:
1026 if (swap == V_028C70_SWAP_STD) { /* R */
1027 blend = normal = V_028714_SPI_SHADER_32_R;
1028 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1029 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1030 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1031 else
1032 assert(0);
1033 break;
1034
1035 case V_028C70_COLOR_32_32:
1036 if (swap == V_028C70_SWAP_STD) { /* RG */
1037 blend = normal = V_028714_SPI_SHADER_32_GR;
1038 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1039 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1040 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1041 else
1042 assert(0);
1043 break;
1044
1045 case V_028C70_COLOR_32_32_32_32:
1046 case V_028C70_COLOR_8_24:
1047 case V_028C70_COLOR_24_8:
1048 case V_028C70_COLOR_X24_8_32_FLOAT:
1049 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1050 break;
1051
1052 default:
1053 unreachable("unhandled blend format");
1054 }
1055
1056 if (blend_enable && blend_need_alpha)
1057 return blend_alpha;
1058 else if(blend_need_alpha)
1059 return alpha;
1060 else if(blend_enable)
1061 return blend;
1062 else
1063 return normal;
1064 }
1065
1066 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
1067 {
1068 unsigned i, cb_shader_mask = 0;
1069
1070 for (i = 0; i < 8; i++) {
1071 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
1072 case V_028714_SPI_SHADER_ZERO:
1073 break;
1074 case V_028714_SPI_SHADER_32_R:
1075 cb_shader_mask |= 0x1 << (i * 4);
1076 break;
1077 case V_028714_SPI_SHADER_32_GR:
1078 cb_shader_mask |= 0x3 << (i * 4);
1079 break;
1080 case V_028714_SPI_SHADER_32_AR:
1081 cb_shader_mask |= 0x9 << (i * 4);
1082 break;
1083 case V_028714_SPI_SHADER_FP16_ABGR:
1084 case V_028714_SPI_SHADER_UNORM16_ABGR:
1085 case V_028714_SPI_SHADER_SNORM16_ABGR:
1086 case V_028714_SPI_SHADER_UINT16_ABGR:
1087 case V_028714_SPI_SHADER_SINT16_ABGR:
1088 case V_028714_SPI_SHADER_32_ABGR:
1089 cb_shader_mask |= 0xf << (i * 4);
1090 break;
1091 default:
1092 assert(0);
1093 }
1094 }
1095 return cb_shader_mask;
1096 }
1097
1098 static void
1099 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
1100 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1101 uint32_t blend_enable,
1102 uint32_t blend_need_alpha,
1103 bool single_cb_enable,
1104 bool blend_mrt0_is_dual_src)
1105 {
1106 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1107 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1108 struct radv_blend_state *blend = &pipeline->graphics.blend;
1109 unsigned col_format = 0;
1110
1111 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
1112 unsigned cf;
1113
1114 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1115 cf = V_028714_SPI_SHADER_ZERO;
1116 } else {
1117 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
1118
1119 cf = si_choose_spi_color_format(attachment->format,
1120 blend_enable & (1 << i),
1121 blend_need_alpha & (1 << i));
1122 }
1123
1124 col_format |= cf << (4 * i);
1125 }
1126
1127 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
1128
1129 if (blend_mrt0_is_dual_src)
1130 col_format |= (col_format & 0xf) << 4;
1131 blend->spi_shader_col_format = col_format;
1132 }
1133
1134 static bool
1135 format_is_int8(VkFormat format)
1136 {
1137 const struct vk_format_description *desc = vk_format_description(format);
1138 int channel = vk_format_get_first_non_void_channel(format);
1139
1140 return channel >= 0 && desc->channel[channel].pure_integer &&
1141 desc->channel[channel].size == 8;
1142 }
1143
1144 static bool
1145 format_is_int10(VkFormat format)
1146 {
1147 const struct vk_format_description *desc = vk_format_description(format);
1148
1149 if (desc->nr_channels != 4)
1150 return false;
1151 for (unsigned i = 0; i < 4; i++) {
1152 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
1153 return true;
1154 }
1155 return false;
1156 }
1157
1158 unsigned radv_format_meta_fs_key(VkFormat format)
1159 {
1160 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
1161 bool is_int8 = format_is_int8(format);
1162 bool is_int10 = format_is_int10(format);
1163
1164 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
1165 }
1166
1167 static void
1168 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1169 unsigned *is_int8, unsigned *is_int10)
1170 {
1171 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1172 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1173 *is_int8 = 0;
1174 *is_int10 = 0;
1175
1176 for (unsigned i = 0; i < subpass->color_count; ++i) {
1177 struct radv_render_pass_attachment *attachment;
1178
1179 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
1180 continue;
1181
1182 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1183
1184 if (format_is_int8(attachment->format))
1185 *is_int8 |= 1 << i;
1186 if (format_is_int10(attachment->format))
1187 *is_int10 |= 1 << i;
1188 }
1189 }
1190
1191 static void
1192 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
1193 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1194 const struct radv_graphics_pipeline_create_info *extra)
1195 {
1196 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
1197 struct radv_blend_state *blend = &pipeline->graphics.blend;
1198 unsigned mode = V_028808_CB_NORMAL;
1199 uint32_t blend_enable = 0, blend_need_alpha = 0;
1200 bool blend_mrt0_is_dual_src = false;
1201 int i;
1202 bool single_cb_enable = false;
1203
1204 if (!vkblend)
1205 return;
1206
1207 if (extra && extra->custom_blend_mode) {
1208 single_cb_enable = true;
1209 mode = extra->custom_blend_mode;
1210 }
1211 blend->cb_color_control = 0;
1212 if (vkblend->logicOpEnable)
1213 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
1214 else
1215 blend->cb_color_control |= S_028808_ROP3(0xcc);
1216
1217 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1218 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1219 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1220 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1221
1222 blend->cb_target_mask = 0;
1223 for (i = 0; i < vkblend->attachmentCount; i++) {
1224 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
1225 unsigned blend_cntl = 0;
1226 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
1227 VkBlendOp eqRGB = att->colorBlendOp;
1228 VkBlendFactor srcRGB = att->srcColorBlendFactor;
1229 VkBlendFactor dstRGB = att->dstColorBlendFactor;
1230 VkBlendOp eqA = att->alphaBlendOp;
1231 VkBlendFactor srcA = att->srcAlphaBlendFactor;
1232 VkBlendFactor dstA = att->dstAlphaBlendFactor;
1233
1234 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1235
1236 if (!att->colorWriteMask)
1237 continue;
1238
1239 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
1240 if (!att->blendEnable) {
1241 blend->cb_blend_control[i] = blend_cntl;
1242 continue;
1243 }
1244
1245 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
1246 if (i == 0)
1247 blend_mrt0_is_dual_src = true;
1248
1249 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
1250 srcRGB = VK_BLEND_FACTOR_ONE;
1251 dstRGB = VK_BLEND_FACTOR_ONE;
1252 }
1253 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
1254 srcA = VK_BLEND_FACTOR_ONE;
1255 dstA = VK_BLEND_FACTOR_ONE;
1256 }
1257
1258 /* Blending optimizations for RB+.
1259 * These transformations don't change the behavior.
1260 *
1261 * First, get rid of DST in the blend factors:
1262 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
1263 */
1264 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
1265 VK_BLEND_FACTOR_DST_COLOR,
1266 VK_BLEND_FACTOR_SRC_COLOR);
1267
1268 si_blend_remove_dst(&eqA, &srcA, &dstA,
1269 VK_BLEND_FACTOR_DST_COLOR,
1270 VK_BLEND_FACTOR_SRC_COLOR);
1271
1272 si_blend_remove_dst(&eqA, &srcA, &dstA,
1273 VK_BLEND_FACTOR_DST_ALPHA,
1274 VK_BLEND_FACTOR_SRC_ALPHA);
1275
1276 /* Look up the ideal settings from tables. */
1277 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
1278 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
1279 srcA_opt = si_translate_blend_opt_factor(srcA, true);
1280 dstA_opt = si_translate_blend_opt_factor(dstA, true);
1281
1282 /* Handle interdependencies. */
1283 if (si_blend_factor_uses_dst(srcRGB))
1284 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
1285 if (si_blend_factor_uses_dst(srcA))
1286 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
1287
1288 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
1289 (dstRGB == VK_BLEND_FACTOR_ZERO ||
1290 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1291 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
1292 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
1293
1294 /* Set the final value. */
1295 blend->sx_mrt_blend_opt[i] =
1296 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
1297 S_028760_COLOR_DST_OPT(dstRGB_opt) |
1298 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
1299 S_028760_ALPHA_SRC_OPT(srcA_opt) |
1300 S_028760_ALPHA_DST_OPT(dstA_opt) |
1301 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
1302 blend_cntl |= S_028780_ENABLE(1);
1303
1304 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1305 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1306 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1307 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1308 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1309 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1310 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1311 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1312 }
1313 blend->cb_blend_control[i] = blend_cntl;
1314
1315 blend_enable |= 1 << i;
1316
1317 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1318 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1319 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1320 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1321 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1322 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1323 blend_need_alpha |= 1 << i;
1324 }
1325 for (i = vkblend->attachmentCount; i < 8; i++) {
1326 blend->cb_blend_control[i] = 0;
1327 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1328 }
1329
1330 /* disable RB+ for now */
1331 if (pipeline->device->physical_device->has_rbplus)
1332 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
1333
1334 if (blend->cb_target_mask)
1335 blend->cb_color_control |= S_028808_MODE(mode);
1336 else
1337 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1338
1339 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1340 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1341 }
1342
1343 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1344 {
1345 switch (op) {
1346 case VK_STENCIL_OP_KEEP:
1347 return V_02842C_STENCIL_KEEP;
1348 case VK_STENCIL_OP_ZERO:
1349 return V_02842C_STENCIL_ZERO;
1350 case VK_STENCIL_OP_REPLACE:
1351 return V_02842C_STENCIL_REPLACE_TEST;
1352 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1353 return V_02842C_STENCIL_ADD_CLAMP;
1354 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1355 return V_02842C_STENCIL_SUB_CLAMP;
1356 case VK_STENCIL_OP_INVERT:
1357 return V_02842C_STENCIL_INVERT;
1358 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1359 return V_02842C_STENCIL_ADD_WRAP;
1360 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1361 return V_02842C_STENCIL_SUB_WRAP;
1362 default:
1363 return 0;
1364 }
1365 }
1366 static void
1367 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1368 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1369 const struct radv_graphics_pipeline_create_info *extra)
1370 {
1371 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1372 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1373
1374 memset(ds, 0, sizeof(*ds));
1375 if (!vkds)
1376 return;
1377
1378 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1379 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1380 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
1381 return;
1382
1383 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
1384 bool has_depth_attachment = vk_format_is_depth(attachment->format);
1385 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
1386
1387 if (has_depth_attachment) {
1388 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1389 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1390 S_028800_ZFUNC(vkds->depthCompareOp) |
1391 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1392 }
1393
1394 if (has_stencil_attachment && vkds->stencilTestEnable) {
1395 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1396 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1397 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1398 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1399 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1400
1401 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1402 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1403 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1404 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1405 }
1406
1407 if (extra) {
1408
1409 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1410 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1411
1412 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1413 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1414 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1415 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1416 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1417 }
1418 }
1419
1420 static uint32_t si_translate_fill(VkPolygonMode func)
1421 {
1422 switch(func) {
1423 case VK_POLYGON_MODE_FILL:
1424 return V_028814_X_DRAW_TRIANGLES;
1425 case VK_POLYGON_MODE_LINE:
1426 return V_028814_X_DRAW_LINES;
1427 case VK_POLYGON_MODE_POINT:
1428 return V_028814_X_DRAW_POINTS;
1429 default:
1430 assert(0);
1431 return V_028814_X_DRAW_POINTS;
1432 }
1433 }
1434 static void
1435 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1436 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1437 {
1438 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1439 struct radv_raster_state *raster = &pipeline->graphics.raster;
1440
1441 memset(raster, 0, sizeof(*raster));
1442
1443 raster->spi_interp_control =
1444 S_0286D4_FLAT_SHADE_ENA(1) |
1445 S_0286D4_PNT_SPRITE_ENA(1) |
1446 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1447 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1448 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1449 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1450 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1451
1452
1453 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1454 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1455 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1456 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1457 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1458 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1459
1460 raster->pa_su_vtx_cntl =
1461 S_028BE4_PIX_CENTER(1) | // TODO verify
1462 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1463 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1464
1465 raster->pa_su_sc_mode_cntl =
1466 S_028814_FACE(vkraster->frontFace) |
1467 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1468 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1469 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1470 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1471 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1472 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1473 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1474 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1475
1476 }
1477
1478 static void
1479 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1480 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1481 {
1482 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1483 struct radv_blend_state *blend = &pipeline->graphics.blend;
1484 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1485 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1486 int ps_iter_samples = 1;
1487 uint32_t mask = 0xffff;
1488
1489 if (vkms)
1490 ms->num_samples = vkms->rasterizationSamples;
1491 else
1492 ms->num_samples = 1;
1493
1494 if (vkms && vkms->sampleShadingEnable) {
1495 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
1496 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1497 ps_iter_samples = ms->num_samples;
1498 }
1499
1500 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1501 ms->pa_sc_aa_config = 0;
1502 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1503 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1504 ms->pa_sc_mode_cntl_1 =
1505 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1506 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1507 /* always 1: */
1508 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1509 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1510 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1511 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1512 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1513 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1514 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1515
1516 if (ms->num_samples > 1) {
1517 unsigned log_samples = util_logbase2(ms->num_samples);
1518 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1519 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1520 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1521 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1522 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1523 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1524 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1525 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1526 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1527 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1528 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1529 }
1530
1531 if (vkms) {
1532 if (vkms->alphaToCoverageEnable)
1533 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1534
1535 if (vkms->pSampleMask)
1536 mask = vkms->pSampleMask[0] & 0xffff;
1537 }
1538
1539 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1540 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1541 }
1542
1543 static bool
1544 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1545 {
1546 switch (topology) {
1547 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1548 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1549 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1550 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1551 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1552 return false;
1553 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1554 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1555 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1556 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1557 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1558 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1559 return true;
1560 default:
1561 unreachable("unhandled primitive type");
1562 }
1563 }
1564
1565 static uint32_t
1566 si_translate_prim(enum VkPrimitiveTopology topology)
1567 {
1568 switch (topology) {
1569 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1570 return V_008958_DI_PT_POINTLIST;
1571 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1572 return V_008958_DI_PT_LINELIST;
1573 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1574 return V_008958_DI_PT_LINESTRIP;
1575 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1576 return V_008958_DI_PT_TRILIST;
1577 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1578 return V_008958_DI_PT_TRISTRIP;
1579 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1580 return V_008958_DI_PT_TRIFAN;
1581 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1582 return V_008958_DI_PT_LINELIST_ADJ;
1583 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1584 return V_008958_DI_PT_LINESTRIP_ADJ;
1585 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1586 return V_008958_DI_PT_TRILIST_ADJ;
1587 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1588 return V_008958_DI_PT_TRISTRIP_ADJ;
1589 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1590 return V_008958_DI_PT_PATCH;
1591 default:
1592 assert(0);
1593 return 0;
1594 }
1595 }
1596
1597 static uint32_t
1598 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1599 {
1600 switch (gl_prim) {
1601 case 0: /* GL_POINTS */
1602 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1603 case 1: /* GL_LINES */
1604 case 3: /* GL_LINE_STRIP */
1605 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1606 case 0x8E7A: /* GL_ISOLINES */
1607 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1608
1609 case 4: /* GL_TRIANGLES */
1610 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1611 case 5: /* GL_TRIANGLE_STRIP */
1612 case 7: /* GL_QUADS */
1613 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1614 default:
1615 assert(0);
1616 return 0;
1617 }
1618 }
1619
1620 static uint32_t
1621 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1622 {
1623 switch (topology) {
1624 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1625 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1626 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1627 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1628 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1629 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1630 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1631 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1632 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1633 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1634 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1635 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1636 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1637 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1638 default:
1639 assert(0);
1640 return 0;
1641 }
1642 }
1643
1644 static unsigned si_map_swizzle(unsigned swizzle)
1645 {
1646 switch (swizzle) {
1647 case VK_SWIZZLE_Y:
1648 return V_008F0C_SQ_SEL_Y;
1649 case VK_SWIZZLE_Z:
1650 return V_008F0C_SQ_SEL_Z;
1651 case VK_SWIZZLE_W:
1652 return V_008F0C_SQ_SEL_W;
1653 case VK_SWIZZLE_0:
1654 return V_008F0C_SQ_SEL_0;
1655 case VK_SWIZZLE_1:
1656 return V_008F0C_SQ_SEL_1;
1657 default: /* VK_SWIZZLE_X */
1658 return V_008F0C_SQ_SEL_X;
1659 }
1660 }
1661
1662 static void
1663 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1664 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1665 {
1666 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1667 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1668 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1669
1670 pipeline->dynamic_state = default_dynamic_state;
1671
1672 if (pCreateInfo->pDynamicState) {
1673 /* Remove all of the states that are marked as dynamic */
1674 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1675 for (uint32_t s = 0; s < count; s++)
1676 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1677 }
1678
1679 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1680
1681 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1682 *
1683 * pViewportState is [...] NULL if the pipeline
1684 * has rasterization disabled.
1685 */
1686 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1687 assert(pCreateInfo->pViewportState);
1688
1689 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1690 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1691 typed_memcpy(dynamic->viewport.viewports,
1692 pCreateInfo->pViewportState->pViewports,
1693 pCreateInfo->pViewportState->viewportCount);
1694 }
1695
1696 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1697 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1698 typed_memcpy(dynamic->scissor.scissors,
1699 pCreateInfo->pViewportState->pScissors,
1700 pCreateInfo->pViewportState->scissorCount);
1701 }
1702 }
1703
1704 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1705 assert(pCreateInfo->pRasterizationState);
1706 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1707 }
1708
1709 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1710 assert(pCreateInfo->pRasterizationState);
1711 dynamic->depth_bias.bias =
1712 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1713 dynamic->depth_bias.clamp =
1714 pCreateInfo->pRasterizationState->depthBiasClamp;
1715 dynamic->depth_bias.slope =
1716 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1717 }
1718
1719 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1720 *
1721 * pColorBlendState is [...] NULL if the pipeline has rasterization
1722 * disabled or if the subpass of the render pass the pipeline is
1723 * created against does not use any color attachments.
1724 */
1725 bool uses_color_att = false;
1726 for (unsigned i = 0; i < subpass->color_count; ++i) {
1727 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1728 uses_color_att = true;
1729 break;
1730 }
1731 }
1732
1733 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1734 assert(pCreateInfo->pColorBlendState);
1735 typed_memcpy(dynamic->blend_constants,
1736 pCreateInfo->pColorBlendState->blendConstants, 4);
1737 }
1738
1739 /* If there is no depthstencil attachment, then don't read
1740 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1741 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1742 * no need to override the depthstencil defaults in
1743 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1744 *
1745 * Section 9.2 of the Vulkan 1.0.15 spec says:
1746 *
1747 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1748 * disabled or if the subpass of the render pass the pipeline is created
1749 * against does not use a depth/stencil attachment.
1750 */
1751 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1752 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1753 assert(pCreateInfo->pDepthStencilState);
1754
1755 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1756 dynamic->depth_bounds.min =
1757 pCreateInfo->pDepthStencilState->minDepthBounds;
1758 dynamic->depth_bounds.max =
1759 pCreateInfo->pDepthStencilState->maxDepthBounds;
1760 }
1761
1762 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1763 dynamic->stencil_compare_mask.front =
1764 pCreateInfo->pDepthStencilState->front.compareMask;
1765 dynamic->stencil_compare_mask.back =
1766 pCreateInfo->pDepthStencilState->back.compareMask;
1767 }
1768
1769 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1770 dynamic->stencil_write_mask.front =
1771 pCreateInfo->pDepthStencilState->front.writeMask;
1772 dynamic->stencil_write_mask.back =
1773 pCreateInfo->pDepthStencilState->back.writeMask;
1774 }
1775
1776 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1777 dynamic->stencil_reference.front =
1778 pCreateInfo->pDepthStencilState->front.reference;
1779 dynamic->stencil_reference.back =
1780 pCreateInfo->pDepthStencilState->back.reference;
1781 }
1782 }
1783
1784 pipeline->dynamic_state_mask = states;
1785 }
1786
1787 static struct ac_shader_variant_key
1788 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1789 {
1790 struct ac_shader_variant_key key;
1791 const VkPipelineVertexInputStateCreateInfo *input_state =
1792 pCreateInfo->pVertexInputState;
1793
1794 memset(&key, 0, sizeof(key));
1795 key.vs.instance_rate_inputs = 0;
1796 key.vs.as_es = as_es;
1797 key.vs.as_ls = as_ls;
1798 key.vs.export_prim_id = export_prim_id;
1799
1800 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1801 unsigned binding;
1802 binding = input_state->pVertexAttributeDescriptions[i].binding;
1803 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1804 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1805 }
1806 return key;
1807 }
1808
1809 static void
1810 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1811 {
1812 struct radv_device *device = pipeline->device;
1813 unsigned num_se = device->physical_device->rad_info.max_se;
1814 unsigned wave_size = 64;
1815 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1816 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1817 unsigned alignment = 256 * num_se;
1818 /* The maximum size is 63.999 MB per SE. */
1819 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1820 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1821 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1822 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1823 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1824
1825 /* Calculate the minimum size. */
1826 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1827 wave_size, alignment);
1828 /* These are recommended sizes, not minimum sizes. */
1829 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1830 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1831 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1832 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1833
1834 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1835 esgs_ring_size = align(esgs_ring_size, alignment);
1836 gsvs_ring_size = align(gsvs_ring_size, alignment);
1837
1838 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1839 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1840 }
1841
1842 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1843 unsigned *lds_size)
1844 {
1845 /* SPI barrier management bug:
1846 * Make sure we have at least 4k of LDS in use to avoid the bug.
1847 * It applies to workgroup sizes of more than one wavefront.
1848 */
1849 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1850 device->physical_device->rad_info.family == CHIP_KABINI ||
1851 device->physical_device->rad_info.family == CHIP_MULLINS)
1852 *lds_size = MAX2(*lds_size, 8);
1853 }
1854
1855 static void
1856 calculate_tess_state(struct radv_pipeline *pipeline,
1857 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1858 {
1859 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1860 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1861 unsigned num_tcs_patch_outputs;
1862 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1863 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1864 unsigned lds_size, hardware_lds_size;
1865 unsigned perpatch_output_offset;
1866 unsigned num_patches;
1867 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1868
1869 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1870 * are laid out in LDS. */
1871 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1872
1873 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1874 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1875 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1876
1877 /* Ensure that we only need one wave per SIMD so we don't need to check
1878 * resource usage. Also ensures that the number of tcs in and out
1879 * vertices per threadgroup are at most 256.
1880 */
1881 input_vertex_size = num_tcs_inputs * 16;
1882 output_vertex_size = num_tcs_outputs * 16;
1883
1884 input_patch_size = num_tcs_input_cp * input_vertex_size;
1885
1886 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1887 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1888 /* Ensure that we only need one wave per SIMD so we don't need to check
1889 * resource usage. Also ensures that the number of tcs in and out
1890 * vertices per threadgroup are at most 256.
1891 */
1892 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1893
1894 /* Make sure that the data fits in LDS. This assumes the shaders only
1895 * use LDS for the inputs and outputs.
1896 */
1897 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1898 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1899
1900 /* Make sure the output data fits in the offchip buffer */
1901 num_patches = MIN2(num_patches,
1902 (pipeline->device->tess_offchip_block_dw_size * 4) /
1903 output_patch_size);
1904
1905 /* Not necessary for correctness, but improves performance. The
1906 * specific value is taken from the proprietary driver.
1907 */
1908 num_patches = MIN2(num_patches, 40);
1909
1910 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1911 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1912 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1913 num_patches = MIN2(num_patches, one_wave);
1914 }
1915
1916 output_patch0_offset = input_patch_size * num_patches;
1917 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1918
1919 lds_size = output_patch0_offset + output_patch_size * num_patches;
1920
1921 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1922 assert(lds_size <= 65536);
1923 lds_size = align(lds_size, 512) / 512;
1924 } else {
1925 assert(lds_size <= 32768);
1926 lds_size = align(lds_size, 256) / 256;
1927 }
1928 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1929
1930 tess->lds_size = lds_size;
1931
1932 tess->tcs_in_layout = (input_patch_size / 4) |
1933 ((input_vertex_size / 4) << 13);
1934 tess->tcs_out_layout = (output_patch_size / 4) |
1935 ((output_vertex_size / 4) << 13);
1936 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1937 ((perpatch_output_offset / 16) << 16);
1938 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1939 (num_tcs_output_cp << 9) | num_patches;
1940
1941 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1942 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1943 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1944 tess->num_patches = num_patches;
1945 tess->num_tcs_input_cp = num_tcs_input_cp;
1946
1947 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1948 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1949
1950 switch (tes->info.tes.primitive_mode) {
1951 case GL_TRIANGLES:
1952 type = V_028B6C_TESS_TRIANGLE;
1953 break;
1954 case GL_QUADS:
1955 type = V_028B6C_TESS_QUAD;
1956 break;
1957 case GL_ISOLINES:
1958 type = V_028B6C_TESS_ISOLINE;
1959 break;
1960 }
1961
1962 switch (tes->info.tes.spacing) {
1963 case TESS_SPACING_EQUAL:
1964 partitioning = V_028B6C_PART_INTEGER;
1965 break;
1966 case TESS_SPACING_FRACTIONAL_ODD:
1967 partitioning = V_028B6C_PART_FRAC_ODD;
1968 break;
1969 case TESS_SPACING_FRACTIONAL_EVEN:
1970 partitioning = V_028B6C_PART_FRAC_EVEN;
1971 break;
1972 default:
1973 break;
1974 }
1975
1976 if (tes->info.tes.point_mode)
1977 topology = V_028B6C_OUTPUT_POINT;
1978 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1979 topology = V_028B6C_OUTPUT_LINE;
1980 else if (tes->info.tes.ccw)
1981 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1982 else
1983 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1984
1985 if (pipeline->device->has_distributed_tess) {
1986 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1987 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1988 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1989 else
1990 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1991 } else
1992 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1993
1994 tess->tf_param = S_028B6C_TYPE(type) |
1995 S_028B6C_PARTITIONING(partitioning) |
1996 S_028B6C_TOPOLOGY(topology) |
1997 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1998 }
1999
2000 static const struct radv_prim_vertex_count prim_size_table[] = {
2001 [V_008958_DI_PT_NONE] = {0, 0},
2002 [V_008958_DI_PT_POINTLIST] = {1, 1},
2003 [V_008958_DI_PT_LINELIST] = {2, 2},
2004 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2005 [V_008958_DI_PT_TRILIST] = {3, 3},
2006 [V_008958_DI_PT_TRIFAN] = {3, 1},
2007 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2008 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2009 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2010 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2011 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2012 [V_008958_DI_PT_RECTLIST] = {3, 3},
2013 [V_008958_DI_PT_LINELOOP] = {2, 1},
2014 [V_008958_DI_PT_POLYGON] = {3, 1},
2015 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2016 };
2017
2018 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
2019 {
2020 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
2021 unsigned cut_mode;
2022
2023 if (gs_max_vert_out <= 128) {
2024 cut_mode = V_028A40_GS_CUT_128;
2025 } else if (gs_max_vert_out <= 256) {
2026 cut_mode = V_028A40_GS_CUT_256;
2027 } else if (gs_max_vert_out <= 512) {
2028 cut_mode = V_028A40_GS_CUT_512;
2029 } else {
2030 assert(gs_max_vert_out <= 1024);
2031 cut_mode = V_028A40_GS_CUT_1024;
2032 }
2033
2034 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2035 S_028A40_CUT_MODE(cut_mode)|
2036 S_028A40_ES_WRITE_OPTIMIZE(1) |
2037 S_028A40_GS_WRITE_OPTIMIZE(1);
2038 }
2039
2040 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
2041 {
2042 struct radv_shader_variant *vs;
2043 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2044
2045 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
2046
2047 pipeline->graphics.vgt_primitiveid_en = false;
2048 pipeline->graphics.vgt_gs_mode = 0;
2049
2050 if (radv_pipeline_has_gs(pipeline)) {
2051 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
2052 } else if (outinfo->export_prim_id) {
2053 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2054 pipeline->graphics.vgt_primitiveid_en = true;
2055 }
2056 }
2057
2058 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
2059 {
2060 struct radv_shader_variant *vs;
2061 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2062
2063 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
2064
2065 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2066 clip_dist_mask = outinfo->clip_dist_mask;
2067 cull_dist_mask = outinfo->cull_dist_mask;
2068 total_mask = clip_dist_mask | cull_dist_mask;
2069
2070 bool misc_vec_ena = outinfo->writes_pointsize ||
2071 outinfo->writes_layer ||
2072 outinfo->writes_viewport_index;
2073 pipeline->graphics.pa_cl_vs_out_cntl =
2074 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2075 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2076 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2077 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2078 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2079 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2080 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2081 cull_dist_mask << 8 |
2082 clip_dist_mask;
2083
2084 }
2085
2086 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2087 {
2088 uint32_t ps_input_cntl;
2089 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2090 ps_input_cntl = S_028644_OFFSET(offset);
2091 if (flat_shade)
2092 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2093 } else {
2094 /* The input is a DEFAULT_VAL constant. */
2095 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2096 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2097 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2098 ps_input_cntl = S_028644_OFFSET(0x20) |
2099 S_028644_DEFAULT_VAL(offset);
2100 }
2101 return ps_input_cntl;
2102 }
2103
2104 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
2105 {
2106 struct radv_shader_variant *ps, *vs;
2107 struct ac_vs_output_info *outinfo;
2108
2109 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2110 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2111
2112 outinfo = &vs->info.vs.outinfo;
2113
2114 unsigned ps_offset = 0;
2115
2116 if (ps->info.fs.prim_id_input) {
2117 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2118 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2119 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2120 ++ps_offset;
2121 }
2122 }
2123
2124 if (ps->info.fs.layer_input) {
2125 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2126 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2127 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2128 else
2129 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2130 ++ps_offset;
2131 }
2132
2133 if (ps->info.fs.has_pcoord) {
2134 unsigned val;
2135 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2136 pipeline->graphics.ps_input_cntl[ps_offset] = val;
2137 ps_offset++;
2138 }
2139
2140 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2141 unsigned vs_offset;
2142 bool flat_shade;
2143 if (!(ps->info.fs.input_mask & (1u << i)))
2144 continue;
2145
2146 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2147 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2148 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2149 ++ps_offset;
2150 continue;
2151 }
2152
2153 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2154
2155 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2156 ++ps_offset;
2157 }
2158
2159 pipeline->graphics.ps_input_cntl_num = ps_offset;
2160 }
2161
2162 VkResult
2163 radv_pipeline_init(struct radv_pipeline *pipeline,
2164 struct radv_device *device,
2165 struct radv_pipeline_cache *cache,
2166 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2167 const struct radv_graphics_pipeline_create_info *extra,
2168 const VkAllocationCallbacks *alloc)
2169 {
2170 struct radv_shader_module fs_m = {0};
2171 VkResult result;
2172 bool has_view_index = false;
2173
2174 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2175 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2176 if (subpass->view_mask)
2177 has_view_index = true;
2178 if (alloc == NULL)
2179 alloc = &device->alloc;
2180
2181 pipeline->device = device;
2182 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2183
2184 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2185 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2186 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2187 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2188 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2189 pStages[stage] = &pCreateInfo->pStages[i];
2190 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
2191 }
2192
2193 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2194
2195 if (!modules[MESA_SHADER_FRAGMENT]) {
2196 nir_builder fs_b;
2197 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2198 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2199 fs_m.nir = fs_b.shader;
2200 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2201 }
2202
2203 if (modules[MESA_SHADER_FRAGMENT]) {
2204 struct ac_shader_variant_key key = {0};
2205 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
2206 if (pCreateInfo->pMultisampleState &&
2207 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
2208 key.fs.multisample = true;
2209
2210 if (pipeline->device->physical_device->rad_info.chip_class < VI)
2211 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);
2212
2213 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
2214
2215 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2216 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
2217 stage ? stage->pName : "main",
2218 MESA_SHADER_FRAGMENT,
2219 stage ? stage->pSpecializationInfo : NULL,
2220 pipeline->layout, &key);
2221 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
2222 }
2223
2224 if (fs_m.nir)
2225 ralloc_free(fs_m.nir);
2226
2227 if (modules[MESA_SHADER_VERTEX]) {
2228 bool as_es = false;
2229 bool as_ls = false;
2230 bool export_prim_id = false;
2231 if (modules[MESA_SHADER_TESS_CTRL])
2232 as_ls = true;
2233 else if (modules[MESA_SHADER_GEOMETRY])
2234 as_es = true;
2235 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2236 export_prim_id = true;
2237 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
2238 key.has_multiview_view_index = has_view_index;
2239
2240 pipeline->shaders[MESA_SHADER_VERTEX] =
2241 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
2242 pStages[MESA_SHADER_VERTEX]->pName,
2243 MESA_SHADER_VERTEX,
2244 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
2245 pipeline->layout, &key);
2246
2247 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
2248 }
2249
2250 if (modules[MESA_SHADER_GEOMETRY]) {
2251 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
2252 key.has_multiview_view_index = has_view_index;
2253
2254 pipeline->shaders[MESA_SHADER_GEOMETRY] =
2255 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
2256 pStages[MESA_SHADER_GEOMETRY]->pName,
2257 MESA_SHADER_GEOMETRY,
2258 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
2259 pipeline->layout, &key);
2260
2261 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
2262 }
2263
2264 if (modules[MESA_SHADER_TESS_EVAL]) {
2265 assert(modules[MESA_SHADER_TESS_CTRL]);
2266
2267 radv_tess_pipeline_compile(pipeline,
2268 cache,
2269 modules[MESA_SHADER_TESS_CTRL],
2270 modules[MESA_SHADER_TESS_EVAL],
2271 pStages[MESA_SHADER_TESS_CTRL]->pName,
2272 pStages[MESA_SHADER_TESS_EVAL]->pName,
2273 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
2274 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
2275 pipeline->layout,
2276 pCreateInfo->pTessellationState->patchControlPoints,
2277 has_view_index);
2278 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
2279 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
2280 }
2281
2282 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2283 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2284 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2285 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2286 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2287
2288 if (radv_pipeline_has_gs(pipeline)) {
2289 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2290 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2291 } else {
2292 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2293 }
2294 if (extra && extra->use_rectlist) {
2295 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2296 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2297 pipeline->graphics.can_use_guardband = true;
2298 }
2299 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2300 /* prim vertex count will need TESS changes */
2301 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2302
2303 /* Ensure that some export memory is always allocated, for two reasons:
2304 *
2305 * 1) Correctness: The hardware ignores the EXEC mask if no export
2306 * memory is allocated, so KILL and alpha test do not work correctly
2307 * without this.
2308 * 2) Performance: Every shader needs at least a NULL export, even when
2309 * it writes no color/depth output. The NULL export instruction
2310 * stalls without this setting.
2311 *
2312 * Don't add this to CB_SHADER_MASK.
2313 */
2314 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2315 if (!pipeline->graphics.blend.spi_shader_col_format) {
2316 if (!ps->info.fs.writes_z &&
2317 !ps->info.fs.writes_stencil &&
2318 !ps->info.fs.writes_sample_mask)
2319 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2320 }
2321
2322 unsigned z_order;
2323 pipeline->graphics.db_shader_control = 0;
2324 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2325 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2326 else
2327 z_order = V_02880C_LATE_Z;
2328
2329 pipeline->graphics.db_shader_control =
2330 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2331 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2332 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2333 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2334 S_02880C_Z_ORDER(z_order) |
2335 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2336 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2337 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2338
2339 if (pipeline->device->physical_device->has_rbplus)
2340 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
2341
2342 pipeline->graphics.shader_z_format =
2343 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2344 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2345 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2346 V_028710_SPI_SHADER_ZERO;
2347
2348 calculate_vgt_gs_mode(pipeline);
2349 calculate_pa_cl_vs_out_cntl(pipeline);
2350 calculate_ps_inputs(pipeline);
2351
2352 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2353 if (pipeline->shaders[i]) {
2354 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2355 }
2356 }
2357
2358 uint32_t stages = 0;
2359 if (radv_pipeline_has_tess(pipeline)) {
2360 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2361 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2362
2363 if (radv_pipeline_has_gs(pipeline))
2364 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2365 S_028B54_GS_EN(1) |
2366 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2367 else
2368 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2369
2370 } else if (radv_pipeline_has_gs(pipeline))
2371 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2372 S_028B54_GS_EN(1) |
2373 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2374
2375 if (device->physical_device->rad_info.chip_class >= GFX9)
2376 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2377
2378 pipeline->graphics.vgt_shader_stages_en = stages;
2379
2380 if (radv_pipeline_has_gs(pipeline))
2381 calculate_gs_ring_sizes(pipeline);
2382
2383 if (radv_pipeline_has_tess(pipeline)) {
2384 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2385 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2386 pipeline->graphics.prim_vertex_count.incr = 1;
2387 }
2388 calculate_tess_state(pipeline, pCreateInfo);
2389 }
2390
2391 const VkPipelineVertexInputStateCreateInfo *vi_info =
2392 pCreateInfo->pVertexInputState;
2393 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2394 const VkVertexInputAttributeDescription *desc =
2395 &vi_info->pVertexAttributeDescriptions[i];
2396 unsigned loc = desc->location;
2397 const struct vk_format_description *format_desc;
2398 int first_non_void;
2399 uint32_t num_format, data_format;
2400 format_desc = vk_format_description(desc->format);
2401 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2402
2403 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2404 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2405
2406 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2407 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2408 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2409 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2410 S_008F0C_NUM_FORMAT(num_format) |
2411 S_008F0C_DATA_FORMAT(data_format);
2412 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
2413 pipeline->va_offset[loc] = desc->offset;
2414 pipeline->va_binding[loc] = desc->binding;
2415 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
2416 }
2417
2418 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2419 const VkVertexInputBindingDescription *desc =
2420 &vi_info->pVertexBindingDescriptions[i];
2421
2422 pipeline->binding_stride[desc->binding] = desc->stride;
2423 }
2424
2425 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2426 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2427 if (loc->sgpr_idx != -1) {
2428 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2429 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2430 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2431 pipeline->graphics.vtx_emit_num = 3;
2432 else
2433 pipeline->graphics.vtx_emit_num = 2;
2434 }
2435 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2436 radv_dump_pipeline_stats(device, pipeline);
2437 }
2438
2439 result = radv_pipeline_scratch_init(device, pipeline);
2440 return result;
2441 }
2442
2443 VkResult
2444 radv_graphics_pipeline_create(
2445 VkDevice _device,
2446 VkPipelineCache _cache,
2447 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2448 const struct radv_graphics_pipeline_create_info *extra,
2449 const VkAllocationCallbacks *pAllocator,
2450 VkPipeline *pPipeline)
2451 {
2452 RADV_FROM_HANDLE(radv_device, device, _device);
2453 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2454 struct radv_pipeline *pipeline;
2455 VkResult result;
2456
2457 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2458 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2459 if (pipeline == NULL)
2460 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2461
2462 memset(pipeline, 0, sizeof(*pipeline));
2463 result = radv_pipeline_init(pipeline, device, cache,
2464 pCreateInfo, extra, pAllocator);
2465 if (result != VK_SUCCESS) {
2466 radv_pipeline_destroy(device, pipeline, pAllocator);
2467 return result;
2468 }
2469
2470 *pPipeline = radv_pipeline_to_handle(pipeline);
2471
2472 return VK_SUCCESS;
2473 }
2474
2475 VkResult radv_CreateGraphicsPipelines(
2476 VkDevice _device,
2477 VkPipelineCache pipelineCache,
2478 uint32_t count,
2479 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2480 const VkAllocationCallbacks* pAllocator,
2481 VkPipeline* pPipelines)
2482 {
2483 VkResult result = VK_SUCCESS;
2484 unsigned i = 0;
2485
2486 for (; i < count; i++) {
2487 VkResult r;
2488 r = radv_graphics_pipeline_create(_device,
2489 pipelineCache,
2490 &pCreateInfos[i],
2491 NULL, pAllocator, &pPipelines[i]);
2492 if (r != VK_SUCCESS) {
2493 result = r;
2494 pPipelines[i] = VK_NULL_HANDLE;
2495 }
2496 }
2497
2498 return result;
2499 }
2500
2501 static VkResult radv_compute_pipeline_create(
2502 VkDevice _device,
2503 VkPipelineCache _cache,
2504 const VkComputePipelineCreateInfo* pCreateInfo,
2505 const VkAllocationCallbacks* pAllocator,
2506 VkPipeline* pPipeline)
2507 {
2508 RADV_FROM_HANDLE(radv_device, device, _device);
2509 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2510 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2511 struct radv_pipeline *pipeline;
2512 VkResult result;
2513
2514 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2515 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2516 if (pipeline == NULL)
2517 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2518
2519 memset(pipeline, 0, sizeof(*pipeline));
2520 pipeline->device = device;
2521 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2522
2523 pipeline->shaders[MESA_SHADER_COMPUTE] =
2524 radv_pipeline_compile(pipeline, cache, module,
2525 pCreateInfo->stage.pName,
2526 MESA_SHADER_COMPUTE,
2527 pCreateInfo->stage.pSpecializationInfo,
2528 pipeline->layout, NULL);
2529
2530
2531 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2532 result = radv_pipeline_scratch_init(device, pipeline);
2533 if (result != VK_SUCCESS) {
2534 radv_pipeline_destroy(device, pipeline, pAllocator);
2535 return result;
2536 }
2537
2538 *pPipeline = radv_pipeline_to_handle(pipeline);
2539
2540 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2541 radv_dump_pipeline_stats(device, pipeline);
2542 }
2543 return VK_SUCCESS;
2544 }
2545 VkResult radv_CreateComputePipelines(
2546 VkDevice _device,
2547 VkPipelineCache pipelineCache,
2548 uint32_t count,
2549 const VkComputePipelineCreateInfo* pCreateInfos,
2550 const VkAllocationCallbacks* pAllocator,
2551 VkPipeline* pPipelines)
2552 {
2553 VkResult result = VK_SUCCESS;
2554
2555 unsigned i = 0;
2556 for (; i < count; i++) {
2557 VkResult r;
2558 r = radv_compute_pipeline_create(_device, pipelineCache,
2559 &pCreateInfos[i],
2560 pAllocator, &pPipelines[i]);
2561 if (r != VK_SUCCESS) {
2562 result = r;
2563 pPipelines[i] = VK_NULL_HANDLE;
2564 }
2565 }
2566
2567 return result;
2568 }
2569
2570 void *radv_alloc_shader_memory(struct radv_device *device,
2571 struct radv_shader_variant *shader)
2572 {
2573 mtx_lock(&device->shader_slab_mutex);
2574 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
2575 uint64_t offset = 0;
2576 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
2577 if (s->bo_offset - offset >= shader->code_size) {
2578 shader->bo = slab->bo;
2579 shader->bo_offset = offset;
2580 list_addtail(&shader->slab_list, &s->slab_list);
2581 mtx_unlock(&device->shader_slab_mutex);
2582 return slab->ptr + offset;
2583 }
2584 offset = align_u64(s->bo_offset + s->code_size, 256);
2585 }
2586 if (slab->size - offset >= shader->code_size) {
2587 shader->bo = slab->bo;
2588 shader->bo_offset = offset;
2589 list_addtail(&shader->slab_list, &slab->shaders);
2590 mtx_unlock(&device->shader_slab_mutex);
2591 return slab->ptr + offset;
2592 }
2593 }
2594
2595 mtx_unlock(&device->shader_slab_mutex);
2596 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
2597
2598 slab->size = 256 * 1024;
2599 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
2600 RADEON_DOMAIN_VRAM, 0);
2601 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
2602 list_inithead(&slab->shaders);
2603
2604 mtx_lock(&device->shader_slab_mutex);
2605 list_add(&slab->slabs, &device->shader_slabs);
2606
2607 shader->bo = slab->bo;
2608 shader->bo_offset = 0;
2609 list_add(&shader->slab_list, &slab->shaders);
2610 mtx_unlock(&device->shader_slab_mutex);
2611 return slab->ptr;
2612 }
2613
2614 void radv_destroy_shader_slabs(struct radv_device *device)
2615 {
2616 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
2617 device->ws->buffer_destroy(slab->bo);
2618 free(slab);
2619 }
2620 mtx_destroy(&device->shader_slab_mutex);
2621 }