2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 void radv_shader_variant_destroy(struct radv_device
*device
,
45 struct radv_shader_variant
*variant
);
47 static const struct nir_shader_compiler_options nir_options
= {
48 .vertex_id_zero_based
= true,
52 .lower_pack_snorm_2x16
= true,
53 .lower_pack_snorm_4x8
= true,
54 .lower_pack_unorm_2x16
= true,
55 .lower_pack_unorm_4x8
= true,
56 .lower_unpack_snorm_2x16
= true,
57 .lower_unpack_snorm_4x8
= true,
58 .lower_unpack_unorm_2x16
= true,
59 .lower_unpack_unorm_4x8
= true,
60 .lower_extract_byte
= true,
61 .lower_extract_word
= true,
64 VkResult
radv_CreateShaderModule(
66 const VkShaderModuleCreateInfo
* pCreateInfo
,
67 const VkAllocationCallbacks
* pAllocator
,
68 VkShaderModule
* pShaderModule
)
70 RADV_FROM_HANDLE(radv_device
, device
, _device
);
71 struct radv_shader_module
*module
;
73 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
74 assert(pCreateInfo
->flags
== 0);
76 module
= vk_alloc2(&device
->alloc
, pAllocator
,
77 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
78 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
80 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
83 module
->size
= pCreateInfo
->codeSize
;
84 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
86 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
88 *pShaderModule
= radv_shader_module_to_handle(module
);
93 void radv_DestroyShaderModule(
95 VkShaderModule _module
,
96 const VkAllocationCallbacks
* pAllocator
)
98 RADV_FROM_HANDLE(radv_device
, device
, _device
);
99 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
104 vk_free2(&device
->alloc
, pAllocator
, module
);
107 void radv_DestroyPipeline(
109 VkPipeline _pipeline
,
110 const VkAllocationCallbacks
* pAllocator
)
112 RADV_FROM_HANDLE(radv_device
, device
, _device
);
113 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
118 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
119 if (pipeline
->shaders
[i
])
120 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
122 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
127 radv_optimize_nir(struct nir_shader
*shader
)
134 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
135 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
136 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
138 NIR_PASS(progress
, shader
, nir_copy_prop
);
139 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
140 NIR_PASS(progress
, shader
, nir_opt_dce
);
141 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
142 NIR_PASS(progress
, shader
, nir_opt_cse
);
143 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8);
144 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
145 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
146 NIR_PASS(progress
, shader
, nir_opt_undef
);
147 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
152 radv_shader_compile_to_nir(struct radv_device
*device
,
153 struct radv_shader_module
*module
,
154 const char *entrypoint_name
,
155 gl_shader_stage stage
,
156 const VkSpecializationInfo
*spec_info
,
159 if (strcmp(entrypoint_name
, "main") != 0) {
160 radv_finishme("Multiple shaders per module not really supported");
164 nir_function
*entry_point
;
166 /* Some things such as our meta clear/blit code will give us a NIR
167 * shader directly. In that case, we just ignore the SPIR-V entirely
168 * and just use the NIR shader */
170 nir
->options
= &nir_options
;
171 nir_validate_shader(nir
);
173 assert(exec_list_length(&nir
->functions
) == 1);
174 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
175 entry_point
= exec_node_data(nir_function
, node
, node
);
177 uint32_t *spirv
= (uint32_t *) module
->data
;
178 assert(module
->size
% 4 == 0);
180 uint32_t num_spec_entries
= 0;
181 struct nir_spirv_specialization
*spec_entries
= NULL
;
182 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
183 num_spec_entries
= spec_info
->mapEntryCount
;
184 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
185 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
186 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
187 const void *data
= spec_info
->pData
+ entry
.offset
;
188 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
190 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
191 spec_entries
[i
].data
= *(const uint32_t *)data
;
195 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
196 spec_entries
, num_spec_entries
,
197 stage
, entrypoint_name
, &nir_options
);
198 nir
= entry_point
->shader
;
199 assert(nir
->stage
== stage
);
200 nir_validate_shader(nir
);
204 nir_lower_returns(nir
);
205 nir_validate_shader(nir
);
207 nir_inline_functions(nir
);
208 nir_validate_shader(nir
);
210 /* Pick off the single entrypoint that we want */
211 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
212 if (func
!= entry_point
)
213 exec_node_remove(&func
->node
);
215 assert(exec_list_length(&nir
->functions
) == 1);
216 entry_point
->name
= ralloc_strdup(entry_point
, "main");
218 nir_remove_dead_variables(nir
, nir_var_shader_in
);
219 nir_remove_dead_variables(nir
, nir_var_shader_out
);
220 nir_remove_dead_variables(nir
, nir_var_system_value
);
221 nir_validate_shader(nir
);
223 nir_lower_system_values(nir
);
224 nir_validate_shader(nir
);
227 /* Vulkan uses the separate-shader linking model */
228 nir
->info
->separate_shader
= true;
230 // nir = brw_preprocess_nir(compiler, nir);
232 nir_shader_gather_info(nir
, entry_point
->impl
);
234 nir_variable_mode indirect_mask
= 0;
235 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
236 indirect_mask
|= nir_var_shader_in
;
237 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
238 indirect_mask
|= nir_var_local
;
240 nir_lower_indirect_derefs(nir
, indirect_mask
);
242 static const nir_lower_tex_options tex_options
= {
246 nir_lower_tex(nir
, &tex_options
);
248 nir_lower_vars_to_ssa(nir
);
249 nir_lower_var_copies(nir
);
250 nir_lower_global_vars_to_local(nir
);
251 nir_remove_dead_variables(nir
, nir_var_local
);
252 radv_optimize_nir(nir
);
255 nir_print_shader(nir
, stderr
);
260 void radv_shader_variant_destroy(struct radv_device
*device
,
261 struct radv_shader_variant
*variant
)
263 if (__sync_fetch_and_sub(&variant
->ref_count
, 1) != 1)
266 device
->ws
->buffer_destroy(variant
->bo
);
271 struct radv_shader_variant
*radv_shader_variant_create(struct radv_device
*device
,
272 struct nir_shader
*shader
,
273 struct radv_pipeline_layout
*layout
,
274 const union ac_shader_variant_key
*key
,
276 unsigned *code_size_out
,
279 struct radv_shader_variant
*variant
= calloc(1, sizeof(struct radv_shader_variant
));
280 enum radeon_family chip_family
= device
->instance
->physicalDevice
.rad_info
.family
;
281 LLVMTargetMachineRef tm
;
285 struct ac_nir_compiler_options options
= {0};
286 options
.layout
= layout
;
290 struct ac_shader_binary binary
;
292 options
.unsafe_math
= env_var_as_boolean("RADV_UNSAFE_MATH", false);
293 options
.family
= chip_family
;
294 options
.chip_class
= device
->instance
->physicalDevice
.rad_info
.chip_class
;
295 tm
= ac_create_target_machine(chip_family
);
296 ac_compile_nir_shader(tm
, &binary
, &variant
->config
,
297 &variant
->info
, shader
, &options
, dump
);
298 LLVMDisposeTargetMachine(tm
);
300 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
301 unsigned vgpr_comp_cnt
= 0;
304 radv_finishme("shader scratch space");
305 switch (shader
->stage
) {
306 case MESA_SHADER_VERTEX
:
307 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
308 S_00B12C_SCRATCH_EN(scratch_enabled
);
309 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
311 case MESA_SHADER_FRAGMENT
:
312 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
313 S_00B12C_SCRATCH_EN(scratch_enabled
);
315 case MESA_SHADER_COMPUTE
:
316 variant
->rsrc2
= S_00B84C_USER_SGPR(variant
->info
.num_user_sgprs
) |
317 S_00B84C_SCRATCH_EN(scratch_enabled
) |
318 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
319 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
320 S_00B84C_TG_SIZE_EN(1) |
321 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
324 unreachable("unsupported shader type");
328 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
329 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
330 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
331 S_00B848_DX10_CLAMP(1) |
332 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
334 variant
->bo
= device
->ws
->buffer_create(device
->ws
, binary
.code_size
, 256,
335 RADEON_DOMAIN_GTT
, RADEON_FLAG_CPU_ACCESS
);
337 void *ptr
= device
->ws
->buffer_map(variant
->bo
);
338 memcpy(ptr
, binary
.code
, binary
.code_size
);
339 device
->ws
->buffer_unmap(variant
->bo
);
342 *code_out
= binary
.code
;
343 *code_size_out
= binary
.code_size
;
348 free(binary
.global_symbol_offsets
);
350 free(binary
.disasm_string
);
351 variant
->ref_count
= 1;
356 static struct radv_shader_variant
*
357 radv_pipeline_compile(struct radv_pipeline
*pipeline
,
358 struct radv_pipeline_cache
*cache
,
359 struct radv_shader_module
*module
,
360 const char *entrypoint
,
361 gl_shader_stage stage
,
362 const VkSpecializationInfo
*spec_info
,
363 struct radv_pipeline_layout
*layout
,
364 const union ac_shader_variant_key
*key
,
367 unsigned char sha1
[20];
368 struct radv_shader_variant
*variant
;
371 unsigned code_size
= 0;
374 _mesa_sha1_compute(module
->nir
->info
->name
,
375 strlen(module
->nir
->info
->name
),
378 radv_hash_shader(sha1
, module
, entrypoint
, spec_info
, layout
, key
);
381 variant
= radv_create_shader_variant_from_pipeline_cache(pipeline
->device
,
388 nir
= radv_shader_compile_to_nir(pipeline
->device
,
389 module
, entrypoint
, stage
,
394 variant
= radv_shader_variant_create(pipeline
->device
, nir
, layout
, key
,
395 &code
, &code_size
, dump
);
399 if (variant
&& cache
)
400 variant
= radv_pipeline_cache_insert_shader(cache
, sha1
, variant
,
408 static uint32_t si_translate_blend_function(VkBlendOp op
)
411 case VK_BLEND_OP_ADD
:
412 return V_028780_COMB_DST_PLUS_SRC
;
413 case VK_BLEND_OP_SUBTRACT
:
414 return V_028780_COMB_SRC_MINUS_DST
;
415 case VK_BLEND_OP_REVERSE_SUBTRACT
:
416 return V_028780_COMB_DST_MINUS_SRC
;
417 case VK_BLEND_OP_MIN
:
418 return V_028780_COMB_MIN_DST_SRC
;
419 case VK_BLEND_OP_MAX
:
420 return V_028780_COMB_MAX_DST_SRC
;
426 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
429 case VK_BLEND_FACTOR_ZERO
:
430 return V_028780_BLEND_ZERO
;
431 case VK_BLEND_FACTOR_ONE
:
432 return V_028780_BLEND_ONE
;
433 case VK_BLEND_FACTOR_SRC_COLOR
:
434 return V_028780_BLEND_SRC_COLOR
;
435 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
436 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
437 case VK_BLEND_FACTOR_DST_COLOR
:
438 return V_028780_BLEND_DST_COLOR
;
439 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
440 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
441 case VK_BLEND_FACTOR_SRC_ALPHA
:
442 return V_028780_BLEND_SRC_ALPHA
;
443 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
444 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
445 case VK_BLEND_FACTOR_DST_ALPHA
:
446 return V_028780_BLEND_DST_ALPHA
;
447 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
448 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
449 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
450 return V_028780_BLEND_CONSTANT_COLOR
;
451 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
452 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
453 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
454 return V_028780_BLEND_CONSTANT_ALPHA
;
455 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
456 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
457 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
458 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
459 case VK_BLEND_FACTOR_SRC1_COLOR
:
460 return V_028780_BLEND_SRC1_COLOR
;
461 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
462 return V_028780_BLEND_INV_SRC1_COLOR
;
463 case VK_BLEND_FACTOR_SRC1_ALPHA
:
464 return V_028780_BLEND_SRC1_ALPHA
;
465 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
466 return V_028780_BLEND_INV_SRC1_ALPHA
;
472 static bool is_dual_src(VkBlendFactor factor
)
475 case VK_BLEND_FACTOR_SRC1_COLOR
:
476 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
477 case VK_BLEND_FACTOR_SRC1_ALPHA
:
478 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
485 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
487 bool blend_need_alpha
)
489 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
490 unsigned format
, ntype
, swap
;
492 /* Alpha is needed for alpha-to-coverage.
493 * Blending may be with or without alpha.
495 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
496 unsigned alpha
= 0; /* exports alpha, but may not support blending */
497 unsigned blend
= 0; /* supports blending, but may not export alpha */
498 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
500 format
= radv_translate_colorformat(vk_format
);
501 ntype
= radv_translate_color_numformat(vk_format
, desc
,
502 vk_format_get_first_non_void_channel(vk_format
));
503 swap
= radv_translate_colorswap(vk_format
, false);
505 /* Choose the SPI color formats. These are required values for Stoney/RB+.
506 * Other chips have multiple choices, though they are not necessarily better.
509 case V_028C70_COLOR_5_6_5
:
510 case V_028C70_COLOR_1_5_5_5
:
511 case V_028C70_COLOR_5_5_5_1
:
512 case V_028C70_COLOR_4_4_4_4
:
513 case V_028C70_COLOR_10_11_11
:
514 case V_028C70_COLOR_11_11_10
:
515 case V_028C70_COLOR_8
:
516 case V_028C70_COLOR_8_8
:
517 case V_028C70_COLOR_8_8_8_8
:
518 case V_028C70_COLOR_10_10_10_2
:
519 case V_028C70_COLOR_2_10_10_10
:
520 if (ntype
== V_028C70_NUMBER_UINT
)
521 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
522 else if (ntype
== V_028C70_NUMBER_SINT
)
523 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
525 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
528 case V_028C70_COLOR_16
:
529 case V_028C70_COLOR_16_16
:
530 case V_028C70_COLOR_16_16_16_16
:
531 if (ntype
== V_028C70_NUMBER_UNORM
||
532 ntype
== V_028C70_NUMBER_SNORM
) {
533 /* UNORM16 and SNORM16 don't support blending */
534 if (ntype
== V_028C70_NUMBER_UNORM
)
535 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
537 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
539 /* Use 32 bits per channel for blending. */
540 if (format
== V_028C70_COLOR_16
) {
541 if (swap
== V_028C70_SWAP_STD
) { /* R */
542 blend
= V_028714_SPI_SHADER_32_R
;
543 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
544 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
545 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
548 } else if (format
== V_028C70_COLOR_16_16
) {
549 if (swap
== V_028C70_SWAP_STD
) { /* RG */
550 blend
= V_028714_SPI_SHADER_32_GR
;
551 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
552 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
553 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
556 } else /* 16_16_16_16 */
557 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
558 } else if (ntype
== V_028C70_NUMBER_UINT
)
559 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
560 else if (ntype
== V_028C70_NUMBER_SINT
)
561 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
562 else if (ntype
== V_028C70_NUMBER_FLOAT
)
563 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
568 case V_028C70_COLOR_32
:
569 if (swap
== V_028C70_SWAP_STD
) { /* R */
570 blend
= normal
= V_028714_SPI_SHADER_32_R
;
571 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
572 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
573 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
578 case V_028C70_COLOR_32_32
:
579 if (swap
== V_028C70_SWAP_STD
) { /* RG */
580 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
581 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
582 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
583 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
588 case V_028C70_COLOR_32_32_32_32
:
589 case V_028C70_COLOR_8_24
:
590 case V_028C70_COLOR_24_8
:
591 case V_028C70_COLOR_X24_8_32_FLOAT
:
592 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
596 unreachable("unhandled blend format");
599 if (blend_enable
&& blend_need_alpha
)
601 else if(blend_need_alpha
)
603 else if(blend_enable
)
609 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
611 unsigned i
, cb_shader_mask
= 0;
613 for (i
= 0; i
< 8; i
++) {
614 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
615 case V_028714_SPI_SHADER_ZERO
:
617 case V_028714_SPI_SHADER_32_R
:
618 cb_shader_mask
|= 0x1 << (i
* 4);
620 case V_028714_SPI_SHADER_32_GR
:
621 cb_shader_mask
|= 0x3 << (i
* 4);
623 case V_028714_SPI_SHADER_32_AR
:
624 cb_shader_mask
|= 0x9 << (i
* 4);
626 case V_028714_SPI_SHADER_FP16_ABGR
:
627 case V_028714_SPI_SHADER_UNORM16_ABGR
:
628 case V_028714_SPI_SHADER_SNORM16_ABGR
:
629 case V_028714_SPI_SHADER_UINT16_ABGR
:
630 case V_028714_SPI_SHADER_SINT16_ABGR
:
631 case V_028714_SPI_SHADER_32_ABGR
:
632 cb_shader_mask
|= 0xf << (i
* 4);
638 return cb_shader_mask
;
642 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
643 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
644 uint32_t blend_enable
,
645 uint32_t blend_need_alpha
,
646 bool single_cb_enable
,
647 bool blend_mrt0_is_dual_src
)
649 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
650 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
651 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
652 unsigned col_format
= 0;
654 for (unsigned i
= 0; i
< (single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
655 struct radv_render_pass_attachment
*attachment
;
658 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
660 cf
= si_choose_spi_color_format(attachment
->format
,
661 blend_enable
& (1 << i
),
662 blend_need_alpha
& (1 << i
));
664 col_format
|= cf
<< (4 * i
);
667 blend
->cb_shader_mask
= si_get_cb_shader_mask(col_format
);
669 if (blend_mrt0_is_dual_src
)
670 col_format
|= (col_format
& 0xf) << 4;
672 col_format
|= V_028714_SPI_SHADER_32_R
;
673 blend
->spi_shader_col_format
= col_format
;
677 format_is_int8(VkFormat format
)
679 const struct vk_format_description
*desc
= vk_format_description(format
);
680 int channel
= vk_format_get_first_non_void_channel(format
);
682 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
683 desc
->channel
[channel
].size
== 8;
686 unsigned radv_format_meta_fs_key(VkFormat format
)
688 unsigned col_format
= si_choose_spi_color_format(format
, false, false) - 1;
689 bool is_int8
= format_is_int8(format
);
691 return col_format
+ (is_int8
? 3 : 0);
695 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
697 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
698 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
699 unsigned is_int8
= 0;
701 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
702 struct radv_render_pass_attachment
*attachment
;
704 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
706 if (format_is_int8(attachment
->format
))
714 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
715 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
716 const struct radv_graphics_pipeline_create_info
*extra
)
718 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
719 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
720 unsigned mode
= V_028808_CB_NORMAL
;
721 uint32_t blend_enable
= 0, blend_need_alpha
= 0;
722 bool blend_mrt0_is_dual_src
= false;
724 bool single_cb_enable
= false;
729 if (extra
&& extra
->custom_blend_mode
) {
730 single_cb_enable
= true;
731 mode
= extra
->custom_blend_mode
;
733 blend
->cb_color_control
= 0;
734 if (vkblend
->logicOpEnable
)
735 blend
->cb_color_control
|= S_028808_ROP3(vkblend
->logicOp
| (vkblend
->logicOp
<< 4));
737 blend
->cb_color_control
|= S_028808_ROP3(0xcc);
739 blend
->db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
740 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
741 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
742 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
744 blend
->cb_target_mask
= 0;
745 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
746 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
747 unsigned blend_cntl
= 0;
748 VkBlendOp eqRGB
= att
->colorBlendOp
;
749 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
750 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
751 VkBlendOp eqA
= att
->alphaBlendOp
;
752 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
753 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
755 blend
->sx_mrt0_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
757 if (!att
->colorWriteMask
)
760 blend
->cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
761 if (!att
->blendEnable
) {
762 blend
->cb_blend_control
[i
] = blend_cntl
;
766 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
768 blend_mrt0_is_dual_src
= true;
770 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
771 srcRGB
= VK_BLEND_FACTOR_ONE
;
772 dstRGB
= VK_BLEND_FACTOR_ONE
;
774 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
775 srcA
= VK_BLEND_FACTOR_ONE
;
776 dstA
= VK_BLEND_FACTOR_ONE
;
779 blend_cntl
|= S_028780_ENABLE(1);
781 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
782 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
783 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
784 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
785 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
786 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
787 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
788 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
790 blend
->cb_blend_control
[i
] = blend_cntl
;
792 blend_enable
|= 1 << i
;
794 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
795 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
796 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
797 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
798 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
799 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
800 blend_need_alpha
|= 1 << i
;
802 for (i
= vkblend
->attachmentCount
; i
< 8; i
++)
803 blend
->cb_blend_control
[i
] = 0;
805 if (blend
->cb_target_mask
)
806 blend
->cb_color_control
|= S_028808_MODE(mode
);
808 blend
->cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
810 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
,
811 blend_enable
, blend_need_alpha
, single_cb_enable
, blend_mrt0_is_dual_src
);
814 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
817 case VK_STENCIL_OP_KEEP
:
818 return V_02842C_STENCIL_KEEP
;
819 case VK_STENCIL_OP_ZERO
:
820 return V_02842C_STENCIL_ZERO
;
821 case VK_STENCIL_OP_REPLACE
:
822 return V_02842C_STENCIL_REPLACE_TEST
;
823 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
824 return V_02842C_STENCIL_ADD_CLAMP
;
825 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
826 return V_02842C_STENCIL_SUB_CLAMP
;
827 case VK_STENCIL_OP_INVERT
:
828 return V_02842C_STENCIL_INVERT
;
829 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
830 return V_02842C_STENCIL_ADD_WRAP
;
831 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
832 return V_02842C_STENCIL_SUB_WRAP
;
838 radv_pipeline_init_depth_stencil_state(struct radv_pipeline
*pipeline
,
839 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
840 const struct radv_graphics_pipeline_create_info
*extra
)
842 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
843 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
845 memset(ds
, 0, sizeof(*ds
));
848 ds
->db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
849 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
850 S_028800_ZFUNC(vkds
->depthCompareOp
) |
851 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
853 if (vkds
->stencilTestEnable
) {
854 ds
->db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
855 ds
->db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
856 ds
->db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
857 ds
->db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
858 ds
->db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
860 ds
->db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
861 ds
->db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
862 ds
->db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
863 ds
->db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
868 ds
->db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
869 ds
->db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
871 ds
->db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
872 ds
->db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
873 ds
->db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
874 ds
->db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
875 ds
->db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
879 static uint32_t si_translate_fill(VkPolygonMode func
)
882 case VK_POLYGON_MODE_FILL
:
883 return V_028814_X_DRAW_TRIANGLES
;
884 case VK_POLYGON_MODE_LINE
:
885 return V_028814_X_DRAW_LINES
;
886 case VK_POLYGON_MODE_POINT
:
887 return V_028814_X_DRAW_POINTS
;
890 return V_028814_X_DRAW_POINTS
;
894 radv_pipeline_init_raster_state(struct radv_pipeline
*pipeline
,
895 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
897 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
898 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
900 memset(raster
, 0, sizeof(*raster
));
902 raster
->spi_interp_control
=
903 S_0286D4_FLAT_SHADE_ENA(1) |
904 S_0286D4_PNT_SPRITE_ENA(1) |
905 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
906 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
907 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
908 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
909 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
911 raster
->pa_cl_vs_out_cntl
= S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
912 raster
->pa_cl_clip_cntl
= S_028810_PS_UCP_MODE(3) |
913 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
914 S_028810_ZCLIP_NEAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
915 S_028810_ZCLIP_FAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
916 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
917 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
919 raster
->pa_su_vtx_cntl
=
920 S_028BE4_PIX_CENTER(1) | // TODO verify
921 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
922 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
);
924 raster
->pa_su_sc_mode_cntl
=
925 S_028814_FACE(vkraster
->frontFace
) |
926 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
927 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
928 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
929 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
930 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
931 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
932 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
933 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0);
938 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
939 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
941 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
942 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
943 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
944 unsigned num_tile_pipes
= pipeline
->device
->instance
->physicalDevice
.rad_info
.num_tile_pipes
;
945 int ps_iter_samples
= 1;
946 uint32_t mask
= 0xffff;
948 ms
->num_samples
= vkms
->rasterizationSamples
;
949 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
950 ms
->pa_sc_aa_config
= 0;
951 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
952 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
953 ms
->pa_sc_mode_cntl_1
=
954 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
955 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
957 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
958 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
959 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
960 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
961 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
962 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
964 if (vkms
->rasterizationSamples
> 1) {
965 unsigned log_samples
= util_logbase2(vkms
->rasterizationSamples
);
966 unsigned log_ps_iter_samples
= util_logbase2(util_next_power_of_two(ps_iter_samples
));
967 ms
->pa_sc_mode_cntl_0
= S_028A48_MSAA_ENABLE(1);
968 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
969 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
970 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
971 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
972 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
973 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
974 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples
)) |
975 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
976 ms
->pa_sc_mode_cntl_1
|= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
979 if (vkms
->alphaToCoverageEnable
)
980 blend
->db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
982 if (vkms
->pSampleMask
) {
983 mask
= vkms
->pSampleMask
[0] & 0xffff;
986 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
987 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
991 si_translate_prim(enum VkPrimitiveTopology topology
)
994 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
995 return V_008958_DI_PT_POINTLIST
;
996 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
997 return V_008958_DI_PT_LINELIST
;
998 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
999 return V_008958_DI_PT_LINESTRIP
;
1000 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1001 return V_008958_DI_PT_TRILIST
;
1002 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1003 return V_008958_DI_PT_TRISTRIP
;
1004 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1005 return V_008958_DI_PT_TRIFAN
;
1006 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1007 return V_008958_DI_PT_LINELIST_ADJ
;
1008 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1009 return V_008958_DI_PT_LINESTRIP_ADJ
;
1010 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1011 return V_008958_DI_PT_TRILIST_ADJ
;
1012 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1013 return V_008958_DI_PT_TRISTRIP_ADJ
;
1014 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1015 return V_008958_DI_PT_PATCH
;
1023 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1026 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1027 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1028 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1029 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1030 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1031 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1032 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1033 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1034 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1035 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1036 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1037 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1038 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1039 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1046 static unsigned si_map_swizzle(unsigned swizzle
)
1050 return V_008F0C_SQ_SEL_Y
;
1052 return V_008F0C_SQ_SEL_Z
;
1054 return V_008F0C_SQ_SEL_W
;
1056 return V_008F0C_SQ_SEL_0
;
1058 return V_008F0C_SQ_SEL_1
;
1059 default: /* VK_SWIZZLE_X */
1060 return V_008F0C_SQ_SEL_X
;
1065 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1066 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1068 radv_cmd_dirty_mask_t states
= RADV_CMD_DIRTY_DYNAMIC_ALL
;
1069 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1070 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1072 pipeline
->dynamic_state
= default_dynamic_state
;
1074 if (pCreateInfo
->pDynamicState
) {
1075 /* Remove all of the states that are marked as dynamic */
1076 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1077 for (uint32_t s
= 0; s
< count
; s
++)
1078 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1081 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1083 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1085 * pViewportState is [...] NULL if the pipeline
1086 * has rasterization disabled.
1088 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1089 assert(pCreateInfo
->pViewportState
);
1091 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1092 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1093 typed_memcpy(dynamic
->viewport
.viewports
,
1094 pCreateInfo
->pViewportState
->pViewports
,
1095 pCreateInfo
->pViewportState
->viewportCount
);
1098 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1099 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1100 typed_memcpy(dynamic
->scissor
.scissors
,
1101 pCreateInfo
->pViewportState
->pScissors
,
1102 pCreateInfo
->pViewportState
->scissorCount
);
1106 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1107 assert(pCreateInfo
->pRasterizationState
);
1108 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1111 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1112 assert(pCreateInfo
->pRasterizationState
);
1113 dynamic
->depth_bias
.bias
=
1114 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1115 dynamic
->depth_bias
.clamp
=
1116 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1117 dynamic
->depth_bias
.slope
=
1118 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1121 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1123 * pColorBlendState is [...] NULL if the pipeline has rasterization
1124 * disabled or if the subpass of the render pass the pipeline is
1125 * created against does not use any color attachments.
1127 bool uses_color_att
= false;
1128 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1129 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1130 uses_color_att
= true;
1135 if (uses_color_att
&& states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
1136 assert(pCreateInfo
->pColorBlendState
);
1137 typed_memcpy(dynamic
->blend_constants
,
1138 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1141 /* If there is no depthstencil attachment, then don't read
1142 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1143 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1144 * no need to override the depthstencil defaults in
1145 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1147 * Section 9.2 of the Vulkan 1.0.15 spec says:
1149 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1150 * disabled or if the subpass of the render pass the pipeline is created
1151 * against does not use a depth/stencil attachment.
1153 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1154 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1155 assert(pCreateInfo
->pDepthStencilState
);
1157 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1158 dynamic
->depth_bounds
.min
=
1159 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1160 dynamic
->depth_bounds
.max
=
1161 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1164 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1165 dynamic
->stencil_compare_mask
.front
=
1166 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1167 dynamic
->stencil_compare_mask
.back
=
1168 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1171 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1172 dynamic
->stencil_write_mask
.front
=
1173 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1174 dynamic
->stencil_write_mask
.back
=
1175 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1178 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1179 dynamic
->stencil_reference
.front
=
1180 pCreateInfo
->pDepthStencilState
->front
.reference
;
1181 dynamic
->stencil_reference
.back
=
1182 pCreateInfo
->pDepthStencilState
->back
.reference
;
1186 pipeline
->dynamic_state_mask
= states
;
1189 static union ac_shader_variant_key
1190 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1192 union ac_shader_variant_key key
;
1193 const VkPipelineVertexInputStateCreateInfo
*input_state
=
1194 pCreateInfo
->pVertexInputState
;
1196 memset(&key
, 0, sizeof(key
));
1197 key
.vs
.instance_rate_inputs
= 0;
1199 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
1201 binding
= input_state
->pVertexAttributeDescriptions
[i
].binding
;
1202 if (input_state
->pVertexBindingDescriptions
[binding
].inputRate
)
1203 key
.vs
.instance_rate_inputs
|= 1u << input_state
->pVertexAttributeDescriptions
[i
].location
;
1209 radv_pipeline_init(struct radv_pipeline
*pipeline
,
1210 struct radv_device
*device
,
1211 struct radv_pipeline_cache
*cache
,
1212 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1213 const struct radv_graphics_pipeline_create_info
*extra
,
1214 const VkAllocationCallbacks
*alloc
)
1216 struct radv_shader_module fs_m
= {0};
1218 bool dump
= getenv("RADV_DUMP_SHADERS");
1220 alloc
= &device
->alloc
;
1222 pipeline
->device
= device
;
1223 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1225 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
1226 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1227 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1228 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1229 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1230 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1231 modules
[stage
] = radv_shader_module_from_handle(pStages
[stage
]->module
);
1234 radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
1237 if (modules
[MESA_SHADER_VERTEX
]) {
1238 union ac_shader_variant_key key
= radv_compute_vs_key(pCreateInfo
);
1240 pipeline
->shaders
[MESA_SHADER_VERTEX
] =
1241 radv_pipeline_compile(pipeline
, cache
, modules
[MESA_SHADER_VERTEX
],
1242 pStages
[MESA_SHADER_VERTEX
]->pName
,
1244 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
,
1245 pipeline
->layout
, &key
, dump
);
1247 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX
);
1250 if (!modules
[MESA_SHADER_FRAGMENT
]) {
1252 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
1253 fs_b
.shader
->info
->name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
1254 fs_m
.nir
= fs_b
.shader
;
1255 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
1258 if (modules
[MESA_SHADER_FRAGMENT
]) {
1259 union ac_shader_variant_key key
;
1260 key
.fs
.col_format
= pipeline
->graphics
.blend
.spi_shader_col_format
;
1261 key
.fs
.is_int8
= radv_pipeline_compute_is_int8(pCreateInfo
);
1263 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[MESA_SHADER_FRAGMENT
];
1265 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
1266 radv_pipeline_compile(pipeline
, cache
, modules
[MESA_SHADER_FRAGMENT
],
1267 stage
? stage
->pName
: "main",
1268 MESA_SHADER_FRAGMENT
,
1269 stage
? stage
->pSpecializationInfo
: NULL
,
1270 pipeline
->layout
, &key
, dump
);
1271 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT
);
1275 ralloc_free(fs_m
.nir
);
1277 radv_pipeline_init_depth_stencil_state(pipeline
, pCreateInfo
, extra
);
1278 radv_pipeline_init_raster_state(pipeline
, pCreateInfo
);
1279 radv_pipeline_init_multisample_state(pipeline
, pCreateInfo
);
1280 pipeline
->graphics
.prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
1281 pipeline
->graphics
.gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
1282 if (extra
&& extra
->use_rectlist
) {
1283 pipeline
->graphics
.prim
= V_008958_DI_PT_RECTLIST
;
1284 pipeline
->graphics
.gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1286 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
1288 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1289 pCreateInfo
->pVertexInputState
;
1290 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1291 const VkVertexInputAttributeDescription
*desc
=
1292 &vi_info
->pVertexAttributeDescriptions
[i
];
1293 unsigned loc
= desc
->location
;
1294 const struct vk_format_description
*format_desc
;
1296 uint32_t num_format
, data_format
;
1297 format_desc
= vk_format_description(desc
->format
);
1298 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
1300 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
1301 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
1303 pipeline
->va_rsrc_word3
[loc
] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc
->swizzle
[0])) |
1304 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc
->swizzle
[1])) |
1305 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc
->swizzle
[2])) |
1306 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc
->swizzle
[3])) |
1307 S_008F0C_NUM_FORMAT(num_format
) |
1308 S_008F0C_DATA_FORMAT(data_format
);
1309 pipeline
->va_format_size
[loc
] = format_desc
->block
.bits
/ 8;
1310 pipeline
->va_offset
[loc
] = desc
->offset
;
1311 pipeline
->va_binding
[loc
] = desc
->binding
;
1312 pipeline
->num_vertex_attribs
= MAX2(pipeline
->num_vertex_attribs
, loc
+ 1);
1315 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1316 const VkVertexInputBindingDescription
*desc
=
1317 &vi_info
->pVertexBindingDescriptions
[i
];
1319 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1326 radv_graphics_pipeline_create(
1328 VkPipelineCache _cache
,
1329 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1330 const struct radv_graphics_pipeline_create_info
*extra
,
1331 const VkAllocationCallbacks
*pAllocator
,
1332 VkPipeline
*pPipeline
)
1334 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1335 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
1336 struct radv_pipeline
*pipeline
;
1339 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1340 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1341 if (pipeline
== NULL
)
1342 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1344 memset(pipeline
, 0, sizeof(*pipeline
));
1345 result
= radv_pipeline_init(pipeline
, device
, cache
,
1346 pCreateInfo
, extra
, pAllocator
);
1347 if (result
!= VK_SUCCESS
) {
1348 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
1352 *pPipeline
= radv_pipeline_to_handle(pipeline
);
1357 VkResult
radv_CreateGraphicsPipelines(
1359 VkPipelineCache pipelineCache
,
1361 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1362 const VkAllocationCallbacks
* pAllocator
,
1363 VkPipeline
* pPipelines
)
1365 VkResult result
= VK_SUCCESS
;
1368 for (; i
< count
; i
++) {
1369 result
= radv_graphics_pipeline_create(_device
,
1372 NULL
, pAllocator
, &pPipelines
[i
]);
1373 if (result
!= VK_SUCCESS
) {
1374 for (unsigned j
= 0; j
< i
; j
++) {
1375 radv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);
1385 static VkResult
radv_compute_pipeline_create(
1387 VkPipelineCache _cache
,
1388 const VkComputePipelineCreateInfo
* pCreateInfo
,
1389 const VkAllocationCallbacks
* pAllocator
,
1390 VkPipeline
* pPipeline
)
1392 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1393 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
1394 RADV_FROM_HANDLE(radv_shader_module
, module
, pCreateInfo
->stage
.module
);
1395 struct radv_pipeline
*pipeline
;
1396 bool dump
= getenv("RADV_DUMP_SHADERS");
1398 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1399 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1400 if (pipeline
== NULL
)
1401 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1403 memset(pipeline
, 0, sizeof(*pipeline
));
1404 pipeline
->device
= device
;
1405 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1407 pipeline
->shaders
[MESA_SHADER_COMPUTE
] =
1408 radv_pipeline_compile(pipeline
, cache
, module
,
1409 pCreateInfo
->stage
.pName
,
1410 MESA_SHADER_COMPUTE
,
1411 pCreateInfo
->stage
.pSpecializationInfo
,
1412 pipeline
->layout
, NULL
, dump
);
1414 *pPipeline
= radv_pipeline_to_handle(pipeline
);
1417 VkResult
radv_CreateComputePipelines(
1419 VkPipelineCache pipelineCache
,
1421 const VkComputePipelineCreateInfo
* pCreateInfos
,
1422 const VkAllocationCallbacks
* pAllocator
,
1423 VkPipeline
* pPipelines
)
1425 VkResult result
= VK_SUCCESS
;
1428 for (; i
< count
; i
++) {
1429 result
= radv_compute_pipeline_create(_device
, pipelineCache
,
1431 pAllocator
, &pPipelines
[i
]);
1432 if (result
!= VK_SUCCESS
) {
1433 for (unsigned j
= 0; j
< i
; j
++) {
1434 radv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);