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radv: add tessellation support to shader naming
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44
45 void radv_shader_variant_destroy(struct radv_device *device,
46 struct radv_shader_variant *variant);
47
48 static const struct nir_shader_compiler_options nir_options = {
49 .vertex_id_zero_based = true,
50 .lower_scmp = true,
51 .lower_flrp32 = true,
52 .lower_fsat = true,
53 .lower_pack_snorm_2x16 = true,
54 .lower_pack_snorm_4x8 = true,
55 .lower_pack_unorm_2x16 = true,
56 .lower_pack_unorm_4x8 = true,
57 .lower_unpack_snorm_2x16 = true,
58 .lower_unpack_snorm_4x8 = true,
59 .lower_unpack_unorm_2x16 = true,
60 .lower_unpack_unorm_4x8 = true,
61 .lower_extract_byte = true,
62 .lower_extract_word = true,
63 };
64
65 VkResult radv_CreateShaderModule(
66 VkDevice _device,
67 const VkShaderModuleCreateInfo* pCreateInfo,
68 const VkAllocationCallbacks* pAllocator,
69 VkShaderModule* pShaderModule)
70 {
71 RADV_FROM_HANDLE(radv_device, device, _device);
72 struct radv_shader_module *module;
73
74 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
75 assert(pCreateInfo->flags == 0);
76
77 module = vk_alloc2(&device->alloc, pAllocator,
78 sizeof(*module) + pCreateInfo->codeSize, 8,
79 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
80 if (module == NULL)
81 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
82
83 module->nir = NULL;
84 module->size = pCreateInfo->codeSize;
85 memcpy(module->data, pCreateInfo->pCode, module->size);
86
87 _mesa_sha1_compute(module->data, module->size, module->sha1);
88
89 *pShaderModule = radv_shader_module_to_handle(module);
90
91 return VK_SUCCESS;
92 }
93
94 void radv_DestroyShaderModule(
95 VkDevice _device,
96 VkShaderModule _module,
97 const VkAllocationCallbacks* pAllocator)
98 {
99 RADV_FROM_HANDLE(radv_device, device, _device);
100 RADV_FROM_HANDLE(radv_shader_module, module, _module);
101
102 if (!module)
103 return;
104
105 vk_free2(&device->alloc, pAllocator, module);
106 }
107
108
109 static void
110 radv_pipeline_destroy(struct radv_device *device,
111 struct radv_pipeline *pipeline,
112 const VkAllocationCallbacks* allocator)
113 {
114 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
115 if (pipeline->shaders[i])
116 radv_shader_variant_destroy(device, pipeline->shaders[i]);
117
118 if (pipeline->gs_copy_shader)
119 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
120
121 vk_free2(&device->alloc, allocator, pipeline);
122 }
123
124 void radv_DestroyPipeline(
125 VkDevice _device,
126 VkPipeline _pipeline,
127 const VkAllocationCallbacks* pAllocator)
128 {
129 RADV_FROM_HANDLE(radv_device, device, _device);
130 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
131
132 if (!_pipeline)
133 return;
134
135 radv_pipeline_destroy(device, pipeline, pAllocator);
136 }
137
138
139 static void
140 radv_optimize_nir(struct nir_shader *shader)
141 {
142 bool progress;
143
144 do {
145 progress = false;
146
147 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
148 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
149 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
150
151 NIR_PASS(progress, shader, nir_copy_prop);
152 NIR_PASS(progress, shader, nir_opt_remove_phis);
153 NIR_PASS(progress, shader, nir_opt_dce);
154 NIR_PASS(progress, shader, nir_opt_dead_cf);
155 NIR_PASS(progress, shader, nir_opt_cse);
156 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
157 NIR_PASS(progress, shader, nir_opt_algebraic);
158 NIR_PASS(progress, shader, nir_opt_constant_folding);
159 NIR_PASS(progress, shader, nir_opt_undef);
160 NIR_PASS(progress, shader, nir_opt_conditional_discard);
161 } while (progress);
162 }
163
164 static nir_shader *
165 radv_shader_compile_to_nir(struct radv_device *device,
166 struct radv_shader_module *module,
167 const char *entrypoint_name,
168 gl_shader_stage stage,
169 const VkSpecializationInfo *spec_info,
170 bool dump)
171 {
172 if (strcmp(entrypoint_name, "main") != 0) {
173 radv_finishme("Multiple shaders per module not really supported");
174 }
175
176 nir_shader *nir;
177 nir_function *entry_point;
178 if (module->nir) {
179 /* Some things such as our meta clear/blit code will give us a NIR
180 * shader directly. In that case, we just ignore the SPIR-V entirely
181 * and just use the NIR shader */
182 nir = module->nir;
183 nir->options = &nir_options;
184 nir_validate_shader(nir);
185
186 assert(exec_list_length(&nir->functions) == 1);
187 struct exec_node *node = exec_list_get_head(&nir->functions);
188 entry_point = exec_node_data(nir_function, node, node);
189 } else {
190 uint32_t *spirv = (uint32_t *) module->data;
191 assert(module->size % 4 == 0);
192
193 uint32_t num_spec_entries = 0;
194 struct nir_spirv_specialization *spec_entries = NULL;
195 if (spec_info && spec_info->mapEntryCount > 0) {
196 num_spec_entries = spec_info->mapEntryCount;
197 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
198 for (uint32_t i = 0; i < num_spec_entries; i++) {
199 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
200 const void *data = spec_info->pData + entry.offset;
201 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
202
203 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
204 if (spec_info->dataSize == 8)
205 spec_entries[i].data64 = *(const uint64_t *)data;
206 else
207 spec_entries[i].data32 = *(const uint32_t *)data;
208 }
209 }
210 const struct nir_spirv_supported_extensions supported_ext = {
211 .draw_parameters = true,
212 .float64 = true,
213 .image_read_without_format = true,
214 .image_write_without_format = true,
215 };
216 entry_point = spirv_to_nir(spirv, module->size / 4,
217 spec_entries, num_spec_entries,
218 stage, entrypoint_name, &supported_ext, &nir_options);
219 nir = entry_point->shader;
220 assert(nir->stage == stage);
221 nir_validate_shader(nir);
222
223 free(spec_entries);
224
225 /* We have to lower away local constant initializers right before we
226 * inline functions. That way they get properly initialized at the top
227 * of the function and not at the top of its caller.
228 */
229 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
230 NIR_PASS_V(nir, nir_lower_returns);
231 NIR_PASS_V(nir, nir_inline_functions);
232
233 /* Pick off the single entrypoint that we want */
234 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
235 if (func != entry_point)
236 exec_node_remove(&func->node);
237 }
238 assert(exec_list_length(&nir->functions) == 1);
239 entry_point->name = ralloc_strdup(entry_point, "main");
240
241 NIR_PASS_V(nir, nir_remove_dead_variables,
242 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
243
244 /* Now that we've deleted all but the main function, we can go ahead and
245 * lower the rest of the constant initializers.
246 */
247 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
248 NIR_PASS_V(nir, nir_lower_system_values);
249 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
250 }
251
252 /* Vulkan uses the separate-shader linking model */
253 nir->info->separate_shader = true;
254
255 nir_shader_gather_info(nir, entry_point->impl);
256
257 nir_variable_mode indirect_mask = 0;
258 indirect_mask |= nir_var_shader_in;
259 indirect_mask |= nir_var_local;
260
261 nir_lower_indirect_derefs(nir, indirect_mask);
262
263 static const nir_lower_tex_options tex_options = {
264 .lower_txp = ~0,
265 };
266
267 nir_lower_tex(nir, &tex_options);
268
269 nir_lower_vars_to_ssa(nir);
270 nir_lower_var_copies(nir);
271 nir_lower_global_vars_to_local(nir);
272 nir_remove_dead_variables(nir, nir_var_local);
273 radv_optimize_nir(nir);
274
275 if (dump)
276 nir_print_shader(nir, stderr);
277
278 return nir;
279 }
280
281 static const char *radv_get_shader_name(struct radv_shader_variant *var,
282 gl_shader_stage stage)
283 {
284 switch (stage) {
285 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
286 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
287 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
288 case MESA_SHADER_COMPUTE: return "Compute Shader";
289 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
290 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
291 default:
292 return "Unknown shader";
293 };
294
295 }
296 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
297 {
298 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
299 struct radv_shader_variant *var;
300 struct ac_shader_config *conf;
301 int i;
302 FILE *file = stderr;
303 unsigned max_simd_waves = 10;
304 unsigned lds_per_wave = 0;
305
306 for (i = 0; i < MESA_SHADER_STAGES; i++) {
307 if (!pipeline->shaders[i])
308 continue;
309 var = pipeline->shaders[i];
310
311 conf = &var->config;
312
313 if (i == MESA_SHADER_FRAGMENT) {
314 lds_per_wave = conf->lds_size * lds_increment +
315 align(var->info.fs.num_interp * 48, lds_increment);
316 }
317
318 if (conf->num_sgprs) {
319 if (device->physical_device->rad_info.chip_class >= VI)
320 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
321 else
322 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
323 }
324
325 if (conf->num_vgprs)
326 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
327
328 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
329 * that PS can use.
330 */
331 if (lds_per_wave)
332 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
333
334 fprintf(file, "\n%s:\n",
335 radv_get_shader_name(var, i));
336 if (i == MESA_SHADER_FRAGMENT) {
337 fprintf(file, "*** SHADER CONFIG ***\n"
338 "SPI_PS_INPUT_ADDR = 0x%04x\n"
339 "SPI_PS_INPUT_ENA = 0x%04x\n",
340 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
341 }
342 fprintf(file, "*** SHADER STATS ***\n"
343 "SGPRS: %d\n"
344 "VGPRS: %d\n"
345 "Spilled SGPRs: %d\n"
346 "Spilled VGPRs: %d\n"
347 "Code Size: %d bytes\n"
348 "LDS: %d blocks\n"
349 "Scratch: %d bytes per wave\n"
350 "Max Waves: %d\n"
351 "********************\n\n\n",
352 conf->num_sgprs, conf->num_vgprs,
353 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
354 conf->lds_size, conf->scratch_bytes_per_wave,
355 max_simd_waves);
356 }
357 }
358
359 void radv_shader_variant_destroy(struct radv_device *device,
360 struct radv_shader_variant *variant)
361 {
362 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
363 return;
364
365 device->ws->buffer_destroy(variant->bo);
366 free(variant);
367 }
368
369 static void radv_fill_shader_variant(struct radv_device *device,
370 struct radv_shader_variant *variant,
371 struct ac_shader_binary *binary,
372 gl_shader_stage stage)
373 {
374 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
375 unsigned vgpr_comp_cnt = 0;
376
377 if (scratch_enabled && !device->llvm_supports_spill)
378 radv_finishme("shader scratch support only available with LLVM 4.0");
379
380 variant->code_size = binary->code_size;
381
382 switch (stage) {
383 case MESA_SHADER_VERTEX:
384 case MESA_SHADER_GEOMETRY:
385 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
386 S_00B12C_SCRATCH_EN(scratch_enabled);
387 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
388 break;
389 case MESA_SHADER_FRAGMENT:
390 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
391 S_00B12C_SCRATCH_EN(scratch_enabled);
392 break;
393 case MESA_SHADER_COMPUTE:
394 variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) |
395 S_00B84C_SCRATCH_EN(scratch_enabled) |
396 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
397 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
398 S_00B84C_TG_SIZE_EN(1) |
399 S_00B84C_LDS_SIZE(variant->config.lds_size);
400 break;
401 default:
402 unreachable("unsupported shader type");
403 break;
404 }
405
406 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
407 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
408 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
409 S_00B848_DX10_CLAMP(1) |
410 S_00B848_FLOAT_MODE(variant->config.float_mode);
411
412 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
413 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
414
415 void *ptr = device->ws->buffer_map(variant->bo);
416 memcpy(ptr, binary->code, binary->code_size);
417 device->ws->buffer_unmap(variant->bo);
418
419
420 }
421
422 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
423 struct nir_shader *shader,
424 struct radv_pipeline_layout *layout,
425 const union ac_shader_variant_key *key,
426 void** code_out,
427 unsigned *code_size_out,
428 bool dump)
429 {
430 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
431 enum radeon_family chip_family = device->physical_device->rad_info.family;
432 LLVMTargetMachineRef tm;
433 if (!variant)
434 return NULL;
435
436 struct ac_nir_compiler_options options = {0};
437 options.layout = layout;
438 if (key)
439 options.key = *key;
440
441 struct ac_shader_binary binary;
442
443 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
444 options.family = chip_family;
445 options.chip_class = device->physical_device->rad_info.chip_class;
446 options.supports_spill = device->llvm_supports_spill;
447 tm = ac_create_target_machine(chip_family, options.supports_spill);
448 ac_compile_nir_shader(tm, &binary, &variant->config,
449 &variant->info, shader, &options, dump);
450 LLVMDisposeTargetMachine(tm);
451
452 radv_fill_shader_variant(device, variant, &binary, shader->stage);
453
454 if (code_out) {
455 *code_out = binary.code;
456 *code_size_out = binary.code_size;
457 } else
458 free(binary.code);
459 free(binary.config);
460 free(binary.rodata);
461 free(binary.global_symbol_offsets);
462 free(binary.relocs);
463 free(binary.disasm_string);
464 variant->ref_count = 1;
465 return variant;
466 }
467
468 static struct radv_shader_variant *
469 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
470 struct nir_shader *nir,
471 void** code_out,
472 unsigned *code_size_out,
473 bool dump_shader)
474 {
475 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
476 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
477 LLVMTargetMachineRef tm;
478 if (!variant)
479 return NULL;
480
481 struct ac_nir_compiler_options options = {0};
482 struct ac_shader_binary binary;
483 options.family = chip_family;
484 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
485 options.supports_spill = pipeline->device->llvm_supports_spill;
486 tm = ac_create_target_machine(chip_family, options.supports_spill);
487 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
488 LLVMDisposeTargetMachine(tm);
489
490 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
491
492 if (code_out) {
493 *code_out = binary.code;
494 *code_size_out = binary.code_size;
495 } else
496 free(binary.code);
497 free(binary.config);
498 free(binary.rodata);
499 free(binary.global_symbol_offsets);
500 free(binary.relocs);
501 free(binary.disasm_string);
502 variant->ref_count = 1;
503 return variant;
504 }
505
506 static struct radv_shader_variant *
507 radv_pipeline_compile(struct radv_pipeline *pipeline,
508 struct radv_pipeline_cache *cache,
509 struct radv_shader_module *module,
510 const char *entrypoint,
511 gl_shader_stage stage,
512 const VkSpecializationInfo *spec_info,
513 struct radv_pipeline_layout *layout,
514 const union ac_shader_variant_key *key)
515 {
516 unsigned char sha1[20];
517 unsigned char gs_copy_sha1[20];
518 struct radv_shader_variant *variant;
519 nir_shader *nir;
520 void *code = NULL;
521 unsigned code_size = 0;
522 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
523
524 if (module->nir)
525 _mesa_sha1_compute(module->nir->info->name,
526 strlen(module->nir->info->name),
527 module->sha1);
528
529 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
530 if (stage == MESA_SHADER_GEOMETRY)
531 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
532 layout, key, 1);
533
534 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
535 cache,
536 sha1);
537
538 if (stage == MESA_SHADER_GEOMETRY) {
539 pipeline->gs_copy_shader =
540 radv_create_shader_variant_from_pipeline_cache(
541 pipeline->device,
542 cache,
543 gs_copy_sha1);
544 }
545
546 if (variant &&
547 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
548 return variant;
549
550 nir = radv_shader_compile_to_nir(pipeline->device,
551 module, entrypoint, stage,
552 spec_info, dump);
553 if (nir == NULL)
554 return NULL;
555
556 if (!variant) {
557 variant = radv_shader_variant_create(pipeline->device, nir,
558 layout, key, &code,
559 &code_size, dump);
560 }
561
562 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
563 void *gs_copy_code = NULL;
564 unsigned gs_copy_code_size = 0;
565 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
566 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
567
568 if (pipeline->gs_copy_shader) {
569 pipeline->gs_copy_shader =
570 radv_pipeline_cache_insert_shader(cache,
571 gs_copy_sha1,
572 pipeline->gs_copy_shader,
573 gs_copy_code,
574 gs_copy_code_size);
575 }
576 }
577 if (!module->nir)
578 ralloc_free(nir);
579
580 if (variant)
581 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
582 code, code_size);
583
584 if (code)
585 free(code);
586 return variant;
587 }
588
589 static VkResult
590 radv_pipeline_scratch_init(struct radv_device *device,
591 struct radv_pipeline *pipeline)
592 {
593 unsigned scratch_bytes_per_wave = 0;
594 unsigned max_waves = 0;
595 unsigned min_waves = 1;
596
597 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
598 if (pipeline->shaders[i]) {
599 unsigned max_stage_waves = device->scratch_waves;
600
601 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
602 pipeline->shaders[i]->config.scratch_bytes_per_wave);
603
604 max_stage_waves = MIN2(max_stage_waves,
605 4 * device->physical_device->rad_info.num_good_compute_units *
606 (256 / pipeline->shaders[i]->config.num_vgprs));
607 max_waves = MAX2(max_waves, max_stage_waves);
608 }
609 }
610
611 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
612 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
613 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
614 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
615 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
616 }
617
618 if (scratch_bytes_per_wave)
619 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
620
621 if (scratch_bytes_per_wave && max_waves < min_waves) {
622 /* Not really true at this moment, but will be true on first
623 * execution. Avoid having hanging shaders. */
624 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
625 }
626 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
627 pipeline->max_waves = max_waves;
628 return VK_SUCCESS;
629 }
630
631 static uint32_t si_translate_blend_function(VkBlendOp op)
632 {
633 switch (op) {
634 case VK_BLEND_OP_ADD:
635 return V_028780_COMB_DST_PLUS_SRC;
636 case VK_BLEND_OP_SUBTRACT:
637 return V_028780_COMB_SRC_MINUS_DST;
638 case VK_BLEND_OP_REVERSE_SUBTRACT:
639 return V_028780_COMB_DST_MINUS_SRC;
640 case VK_BLEND_OP_MIN:
641 return V_028780_COMB_MIN_DST_SRC;
642 case VK_BLEND_OP_MAX:
643 return V_028780_COMB_MAX_DST_SRC;
644 default:
645 return 0;
646 }
647 }
648
649 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
650 {
651 switch (factor) {
652 case VK_BLEND_FACTOR_ZERO:
653 return V_028780_BLEND_ZERO;
654 case VK_BLEND_FACTOR_ONE:
655 return V_028780_BLEND_ONE;
656 case VK_BLEND_FACTOR_SRC_COLOR:
657 return V_028780_BLEND_SRC_COLOR;
658 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
659 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
660 case VK_BLEND_FACTOR_DST_COLOR:
661 return V_028780_BLEND_DST_COLOR;
662 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
663 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
664 case VK_BLEND_FACTOR_SRC_ALPHA:
665 return V_028780_BLEND_SRC_ALPHA;
666 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
667 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
668 case VK_BLEND_FACTOR_DST_ALPHA:
669 return V_028780_BLEND_DST_ALPHA;
670 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
671 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
672 case VK_BLEND_FACTOR_CONSTANT_COLOR:
673 return V_028780_BLEND_CONSTANT_COLOR;
674 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
675 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
676 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
677 return V_028780_BLEND_CONSTANT_ALPHA;
678 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
679 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
680 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
681 return V_028780_BLEND_SRC_ALPHA_SATURATE;
682 case VK_BLEND_FACTOR_SRC1_COLOR:
683 return V_028780_BLEND_SRC1_COLOR;
684 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
685 return V_028780_BLEND_INV_SRC1_COLOR;
686 case VK_BLEND_FACTOR_SRC1_ALPHA:
687 return V_028780_BLEND_SRC1_ALPHA;
688 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
689 return V_028780_BLEND_INV_SRC1_ALPHA;
690 default:
691 return 0;
692 }
693 }
694
695 static bool is_dual_src(VkBlendFactor factor)
696 {
697 switch (factor) {
698 case VK_BLEND_FACTOR_SRC1_COLOR:
699 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
700 case VK_BLEND_FACTOR_SRC1_ALPHA:
701 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
702 return true;
703 default:
704 return false;
705 }
706 }
707
708 static unsigned si_choose_spi_color_format(VkFormat vk_format,
709 bool blend_enable,
710 bool blend_need_alpha)
711 {
712 const struct vk_format_description *desc = vk_format_description(vk_format);
713 unsigned format, ntype, swap;
714
715 /* Alpha is needed for alpha-to-coverage.
716 * Blending may be with or without alpha.
717 */
718 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
719 unsigned alpha = 0; /* exports alpha, but may not support blending */
720 unsigned blend = 0; /* supports blending, but may not export alpha */
721 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
722
723 format = radv_translate_colorformat(vk_format);
724 ntype = radv_translate_color_numformat(vk_format, desc,
725 vk_format_get_first_non_void_channel(vk_format));
726 swap = radv_translate_colorswap(vk_format, false);
727
728 /* Choose the SPI color formats. These are required values for Stoney/RB+.
729 * Other chips have multiple choices, though they are not necessarily better.
730 */
731 switch (format) {
732 case V_028C70_COLOR_5_6_5:
733 case V_028C70_COLOR_1_5_5_5:
734 case V_028C70_COLOR_5_5_5_1:
735 case V_028C70_COLOR_4_4_4_4:
736 case V_028C70_COLOR_10_11_11:
737 case V_028C70_COLOR_11_11_10:
738 case V_028C70_COLOR_8:
739 case V_028C70_COLOR_8_8:
740 case V_028C70_COLOR_8_8_8_8:
741 case V_028C70_COLOR_10_10_10_2:
742 case V_028C70_COLOR_2_10_10_10:
743 if (ntype == V_028C70_NUMBER_UINT)
744 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
745 else if (ntype == V_028C70_NUMBER_SINT)
746 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
747 else
748 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
749 break;
750
751 case V_028C70_COLOR_16:
752 case V_028C70_COLOR_16_16:
753 case V_028C70_COLOR_16_16_16_16:
754 if (ntype == V_028C70_NUMBER_UNORM ||
755 ntype == V_028C70_NUMBER_SNORM) {
756 /* UNORM16 and SNORM16 don't support blending */
757 if (ntype == V_028C70_NUMBER_UNORM)
758 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
759 else
760 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
761
762 /* Use 32 bits per channel for blending. */
763 if (format == V_028C70_COLOR_16) {
764 if (swap == V_028C70_SWAP_STD) { /* R */
765 blend = V_028714_SPI_SHADER_32_R;
766 blend_alpha = V_028714_SPI_SHADER_32_AR;
767 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
768 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
769 else
770 assert(0);
771 } else if (format == V_028C70_COLOR_16_16) {
772 if (swap == V_028C70_SWAP_STD) { /* RG */
773 blend = V_028714_SPI_SHADER_32_GR;
774 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
775 } else if (swap == V_028C70_SWAP_ALT) /* RA */
776 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
777 else
778 assert(0);
779 } else /* 16_16_16_16 */
780 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
781 } else if (ntype == V_028C70_NUMBER_UINT)
782 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
783 else if (ntype == V_028C70_NUMBER_SINT)
784 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
785 else if (ntype == V_028C70_NUMBER_FLOAT)
786 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
787 else
788 assert(0);
789 break;
790
791 case V_028C70_COLOR_32:
792 if (swap == V_028C70_SWAP_STD) { /* R */
793 blend = normal = V_028714_SPI_SHADER_32_R;
794 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
795 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
796 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
797 else
798 assert(0);
799 break;
800
801 case V_028C70_COLOR_32_32:
802 if (swap == V_028C70_SWAP_STD) { /* RG */
803 blend = normal = V_028714_SPI_SHADER_32_GR;
804 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
805 } else if (swap == V_028C70_SWAP_ALT) /* RA */
806 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
807 else
808 assert(0);
809 break;
810
811 case V_028C70_COLOR_32_32_32_32:
812 case V_028C70_COLOR_8_24:
813 case V_028C70_COLOR_24_8:
814 case V_028C70_COLOR_X24_8_32_FLOAT:
815 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
816 break;
817
818 default:
819 unreachable("unhandled blend format");
820 }
821
822 if (blend_enable && blend_need_alpha)
823 return blend_alpha;
824 else if(blend_need_alpha)
825 return alpha;
826 else if(blend_enable)
827 return blend;
828 else
829 return normal;
830 }
831
832 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
833 {
834 unsigned i, cb_shader_mask = 0;
835
836 for (i = 0; i < 8; i++) {
837 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
838 case V_028714_SPI_SHADER_ZERO:
839 break;
840 case V_028714_SPI_SHADER_32_R:
841 cb_shader_mask |= 0x1 << (i * 4);
842 break;
843 case V_028714_SPI_SHADER_32_GR:
844 cb_shader_mask |= 0x3 << (i * 4);
845 break;
846 case V_028714_SPI_SHADER_32_AR:
847 cb_shader_mask |= 0x9 << (i * 4);
848 break;
849 case V_028714_SPI_SHADER_FP16_ABGR:
850 case V_028714_SPI_SHADER_UNORM16_ABGR:
851 case V_028714_SPI_SHADER_SNORM16_ABGR:
852 case V_028714_SPI_SHADER_UINT16_ABGR:
853 case V_028714_SPI_SHADER_SINT16_ABGR:
854 case V_028714_SPI_SHADER_32_ABGR:
855 cb_shader_mask |= 0xf << (i * 4);
856 break;
857 default:
858 assert(0);
859 }
860 }
861 return cb_shader_mask;
862 }
863
864 static void
865 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
866 const VkGraphicsPipelineCreateInfo *pCreateInfo,
867 uint32_t blend_enable,
868 uint32_t blend_need_alpha,
869 bool single_cb_enable,
870 bool blend_mrt0_is_dual_src)
871 {
872 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
873 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
874 struct radv_blend_state *blend = &pipeline->graphics.blend;
875 unsigned col_format = 0;
876
877 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
878 struct radv_render_pass_attachment *attachment;
879 unsigned cf;
880
881 attachment = pass->attachments + subpass->color_attachments[i].attachment;
882
883 cf = si_choose_spi_color_format(attachment->format,
884 blend_enable & (1 << i),
885 blend_need_alpha & (1 << i));
886
887 col_format |= cf << (4 * i);
888 }
889
890 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
891
892 if (blend_mrt0_is_dual_src)
893 col_format |= (col_format & 0xf) << 4;
894 blend->spi_shader_col_format = col_format;
895 }
896
897 static bool
898 format_is_int8(VkFormat format)
899 {
900 const struct vk_format_description *desc = vk_format_description(format);
901 int channel = vk_format_get_first_non_void_channel(format);
902
903 return channel >= 0 && desc->channel[channel].pure_integer &&
904 desc->channel[channel].size == 8;
905 }
906
907 unsigned radv_format_meta_fs_key(VkFormat format)
908 {
909 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
910 bool is_int8 = format_is_int8(format);
911
912 return col_format + (is_int8 ? 3 : 0);
913 }
914
915 static unsigned
916 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
917 {
918 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
919 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
920 unsigned is_int8 = 0;
921
922 for (unsigned i = 0; i < subpass->color_count; ++i) {
923 struct radv_render_pass_attachment *attachment;
924
925 attachment = pass->attachments + subpass->color_attachments[i].attachment;
926
927 if (format_is_int8(attachment->format))
928 is_int8 |= 1 << i;
929 }
930
931 return is_int8;
932 }
933
934 static void
935 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
936 const VkGraphicsPipelineCreateInfo *pCreateInfo,
937 const struct radv_graphics_pipeline_create_info *extra)
938 {
939 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
940 struct radv_blend_state *blend = &pipeline->graphics.blend;
941 unsigned mode = V_028808_CB_NORMAL;
942 uint32_t blend_enable = 0, blend_need_alpha = 0;
943 bool blend_mrt0_is_dual_src = false;
944 int i;
945 bool single_cb_enable = false;
946
947 if (!vkblend)
948 return;
949
950 if (extra && extra->custom_blend_mode) {
951 single_cb_enable = true;
952 mode = extra->custom_blend_mode;
953 }
954 blend->cb_color_control = 0;
955 if (vkblend->logicOpEnable)
956 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
957 else
958 blend->cb_color_control |= S_028808_ROP3(0xcc);
959
960 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
961 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
962 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
963 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
964
965 blend->cb_target_mask = 0;
966 for (i = 0; i < vkblend->attachmentCount; i++) {
967 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
968 unsigned blend_cntl = 0;
969 VkBlendOp eqRGB = att->colorBlendOp;
970 VkBlendFactor srcRGB = att->srcColorBlendFactor;
971 VkBlendFactor dstRGB = att->dstColorBlendFactor;
972 VkBlendOp eqA = att->alphaBlendOp;
973 VkBlendFactor srcA = att->srcAlphaBlendFactor;
974 VkBlendFactor dstA = att->dstAlphaBlendFactor;
975
976 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
977
978 if (!att->colorWriteMask)
979 continue;
980
981 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
982 if (!att->blendEnable) {
983 blend->cb_blend_control[i] = blend_cntl;
984 continue;
985 }
986
987 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
988 if (i == 0)
989 blend_mrt0_is_dual_src = true;
990
991 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
992 srcRGB = VK_BLEND_FACTOR_ONE;
993 dstRGB = VK_BLEND_FACTOR_ONE;
994 }
995 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
996 srcA = VK_BLEND_FACTOR_ONE;
997 dstA = VK_BLEND_FACTOR_ONE;
998 }
999
1000 blend_cntl |= S_028780_ENABLE(1);
1001
1002 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1003 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1004 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1005 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1006 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1007 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1008 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1009 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1010 }
1011 blend->cb_blend_control[i] = blend_cntl;
1012
1013 blend_enable |= 1 << i;
1014
1015 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1016 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1017 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1018 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1019 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1020 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1021 blend_need_alpha |= 1 << i;
1022 }
1023 for (i = vkblend->attachmentCount; i < 8; i++)
1024 blend->cb_blend_control[i] = 0;
1025
1026 if (blend->cb_target_mask)
1027 blend->cb_color_control |= S_028808_MODE(mode);
1028 else
1029 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1030
1031 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1032 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1033 }
1034
1035 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1036 {
1037 switch (op) {
1038 case VK_STENCIL_OP_KEEP:
1039 return V_02842C_STENCIL_KEEP;
1040 case VK_STENCIL_OP_ZERO:
1041 return V_02842C_STENCIL_ZERO;
1042 case VK_STENCIL_OP_REPLACE:
1043 return V_02842C_STENCIL_REPLACE_TEST;
1044 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1045 return V_02842C_STENCIL_ADD_CLAMP;
1046 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1047 return V_02842C_STENCIL_SUB_CLAMP;
1048 case VK_STENCIL_OP_INVERT:
1049 return V_02842C_STENCIL_INVERT;
1050 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1051 return V_02842C_STENCIL_ADD_WRAP;
1052 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1053 return V_02842C_STENCIL_SUB_WRAP;
1054 default:
1055 return 0;
1056 }
1057 }
1058 static void
1059 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1060 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1061 const struct radv_graphics_pipeline_create_info *extra)
1062 {
1063 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1064 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1065
1066 memset(ds, 0, sizeof(*ds));
1067 if (!vkds)
1068 return;
1069 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1070 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1071 S_028800_ZFUNC(vkds->depthCompareOp) |
1072 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1073
1074 if (vkds->stencilTestEnable) {
1075 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1076 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1077 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1078 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1079 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1080
1081 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1082 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1083 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1084 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1085 }
1086
1087 if (extra) {
1088
1089 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1090 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1091
1092 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1093 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1094 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1095 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1096 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1097 }
1098 }
1099
1100 static uint32_t si_translate_fill(VkPolygonMode func)
1101 {
1102 switch(func) {
1103 case VK_POLYGON_MODE_FILL:
1104 return V_028814_X_DRAW_TRIANGLES;
1105 case VK_POLYGON_MODE_LINE:
1106 return V_028814_X_DRAW_LINES;
1107 case VK_POLYGON_MODE_POINT:
1108 return V_028814_X_DRAW_POINTS;
1109 default:
1110 assert(0);
1111 return V_028814_X_DRAW_POINTS;
1112 }
1113 }
1114 static void
1115 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1116 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1117 {
1118 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1119 struct radv_raster_state *raster = &pipeline->graphics.raster;
1120
1121 memset(raster, 0, sizeof(*raster));
1122
1123 raster->spi_interp_control =
1124 S_0286D4_FLAT_SHADE_ENA(1) |
1125 S_0286D4_PNT_SPRITE_ENA(1) |
1126 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1127 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1128 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1129 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1130 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1131
1132
1133 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1134 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1135 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1136 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1137 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1138 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1139
1140 raster->pa_su_vtx_cntl =
1141 S_028BE4_PIX_CENTER(1) | // TODO verify
1142 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1143 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1144
1145 raster->pa_su_sc_mode_cntl =
1146 S_028814_FACE(vkraster->frontFace) |
1147 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1148 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1149 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1150 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1151 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1152 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1153 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1154 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1155
1156 }
1157
1158 static void
1159 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1160 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1161 {
1162 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1163 struct radv_blend_state *blend = &pipeline->graphics.blend;
1164 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1165 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1166 int ps_iter_samples = 1;
1167 uint32_t mask = 0xffff;
1168
1169 if (vkms)
1170 ms->num_samples = vkms->rasterizationSamples;
1171 else
1172 ms->num_samples = 1;
1173
1174 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1175 ps_iter_samples = ms->num_samples;
1176 }
1177
1178 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1179 ms->pa_sc_aa_config = 0;
1180 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1181 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1182 ms->pa_sc_mode_cntl_1 =
1183 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1184 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1185 /* always 1: */
1186 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1187 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1188 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1189 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1190 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1191 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1192
1193 if (ms->num_samples > 1) {
1194 unsigned log_samples = util_logbase2(ms->num_samples);
1195 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1196 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1197 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1198 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1199 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1200 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1201 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1202 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1203 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1204 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1205 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1206 }
1207
1208 if (vkms) {
1209 if (vkms->alphaToCoverageEnable)
1210 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1211
1212 if (vkms->pSampleMask)
1213 mask = vkms->pSampleMask[0] & 0xffff;
1214 }
1215
1216 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1217 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1218 }
1219
1220 static bool
1221 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1222 {
1223 switch (topology) {
1224 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1225 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1226 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1227 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1228 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1229 return false;
1230 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1231 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1232 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1234 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1235 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1236 return true;
1237 default:
1238 unreachable("unhandled primitive type");
1239 }
1240 }
1241
1242 static uint32_t
1243 si_translate_prim(enum VkPrimitiveTopology topology)
1244 {
1245 switch (topology) {
1246 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1247 return V_008958_DI_PT_POINTLIST;
1248 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1249 return V_008958_DI_PT_LINELIST;
1250 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1251 return V_008958_DI_PT_LINESTRIP;
1252 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1253 return V_008958_DI_PT_TRILIST;
1254 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1255 return V_008958_DI_PT_TRISTRIP;
1256 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1257 return V_008958_DI_PT_TRIFAN;
1258 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1259 return V_008958_DI_PT_LINELIST_ADJ;
1260 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1261 return V_008958_DI_PT_LINESTRIP_ADJ;
1262 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1263 return V_008958_DI_PT_TRILIST_ADJ;
1264 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1265 return V_008958_DI_PT_TRISTRIP_ADJ;
1266 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1267 return V_008958_DI_PT_PATCH;
1268 default:
1269 assert(0);
1270 return 0;
1271 }
1272 }
1273
1274 static uint32_t
1275 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1276 {
1277 switch (gl_prim) {
1278 case 0: /* GL_POINTS */
1279 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1280 case 1: /* GL_LINES */
1281 case 3: /* GL_LINE_STRIP */
1282 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1283 case 0x8E7A: /* GL_ISOLINES */
1284 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1285
1286 case 4: /* GL_TRIANGLES */
1287 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1288 case 5: /* GL_TRIANGLE_STRIP */
1289 case 7: /* GL_QUADS */
1290 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1291 default:
1292 assert(0);
1293 return 0;
1294 }
1295 }
1296
1297 static uint32_t
1298 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1299 {
1300 switch (topology) {
1301 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1302 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1303 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1304 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1305 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1306 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1307 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1308 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1309 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1310 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1311 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1312 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1313 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1314 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1315 default:
1316 assert(0);
1317 return 0;
1318 }
1319 }
1320
1321 static unsigned si_map_swizzle(unsigned swizzle)
1322 {
1323 switch (swizzle) {
1324 case VK_SWIZZLE_Y:
1325 return V_008F0C_SQ_SEL_Y;
1326 case VK_SWIZZLE_Z:
1327 return V_008F0C_SQ_SEL_Z;
1328 case VK_SWIZZLE_W:
1329 return V_008F0C_SQ_SEL_W;
1330 case VK_SWIZZLE_0:
1331 return V_008F0C_SQ_SEL_0;
1332 case VK_SWIZZLE_1:
1333 return V_008F0C_SQ_SEL_1;
1334 default: /* VK_SWIZZLE_X */
1335 return V_008F0C_SQ_SEL_X;
1336 }
1337 }
1338
1339 static void
1340 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1341 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1342 {
1343 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1344 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1345 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1346
1347 pipeline->dynamic_state = default_dynamic_state;
1348
1349 if (pCreateInfo->pDynamicState) {
1350 /* Remove all of the states that are marked as dynamic */
1351 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1352 for (uint32_t s = 0; s < count; s++)
1353 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1354 }
1355
1356 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1357
1358 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1359 *
1360 * pViewportState is [...] NULL if the pipeline
1361 * has rasterization disabled.
1362 */
1363 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1364 assert(pCreateInfo->pViewportState);
1365
1366 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1367 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1368 typed_memcpy(dynamic->viewport.viewports,
1369 pCreateInfo->pViewportState->pViewports,
1370 pCreateInfo->pViewportState->viewportCount);
1371 }
1372
1373 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1374 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1375 typed_memcpy(dynamic->scissor.scissors,
1376 pCreateInfo->pViewportState->pScissors,
1377 pCreateInfo->pViewportState->scissorCount);
1378 }
1379 }
1380
1381 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1382 assert(pCreateInfo->pRasterizationState);
1383 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1384 }
1385
1386 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1387 assert(pCreateInfo->pRasterizationState);
1388 dynamic->depth_bias.bias =
1389 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1390 dynamic->depth_bias.clamp =
1391 pCreateInfo->pRasterizationState->depthBiasClamp;
1392 dynamic->depth_bias.slope =
1393 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1394 }
1395
1396 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1397 *
1398 * pColorBlendState is [...] NULL if the pipeline has rasterization
1399 * disabled or if the subpass of the render pass the pipeline is
1400 * created against does not use any color attachments.
1401 */
1402 bool uses_color_att = false;
1403 for (unsigned i = 0; i < subpass->color_count; ++i) {
1404 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1405 uses_color_att = true;
1406 break;
1407 }
1408 }
1409
1410 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1411 assert(pCreateInfo->pColorBlendState);
1412 typed_memcpy(dynamic->blend_constants,
1413 pCreateInfo->pColorBlendState->blendConstants, 4);
1414 }
1415
1416 /* If there is no depthstencil attachment, then don't read
1417 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1418 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1419 * no need to override the depthstencil defaults in
1420 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1421 *
1422 * Section 9.2 of the Vulkan 1.0.15 spec says:
1423 *
1424 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1425 * disabled or if the subpass of the render pass the pipeline is created
1426 * against does not use a depth/stencil attachment.
1427 */
1428 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1429 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1430 assert(pCreateInfo->pDepthStencilState);
1431
1432 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1433 dynamic->depth_bounds.min =
1434 pCreateInfo->pDepthStencilState->minDepthBounds;
1435 dynamic->depth_bounds.max =
1436 pCreateInfo->pDepthStencilState->maxDepthBounds;
1437 }
1438
1439 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1440 dynamic->stencil_compare_mask.front =
1441 pCreateInfo->pDepthStencilState->front.compareMask;
1442 dynamic->stencil_compare_mask.back =
1443 pCreateInfo->pDepthStencilState->back.compareMask;
1444 }
1445
1446 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1447 dynamic->stencil_write_mask.front =
1448 pCreateInfo->pDepthStencilState->front.writeMask;
1449 dynamic->stencil_write_mask.back =
1450 pCreateInfo->pDepthStencilState->back.writeMask;
1451 }
1452
1453 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1454 dynamic->stencil_reference.front =
1455 pCreateInfo->pDepthStencilState->front.reference;
1456 dynamic->stencil_reference.back =
1457 pCreateInfo->pDepthStencilState->back.reference;
1458 }
1459 }
1460
1461 pipeline->dynamic_state_mask = states;
1462 }
1463
1464 static union ac_shader_variant_key
1465 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es)
1466 {
1467 union ac_shader_variant_key key;
1468 const VkPipelineVertexInputStateCreateInfo *input_state =
1469 pCreateInfo->pVertexInputState;
1470
1471 memset(&key, 0, sizeof(key));
1472 key.vs.instance_rate_inputs = 0;
1473 key.vs.as_es = as_es;
1474
1475 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1476 unsigned binding;
1477 binding = input_state->pVertexAttributeDescriptions[i].binding;
1478 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1479 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1480 }
1481 return key;
1482 }
1483
1484 static void
1485 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1486 {
1487 struct radv_device *device = pipeline->device;
1488 unsigned num_se = device->physical_device->rad_info.max_se;
1489 unsigned wave_size = 64;
1490 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1491 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1492 unsigned alignment = 256 * num_se;
1493 /* The maximum size is 63.999 MB per SE. */
1494 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1495 struct ac_es_output_info *es_info = &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1496 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1497
1498 /* Calculate the minimum size. */
1499 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1500 wave_size, alignment);
1501 /* These are recommended sizes, not minimum sizes. */
1502 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1503 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1504 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1505 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1506
1507 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1508 esgs_ring_size = align(esgs_ring_size, alignment);
1509 gsvs_ring_size = align(gsvs_ring_size, alignment);
1510
1511 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1512 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1513 }
1514
1515 static const struct radv_prim_vertex_count prim_size_table[] = {
1516 [V_008958_DI_PT_NONE] = {0, 0},
1517 [V_008958_DI_PT_POINTLIST] = {1, 1},
1518 [V_008958_DI_PT_LINELIST] = {2, 2},
1519 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1520 [V_008958_DI_PT_TRILIST] = {3, 3},
1521 [V_008958_DI_PT_TRIFAN] = {3, 1},
1522 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1523 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1524 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1525 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1526 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1527 [V_008958_DI_PT_RECTLIST] = {3, 3},
1528 [V_008958_DI_PT_LINELOOP] = {2, 1},
1529 [V_008958_DI_PT_POLYGON] = {3, 1},
1530 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1531 };
1532
1533 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1534 {
1535 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1536 unsigned cut_mode;
1537
1538 if (gs_max_vert_out <= 128) {
1539 cut_mode = V_028A40_GS_CUT_128;
1540 } else if (gs_max_vert_out <= 256) {
1541 cut_mode = V_028A40_GS_CUT_256;
1542 } else if (gs_max_vert_out <= 512) {
1543 cut_mode = V_028A40_GS_CUT_512;
1544 } else {
1545 assert(gs_max_vert_out <= 1024);
1546 cut_mode = V_028A40_GS_CUT_1024;
1547 }
1548
1549 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1550 S_028A40_CUT_MODE(cut_mode)|
1551 S_028A40_ES_WRITE_OPTIMIZE(1) |
1552 S_028A40_GS_WRITE_OPTIMIZE(1);
1553 }
1554
1555 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1556 {
1557 struct radv_shader_variant *vs;
1558 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : pipeline->shaders[MESA_SHADER_VERTEX];
1559
1560 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1561
1562 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1563 clip_dist_mask = outinfo->clip_dist_mask;
1564 cull_dist_mask = outinfo->cull_dist_mask;
1565 total_mask = clip_dist_mask | cull_dist_mask;
1566
1567 bool misc_vec_ena = outinfo->writes_pointsize ||
1568 outinfo->writes_layer ||
1569 outinfo->writes_viewport_index;
1570 pipeline->graphics.pa_cl_vs_out_cntl =
1571 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1572 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1573 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1574 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1575 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1576 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1577 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1578 cull_dist_mask << 8 |
1579 clip_dist_mask;
1580
1581 }
1582 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1583 {
1584 struct radv_shader_variant *ps, *vs;
1585 struct ac_vs_output_info *outinfo;
1586
1587 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1588 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : pipeline->shaders[MESA_SHADER_VERTEX];
1589
1590 outinfo = &vs->info.vs.outinfo;
1591
1592 unsigned ps_offset = 0;
1593 if (ps->info.fs.has_pcoord) {
1594 unsigned val;
1595 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1596 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1597 ps_offset++;
1598 }
1599
1600 if (ps->info.fs.prim_id_input && (outinfo->prim_id_output != 0xffffffff)) {
1601 unsigned vs_offset, flat_shade;
1602 unsigned val;
1603 vs_offset = outinfo->prim_id_output;
1604 flat_shade = true;
1605 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
1606 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1607 ++ps_offset;
1608 }
1609
1610 if (ps->info.fs.layer_input && (outinfo->layer_output != 0xffffffff)) {
1611 unsigned vs_offset, flat_shade;
1612 unsigned val;
1613 vs_offset = outinfo->layer_output;
1614 flat_shade = true;
1615 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
1616 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1617 ++ps_offset;
1618 }
1619
1620 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1621 unsigned vs_offset, flat_shade;
1622 unsigned val;
1623
1624 if (!(ps->info.fs.input_mask & (1u << i)))
1625 continue;
1626
1627 if (!(outinfo->export_mask & (1u << i))) {
1628 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1629 ++ps_offset;
1630 continue;
1631 }
1632
1633 vs_offset = util_bitcount(outinfo->export_mask & ((1u << i) - 1));
1634 if (outinfo->prim_id_output != 0xffffffff) {
1635 if (vs_offset >= outinfo->prim_id_output)
1636 vs_offset++;
1637 }
1638 if (outinfo->layer_output != 0xffffffff) {
1639 if (vs_offset >= outinfo->layer_output)
1640 vs_offset++;
1641 }
1642 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1643
1644 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
1645 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1646 ++ps_offset;
1647 }
1648
1649 pipeline->graphics.ps_input_cntl_num = ps_offset;
1650 }
1651
1652 VkResult
1653 radv_pipeline_init(struct radv_pipeline *pipeline,
1654 struct radv_device *device,
1655 struct radv_pipeline_cache *cache,
1656 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1657 const struct radv_graphics_pipeline_create_info *extra,
1658 const VkAllocationCallbacks *alloc)
1659 {
1660 struct radv_shader_module fs_m = {0};
1661 VkResult result;
1662
1663 if (alloc == NULL)
1664 alloc = &device->alloc;
1665
1666 pipeline->device = device;
1667 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1668
1669 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1670 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1671 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1672 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1673 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1674 pStages[stage] = &pCreateInfo->pStages[i];
1675 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1676 }
1677
1678 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1679
1680 if (modules[MESA_SHADER_VERTEX]) {
1681 bool as_es = modules[MESA_SHADER_GEOMETRY] != NULL;
1682 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es);
1683
1684 pipeline->shaders[MESA_SHADER_VERTEX] =
1685 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1686 pStages[MESA_SHADER_VERTEX]->pName,
1687 MESA_SHADER_VERTEX,
1688 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1689 pipeline->layout, &key);
1690
1691 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1692 }
1693
1694 if (modules[MESA_SHADER_GEOMETRY]) {
1695 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false);
1696
1697 pipeline->shaders[MESA_SHADER_GEOMETRY] =
1698 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
1699 pStages[MESA_SHADER_GEOMETRY]->pName,
1700 MESA_SHADER_GEOMETRY,
1701 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
1702 pipeline->layout, &key);
1703
1704 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
1705 calculate_gs_ring_sizes(pipeline);
1706
1707 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
1708 } else
1709 pipeline->graphics.vgt_gs_mode = 0;
1710
1711 if (!modules[MESA_SHADER_FRAGMENT]) {
1712 nir_builder fs_b;
1713 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1714 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
1715 fs_m.nir = fs_b.shader;
1716 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1717 }
1718
1719 if (modules[MESA_SHADER_FRAGMENT]) {
1720 union ac_shader_variant_key key;
1721 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1722 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
1723
1724 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1725
1726 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1727 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1728 stage ? stage->pName : "main",
1729 MESA_SHADER_FRAGMENT,
1730 stage ? stage->pSpecializationInfo : NULL,
1731 pipeline->layout, &key);
1732 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1733 }
1734
1735 if (fs_m.nir)
1736 ralloc_free(fs_m.nir);
1737
1738 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1739 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1740 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1741 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1742 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
1743
1744 if (radv_pipeline_has_gs(pipeline)) {
1745 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
1746 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1747 } else {
1748 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1749 }
1750 if (extra && extra->use_rectlist) {
1751 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1752 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1753 pipeline->graphics.can_use_guardband = true;
1754 }
1755 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1756 /* prim vertex count will need TESS changes */
1757 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
1758
1759 /* Ensure that some export memory is always allocated, for two reasons:
1760 *
1761 * 1) Correctness: The hardware ignores the EXEC mask if no export
1762 * memory is allocated, so KILL and alpha test do not work correctly
1763 * without this.
1764 * 2) Performance: Every shader needs at least a NULL export, even when
1765 * it writes no color/depth output. The NULL export instruction
1766 * stalls without this setting.
1767 *
1768 * Don't add this to CB_SHADER_MASK.
1769 */
1770 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1771 if (!pipeline->graphics.blend.spi_shader_col_format) {
1772 if (!ps->info.fs.writes_z &&
1773 !ps->info.fs.writes_stencil &&
1774 !ps->info.fs.writes_sample_mask)
1775 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1776 }
1777
1778 unsigned z_order;
1779 pipeline->graphics.db_shader_control = 0;
1780 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
1781 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
1782 else
1783 z_order = V_02880C_LATE_Z;
1784
1785 pipeline->graphics.db_shader_control =
1786 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
1787 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
1788 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
1789 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
1790 S_02880C_Z_ORDER(z_order) |
1791 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
1792 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
1793 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
1794
1795 pipeline->graphics.shader_z_format =
1796 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
1797 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
1798 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
1799 V_028710_SPI_SHADER_ZERO;
1800
1801 calculate_pa_cl_vs_out_cntl(pipeline);
1802 calculate_ps_inputs(pipeline);
1803
1804 uint32_t stages = 0;
1805 if (radv_pipeline_has_gs(pipeline))
1806 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1807 S_028B54_GS_EN(1) |
1808 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1809 pipeline->graphics.vgt_shader_stages_en = stages;
1810
1811 const VkPipelineVertexInputStateCreateInfo *vi_info =
1812 pCreateInfo->pVertexInputState;
1813 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1814 const VkVertexInputAttributeDescription *desc =
1815 &vi_info->pVertexAttributeDescriptions[i];
1816 unsigned loc = desc->location;
1817 const struct vk_format_description *format_desc;
1818 int first_non_void;
1819 uint32_t num_format, data_format;
1820 format_desc = vk_format_description(desc->format);
1821 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1822
1823 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1824 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1825
1826 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
1827 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
1828 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
1829 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
1830 S_008F0C_NUM_FORMAT(num_format) |
1831 S_008F0C_DATA_FORMAT(data_format);
1832 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
1833 pipeline->va_offset[loc] = desc->offset;
1834 pipeline->va_binding[loc] = desc->binding;
1835 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
1836 }
1837
1838 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1839 const VkVertexInputBindingDescription *desc =
1840 &vi_info->pVertexBindingDescriptions[i];
1841
1842 pipeline->binding_stride[desc->binding] = desc->stride;
1843 }
1844
1845 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1846 radv_dump_pipeline_stats(device, pipeline);
1847 }
1848
1849 result = radv_pipeline_scratch_init(device, pipeline);
1850 return result;
1851 }
1852
1853 VkResult
1854 radv_graphics_pipeline_create(
1855 VkDevice _device,
1856 VkPipelineCache _cache,
1857 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1858 const struct radv_graphics_pipeline_create_info *extra,
1859 const VkAllocationCallbacks *pAllocator,
1860 VkPipeline *pPipeline)
1861 {
1862 RADV_FROM_HANDLE(radv_device, device, _device);
1863 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1864 struct radv_pipeline *pipeline;
1865 VkResult result;
1866
1867 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1868 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1869 if (pipeline == NULL)
1870 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1871
1872 memset(pipeline, 0, sizeof(*pipeline));
1873 result = radv_pipeline_init(pipeline, device, cache,
1874 pCreateInfo, extra, pAllocator);
1875 if (result != VK_SUCCESS) {
1876 radv_pipeline_destroy(device, pipeline, pAllocator);
1877 return result;
1878 }
1879
1880 *pPipeline = radv_pipeline_to_handle(pipeline);
1881
1882 return VK_SUCCESS;
1883 }
1884
1885 VkResult radv_CreateGraphicsPipelines(
1886 VkDevice _device,
1887 VkPipelineCache pipelineCache,
1888 uint32_t count,
1889 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1890 const VkAllocationCallbacks* pAllocator,
1891 VkPipeline* pPipelines)
1892 {
1893 VkResult result = VK_SUCCESS;
1894 unsigned i = 0;
1895
1896 for (; i < count; i++) {
1897 VkResult r;
1898 r = radv_graphics_pipeline_create(_device,
1899 pipelineCache,
1900 &pCreateInfos[i],
1901 NULL, pAllocator, &pPipelines[i]);
1902 if (r != VK_SUCCESS) {
1903 result = r;
1904 pPipelines[i] = VK_NULL_HANDLE;
1905 }
1906 }
1907
1908 return result;
1909 }
1910
1911 static VkResult radv_compute_pipeline_create(
1912 VkDevice _device,
1913 VkPipelineCache _cache,
1914 const VkComputePipelineCreateInfo* pCreateInfo,
1915 const VkAllocationCallbacks* pAllocator,
1916 VkPipeline* pPipeline)
1917 {
1918 RADV_FROM_HANDLE(radv_device, device, _device);
1919 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1920 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
1921 struct radv_pipeline *pipeline;
1922 VkResult result;
1923
1924 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1925 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1926 if (pipeline == NULL)
1927 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1928
1929 memset(pipeline, 0, sizeof(*pipeline));
1930 pipeline->device = device;
1931 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1932
1933 pipeline->shaders[MESA_SHADER_COMPUTE] =
1934 radv_pipeline_compile(pipeline, cache, module,
1935 pCreateInfo->stage.pName,
1936 MESA_SHADER_COMPUTE,
1937 pCreateInfo->stage.pSpecializationInfo,
1938 pipeline->layout, NULL);
1939
1940
1941 result = radv_pipeline_scratch_init(device, pipeline);
1942 if (result != VK_SUCCESS) {
1943 radv_pipeline_destroy(device, pipeline, pAllocator);
1944 return result;
1945 }
1946
1947 *pPipeline = radv_pipeline_to_handle(pipeline);
1948
1949 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1950 radv_dump_pipeline_stats(device, pipeline);
1951 }
1952 return VK_SUCCESS;
1953 }
1954 VkResult radv_CreateComputePipelines(
1955 VkDevice _device,
1956 VkPipelineCache pipelineCache,
1957 uint32_t count,
1958 const VkComputePipelineCreateInfo* pCreateInfos,
1959 const VkAllocationCallbacks* pAllocator,
1960 VkPipeline* pPipelines)
1961 {
1962 VkResult result = VK_SUCCESS;
1963
1964 unsigned i = 0;
1965 for (; i < count; i++) {
1966 VkResult r;
1967 r = radv_compute_pipeline_create(_device, pipelineCache,
1968 &pCreateInfos[i],
1969 pAllocator, &pPipelines[i]);
1970 if (r != VK_SUCCESS) {
1971 result = r;
1972 pPipelines[i] = VK_NULL_HANDLE;
1973 }
1974 }
1975
1976 return result;
1977 }