projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv/gfx10: add an option to switch from legacy to NGG streamout
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
38 #include "vk_util.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/TargetMachine.h>
42
43 #include "sid.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
52
53 struct radv_blend_state {
54 uint32_t blend_enable_4bit;
55 uint32_t need_src_alpha;
56
57 uint32_t cb_color_control;
58 uint32_t cb_target_mask;
59 uint32_t cb_target_enabled_4bit;
60 uint32_t sx_mrt_blend_opt[8];
61 uint32_t cb_blend_control[8];
62
63 uint32_t spi_shader_col_format;
64 uint32_t cb_shader_mask;
65 uint32_t db_alpha_to_mask;
66
67 uint32_t commutative_4bit;
68
69 bool single_cb_enable;
70 bool mrt0_is_dual_src;
71 };
72
73 struct radv_dsa_order_invariance {
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
76 */
77 bool zs;
78
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
81 * fragments arrive.
82 */
83 bool pass_set;
84 };
85
86 struct radv_tessellation_state {
87 uint32_t ls_hs_config;
88 unsigned num_patches;
89 unsigned lds_size;
90 uint32_t tf_param;
91 };
92
93 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
94 {
95 struct radv_shader_variant *variant = NULL;
96 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
97 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
98 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
99 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
100 else if (pipeline->shaders[MESA_SHADER_VERTEX])
101 variant = pipeline->shaders[MESA_SHADER_VERTEX];
102 else
103 return false;
104 return variant->info.is_ngg;
105 }
106
107 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
108 {
109 if (!radv_pipeline_has_gs(pipeline))
110 return false;
111
112 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
113 * On GFX10, it might be required in rare cases if it's not possible to
114 * enable NGG.
115 */
116 if (radv_pipeline_has_ngg(pipeline))
117 return false;
118
119 assert(pipeline->gs_copy_shader);
120 return true;
121 }
122
123 static void
124 radv_pipeline_destroy(struct radv_device *device,
125 struct radv_pipeline *pipeline,
126 const VkAllocationCallbacks* allocator)
127 {
128 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
129 if (pipeline->shaders[i])
130 radv_shader_variant_destroy(device, pipeline->shaders[i]);
131
132 if (pipeline->gs_copy_shader)
133 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
134
135 if(pipeline->cs.buf)
136 free(pipeline->cs.buf);
137 vk_free2(&device->alloc, allocator, pipeline);
138 }
139
140 void radv_DestroyPipeline(
141 VkDevice _device,
142 VkPipeline _pipeline,
143 const VkAllocationCallbacks* pAllocator)
144 {
145 RADV_FROM_HANDLE(radv_device, device, _device);
146 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
147
148 if (!_pipeline)
149 return;
150
151 radv_pipeline_destroy(device, pipeline, pAllocator);
152 }
153
154 static uint32_t get_hash_flags(struct radv_device *device)
155 {
156 uint32_t hash_flags = 0;
157
158 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
159 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
160 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
161 hash_flags |= RADV_HASH_SHADER_NO_NGG;
162 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
163 hash_flags |= RADV_HASH_SHADER_SISCHED;
164 if (device->physical_device->cs_wave_size == 32)
165 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
166 if (device->physical_device->ps_wave_size == 32)
167 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
168 if (device->physical_device->ge_wave_size == 32)
169 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
170 return hash_flags;
171 }
172
173 static VkResult
174 radv_pipeline_scratch_init(struct radv_device *device,
175 struct radv_pipeline *pipeline)
176 {
177 unsigned scratch_bytes_per_wave = 0;
178 unsigned max_waves = 0;
179 unsigned min_waves = 1;
180
181 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
182 if (pipeline->shaders[i]) {
183 unsigned max_stage_waves = device->scratch_waves;
184
185 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
186 pipeline->shaders[i]->config.scratch_bytes_per_wave);
187
188 max_stage_waves = MIN2(max_stage_waves,
189 4 * device->physical_device->rad_info.num_good_compute_units *
190 (256 / pipeline->shaders[i]->config.num_vgprs));
191 max_waves = MAX2(max_waves, max_stage_waves);
192 }
193 }
194
195 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
196 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
197 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
198 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
199 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
200 }
201
202 if (scratch_bytes_per_wave)
203 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
204
205 if (scratch_bytes_per_wave && max_waves < min_waves) {
206 /* Not really true at this moment, but will be true on first
207 * execution. Avoid having hanging shaders. */
208 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
209 }
210 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
211 pipeline->max_waves = max_waves;
212 return VK_SUCCESS;
213 }
214
215 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
216 {
217 switch (op) {
218 case VK_LOGIC_OP_CLEAR:
219 return V_028808_ROP3_CLEAR;
220 case VK_LOGIC_OP_AND:
221 return V_028808_ROP3_AND;
222 case VK_LOGIC_OP_AND_REVERSE:
223 return V_028808_ROP3_AND_REVERSE;
224 case VK_LOGIC_OP_COPY:
225 return V_028808_ROP3_COPY;
226 case VK_LOGIC_OP_AND_INVERTED:
227 return V_028808_ROP3_AND_INVERTED;
228 case VK_LOGIC_OP_NO_OP:
229 return V_028808_ROP3_NO_OP;
230 case VK_LOGIC_OP_XOR:
231 return V_028808_ROP3_XOR;
232 case VK_LOGIC_OP_OR:
233 return V_028808_ROP3_OR;
234 case VK_LOGIC_OP_NOR:
235 return V_028808_ROP3_NOR;
236 case VK_LOGIC_OP_EQUIVALENT:
237 return V_028808_ROP3_EQUIVALENT;
238 case VK_LOGIC_OP_INVERT:
239 return V_028808_ROP3_INVERT;
240 case VK_LOGIC_OP_OR_REVERSE:
241 return V_028808_ROP3_OR_REVERSE;
242 case VK_LOGIC_OP_COPY_INVERTED:
243 return V_028808_ROP3_COPY_INVERTED;
244 case VK_LOGIC_OP_OR_INVERTED:
245 return V_028808_ROP3_OR_INVERTED;
246 case VK_LOGIC_OP_NAND:
247 return V_028808_ROP3_NAND;
248 case VK_LOGIC_OP_SET:
249 return V_028808_ROP3_SET;
250 default:
251 unreachable("Unhandled logic op");
252 }
253 }
254
255
256 static uint32_t si_translate_blend_function(VkBlendOp op)
257 {
258 switch (op) {
259 case VK_BLEND_OP_ADD:
260 return V_028780_COMB_DST_PLUS_SRC;
261 case VK_BLEND_OP_SUBTRACT:
262 return V_028780_COMB_SRC_MINUS_DST;
263 case VK_BLEND_OP_REVERSE_SUBTRACT:
264 return V_028780_COMB_DST_MINUS_SRC;
265 case VK_BLEND_OP_MIN:
266 return V_028780_COMB_MIN_DST_SRC;
267 case VK_BLEND_OP_MAX:
268 return V_028780_COMB_MAX_DST_SRC;
269 default:
270 return 0;
271 }
272 }
273
274 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
275 {
276 switch (factor) {
277 case VK_BLEND_FACTOR_ZERO:
278 return V_028780_BLEND_ZERO;
279 case VK_BLEND_FACTOR_ONE:
280 return V_028780_BLEND_ONE;
281 case VK_BLEND_FACTOR_SRC_COLOR:
282 return V_028780_BLEND_SRC_COLOR;
283 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
284 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
285 case VK_BLEND_FACTOR_DST_COLOR:
286 return V_028780_BLEND_DST_COLOR;
287 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
288 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
289 case VK_BLEND_FACTOR_SRC_ALPHA:
290 return V_028780_BLEND_SRC_ALPHA;
291 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
292 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
293 case VK_BLEND_FACTOR_DST_ALPHA:
294 return V_028780_BLEND_DST_ALPHA;
295 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
296 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
297 case VK_BLEND_FACTOR_CONSTANT_COLOR:
298 return V_028780_BLEND_CONSTANT_COLOR;
299 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
300 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
301 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
302 return V_028780_BLEND_CONSTANT_ALPHA;
303 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
304 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
305 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
306 return V_028780_BLEND_SRC_ALPHA_SATURATE;
307 case VK_BLEND_FACTOR_SRC1_COLOR:
308 return V_028780_BLEND_SRC1_COLOR;
309 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
310 return V_028780_BLEND_INV_SRC1_COLOR;
311 case VK_BLEND_FACTOR_SRC1_ALPHA:
312 return V_028780_BLEND_SRC1_ALPHA;
313 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
314 return V_028780_BLEND_INV_SRC1_ALPHA;
315 default:
316 return 0;
317 }
318 }
319
320 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
321 {
322 switch (op) {
323 case VK_BLEND_OP_ADD:
324 return V_028760_OPT_COMB_ADD;
325 case VK_BLEND_OP_SUBTRACT:
326 return V_028760_OPT_COMB_SUBTRACT;
327 case VK_BLEND_OP_REVERSE_SUBTRACT:
328 return V_028760_OPT_COMB_REVSUBTRACT;
329 case VK_BLEND_OP_MIN:
330 return V_028760_OPT_COMB_MIN;
331 case VK_BLEND_OP_MAX:
332 return V_028760_OPT_COMB_MAX;
333 default:
334 return V_028760_OPT_COMB_BLEND_DISABLED;
335 }
336 }
337
338 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
339 {
340 switch (factor) {
341 case VK_BLEND_FACTOR_ZERO:
342 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
343 case VK_BLEND_FACTOR_ONE:
344 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
345 case VK_BLEND_FACTOR_SRC_COLOR:
346 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
347 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
348 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
349 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
350 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
351 case VK_BLEND_FACTOR_SRC_ALPHA:
352 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
353 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
354 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
355 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
357 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
358 default:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
360 }
361 }
362
363 /**
364 * Get rid of DST in the blend factors by commuting the operands:
365 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
366 */
367 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
368 unsigned *dst_factor, unsigned expected_dst,
369 unsigned replacement_src)
370 {
371 if (*src_factor == expected_dst &&
372 *dst_factor == VK_BLEND_FACTOR_ZERO) {
373 *src_factor = VK_BLEND_FACTOR_ZERO;
374 *dst_factor = replacement_src;
375
376 /* Commuting the operands requires reversing subtractions. */
377 if (*func == VK_BLEND_OP_SUBTRACT)
378 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
379 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
380 *func = VK_BLEND_OP_SUBTRACT;
381 }
382 }
383
384 static bool si_blend_factor_uses_dst(unsigned factor)
385 {
386 return factor == VK_BLEND_FACTOR_DST_COLOR ||
387 factor == VK_BLEND_FACTOR_DST_ALPHA ||
388 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
389 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
390 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
391 }
392
393 static bool is_dual_src(VkBlendFactor factor)
394 {
395 switch (factor) {
396 case VK_BLEND_FACTOR_SRC1_COLOR:
397 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
398 case VK_BLEND_FACTOR_SRC1_ALPHA:
399 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
400 return true;
401 default:
402 return false;
403 }
404 }
405
406 static unsigned si_choose_spi_color_format(VkFormat vk_format,
407 bool blend_enable,
408 bool blend_need_alpha)
409 {
410 const struct vk_format_description *desc = vk_format_description(vk_format);
411 unsigned format, ntype, swap;
412
413 /* Alpha is needed for alpha-to-coverage.
414 * Blending may be with or without alpha.
415 */
416 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
417 unsigned alpha = 0; /* exports alpha, but may not support blending */
418 unsigned blend = 0; /* supports blending, but may not export alpha */
419 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
420
421 format = radv_translate_colorformat(vk_format);
422 ntype = radv_translate_color_numformat(vk_format, desc,
423 vk_format_get_first_non_void_channel(vk_format));
424 swap = radv_translate_colorswap(vk_format, false);
425
426 /* Choose the SPI color formats. These are required values for Stoney/RB+.
427 * Other chips have multiple choices, though they are not necessarily better.
428 */
429 switch (format) {
430 case V_028C70_COLOR_5_6_5:
431 case V_028C70_COLOR_1_5_5_5:
432 case V_028C70_COLOR_5_5_5_1:
433 case V_028C70_COLOR_4_4_4_4:
434 case V_028C70_COLOR_10_11_11:
435 case V_028C70_COLOR_11_11_10:
436 case V_028C70_COLOR_8:
437 case V_028C70_COLOR_8_8:
438 case V_028C70_COLOR_8_8_8_8:
439 case V_028C70_COLOR_10_10_10_2:
440 case V_028C70_COLOR_2_10_10_10:
441 if (ntype == V_028C70_NUMBER_UINT)
442 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
443 else if (ntype == V_028C70_NUMBER_SINT)
444 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
445 else
446 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
447 break;
448
449 case V_028C70_COLOR_16:
450 case V_028C70_COLOR_16_16:
451 case V_028C70_COLOR_16_16_16_16:
452 if (ntype == V_028C70_NUMBER_UNORM ||
453 ntype == V_028C70_NUMBER_SNORM) {
454 /* UNORM16 and SNORM16 don't support blending */
455 if (ntype == V_028C70_NUMBER_UNORM)
456 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
457 else
458 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
459
460 /* Use 32 bits per channel for blending. */
461 if (format == V_028C70_COLOR_16) {
462 if (swap == V_028C70_SWAP_STD) { /* R */
463 blend = V_028714_SPI_SHADER_32_R;
464 blend_alpha = V_028714_SPI_SHADER_32_AR;
465 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
466 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
467 else
468 assert(0);
469 } else if (format == V_028C70_COLOR_16_16) {
470 if (swap == V_028C70_SWAP_STD) { /* RG */
471 blend = V_028714_SPI_SHADER_32_GR;
472 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
473 } else if (swap == V_028C70_SWAP_ALT) /* RA */
474 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
475 else
476 assert(0);
477 } else /* 16_16_16_16 */
478 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
479 } else if (ntype == V_028C70_NUMBER_UINT)
480 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
481 else if (ntype == V_028C70_NUMBER_SINT)
482 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
483 else if (ntype == V_028C70_NUMBER_FLOAT)
484 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
485 else
486 assert(0);
487 break;
488
489 case V_028C70_COLOR_32:
490 if (swap == V_028C70_SWAP_STD) { /* R */
491 blend = normal = V_028714_SPI_SHADER_32_R;
492 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
493 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
494 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
495 else
496 assert(0);
497 break;
498
499 case V_028C70_COLOR_32_32:
500 if (swap == V_028C70_SWAP_STD) { /* RG */
501 blend = normal = V_028714_SPI_SHADER_32_GR;
502 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
503 } else if (swap == V_028C70_SWAP_ALT) /* RA */
504 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
505 else
506 assert(0);
507 break;
508
509 case V_028C70_COLOR_32_32_32_32:
510 case V_028C70_COLOR_8_24:
511 case V_028C70_COLOR_24_8:
512 case V_028C70_COLOR_X24_8_32_FLOAT:
513 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
514 break;
515
516 default:
517 unreachable("unhandled blend format");
518 }
519
520 if (blend_enable && blend_need_alpha)
521 return blend_alpha;
522 else if(blend_need_alpha)
523 return alpha;
524 else if(blend_enable)
525 return blend;
526 else
527 return normal;
528 }
529
530 static void
531 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
532 const VkGraphicsPipelineCreateInfo *pCreateInfo,
533 struct radv_blend_state *blend)
534 {
535 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
536 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
537 unsigned col_format = 0;
538 unsigned num_targets;
539
540 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
541 unsigned cf;
542
543 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
544 cf = V_028714_SPI_SHADER_ZERO;
545 } else {
546 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
547 bool blend_enable =
548 blend->blend_enable_4bit & (0xfu << (i * 4));
549
550 cf = si_choose_spi_color_format(attachment->format,
551 blend_enable,
552 blend->need_src_alpha & (1 << i));
553 }
554
555 col_format |= cf << (4 * i);
556 }
557
558 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
559 /* When a subpass doesn't have any color attachments, write the
560 * alpha channel of MRT0 when alpha coverage is enabled because
561 * the depth attachment needs it.
562 */
563 col_format |= V_028714_SPI_SHADER_32_AR;
564 }
565
566 /* If the i-th target format is set, all previous target formats must
567 * be non-zero to avoid hangs.
568 */
569 num_targets = (util_last_bit(col_format) + 3) / 4;
570 for (unsigned i = 0; i < num_targets; i++) {
571 if (!(col_format & (0xf << (i * 4)))) {
572 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
573 }
574 }
575
576 /* The output for dual source blending should have the same format as
577 * the first output.
578 */
579 if (blend->mrt0_is_dual_src)
580 col_format |= (col_format & 0xf) << 4;
581
582 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
583 blend->spi_shader_col_format = col_format;
584 }
585
586 static bool
587 format_is_int8(VkFormat format)
588 {
589 const struct vk_format_description *desc = vk_format_description(format);
590 int channel = vk_format_get_first_non_void_channel(format);
591
592 return channel >= 0 && desc->channel[channel].pure_integer &&
593 desc->channel[channel].size == 8;
594 }
595
596 static bool
597 format_is_int10(VkFormat format)
598 {
599 const struct vk_format_description *desc = vk_format_description(format);
600
601 if (desc->nr_channels != 4)
602 return false;
603 for (unsigned i = 0; i < 4; i++) {
604 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
605 return true;
606 }
607 return false;
608 }
609
610 /*
611 * Ordered so that for each i,
612 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
613 */
614 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
615 VK_FORMAT_R32_SFLOAT,
616 VK_FORMAT_R32G32_SFLOAT,
617 VK_FORMAT_R8G8B8A8_UNORM,
618 VK_FORMAT_R16G16B16A16_UNORM,
619 VK_FORMAT_R16G16B16A16_SNORM,
620 VK_FORMAT_R16G16B16A16_UINT,
621 VK_FORMAT_R16G16B16A16_SINT,
622 VK_FORMAT_R32G32B32A32_SFLOAT,
623 VK_FORMAT_R8G8B8A8_UINT,
624 VK_FORMAT_R8G8B8A8_SINT,
625 VK_FORMAT_A2R10G10B10_UINT_PACK32,
626 VK_FORMAT_A2R10G10B10_SINT_PACK32,
627 };
628
629 unsigned radv_format_meta_fs_key(VkFormat format)
630 {
631 unsigned col_format = si_choose_spi_color_format(format, false, false);
632
633 assert(col_format != V_028714_SPI_SHADER_32_AR);
634 if (col_format >= V_028714_SPI_SHADER_32_AR)
635 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
636
637 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
638 bool is_int8 = format_is_int8(format);
639 bool is_int10 = format_is_int10(format);
640
641 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
642 }
643
644 static void
645 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
646 unsigned *is_int8, unsigned *is_int10)
647 {
648 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
649 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
650 *is_int8 = 0;
651 *is_int10 = 0;
652
653 for (unsigned i = 0; i < subpass->color_count; ++i) {
654 struct radv_render_pass_attachment *attachment;
655
656 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
657 continue;
658
659 attachment = pass->attachments + subpass->color_attachments[i].attachment;
660
661 if (format_is_int8(attachment->format))
662 *is_int8 |= 1 << i;
663 if (format_is_int10(attachment->format))
664 *is_int10 |= 1 << i;
665 }
666 }
667
668 static void
669 radv_blend_check_commutativity(struct radv_blend_state *blend,
670 VkBlendOp op, VkBlendFactor src,
671 VkBlendFactor dst, unsigned chanmask)
672 {
673 /* Src factor is allowed when it does not depend on Dst. */
674 static const uint32_t src_allowed =
675 (1u << VK_BLEND_FACTOR_ONE) |
676 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
677 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
678 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
679 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
680 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
681 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
682 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
683 (1u << VK_BLEND_FACTOR_ZERO) |
684 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
685 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
686 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
687 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
688 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
689 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
690
691 if (dst == VK_BLEND_FACTOR_ONE &&
692 (src_allowed & (1u << src))) {
693 /* Addition is commutative, but floating point addition isn't
694 * associative: subtle changes can be introduced via different
695 * rounding. Be conservative, only enable for min and max.
696 */
697 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
698 blend->commutative_4bit |= chanmask;
699 }
700 }
701
702 static struct radv_blend_state
703 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
704 const VkGraphicsPipelineCreateInfo *pCreateInfo,
705 const struct radv_graphics_pipeline_create_info *extra)
706 {
707 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
708 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
709 struct radv_blend_state blend = {0};
710 unsigned mode = V_028808_CB_NORMAL;
711 int i;
712
713 if (!vkblend)
714 return blend;
715
716 if (extra && extra->custom_blend_mode) {
717 blend.single_cb_enable = true;
718 mode = extra->custom_blend_mode;
719 }
720 blend.cb_color_control = 0;
721 if (vkblend->logicOpEnable)
722 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
723 else
724 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
725
726 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
727 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
728 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
729 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
730 S_028B70_OFFSET_ROUND(1);
731
732 if (vkms && vkms->alphaToCoverageEnable) {
733 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
734 blend.need_src_alpha |= 0x1;
735 }
736
737 blend.cb_target_mask = 0;
738 for (i = 0; i < vkblend->attachmentCount; i++) {
739 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
740 unsigned blend_cntl = 0;
741 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
742 VkBlendOp eqRGB = att->colorBlendOp;
743 VkBlendFactor srcRGB = att->srcColorBlendFactor;
744 VkBlendFactor dstRGB = att->dstColorBlendFactor;
745 VkBlendOp eqA = att->alphaBlendOp;
746 VkBlendFactor srcA = att->srcAlphaBlendFactor;
747 VkBlendFactor dstA = att->dstAlphaBlendFactor;
748
749 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
750
751 if (!att->colorWriteMask)
752 continue;
753
754 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
755 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
756 if (!att->blendEnable) {
757 blend.cb_blend_control[i] = blend_cntl;
758 continue;
759 }
760
761 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
762 if (i == 0)
763 blend.mrt0_is_dual_src = true;
764
765 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
766 srcRGB = VK_BLEND_FACTOR_ONE;
767 dstRGB = VK_BLEND_FACTOR_ONE;
768 }
769 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
770 srcA = VK_BLEND_FACTOR_ONE;
771 dstA = VK_BLEND_FACTOR_ONE;
772 }
773
774 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
775 0x7 << (4 * i));
776 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
777 0x8 << (4 * i));
778
779 /* Blending optimizations for RB+.
780 * These transformations don't change the behavior.
781 *
782 * First, get rid of DST in the blend factors:
783 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
784 */
785 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
786 VK_BLEND_FACTOR_DST_COLOR,
787 VK_BLEND_FACTOR_SRC_COLOR);
788
789 si_blend_remove_dst(&eqA, &srcA, &dstA,
790 VK_BLEND_FACTOR_DST_COLOR,
791 VK_BLEND_FACTOR_SRC_COLOR);
792
793 si_blend_remove_dst(&eqA, &srcA, &dstA,
794 VK_BLEND_FACTOR_DST_ALPHA,
795 VK_BLEND_FACTOR_SRC_ALPHA);
796
797 /* Look up the ideal settings from tables. */
798 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
799 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
800 srcA_opt = si_translate_blend_opt_factor(srcA, true);
801 dstA_opt = si_translate_blend_opt_factor(dstA, true);
802
803 /* Handle interdependencies. */
804 if (si_blend_factor_uses_dst(srcRGB))
805 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
806 if (si_blend_factor_uses_dst(srcA))
807 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
808
809 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
810 (dstRGB == VK_BLEND_FACTOR_ZERO ||
811 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
812 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
813 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
814
815 /* Set the final value. */
816 blend.sx_mrt_blend_opt[i] =
817 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
818 S_028760_COLOR_DST_OPT(dstRGB_opt) |
819 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
820 S_028760_ALPHA_SRC_OPT(srcA_opt) |
821 S_028760_ALPHA_DST_OPT(dstA_opt) |
822 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
823 blend_cntl |= S_028780_ENABLE(1);
824
825 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
826 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
827 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
828 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
829 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
830 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
831 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
832 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
833 }
834 blend.cb_blend_control[i] = blend_cntl;
835
836 blend.blend_enable_4bit |= 0xfu << (i * 4);
837
838 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
839 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
840 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
841 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
842 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
843 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
844 blend.need_src_alpha |= 1 << i;
845 }
846 for (i = vkblend->attachmentCount; i < 8; i++) {
847 blend.cb_blend_control[i] = 0;
848 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
849 }
850
851 if (pipeline->device->physical_device->rad_info.has_rbplus) {
852 /* Disable RB+ blend optimizations for dual source blending. */
853 if (blend.mrt0_is_dual_src) {
854 for (i = 0; i < 8; i++) {
855 blend.sx_mrt_blend_opt[i] =
856 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
857 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
858 }
859 }
860
861 /* RB+ doesn't work with dual source blending, logic op and
862 * RESOLVE.
863 */
864 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
865 mode == V_028808_CB_RESOLVE)
866 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
867 }
868
869 if (blend.cb_target_mask)
870 blend.cb_color_control |= S_028808_MODE(mode);
871 else
872 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
873
874 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
875 return blend;
876 }
877
878 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
879 {
880 switch (op) {
881 case VK_STENCIL_OP_KEEP:
882 return V_02842C_STENCIL_KEEP;
883 case VK_STENCIL_OP_ZERO:
884 return V_02842C_STENCIL_ZERO;
885 case VK_STENCIL_OP_REPLACE:
886 return V_02842C_STENCIL_REPLACE_TEST;
887 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
888 return V_02842C_STENCIL_ADD_CLAMP;
889 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
890 return V_02842C_STENCIL_SUB_CLAMP;
891 case VK_STENCIL_OP_INVERT:
892 return V_02842C_STENCIL_INVERT;
893 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
894 return V_02842C_STENCIL_ADD_WRAP;
895 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
896 return V_02842C_STENCIL_SUB_WRAP;
897 default:
898 return 0;
899 }
900 }
901
902 static uint32_t si_translate_fill(VkPolygonMode func)
903 {
904 switch(func) {
905 case VK_POLYGON_MODE_FILL:
906 return V_028814_X_DRAW_TRIANGLES;
907 case VK_POLYGON_MODE_LINE:
908 return V_028814_X_DRAW_LINES;
909 case VK_POLYGON_MODE_POINT:
910 return V_028814_X_DRAW_POINTS;
911 default:
912 assert(0);
913 return V_028814_X_DRAW_POINTS;
914 }
915 }
916
917 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
918 {
919 uint32_t num_samples = vkms->rasterizationSamples;
920 uint32_t ps_iter_samples = 1;
921
922 if (vkms->sampleShadingEnable) {
923 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
924 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
925 }
926 return ps_iter_samples;
927 }
928
929 static bool
930 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
931 {
932 return pCreateInfo->depthTestEnable &&
933 pCreateInfo->depthWriteEnable &&
934 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
935 }
936
937 static bool
938 radv_writes_stencil(const VkStencilOpState *state)
939 {
940 return state->writeMask &&
941 (state->failOp != VK_STENCIL_OP_KEEP ||
942 state->passOp != VK_STENCIL_OP_KEEP ||
943 state->depthFailOp != VK_STENCIL_OP_KEEP);
944 }
945
946 static bool
947 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
948 {
949 return pCreateInfo->stencilTestEnable &&
950 (radv_writes_stencil(&pCreateInfo->front) ||
951 radv_writes_stencil(&pCreateInfo->back));
952 }
953
954 static bool
955 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
956 {
957 return radv_is_depth_write_enabled(pCreateInfo) ||
958 radv_is_stencil_write_enabled(pCreateInfo);
959 }
960
961 static bool
962 radv_order_invariant_stencil_op(VkStencilOp op)
963 {
964 /* REPLACE is normally order invariant, except when the stencil
965 * reference value is written by the fragment shader. Tracking this
966 * interaction does not seem worth the effort, so be conservative.
967 */
968 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
969 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
970 op != VK_STENCIL_OP_REPLACE;
971 }
972
973 static bool
974 radv_order_invariant_stencil_state(const VkStencilOpState *state)
975 {
976 /* Compute whether, assuming Z writes are disabled, this stencil state
977 * is order invariant in the sense that the set of passing fragments as
978 * well as the final stencil buffer result does not depend on the order
979 * of fragments.
980 */
981 return !state->writeMask ||
982 /* The following assumes that Z writes are disabled. */
983 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
984 radv_order_invariant_stencil_op(state->passOp) &&
985 radv_order_invariant_stencil_op(state->depthFailOp)) ||
986 (state->compareOp == VK_COMPARE_OP_NEVER &&
987 radv_order_invariant_stencil_op(state->failOp));
988 }
989
990 static bool
991 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
992 struct radv_blend_state *blend,
993 const VkGraphicsPipelineCreateInfo *pCreateInfo)
994 {
995 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
996 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
997 unsigned colormask = blend->cb_target_enabled_4bit;
998
999 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1000 return false;
1001
1002 /* Be conservative if a logic operation is enabled with color buffers. */
1003 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
1004 return false;
1005
1006 /* Default depth/stencil invariance when no attachment is bound. */
1007 struct radv_dsa_order_invariance dsa_order_invariant = {
1008 .zs = true, .pass_set = true
1009 };
1010
1011 if (pCreateInfo->pDepthStencilState &&
1012 subpass->depth_stencil_attachment) {
1013 const VkPipelineDepthStencilStateCreateInfo *vkds =
1014 pCreateInfo->pDepthStencilState;
1015 struct radv_render_pass_attachment *attachment =
1016 pass->attachments + subpass->depth_stencil_attachment->attachment;
1017 bool has_stencil = vk_format_is_stencil(attachment->format);
1018 struct radv_dsa_order_invariance order_invariance[2];
1019 struct radv_shader_variant *ps =
1020 pipeline->shaders[MESA_SHADER_FRAGMENT];
1021
1022 /* Compute depth/stencil order invariance in order to know if
1023 * it's safe to enable out-of-order.
1024 */
1025 bool zfunc_is_ordered =
1026 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1027 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1028 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1029 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1030 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1031
1032 bool nozwrite_and_order_invariant_stencil =
1033 !radv_is_ds_write_enabled(vkds) ||
1034 (!radv_is_depth_write_enabled(vkds) &&
1035 radv_order_invariant_stencil_state(&vkds->front) &&
1036 radv_order_invariant_stencil_state(&vkds->back));
1037
1038 order_invariance[1].zs =
1039 nozwrite_and_order_invariant_stencil ||
1040 (!radv_is_stencil_write_enabled(vkds) &&
1041 zfunc_is_ordered);
1042 order_invariance[0].zs =
1043 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1044
1045 order_invariance[1].pass_set =
1046 nozwrite_and_order_invariant_stencil ||
1047 (!radv_is_stencil_write_enabled(vkds) &&
1048 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1049 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1050 order_invariance[0].pass_set =
1051 !radv_is_depth_write_enabled(vkds) ||
1052 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1053 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1054
1055 dsa_order_invariant = order_invariance[has_stencil];
1056 if (!dsa_order_invariant.zs)
1057 return false;
1058
1059 /* The set of PS invocations is always order invariant,
1060 * except when early Z/S tests are requested.
1061 */
1062 if (ps &&
1063 ps->info.ps.writes_memory &&
1064 ps->info.ps.early_fragment_test &&
1065 !dsa_order_invariant.pass_set)
1066 return false;
1067
1068 /* Determine if out-of-order rasterization should be disabled
1069 * when occlusion queries are used.
1070 */
1071 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1072 !dsa_order_invariant.pass_set;
1073 }
1074
1075 /* No color buffers are enabled for writing. */
1076 if (!colormask)
1077 return true;
1078
1079 unsigned blendmask = colormask & blend->blend_enable_4bit;
1080
1081 if (blendmask) {
1082 /* Only commutative blending. */
1083 if (blendmask & ~blend->commutative_4bit)
1084 return false;
1085
1086 if (!dsa_order_invariant.pass_set)
1087 return false;
1088 }
1089
1090 if (colormask & ~blendmask)
1091 return false;
1092
1093 return true;
1094 }
1095
1096 static void
1097 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1098 struct radv_blend_state *blend,
1099 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1100 {
1101 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1102 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1103 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1104 bool out_of_order_rast = false;
1105 int ps_iter_samples = 1;
1106 uint32_t mask = 0xffff;
1107
1108 if (vkms)
1109 ms->num_samples = vkms->rasterizationSamples;
1110 else
1111 ms->num_samples = 1;
1112
1113 if (vkms)
1114 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1115 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1116 ps_iter_samples = ms->num_samples;
1117 }
1118
1119 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1120 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1121 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1122 /* Out-of-order rasterization is explicitly enabled by the
1123 * application.
1124 */
1125 out_of_order_rast = true;
1126 } else {
1127 /* Determine if the driver can enable out-of-order
1128 * rasterization internally.
1129 */
1130 out_of_order_rast =
1131 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1132 }
1133
1134 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1135 ms->pa_sc_aa_config = 0;
1136 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1137 S_028804_INCOHERENT_EQAA_READS(1) |
1138 S_028804_INTERPOLATE_COMP_Z(1) |
1139 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1140 ms->pa_sc_mode_cntl_1 =
1141 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1142 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1143 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1144 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1145 /* always 1: */
1146 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1147 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1148 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1149 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1150 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1151 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1152 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1153 S_028A48_VPORT_SCISSOR_ENABLE(1);
1154
1155 if (ms->num_samples > 1) {
1156 unsigned log_samples = util_logbase2(ms->num_samples);
1157 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1158 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1159 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1160 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1161 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1162 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1163 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1164 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1165 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1166 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1167 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1168 if (ps_iter_samples > 1)
1169 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1170 }
1171
1172 if (vkms && vkms->pSampleMask) {
1173 mask = vkms->pSampleMask[0] & 0xffff;
1174 }
1175
1176 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1177 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1178 }
1179
1180 static bool
1181 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1182 {
1183 switch (topology) {
1184 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1187 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1188 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1189 return false;
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1193 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1194 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1195 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1196 return true;
1197 default:
1198 unreachable("unhandled primitive type");
1199 }
1200 }
1201
1202 static uint32_t
1203 si_translate_prim(enum VkPrimitiveTopology topology)
1204 {
1205 switch (topology) {
1206 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1207 return V_008958_DI_PT_POINTLIST;
1208 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1209 return V_008958_DI_PT_LINELIST;
1210 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1211 return V_008958_DI_PT_LINESTRIP;
1212 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1213 return V_008958_DI_PT_TRILIST;
1214 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1215 return V_008958_DI_PT_TRISTRIP;
1216 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1217 return V_008958_DI_PT_TRIFAN;
1218 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1219 return V_008958_DI_PT_LINELIST_ADJ;
1220 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1221 return V_008958_DI_PT_LINESTRIP_ADJ;
1222 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1223 return V_008958_DI_PT_TRILIST_ADJ;
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1225 return V_008958_DI_PT_TRISTRIP_ADJ;
1226 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1227 return V_008958_DI_PT_PATCH;
1228 default:
1229 assert(0);
1230 return 0;
1231 }
1232 }
1233
1234 static uint32_t
1235 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1236 {
1237 switch (gl_prim) {
1238 case 0: /* GL_POINTS */
1239 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1240 case 1: /* GL_LINES */
1241 case 3: /* GL_LINE_STRIP */
1242 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1243 case 0x8E7A: /* GL_ISOLINES */
1244 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1245
1246 case 4: /* GL_TRIANGLES */
1247 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1248 case 5: /* GL_TRIANGLE_STRIP */
1249 case 7: /* GL_QUADS */
1250 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1251 default:
1252 assert(0);
1253 return 0;
1254 }
1255 }
1256
1257 static uint32_t
1258 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1259 {
1260 switch (topology) {
1261 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1262 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1263 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1264 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1265 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1266 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1267 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1268 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1269 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1270 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1271 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1272 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1273 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1274 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1275 default:
1276 assert(0);
1277 return 0;
1278 }
1279 }
1280
1281 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1282 {
1283 switch(state) {
1284 case VK_DYNAMIC_STATE_VIEWPORT:
1285 return RADV_DYNAMIC_VIEWPORT;
1286 case VK_DYNAMIC_STATE_SCISSOR:
1287 return RADV_DYNAMIC_SCISSOR;
1288 case VK_DYNAMIC_STATE_LINE_WIDTH:
1289 return RADV_DYNAMIC_LINE_WIDTH;
1290 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1291 return RADV_DYNAMIC_DEPTH_BIAS;
1292 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1293 return RADV_DYNAMIC_BLEND_CONSTANTS;
1294 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1295 return RADV_DYNAMIC_DEPTH_BOUNDS;
1296 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1297 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1298 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1299 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1300 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1301 return RADV_DYNAMIC_STENCIL_REFERENCE;
1302 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1303 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1304 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1305 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1306 default:
1307 unreachable("Unhandled dynamic state");
1308 }
1309 }
1310
1311 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1312 {
1313 uint32_t states = RADV_DYNAMIC_ALL;
1314
1315 /* If rasterization is disabled we do not care about any of the dynamic states,
1316 * since they are all rasterization related only. */
1317 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1318 return 0;
1319
1320 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1321 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1322
1323 if (!pCreateInfo->pDepthStencilState ||
1324 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1325 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1326
1327 if (!pCreateInfo->pDepthStencilState ||
1328 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1329 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1330 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1331 RADV_DYNAMIC_STENCIL_REFERENCE);
1332
1333 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1334 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1335
1336 if (!pCreateInfo->pMultisampleState ||
1337 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1338 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1339 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1340
1341 /* TODO: blend constants & line width. */
1342
1343 return states;
1344 }
1345
1346
1347 static void
1348 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1349 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1350 {
1351 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1352 uint32_t states = needed_states;
1353 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1354 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1355
1356 pipeline->dynamic_state = default_dynamic_state;
1357 pipeline->graphics.needed_dynamic_state = needed_states;
1358
1359 if (pCreateInfo->pDynamicState) {
1360 /* Remove all of the states that are marked as dynamic */
1361 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1362 for (uint32_t s = 0; s < count; s++)
1363 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1364 }
1365
1366 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1367
1368 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1369 assert(pCreateInfo->pViewportState);
1370
1371 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1372 if (states & RADV_DYNAMIC_VIEWPORT) {
1373 typed_memcpy(dynamic->viewport.viewports,
1374 pCreateInfo->pViewportState->pViewports,
1375 pCreateInfo->pViewportState->viewportCount);
1376 }
1377 }
1378
1379 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1380 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1381 if (states & RADV_DYNAMIC_SCISSOR) {
1382 typed_memcpy(dynamic->scissor.scissors,
1383 pCreateInfo->pViewportState->pScissors,
1384 pCreateInfo->pViewportState->scissorCount);
1385 }
1386 }
1387
1388 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1389 assert(pCreateInfo->pRasterizationState);
1390 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1391 }
1392
1393 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1394 assert(pCreateInfo->pRasterizationState);
1395 dynamic->depth_bias.bias =
1396 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1397 dynamic->depth_bias.clamp =
1398 pCreateInfo->pRasterizationState->depthBiasClamp;
1399 dynamic->depth_bias.slope =
1400 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1401 }
1402
1403 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1404 *
1405 * pColorBlendState is [...] NULL if the pipeline has rasterization
1406 * disabled or if the subpass of the render pass the pipeline is
1407 * created against does not use any color attachments.
1408 */
1409 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1410 assert(pCreateInfo->pColorBlendState);
1411 typed_memcpy(dynamic->blend_constants,
1412 pCreateInfo->pColorBlendState->blendConstants, 4);
1413 }
1414
1415 /* If there is no depthstencil attachment, then don't read
1416 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1417 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1418 * no need to override the depthstencil defaults in
1419 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1420 *
1421 * Section 9.2 of the Vulkan 1.0.15 spec says:
1422 *
1423 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1424 * disabled or if the subpass of the render pass the pipeline is created
1425 * against does not use a depth/stencil attachment.
1426 */
1427 if (needed_states && subpass->depth_stencil_attachment) {
1428 assert(pCreateInfo->pDepthStencilState);
1429
1430 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1431 dynamic->depth_bounds.min =
1432 pCreateInfo->pDepthStencilState->minDepthBounds;
1433 dynamic->depth_bounds.max =
1434 pCreateInfo->pDepthStencilState->maxDepthBounds;
1435 }
1436
1437 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1438 dynamic->stencil_compare_mask.front =
1439 pCreateInfo->pDepthStencilState->front.compareMask;
1440 dynamic->stencil_compare_mask.back =
1441 pCreateInfo->pDepthStencilState->back.compareMask;
1442 }
1443
1444 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1445 dynamic->stencil_write_mask.front =
1446 pCreateInfo->pDepthStencilState->front.writeMask;
1447 dynamic->stencil_write_mask.back =
1448 pCreateInfo->pDepthStencilState->back.writeMask;
1449 }
1450
1451 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1452 dynamic->stencil_reference.front =
1453 pCreateInfo->pDepthStencilState->front.reference;
1454 dynamic->stencil_reference.back =
1455 pCreateInfo->pDepthStencilState->back.reference;
1456 }
1457 }
1458
1459 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1460 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1461 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1462 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1463 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1464 typed_memcpy(dynamic->discard_rectangle.rectangles,
1465 discard_rectangle_info->pDiscardRectangles,
1466 discard_rectangle_info->discardRectangleCount);
1467 }
1468 }
1469
1470 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1471 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1472 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1473 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1474 /* If sampleLocationsEnable is VK_FALSE, the default sample
1475 * locations are used and the values specified in
1476 * sampleLocationsInfo are ignored.
1477 */
1478 if (sample_location_info->sampleLocationsEnable) {
1479 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1480 &sample_location_info->sampleLocationsInfo;
1481
1482 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1483
1484 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1485 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1486 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1487 typed_memcpy(&dynamic->sample_location.locations[0],
1488 pSampleLocationsInfo->pSampleLocations,
1489 pSampleLocationsInfo->sampleLocationsCount);
1490 }
1491 }
1492
1493 pipeline->dynamic_state.mask = states;
1494 }
1495
1496 static void
1497 gfx9_get_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1498 const struct radv_pipeline *pipeline,
1499 nir_shader **nir,
1500 struct radv_shader_info *infos,
1501 struct gfx9_gs_info *out)
1502 {
1503 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1504 struct radv_es_output_info *es_info;
1505 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1506 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1507 else
1508 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1509 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1510 &infos[MESA_SHADER_VERTEX].vs.es_info;
1511
1512 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1513 bool uses_adjacency;
1514 switch(pCreateInfo->pInputAssemblyState->topology) {
1515 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1516 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1517 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1518 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1519 uses_adjacency = true;
1520 break;
1521 default:
1522 uses_adjacency = false;
1523 break;
1524 }
1525
1526 /* All these are in dwords: */
1527 /* We can't allow using the whole LDS, because GS waves compete with
1528 * other shader stages for LDS space. */
1529 const unsigned max_lds_size = 8 * 1024;
1530 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1531 unsigned esgs_lds_size;
1532
1533 /* All these are per subgroup: */
1534 const unsigned max_out_prims = 32 * 1024;
1535 const unsigned max_es_verts = 255;
1536 const unsigned ideal_gs_prims = 64;
1537 unsigned max_gs_prims, gs_prims;
1538 unsigned min_es_verts, es_verts, worst_case_es_verts;
1539
1540 if (uses_adjacency || gs_num_invocations > 1)
1541 max_gs_prims = 127 / gs_num_invocations;
1542 else
1543 max_gs_prims = 255;
1544
1545 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1546 * Make sure we don't go over the maximum value.
1547 */
1548 if (gs_info->gs.vertices_out > 0) {
1549 max_gs_prims = MIN2(max_gs_prims,
1550 max_out_prims /
1551 (gs_info->gs.vertices_out * gs_num_invocations));
1552 }
1553 assert(max_gs_prims > 0);
1554
1555 /* If the primitive has adjacency, halve the number of vertices
1556 * that will be reused in multiple primitives.
1557 */
1558 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1559
1560 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1561 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1562
1563 /* Compute ESGS LDS size based on the worst case number of ES vertices
1564 * needed to create the target number of GS prims per subgroup.
1565 */
1566 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1567
1568 /* If total LDS usage is too big, refactor partitions based on ratio
1569 * of ESGS item sizes.
1570 */
1571 if (esgs_lds_size > max_lds_size) {
1572 /* Our target GS Prims Per Subgroup was too large. Calculate
1573 * the maximum number of GS Prims Per Subgroup that will fit
1574 * into LDS, capped by the maximum that the hardware can support.
1575 */
1576 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1577 max_gs_prims);
1578 assert(gs_prims > 0);
1579 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1580 max_es_verts);
1581
1582 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1583 assert(esgs_lds_size <= max_lds_size);
1584 }
1585
1586 /* Now calculate remaining ESGS information. */
1587 if (esgs_lds_size)
1588 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1589 else
1590 es_verts = max_es_verts;
1591
1592 /* Vertices for adjacency primitives are not always reused, so restore
1593 * it for ES_VERTS_PER_SUBGRP.
1594 */
1595 min_es_verts = gs_info->gs.vertices_in;
1596
1597 /* For normal primitives, the VGT only checks if they are past the ES
1598 * verts per subgroup after allocating a full GS primitive and if they
1599 * are, kick off a new subgroup. But if those additional ES verts are
1600 * unique (e.g. not reused) we need to make sure there is enough LDS
1601 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1602 */
1603 es_verts -= min_es_verts - 1;
1604
1605 uint32_t es_verts_per_subgroup = es_verts;
1606 uint32_t gs_prims_per_subgroup = gs_prims;
1607 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1608 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1609 out->lds_size = align(esgs_lds_size, 128) / 128;
1610 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1611 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1612 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1613 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1614 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1615 assert(max_prims_per_subgroup <= max_out_prims);
1616 }
1617
1618 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1619 unsigned min_verts_per_prim, bool use_adjacency)
1620 {
1621 unsigned max_reuse = max_esverts - min_verts_per_prim;
1622 if (use_adjacency)
1623 max_reuse /= 2;
1624 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1625 }
1626
1627 static unsigned
1628 radv_get_num_input_vertices(nir_shader **nir)
1629 {
1630 if (nir[MESA_SHADER_GEOMETRY]) {
1631 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1632
1633 return gs->info.gs.vertices_in;
1634 }
1635
1636 if (nir[MESA_SHADER_TESS_CTRL]) {
1637 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1638
1639 if (tes->info.tess.point_mode)
1640 return 1;
1641 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1642 return 2;
1643 return 3;
1644 }
1645
1646 return 3;
1647 }
1648
1649 static void
1650 gfx10_get_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1651 struct radv_pipeline *pipeline,
1652 nir_shader **nir,
1653 struct radv_shader_info *infos,
1654 struct gfx10_ngg_info *ngg)
1655 {
1656 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1657 struct radv_es_output_info *es_info =
1658 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1659 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1660 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1661 unsigned min_verts_per_prim =
1662 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1663 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1664 bool uses_adjacency;
1665 switch(pCreateInfo->pInputAssemblyState->topology) {
1666 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1667 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1668 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1669 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1670 uses_adjacency = true;
1671 break;
1672 default:
1673 uses_adjacency = false;
1674 break;
1675 }
1676
1677 /* All these are in dwords: */
1678 /* We can't allow using the whole LDS, because GS waves compete with
1679 * other shader stages for LDS space.
1680 *
1681 * Streamout can increase the ESGS buffer size later on, so be more
1682 * conservative with streamout and use 4K dwords. This may be suboptimal.
1683 *
1684 * Otherwise, use the limit of 7K dwords. The reason is that we need
1685 * to leave some headroom for the max_esverts increase at the end.
1686 *
1687 * TODO: We should really take the shader's internal LDS use into
1688 * account. The linker will fail if the size is greater than
1689 * 8K dwords.
1690 */
1691 const unsigned max_lds_size = (0 /*gs_info->info.so.num_outputs*/ ? 4 : 7) * 1024 - 128;
1692 const unsigned target_lds_size = max_lds_size;
1693 unsigned esvert_lds_size = 0;
1694 unsigned gsprim_lds_size = 0;
1695
1696 /* All these are per subgroup: */
1697 bool max_vert_out_per_gs_instance = false;
1698 unsigned max_esverts_base = 256;
1699 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1700
1701 /* Hardware has the following non-natural restrictions on the value
1702 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1703 * the draw:
1704 * - at most 252 for any line input primitive type
1705 * - at most 251 for any quad input primitive type
1706 * - at most 251 for triangle strips with adjacency (this happens to
1707 * be the natural limit for triangle *lists* with adjacency)
1708 */
1709 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1710
1711 if (gs_type == MESA_SHADER_GEOMETRY) {
1712 unsigned max_out_verts_per_gsprim =
1713 gs_info->gs.vertices_out * gs_num_invocations;
1714
1715 if (max_out_verts_per_gsprim <= 256) {
1716 if (max_out_verts_per_gsprim) {
1717 max_gsprims_base = MIN2(max_gsprims_base,
1718 256 / max_out_verts_per_gsprim);
1719 }
1720 } else {
1721 /* Use special multi-cycling mode in which each GS
1722 * instance gets its own subgroup. Does not work with
1723 * tessellation. */
1724 max_vert_out_per_gs_instance = true;
1725 max_gsprims_base = 1;
1726 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1727 }
1728
1729 esvert_lds_size = es_info->esgs_itemsize / 4;
1730 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1731 } else {
1732 /* TODO: This needs to be adjusted once LDS use for compaction
1733 * after culling is implemented. */
1734 /*
1735 if (es_info->info.so.num_outputs)
1736 esvert_lds_size = 4 * es_info->info.so.num_outputs + 1;
1737 */
1738
1739 /* LDS size for passing data from GS to ES.
1740 * GS stores Primitive IDs (one DWORD) into LDS at the address
1741 * corresponding to the ES thread of the provoking vertex. All
1742 * ES threads load and export PrimitiveID for their thread.
1743 */
1744 if (!nir[MESA_SHADER_TESS_CTRL] &&
1745 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1746 esvert_lds_size = MAX2(esvert_lds_size, 1);
1747 }
1748
1749 unsigned max_gsprims = max_gsprims_base;
1750 unsigned max_esverts = max_esverts_base;
1751
1752 if (esvert_lds_size)
1753 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1754 if (gsprim_lds_size)
1755 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1756
1757 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1758 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1759 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1760
1761 if (esvert_lds_size || gsprim_lds_size) {
1762 /* Now that we have a rough proportionality between esverts
1763 * and gsprims based on the primitive type, scale both of them
1764 * down simultaneously based on required LDS space.
1765 *
1766 * We could be smarter about this if we knew how much vertex
1767 * reuse to expect.
1768 */
1769 unsigned lds_total = max_esverts * esvert_lds_size +
1770 max_gsprims * gsprim_lds_size;
1771 if (lds_total > target_lds_size) {
1772 max_esverts = max_esverts * target_lds_size / lds_total;
1773 max_gsprims = max_gsprims * target_lds_size / lds_total;
1774
1775 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1776 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1777 min_verts_per_prim, uses_adjacency);
1778 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1779 }
1780 }
1781
1782 /* Round up towards full wave sizes for better ALU utilization. */
1783 if (!max_vert_out_per_gs_instance) {
1784 const unsigned wavesize = pipeline->device->physical_device->ge_wave_size;
1785 unsigned orig_max_esverts;
1786 unsigned orig_max_gsprims;
1787 do {
1788 orig_max_esverts = max_esverts;
1789 orig_max_gsprims = max_gsprims;
1790
1791 max_esverts = align(max_esverts, wavesize);
1792 max_esverts = MIN2(max_esverts, max_esverts_base);
1793 if (esvert_lds_size)
1794 max_esverts = MIN2(max_esverts,
1795 (max_lds_size - max_gsprims * gsprim_lds_size) /
1796 esvert_lds_size);
1797 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1798
1799 max_gsprims = align(max_gsprims, wavesize);
1800 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1801 if (gsprim_lds_size)
1802 max_gsprims = MIN2(max_gsprims,
1803 (max_lds_size - max_esverts * esvert_lds_size) /
1804 gsprim_lds_size);
1805 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1806 min_verts_per_prim, uses_adjacency);
1807 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1808 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1809 }
1810
1811 /* Hardware restriction: minimum value of max_esverts */
1812 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1813
1814 unsigned max_out_vertices =
1815 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1816 gs_type == MESA_SHADER_GEOMETRY ?
1817 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1818 max_esverts;
1819 assert(max_out_vertices <= 256);
1820
1821 unsigned prim_amp_factor = 1;
1822 if (gs_type == MESA_SHADER_GEOMETRY) {
1823 /* Number of output primitives per GS input primitive after
1824 * GS instancing. */
1825 prim_amp_factor = gs_info->gs.vertices_out;
1826 }
1827
1828 /* The GE only checks against the maximum number of ES verts after
1829 * allocating a full GS primitive. So we need to ensure that whenever
1830 * this check passes, there is enough space for a full primitive without
1831 * vertex reuse.
1832 */
1833 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1834 ngg->max_gsprims = max_gsprims;
1835 ngg->max_out_verts = max_out_vertices;
1836 ngg->prim_amp_factor = prim_amp_factor;
1837 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1838 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1839 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1840
1841 if (gs_type == MESA_SHADER_GEOMETRY) {
1842 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1843 } else {
1844 ngg->vgt_esgs_ring_itemsize = 1;
1845 }
1846
1847 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1848
1849 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1850 }
1851
1852 static void
1853 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1854 const struct gfx9_gs_info *gs)
1855 {
1856 struct radv_device *device = pipeline->device;
1857 unsigned num_se = device->physical_device->rad_info.max_se;
1858 unsigned wave_size = 64;
1859 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1860 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1861 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1862 */
1863 unsigned gs_vertex_reuse =
1864 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1865 unsigned alignment = 256 * num_se;
1866 /* The maximum size is 63.999 MB per SE. */
1867 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1868 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1869
1870 /* Calculate the minimum size. */
1871 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1872 wave_size, alignment);
1873 /* These are recommended sizes, not minimum sizes. */
1874 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1875 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1876 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1877 gs_info->gs.max_gsvs_emit_size;
1878
1879 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1880 esgs_ring_size = align(esgs_ring_size, alignment);
1881 gsvs_ring_size = align(gsvs_ring_size, alignment);
1882
1883 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1884 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1885
1886 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1887 }
1888
1889 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1890 unsigned *lds_size)
1891 {
1892 /* If tessellation is all offchip and on-chip GS isn't used, this
1893 * workaround is not needed.
1894 */
1895 return;
1896
1897 /* SPI barrier management bug:
1898 * Make sure we have at least 4k of LDS in use to avoid the bug.
1899 * It applies to workgroup sizes of more than one wavefront.
1900 */
1901 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1902 device->physical_device->rad_info.family == CHIP_KABINI)
1903 *lds_size = MAX2(*lds_size, 8);
1904 }
1905
1906 struct radv_shader_variant *
1907 radv_get_shader(struct radv_pipeline *pipeline,
1908 gl_shader_stage stage)
1909 {
1910 if (stage == MESA_SHADER_VERTEX) {
1911 if (pipeline->shaders[MESA_SHADER_VERTEX])
1912 return pipeline->shaders[MESA_SHADER_VERTEX];
1913 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1914 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1915 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1916 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1917 } else if (stage == MESA_SHADER_TESS_EVAL) {
1918 if (!radv_pipeline_has_tess(pipeline))
1919 return NULL;
1920 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1921 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1922 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1923 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1924 }
1925 return pipeline->shaders[stage];
1926 }
1927
1928 static struct radv_tessellation_state
1929 calculate_tess_state(struct radv_pipeline *pipeline,
1930 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1931 {
1932 unsigned num_tcs_input_cp;
1933 unsigned num_tcs_output_cp;
1934 unsigned lds_size;
1935 unsigned num_patches;
1936 struct radv_tessellation_state tess = {0};
1937
1938 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1939 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1940 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1941
1942 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1943
1944 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1945 assert(lds_size <= 65536);
1946 lds_size = align(lds_size, 512) / 512;
1947 } else {
1948 assert(lds_size <= 32768);
1949 lds_size = align(lds_size, 256) / 256;
1950 }
1951 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1952
1953 tess.lds_size = lds_size;
1954
1955 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1956 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1957 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1958 tess.num_patches = num_patches;
1959
1960 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1961 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1962
1963 switch (tes->info.tes.primitive_mode) {
1964 case GL_TRIANGLES:
1965 type = V_028B6C_TESS_TRIANGLE;
1966 break;
1967 case GL_QUADS:
1968 type = V_028B6C_TESS_QUAD;
1969 break;
1970 case GL_ISOLINES:
1971 type = V_028B6C_TESS_ISOLINE;
1972 break;
1973 }
1974
1975 switch (tes->info.tes.spacing) {
1976 case TESS_SPACING_EQUAL:
1977 partitioning = V_028B6C_PART_INTEGER;
1978 break;
1979 case TESS_SPACING_FRACTIONAL_ODD:
1980 partitioning = V_028B6C_PART_FRAC_ODD;
1981 break;
1982 case TESS_SPACING_FRACTIONAL_EVEN:
1983 partitioning = V_028B6C_PART_FRAC_EVEN;
1984 break;
1985 default:
1986 break;
1987 }
1988
1989 bool ccw = tes->info.tes.ccw;
1990 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
1991 vk_find_struct_const(pCreateInfo->pTessellationState,
1992 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
1993
1994 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
1995 ccw = !ccw;
1996
1997 if (tes->info.tes.point_mode)
1998 topology = V_028B6C_OUTPUT_POINT;
1999 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2000 topology = V_028B6C_OUTPUT_LINE;
2001 else if (ccw)
2002 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2003 else
2004 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2005
2006 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2007 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2008 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2009 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2010 else
2011 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2012 } else
2013 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2014
2015 tess.tf_param = S_028B6C_TYPE(type) |
2016 S_028B6C_PARTITIONING(partitioning) |
2017 S_028B6C_TOPOLOGY(topology) |
2018 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2019
2020 return tess;
2021 }
2022
2023 static const struct radv_prim_vertex_count prim_size_table[] = {
2024 [V_008958_DI_PT_NONE] = {0, 0},
2025 [V_008958_DI_PT_POINTLIST] = {1, 1},
2026 [V_008958_DI_PT_LINELIST] = {2, 2},
2027 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2028 [V_008958_DI_PT_TRILIST] = {3, 3},
2029 [V_008958_DI_PT_TRIFAN] = {3, 1},
2030 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2031 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2032 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2033 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2034 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2035 [V_008958_DI_PT_RECTLIST] = {3, 3},
2036 [V_008958_DI_PT_LINELOOP] = {2, 1},
2037 [V_008958_DI_PT_POLYGON] = {3, 1},
2038 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2039 };
2040
2041 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2042 {
2043 if (radv_pipeline_has_gs(pipeline))
2044 if (radv_pipeline_has_ngg(pipeline))
2045 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2046 else
2047 return &pipeline->gs_copy_shader->info.vs.outinfo;
2048 else if (radv_pipeline_has_tess(pipeline))
2049 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2050 else
2051 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2052 }
2053
2054 static void
2055 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2056 {
2057 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2058 int shader_count = 0;
2059
2060 if(shaders[MESA_SHADER_FRAGMENT]) {
2061 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2062 }
2063 if(shaders[MESA_SHADER_GEOMETRY]) {
2064 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2065 }
2066 if(shaders[MESA_SHADER_TESS_EVAL]) {
2067 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2068 }
2069 if(shaders[MESA_SHADER_TESS_CTRL]) {
2070 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2071 }
2072 if(shaders[MESA_SHADER_VERTEX]) {
2073 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2074 }
2075
2076 if (shader_count > 1) {
2077 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2078 unsigned last = ordered_shaders[0]->info.stage;
2079
2080 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2081 ordered_shaders[1]->info.has_transform_feedback_varyings)
2082 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2083
2084 for (int i = 0; i < shader_count; ++i) {
2085 nir_variable_mode mask = 0;
2086
2087 if (ordered_shaders[i]->info.stage != first)
2088 mask = mask | nir_var_shader_in;
2089
2090 if (ordered_shaders[i]->info.stage != last)
2091 mask = mask | nir_var_shader_out;
2092
2093 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2094 radv_optimize_nir(ordered_shaders[i], false, false);
2095 }
2096 }
2097
2098 for (int i = 1; i < shader_count; ++i) {
2099 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2100 ordered_shaders[i - 1]);
2101
2102 if (nir_link_opt_varyings(ordered_shaders[i],
2103 ordered_shaders[i - 1]))
2104 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2105
2106 nir_remove_dead_variables(ordered_shaders[i],
2107 nir_var_shader_out);
2108 nir_remove_dead_variables(ordered_shaders[i - 1],
2109 nir_var_shader_in);
2110
2111 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2112 ordered_shaders[i - 1]);
2113
2114 nir_compact_varyings(ordered_shaders[i],
2115 ordered_shaders[i - 1], true);
2116
2117 if (progress) {
2118 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2119 ac_lower_indirect_derefs(ordered_shaders[i],
2120 pipeline->device->physical_device->rad_info.chip_class);
2121 }
2122 radv_optimize_nir(ordered_shaders[i], false, false);
2123
2124 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2125 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2126 pipeline->device->physical_device->rad_info.chip_class);
2127 }
2128 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2129 }
2130 }
2131 }
2132
2133 static uint32_t
2134 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2135 uint32_t attrib_binding)
2136 {
2137 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2138 const VkVertexInputBindingDescription *input_binding =
2139 &input_state->pVertexBindingDescriptions[i];
2140
2141 if (input_binding->binding == attrib_binding)
2142 return input_binding->stride;
2143 }
2144
2145 return 0;
2146 }
2147
2148 static struct radv_pipeline_key
2149 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2150 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2151 const struct radv_blend_state *blend,
2152 bool has_view_index)
2153 {
2154 const VkPipelineVertexInputStateCreateInfo *input_state =
2155 pCreateInfo->pVertexInputState;
2156 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2157 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2158
2159 struct radv_pipeline_key key;
2160 memset(&key, 0, sizeof(key));
2161
2162 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2163 key.optimisations_disabled = 1;
2164
2165 key.has_multiview_view_index = has_view_index;
2166
2167 uint32_t binding_input_rate = 0;
2168 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2169 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2170 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2171 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2172 binding_input_rate |= 1u << binding;
2173 instance_rate_divisors[binding] = 1;
2174 }
2175 }
2176 if (divisor_state) {
2177 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2178 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2179 divisor_state->pVertexBindingDivisors[i].divisor;
2180 }
2181 }
2182
2183 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2184 const VkVertexInputAttributeDescription *desc =
2185 &input_state->pVertexAttributeDescriptions[i];
2186 const struct vk_format_description *format_desc;
2187 unsigned location = desc->location;
2188 unsigned binding = desc->binding;
2189 unsigned num_format, data_format;
2190 int first_non_void;
2191
2192 if (binding_input_rate & (1u << binding)) {
2193 key.instance_rate_inputs |= 1u << location;
2194 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2195 }
2196
2197 format_desc = vk_format_description(desc->format);
2198 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2199
2200 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2201 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2202
2203 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2204 key.vertex_attribute_bindings[location] = desc->binding;
2205 key.vertex_attribute_offsets[location] = desc->offset;
2206 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2207
2208 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2209 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2210 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2211 uint64_t adjust;
2212 switch(format) {
2213 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2214 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2215 adjust = RADV_ALPHA_ADJUST_SNORM;
2216 break;
2217 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2218 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2219 adjust = RADV_ALPHA_ADJUST_SSCALED;
2220 break;
2221 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2222 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2223 adjust = RADV_ALPHA_ADJUST_SINT;
2224 break;
2225 default:
2226 adjust = 0;
2227 break;
2228 }
2229 key.vertex_alpha_adjust |= adjust << (2 * location);
2230 }
2231
2232 switch (desc->format) {
2233 case VK_FORMAT_B8G8R8A8_UNORM:
2234 case VK_FORMAT_B8G8R8A8_SNORM:
2235 case VK_FORMAT_B8G8R8A8_USCALED:
2236 case VK_FORMAT_B8G8R8A8_SSCALED:
2237 case VK_FORMAT_B8G8R8A8_UINT:
2238 case VK_FORMAT_B8G8R8A8_SINT:
2239 case VK_FORMAT_B8G8R8A8_SRGB:
2240 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2241 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2242 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2243 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2244 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2245 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2246 key.vertex_post_shuffle |= 1 << location;
2247 break;
2248 default:
2249 break;
2250 }
2251 }
2252
2253 if (pCreateInfo->pTessellationState)
2254 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
2255
2256
2257 if (pCreateInfo->pMultisampleState &&
2258 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
2259 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
2260 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
2261 key.num_samples = num_samples;
2262 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2263 }
2264
2265 key.col_format = blend->spi_shader_col_format;
2266 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2267 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2268
2269 return key;
2270 }
2271
2272 static bool
2273 radv_nir_stage_uses_xfb(const nir_shader *nir)
2274 {
2275 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2276 bool uses_xfb = !!xfb;
2277
2278 ralloc_free(xfb);
2279 return uses_xfb;
2280 }
2281
2282 static void
2283 radv_fill_shader_keys(struct radv_device *device,
2284 struct radv_shader_variant_key *keys,
2285 const struct radv_pipeline_key *key,
2286 nir_shader **nir)
2287 {
2288 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2289 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2290 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2291 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2292 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2293 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2294 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2295 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2296 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2297 }
2298
2299 if (nir[MESA_SHADER_TESS_CTRL]) {
2300 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2301 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2302 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2303 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2304
2305 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2306 }
2307
2308 if (nir[MESA_SHADER_GEOMETRY]) {
2309 if (nir[MESA_SHADER_TESS_CTRL])
2310 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2311 else
2312 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2313 }
2314
2315 if (device->physical_device->rad_info.chip_class >= GFX10 &&
2316 device->physical_device->rad_info.family != CHIP_NAVI14 &&
2317 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG)) {
2318 if (nir[MESA_SHADER_TESS_CTRL]) {
2319 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2320 } else {
2321 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2322 }
2323
2324 if (nir[MESA_SHADER_TESS_CTRL] &&
2325 nir[MESA_SHADER_GEOMETRY] &&
2326 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2327 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2328 /* Fallback to the legacy path if tessellation is
2329 * enabled with extreme geometry because
2330 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2331 * might hang.
2332 */
2333 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2334 }
2335
2336 /*
2337 * Disable NGG with geometry shaders. There are a bunch of
2338 * issues still:
2339 * * GS primitives in pipeline statistic queries do not get
2340 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2341 * * General issues with the last primitive missing/corrupt:
2342 * https://bugs.freedesktop.org/show_bug.cgi?id=111248
2343 *
2344 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2345 */
2346 if (nir[MESA_SHADER_GEOMETRY]) {
2347 if (nir[MESA_SHADER_TESS_CTRL])
2348 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2349 else
2350 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2351 }
2352
2353 if (!device->physical_device->use_ngg_streamout) {
2354 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2355
2356 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2357 if (nir[i])
2358 last_xfb_stage = i;
2359 }
2360
2361 if (nir[last_xfb_stage] &&
2362 radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
2363 if (nir[MESA_SHADER_TESS_CTRL])
2364 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2365 else
2366 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2367 }
2368 }
2369 }
2370
2371 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2372 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2373
2374 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2375 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2376 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2377 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2378 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2379 }
2380
2381 static void
2382 radv_fill_shader_info(struct radv_pipeline *pipeline,
2383 struct radv_shader_variant_key *keys,
2384 struct radv_shader_info *infos,
2385 nir_shader **nir)
2386 {
2387 unsigned active_stages = 0;
2388 unsigned filled_stages = 0;
2389
2390 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2391 if (nir[i])
2392 active_stages |= (1 << i);
2393 }
2394
2395 if (nir[MESA_SHADER_FRAGMENT]) {
2396 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2397 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2398 pipeline->layout,
2399 &keys[MESA_SHADER_FRAGMENT],
2400 &infos[MESA_SHADER_FRAGMENT]);
2401
2402 /* TODO: These are no longer used as keys we should refactor this */
2403 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2404 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2405 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2406 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2407 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2408 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2409 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2410 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2411 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2412 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2413 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2414 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2415
2416 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2417 }
2418
2419 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2420 nir[MESA_SHADER_TESS_CTRL]) {
2421 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2422 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2423 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2424
2425 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2426
2427 for (int i = 0; i < 2; i++) {
2428 radv_nir_shader_info_pass(combined_nir[i],
2429 pipeline->layout, &key,
2430 &infos[MESA_SHADER_TESS_CTRL]);
2431 }
2432
2433 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2434 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2435 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2436 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2437
2438 filled_stages |= (1 << MESA_SHADER_VERTEX);
2439 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2440 }
2441
2442 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2443 nir[MESA_SHADER_GEOMETRY]) {
2444 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2445 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2446
2447 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2448
2449 for (int i = 0; i < 2; i++) {
2450 radv_nir_shader_info_pass(combined_nir[i],
2451 pipeline->layout,
2452 &keys[pre_stage],
2453 &infos[MESA_SHADER_GEOMETRY]);
2454 }
2455
2456 filled_stages |= (1 << pre_stage);
2457 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2458 }
2459
2460 active_stages ^= filled_stages;
2461 while (active_stages) {
2462 int i = u_bit_scan(&active_stages);
2463
2464 if (i == MESA_SHADER_TESS_CTRL) {
2465 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2466 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2467 }
2468
2469 if (i == MESA_SHADER_TESS_EVAL) {
2470 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2471 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2472 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2473 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2474 }
2475
2476 radv_nir_shader_info_init(&infos[i]);
2477 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2478 &keys[i], &infos[i]);
2479 }
2480 }
2481
2482 static void
2483 merge_tess_info(struct shader_info *tes_info,
2484 const struct shader_info *tcs_info)
2485 {
2486 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2487 *
2488 * "PointMode. Controls generation of points rather than triangles
2489 * or lines. This functionality defaults to disabled, and is
2490 * enabled if either shader stage includes the execution mode.
2491 *
2492 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2493 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2494 * and OutputVertices, it says:
2495 *
2496 * "One mode must be set in at least one of the tessellation
2497 * shader stages."
2498 *
2499 * So, the fields can be set in either the TCS or TES, but they must
2500 * agree if set in both. Our backend looks at TES, so bitwise-or in
2501 * the values from the TCS.
2502 */
2503 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2504 tes_info->tess.tcs_vertices_out == 0 ||
2505 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2506 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2507
2508 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2509 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2510 tcs_info->tess.spacing == tes_info->tess.spacing);
2511 tes_info->tess.spacing |= tcs_info->tess.spacing;
2512
2513 assert(tcs_info->tess.primitive_mode == 0 ||
2514 tes_info->tess.primitive_mode == 0 ||
2515 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2516 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2517 tes_info->tess.ccw |= tcs_info->tess.ccw;
2518 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2519 }
2520
2521 static
2522 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2523 {
2524 if (!ext)
2525 return;
2526
2527 if (ext->pPipelineCreationFeedback) {
2528 ext->pPipelineCreationFeedback->flags = 0;
2529 ext->pPipelineCreationFeedback->duration = 0;
2530 }
2531
2532 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2533 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2534 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2535 }
2536 }
2537
2538 static
2539 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2540 {
2541 if (!feedback)
2542 return;
2543
2544 feedback->duration -= radv_get_current_time();
2545 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2546 }
2547
2548 static
2549 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2550 {
2551 if (!feedback)
2552 return;
2553
2554 feedback->duration += radv_get_current_time();
2555 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2556 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2557 }
2558
2559 static
2560 void radv_create_shaders(struct radv_pipeline *pipeline,
2561 struct radv_device *device,
2562 struct radv_pipeline_cache *cache,
2563 const struct radv_pipeline_key *key,
2564 const VkPipelineShaderStageCreateInfo **pStages,
2565 const VkPipelineCreateFlags flags,
2566 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2567 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2568 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2569 {
2570 struct radv_shader_module fs_m = {0};
2571 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2572 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2573 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2574 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2575 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2576 unsigned char hash[20], gs_copy_hash[20];
2577 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2578
2579 radv_start_feedback(pipeline_feedback);
2580
2581 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2582 if (pStages[i]) {
2583 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2584 if (modules[i]->nir)
2585 _mesa_sha1_compute(modules[i]->nir->info.name,
2586 strlen(modules[i]->nir->info.name),
2587 modules[i]->sha1);
2588
2589 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2590 }
2591 }
2592
2593 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2594 memcpy(gs_copy_hash, hash, 20);
2595 gs_copy_hash[0] ^= 1;
2596
2597 bool found_in_application_cache = true;
2598 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
2599 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2600 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2601 &found_in_application_cache);
2602 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2603 }
2604
2605 if (!keep_executable_info &&
2606 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2607 &found_in_application_cache) &&
2608 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2609 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2610 return;
2611 }
2612
2613 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2614 nir_builder fs_b;
2615 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2616 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2617 fs_m.nir = fs_b.shader;
2618 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2619 }
2620
2621 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2622 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2623
2624 if (!modules[i])
2625 continue;
2626
2627 radv_start_feedback(stage_feedbacks[i]);
2628
2629 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2630 stage ? stage->pName : "main", i,
2631 stage ? stage->pSpecializationInfo : NULL,
2632 flags, pipeline->layout);
2633
2634 /* We don't want to alter meta shaders IR directly so clone it
2635 * first.
2636 */
2637 if (nir[i]->info.name) {
2638 nir[i] = nir_shader_clone(NULL, nir[i]);
2639 }
2640
2641 radv_stop_feedback(stage_feedbacks[i], false);
2642 }
2643
2644 if (nir[MESA_SHADER_TESS_CTRL]) {
2645 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2646 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2647 }
2648
2649 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2650 radv_link_shaders(pipeline, nir);
2651
2652 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2653 if (nir[i]) {
2654 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2655 nir_lower_non_uniform_ubo_access |
2656 nir_lower_non_uniform_ssbo_access |
2657 nir_lower_non_uniform_texture_access |
2658 nir_lower_non_uniform_image_access);
2659 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2660 }
2661
2662 if (radv_can_dump_shader(device, modules[i], false))
2663 nir_print_shader(nir[i], stderr);
2664 }
2665
2666 if (nir[MESA_SHADER_FRAGMENT])
2667 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2668
2669 radv_fill_shader_keys(device, keys, key, nir);
2670
2671 radv_fill_shader_info(pipeline, keys, infos, nir);
2672
2673 if ((nir[MESA_SHADER_VERTEX] &&
2674 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2675 (nir[MESA_SHADER_TESS_EVAL] &&
2676 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2677 struct gfx10_ngg_info *ngg_info;
2678
2679 if (nir[MESA_SHADER_GEOMETRY])
2680 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2681 else if (nir[MESA_SHADER_TESS_CTRL])
2682 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2683 else
2684 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2685
2686 gfx10_get_ngg_info(pCreateInfo, pipeline, nir, infos, ngg_info);
2687 } else if (nir[MESA_SHADER_GEOMETRY]) {
2688 struct gfx9_gs_info *gs_info =
2689 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2690
2691 gfx9_get_gs_info(pCreateInfo, pipeline, nir, infos, gs_info);
2692 }
2693
2694 if (nir[MESA_SHADER_FRAGMENT]) {
2695 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2696 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2697
2698 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2699 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2700 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2701 infos + MESA_SHADER_FRAGMENT,
2702 keep_executable_info, &binaries[MESA_SHADER_FRAGMENT]);
2703
2704 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2705 }
2706
2707 /* TODO: These are no longer used as keys we should refactor this */
2708 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2709 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2710 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2711 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2712 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2713 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2714 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2715 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2716 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2717 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2718 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2719 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2720 }
2721
2722 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2723 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2724 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2725 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2726 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2727
2728 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2729
2730 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2731 pipeline->layout,
2732 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2733 &binaries[MESA_SHADER_TESS_CTRL]);
2734
2735 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2736 }
2737 modules[MESA_SHADER_VERTEX] = NULL;
2738 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2739 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2740 }
2741
2742 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2743 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2744 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2745 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2746
2747 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2748
2749 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2750 pipeline->layout,
2751 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2752 &binaries[MESA_SHADER_GEOMETRY]);
2753
2754 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2755 }
2756 modules[pre_stage] = NULL;
2757 }
2758
2759 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2760 if(modules[i] && !pipeline->shaders[i]) {
2761 if (i == MESA_SHADER_TESS_CTRL) {
2762 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2763 }
2764 if (i == MESA_SHADER_TESS_EVAL) {
2765 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2766 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2767 }
2768
2769 radv_start_feedback(stage_feedbacks[i]);
2770
2771 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2772 pipeline->layout,
2773 keys + i, infos + i,keep_executable_info,
2774 &binaries[i]);
2775
2776 radv_stop_feedback(stage_feedbacks[i], false);
2777 }
2778 }
2779
2780 if(modules[MESA_SHADER_GEOMETRY]) {
2781 struct radv_shader_binary *gs_copy_binary = NULL;
2782 if (!pipeline->gs_copy_shader &&
2783 !radv_pipeline_has_ngg(pipeline)) {
2784 struct radv_shader_info info = {};
2785 struct radv_shader_variant_key key = {};
2786
2787 key.has_multiview_view_index =
2788 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2789
2790 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2791 pipeline->layout, &key,
2792 &info);
2793
2794 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2795 device, nir[MESA_SHADER_GEOMETRY], &info,
2796 &gs_copy_binary, keep_executable_info,
2797 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2798 }
2799
2800 if (!keep_executable_info && pipeline->gs_copy_shader) {
2801 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2802 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2803
2804 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2805 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2806
2807 radv_pipeline_cache_insert_shaders(device, cache,
2808 gs_copy_hash,
2809 variants,
2810 binaries);
2811 }
2812 free(gs_copy_binary);
2813 }
2814
2815 if (!keep_executable_info) {
2816 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2817 binaries);
2818 }
2819
2820 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2821 free(binaries[i]);
2822 if (nir[i]) {
2823 ralloc_free(nir[i]);
2824
2825 if (radv_can_dump_shader_stats(device, modules[i]))
2826 radv_shader_dump_stats(device,
2827 pipeline->shaders[i],
2828 i, stderr);
2829 }
2830 }
2831
2832 if (fs_m.nir)
2833 ralloc_free(fs_m.nir);
2834
2835 radv_stop_feedback(pipeline_feedback, false);
2836 }
2837
2838 static uint32_t
2839 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2840 gl_shader_stage stage, enum chip_class chip_class)
2841 {
2842 bool has_gs = radv_pipeline_has_gs(pipeline);
2843 bool has_tess = radv_pipeline_has_tess(pipeline);
2844 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2845
2846 switch (stage) {
2847 case MESA_SHADER_FRAGMENT:
2848 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2849 case MESA_SHADER_VERTEX:
2850 if (has_tess) {
2851 if (chip_class >= GFX10) {
2852 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2853 } else if (chip_class == GFX9) {
2854 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2855 } else {
2856 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2857 }
2858
2859 }
2860
2861 if (has_gs) {
2862 if (chip_class >= GFX10) {
2863 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2864 } else {
2865 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2866 }
2867 }
2868
2869 if (has_ngg)
2870 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2871
2872 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2873 case MESA_SHADER_GEOMETRY:
2874 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2875 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2876 case MESA_SHADER_COMPUTE:
2877 return R_00B900_COMPUTE_USER_DATA_0;
2878 case MESA_SHADER_TESS_CTRL:
2879 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2880 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2881 case MESA_SHADER_TESS_EVAL:
2882 if (has_gs) {
2883 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2884 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2885 } else if (has_ngg) {
2886 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2887 } else {
2888 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2889 }
2890 default:
2891 unreachable("unknown shader");
2892 }
2893 }
2894
2895 struct radv_bin_size_entry {
2896 unsigned bpp;
2897 VkExtent2D extent;
2898 };
2899
2900 static VkExtent2D
2901 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2902 {
2903 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2904 {
2905 /* One RB / SE */
2906 {
2907 /* One shader engine */
2908 { 0, {128, 128}},
2909 { 1, { 64, 128}},
2910 { 2, { 32, 128}},
2911 { 3, { 16, 128}},
2912 { 17, { 0, 0}},
2913 { UINT_MAX, { 0, 0}},
2914 },
2915 {
2916 /* Two shader engines */
2917 { 0, {128, 128}},
2918 { 2, { 64, 128}},
2919 { 3, { 32, 128}},
2920 { 5, { 16, 128}},
2921 { 17, { 0, 0}},
2922 { UINT_MAX, { 0, 0}},
2923 },
2924 {
2925 /* Four shader engines */
2926 { 0, {128, 128}},
2927 { 3, { 64, 128}},
2928 { 5, { 16, 128}},
2929 { 17, { 0, 0}},
2930 { UINT_MAX, { 0, 0}},
2931 },
2932 },
2933 {
2934 /* Two RB / SE */
2935 {
2936 /* One shader engine */
2937 { 0, {128, 128}},
2938 { 2, { 64, 128}},
2939 { 3, { 32, 128}},
2940 { 5, { 16, 128}},
2941 { 33, { 0, 0}},
2942 { UINT_MAX, { 0, 0}},
2943 },
2944 {
2945 /* Two shader engines */
2946 { 0, {128, 128}},
2947 { 3, { 64, 128}},
2948 { 5, { 32, 128}},
2949 { 9, { 16, 128}},
2950 { 33, { 0, 0}},
2951 { UINT_MAX, { 0, 0}},
2952 },
2953 {
2954 /* Four shader engines */
2955 { 0, {256, 256}},
2956 { 2, {128, 256}},
2957 { 3, {128, 128}},
2958 { 5, { 64, 128}},
2959 { 9, { 16, 128}},
2960 { 33, { 0, 0}},
2961 { UINT_MAX, { 0, 0}},
2962 },
2963 },
2964 {
2965 /* Four RB / SE */
2966 {
2967 /* One shader engine */
2968 { 0, {128, 256}},
2969 { 2, {128, 128}},
2970 { 3, { 64, 128}},
2971 { 5, { 32, 128}},
2972 { 9, { 16, 128}},
2973 { 33, { 0, 0}},
2974 { UINT_MAX, { 0, 0}},
2975 },
2976 {
2977 /* Two shader engines */
2978 { 0, {256, 256}},
2979 { 2, {128, 256}},
2980 { 3, {128, 128}},
2981 { 5, { 64, 128}},
2982 { 9, { 32, 128}},
2983 { 17, { 16, 128}},
2984 { 33, { 0, 0}},
2985 { UINT_MAX, { 0, 0}},
2986 },
2987 {
2988 /* Four shader engines */
2989 { 0, {256, 512}},
2990 { 2, {256, 256}},
2991 { 3, {128, 256}},
2992 { 5, {128, 128}},
2993 { 9, { 64, 128}},
2994 { 17, { 16, 128}},
2995 { 33, { 0, 0}},
2996 { UINT_MAX, { 0, 0}},
2997 },
2998 },
2999 };
3000 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3001 {
3002 // One RB / SE
3003 {
3004 // One shader engine
3005 { 0, {128, 256}},
3006 { 2, {128, 128}},
3007 { 4, { 64, 128}},
3008 { 7, { 32, 128}},
3009 { 13, { 16, 128}},
3010 { 49, { 0, 0}},
3011 { UINT_MAX, { 0, 0}},
3012 },
3013 {
3014 // Two shader engines
3015 { 0, {256, 256}},
3016 { 2, {128, 256}},
3017 { 4, {128, 128}},
3018 { 7, { 64, 128}},
3019 { 13, { 32, 128}},
3020 { 25, { 16, 128}},
3021 { 49, { 0, 0}},
3022 { UINT_MAX, { 0, 0}},
3023 },
3024 {
3025 // Four shader engines
3026 { 0, {256, 512}},
3027 { 2, {256, 256}},
3028 { 4, {128, 256}},
3029 { 7, {128, 128}},
3030 { 13, { 64, 128}},
3031 { 25, { 16, 128}},
3032 { 49, { 0, 0}},
3033 { UINT_MAX, { 0, 0}},
3034 },
3035 },
3036 {
3037 // Two RB / SE
3038 {
3039 // One shader engine
3040 { 0, {256, 256}},
3041 { 2, {128, 256}},
3042 { 4, {128, 128}},
3043 { 7, { 64, 128}},
3044 { 13, { 32, 128}},
3045 { 25, { 16, 128}},
3046 { 97, { 0, 0}},
3047 { UINT_MAX, { 0, 0}},
3048 },
3049 {
3050 // Two shader engines
3051 { 0, {256, 512}},
3052 { 2, {256, 256}},
3053 { 4, {128, 256}},
3054 { 7, {128, 128}},
3055 { 13, { 64, 128}},
3056 { 25, { 32, 128}},
3057 { 49, { 16, 128}},
3058 { 97, { 0, 0}},
3059 { UINT_MAX, { 0, 0}},
3060 },
3061 {
3062 // Four shader engines
3063 { 0, {512, 512}},
3064 { 2, {256, 512}},
3065 { 4, {256, 256}},
3066 { 7, {128, 256}},
3067 { 13, {128, 128}},
3068 { 25, { 64, 128}},
3069 { 49, { 16, 128}},
3070 { 97, { 0, 0}},
3071 { UINT_MAX, { 0, 0}},
3072 },
3073 },
3074 {
3075 // Four RB / SE
3076 {
3077 // One shader engine
3078 { 0, {256, 512}},
3079 { 2, {256, 256}},
3080 { 4, {128, 256}},
3081 { 7, {128, 128}},
3082 { 13, { 64, 128}},
3083 { 25, { 32, 128}},
3084 { 49, { 16, 128}},
3085 { UINT_MAX, { 0, 0}},
3086 },
3087 {
3088 // Two shader engines
3089 { 0, {512, 512}},
3090 { 2, {256, 512}},
3091 { 4, {256, 256}},
3092 { 7, {128, 256}},
3093 { 13, {128, 128}},
3094 { 25, { 64, 128}},
3095 { 49, { 32, 128}},
3096 { 97, { 16, 128}},
3097 { UINT_MAX, { 0, 0}},
3098 },
3099 {
3100 // Four shader engines
3101 { 0, {512, 512}},
3102 { 4, {256, 512}},
3103 { 7, {256, 256}},
3104 { 13, {128, 256}},
3105 { 25, {128, 128}},
3106 { 49, { 64, 128}},
3107 { 97, { 16, 128}},
3108 { UINT_MAX, { 0, 0}},
3109 },
3110 },
3111 };
3112
3113 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3114 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3115 VkExtent2D extent = {512, 512};
3116
3117 unsigned log_num_rb_per_se =
3118 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3119 pipeline->device->physical_device->rad_info.max_se);
3120 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3121
3122 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3123 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3124 unsigned effective_samples = total_samples;
3125 unsigned color_bytes_per_pixel = 0;
3126
3127 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3128 if (vkblend) {
3129 for (unsigned i = 0; i < subpass->color_count; i++) {
3130 if (!vkblend->pAttachments[i].colorWriteMask)
3131 continue;
3132
3133 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3134 continue;
3135
3136 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3137 color_bytes_per_pixel += vk_format_get_blocksize(format);
3138 }
3139
3140 /* MSAA images typically don't use all samples all the time. */
3141 if (effective_samples >= 2 && ps_iter_samples <= 1)
3142 effective_samples = 2;
3143 color_bytes_per_pixel *= effective_samples;
3144 }
3145
3146 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3147 while(color_entry[1].bpp <= color_bytes_per_pixel)
3148 ++color_entry;
3149
3150 extent = color_entry->extent;
3151
3152 if (subpass->depth_stencil_attachment) {
3153 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3154
3155 /* Coefficients taken from AMDVLK */
3156 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3157 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3158 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3159
3160 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3161 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3162 ++ds_entry;
3163
3164 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3165 extent = ds_entry->extent;
3166 }
3167
3168 return extent;
3169 }
3170
3171 static VkExtent2D
3172 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3173 {
3174 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3175 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3176 VkExtent2D extent = {512, 512};
3177
3178 unsigned sdp_interface_count;
3179
3180 switch(pipeline->device->physical_device->rad_info.family) {
3181 case CHIP_NAVI10:
3182 case CHIP_NAVI12:
3183 sdp_interface_count = 16;
3184 break;
3185 case CHIP_NAVI14:
3186 sdp_interface_count = 8;
3187 break;
3188 default:
3189 unreachable("Unhandled GFX10 chip");
3190 }
3191
3192 const unsigned db_tag_size = 64;
3193 const unsigned db_tag_count = 312;
3194 const unsigned color_tag_size = 1024;
3195 const unsigned color_tag_count = 31;
3196 const unsigned fmask_tag_size = 256;
3197 const unsigned fmask_tag_count = 44;
3198
3199 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3200 const unsigned pipe_count = MAX2(rb_count, sdp_interface_count);
3201
3202 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3203 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3204 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3205
3206 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3207 const unsigned samples_log = util_logbase2_ceil(total_samples);
3208
3209 unsigned color_bytes_per_pixel = 0;
3210 unsigned fmask_bytes_per_pixel = 0;
3211
3212 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3213 if (vkblend) {
3214 for (unsigned i = 0; i < subpass->color_count; i++) {
3215 if (!vkblend->pAttachments[i].colorWriteMask)
3216 continue;
3217
3218 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3219 continue;
3220
3221 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3222 color_bytes_per_pixel += vk_format_get_blocksize(format);
3223
3224 if (total_samples > 1) {
3225 const unsigned fmask_array[] = {0, 1, 1, 4};
3226 fmask_bytes_per_pixel += fmask_array[samples_log];
3227 }
3228 }
3229
3230 color_bytes_per_pixel *= total_samples;
3231 }
3232 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3233
3234 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3235 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3236 extent.height = 1ull << (color_pixel_count_log / 2);
3237
3238 if (fmask_bytes_per_pixel) {
3239 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3240
3241 const VkExtent2D fmask_extent = (VkExtent2D){
3242 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3243 .height = 1ull << (color_pixel_count_log / 2)
3244 };
3245
3246 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3247 extent = fmask_extent;
3248 }
3249
3250 if (subpass->depth_stencil_attachment) {
3251 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3252
3253 /* Coefficients taken from AMDVLK */
3254 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3255 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3256 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3257
3258 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3259
3260 const VkExtent2D db_extent = (VkExtent2D){
3261 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3262 .height = 1ull << (color_pixel_count_log / 2)
3263 };
3264
3265 if (db_extent.width * db_extent.height < extent.width * extent.height)
3266 extent = db_extent;
3267 }
3268
3269 extent.width = MAX2(extent.width, 128);
3270 extent.height = MAX2(extent.width, 64);
3271
3272 return extent;
3273 }
3274
3275 static void
3276 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3277 struct radv_pipeline *pipeline,
3278 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3279 {
3280 uint32_t pa_sc_binner_cntl_0 =
3281 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3282 S_028C44_DISABLE_START_OF_PRIM(1);
3283 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3284
3285 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3286 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3287 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3288 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3289 unsigned min_bytes_per_pixel = 0;
3290
3291 if (vkblend) {
3292 for (unsigned i = 0; i < subpass->color_count; i++) {
3293 if (!vkblend->pAttachments[i].colorWriteMask)
3294 continue;
3295
3296 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3297 continue;
3298
3299 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3300 unsigned bytes = vk_format_get_blocksize(format);
3301 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3302 min_bytes_per_pixel = bytes;
3303 }
3304 }
3305
3306 pa_sc_binner_cntl_0 =
3307 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3308 S_028C44_BIN_SIZE_X(0) |
3309 S_028C44_BIN_SIZE_Y(0) |
3310 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3311 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3312 S_028C44_DISABLE_START_OF_PRIM(1);
3313 }
3314
3315 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3316 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3317 }
3318
3319 static void
3320 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3321 struct radv_pipeline *pipeline,
3322 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3323 {
3324 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3325 return;
3326
3327 VkExtent2D bin_size;
3328 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3329 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3330 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3331 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3332 } else
3333 unreachable("Unhandled generation for binning bin size calculation");
3334
3335 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3336 unsigned context_states_per_bin; /* allowed range: [1, 6] */
3337 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
3338 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
3339
3340 if (pipeline->device->physical_device->rad_info.has_dedicated_vram) {
3341 context_states_per_bin = 1;
3342 persistent_states_per_bin = 1;
3343 fpovs_per_batch = 63;
3344 } else {
3345 /* The context states are affected by the scissor bug. */
3346 context_states_per_bin = pipeline->device->physical_device->rad_info.has_gfx9_scissor_bug ? 1 : 6;
3347 /* 32 causes hangs for RAVEN. */
3348 persistent_states_per_bin = 16;
3349 fpovs_per_batch = 63;
3350 }
3351
3352 const uint32_t pa_sc_binner_cntl_0 =
3353 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3354 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3355 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3356 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3357 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3358 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
3359 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
3360 S_028C44_DISABLE_START_OF_PRIM(1) |
3361 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
3362 S_028C44_OPTIMAL_BIN_SELECTION(1);
3363
3364 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3365
3366 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3367 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3368 } else
3369 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3370 }
3371
3372
3373 static void
3374 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3375 struct radv_pipeline *pipeline,
3376 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3377 const struct radv_graphics_pipeline_create_info *extra)
3378 {
3379 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
3380 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3381 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3382 struct radv_render_pass_attachment *attachment = NULL;
3383 uint32_t db_depth_control = 0, db_stencil_control = 0;
3384 uint32_t db_render_control = 0, db_render_override2 = 0;
3385 uint32_t db_render_override = 0;
3386
3387 if (subpass->depth_stencil_attachment)
3388 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3389
3390 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3391 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3392
3393 if (vkds && has_depth_attachment) {
3394 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3395 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3396 S_028800_ZFUNC(vkds->depthCompareOp) |
3397 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3398
3399 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3400 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3401 }
3402
3403 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3404 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3405 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3406 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3407 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3408 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3409
3410 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3411 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3412 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3413 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3414 }
3415
3416 if (attachment && extra) {
3417 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3418 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3419
3420 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3421 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3422 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3423 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3424 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3425 }
3426
3427 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3428 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3429
3430 if (!pCreateInfo->pRasterizationState->depthClampEnable) {
3431 /* From VK_EXT_depth_range_unrestricted spec:
3432 *
3433 * "The behavior described in Primitive Clipping still applies.
3434 * If depth clamping is disabled the depth values are still
3435 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3436 * depth clamping is enabled the above equation is ignored and
3437 * the depth values are instead clamped to the VkViewport
3438 * minDepth and maxDepth values, which in the case of this
3439 * extension can be outside of the 0.0 to 1.0 range."
3440 */
3441 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3442 }
3443
3444 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3445 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3446
3447 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3448 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3449 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3450 }
3451
3452 static void
3453 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3454 struct radv_pipeline *pipeline,
3455 const struct radv_blend_state *blend)
3456 {
3457 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3458 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3459 8);
3460 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3461 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3462
3463 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3464
3465 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3466 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3467 }
3468
3469 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3470
3471 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3472 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3473
3474 pipeline->graphics.col_format = blend->spi_shader_col_format;
3475 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3476 }
3477
3478 static const VkConservativeRasterizationModeEXT
3479 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3480 {
3481 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3482 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3483
3484 if (!conservative_raster)
3485 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3486 return conservative_raster->conservativeRasterizationMode;
3487 }
3488
3489 static void
3490 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3491 struct radv_pipeline *pipeline,
3492 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3493 {
3494 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3495 const VkConservativeRasterizationModeEXT mode =
3496 radv_get_conservative_raster_mode(vkraster);
3497 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3498 bool depth_clip_disable = vkraster->depthClampEnable;
3499
3500 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3501 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3502 if (depth_clip_state) {
3503 depth_clip_disable = !depth_clip_state->depthClipEnable;
3504 }
3505
3506 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3507 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3508 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3509 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3510 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3511 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3512
3513 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3514 S_0286D4_FLAT_SHADE_ENA(1) |
3515 S_0286D4_PNT_SPRITE_ENA(1) |
3516 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3517 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3518 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3519 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3520 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3521
3522 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3523 S_028BE4_PIX_CENTER(1) | // TODO verify
3524 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3525 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3526
3527 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3528 S_028814_FACE(vkraster->frontFace) |
3529 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3530 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3531 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3532 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3533 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3534 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3535 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3536 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3537
3538 /* Conservative rasterization. */
3539 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3540 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3541
3542 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3543 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3544 S_028804_OVERRASTERIZATION_AMOUNT(4);
3545
3546 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3547 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3548 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3549
3550 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3551 pa_sc_conservative_rast |=
3552 S_028C4C_OVER_RAST_ENABLE(1) |
3553 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3554 S_028C4C_UNDER_RAST_ENABLE(0) |
3555 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3556 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3557 } else {
3558 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3559 pa_sc_conservative_rast |=
3560 S_028C4C_OVER_RAST_ENABLE(0) |
3561 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3562 S_028C4C_UNDER_RAST_ENABLE(1) |
3563 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3564 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3565 }
3566 }
3567
3568 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3569 pa_sc_conservative_rast);
3570 }
3571
3572
3573 static void
3574 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3575 struct radv_pipeline *pipeline)
3576 {
3577 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3578
3579 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3580 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3581 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3582
3583 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3584 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3585
3586 /* The exclusion bits can be set to improve rasterization efficiency
3587 * if no sample lies on the pixel boundary (-8 sample offset). It's
3588 * currently always TRUE because the driver doesn't support 16 samples.
3589 */
3590 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3591 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3592 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3593 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3594 }
3595
3596 static void
3597 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3598 struct radv_pipeline *pipeline)
3599 {
3600 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3601 const struct radv_shader_variant *vs =
3602 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3603 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3604 pipeline->shaders[MESA_SHADER_VERTEX];
3605 unsigned vgt_primitiveid_en = 0;
3606 uint32_t vgt_gs_mode = 0;
3607
3608 if (radv_pipeline_has_ngg(pipeline))
3609 return;
3610
3611 if (radv_pipeline_has_gs(pipeline)) {
3612 const struct radv_shader_variant *gs =
3613 pipeline->shaders[MESA_SHADER_GEOMETRY];
3614
3615 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3616 pipeline->device->physical_device->rad_info.chip_class);
3617 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3618 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3619 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3620 }
3621
3622 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3623 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3624 }
3625
3626 static void
3627 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3628 struct radeon_cmdbuf *cs,
3629 struct radv_pipeline *pipeline,
3630 struct radv_shader_variant *shader)
3631 {
3632 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3633
3634 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3635 radeon_emit(cs, va >> 8);
3636 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3637 radeon_emit(cs, shader->config.rsrc1);
3638 radeon_emit(cs, shader->config.rsrc2);
3639
3640 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3641 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3642 clip_dist_mask = outinfo->clip_dist_mask;
3643 cull_dist_mask = outinfo->cull_dist_mask;
3644 total_mask = clip_dist_mask | cull_dist_mask;
3645 bool misc_vec_ena = outinfo->writes_pointsize ||
3646 outinfo->writes_layer ||
3647 outinfo->writes_viewport_index;
3648 unsigned spi_vs_out_config, nparams;
3649
3650 /* VS is required to export at least one param. */
3651 nparams = MAX2(outinfo->param_exports, 1);
3652 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3653
3654 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3655 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3656 }
3657
3658 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3659
3660 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3661 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3662 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3663 V_02870C_SPI_SHADER_4COMP :
3664 V_02870C_SPI_SHADER_NONE) |
3665 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3666 V_02870C_SPI_SHADER_4COMP :
3667 V_02870C_SPI_SHADER_NONE) |
3668 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3669 V_02870C_SPI_SHADER_4COMP :
3670 V_02870C_SPI_SHADER_NONE));
3671
3672 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3673 S_028818_VTX_W0_FMT(1) |
3674 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3675 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3676 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3677
3678 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3679 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3680 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3681 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3682 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3683 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3684 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3685 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3686 cull_dist_mask << 8 |
3687 clip_dist_mask);
3688
3689 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3690 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3691 outinfo->writes_viewport_index);
3692 }
3693
3694 static void
3695 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3696 struct radv_pipeline *pipeline,
3697 struct radv_shader_variant *shader)
3698 {
3699 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3700
3701 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3702 radeon_emit(cs, va >> 8);
3703 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3704 radeon_emit(cs, shader->config.rsrc1);
3705 radeon_emit(cs, shader->config.rsrc2);
3706 }
3707
3708 static void
3709 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3710 struct radv_pipeline *pipeline,
3711 struct radv_shader_variant *shader,
3712 const struct radv_tessellation_state *tess)
3713 {
3714 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3715 uint32_t rsrc2 = shader->config.rsrc2;
3716
3717 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3718 radeon_emit(cs, va >> 8);
3719 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3720
3721 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3722 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3723 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3724 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3725
3726 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3727 radeon_emit(cs, shader->config.rsrc1);
3728 radeon_emit(cs, rsrc2);
3729 }
3730
3731 static void
3732 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3733 struct radeon_cmdbuf *cs,
3734 struct radv_pipeline *pipeline,
3735 struct radv_shader_variant *shader)
3736 {
3737 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3738 gl_shader_stage es_type =
3739 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3740 struct radv_shader_variant *es =
3741 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3742 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3743
3744 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3745 radeon_emit(cs, va >> 8);
3746 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3747 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3748 radeon_emit(cs, shader->config.rsrc1);
3749 radeon_emit(cs, shader->config.rsrc2);
3750
3751 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3752 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3753 clip_dist_mask = outinfo->clip_dist_mask;
3754 cull_dist_mask = outinfo->cull_dist_mask;
3755 total_mask = clip_dist_mask | cull_dist_mask;
3756 bool misc_vec_ena = outinfo->writes_pointsize ||
3757 outinfo->writes_layer ||
3758 outinfo->writes_viewport_index;
3759 bool es_enable_prim_id = outinfo->export_prim_id ||
3760 (es && es->info.uses_prim_id);
3761 bool break_wave_at_eoi = false;
3762 unsigned ge_cntl;
3763 unsigned nparams;
3764
3765 if (es_type == MESA_SHADER_TESS_EVAL) {
3766 struct radv_shader_variant *gs =
3767 pipeline->shaders[MESA_SHADER_GEOMETRY];
3768
3769 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3770 break_wave_at_eoi = true;
3771 }
3772
3773 nparams = MAX2(outinfo->param_exports, 1);
3774 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3775 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3776 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3777
3778 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3779 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3780 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3781 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3782 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3783 V_02870C_SPI_SHADER_4COMP :
3784 V_02870C_SPI_SHADER_NONE) |
3785 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3786 V_02870C_SPI_SHADER_4COMP :
3787 V_02870C_SPI_SHADER_NONE) |
3788 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3789 V_02870C_SPI_SHADER_4COMP :
3790 V_02870C_SPI_SHADER_NONE));
3791
3792 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3793 S_028818_VTX_W0_FMT(1) |
3794 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3795 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3796 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3797 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3798 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3799 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3800 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3801 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3802 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3803 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3804 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3805 cull_dist_mask << 8 |
3806 clip_dist_mask);
3807
3808 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3809 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3810 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
3811
3812 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3813 ngg_state->vgt_esgs_ring_itemsize);
3814
3815 /* NGG specific registers. */
3816 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3817 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3818
3819 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3820 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3821 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3822 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3823 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3824 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3825 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3826 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3827 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3828 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3829 S_028B90_CNT(gs_num_invocations) |
3830 S_028B90_ENABLE(gs_num_invocations > 1) |
3831 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3832
3833 /* User edge flags are set by the pos exports. If user edge flags are
3834 * not used, we must use hw-generated edge flags and pass them via
3835 * the prim export to prevent drawing lines on internal edges of
3836 * decomposed primitives (such as quads) with polygon mode = lines.
3837 *
3838 * TODO: We should combine hw-generated edge flags with user edge
3839 * flags in the shader.
3840 */
3841 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3842 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3843 !radv_pipeline_has_gs(pipeline)));
3844
3845 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3846 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
3847 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
3848
3849 /* Bug workaround for a possible hang with non-tessellation cases.
3850 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3851 *
3852 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3853 */
3854 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3855 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3856 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3857 !radv_pipeline_has_tess(pipeline) &&
3858 ngg_state->hw_max_esverts != 256) {
3859 ge_cntl &= C_03096C_VERT_GRP_SIZE;
3860
3861 if (ngg_state->hw_max_esverts > 5) {
3862 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
3863 }
3864 }
3865
3866 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
3867 }
3868
3869 static void
3870 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3871 struct radv_pipeline *pipeline,
3872 struct radv_shader_variant *shader,
3873 const struct radv_tessellation_state *tess)
3874 {
3875 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3876
3877 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3878 unsigned hs_rsrc2 = shader->config.rsrc2;
3879
3880 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3881 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3882 } else {
3883 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3884 }
3885
3886 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3887 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3888 radeon_emit(cs, va >> 8);
3889 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3890 } else {
3891 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3892 radeon_emit(cs, va >> 8);
3893 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
3894 }
3895
3896 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3897 radeon_emit(cs, shader->config.rsrc1);
3898 radeon_emit(cs, hs_rsrc2);
3899 } else {
3900 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3901 radeon_emit(cs, va >> 8);
3902 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
3903 radeon_emit(cs, shader->config.rsrc1);
3904 radeon_emit(cs, shader->config.rsrc2);
3905 }
3906 }
3907
3908 static void
3909 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
3910 struct radeon_cmdbuf *cs,
3911 struct radv_pipeline *pipeline,
3912 const struct radv_tessellation_state *tess)
3913 {
3914 struct radv_shader_variant *vs;
3915
3916 /* Skip shaders merged into HS/GS */
3917 vs = pipeline->shaders[MESA_SHADER_VERTEX];
3918 if (!vs)
3919 return;
3920
3921 if (vs->info.vs.as_ls)
3922 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
3923 else if (vs->info.vs.as_es)
3924 radv_pipeline_generate_hw_es(cs, pipeline, vs);
3925 else if (vs->info.is_ngg)
3926 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
3927 else
3928 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
3929 }
3930
3931 static void
3932 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
3933 struct radeon_cmdbuf *cs,
3934 struct radv_pipeline *pipeline,
3935 const struct radv_tessellation_state *tess)
3936 {
3937 if (!radv_pipeline_has_tess(pipeline))
3938 return;
3939
3940 struct radv_shader_variant *tes, *tcs;
3941
3942 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
3943 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
3944
3945 if (tes) {
3946 if (tes->info.is_ngg) {
3947 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
3948 } else if (tes->info.tes.as_es)
3949 radv_pipeline_generate_hw_es(cs, pipeline, tes);
3950 else
3951 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
3952 }
3953
3954 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
3955
3956 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
3957 tess->tf_param);
3958
3959 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
3960 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
3961 tess->ls_hs_config);
3962 else
3963 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
3964 tess->ls_hs_config);
3965
3966 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
3967 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
3968 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3969 S_028A44_ES_VERTS_PER_SUBGRP(250) |
3970 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
3971 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
3972 }
3973 }
3974
3975 static void
3976 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
3977 struct radeon_cmdbuf *cs,
3978 struct radv_pipeline *pipeline,
3979 struct radv_shader_variant *gs)
3980 {
3981 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
3982 unsigned gs_max_out_vertices;
3983 uint8_t *num_components;
3984 uint8_t max_stream;
3985 unsigned offset;
3986 uint64_t va;
3987
3988 gs_max_out_vertices = gs->info.gs.vertices_out;
3989 max_stream = gs->info.gs.max_stream;
3990 num_components = gs->info.gs.num_stream_output_components;
3991
3992 offset = num_components[0] * gs_max_out_vertices;
3993
3994 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
3995 radeon_emit(ctx_cs, offset);
3996 if (max_stream >= 1)
3997 offset += num_components[1] * gs_max_out_vertices;
3998 radeon_emit(ctx_cs, offset);
3999 if (max_stream >= 2)
4000 offset += num_components[2] * gs_max_out_vertices;
4001 radeon_emit(ctx_cs, offset);
4002 if (max_stream >= 3)
4003 offset += num_components[3] * gs_max_out_vertices;
4004 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4005
4006 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4007 radeon_emit(ctx_cs, num_components[0]);
4008 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4009 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4010 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4011
4012 uint32_t gs_num_invocations = gs->info.gs.invocations;
4013 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4014 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4015 S_028B90_ENABLE(gs_num_invocations > 0));
4016
4017 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4018 gs_state->vgt_esgs_ring_itemsize);
4019
4020 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4021
4022 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4023 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4024 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4025 radeon_emit(cs, va >> 8);
4026 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4027 } else {
4028 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4029 radeon_emit(cs, va >> 8);
4030 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4031 }
4032
4033 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4034 radeon_emit(cs, gs->config.rsrc1);
4035 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4036
4037 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4038 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4039 } else {
4040 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4041 radeon_emit(cs, va >> 8);
4042 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4043 radeon_emit(cs, gs->config.rsrc1);
4044 radeon_emit(cs, gs->config.rsrc2);
4045 }
4046
4047 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4048 }
4049
4050 static void
4051 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4052 struct radeon_cmdbuf *cs,
4053 struct radv_pipeline *pipeline)
4054 {
4055 struct radv_shader_variant *gs;
4056
4057 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4058 if (!gs)
4059 return;
4060
4061 if (gs->info.is_ngg)
4062 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4063 else
4064 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4065
4066 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4067 gs->info.gs.vertices_out);
4068 }
4069
4070 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
4071 {
4072 uint32_t ps_input_cntl;
4073 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4074 ps_input_cntl = S_028644_OFFSET(offset);
4075 if (flat_shade)
4076 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4077 if (float16) {
4078 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4079 S_028644_ATTR0_VALID(1);
4080 }
4081 } else {
4082 /* The input is a DEFAULT_VAL constant. */
4083 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4084 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4085 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4086 ps_input_cntl = S_028644_OFFSET(0x20) |
4087 S_028644_DEFAULT_VAL(offset);
4088 }
4089 return ps_input_cntl;
4090 }
4091
4092 static void
4093 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4094 struct radv_pipeline *pipeline)
4095 {
4096 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4097 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4098 uint32_t ps_input_cntl[32];
4099
4100 unsigned ps_offset = 0;
4101
4102 if (ps->info.ps.prim_id_input) {
4103 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4104 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4105 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4106 ++ps_offset;
4107 }
4108 }
4109
4110 if (ps->info.ps.layer_input ||
4111 ps->info.needs_multiview_view_index) {
4112 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4113 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4114 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4115 else
4116 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
4117 ++ps_offset;
4118 }
4119
4120 if (ps->info.ps.has_pcoord) {
4121 unsigned val;
4122 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4123 ps_input_cntl[ps_offset] = val;
4124 ps_offset++;
4125 }
4126
4127 if (ps->info.ps.num_input_clips_culls) {
4128 unsigned vs_offset;
4129
4130 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4131 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4132 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4133 ++ps_offset;
4134 }
4135
4136 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4137 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4138 ps->info.ps.num_input_clips_culls > 4) {
4139 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4140 ++ps_offset;
4141 }
4142 }
4143
4144 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4145 unsigned vs_offset;
4146 bool flat_shade;
4147 bool float16;
4148 if (!(ps->info.ps.input_mask & (1u << i)))
4149 continue;
4150
4151 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4152 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4153 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4154 ++ps_offset;
4155 continue;
4156 }
4157
4158 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4159 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4160
4161 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
4162 ++ps_offset;
4163 }
4164
4165 if (ps_offset) {
4166 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4167 for (unsigned i = 0; i < ps_offset; i++) {
4168 radeon_emit(ctx_cs, ps_input_cntl[i]);
4169 }
4170 }
4171 }
4172
4173 static uint32_t
4174 radv_compute_db_shader_control(const struct radv_device *device,
4175 const struct radv_pipeline *pipeline,
4176 const struct radv_shader_variant *ps)
4177 {
4178 unsigned z_order;
4179 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4180 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4181 else
4182 z_order = V_02880C_LATE_Z;
4183
4184 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4185 !device->physical_device->rad_info.rbplus_allowed;
4186
4187 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4188 * but this appears to break Project Cars (DXVK). See
4189 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4190 */
4191 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4192
4193 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4194 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4195 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4196 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4197 S_02880C_Z_ORDER(z_order) |
4198 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4199 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4200 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4201 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4202 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4203 }
4204
4205 static void
4206 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4207 struct radeon_cmdbuf *cs,
4208 struct radv_pipeline *pipeline)
4209 {
4210 struct radv_shader_variant *ps;
4211 uint64_t va;
4212 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4213
4214 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4215 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4216
4217 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4218 radeon_emit(cs, va >> 8);
4219 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4220 radeon_emit(cs, ps->config.rsrc1);
4221 radeon_emit(cs, ps->config.rsrc2);
4222
4223 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4224 radv_compute_db_shader_control(pipeline->device,
4225 pipeline, ps));
4226
4227 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4228 ps->config.spi_ps_input_ena);
4229
4230 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4231 ps->config.spi_ps_input_addr);
4232
4233 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4234 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4235 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4236
4237 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4238
4239 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4240 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4241 ps->info.ps.writes_stencil,
4242 ps->info.ps.writes_sample_mask));
4243
4244 if (pipeline->device->dfsm_allowed) {
4245 /* optimise this? */
4246 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4247 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4248 }
4249 }
4250
4251 static void
4252 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4253 struct radv_pipeline *pipeline)
4254 {
4255 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4256 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4257 return;
4258
4259 unsigned vtx_reuse_depth = 30;
4260 if (radv_pipeline_has_tess(pipeline) &&
4261 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4262 vtx_reuse_depth = 14;
4263 }
4264 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4265 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4266 }
4267
4268 static uint32_t
4269 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4270 {
4271 uint32_t stages = 0;
4272 if (radv_pipeline_has_tess(pipeline)) {
4273 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4274 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4275
4276 if (radv_pipeline_has_gs(pipeline))
4277 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4278 S_028B54_GS_EN(1);
4279 else if (radv_pipeline_has_ngg(pipeline))
4280 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4281 else
4282 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4283 } else if (radv_pipeline_has_gs(pipeline)) {
4284 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4285 S_028B54_GS_EN(1);
4286 } else if (radv_pipeline_has_ngg(pipeline)) {
4287 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4288 }
4289
4290 if (radv_pipeline_has_ngg(pipeline)) {
4291 stages |= S_028B54_PRIMGEN_EN(1);
4292 } else if (radv_pipeline_has_gs(pipeline)) {
4293 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4294 }
4295
4296 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4297 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4298
4299 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4300 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4301
4302 if (radv_pipeline_has_tess(pipeline))
4303 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4304
4305 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4306 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4307 if (pipeline->gs_copy_shader)
4308 vs_size = pipeline->gs_copy_shader->info.wave_size;
4309 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4310 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4311 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4312 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4313
4314 if (radv_pipeline_has_ngg(pipeline))
4315 gs_size = vs_size;
4316
4317 /* legacy GS only supports Wave64 */
4318 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4319 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4320 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4321 }
4322
4323 return stages;
4324 }
4325
4326 static uint32_t
4327 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4328 {
4329 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4330 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4331
4332 if (!discard_rectangle_info)
4333 return 0xffff;
4334
4335 unsigned mask = 0;
4336
4337 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4338 /* Interpret i as a bitmask, and then set the bit in the mask if
4339 * that combination of rectangles in which the pixel is contained
4340 * should pass the cliprect test. */
4341 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4342
4343 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4344 !relevant_subset)
4345 continue;
4346
4347 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4348 relevant_subset)
4349 continue;
4350
4351 mask |= 1u << i;
4352 }
4353
4354 return mask;
4355 }
4356
4357 static void
4358 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4359 struct radv_pipeline *pipeline,
4360 const struct radv_tessellation_state *tess)
4361 {
4362 bool break_wave_at_eoi = false;
4363 unsigned primgroup_size;
4364 unsigned vertgroup_size;
4365
4366 if (radv_pipeline_has_tess(pipeline)) {
4367 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4368 vertgroup_size = 0;
4369 } else if (radv_pipeline_has_gs(pipeline)) {
4370 const struct gfx9_gs_info *gs_state =
4371 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4372 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4373 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4374 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4375 } else {
4376 primgroup_size = 128; /* recommended without a GS and tess */
4377 vertgroup_size = 0;
4378 }
4379
4380 if (radv_pipeline_has_tess(pipeline)) {
4381 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4382 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4383 break_wave_at_eoi = true;
4384 }
4385
4386 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4387 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4388 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4389 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4390 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4391 }
4392
4393 static void
4394 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4395 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4396 const struct radv_graphics_pipeline_create_info *extra,
4397 const struct radv_blend_state *blend,
4398 const struct radv_tessellation_state *tess,
4399 unsigned prim, unsigned gs_out)
4400 {
4401 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4402 struct radeon_cmdbuf *cs = &pipeline->cs;
4403
4404 cs->max_dw = 64;
4405 ctx_cs->max_dw = 256;
4406 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4407 ctx_cs->buf = cs->buf + cs->max_dw;
4408
4409 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4410 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4411 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4412 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4413 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4414 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4415 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4416 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4417 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4418 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4419 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4420 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo);
4421
4422 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4423 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4424
4425 radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
4426 S_0286E8_WAVES(pipeline->max_waves) |
4427 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4428
4429 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4430
4431 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4432 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4433 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4434 } else {
4435 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4436 }
4437 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4438
4439 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4440
4441 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4442
4443 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4444 assert(cs->cdw <= cs->max_dw);
4445 }
4446
4447 static struct radv_ia_multi_vgt_param_helpers
4448 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4449 const struct radv_tessellation_state *tess,
4450 uint32_t prim)
4451 {
4452 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4453 const struct radv_device *device = pipeline->device;
4454
4455 if (radv_pipeline_has_tess(pipeline))
4456 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4457 else if (radv_pipeline_has_gs(pipeline))
4458 ia_multi_vgt_param.primgroup_size = 64;
4459 else
4460 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4461
4462 /* GS requirement. */
4463 ia_multi_vgt_param.partial_es_wave = false;
4464 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4465 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4466 ia_multi_vgt_param.partial_es_wave = true;
4467
4468 ia_multi_vgt_param.wd_switch_on_eop = false;
4469 if (device->physical_device->rad_info.chip_class >= GFX7) {
4470 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4471 * 4 shader engines. Set 1 to pass the assertion below.
4472 * The other cases are hardware requirements. */
4473 if (device->physical_device->rad_info.max_se < 4 ||
4474 prim == V_008958_DI_PT_POLYGON ||
4475 prim == V_008958_DI_PT_LINELOOP ||
4476 prim == V_008958_DI_PT_TRIFAN ||
4477 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4478 (pipeline->graphics.prim_restart_enable &&
4479 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4480 (prim != V_008958_DI_PT_POINTLIST &&
4481 prim != V_008958_DI_PT_LINESTRIP))))
4482 ia_multi_vgt_param.wd_switch_on_eop = true;
4483 }
4484
4485 ia_multi_vgt_param.ia_switch_on_eoi = false;
4486 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4487 ia_multi_vgt_param.ia_switch_on_eoi = true;
4488 if (radv_pipeline_has_gs(pipeline) &&
4489 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4490 ia_multi_vgt_param.ia_switch_on_eoi = true;
4491 if (radv_pipeline_has_tess(pipeline)) {
4492 /* SWITCH_ON_EOI must be set if PrimID is used. */
4493 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4494 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4495 ia_multi_vgt_param.ia_switch_on_eoi = true;
4496 }
4497
4498 ia_multi_vgt_param.partial_vs_wave = false;
4499 if (radv_pipeline_has_tess(pipeline)) {
4500 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4501 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4502 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4503 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4504 radv_pipeline_has_gs(pipeline))
4505 ia_multi_vgt_param.partial_vs_wave = true;
4506 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4507 if (device->physical_device->rad_info.has_distributed_tess) {
4508 if (radv_pipeline_has_gs(pipeline)) {
4509 if (device->physical_device->rad_info.chip_class <= GFX8)
4510 ia_multi_vgt_param.partial_es_wave = true;
4511 } else {
4512 ia_multi_vgt_param.partial_vs_wave = true;
4513 }
4514 }
4515 }
4516
4517 /* Workaround for a VGT hang when strip primitive types are used with
4518 * primitive restart.
4519 */
4520 if (pipeline->graphics.prim_restart_enable &&
4521 (prim == V_008958_DI_PT_LINESTRIP ||
4522 prim == V_008958_DI_PT_TRISTRIP ||
4523 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4524 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4525 ia_multi_vgt_param.partial_vs_wave = true;
4526 }
4527
4528 if (radv_pipeline_has_gs(pipeline)) {
4529 /* On these chips there is the possibility of a hang if the
4530 * pipeline uses a GS and partial_vs_wave is not set.
4531 *
4532 * This mostly does not hit 4-SE chips, as those typically set
4533 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4534 * with GS due to another workaround.
4535 *
4536 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4537 */
4538 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4539 device->physical_device->rad_info.family == CHIP_FIJI ||
4540 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4541 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4542 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4543 device->physical_device->rad_info.family == CHIP_VEGAM) {
4544 ia_multi_vgt_param.partial_vs_wave = true;
4545 }
4546 }
4547
4548 ia_multi_vgt_param.base =
4549 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4550 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4551 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4552 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4553 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4554
4555 return ia_multi_vgt_param;
4556 }
4557
4558
4559 static void
4560 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4561 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4562 {
4563 const VkPipelineVertexInputStateCreateInfo *vi_info =
4564 pCreateInfo->pVertexInputState;
4565 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4566
4567 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4568 const VkVertexInputAttributeDescription *desc =
4569 &vi_info->pVertexAttributeDescriptions[i];
4570 unsigned loc = desc->location;
4571 const struct vk_format_description *format_desc;
4572
4573 format_desc = vk_format_description(desc->format);
4574
4575 velems->format_size[loc] = format_desc->block.bits / 8;
4576 }
4577
4578 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4579 const VkVertexInputBindingDescription *desc =
4580 &vi_info->pVertexBindingDescriptions[i];
4581
4582 pipeline->binding_stride[desc->binding] = desc->stride;
4583 pipeline->num_vertex_bindings =
4584 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4585 }
4586 }
4587
4588 static struct radv_shader_variant *
4589 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4590 {
4591 int i;
4592
4593 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4594 struct radv_shader_variant *shader =
4595 radv_get_shader(pipeline, i);
4596
4597 if (shader && shader->info.so.num_outputs > 0)
4598 return shader;
4599 }
4600
4601 return NULL;
4602 }
4603
4604 static VkResult
4605 radv_pipeline_init(struct radv_pipeline *pipeline,
4606 struct radv_device *device,
4607 struct radv_pipeline_cache *cache,
4608 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4609 const struct radv_graphics_pipeline_create_info *extra)
4610 {
4611 VkResult result;
4612 bool has_view_index = false;
4613
4614 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4615 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4616 if (subpass->view_mask)
4617 has_view_index = true;
4618
4619 pipeline->device = device;
4620 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4621 assert(pipeline->layout);
4622
4623 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4624
4625 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4626 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4627 radv_init_feedback(creation_feedback);
4628
4629 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4630
4631 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4632 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4633 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4634 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4635 pStages[stage] = &pCreateInfo->pStages[i];
4636 if(creation_feedback)
4637 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4638 }
4639
4640 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4641 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pCreateInfo, pipeline_feedback, stage_feedbacks);
4642
4643 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4644 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4645 uint32_t gs_out;
4646 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4647
4648 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4649
4650 if (radv_pipeline_has_gs(pipeline)) {
4651 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4652 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4653 } else if (radv_pipeline_has_tess(pipeline)) {
4654 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4655 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4656 else
4657 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4658 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4659 } else {
4660 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4661 }
4662 if (extra && extra->use_rectlist) {
4663 prim = V_008958_DI_PT_RECTLIST;
4664 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4665 pipeline->graphics.can_use_guardband = true;
4666 if (radv_pipeline_has_ngg(pipeline))
4667 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4668 }
4669 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4670 /* prim vertex count will need TESS changes */
4671 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
4672
4673 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
4674
4675 /* Ensure that some export memory is always allocated, for two reasons:
4676 *
4677 * 1) Correctness: The hardware ignores the EXEC mask if no export
4678 * memory is allocated, so KILL and alpha test do not work correctly
4679 * without this.
4680 * 2) Performance: Every shader needs at least a NULL export, even when
4681 * it writes no color/depth output. The NULL export instruction
4682 * stalls without this setting.
4683 *
4684 * Don't add this to CB_SHADER_MASK.
4685 *
4686 * GFX10 supports pixel shaders without exports by setting both the
4687 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4688 * instructions if any are present.
4689 */
4690 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4691 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4692 ps->info.ps.can_discard) &&
4693 !blend.spi_shader_col_format) {
4694 if (!ps->info.ps.writes_z &&
4695 !ps->info.ps.writes_stencil &&
4696 !ps->info.ps.writes_sample_mask)
4697 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4698 }
4699
4700 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4701 if (pipeline->shaders[i]) {
4702 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4703 }
4704 }
4705
4706 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4707 struct radv_shader_variant *gs =
4708 pipeline->shaders[MESA_SHADER_GEOMETRY];
4709
4710 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
4711 }
4712
4713 struct radv_tessellation_state tess = {0};
4714 if (radv_pipeline_has_tess(pipeline)) {
4715 if (prim == V_008958_DI_PT_PATCH) {
4716 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
4717 pipeline->graphics.prim_vertex_count.incr = 1;
4718 }
4719 tess = calculate_tess_state(pipeline, pCreateInfo);
4720 }
4721
4722 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
4723
4724 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4725
4726 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4727 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4728
4729 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4730 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4731 if (loc->sgpr_idx != -1) {
4732 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4733 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4734 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
4735 pipeline->graphics.vtx_emit_num = 3;
4736 else
4737 pipeline->graphics.vtx_emit_num = 2;
4738 }
4739
4740 /* Find the last vertex shader stage that eventually uses streamout. */
4741 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4742
4743 result = radv_pipeline_scratch_init(device, pipeline);
4744 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
4745
4746 return result;
4747 }
4748
4749 VkResult
4750 radv_graphics_pipeline_create(
4751 VkDevice _device,
4752 VkPipelineCache _cache,
4753 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4754 const struct radv_graphics_pipeline_create_info *extra,
4755 const VkAllocationCallbacks *pAllocator,
4756 VkPipeline *pPipeline)
4757 {
4758 RADV_FROM_HANDLE(radv_device, device, _device);
4759 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4760 struct radv_pipeline *pipeline;
4761 VkResult result;
4762
4763 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4764 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4765 if (pipeline == NULL)
4766 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4767
4768 result = radv_pipeline_init(pipeline, device, cache,
4769 pCreateInfo, extra);
4770 if (result != VK_SUCCESS) {
4771 radv_pipeline_destroy(device, pipeline, pAllocator);
4772 return result;
4773 }
4774
4775 *pPipeline = radv_pipeline_to_handle(pipeline);
4776
4777 return VK_SUCCESS;
4778 }
4779
4780 VkResult radv_CreateGraphicsPipelines(
4781 VkDevice _device,
4782 VkPipelineCache pipelineCache,
4783 uint32_t count,
4784 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4785 const VkAllocationCallbacks* pAllocator,
4786 VkPipeline* pPipelines)
4787 {
4788 VkResult result = VK_SUCCESS;
4789 unsigned i = 0;
4790
4791 for (; i < count; i++) {
4792 VkResult r;
4793 r = radv_graphics_pipeline_create(_device,
4794 pipelineCache,
4795 &pCreateInfos[i],
4796 NULL, pAllocator, &pPipelines[i]);
4797 if (r != VK_SUCCESS) {
4798 result = r;
4799 pPipelines[i] = VK_NULL_HANDLE;
4800 }
4801 }
4802
4803 return result;
4804 }
4805
4806
4807 static void
4808 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
4809 {
4810 struct radv_shader_variant *compute_shader;
4811 struct radv_device *device = pipeline->device;
4812 unsigned threads_per_threadgroup;
4813 unsigned threadgroups_per_cu = 1;
4814 unsigned waves_per_threadgroup;
4815 unsigned max_waves_per_sh = 0;
4816 uint64_t va;
4817
4818 pipeline->cs.buf = malloc(20 * 4);
4819 pipeline->cs.max_dw = 20;
4820
4821 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4822 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
4823
4824 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
4825 radeon_emit(&pipeline->cs, va >> 8);
4826 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
4827
4828 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
4829 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
4830 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
4831
4832 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
4833 S_00B860_WAVES(pipeline->max_waves) |
4834 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4835
4836 /* Calculate best compute resource limits. */
4837 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
4838 compute_shader->info.cs.block_size[1] *
4839 compute_shader->info.cs.block_size[2];
4840 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
4841 device->physical_device->cs_wave_size);
4842
4843 if (device->physical_device->rad_info.chip_class >= GFX10 &&
4844 waves_per_threadgroup == 1)
4845 threadgroups_per_cu = 2;
4846
4847 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
4848 ac_get_compute_resource_limits(&device->physical_device->rad_info,
4849 waves_per_threadgroup,
4850 max_waves_per_sh,
4851 threadgroups_per_cu));
4852
4853 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4854 radeon_emit(&pipeline->cs,
4855 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
4856 radeon_emit(&pipeline->cs,
4857 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
4858 radeon_emit(&pipeline->cs,
4859 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
4860
4861 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
4862 }
4863
4864 static VkResult radv_compute_pipeline_create(
4865 VkDevice _device,
4866 VkPipelineCache _cache,
4867 const VkComputePipelineCreateInfo* pCreateInfo,
4868 const VkAllocationCallbacks* pAllocator,
4869 VkPipeline* pPipeline)
4870 {
4871 RADV_FROM_HANDLE(radv_device, device, _device);
4872 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4873 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4874 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4875 struct radv_pipeline *pipeline;
4876 VkResult result;
4877
4878 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4879 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4880 if (pipeline == NULL)
4881 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4882
4883 pipeline->device = device;
4884 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4885 assert(pipeline->layout);
4886
4887 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4888 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4889 radv_init_feedback(creation_feedback);
4890
4891 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4892 if (creation_feedback)
4893 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
4894
4895 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
4896 radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, NULL, pipeline_feedback, stage_feedbacks);
4897
4898 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
4899 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
4900 result = radv_pipeline_scratch_init(device, pipeline);
4901 if (result != VK_SUCCESS) {
4902 radv_pipeline_destroy(device, pipeline, pAllocator);
4903 return result;
4904 }
4905
4906 radv_compute_generate_pm4(pipeline);
4907
4908 *pPipeline = radv_pipeline_to_handle(pipeline);
4909
4910 return VK_SUCCESS;
4911 }
4912
4913 VkResult radv_CreateComputePipelines(
4914 VkDevice _device,
4915 VkPipelineCache pipelineCache,
4916 uint32_t count,
4917 const VkComputePipelineCreateInfo* pCreateInfos,
4918 const VkAllocationCallbacks* pAllocator,
4919 VkPipeline* pPipelines)
4920 {
4921 VkResult result = VK_SUCCESS;
4922
4923 unsigned i = 0;
4924 for (; i < count; i++) {
4925 VkResult r;
4926 r = radv_compute_pipeline_create(_device, pipelineCache,
4927 &pCreateInfos[i],
4928 pAllocator, &pPipelines[i]);
4929 if (r != VK_SUCCESS) {
4930 result = r;
4931 pPipelines[i] = VK_NULL_HANDLE;
4932 }
4933 }
4934
4935 return result;
4936 }
4937
4938
4939 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
4940 {
4941 uint32_t ret = 0;
4942 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
4943 if (pipeline->shaders[i])
4944 ret += i == MESA_SHADER_GEOMETRY ? 2u : 1u;
4945
4946 }
4947 return ret;
4948 }
4949
4950 static struct radv_shader_variant *
4951 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
4952 {
4953 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
4954 if (!pipeline->shaders[i])
4955 continue;
4956 if (!index) {
4957 *stage = i;
4958 return pipeline->shaders[i];
4959 }
4960
4961 --index;
4962
4963 if (i == MESA_SHADER_GEOMETRY) {
4964 if (!index) {
4965 *stage = i;
4966 return pipeline->gs_copy_shader;
4967 }
4968 --index;
4969 }
4970 }
4971
4972 *stage = -1;
4973 return NULL;
4974 }
4975
4976 /* Basically strlcpy (which does not exist on linux) specialized for
4977 * descriptions. */
4978 static void desc_copy(char *desc, const char *src) {
4979 int len = strlen(src);
4980 assert(len < VK_MAX_DESCRIPTION_SIZE);
4981 memcpy(desc, src, len);
4982 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
4983 }
4984
4985 VkResult radv_GetPipelineExecutablePropertiesKHR(
4986 VkDevice _device,
4987 const VkPipelineInfoKHR* pPipelineInfo,
4988 uint32_t* pExecutableCount,
4989 VkPipelineExecutablePropertiesKHR* pProperties)
4990 {
4991 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
4992 const uint32_t total_count = radv_get_executable_count(pipeline);
4993
4994 if (!pProperties) {
4995 *pExecutableCount = total_count;
4996 return VK_SUCCESS;
4997 }
4998
4999 const uint32_t count = MIN2(total_count, *pExecutableCount);
5000 for (unsigned i = 0, executable_idx = 0;
5001 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5002 if (!pipeline->shaders[i])
5003 continue;
5004 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5005 const char *name = NULL;
5006 const char *description = NULL;
5007 switch(i) {
5008 case MESA_SHADER_VERTEX:
5009 name = "Vertex Shader";
5010 description = "Vulkan Vertex Shader";
5011 break;
5012 case MESA_SHADER_TESS_CTRL:
5013 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5014 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5015 name = "Vertex + Tessellation Control Shaders";
5016 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5017 } else {
5018 name = "Tessellation Control Shader";
5019 description = "Vulkan Tessellation Control Shader";
5020 }
5021 break;
5022 case MESA_SHADER_TESS_EVAL:
5023 name = "Tessellation Evaluation Shader";
5024 description = "Vulkan Tessellation Evaluation Shader";
5025 break;
5026 case MESA_SHADER_GEOMETRY:
5027 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5028 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5029 name = "Tessellation Evaluation + Geometry Shaders";
5030 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5031 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5032 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5033 name = "Vertex + Geometry Shader";
5034 description = "Combined Vulkan Vertex and Geometry Shaders";
5035 } else {
5036 name = "Geometry Shader";
5037 description = "Vulkan Geometry Shader";
5038 }
5039 break;
5040 case MESA_SHADER_FRAGMENT:
5041 name = "Fragment Shader";
5042 description = "Vulkan Fragment Shader";
5043 break;
5044 case MESA_SHADER_COMPUTE:
5045 name = "Compute Shader";
5046 description = "Vulkan Compute Shader";
5047 break;
5048 }
5049
5050 desc_copy(pProperties[executable_idx].name, name);
5051 desc_copy(pProperties[executable_idx].description, description);
5052
5053 ++executable_idx;
5054 if (i == MESA_SHADER_GEOMETRY) {
5055 assert(pipeline->gs_copy_shader);
5056 if (executable_idx >= count)
5057 break;
5058
5059 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5060 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5061 desc_copy(pProperties[executable_idx].description,
5062 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5063
5064 ++executable_idx;
5065 }
5066 }
5067
5068 for (unsigned i = 0; i < count; ++i)
5069 pProperties[i].subgroupSize = 64;
5070
5071 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5072 *pExecutableCount = count;
5073 return result;
5074 }
5075
5076 VkResult radv_GetPipelineExecutableStatisticsKHR(
5077 VkDevice _device,
5078 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5079 uint32_t* pStatisticCount,
5080 VkPipelineExecutableStatisticKHR* pStatistics)
5081 {
5082 RADV_FROM_HANDLE(radv_device, device, _device);
5083 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5084 gl_shader_stage stage;
5085 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5086
5087 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5088 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5089 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5090
5091 VkPipelineExecutableStatisticKHR *s = pStatistics;
5092 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5093 VkResult result = VK_SUCCESS;
5094
5095 if (s < end) {
5096 desc_copy(s->name, "SGPRs");
5097 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5098 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5099 s->value.u64 = shader->config.num_sgprs;
5100 }
5101 ++s;
5102
5103 if (s < end) {
5104 desc_copy(s->name, "VGPRs");
5105 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5106 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5107 s->value.u64 = shader->config.num_vgprs;
5108 }
5109 ++s;
5110
5111 if (s < end) {
5112 desc_copy(s->name, "Spilled SGPRs");
5113 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5114 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5115 s->value.u64 = shader->config.spilled_sgprs;
5116 }
5117 ++s;
5118
5119 if (s < end) {
5120 desc_copy(s->name, "Spilled VGPRs");
5121 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5122 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5123 s->value.u64 = shader->config.spilled_vgprs;
5124 }
5125 ++s;
5126
5127 if (s < end) {
5128 desc_copy(s->name, "PrivMem VGPRs");
5129 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5130 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5131 s->value.u64 = shader->info.private_mem_vgprs;
5132 }
5133 ++s;
5134
5135 if (s < end) {
5136 desc_copy(s->name, "Code size");
5137 desc_copy(s->description, "Code size in bytes");
5138 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5139 s->value.u64 = shader->exec_size;
5140 }
5141 ++s;
5142
5143 if (s < end) {
5144 desc_copy(s->name, "LDS size");
5145 desc_copy(s->description, "LDS size in bytes per workgroup");
5146 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5147 s->value.u64 = shader->config.lds_size * lds_increment;
5148 }
5149 ++s;
5150
5151 if (s < end) {
5152 desc_copy(s->name, "Scratch size");
5153 desc_copy(s->description, "Private memory in bytes per subgroup");
5154 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5155 s->value.u64 = shader->config.scratch_bytes_per_wave;
5156 }
5157 ++s;
5158
5159 if (s < end) {
5160 desc_copy(s->name, "Subgroups per SIMD");
5161 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5162 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5163 s->value.u64 = max_waves;
5164 }
5165 ++s;
5166
5167 if (!pStatistics)
5168 *pStatisticCount = s - pStatistics;
5169 else if (s > end) {
5170 *pStatisticCount = end - pStatistics;
5171 result = VK_INCOMPLETE;
5172 } else {
5173 *pStatisticCount = s - pStatistics;
5174 }
5175
5176 return result;
5177 }
5178
5179 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5180 {
5181 size_t total_size = strlen(src) + 1;
5182
5183 if (!data) {
5184 *data_size = total_size;
5185 return VK_SUCCESS;
5186 }
5187
5188 size_t size = MIN2(total_size, *data_size);
5189
5190 memcpy(data, src, size);
5191 if (size)
5192 *((char*)data + size - 1) = 0;
5193 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5194 }
5195
5196 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5197 VkDevice device,
5198 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5199 uint32_t* pInternalRepresentationCount,
5200 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5201 {
5202 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5203 gl_shader_stage stage;
5204 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5205
5206 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5207 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5208 VkResult result = VK_SUCCESS;
5209 /* optimized NIR */
5210 if (p < end) {
5211 p->isText = true;
5212 desc_copy(p->name, "NIR Shader(s)");
5213 desc_copy(p->description, "The optimized NIR shader(s)");
5214 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5215 result = VK_INCOMPLETE;
5216 }
5217 ++p;
5218
5219 /* LLVM IR */
5220 if (p < end) {
5221 p->isText = true;
5222 desc_copy(p->name, "LLVM IR");
5223 desc_copy(p->description, "The LLVM IR after some optimizations");
5224 if (radv_copy_representation(p->pData, &p->dataSize, shader->llvm_ir_string) != VK_SUCCESS)
5225 result = VK_INCOMPLETE;
5226 }
5227 ++p;
5228
5229 /* Disassembler */
5230 if (p < end) {
5231 p->isText = true;
5232 desc_copy(p->name, "Assembly");
5233 desc_copy(p->description, "Final Assembly");
5234 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5235 result = VK_INCOMPLETE;
5236 }
5237 ++p;
5238
5239 if (!pInternalRepresentations)
5240 *pInternalRepresentationCount = p - pInternalRepresentations;
5241 else if(p > end) {
5242 result = VK_INCOMPLETE;
5243 *pInternalRepresentationCount = end - pInternalRepresentations;
5244 } else {
5245 *pInternalRepresentationCount = p - pInternalRepresentations;
5246 }
5247
5248 return result;
5249 }