projects / mesa.git / blob
? search:


49610a1a223a0a45f960ba4e59a6524797b68ac0
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_private.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34
35 #include <llvm-c/Core.h>
36 #include <llvm-c/TargetMachine.h>
37
38 #include "sid.h"
39 #include "gfx9d.h"
40 #include "r600d_common.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_nir_to_llvm.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 void radv_shader_variant_destroy(struct radv_device *device,
49 struct radv_shader_variant *variant);
50
51 static const struct nir_shader_compiler_options nir_options = {
52 .vertex_id_zero_based = true,
53 .lower_scmp = true,
54 .lower_flrp32 = true,
55 .lower_fsat = true,
56 .lower_fdiv = true,
57 .lower_sub = true,
58 .lower_pack_snorm_2x16 = true,
59 .lower_pack_snorm_4x8 = true,
60 .lower_pack_unorm_2x16 = true,
61 .lower_pack_unorm_4x8 = true,
62 .lower_unpack_snorm_2x16 = true,
63 .lower_unpack_snorm_4x8 = true,
64 .lower_unpack_unorm_2x16 = true,
65 .lower_unpack_unorm_4x8 = true,
66 .lower_extract_byte = true,
67 .lower_extract_word = true,
68 .max_unroll_iterations = 32
69 };
70
71 VkResult radv_CreateShaderModule(
72 VkDevice _device,
73 const VkShaderModuleCreateInfo* pCreateInfo,
74 const VkAllocationCallbacks* pAllocator,
75 VkShaderModule* pShaderModule)
76 {
77 RADV_FROM_HANDLE(radv_device, device, _device);
78 struct radv_shader_module *module;
79
80 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
81 assert(pCreateInfo->flags == 0);
82
83 module = vk_alloc2(&device->alloc, pAllocator,
84 sizeof(*module) + pCreateInfo->codeSize, 8,
85 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
86 if (module == NULL)
87 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
88
89 module->nir = NULL;
90 module->size = pCreateInfo->codeSize;
91 memcpy(module->data, pCreateInfo->pCode, module->size);
92
93 _mesa_sha1_compute(module->data, module->size, module->sha1);
94
95 *pShaderModule = radv_shader_module_to_handle(module);
96
97 return VK_SUCCESS;
98 }
99
100 void radv_DestroyShaderModule(
101 VkDevice _device,
102 VkShaderModule _module,
103 const VkAllocationCallbacks* pAllocator)
104 {
105 RADV_FROM_HANDLE(radv_device, device, _device);
106 RADV_FROM_HANDLE(radv_shader_module, module, _module);
107
108 if (!module)
109 return;
110
111 vk_free2(&device->alloc, pAllocator, module);
112 }
113
114
115 static void
116 radv_pipeline_destroy(struct radv_device *device,
117 struct radv_pipeline *pipeline,
118 const VkAllocationCallbacks* allocator)
119 {
120 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
121 if (pipeline->shaders[i])
122 radv_shader_variant_destroy(device, pipeline->shaders[i]);
123
124 if (pipeline->gs_copy_shader)
125 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
126
127 vk_free2(&device->alloc, allocator, pipeline);
128 }
129
130 void radv_DestroyPipeline(
131 VkDevice _device,
132 VkPipeline _pipeline,
133 const VkAllocationCallbacks* pAllocator)
134 {
135 RADV_FROM_HANDLE(radv_device, device, _device);
136 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
137
138 if (!_pipeline)
139 return;
140
141 radv_pipeline_destroy(device, pipeline, pAllocator);
142 }
143
144
145 static void
146 radv_optimize_nir(struct nir_shader *shader)
147 {
148 bool progress;
149
150 do {
151 progress = false;
152
153 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
154 NIR_PASS_V(shader, nir_lower_64bit_pack);
155 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
156 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
157
158 NIR_PASS(progress, shader, nir_copy_prop);
159 NIR_PASS(progress, shader, nir_opt_remove_phis);
160 NIR_PASS(progress, shader, nir_opt_dce);
161 if (nir_opt_trivial_continues(shader)) {
162 progress = true;
163 NIR_PASS(progress, shader, nir_copy_prop);
164 NIR_PASS(progress, shader, nir_opt_dce);
165 }
166 NIR_PASS(progress, shader, nir_opt_if);
167 NIR_PASS(progress, shader, nir_opt_dead_cf);
168 NIR_PASS(progress, shader, nir_opt_cse);
169 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
170 NIR_PASS(progress, shader, nir_opt_algebraic);
171 NIR_PASS(progress, shader, nir_opt_constant_folding);
172 NIR_PASS(progress, shader, nir_opt_undef);
173 NIR_PASS(progress, shader, nir_opt_conditional_discard);
174 if (shader->options->max_unroll_iterations) {
175 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
176 }
177 } while (progress);
178 }
179
180 static nir_shader *
181 radv_shader_compile_to_nir(struct radv_device *device,
182 struct radv_shader_module *module,
183 const char *entrypoint_name,
184 gl_shader_stage stage,
185 const VkSpecializationInfo *spec_info,
186 bool dump)
187 {
188 if (strcmp(entrypoint_name, "main") != 0) {
189 radv_finishme("Multiple shaders per module not really supported");
190 }
191
192 nir_shader *nir;
193 nir_function *entry_point;
194 if (module->nir) {
195 /* Some things such as our meta clear/blit code will give us a NIR
196 * shader directly. In that case, we just ignore the SPIR-V entirely
197 * and just use the NIR shader */
198 nir = module->nir;
199 nir->options = &nir_options;
200 nir_validate_shader(nir);
201
202 assert(exec_list_length(&nir->functions) == 1);
203 struct exec_node *node = exec_list_get_head(&nir->functions);
204 entry_point = exec_node_data(nir_function, node, node);
205 } else {
206 uint32_t *spirv = (uint32_t *) module->data;
207 assert(module->size % 4 == 0);
208
209 uint32_t num_spec_entries = 0;
210 struct nir_spirv_specialization *spec_entries = NULL;
211 if (spec_info && spec_info->mapEntryCount > 0) {
212 num_spec_entries = spec_info->mapEntryCount;
213 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
214 for (uint32_t i = 0; i < num_spec_entries; i++) {
215 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
216 const void *data = spec_info->pData + entry.offset;
217 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
218
219 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
220 if (spec_info->dataSize == 8)
221 spec_entries[i].data64 = *(const uint64_t *)data;
222 else
223 spec_entries[i].data32 = *(const uint32_t *)data;
224 }
225 }
226 const struct nir_spirv_supported_extensions supported_ext = {
227 .draw_parameters = true,
228 .float64 = true,
229 .image_read_without_format = true,
230 .image_write_without_format = true,
231 .tessellation = true,
232 .int64 = true,
233 };
234 entry_point = spirv_to_nir(spirv, module->size / 4,
235 spec_entries, num_spec_entries,
236 stage, entrypoint_name, &supported_ext, &nir_options);
237 nir = entry_point->shader;
238 assert(nir->stage == stage);
239 nir_validate_shader(nir);
240
241 free(spec_entries);
242
243 /* We have to lower away local constant initializers right before we
244 * inline functions. That way they get properly initialized at the top
245 * of the function and not at the top of its caller.
246 */
247 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
248 NIR_PASS_V(nir, nir_lower_returns);
249 NIR_PASS_V(nir, nir_inline_functions);
250
251 /* Pick off the single entrypoint that we want */
252 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
253 if (func != entry_point)
254 exec_node_remove(&func->node);
255 }
256 assert(exec_list_length(&nir->functions) == 1);
257 entry_point->name = ralloc_strdup(entry_point, "main");
258
259 NIR_PASS_V(nir, nir_remove_dead_variables,
260 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
261
262 /* Now that we've deleted all but the main function, we can go ahead and
263 * lower the rest of the constant initializers.
264 */
265 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
266 NIR_PASS_V(nir, nir_lower_system_values);
267 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
268 }
269
270 /* Vulkan uses the separate-shader linking model */
271 nir->info.separate_shader = true;
272
273 nir_shader_gather_info(nir, entry_point->impl);
274
275 nir_variable_mode indirect_mask = 0;
276 indirect_mask |= nir_var_shader_in;
277 indirect_mask |= nir_var_local;
278
279 nir_lower_indirect_derefs(nir, indirect_mask);
280
281 static const nir_lower_tex_options tex_options = {
282 .lower_txp = ~0,
283 };
284
285 nir_lower_tex(nir, &tex_options);
286
287 nir_lower_vars_to_ssa(nir);
288 nir_lower_var_copies(nir);
289 nir_lower_global_vars_to_local(nir);
290 nir_remove_dead_variables(nir, nir_var_local);
291 radv_optimize_nir(nir);
292
293 if (dump)
294 nir_print_shader(nir, stderr);
295
296 return nir;
297 }
298
299 static const char *radv_get_shader_name(struct radv_shader_variant *var,
300 gl_shader_stage stage)
301 {
302 switch (stage) {
303 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
304 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
305 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
306 case MESA_SHADER_COMPUTE: return "Compute Shader";
307 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
308 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
309 default:
310 return "Unknown shader";
311 };
312
313 }
314 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
315 {
316 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
317 struct radv_shader_variant *var;
318 struct ac_shader_config *conf;
319 int i;
320 FILE *file = stderr;
321 unsigned max_simd_waves = 10;
322 unsigned lds_per_wave = 0;
323
324 for (i = 0; i < MESA_SHADER_STAGES; i++) {
325 if (!pipeline->shaders[i])
326 continue;
327 var = pipeline->shaders[i];
328
329 conf = &var->config;
330
331 if (i == MESA_SHADER_FRAGMENT) {
332 lds_per_wave = conf->lds_size * lds_increment +
333 align(var->info.fs.num_interp * 48, lds_increment);
334 }
335
336 if (conf->num_sgprs) {
337 if (device->physical_device->rad_info.chip_class >= VI)
338 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
339 else
340 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
341 }
342
343 if (conf->num_vgprs)
344 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
345
346 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
347 * that PS can use.
348 */
349 if (lds_per_wave)
350 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
351
352 fprintf(file, "\n%s:\n",
353 radv_get_shader_name(var, i));
354 if (i == MESA_SHADER_FRAGMENT) {
355 fprintf(file, "*** SHADER CONFIG ***\n"
356 "SPI_PS_INPUT_ADDR = 0x%04x\n"
357 "SPI_PS_INPUT_ENA = 0x%04x\n",
358 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
359 }
360 fprintf(file, "*** SHADER STATS ***\n"
361 "SGPRS: %d\n"
362 "VGPRS: %d\n"
363 "Spilled SGPRs: %d\n"
364 "Spilled VGPRs: %d\n"
365 "Code Size: %d bytes\n"
366 "LDS: %d blocks\n"
367 "Scratch: %d bytes per wave\n"
368 "Max Waves: %d\n"
369 "********************\n\n\n",
370 conf->num_sgprs, conf->num_vgprs,
371 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
372 conf->lds_size, conf->scratch_bytes_per_wave,
373 max_simd_waves);
374 }
375 }
376
377 void radv_shader_variant_destroy(struct radv_device *device,
378 struct radv_shader_variant *variant)
379 {
380 if (!p_atomic_dec_zero(&variant->ref_count))
381 return;
382
383 device->ws->buffer_destroy(variant->bo);
384 free(variant);
385 }
386
387 static void radv_fill_shader_variant(struct radv_device *device,
388 struct radv_shader_variant *variant,
389 struct ac_shader_binary *binary,
390 gl_shader_stage stage)
391 {
392 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
393 unsigned vgpr_comp_cnt = 0;
394
395 if (scratch_enabled && !device->llvm_supports_spill)
396 radv_finishme("shader scratch support only available with LLVM 4.0");
397
398 variant->code_size = binary->code_size;
399 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
400 S_00B12C_SCRATCH_EN(scratch_enabled);
401
402 switch (stage) {
403 case MESA_SHADER_TESS_EVAL:
404 vgpr_comp_cnt = 3;
405 /* fallthrough */
406 case MESA_SHADER_TESS_CTRL:
407 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
408 break;
409 case MESA_SHADER_VERTEX:
410 case MESA_SHADER_GEOMETRY:
411 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
412 break;
413 case MESA_SHADER_FRAGMENT:
414 break;
415 case MESA_SHADER_COMPUTE:
416 variant->rsrc2 |=
417 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
418 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
419 S_00B84C_TG_SIZE_EN(1) |
420 S_00B84C_LDS_SIZE(variant->config.lds_size);
421 break;
422 default:
423 unreachable("unsupported shader type");
424 break;
425 }
426
427 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
428 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
429 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
430 S_00B848_DX10_CLAMP(1) |
431 S_00B848_FLOAT_MODE(variant->config.float_mode);
432
433 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
434 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
435
436 void *ptr = device->ws->buffer_map(variant->bo);
437 memcpy(ptr, binary->code, binary->code_size);
438 device->ws->buffer_unmap(variant->bo);
439
440
441 }
442
443 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
444 struct nir_shader *shader,
445 struct radv_pipeline_layout *layout,
446 const union ac_shader_variant_key *key,
447 void** code_out,
448 unsigned *code_size_out,
449 bool dump)
450 {
451 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
452 enum radeon_family chip_family = device->physical_device->rad_info.family;
453 LLVMTargetMachineRef tm;
454 if (!variant)
455 return NULL;
456
457 struct ac_nir_compiler_options options = {0};
458 options.layout = layout;
459 if (key)
460 options.key = *key;
461
462 struct ac_shader_binary binary;
463
464 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
465 options.family = chip_family;
466 options.chip_class = device->physical_device->rad_info.chip_class;
467 options.supports_spill = device->llvm_supports_spill;
468 tm = ac_create_target_machine(chip_family, options.supports_spill);
469 ac_compile_nir_shader(tm, &binary, &variant->config,
470 &variant->info, shader, &options, dump);
471 LLVMDisposeTargetMachine(tm);
472
473 radv_fill_shader_variant(device, variant, &binary, shader->stage);
474
475 if (code_out) {
476 *code_out = binary.code;
477 *code_size_out = binary.code_size;
478 } else
479 free(binary.code);
480 free(binary.config);
481 free(binary.rodata);
482 free(binary.global_symbol_offsets);
483 free(binary.relocs);
484 free(binary.disasm_string);
485 variant->ref_count = 1;
486 return variant;
487 }
488
489 static struct radv_shader_variant *
490 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
491 struct nir_shader *nir,
492 void** code_out,
493 unsigned *code_size_out,
494 bool dump_shader)
495 {
496 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
497 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
498 LLVMTargetMachineRef tm;
499 if (!variant)
500 return NULL;
501
502 struct ac_nir_compiler_options options = {0};
503 struct ac_shader_binary binary;
504 options.family = chip_family;
505 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
506 options.supports_spill = pipeline->device->llvm_supports_spill;
507 tm = ac_create_target_machine(chip_family, options.supports_spill);
508 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
509 LLVMDisposeTargetMachine(tm);
510
511 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
512
513 if (code_out) {
514 *code_out = binary.code;
515 *code_size_out = binary.code_size;
516 } else
517 free(binary.code);
518 free(binary.config);
519 free(binary.rodata);
520 free(binary.global_symbol_offsets);
521 free(binary.relocs);
522 free(binary.disasm_string);
523 variant->ref_count = 1;
524 return variant;
525 }
526
527 static struct radv_shader_variant *
528 radv_pipeline_compile(struct radv_pipeline *pipeline,
529 struct radv_pipeline_cache *cache,
530 struct radv_shader_module *module,
531 const char *entrypoint,
532 gl_shader_stage stage,
533 const VkSpecializationInfo *spec_info,
534 struct radv_pipeline_layout *layout,
535 const union ac_shader_variant_key *key)
536 {
537 unsigned char sha1[20];
538 unsigned char gs_copy_sha1[20];
539 struct radv_shader_variant *variant;
540 nir_shader *nir;
541 void *code = NULL;
542 unsigned code_size = 0;
543 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
544
545 if (module->nir)
546 _mesa_sha1_compute(module->nir->info.name,
547 strlen(module->nir->info.name),
548 module->sha1);
549
550 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
551 if (stage == MESA_SHADER_GEOMETRY)
552 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
553 layout, key, 1);
554
555 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
556 cache,
557 sha1);
558
559 if (stage == MESA_SHADER_GEOMETRY) {
560 pipeline->gs_copy_shader =
561 radv_create_shader_variant_from_pipeline_cache(
562 pipeline->device,
563 cache,
564 gs_copy_sha1);
565 }
566
567 if (variant &&
568 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
569 return variant;
570
571 nir = radv_shader_compile_to_nir(pipeline->device,
572 module, entrypoint, stage,
573 spec_info, dump);
574 if (nir == NULL)
575 return NULL;
576
577 if (!variant) {
578 variant = radv_shader_variant_create(pipeline->device, nir,
579 layout, key, &code,
580 &code_size, dump);
581 }
582
583 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
584 void *gs_copy_code = NULL;
585 unsigned gs_copy_code_size = 0;
586 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
587 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
588
589 if (pipeline->gs_copy_shader) {
590 pipeline->gs_copy_shader =
591 radv_pipeline_cache_insert_shader(cache,
592 gs_copy_sha1,
593 pipeline->gs_copy_shader,
594 gs_copy_code,
595 gs_copy_code_size);
596 }
597 }
598 if (!module->nir)
599 ralloc_free(nir);
600
601 if (variant)
602 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
603 code, code_size);
604
605 if (code)
606 free(code);
607 return variant;
608 }
609
610 static union ac_shader_variant_key
611 radv_compute_tes_key(bool as_es, bool export_prim_id)
612 {
613 union ac_shader_variant_key key;
614 memset(&key, 0, sizeof(key));
615 key.tes.as_es = as_es;
616 /* export prim id only happens when no geom shader */
617 if (!as_es)
618 key.tes.export_prim_id = export_prim_id;
619 return key;
620 }
621
622 static union ac_shader_variant_key
623 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
624 {
625 union ac_shader_variant_key key;
626 memset(&key, 0, sizeof(key));
627 key.tcs.primitive_mode = primitive_mode;
628 key.tcs.input_vertices = input_vertices;
629 return key;
630 }
631
632 static void
633 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
634 struct radv_pipeline_cache *cache,
635 struct radv_shader_module *tcs_module,
636 struct radv_shader_module *tes_module,
637 const char *tcs_entrypoint,
638 const char *tes_entrypoint,
639 const VkSpecializationInfo *tcs_spec_info,
640 const VkSpecializationInfo *tes_spec_info,
641 struct radv_pipeline_layout *layout,
642 unsigned input_vertices)
643 {
644 unsigned char tcs_sha1[20], tes_sha1[20];
645 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
646 nir_shader *tes_nir, *tcs_nir;
647 void *tes_code = NULL, *tcs_code = NULL;
648 unsigned tes_code_size = 0, tcs_code_size = 0;
649 union ac_shader_variant_key tes_key;
650 union ac_shader_variant_key tcs_key;
651 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
652
653 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
654 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
655 if (tes_module->nir)
656 _mesa_sha1_compute(tes_module->nir->info.name,
657 strlen(tes_module->nir->info.name),
658 tes_module->sha1);
659 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
660
661 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
662 cache,
663 tes_sha1);
664
665 if (tes_variant) {
666 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
667
668 if (tcs_module->nir)
669 _mesa_sha1_compute(tcs_module->nir->info.name,
670 strlen(tcs_module->nir->info.name),
671 tcs_module->sha1);
672
673 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
674
675 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
676 cache,
677 tcs_sha1);
678 }
679
680 if (tcs_variant && tes_variant) {
681 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
682 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
683 return;
684 }
685
686 tes_nir = radv_shader_compile_to_nir(pipeline->device,
687 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
688 tes_spec_info, dump);
689 if (tes_nir == NULL)
690 return;
691
692 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
693 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
694 tcs_spec_info, dump);
695 if (tcs_nir == NULL)
696 return;
697
698 nir_lower_tes_patch_vertices(tes_nir,
699 tcs_nir->info.tess.tcs_vertices_out);
700
701 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
702 layout, &tes_key, &tes_code,
703 &tes_code_size, dump);
704
705 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
706 if (tcs_module->nir)
707 _mesa_sha1_compute(tcs_module->nir->info.name,
708 strlen(tcs_module->nir->info.name),
709 tcs_module->sha1);
710
711 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
712
713 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
714 layout, &tcs_key, &tcs_code,
715 &tcs_code_size, dump);
716
717 if (!tes_module->nir)
718 ralloc_free(tes_nir);
719
720 if (!tcs_module->nir)
721 ralloc_free(tcs_nir);
722
723 if (tes_variant)
724 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
725 tes_code, tes_code_size);
726
727 if (tcs_variant)
728 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
729 tcs_code, tcs_code_size);
730
731 if (tes_code)
732 free(tes_code);
733 if (tcs_code)
734 free(tcs_code);
735 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
736 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
737 return;
738 }
739
740 static VkResult
741 radv_pipeline_scratch_init(struct radv_device *device,
742 struct radv_pipeline *pipeline)
743 {
744 unsigned scratch_bytes_per_wave = 0;
745 unsigned max_waves = 0;
746 unsigned min_waves = 1;
747
748 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
749 if (pipeline->shaders[i]) {
750 unsigned max_stage_waves = device->scratch_waves;
751
752 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
753 pipeline->shaders[i]->config.scratch_bytes_per_wave);
754
755 max_stage_waves = MIN2(max_stage_waves,
756 4 * device->physical_device->rad_info.num_good_compute_units *
757 (256 / pipeline->shaders[i]->config.num_vgprs));
758 max_waves = MAX2(max_waves, max_stage_waves);
759 }
760 }
761
762 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
763 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
764 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
765 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
766 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
767 }
768
769 if (scratch_bytes_per_wave)
770 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
771
772 if (scratch_bytes_per_wave && max_waves < min_waves) {
773 /* Not really true at this moment, but will be true on first
774 * execution. Avoid having hanging shaders. */
775 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
776 }
777 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
778 pipeline->max_waves = max_waves;
779 return VK_SUCCESS;
780 }
781
782 static uint32_t si_translate_blend_function(VkBlendOp op)
783 {
784 switch (op) {
785 case VK_BLEND_OP_ADD:
786 return V_028780_COMB_DST_PLUS_SRC;
787 case VK_BLEND_OP_SUBTRACT:
788 return V_028780_COMB_SRC_MINUS_DST;
789 case VK_BLEND_OP_REVERSE_SUBTRACT:
790 return V_028780_COMB_DST_MINUS_SRC;
791 case VK_BLEND_OP_MIN:
792 return V_028780_COMB_MIN_DST_SRC;
793 case VK_BLEND_OP_MAX:
794 return V_028780_COMB_MAX_DST_SRC;
795 default:
796 return 0;
797 }
798 }
799
800 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
801 {
802 switch (factor) {
803 case VK_BLEND_FACTOR_ZERO:
804 return V_028780_BLEND_ZERO;
805 case VK_BLEND_FACTOR_ONE:
806 return V_028780_BLEND_ONE;
807 case VK_BLEND_FACTOR_SRC_COLOR:
808 return V_028780_BLEND_SRC_COLOR;
809 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
810 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
811 case VK_BLEND_FACTOR_DST_COLOR:
812 return V_028780_BLEND_DST_COLOR;
813 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
814 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
815 case VK_BLEND_FACTOR_SRC_ALPHA:
816 return V_028780_BLEND_SRC_ALPHA;
817 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
818 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
819 case VK_BLEND_FACTOR_DST_ALPHA:
820 return V_028780_BLEND_DST_ALPHA;
821 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
822 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
823 case VK_BLEND_FACTOR_CONSTANT_COLOR:
824 return V_028780_BLEND_CONSTANT_COLOR;
825 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
826 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
827 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
828 return V_028780_BLEND_CONSTANT_ALPHA;
829 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
830 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
831 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
832 return V_028780_BLEND_SRC_ALPHA_SATURATE;
833 case VK_BLEND_FACTOR_SRC1_COLOR:
834 return V_028780_BLEND_SRC1_COLOR;
835 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
836 return V_028780_BLEND_INV_SRC1_COLOR;
837 case VK_BLEND_FACTOR_SRC1_ALPHA:
838 return V_028780_BLEND_SRC1_ALPHA;
839 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
840 return V_028780_BLEND_INV_SRC1_ALPHA;
841 default:
842 return 0;
843 }
844 }
845
846 static bool is_dual_src(VkBlendFactor factor)
847 {
848 switch (factor) {
849 case VK_BLEND_FACTOR_SRC1_COLOR:
850 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
851 case VK_BLEND_FACTOR_SRC1_ALPHA:
852 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
853 return true;
854 default:
855 return false;
856 }
857 }
858
859 static unsigned si_choose_spi_color_format(VkFormat vk_format,
860 bool blend_enable,
861 bool blend_need_alpha)
862 {
863 const struct vk_format_description *desc = vk_format_description(vk_format);
864 unsigned format, ntype, swap;
865
866 /* Alpha is needed for alpha-to-coverage.
867 * Blending may be with or without alpha.
868 */
869 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
870 unsigned alpha = 0; /* exports alpha, but may not support blending */
871 unsigned blend = 0; /* supports blending, but may not export alpha */
872 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
873
874 format = radv_translate_colorformat(vk_format);
875 ntype = radv_translate_color_numformat(vk_format, desc,
876 vk_format_get_first_non_void_channel(vk_format));
877 swap = radv_translate_colorswap(vk_format, false);
878
879 /* Choose the SPI color formats. These are required values for Stoney/RB+.
880 * Other chips have multiple choices, though they are not necessarily better.
881 */
882 switch (format) {
883 case V_028C70_COLOR_5_6_5:
884 case V_028C70_COLOR_1_5_5_5:
885 case V_028C70_COLOR_5_5_5_1:
886 case V_028C70_COLOR_4_4_4_4:
887 case V_028C70_COLOR_10_11_11:
888 case V_028C70_COLOR_11_11_10:
889 case V_028C70_COLOR_8:
890 case V_028C70_COLOR_8_8:
891 case V_028C70_COLOR_8_8_8_8:
892 case V_028C70_COLOR_10_10_10_2:
893 case V_028C70_COLOR_2_10_10_10:
894 if (ntype == V_028C70_NUMBER_UINT)
895 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
896 else if (ntype == V_028C70_NUMBER_SINT)
897 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
898 else
899 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
900 break;
901
902 case V_028C70_COLOR_16:
903 case V_028C70_COLOR_16_16:
904 case V_028C70_COLOR_16_16_16_16:
905 if (ntype == V_028C70_NUMBER_UNORM ||
906 ntype == V_028C70_NUMBER_SNORM) {
907 /* UNORM16 and SNORM16 don't support blending */
908 if (ntype == V_028C70_NUMBER_UNORM)
909 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
910 else
911 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
912
913 /* Use 32 bits per channel for blending. */
914 if (format == V_028C70_COLOR_16) {
915 if (swap == V_028C70_SWAP_STD) { /* R */
916 blend = V_028714_SPI_SHADER_32_R;
917 blend_alpha = V_028714_SPI_SHADER_32_AR;
918 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
919 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
920 else
921 assert(0);
922 } else if (format == V_028C70_COLOR_16_16) {
923 if (swap == V_028C70_SWAP_STD) { /* RG */
924 blend = V_028714_SPI_SHADER_32_GR;
925 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
926 } else if (swap == V_028C70_SWAP_ALT) /* RA */
927 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
928 else
929 assert(0);
930 } else /* 16_16_16_16 */
931 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
932 } else if (ntype == V_028C70_NUMBER_UINT)
933 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
934 else if (ntype == V_028C70_NUMBER_SINT)
935 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
936 else if (ntype == V_028C70_NUMBER_FLOAT)
937 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
938 else
939 assert(0);
940 break;
941
942 case V_028C70_COLOR_32:
943 if (swap == V_028C70_SWAP_STD) { /* R */
944 blend = normal = V_028714_SPI_SHADER_32_R;
945 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
946 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
947 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
948 else
949 assert(0);
950 break;
951
952 case V_028C70_COLOR_32_32:
953 if (swap == V_028C70_SWAP_STD) { /* RG */
954 blend = normal = V_028714_SPI_SHADER_32_GR;
955 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
956 } else if (swap == V_028C70_SWAP_ALT) /* RA */
957 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
958 else
959 assert(0);
960 break;
961
962 case V_028C70_COLOR_32_32_32_32:
963 case V_028C70_COLOR_8_24:
964 case V_028C70_COLOR_24_8:
965 case V_028C70_COLOR_X24_8_32_FLOAT:
966 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
967 break;
968
969 default:
970 unreachable("unhandled blend format");
971 }
972
973 if (blend_enable && blend_need_alpha)
974 return blend_alpha;
975 else if(blend_need_alpha)
976 return alpha;
977 else if(blend_enable)
978 return blend;
979 else
980 return normal;
981 }
982
983 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
984 {
985 unsigned i, cb_shader_mask = 0;
986
987 for (i = 0; i < 8; i++) {
988 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
989 case V_028714_SPI_SHADER_ZERO:
990 break;
991 case V_028714_SPI_SHADER_32_R:
992 cb_shader_mask |= 0x1 << (i * 4);
993 break;
994 case V_028714_SPI_SHADER_32_GR:
995 cb_shader_mask |= 0x3 << (i * 4);
996 break;
997 case V_028714_SPI_SHADER_32_AR:
998 cb_shader_mask |= 0x9 << (i * 4);
999 break;
1000 case V_028714_SPI_SHADER_FP16_ABGR:
1001 case V_028714_SPI_SHADER_UNORM16_ABGR:
1002 case V_028714_SPI_SHADER_SNORM16_ABGR:
1003 case V_028714_SPI_SHADER_UINT16_ABGR:
1004 case V_028714_SPI_SHADER_SINT16_ABGR:
1005 case V_028714_SPI_SHADER_32_ABGR:
1006 cb_shader_mask |= 0xf << (i * 4);
1007 break;
1008 default:
1009 assert(0);
1010 }
1011 }
1012 return cb_shader_mask;
1013 }
1014
1015 static void
1016 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
1017 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1018 uint32_t blend_enable,
1019 uint32_t blend_need_alpha,
1020 bool single_cb_enable,
1021 bool blend_mrt0_is_dual_src)
1022 {
1023 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1024 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1025 struct radv_blend_state *blend = &pipeline->graphics.blend;
1026 unsigned col_format = 0;
1027
1028 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
1029 struct radv_render_pass_attachment *attachment;
1030 unsigned cf;
1031
1032 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1033
1034 cf = si_choose_spi_color_format(attachment->format,
1035 blend_enable & (1 << i),
1036 blend_need_alpha & (1 << i));
1037
1038 col_format |= cf << (4 * i);
1039 }
1040
1041 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
1042
1043 if (blend_mrt0_is_dual_src)
1044 col_format |= (col_format & 0xf) << 4;
1045 blend->spi_shader_col_format = col_format;
1046 }
1047
1048 static bool
1049 format_is_int8(VkFormat format)
1050 {
1051 const struct vk_format_description *desc = vk_format_description(format);
1052 int channel = vk_format_get_first_non_void_channel(format);
1053
1054 return channel >= 0 && desc->channel[channel].pure_integer &&
1055 desc->channel[channel].size == 8;
1056 }
1057
1058 unsigned radv_format_meta_fs_key(VkFormat format)
1059 {
1060 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
1061 bool is_int8 = format_is_int8(format);
1062
1063 return col_format + (is_int8 ? 3 : 0);
1064 }
1065
1066 static unsigned
1067 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1068 {
1069 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1070 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1071 unsigned is_int8 = 0;
1072
1073 for (unsigned i = 0; i < subpass->color_count; ++i) {
1074 struct radv_render_pass_attachment *attachment;
1075
1076 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1077
1078 if (format_is_int8(attachment->format))
1079 is_int8 |= 1 << i;
1080 }
1081
1082 return is_int8;
1083 }
1084
1085 static void
1086 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
1087 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1088 const struct radv_graphics_pipeline_create_info *extra)
1089 {
1090 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
1091 struct radv_blend_state *blend = &pipeline->graphics.blend;
1092 unsigned mode = V_028808_CB_NORMAL;
1093 uint32_t blend_enable = 0, blend_need_alpha = 0;
1094 bool blend_mrt0_is_dual_src = false;
1095 int i;
1096 bool single_cb_enable = false;
1097
1098 if (!vkblend)
1099 return;
1100
1101 if (extra && extra->custom_blend_mode) {
1102 single_cb_enable = true;
1103 mode = extra->custom_blend_mode;
1104 }
1105 blend->cb_color_control = 0;
1106 if (vkblend->logicOpEnable)
1107 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
1108 else
1109 blend->cb_color_control |= S_028808_ROP3(0xcc);
1110
1111 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1112 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1113 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1114 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1115
1116 blend->cb_target_mask = 0;
1117 for (i = 0; i < vkblend->attachmentCount; i++) {
1118 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
1119 unsigned blend_cntl = 0;
1120 VkBlendOp eqRGB = att->colorBlendOp;
1121 VkBlendFactor srcRGB = att->srcColorBlendFactor;
1122 VkBlendFactor dstRGB = att->dstColorBlendFactor;
1123 VkBlendOp eqA = att->alphaBlendOp;
1124 VkBlendFactor srcA = att->srcAlphaBlendFactor;
1125 VkBlendFactor dstA = att->dstAlphaBlendFactor;
1126
1127 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1128
1129 if (!att->colorWriteMask)
1130 continue;
1131
1132 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
1133 if (!att->blendEnable) {
1134 blend->cb_blend_control[i] = blend_cntl;
1135 continue;
1136 }
1137
1138 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
1139 if (i == 0)
1140 blend_mrt0_is_dual_src = true;
1141
1142 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
1143 srcRGB = VK_BLEND_FACTOR_ONE;
1144 dstRGB = VK_BLEND_FACTOR_ONE;
1145 }
1146 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
1147 srcA = VK_BLEND_FACTOR_ONE;
1148 dstA = VK_BLEND_FACTOR_ONE;
1149 }
1150
1151 blend_cntl |= S_028780_ENABLE(1);
1152
1153 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1154 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1155 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1156 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1157 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1158 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1159 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1160 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1161 }
1162 blend->cb_blend_control[i] = blend_cntl;
1163
1164 blend_enable |= 1 << i;
1165
1166 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1167 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1168 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1169 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1170 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1171 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1172 blend_need_alpha |= 1 << i;
1173 }
1174 for (i = vkblend->attachmentCount; i < 8; i++)
1175 blend->cb_blend_control[i] = 0;
1176
1177 if (blend->cb_target_mask)
1178 blend->cb_color_control |= S_028808_MODE(mode);
1179 else
1180 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1181
1182 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1183 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1184 }
1185
1186 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1187 {
1188 switch (op) {
1189 case VK_STENCIL_OP_KEEP:
1190 return V_02842C_STENCIL_KEEP;
1191 case VK_STENCIL_OP_ZERO:
1192 return V_02842C_STENCIL_ZERO;
1193 case VK_STENCIL_OP_REPLACE:
1194 return V_02842C_STENCIL_REPLACE_TEST;
1195 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1196 return V_02842C_STENCIL_ADD_CLAMP;
1197 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1198 return V_02842C_STENCIL_SUB_CLAMP;
1199 case VK_STENCIL_OP_INVERT:
1200 return V_02842C_STENCIL_INVERT;
1201 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1202 return V_02842C_STENCIL_ADD_WRAP;
1203 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1204 return V_02842C_STENCIL_SUB_WRAP;
1205 default:
1206 return 0;
1207 }
1208 }
1209 static void
1210 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1211 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1212 const struct radv_graphics_pipeline_create_info *extra)
1213 {
1214 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1215 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1216
1217 memset(ds, 0, sizeof(*ds));
1218 if (!vkds)
1219 return;
1220 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1221 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1222 S_028800_ZFUNC(vkds->depthCompareOp) |
1223 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1224
1225 if (vkds->stencilTestEnable) {
1226 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1227 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1228 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1229 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1230 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1231
1232 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1233 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1234 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1235 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1236 }
1237
1238 if (extra) {
1239
1240 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1241 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1242
1243 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1244 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1245 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1246 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1247 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1248 }
1249 }
1250
1251 static uint32_t si_translate_fill(VkPolygonMode func)
1252 {
1253 switch(func) {
1254 case VK_POLYGON_MODE_FILL:
1255 return V_028814_X_DRAW_TRIANGLES;
1256 case VK_POLYGON_MODE_LINE:
1257 return V_028814_X_DRAW_LINES;
1258 case VK_POLYGON_MODE_POINT:
1259 return V_028814_X_DRAW_POINTS;
1260 default:
1261 assert(0);
1262 return V_028814_X_DRAW_POINTS;
1263 }
1264 }
1265 static void
1266 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1267 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1268 {
1269 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1270 struct radv_raster_state *raster = &pipeline->graphics.raster;
1271
1272 memset(raster, 0, sizeof(*raster));
1273
1274 raster->spi_interp_control =
1275 S_0286D4_FLAT_SHADE_ENA(1) |
1276 S_0286D4_PNT_SPRITE_ENA(1) |
1277 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1278 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1279 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1280 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1281 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1282
1283
1284 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1285 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1286 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1287 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1288 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1289 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1290
1291 raster->pa_su_vtx_cntl =
1292 S_028BE4_PIX_CENTER(1) | // TODO verify
1293 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1294 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1295
1296 raster->pa_su_sc_mode_cntl =
1297 S_028814_FACE(vkraster->frontFace) |
1298 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1299 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1300 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1301 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1302 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1303 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1304 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1305 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1306
1307 }
1308
1309 static void
1310 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1311 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1312 {
1313 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1314 struct radv_blend_state *blend = &pipeline->graphics.blend;
1315 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1316 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1317 int ps_iter_samples = 1;
1318 uint32_t mask = 0xffff;
1319
1320 if (vkms)
1321 ms->num_samples = vkms->rasterizationSamples;
1322 else
1323 ms->num_samples = 1;
1324
1325 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1326 ps_iter_samples = ms->num_samples;
1327 }
1328
1329 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1330 ms->pa_sc_aa_config = 0;
1331 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1332 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1333 ms->pa_sc_mode_cntl_1 =
1334 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1335 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1336 /* always 1: */
1337 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1338 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1339 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1340 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1341 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1342 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1343 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1344
1345 if (ms->num_samples > 1) {
1346 unsigned log_samples = util_logbase2(ms->num_samples);
1347 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1348 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1349 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1350 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1351 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1352 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1353 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1354 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1355 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1356 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1357 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1358 }
1359
1360 if (vkms) {
1361 if (vkms->alphaToCoverageEnable)
1362 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1363
1364 if (vkms->pSampleMask)
1365 mask = vkms->pSampleMask[0] & 0xffff;
1366 }
1367
1368 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1369 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1370 }
1371
1372 static bool
1373 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1374 {
1375 switch (topology) {
1376 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1377 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1378 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1379 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1380 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1381 return false;
1382 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1383 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1384 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1385 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1386 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1387 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1388 return true;
1389 default:
1390 unreachable("unhandled primitive type");
1391 }
1392 }
1393
1394 static uint32_t
1395 si_translate_prim(enum VkPrimitiveTopology topology)
1396 {
1397 switch (topology) {
1398 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1399 return V_008958_DI_PT_POINTLIST;
1400 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1401 return V_008958_DI_PT_LINELIST;
1402 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1403 return V_008958_DI_PT_LINESTRIP;
1404 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1405 return V_008958_DI_PT_TRILIST;
1406 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1407 return V_008958_DI_PT_TRISTRIP;
1408 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1409 return V_008958_DI_PT_TRIFAN;
1410 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1411 return V_008958_DI_PT_LINELIST_ADJ;
1412 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1413 return V_008958_DI_PT_LINESTRIP_ADJ;
1414 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1415 return V_008958_DI_PT_TRILIST_ADJ;
1416 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1417 return V_008958_DI_PT_TRISTRIP_ADJ;
1418 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1419 return V_008958_DI_PT_PATCH;
1420 default:
1421 assert(0);
1422 return 0;
1423 }
1424 }
1425
1426 static uint32_t
1427 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1428 {
1429 switch (gl_prim) {
1430 case 0: /* GL_POINTS */
1431 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1432 case 1: /* GL_LINES */
1433 case 3: /* GL_LINE_STRIP */
1434 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1435 case 0x8E7A: /* GL_ISOLINES */
1436 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1437
1438 case 4: /* GL_TRIANGLES */
1439 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1440 case 5: /* GL_TRIANGLE_STRIP */
1441 case 7: /* GL_QUADS */
1442 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1443 default:
1444 assert(0);
1445 return 0;
1446 }
1447 }
1448
1449 static uint32_t
1450 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1451 {
1452 switch (topology) {
1453 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1454 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1455 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1456 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1457 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1458 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1459 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1460 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1461 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1462 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1463 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1464 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1465 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1466 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1467 default:
1468 assert(0);
1469 return 0;
1470 }
1471 }
1472
1473 static unsigned si_map_swizzle(unsigned swizzle)
1474 {
1475 switch (swizzle) {
1476 case VK_SWIZZLE_Y:
1477 return V_008F0C_SQ_SEL_Y;
1478 case VK_SWIZZLE_Z:
1479 return V_008F0C_SQ_SEL_Z;
1480 case VK_SWIZZLE_W:
1481 return V_008F0C_SQ_SEL_W;
1482 case VK_SWIZZLE_0:
1483 return V_008F0C_SQ_SEL_0;
1484 case VK_SWIZZLE_1:
1485 return V_008F0C_SQ_SEL_1;
1486 default: /* VK_SWIZZLE_X */
1487 return V_008F0C_SQ_SEL_X;
1488 }
1489 }
1490
1491 static void
1492 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1493 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1494 {
1495 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1496 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1497 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1498
1499 pipeline->dynamic_state = default_dynamic_state;
1500
1501 if (pCreateInfo->pDynamicState) {
1502 /* Remove all of the states that are marked as dynamic */
1503 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1504 for (uint32_t s = 0; s < count; s++)
1505 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1506 }
1507
1508 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1509
1510 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1511 *
1512 * pViewportState is [...] NULL if the pipeline
1513 * has rasterization disabled.
1514 */
1515 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1516 assert(pCreateInfo->pViewportState);
1517
1518 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1519 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1520 typed_memcpy(dynamic->viewport.viewports,
1521 pCreateInfo->pViewportState->pViewports,
1522 pCreateInfo->pViewportState->viewportCount);
1523 }
1524
1525 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1526 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1527 typed_memcpy(dynamic->scissor.scissors,
1528 pCreateInfo->pViewportState->pScissors,
1529 pCreateInfo->pViewportState->scissorCount);
1530 }
1531 }
1532
1533 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1534 assert(pCreateInfo->pRasterizationState);
1535 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1536 }
1537
1538 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1539 assert(pCreateInfo->pRasterizationState);
1540 dynamic->depth_bias.bias =
1541 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1542 dynamic->depth_bias.clamp =
1543 pCreateInfo->pRasterizationState->depthBiasClamp;
1544 dynamic->depth_bias.slope =
1545 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1546 }
1547
1548 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1549 *
1550 * pColorBlendState is [...] NULL if the pipeline has rasterization
1551 * disabled or if the subpass of the render pass the pipeline is
1552 * created against does not use any color attachments.
1553 */
1554 bool uses_color_att = false;
1555 for (unsigned i = 0; i < subpass->color_count; ++i) {
1556 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1557 uses_color_att = true;
1558 break;
1559 }
1560 }
1561
1562 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1563 assert(pCreateInfo->pColorBlendState);
1564 typed_memcpy(dynamic->blend_constants,
1565 pCreateInfo->pColorBlendState->blendConstants, 4);
1566 }
1567
1568 /* If there is no depthstencil attachment, then don't read
1569 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1570 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1571 * no need to override the depthstencil defaults in
1572 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1573 *
1574 * Section 9.2 of the Vulkan 1.0.15 spec says:
1575 *
1576 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1577 * disabled or if the subpass of the render pass the pipeline is created
1578 * against does not use a depth/stencil attachment.
1579 */
1580 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1581 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1582 assert(pCreateInfo->pDepthStencilState);
1583
1584 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1585 dynamic->depth_bounds.min =
1586 pCreateInfo->pDepthStencilState->minDepthBounds;
1587 dynamic->depth_bounds.max =
1588 pCreateInfo->pDepthStencilState->maxDepthBounds;
1589 }
1590
1591 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1592 dynamic->stencil_compare_mask.front =
1593 pCreateInfo->pDepthStencilState->front.compareMask;
1594 dynamic->stencil_compare_mask.back =
1595 pCreateInfo->pDepthStencilState->back.compareMask;
1596 }
1597
1598 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1599 dynamic->stencil_write_mask.front =
1600 pCreateInfo->pDepthStencilState->front.writeMask;
1601 dynamic->stencil_write_mask.back =
1602 pCreateInfo->pDepthStencilState->back.writeMask;
1603 }
1604
1605 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1606 dynamic->stencil_reference.front =
1607 pCreateInfo->pDepthStencilState->front.reference;
1608 dynamic->stencil_reference.back =
1609 pCreateInfo->pDepthStencilState->back.reference;
1610 }
1611 }
1612
1613 pipeline->dynamic_state_mask = states;
1614 }
1615
1616 static union ac_shader_variant_key
1617 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1618 {
1619 union ac_shader_variant_key key;
1620 const VkPipelineVertexInputStateCreateInfo *input_state =
1621 pCreateInfo->pVertexInputState;
1622
1623 memset(&key, 0, sizeof(key));
1624 key.vs.instance_rate_inputs = 0;
1625 key.vs.as_es = as_es;
1626 key.vs.as_ls = as_ls;
1627 key.vs.export_prim_id = export_prim_id;
1628
1629 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1630 unsigned binding;
1631 binding = input_state->pVertexAttributeDescriptions[i].binding;
1632 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1633 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1634 }
1635 return key;
1636 }
1637
1638 static void
1639 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1640 {
1641 struct radv_device *device = pipeline->device;
1642 unsigned num_se = device->physical_device->rad_info.max_se;
1643 unsigned wave_size = 64;
1644 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1645 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1646 unsigned alignment = 256 * num_se;
1647 /* The maximum size is 63.999 MB per SE. */
1648 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1649 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1650 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1651 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1652 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1653
1654 /* Calculate the minimum size. */
1655 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1656 wave_size, alignment);
1657 /* These are recommended sizes, not minimum sizes. */
1658 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1659 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1660 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1661 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1662
1663 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1664 esgs_ring_size = align(esgs_ring_size, alignment);
1665 gsvs_ring_size = align(gsvs_ring_size, alignment);
1666
1667 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1668 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1669 }
1670
1671 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1672 unsigned *lds_size)
1673 {
1674 /* SPI barrier management bug:
1675 * Make sure we have at least 4k of LDS in use to avoid the bug.
1676 * It applies to workgroup sizes of more than one wavefront.
1677 */
1678 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1679 device->physical_device->rad_info.family == CHIP_KABINI ||
1680 device->physical_device->rad_info.family == CHIP_MULLINS)
1681 *lds_size = MAX2(*lds_size, 8);
1682 }
1683
1684 static void
1685 calculate_tess_state(struct radv_pipeline *pipeline,
1686 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1687 {
1688 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1689 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1690 unsigned num_tcs_patch_outputs;
1691 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1692 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1693 unsigned lds_size, hardware_lds_size;
1694 unsigned perpatch_output_offset;
1695 unsigned num_patches;
1696 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1697
1698 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1699 * are laid out in LDS. */
1700 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1701
1702 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1703 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1704 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1705
1706 /* Ensure that we only need one wave per SIMD so we don't need to check
1707 * resource usage. Also ensures that the number of tcs in and out
1708 * vertices per threadgroup are at most 256.
1709 */
1710 input_vertex_size = num_tcs_inputs * 16;
1711 output_vertex_size = num_tcs_outputs * 16;
1712
1713 input_patch_size = num_tcs_input_cp * input_vertex_size;
1714
1715 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1716 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1717 /* Ensure that we only need one wave per SIMD so we don't need to check
1718 * resource usage. Also ensures that the number of tcs in and out
1719 * vertices per threadgroup are at most 256.
1720 */
1721 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1722
1723 /* Make sure that the data fits in LDS. This assumes the shaders only
1724 * use LDS for the inputs and outputs.
1725 */
1726 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1727 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1728
1729 /* Make sure the output data fits in the offchip buffer */
1730 num_patches = MIN2(num_patches,
1731 (pipeline->device->tess_offchip_block_dw_size * 4) /
1732 output_patch_size);
1733
1734 /* Not necessary for correctness, but improves performance. The
1735 * specific value is taken from the proprietary driver.
1736 */
1737 num_patches = MIN2(num_patches, 40);
1738
1739 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1740 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1741 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1742 num_patches = MIN2(num_patches, one_wave);
1743 }
1744
1745 output_patch0_offset = input_patch_size * num_patches;
1746 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1747
1748 lds_size = output_patch0_offset + output_patch_size * num_patches;
1749
1750 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1751 assert(lds_size <= 65536);
1752 lds_size = align(lds_size, 512) / 512;
1753 } else {
1754 assert(lds_size <= 32768);
1755 lds_size = align(lds_size, 256) / 256;
1756 }
1757 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1758
1759 tess->lds_size = lds_size;
1760
1761 tess->tcs_in_layout = (input_patch_size / 4) |
1762 ((input_vertex_size / 4) << 13);
1763 tess->tcs_out_layout = (output_patch_size / 4) |
1764 ((output_vertex_size / 4) << 13);
1765 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1766 ((perpatch_output_offset / 16) << 16);
1767 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1768 (num_tcs_output_cp << 9) | num_patches;
1769
1770 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1771 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1772 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1773 tess->num_patches = num_patches;
1774 tess->num_tcs_input_cp = num_tcs_input_cp;
1775
1776 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1777 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1778
1779 switch (tes->info.tes.primitive_mode) {
1780 case GL_TRIANGLES:
1781 type = V_028B6C_TESS_TRIANGLE;
1782 break;
1783 case GL_QUADS:
1784 type = V_028B6C_TESS_QUAD;
1785 break;
1786 case GL_ISOLINES:
1787 type = V_028B6C_TESS_ISOLINE;
1788 break;
1789 }
1790
1791 switch (tes->info.tes.spacing) {
1792 case TESS_SPACING_EQUAL:
1793 partitioning = V_028B6C_PART_INTEGER;
1794 break;
1795 case TESS_SPACING_FRACTIONAL_ODD:
1796 partitioning = V_028B6C_PART_FRAC_ODD;
1797 break;
1798 case TESS_SPACING_FRACTIONAL_EVEN:
1799 partitioning = V_028B6C_PART_FRAC_EVEN;
1800 break;
1801 default:
1802 break;
1803 }
1804
1805 if (tes->info.tes.point_mode)
1806 topology = V_028B6C_OUTPUT_POINT;
1807 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1808 topology = V_028B6C_OUTPUT_LINE;
1809 else if (tes->info.tes.ccw)
1810 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1811 else
1812 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1813
1814 if (pipeline->device->has_distributed_tess) {
1815 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1816 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1817 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1818 else
1819 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1820 } else
1821 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1822
1823 tess->tf_param = S_028B6C_TYPE(type) |
1824 S_028B6C_PARTITIONING(partitioning) |
1825 S_028B6C_TOPOLOGY(topology) |
1826 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1827 }
1828
1829 static const struct radv_prim_vertex_count prim_size_table[] = {
1830 [V_008958_DI_PT_NONE] = {0, 0},
1831 [V_008958_DI_PT_POINTLIST] = {1, 1},
1832 [V_008958_DI_PT_LINELIST] = {2, 2},
1833 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1834 [V_008958_DI_PT_TRILIST] = {3, 3},
1835 [V_008958_DI_PT_TRIFAN] = {3, 1},
1836 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1837 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1838 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1839 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1840 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1841 [V_008958_DI_PT_RECTLIST] = {3, 3},
1842 [V_008958_DI_PT_LINELOOP] = {2, 1},
1843 [V_008958_DI_PT_POLYGON] = {3, 1},
1844 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1845 };
1846
1847 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1848 {
1849 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1850 unsigned cut_mode;
1851
1852 if (gs_max_vert_out <= 128) {
1853 cut_mode = V_028A40_GS_CUT_128;
1854 } else if (gs_max_vert_out <= 256) {
1855 cut_mode = V_028A40_GS_CUT_256;
1856 } else if (gs_max_vert_out <= 512) {
1857 cut_mode = V_028A40_GS_CUT_512;
1858 } else {
1859 assert(gs_max_vert_out <= 1024);
1860 cut_mode = V_028A40_GS_CUT_1024;
1861 }
1862
1863 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1864 S_028A40_CUT_MODE(cut_mode)|
1865 S_028A40_ES_WRITE_OPTIMIZE(1) |
1866 S_028A40_GS_WRITE_OPTIMIZE(1);
1867 }
1868
1869 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1870 {
1871 struct radv_shader_variant *vs;
1872 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1873
1874 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1875
1876 pipeline->graphics.vgt_primitiveid_en = false;
1877 pipeline->graphics.vgt_gs_mode = 0;
1878
1879 if (radv_pipeline_has_gs(pipeline)) {
1880 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
1881 } else if (outinfo->export_prim_id) {
1882 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1883 pipeline->graphics.vgt_primitiveid_en = true;
1884 }
1885 }
1886
1887 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1888 {
1889 struct radv_shader_variant *vs;
1890 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1891
1892 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1893
1894 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1895 clip_dist_mask = outinfo->clip_dist_mask;
1896 cull_dist_mask = outinfo->cull_dist_mask;
1897 total_mask = clip_dist_mask | cull_dist_mask;
1898
1899 bool misc_vec_ena = outinfo->writes_pointsize ||
1900 outinfo->writes_layer ||
1901 outinfo->writes_viewport_index;
1902 pipeline->graphics.pa_cl_vs_out_cntl =
1903 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1904 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1905 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1906 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1907 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1908 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1909 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1910 cull_dist_mask << 8 |
1911 clip_dist_mask;
1912
1913 }
1914
1915 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1916 {
1917 uint32_t ps_input_cntl;
1918 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1919 ps_input_cntl = S_028644_OFFSET(offset);
1920 if (flat_shade)
1921 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1922 } else {
1923 /* The input is a DEFAULT_VAL constant. */
1924 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1925 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1926 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1927 ps_input_cntl = S_028644_OFFSET(0x20) |
1928 S_028644_DEFAULT_VAL(offset);
1929 }
1930 return ps_input_cntl;
1931 }
1932
1933 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1934 {
1935 struct radv_shader_variant *ps, *vs;
1936 struct ac_vs_output_info *outinfo;
1937
1938 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1939 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1940
1941 outinfo = &vs->info.vs.outinfo;
1942
1943 unsigned ps_offset = 0;
1944
1945 if (ps->info.fs.prim_id_input) {
1946 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1947 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1948 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1949 ++ps_offset;
1950 }
1951 }
1952
1953 if (ps->info.fs.layer_input) {
1954 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1955 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1956 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1957 ++ps_offset;
1958 }
1959 }
1960
1961 if (ps->info.fs.has_pcoord) {
1962 unsigned val;
1963 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1964 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1965 ps_offset++;
1966 }
1967
1968 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1969 unsigned vs_offset;
1970 bool flat_shade;
1971 if (!(ps->info.fs.input_mask & (1u << i)))
1972 continue;
1973
1974 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1975 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1976 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1977 ++ps_offset;
1978 continue;
1979 }
1980
1981 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1982
1983 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1984 ++ps_offset;
1985 }
1986
1987 pipeline->graphics.ps_input_cntl_num = ps_offset;
1988 }
1989
1990 VkResult
1991 radv_pipeline_init(struct radv_pipeline *pipeline,
1992 struct radv_device *device,
1993 struct radv_pipeline_cache *cache,
1994 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1995 const struct radv_graphics_pipeline_create_info *extra,
1996 const VkAllocationCallbacks *alloc)
1997 {
1998 struct radv_shader_module fs_m = {0};
1999 VkResult result;
2000
2001 if (alloc == NULL)
2002 alloc = &device->alloc;
2003
2004 pipeline->device = device;
2005 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2006
2007 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2008 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2009 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2010 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2011 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2012 pStages[stage] = &pCreateInfo->pStages[i];
2013 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
2014 }
2015
2016 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2017
2018 if (!modules[MESA_SHADER_FRAGMENT]) {
2019 nir_builder fs_b;
2020 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2021 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2022 fs_m.nir = fs_b.shader;
2023 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2024 }
2025
2026 if (modules[MESA_SHADER_FRAGMENT]) {
2027 union ac_shader_variant_key key;
2028 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
2029 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
2030
2031 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
2032
2033 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2034 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
2035 stage ? stage->pName : "main",
2036 MESA_SHADER_FRAGMENT,
2037 stage ? stage->pSpecializationInfo : NULL,
2038 pipeline->layout, &key);
2039 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
2040 }
2041
2042 if (fs_m.nir)
2043 ralloc_free(fs_m.nir);
2044
2045 if (modules[MESA_SHADER_VERTEX]) {
2046 bool as_es = false;
2047 bool as_ls = false;
2048 bool export_prim_id = false;
2049 if (modules[MESA_SHADER_TESS_CTRL])
2050 as_ls = true;
2051 else if (modules[MESA_SHADER_GEOMETRY])
2052 as_es = true;
2053 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2054 export_prim_id = true;
2055 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
2056
2057 pipeline->shaders[MESA_SHADER_VERTEX] =
2058 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
2059 pStages[MESA_SHADER_VERTEX]->pName,
2060 MESA_SHADER_VERTEX,
2061 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
2062 pipeline->layout, &key);
2063
2064 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
2065 }
2066
2067 if (modules[MESA_SHADER_GEOMETRY]) {
2068 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
2069
2070 pipeline->shaders[MESA_SHADER_GEOMETRY] =
2071 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
2072 pStages[MESA_SHADER_GEOMETRY]->pName,
2073 MESA_SHADER_GEOMETRY,
2074 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
2075 pipeline->layout, &key);
2076
2077 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
2078 }
2079
2080 if (modules[MESA_SHADER_TESS_EVAL]) {
2081 assert(modules[MESA_SHADER_TESS_CTRL]);
2082
2083 radv_tess_pipeline_compile(pipeline,
2084 cache,
2085 modules[MESA_SHADER_TESS_CTRL],
2086 modules[MESA_SHADER_TESS_EVAL],
2087 pStages[MESA_SHADER_TESS_CTRL]->pName,
2088 pStages[MESA_SHADER_TESS_EVAL]->pName,
2089 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
2090 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
2091 pipeline->layout,
2092 pCreateInfo->pTessellationState->patchControlPoints);
2093 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
2094 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
2095 }
2096
2097 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2098 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2099 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2100 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2101 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2102
2103 if (radv_pipeline_has_gs(pipeline)) {
2104 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2105 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2106 } else {
2107 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2108 }
2109 if (extra && extra->use_rectlist) {
2110 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2111 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2112 pipeline->graphics.can_use_guardband = true;
2113 }
2114 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2115 /* prim vertex count will need TESS changes */
2116 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2117
2118 /* Ensure that some export memory is always allocated, for two reasons:
2119 *
2120 * 1) Correctness: The hardware ignores the EXEC mask if no export
2121 * memory is allocated, so KILL and alpha test do not work correctly
2122 * without this.
2123 * 2) Performance: Every shader needs at least a NULL export, even when
2124 * it writes no color/depth output. The NULL export instruction
2125 * stalls without this setting.
2126 *
2127 * Don't add this to CB_SHADER_MASK.
2128 */
2129 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2130 if (!pipeline->graphics.blend.spi_shader_col_format) {
2131 if (!ps->info.fs.writes_z &&
2132 !ps->info.fs.writes_stencil &&
2133 !ps->info.fs.writes_sample_mask)
2134 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2135 }
2136
2137 unsigned z_order;
2138 pipeline->graphics.db_shader_control = 0;
2139 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2140 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2141 else
2142 z_order = V_02880C_LATE_Z;
2143
2144 pipeline->graphics.db_shader_control =
2145 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2146 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2147 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2148 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2149 S_02880C_Z_ORDER(z_order) |
2150 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2151 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2152 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2153
2154 pipeline->graphics.shader_z_format =
2155 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2156 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2157 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2158 V_028710_SPI_SHADER_ZERO;
2159
2160 calculate_vgt_gs_mode(pipeline);
2161 calculate_pa_cl_vs_out_cntl(pipeline);
2162 calculate_ps_inputs(pipeline);
2163
2164 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2165 if (pipeline->shaders[i]) {
2166 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2167 }
2168 }
2169
2170 uint32_t stages = 0;
2171 if (radv_pipeline_has_tess(pipeline)) {
2172 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2173 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2174
2175 if (radv_pipeline_has_gs(pipeline))
2176 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2177 S_028B54_GS_EN(1) |
2178 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2179 else
2180 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2181
2182 } else if (radv_pipeline_has_gs(pipeline))
2183 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2184 S_028B54_GS_EN(1) |
2185 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2186
2187 if (device->physical_device->rad_info.chip_class >= GFX9)
2188 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2189
2190 pipeline->graphics.vgt_shader_stages_en = stages;
2191
2192 if (radv_pipeline_has_gs(pipeline))
2193 calculate_gs_ring_sizes(pipeline);
2194
2195 if (radv_pipeline_has_tess(pipeline)) {
2196 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2197 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2198 pipeline->graphics.prim_vertex_count.incr = 1;
2199 }
2200 calculate_tess_state(pipeline, pCreateInfo);
2201 }
2202
2203 const VkPipelineVertexInputStateCreateInfo *vi_info =
2204 pCreateInfo->pVertexInputState;
2205 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2206 const VkVertexInputAttributeDescription *desc =
2207 &vi_info->pVertexAttributeDescriptions[i];
2208 unsigned loc = desc->location;
2209 const struct vk_format_description *format_desc;
2210 int first_non_void;
2211 uint32_t num_format, data_format;
2212 format_desc = vk_format_description(desc->format);
2213 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2214
2215 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2216 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2217
2218 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2219 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2220 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2221 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2222 S_008F0C_NUM_FORMAT(num_format) |
2223 S_008F0C_DATA_FORMAT(data_format);
2224 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
2225 pipeline->va_offset[loc] = desc->offset;
2226 pipeline->va_binding[loc] = desc->binding;
2227 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
2228 }
2229
2230 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2231 const VkVertexInputBindingDescription *desc =
2232 &vi_info->pVertexBindingDescriptions[i];
2233
2234 pipeline->binding_stride[desc->binding] = desc->stride;
2235 }
2236
2237 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2238 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2239 if (loc->sgpr_idx != -1) {
2240 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2241 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2242 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2243 pipeline->graphics.vtx_emit_num = 3;
2244 else
2245 pipeline->graphics.vtx_emit_num = 2;
2246 }
2247 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2248 radv_dump_pipeline_stats(device, pipeline);
2249 }
2250
2251 result = radv_pipeline_scratch_init(device, pipeline);
2252 return result;
2253 }
2254
2255 VkResult
2256 radv_graphics_pipeline_create(
2257 VkDevice _device,
2258 VkPipelineCache _cache,
2259 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2260 const struct radv_graphics_pipeline_create_info *extra,
2261 const VkAllocationCallbacks *pAllocator,
2262 VkPipeline *pPipeline)
2263 {
2264 RADV_FROM_HANDLE(radv_device, device, _device);
2265 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2266 struct radv_pipeline *pipeline;
2267 VkResult result;
2268
2269 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2270 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2271 if (pipeline == NULL)
2272 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2273
2274 memset(pipeline, 0, sizeof(*pipeline));
2275 result = radv_pipeline_init(pipeline, device, cache,
2276 pCreateInfo, extra, pAllocator);
2277 if (result != VK_SUCCESS) {
2278 radv_pipeline_destroy(device, pipeline, pAllocator);
2279 return result;
2280 }
2281
2282 *pPipeline = radv_pipeline_to_handle(pipeline);
2283
2284 return VK_SUCCESS;
2285 }
2286
2287 VkResult radv_CreateGraphicsPipelines(
2288 VkDevice _device,
2289 VkPipelineCache pipelineCache,
2290 uint32_t count,
2291 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2292 const VkAllocationCallbacks* pAllocator,
2293 VkPipeline* pPipelines)
2294 {
2295 VkResult result = VK_SUCCESS;
2296 unsigned i = 0;
2297
2298 for (; i < count; i++) {
2299 VkResult r;
2300 r = radv_graphics_pipeline_create(_device,
2301 pipelineCache,
2302 &pCreateInfos[i],
2303 NULL, pAllocator, &pPipelines[i]);
2304 if (r != VK_SUCCESS) {
2305 result = r;
2306 pPipelines[i] = VK_NULL_HANDLE;
2307 }
2308 }
2309
2310 return result;
2311 }
2312
2313 static VkResult radv_compute_pipeline_create(
2314 VkDevice _device,
2315 VkPipelineCache _cache,
2316 const VkComputePipelineCreateInfo* pCreateInfo,
2317 const VkAllocationCallbacks* pAllocator,
2318 VkPipeline* pPipeline)
2319 {
2320 RADV_FROM_HANDLE(radv_device, device, _device);
2321 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2322 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2323 struct radv_pipeline *pipeline;
2324 VkResult result;
2325
2326 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2327 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2328 if (pipeline == NULL)
2329 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2330
2331 memset(pipeline, 0, sizeof(*pipeline));
2332 pipeline->device = device;
2333 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2334
2335 pipeline->shaders[MESA_SHADER_COMPUTE] =
2336 radv_pipeline_compile(pipeline, cache, module,
2337 pCreateInfo->stage.pName,
2338 MESA_SHADER_COMPUTE,
2339 pCreateInfo->stage.pSpecializationInfo,
2340 pipeline->layout, NULL);
2341
2342
2343 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2344 result = radv_pipeline_scratch_init(device, pipeline);
2345 if (result != VK_SUCCESS) {
2346 radv_pipeline_destroy(device, pipeline, pAllocator);
2347 return result;
2348 }
2349
2350 *pPipeline = radv_pipeline_to_handle(pipeline);
2351
2352 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2353 radv_dump_pipeline_stats(device, pipeline);
2354 }
2355 return VK_SUCCESS;
2356 }
2357 VkResult radv_CreateComputePipelines(
2358 VkDevice _device,
2359 VkPipelineCache pipelineCache,
2360 uint32_t count,
2361 const VkComputePipelineCreateInfo* pCreateInfos,
2362 const VkAllocationCallbacks* pAllocator,
2363 VkPipeline* pPipelines)
2364 {
2365 VkResult result = VK_SUCCESS;
2366
2367 unsigned i = 0;
2368 for (; i < count; i++) {
2369 VkResult r;
2370 r = radv_compute_pipeline_create(_device, pipelineCache,
2371 &pCreateInfos[i],
2372 pAllocator, &pPipelines[i]);
2373 if (r != VK_SUCCESS) {
2374 result = r;
2375 pPipelines[i] = VK_NULL_HANDLE;
2376 }
2377 }
2378
2379 return result;
2380 }