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radv: Emit a BATCH_BREAK when changing pixel shaders or CB_TARGET_MASK.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include <llvm-c/Core.h>
42 #include <llvm-c/TargetMachine.h>
43
44 #include "sid.h"
45 #include "ac_binary.h"
46 #include "ac_llvm_util.h"
47 #include "ac_nir_to_llvm.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51 #include "ac_shader_util.h"
52 #include "main/menums.h"
53
54 struct radv_blend_state {
55 uint32_t blend_enable_4bit;
56 uint32_t need_src_alpha;
57
58 uint32_t cb_color_control;
59 uint32_t cb_target_mask;
60 uint32_t cb_target_enabled_4bit;
61 uint32_t sx_mrt_blend_opt[8];
62 uint32_t cb_blend_control[8];
63
64 uint32_t spi_shader_col_format;
65 uint32_t cb_shader_mask;
66 uint32_t db_alpha_to_mask;
67
68 uint32_t commutative_4bit;
69
70 bool single_cb_enable;
71 bool mrt0_is_dual_src;
72 };
73
74 struct radv_dsa_order_invariance {
75 /* Whether the final result in Z/S buffers is guaranteed to be
76 * invariant under changes to the order in which fragments arrive.
77 */
78 bool zs;
79
80 /* Whether the set of fragments that pass the combined Z/S test is
81 * guaranteed to be invariant under changes to the order in which
82 * fragments arrive.
83 */
84 bool pass_set;
85 };
86
87 struct radv_tessellation_state {
88 uint32_t ls_hs_config;
89 unsigned num_patches;
90 unsigned lds_size;
91 uint32_t tf_param;
92 };
93
94 static const VkPipelineMultisampleStateCreateInfo *
95 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
96 {
97 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
98 return pCreateInfo->pMultisampleState;
99 return NULL;
100 }
101
102 static const VkPipelineTessellationStateCreateInfo *
103 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
104 {
105 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
106 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
107 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
108 return pCreateInfo->pTessellationState;
109 }
110 }
111 return NULL;
112 }
113
114 static const VkPipelineDepthStencilStateCreateInfo *
115 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
116 {
117 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
118 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
119
120 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
121 subpass->depth_stencil_attachment)
122 return pCreateInfo->pDepthStencilState;
123 return NULL;
124 }
125
126 static const VkPipelineColorBlendStateCreateInfo *
127 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
128 {
129 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
130 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
131
132 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
133 subpass->has_color_att)
134 return pCreateInfo->pColorBlendState;
135 return NULL;
136 }
137
138 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
139 {
140 struct radv_shader_variant *variant = NULL;
141 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
142 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
143 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
144 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
145 else if (pipeline->shaders[MESA_SHADER_VERTEX])
146 variant = pipeline->shaders[MESA_SHADER_VERTEX];
147 else
148 return false;
149 return variant->info.is_ngg;
150 }
151
152 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
153 {
154 if (!radv_pipeline_has_gs(pipeline))
155 return false;
156
157 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
158 * On GFX10, it might be required in rare cases if it's not possible to
159 * enable NGG.
160 */
161 if (radv_pipeline_has_ngg(pipeline))
162 return false;
163
164 assert(pipeline->gs_copy_shader);
165 return true;
166 }
167
168 static void
169 radv_pipeline_destroy(struct radv_device *device,
170 struct radv_pipeline *pipeline,
171 const VkAllocationCallbacks* allocator)
172 {
173 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
174 if (pipeline->shaders[i])
175 radv_shader_variant_destroy(device, pipeline->shaders[i]);
176
177 if (pipeline->gs_copy_shader)
178 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
179
180 if(pipeline->cs.buf)
181 free(pipeline->cs.buf);
182 vk_free2(&device->alloc, allocator, pipeline);
183 }
184
185 void radv_DestroyPipeline(
186 VkDevice _device,
187 VkPipeline _pipeline,
188 const VkAllocationCallbacks* pAllocator)
189 {
190 RADV_FROM_HANDLE(radv_device, device, _device);
191 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
192
193 if (!_pipeline)
194 return;
195
196 radv_pipeline_destroy(device, pipeline, pAllocator);
197 }
198
199 static uint32_t get_hash_flags(struct radv_device *device)
200 {
201 uint32_t hash_flags = 0;
202
203 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
204 hash_flags |= RADV_HASH_SHADER_NO_NGG;
205 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
206 hash_flags |= RADV_HASH_SHADER_SISCHED;
207 if (device->physical_device->cs_wave_size == 32)
208 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
209 if (device->physical_device->ps_wave_size == 32)
210 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
211 if (device->physical_device->ge_wave_size == 32)
212 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
213 if (device->physical_device->use_aco)
214 hash_flags |= RADV_HASH_SHADER_ACO;
215 return hash_flags;
216 }
217
218 static VkResult
219 radv_pipeline_scratch_init(struct radv_device *device,
220 struct radv_pipeline *pipeline)
221 {
222 unsigned scratch_bytes_per_wave = 0;
223 unsigned max_waves = 0;
224 unsigned min_waves = 1;
225
226 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
227 if (pipeline->shaders[i] &&
228 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
229 unsigned max_stage_waves = device->scratch_waves;
230
231 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
232 pipeline->shaders[i]->config.scratch_bytes_per_wave);
233
234 max_stage_waves = MIN2(max_stage_waves,
235 4 * device->physical_device->rad_info.num_good_compute_units *
236 (256 / pipeline->shaders[i]->config.num_vgprs));
237 max_waves = MAX2(max_waves, max_stage_waves);
238 }
239 }
240
241 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
242 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
243 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
244 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
245 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
246 }
247
248 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
249 pipeline->max_waves = max_waves;
250 return VK_SUCCESS;
251 }
252
253 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
254 {
255 switch (op) {
256 case VK_LOGIC_OP_CLEAR:
257 return V_028808_ROP3_CLEAR;
258 case VK_LOGIC_OP_AND:
259 return V_028808_ROP3_AND;
260 case VK_LOGIC_OP_AND_REVERSE:
261 return V_028808_ROP3_AND_REVERSE;
262 case VK_LOGIC_OP_COPY:
263 return V_028808_ROP3_COPY;
264 case VK_LOGIC_OP_AND_INVERTED:
265 return V_028808_ROP3_AND_INVERTED;
266 case VK_LOGIC_OP_NO_OP:
267 return V_028808_ROP3_NO_OP;
268 case VK_LOGIC_OP_XOR:
269 return V_028808_ROP3_XOR;
270 case VK_LOGIC_OP_OR:
271 return V_028808_ROP3_OR;
272 case VK_LOGIC_OP_NOR:
273 return V_028808_ROP3_NOR;
274 case VK_LOGIC_OP_EQUIVALENT:
275 return V_028808_ROP3_EQUIVALENT;
276 case VK_LOGIC_OP_INVERT:
277 return V_028808_ROP3_INVERT;
278 case VK_LOGIC_OP_OR_REVERSE:
279 return V_028808_ROP3_OR_REVERSE;
280 case VK_LOGIC_OP_COPY_INVERTED:
281 return V_028808_ROP3_COPY_INVERTED;
282 case VK_LOGIC_OP_OR_INVERTED:
283 return V_028808_ROP3_OR_INVERTED;
284 case VK_LOGIC_OP_NAND:
285 return V_028808_ROP3_NAND;
286 case VK_LOGIC_OP_SET:
287 return V_028808_ROP3_SET;
288 default:
289 unreachable("Unhandled logic op");
290 }
291 }
292
293
294 static uint32_t si_translate_blend_function(VkBlendOp op)
295 {
296 switch (op) {
297 case VK_BLEND_OP_ADD:
298 return V_028780_COMB_DST_PLUS_SRC;
299 case VK_BLEND_OP_SUBTRACT:
300 return V_028780_COMB_SRC_MINUS_DST;
301 case VK_BLEND_OP_REVERSE_SUBTRACT:
302 return V_028780_COMB_DST_MINUS_SRC;
303 case VK_BLEND_OP_MIN:
304 return V_028780_COMB_MIN_DST_SRC;
305 case VK_BLEND_OP_MAX:
306 return V_028780_COMB_MAX_DST_SRC;
307 default:
308 return 0;
309 }
310 }
311
312 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
313 {
314 switch (factor) {
315 case VK_BLEND_FACTOR_ZERO:
316 return V_028780_BLEND_ZERO;
317 case VK_BLEND_FACTOR_ONE:
318 return V_028780_BLEND_ONE;
319 case VK_BLEND_FACTOR_SRC_COLOR:
320 return V_028780_BLEND_SRC_COLOR;
321 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
322 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
323 case VK_BLEND_FACTOR_DST_COLOR:
324 return V_028780_BLEND_DST_COLOR;
325 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
326 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
327 case VK_BLEND_FACTOR_SRC_ALPHA:
328 return V_028780_BLEND_SRC_ALPHA;
329 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
330 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
331 case VK_BLEND_FACTOR_DST_ALPHA:
332 return V_028780_BLEND_DST_ALPHA;
333 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
334 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
335 case VK_BLEND_FACTOR_CONSTANT_COLOR:
336 return V_028780_BLEND_CONSTANT_COLOR;
337 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
338 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
339 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
340 return V_028780_BLEND_CONSTANT_ALPHA;
341 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
342 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
343 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
344 return V_028780_BLEND_SRC_ALPHA_SATURATE;
345 case VK_BLEND_FACTOR_SRC1_COLOR:
346 return V_028780_BLEND_SRC1_COLOR;
347 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
348 return V_028780_BLEND_INV_SRC1_COLOR;
349 case VK_BLEND_FACTOR_SRC1_ALPHA:
350 return V_028780_BLEND_SRC1_ALPHA;
351 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
352 return V_028780_BLEND_INV_SRC1_ALPHA;
353 default:
354 return 0;
355 }
356 }
357
358 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
359 {
360 switch (op) {
361 case VK_BLEND_OP_ADD:
362 return V_028760_OPT_COMB_ADD;
363 case VK_BLEND_OP_SUBTRACT:
364 return V_028760_OPT_COMB_SUBTRACT;
365 case VK_BLEND_OP_REVERSE_SUBTRACT:
366 return V_028760_OPT_COMB_REVSUBTRACT;
367 case VK_BLEND_OP_MIN:
368 return V_028760_OPT_COMB_MIN;
369 case VK_BLEND_OP_MAX:
370 return V_028760_OPT_COMB_MAX;
371 default:
372 return V_028760_OPT_COMB_BLEND_DISABLED;
373 }
374 }
375
376 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
377 {
378 switch (factor) {
379 case VK_BLEND_FACTOR_ZERO:
380 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
381 case VK_BLEND_FACTOR_ONE:
382 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
383 case VK_BLEND_FACTOR_SRC_COLOR:
384 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
385 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
386 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
387 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
388 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
389 case VK_BLEND_FACTOR_SRC_ALPHA:
390 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
391 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
392 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
393 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
394 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
395 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
396 default:
397 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
398 }
399 }
400
401 /**
402 * Get rid of DST in the blend factors by commuting the operands:
403 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
404 */
405 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
406 unsigned *dst_factor, unsigned expected_dst,
407 unsigned replacement_src)
408 {
409 if (*src_factor == expected_dst &&
410 *dst_factor == VK_BLEND_FACTOR_ZERO) {
411 *src_factor = VK_BLEND_FACTOR_ZERO;
412 *dst_factor = replacement_src;
413
414 /* Commuting the operands requires reversing subtractions. */
415 if (*func == VK_BLEND_OP_SUBTRACT)
416 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
417 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
418 *func = VK_BLEND_OP_SUBTRACT;
419 }
420 }
421
422 static bool si_blend_factor_uses_dst(unsigned factor)
423 {
424 return factor == VK_BLEND_FACTOR_DST_COLOR ||
425 factor == VK_BLEND_FACTOR_DST_ALPHA ||
426 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
427 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
428 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
429 }
430
431 static bool is_dual_src(VkBlendFactor factor)
432 {
433 switch (factor) {
434 case VK_BLEND_FACTOR_SRC1_COLOR:
435 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
436 case VK_BLEND_FACTOR_SRC1_ALPHA:
437 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
438 return true;
439 default:
440 return false;
441 }
442 }
443
444 static unsigned si_choose_spi_color_format(VkFormat vk_format,
445 bool blend_enable,
446 bool blend_need_alpha)
447 {
448 const struct vk_format_description *desc = vk_format_description(vk_format);
449 unsigned format, ntype, swap;
450
451 /* Alpha is needed for alpha-to-coverage.
452 * Blending may be with or without alpha.
453 */
454 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
455 unsigned alpha = 0; /* exports alpha, but may not support blending */
456 unsigned blend = 0; /* supports blending, but may not export alpha */
457 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
458
459 format = radv_translate_colorformat(vk_format);
460 ntype = radv_translate_color_numformat(vk_format, desc,
461 vk_format_get_first_non_void_channel(vk_format));
462 swap = radv_translate_colorswap(vk_format, false);
463
464 /* Choose the SPI color formats. These are required values for Stoney/RB+.
465 * Other chips have multiple choices, though they are not necessarily better.
466 */
467 switch (format) {
468 case V_028C70_COLOR_5_6_5:
469 case V_028C70_COLOR_1_5_5_5:
470 case V_028C70_COLOR_5_5_5_1:
471 case V_028C70_COLOR_4_4_4_4:
472 case V_028C70_COLOR_10_11_11:
473 case V_028C70_COLOR_11_11_10:
474 case V_028C70_COLOR_8:
475 case V_028C70_COLOR_8_8:
476 case V_028C70_COLOR_8_8_8_8:
477 case V_028C70_COLOR_10_10_10_2:
478 case V_028C70_COLOR_2_10_10_10:
479 if (ntype == V_028C70_NUMBER_UINT)
480 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
481 else if (ntype == V_028C70_NUMBER_SINT)
482 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
483 else
484 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
485 break;
486
487 case V_028C70_COLOR_16:
488 case V_028C70_COLOR_16_16:
489 case V_028C70_COLOR_16_16_16_16:
490 if (ntype == V_028C70_NUMBER_UNORM ||
491 ntype == V_028C70_NUMBER_SNORM) {
492 /* UNORM16 and SNORM16 don't support blending */
493 if (ntype == V_028C70_NUMBER_UNORM)
494 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
495 else
496 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
497
498 /* Use 32 bits per channel for blending. */
499 if (format == V_028C70_COLOR_16) {
500 if (swap == V_028C70_SWAP_STD) { /* R */
501 blend = V_028714_SPI_SHADER_32_R;
502 blend_alpha = V_028714_SPI_SHADER_32_AR;
503 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
504 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
505 else
506 assert(0);
507 } else if (format == V_028C70_COLOR_16_16) {
508 if (swap == V_028C70_SWAP_STD) { /* RG */
509 blend = V_028714_SPI_SHADER_32_GR;
510 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
511 } else if (swap == V_028C70_SWAP_ALT) /* RA */
512 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
513 else
514 assert(0);
515 } else /* 16_16_16_16 */
516 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
517 } else if (ntype == V_028C70_NUMBER_UINT)
518 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
519 else if (ntype == V_028C70_NUMBER_SINT)
520 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
521 else if (ntype == V_028C70_NUMBER_FLOAT)
522 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
523 else
524 assert(0);
525 break;
526
527 case V_028C70_COLOR_32:
528 if (swap == V_028C70_SWAP_STD) { /* R */
529 blend = normal = V_028714_SPI_SHADER_32_R;
530 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
531 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
532 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
533 else
534 assert(0);
535 break;
536
537 case V_028C70_COLOR_32_32:
538 if (swap == V_028C70_SWAP_STD) { /* RG */
539 blend = normal = V_028714_SPI_SHADER_32_GR;
540 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
541 } else if (swap == V_028C70_SWAP_ALT) /* RA */
542 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
543 else
544 assert(0);
545 break;
546
547 case V_028C70_COLOR_32_32_32_32:
548 case V_028C70_COLOR_8_24:
549 case V_028C70_COLOR_24_8:
550 case V_028C70_COLOR_X24_8_32_FLOAT:
551 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
552 break;
553
554 default:
555 unreachable("unhandled blend format");
556 }
557
558 if (blend_enable && blend_need_alpha)
559 return blend_alpha;
560 else if(blend_need_alpha)
561 return alpha;
562 else if(blend_enable)
563 return blend;
564 else
565 return normal;
566 }
567
568 static void
569 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
570 const VkGraphicsPipelineCreateInfo *pCreateInfo,
571 struct radv_blend_state *blend)
572 {
573 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
574 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
575 unsigned col_format = 0;
576 unsigned num_targets;
577
578 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
579 unsigned cf;
580
581 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
582 cf = V_028714_SPI_SHADER_ZERO;
583 } else {
584 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
585 bool blend_enable =
586 blend->blend_enable_4bit & (0xfu << (i * 4));
587
588 cf = si_choose_spi_color_format(attachment->format,
589 blend_enable,
590 blend->need_src_alpha & (1 << i));
591 }
592
593 col_format |= cf << (4 * i);
594 }
595
596 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
597 /* When a subpass doesn't have any color attachments, write the
598 * alpha channel of MRT0 when alpha coverage is enabled because
599 * the depth attachment needs it.
600 */
601 col_format |= V_028714_SPI_SHADER_32_AR;
602 }
603
604 /* If the i-th target format is set, all previous target formats must
605 * be non-zero to avoid hangs.
606 */
607 num_targets = (util_last_bit(col_format) + 3) / 4;
608 for (unsigned i = 0; i < num_targets; i++) {
609 if (!(col_format & (0xf << (i * 4)))) {
610 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
611 }
612 }
613
614 /* The output for dual source blending should have the same format as
615 * the first output.
616 */
617 if (blend->mrt0_is_dual_src)
618 col_format |= (col_format & 0xf) << 4;
619
620 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
621 blend->spi_shader_col_format = col_format;
622 }
623
624 static bool
625 format_is_int8(VkFormat format)
626 {
627 const struct vk_format_description *desc = vk_format_description(format);
628 int channel = vk_format_get_first_non_void_channel(format);
629
630 return channel >= 0 && desc->channel[channel].pure_integer &&
631 desc->channel[channel].size == 8;
632 }
633
634 static bool
635 format_is_int10(VkFormat format)
636 {
637 const struct vk_format_description *desc = vk_format_description(format);
638
639 if (desc->nr_channels != 4)
640 return false;
641 for (unsigned i = 0; i < 4; i++) {
642 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
643 return true;
644 }
645 return false;
646 }
647
648 /*
649 * Ordered so that for each i,
650 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
651 */
652 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
653 VK_FORMAT_R32_SFLOAT,
654 VK_FORMAT_R32G32_SFLOAT,
655 VK_FORMAT_R8G8B8A8_UNORM,
656 VK_FORMAT_R16G16B16A16_UNORM,
657 VK_FORMAT_R16G16B16A16_SNORM,
658 VK_FORMAT_R16G16B16A16_UINT,
659 VK_FORMAT_R16G16B16A16_SINT,
660 VK_FORMAT_R32G32B32A32_SFLOAT,
661 VK_FORMAT_R8G8B8A8_UINT,
662 VK_FORMAT_R8G8B8A8_SINT,
663 VK_FORMAT_A2R10G10B10_UINT_PACK32,
664 VK_FORMAT_A2R10G10B10_SINT_PACK32,
665 };
666
667 unsigned radv_format_meta_fs_key(VkFormat format)
668 {
669 unsigned col_format = si_choose_spi_color_format(format, false, false);
670
671 assert(col_format != V_028714_SPI_SHADER_32_AR);
672 if (col_format >= V_028714_SPI_SHADER_32_AR)
673 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
674
675 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
676 bool is_int8 = format_is_int8(format);
677 bool is_int10 = format_is_int10(format);
678
679 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
680 }
681
682 static void
683 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
684 unsigned *is_int8, unsigned *is_int10)
685 {
686 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
687 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
688 *is_int8 = 0;
689 *is_int10 = 0;
690
691 for (unsigned i = 0; i < subpass->color_count; ++i) {
692 struct radv_render_pass_attachment *attachment;
693
694 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
695 continue;
696
697 attachment = pass->attachments + subpass->color_attachments[i].attachment;
698
699 if (format_is_int8(attachment->format))
700 *is_int8 |= 1 << i;
701 if (format_is_int10(attachment->format))
702 *is_int10 |= 1 << i;
703 }
704 }
705
706 static void
707 radv_blend_check_commutativity(struct radv_blend_state *blend,
708 VkBlendOp op, VkBlendFactor src,
709 VkBlendFactor dst, unsigned chanmask)
710 {
711 /* Src factor is allowed when it does not depend on Dst. */
712 static const uint32_t src_allowed =
713 (1u << VK_BLEND_FACTOR_ONE) |
714 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
715 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
716 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
717 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
718 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
719 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
720 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
721 (1u << VK_BLEND_FACTOR_ZERO) |
722 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
723 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
724 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
725 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
726 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
727 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
728
729 if (dst == VK_BLEND_FACTOR_ONE &&
730 (src_allowed & (1u << src))) {
731 /* Addition is commutative, but floating point addition isn't
732 * associative: subtle changes can be introduced via different
733 * rounding. Be conservative, only enable for min and max.
734 */
735 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
736 blend->commutative_4bit |= chanmask;
737 }
738 }
739
740 static struct radv_blend_state
741 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
742 const VkGraphicsPipelineCreateInfo *pCreateInfo,
743 const struct radv_graphics_pipeline_create_info *extra)
744 {
745 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
746 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
747 struct radv_blend_state blend = {0};
748 unsigned mode = V_028808_CB_NORMAL;
749 int i;
750
751 if (extra && extra->custom_blend_mode) {
752 blend.single_cb_enable = true;
753 mode = extra->custom_blend_mode;
754 }
755
756 blend.cb_color_control = 0;
757 if (vkblend) {
758 if (vkblend->logicOpEnable)
759 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
760 else
761 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
762 }
763
764 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
765 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
766 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
767 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
768 S_028B70_OFFSET_ROUND(1);
769
770 if (vkms && vkms->alphaToCoverageEnable) {
771 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
772 blend.need_src_alpha |= 0x1;
773 }
774
775 blend.cb_target_mask = 0;
776 if (vkblend) {
777 for (i = 0; i < vkblend->attachmentCount; i++) {
778 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
779 unsigned blend_cntl = 0;
780 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
781 VkBlendOp eqRGB = att->colorBlendOp;
782 VkBlendFactor srcRGB = att->srcColorBlendFactor;
783 VkBlendFactor dstRGB = att->dstColorBlendFactor;
784 VkBlendOp eqA = att->alphaBlendOp;
785 VkBlendFactor srcA = att->srcAlphaBlendFactor;
786 VkBlendFactor dstA = att->dstAlphaBlendFactor;
787
788 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
789
790 if (!att->colorWriteMask)
791 continue;
792
793 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
794 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
795 if (!att->blendEnable) {
796 blend.cb_blend_control[i] = blend_cntl;
797 continue;
798 }
799
800 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
801 if (i == 0)
802 blend.mrt0_is_dual_src = true;
803
804 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
805 srcRGB = VK_BLEND_FACTOR_ONE;
806 dstRGB = VK_BLEND_FACTOR_ONE;
807 }
808 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
809 srcA = VK_BLEND_FACTOR_ONE;
810 dstA = VK_BLEND_FACTOR_ONE;
811 }
812
813 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
814 0x7 << (4 * i));
815 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
816 0x8 << (4 * i));
817
818 /* Blending optimizations for RB+.
819 * These transformations don't change the behavior.
820 *
821 * First, get rid of DST in the blend factors:
822 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
823 */
824 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
825 VK_BLEND_FACTOR_DST_COLOR,
826 VK_BLEND_FACTOR_SRC_COLOR);
827
828 si_blend_remove_dst(&eqA, &srcA, &dstA,
829 VK_BLEND_FACTOR_DST_COLOR,
830 VK_BLEND_FACTOR_SRC_COLOR);
831
832 si_blend_remove_dst(&eqA, &srcA, &dstA,
833 VK_BLEND_FACTOR_DST_ALPHA,
834 VK_BLEND_FACTOR_SRC_ALPHA);
835
836 /* Look up the ideal settings from tables. */
837 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
838 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
839 srcA_opt = si_translate_blend_opt_factor(srcA, true);
840 dstA_opt = si_translate_blend_opt_factor(dstA, true);
841
842 /* Handle interdependencies. */
843 if (si_blend_factor_uses_dst(srcRGB))
844 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
845 if (si_blend_factor_uses_dst(srcA))
846 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
847
848 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
849 (dstRGB == VK_BLEND_FACTOR_ZERO ||
850 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
851 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
852 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
853
854 /* Set the final value. */
855 blend.sx_mrt_blend_opt[i] =
856 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
857 S_028760_COLOR_DST_OPT(dstRGB_opt) |
858 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
859 S_028760_ALPHA_SRC_OPT(srcA_opt) |
860 S_028760_ALPHA_DST_OPT(dstA_opt) |
861 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
862 blend_cntl |= S_028780_ENABLE(1);
863
864 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
865 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
866 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
867 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
868 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
869 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
870 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
871 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
872 }
873 blend.cb_blend_control[i] = blend_cntl;
874
875 blend.blend_enable_4bit |= 0xfu << (i * 4);
876
877 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
878 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
879 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
880 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
881 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
882 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
883 blend.need_src_alpha |= 1 << i;
884 }
885 for (i = vkblend->attachmentCount; i < 8; i++) {
886 blend.cb_blend_control[i] = 0;
887 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
888 }
889 }
890
891 if (pipeline->device->physical_device->rad_info.has_rbplus) {
892 /* Disable RB+ blend optimizations for dual source blending. */
893 if (blend.mrt0_is_dual_src) {
894 for (i = 0; i < 8; i++) {
895 blend.sx_mrt_blend_opt[i] =
896 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
897 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
898 }
899 }
900
901 /* RB+ doesn't work with dual source blending, logic op and
902 * RESOLVE.
903 */
904 if (blend.mrt0_is_dual_src ||
905 (vkblend && vkblend->logicOpEnable) ||
906 mode == V_028808_CB_RESOLVE)
907 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
908 }
909
910 if (blend.cb_target_mask)
911 blend.cb_color_control |= S_028808_MODE(mode);
912 else
913 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
914
915 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
916 return blend;
917 }
918
919 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
920 {
921 switch (op) {
922 case VK_STENCIL_OP_KEEP:
923 return V_02842C_STENCIL_KEEP;
924 case VK_STENCIL_OP_ZERO:
925 return V_02842C_STENCIL_ZERO;
926 case VK_STENCIL_OP_REPLACE:
927 return V_02842C_STENCIL_REPLACE_TEST;
928 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
929 return V_02842C_STENCIL_ADD_CLAMP;
930 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
931 return V_02842C_STENCIL_SUB_CLAMP;
932 case VK_STENCIL_OP_INVERT:
933 return V_02842C_STENCIL_INVERT;
934 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
935 return V_02842C_STENCIL_ADD_WRAP;
936 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
937 return V_02842C_STENCIL_SUB_WRAP;
938 default:
939 return 0;
940 }
941 }
942
943 static uint32_t si_translate_fill(VkPolygonMode func)
944 {
945 switch(func) {
946 case VK_POLYGON_MODE_FILL:
947 return V_028814_X_DRAW_TRIANGLES;
948 case VK_POLYGON_MODE_LINE:
949 return V_028814_X_DRAW_LINES;
950 case VK_POLYGON_MODE_POINT:
951 return V_028814_X_DRAW_POINTS;
952 default:
953 assert(0);
954 return V_028814_X_DRAW_POINTS;
955 }
956 }
957
958 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
959 {
960 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
961 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
962 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
963 uint32_t ps_iter_samples = 1;
964 uint32_t num_samples;
965
966 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
967 *
968 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
969 * subpass uses color attachments, totalSamples is the number of
970 * samples of the color attachments. Otherwise, totalSamples is the
971 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
972 * specified at pipeline creation time."
973 */
974 if (subpass->has_color_att) {
975 num_samples = subpass->color_sample_count;
976 } else {
977 num_samples = vkms->rasterizationSamples;
978 }
979
980 if (vkms->sampleShadingEnable) {
981 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
982 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
983 }
984 return ps_iter_samples;
985 }
986
987 static bool
988 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
989 {
990 return pCreateInfo->depthTestEnable &&
991 pCreateInfo->depthWriteEnable &&
992 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
993 }
994
995 static bool
996 radv_writes_stencil(const VkStencilOpState *state)
997 {
998 return state->writeMask &&
999 (state->failOp != VK_STENCIL_OP_KEEP ||
1000 state->passOp != VK_STENCIL_OP_KEEP ||
1001 state->depthFailOp != VK_STENCIL_OP_KEEP);
1002 }
1003
1004 static bool
1005 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
1006 {
1007 return pCreateInfo->stencilTestEnable &&
1008 (radv_writes_stencil(&pCreateInfo->front) ||
1009 radv_writes_stencil(&pCreateInfo->back));
1010 }
1011
1012 static bool
1013 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
1014 {
1015 return radv_is_depth_write_enabled(pCreateInfo) ||
1016 radv_is_stencil_write_enabled(pCreateInfo);
1017 }
1018
1019 static bool
1020 radv_order_invariant_stencil_op(VkStencilOp op)
1021 {
1022 /* REPLACE is normally order invariant, except when the stencil
1023 * reference value is written by the fragment shader. Tracking this
1024 * interaction does not seem worth the effort, so be conservative.
1025 */
1026 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
1027 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
1028 op != VK_STENCIL_OP_REPLACE;
1029 }
1030
1031 static bool
1032 radv_order_invariant_stencil_state(const VkStencilOpState *state)
1033 {
1034 /* Compute whether, assuming Z writes are disabled, this stencil state
1035 * is order invariant in the sense that the set of passing fragments as
1036 * well as the final stencil buffer result does not depend on the order
1037 * of fragments.
1038 */
1039 return !state->writeMask ||
1040 /* The following assumes that Z writes are disabled. */
1041 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
1042 radv_order_invariant_stencil_op(state->passOp) &&
1043 radv_order_invariant_stencil_op(state->depthFailOp)) ||
1044 (state->compareOp == VK_COMPARE_OP_NEVER &&
1045 radv_order_invariant_stencil_op(state->failOp));
1046 }
1047
1048 static bool
1049 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
1050 struct radv_blend_state *blend,
1051 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1052 {
1053 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1054 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1055 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
1056 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
1057 unsigned colormask = blend->cb_target_enabled_4bit;
1058
1059 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1060 return false;
1061
1062 /* Be conservative if a logic operation is enabled with color buffers. */
1063 if (colormask && vkblend && vkblend->logicOpEnable)
1064 return false;
1065
1066 /* Default depth/stencil invariance when no attachment is bound. */
1067 struct radv_dsa_order_invariance dsa_order_invariant = {
1068 .zs = true, .pass_set = true
1069 };
1070
1071 if (vkds) {
1072 struct radv_render_pass_attachment *attachment =
1073 pass->attachments + subpass->depth_stencil_attachment->attachment;
1074 bool has_stencil = vk_format_is_stencil(attachment->format);
1075 struct radv_dsa_order_invariance order_invariance[2];
1076 struct radv_shader_variant *ps =
1077 pipeline->shaders[MESA_SHADER_FRAGMENT];
1078
1079 /* Compute depth/stencil order invariance in order to know if
1080 * it's safe to enable out-of-order.
1081 */
1082 bool zfunc_is_ordered =
1083 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1084 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1085 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1086 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1087 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1088
1089 bool nozwrite_and_order_invariant_stencil =
1090 !radv_is_ds_write_enabled(vkds) ||
1091 (!radv_is_depth_write_enabled(vkds) &&
1092 radv_order_invariant_stencil_state(&vkds->front) &&
1093 radv_order_invariant_stencil_state(&vkds->back));
1094
1095 order_invariance[1].zs =
1096 nozwrite_and_order_invariant_stencil ||
1097 (!radv_is_stencil_write_enabled(vkds) &&
1098 zfunc_is_ordered);
1099 order_invariance[0].zs =
1100 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1101
1102 order_invariance[1].pass_set =
1103 nozwrite_and_order_invariant_stencil ||
1104 (!radv_is_stencil_write_enabled(vkds) &&
1105 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1106 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1107 order_invariance[0].pass_set =
1108 !radv_is_depth_write_enabled(vkds) ||
1109 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1110 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1111
1112 dsa_order_invariant = order_invariance[has_stencil];
1113 if (!dsa_order_invariant.zs)
1114 return false;
1115
1116 /* The set of PS invocations is always order invariant,
1117 * except when early Z/S tests are requested.
1118 */
1119 if (ps &&
1120 ps->info.ps.writes_memory &&
1121 ps->info.ps.early_fragment_test &&
1122 !dsa_order_invariant.pass_set)
1123 return false;
1124
1125 /* Determine if out-of-order rasterization should be disabled
1126 * when occlusion queries are used.
1127 */
1128 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1129 !dsa_order_invariant.pass_set;
1130 }
1131
1132 /* No color buffers are enabled for writing. */
1133 if (!colormask)
1134 return true;
1135
1136 unsigned blendmask = colormask & blend->blend_enable_4bit;
1137
1138 if (blendmask) {
1139 /* Only commutative blending. */
1140 if (blendmask & ~blend->commutative_4bit)
1141 return false;
1142
1143 if (!dsa_order_invariant.pass_set)
1144 return false;
1145 }
1146
1147 if (colormask & ~blendmask)
1148 return false;
1149
1150 return true;
1151 }
1152
1153 static void
1154 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1155 struct radv_blend_state *blend,
1156 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1157 {
1158 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1159 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1160 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1161 bool out_of_order_rast = false;
1162 int ps_iter_samples = 1;
1163 uint32_t mask = 0xffff;
1164
1165 if (vkms) {
1166 ms->num_samples = vkms->rasterizationSamples;
1167
1168 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1169 *
1170 * "Sample shading is enabled for a graphics pipeline:
1171 *
1172 * - If the interface of the fragment shader entry point of the
1173 * graphics pipeline includes an input variable decorated
1174 * with SampleId or SamplePosition. In this case
1175 * minSampleShadingFactor takes the value 1.0.
1176 * - Else if the sampleShadingEnable member of the
1177 * VkPipelineMultisampleStateCreateInfo structure specified
1178 * when creating the graphics pipeline is set to VK_TRUE. In
1179 * this case minSampleShadingFactor takes the value of
1180 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1181 *
1182 * Otherwise, sample shading is considered disabled."
1183 */
1184 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1185 ps_iter_samples = ms->num_samples;
1186 } else {
1187 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1188 }
1189 } else {
1190 ms->num_samples = 1;
1191 }
1192
1193 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1194 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1195 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1196 /* Out-of-order rasterization is explicitly enabled by the
1197 * application.
1198 */
1199 out_of_order_rast = true;
1200 } else {
1201 /* Determine if the driver can enable out-of-order
1202 * rasterization internally.
1203 */
1204 out_of_order_rast =
1205 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1206 }
1207
1208 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1209 ms->pa_sc_aa_config = 0;
1210 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1211 S_028804_INCOHERENT_EQAA_READS(1) |
1212 S_028804_INTERPOLATE_COMP_Z(1) |
1213 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1214 ms->pa_sc_mode_cntl_1 =
1215 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1216 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1217 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1218 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1219 /* always 1: */
1220 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1221 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1222 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1223 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1224 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1225 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1226 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1227 S_028A48_VPORT_SCISSOR_ENABLE(1);
1228
1229 if (ms->num_samples > 1) {
1230 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1231 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1232 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1233 unsigned log_samples = util_logbase2(ms->num_samples);
1234 unsigned log_z_samples = util_logbase2(z_samples);
1235 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1236 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1237 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1238 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1239 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1240 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1241 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1242 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1243 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1244 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1245 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1246 if (ps_iter_samples > 1)
1247 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1248 }
1249
1250 if (vkms && vkms->pSampleMask) {
1251 mask = vkms->pSampleMask[0] & 0xffff;
1252 }
1253
1254 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1255 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1256 }
1257
1258 static bool
1259 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1260 {
1261 switch (topology) {
1262 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1263 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1264 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1265 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1266 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1267 return false;
1268 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1269 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1270 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1271 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1272 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1273 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1274 return true;
1275 default:
1276 unreachable("unhandled primitive type");
1277 }
1278 }
1279
1280 static uint32_t
1281 si_translate_prim(enum VkPrimitiveTopology topology)
1282 {
1283 switch (topology) {
1284 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1285 return V_008958_DI_PT_POINTLIST;
1286 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1287 return V_008958_DI_PT_LINELIST;
1288 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1289 return V_008958_DI_PT_LINESTRIP;
1290 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1291 return V_008958_DI_PT_TRILIST;
1292 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1293 return V_008958_DI_PT_TRISTRIP;
1294 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1295 return V_008958_DI_PT_TRIFAN;
1296 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1297 return V_008958_DI_PT_LINELIST_ADJ;
1298 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1299 return V_008958_DI_PT_LINESTRIP_ADJ;
1300 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1301 return V_008958_DI_PT_TRILIST_ADJ;
1302 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1303 return V_008958_DI_PT_TRISTRIP_ADJ;
1304 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1305 return V_008958_DI_PT_PATCH;
1306 default:
1307 assert(0);
1308 return 0;
1309 }
1310 }
1311
1312 static uint32_t
1313 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1314 {
1315 switch (gl_prim) {
1316 case 0: /* GL_POINTS */
1317 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1318 case 1: /* GL_LINES */
1319 case 3: /* GL_LINE_STRIP */
1320 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1321 case 0x8E7A: /* GL_ISOLINES */
1322 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1323
1324 case 4: /* GL_TRIANGLES */
1325 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1326 case 5: /* GL_TRIANGLE_STRIP */
1327 case 7: /* GL_QUADS */
1328 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1329 default:
1330 assert(0);
1331 return 0;
1332 }
1333 }
1334
1335 static uint32_t
1336 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1337 {
1338 switch (topology) {
1339 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1340 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1341 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1342 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1343 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1344 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1345 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1346 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1347 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1348 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1349 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1350 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1351 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1352 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1353 default:
1354 assert(0);
1355 return 0;
1356 }
1357 }
1358
1359 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1360 {
1361 switch(state) {
1362 case VK_DYNAMIC_STATE_VIEWPORT:
1363 return RADV_DYNAMIC_VIEWPORT;
1364 case VK_DYNAMIC_STATE_SCISSOR:
1365 return RADV_DYNAMIC_SCISSOR;
1366 case VK_DYNAMIC_STATE_LINE_WIDTH:
1367 return RADV_DYNAMIC_LINE_WIDTH;
1368 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1369 return RADV_DYNAMIC_DEPTH_BIAS;
1370 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1371 return RADV_DYNAMIC_BLEND_CONSTANTS;
1372 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1373 return RADV_DYNAMIC_DEPTH_BOUNDS;
1374 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1375 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1376 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1377 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1378 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1379 return RADV_DYNAMIC_STENCIL_REFERENCE;
1380 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1381 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1382 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1383 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1384 default:
1385 unreachable("Unhandled dynamic state");
1386 }
1387 }
1388
1389 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1390 {
1391 uint32_t states = RADV_DYNAMIC_ALL;
1392
1393 /* If rasterization is disabled we do not care about any of the dynamic states,
1394 * since they are all rasterization related only. */
1395 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1396 return 0;
1397
1398 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1399 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1400
1401 if (!pCreateInfo->pDepthStencilState ||
1402 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1403 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1404
1405 if (!pCreateInfo->pDepthStencilState ||
1406 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1407 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1408 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1409 RADV_DYNAMIC_STENCIL_REFERENCE);
1410
1411 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1412 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1413
1414 if (!pCreateInfo->pMultisampleState ||
1415 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1416 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1417 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1418
1419 /* TODO: blend constants & line width. */
1420
1421 return states;
1422 }
1423
1424
1425 static void
1426 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1427 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1428 {
1429 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1430 uint32_t states = needed_states;
1431 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1432 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1433
1434 pipeline->dynamic_state = default_dynamic_state;
1435 pipeline->graphics.needed_dynamic_state = needed_states;
1436
1437 if (pCreateInfo->pDynamicState) {
1438 /* Remove all of the states that are marked as dynamic */
1439 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1440 for (uint32_t s = 0; s < count; s++)
1441 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1442 }
1443
1444 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1445
1446 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1447 assert(pCreateInfo->pViewportState);
1448
1449 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1450 if (states & RADV_DYNAMIC_VIEWPORT) {
1451 typed_memcpy(dynamic->viewport.viewports,
1452 pCreateInfo->pViewportState->pViewports,
1453 pCreateInfo->pViewportState->viewportCount);
1454 }
1455 }
1456
1457 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1458 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1459 if (states & RADV_DYNAMIC_SCISSOR) {
1460 typed_memcpy(dynamic->scissor.scissors,
1461 pCreateInfo->pViewportState->pScissors,
1462 pCreateInfo->pViewportState->scissorCount);
1463 }
1464 }
1465
1466 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1467 assert(pCreateInfo->pRasterizationState);
1468 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1469 }
1470
1471 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1472 assert(pCreateInfo->pRasterizationState);
1473 dynamic->depth_bias.bias =
1474 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1475 dynamic->depth_bias.clamp =
1476 pCreateInfo->pRasterizationState->depthBiasClamp;
1477 dynamic->depth_bias.slope =
1478 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1479 }
1480
1481 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1482 *
1483 * pColorBlendState is [...] NULL if the pipeline has rasterization
1484 * disabled or if the subpass of the render pass the pipeline is
1485 * created against does not use any color attachments.
1486 */
1487 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1488 assert(pCreateInfo->pColorBlendState);
1489 typed_memcpy(dynamic->blend_constants,
1490 pCreateInfo->pColorBlendState->blendConstants, 4);
1491 }
1492
1493 /* If there is no depthstencil attachment, then don't read
1494 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1495 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1496 * no need to override the depthstencil defaults in
1497 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1498 *
1499 * Section 9.2 of the Vulkan 1.0.15 spec says:
1500 *
1501 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1502 * disabled or if the subpass of the render pass the pipeline is created
1503 * against does not use a depth/stencil attachment.
1504 */
1505 if (needed_states && subpass->depth_stencil_attachment) {
1506 assert(pCreateInfo->pDepthStencilState);
1507
1508 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1509 dynamic->depth_bounds.min =
1510 pCreateInfo->pDepthStencilState->minDepthBounds;
1511 dynamic->depth_bounds.max =
1512 pCreateInfo->pDepthStencilState->maxDepthBounds;
1513 }
1514
1515 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1516 dynamic->stencil_compare_mask.front =
1517 pCreateInfo->pDepthStencilState->front.compareMask;
1518 dynamic->stencil_compare_mask.back =
1519 pCreateInfo->pDepthStencilState->back.compareMask;
1520 }
1521
1522 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1523 dynamic->stencil_write_mask.front =
1524 pCreateInfo->pDepthStencilState->front.writeMask;
1525 dynamic->stencil_write_mask.back =
1526 pCreateInfo->pDepthStencilState->back.writeMask;
1527 }
1528
1529 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1530 dynamic->stencil_reference.front =
1531 pCreateInfo->pDepthStencilState->front.reference;
1532 dynamic->stencil_reference.back =
1533 pCreateInfo->pDepthStencilState->back.reference;
1534 }
1535 }
1536
1537 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1538 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1539 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1540 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1541 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1542 typed_memcpy(dynamic->discard_rectangle.rectangles,
1543 discard_rectangle_info->pDiscardRectangles,
1544 discard_rectangle_info->discardRectangleCount);
1545 }
1546 }
1547
1548 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1549 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1550 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1551 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1552 /* If sampleLocationsEnable is VK_FALSE, the default sample
1553 * locations are used and the values specified in
1554 * sampleLocationsInfo are ignored.
1555 */
1556 if (sample_location_info->sampleLocationsEnable) {
1557 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1558 &sample_location_info->sampleLocationsInfo;
1559
1560 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1561
1562 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1563 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1564 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1565 typed_memcpy(&dynamic->sample_location.locations[0],
1566 pSampleLocationsInfo->pSampleLocations,
1567 pSampleLocationsInfo->sampleLocationsCount);
1568 }
1569 }
1570
1571 pipeline->dynamic_state.mask = states;
1572 }
1573
1574 static void
1575 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1576 const struct radv_pipeline *pipeline,
1577 nir_shader **nir,
1578 struct radv_shader_info *infos,
1579 struct gfx9_gs_info *out)
1580 {
1581 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1582 struct radv_es_output_info *es_info;
1583 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1584 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1585 else
1586 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1587 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1588 &infos[MESA_SHADER_VERTEX].vs.es_info;
1589
1590 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1591 bool uses_adjacency;
1592 switch(key->topology) {
1593 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1594 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1595 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1596 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1597 uses_adjacency = true;
1598 break;
1599 default:
1600 uses_adjacency = false;
1601 break;
1602 }
1603
1604 /* All these are in dwords: */
1605 /* We can't allow using the whole LDS, because GS waves compete with
1606 * other shader stages for LDS space. */
1607 const unsigned max_lds_size = 8 * 1024;
1608 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1609 unsigned esgs_lds_size;
1610
1611 /* All these are per subgroup: */
1612 const unsigned max_out_prims = 32 * 1024;
1613 const unsigned max_es_verts = 255;
1614 const unsigned ideal_gs_prims = 64;
1615 unsigned max_gs_prims, gs_prims;
1616 unsigned min_es_verts, es_verts, worst_case_es_verts;
1617
1618 if (uses_adjacency || gs_num_invocations > 1)
1619 max_gs_prims = 127 / gs_num_invocations;
1620 else
1621 max_gs_prims = 255;
1622
1623 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1624 * Make sure we don't go over the maximum value.
1625 */
1626 if (gs_info->gs.vertices_out > 0) {
1627 max_gs_prims = MIN2(max_gs_prims,
1628 max_out_prims /
1629 (gs_info->gs.vertices_out * gs_num_invocations));
1630 }
1631 assert(max_gs_prims > 0);
1632
1633 /* If the primitive has adjacency, halve the number of vertices
1634 * that will be reused in multiple primitives.
1635 */
1636 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1637
1638 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1639 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1640
1641 /* Compute ESGS LDS size based on the worst case number of ES vertices
1642 * needed to create the target number of GS prims per subgroup.
1643 */
1644 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1645
1646 /* If total LDS usage is too big, refactor partitions based on ratio
1647 * of ESGS item sizes.
1648 */
1649 if (esgs_lds_size > max_lds_size) {
1650 /* Our target GS Prims Per Subgroup was too large. Calculate
1651 * the maximum number of GS Prims Per Subgroup that will fit
1652 * into LDS, capped by the maximum that the hardware can support.
1653 */
1654 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1655 max_gs_prims);
1656 assert(gs_prims > 0);
1657 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1658 max_es_verts);
1659
1660 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1661 assert(esgs_lds_size <= max_lds_size);
1662 }
1663
1664 /* Now calculate remaining ESGS information. */
1665 if (esgs_lds_size)
1666 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1667 else
1668 es_verts = max_es_verts;
1669
1670 /* Vertices for adjacency primitives are not always reused, so restore
1671 * it for ES_VERTS_PER_SUBGRP.
1672 */
1673 min_es_verts = gs_info->gs.vertices_in;
1674
1675 /* For normal primitives, the VGT only checks if they are past the ES
1676 * verts per subgroup after allocating a full GS primitive and if they
1677 * are, kick off a new subgroup. But if those additional ES verts are
1678 * unique (e.g. not reused) we need to make sure there is enough LDS
1679 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1680 */
1681 es_verts -= min_es_verts - 1;
1682
1683 uint32_t es_verts_per_subgroup = es_verts;
1684 uint32_t gs_prims_per_subgroup = gs_prims;
1685 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1686 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1687 out->lds_size = align(esgs_lds_size, 128) / 128;
1688 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1689 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1690 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1691 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1692 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1693 assert(max_prims_per_subgroup <= max_out_prims);
1694 }
1695
1696 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1697 unsigned min_verts_per_prim, bool use_adjacency)
1698 {
1699 unsigned max_reuse = max_esverts - min_verts_per_prim;
1700 if (use_adjacency)
1701 max_reuse /= 2;
1702 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1703 }
1704
1705 static unsigned
1706 radv_get_num_input_vertices(nir_shader **nir)
1707 {
1708 if (nir[MESA_SHADER_GEOMETRY]) {
1709 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1710
1711 return gs->info.gs.vertices_in;
1712 }
1713
1714 if (nir[MESA_SHADER_TESS_CTRL]) {
1715 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1716
1717 if (tes->info.tess.point_mode)
1718 return 1;
1719 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1720 return 2;
1721 return 3;
1722 }
1723
1724 return 3;
1725 }
1726
1727 static void
1728 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1729 struct radv_pipeline *pipeline,
1730 nir_shader **nir,
1731 struct radv_shader_info *infos,
1732 struct gfx10_ngg_info *ngg)
1733 {
1734 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1735 struct radv_es_output_info *es_info =
1736 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1737 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1738 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1739 unsigned min_verts_per_prim =
1740 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1741 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1742 bool uses_adjacency;
1743 switch(key->topology) {
1744 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1745 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1746 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1747 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1748 uses_adjacency = true;
1749 break;
1750 default:
1751 uses_adjacency = false;
1752 break;
1753 }
1754
1755 /* All these are in dwords: */
1756 /* We can't allow using the whole LDS, because GS waves compete with
1757 * other shader stages for LDS space.
1758 *
1759 * TODO: We should really take the shader's internal LDS use into
1760 * account. The linker will fail if the size is greater than
1761 * 8K dwords.
1762 */
1763 const unsigned max_lds_size = 8 * 1024 - 768;
1764 const unsigned target_lds_size = max_lds_size;
1765 unsigned esvert_lds_size = 0;
1766 unsigned gsprim_lds_size = 0;
1767
1768 /* All these are per subgroup: */
1769 bool max_vert_out_per_gs_instance = false;
1770 unsigned max_esverts_base = 256;
1771 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1772
1773 /* Hardware has the following non-natural restrictions on the value
1774 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1775 * the draw:
1776 * - at most 252 for any line input primitive type
1777 * - at most 251 for any quad input primitive type
1778 * - at most 251 for triangle strips with adjacency (this happens to
1779 * be the natural limit for triangle *lists* with adjacency)
1780 */
1781 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1782
1783 if (gs_type == MESA_SHADER_GEOMETRY) {
1784 unsigned max_out_verts_per_gsprim =
1785 gs_info->gs.vertices_out * gs_num_invocations;
1786
1787 if (max_out_verts_per_gsprim <= 256) {
1788 if (max_out_verts_per_gsprim) {
1789 max_gsprims_base = MIN2(max_gsprims_base,
1790 256 / max_out_verts_per_gsprim);
1791 }
1792 } else {
1793 /* Use special multi-cycling mode in which each GS
1794 * instance gets its own subgroup. Does not work with
1795 * tessellation. */
1796 max_vert_out_per_gs_instance = true;
1797 max_gsprims_base = 1;
1798 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1799 }
1800
1801 esvert_lds_size = es_info->esgs_itemsize / 4;
1802 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1803 } else {
1804 /* VS and TES. */
1805 /* LDS size for passing data from GS to ES. */
1806 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1807 ? &infos[MESA_SHADER_TESS_EVAL].so
1808 : &infos[MESA_SHADER_VERTEX].so;
1809
1810 if (so_info->num_outputs)
1811 esvert_lds_size = 4 * so_info->num_outputs + 1;
1812
1813 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1814 * corresponding to the ES thread of the provoking vertex. All
1815 * ES threads load and export PrimitiveID for their thread.
1816 */
1817 if (!nir[MESA_SHADER_TESS_CTRL] &&
1818 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1819 esvert_lds_size = MAX2(esvert_lds_size, 1);
1820 }
1821
1822 unsigned max_gsprims = max_gsprims_base;
1823 unsigned max_esverts = max_esverts_base;
1824
1825 if (esvert_lds_size)
1826 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1827 if (gsprim_lds_size)
1828 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1829
1830 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1831 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1832 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1833
1834 if (esvert_lds_size || gsprim_lds_size) {
1835 /* Now that we have a rough proportionality between esverts
1836 * and gsprims based on the primitive type, scale both of them
1837 * down simultaneously based on required LDS space.
1838 *
1839 * We could be smarter about this if we knew how much vertex
1840 * reuse to expect.
1841 */
1842 unsigned lds_total = max_esverts * esvert_lds_size +
1843 max_gsprims * gsprim_lds_size;
1844 if (lds_total > target_lds_size) {
1845 max_esverts = max_esverts * target_lds_size / lds_total;
1846 max_gsprims = max_gsprims * target_lds_size / lds_total;
1847
1848 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1849 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1850 min_verts_per_prim, uses_adjacency);
1851 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1852 }
1853 }
1854
1855 /* Round up towards full wave sizes for better ALU utilization. */
1856 if (!max_vert_out_per_gs_instance) {
1857 unsigned orig_max_esverts;
1858 unsigned orig_max_gsprims;
1859 unsigned wavesize;
1860
1861 if (gs_type == MESA_SHADER_GEOMETRY) {
1862 wavesize = gs_info->wave_size;
1863 } else {
1864 wavesize = nir[MESA_SHADER_TESS_CTRL]
1865 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1866 : infos[MESA_SHADER_VERTEX].wave_size;
1867 }
1868
1869 do {
1870 orig_max_esverts = max_esverts;
1871 orig_max_gsprims = max_gsprims;
1872
1873 max_esverts = align(max_esverts, wavesize);
1874 max_esverts = MIN2(max_esverts, max_esverts_base);
1875 if (esvert_lds_size)
1876 max_esverts = MIN2(max_esverts,
1877 (max_lds_size - max_gsprims * gsprim_lds_size) /
1878 esvert_lds_size);
1879 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1880
1881 max_gsprims = align(max_gsprims, wavesize);
1882 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1883 if (gsprim_lds_size)
1884 max_gsprims = MIN2(max_gsprims,
1885 (max_lds_size - max_esverts * esvert_lds_size) /
1886 gsprim_lds_size);
1887 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1888 min_verts_per_prim, uses_adjacency);
1889 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1890 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1891 }
1892
1893 /* Hardware restriction: minimum value of max_esverts */
1894 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1895
1896 unsigned max_out_vertices =
1897 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1898 gs_type == MESA_SHADER_GEOMETRY ?
1899 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1900 max_esverts;
1901 assert(max_out_vertices <= 256);
1902
1903 unsigned prim_amp_factor = 1;
1904 if (gs_type == MESA_SHADER_GEOMETRY) {
1905 /* Number of output primitives per GS input primitive after
1906 * GS instancing. */
1907 prim_amp_factor = gs_info->gs.vertices_out;
1908 }
1909
1910 /* The GE only checks against the maximum number of ES verts after
1911 * allocating a full GS primitive. So we need to ensure that whenever
1912 * this check passes, there is enough space for a full primitive without
1913 * vertex reuse.
1914 */
1915 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1916 ngg->max_gsprims = max_gsprims;
1917 ngg->max_out_verts = max_out_vertices;
1918 ngg->prim_amp_factor = prim_amp_factor;
1919 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1920 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1921 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1922
1923 if (gs_type == MESA_SHADER_GEOMETRY) {
1924 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1925 } else {
1926 ngg->vgt_esgs_ring_itemsize = 1;
1927 }
1928
1929 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1930
1931 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1932 }
1933
1934 static void
1935 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1936 const struct gfx9_gs_info *gs)
1937 {
1938 struct radv_device *device = pipeline->device;
1939 unsigned num_se = device->physical_device->rad_info.max_se;
1940 unsigned wave_size = 64;
1941 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1942 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1943 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1944 */
1945 unsigned gs_vertex_reuse =
1946 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1947 unsigned alignment = 256 * num_se;
1948 /* The maximum size is 63.999 MB per SE. */
1949 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1950 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1951
1952 /* Calculate the minimum size. */
1953 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1954 wave_size, alignment);
1955 /* These are recommended sizes, not minimum sizes. */
1956 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1957 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1958 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1959 gs_info->gs.max_gsvs_emit_size;
1960
1961 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1962 esgs_ring_size = align(esgs_ring_size, alignment);
1963 gsvs_ring_size = align(gsvs_ring_size, alignment);
1964
1965 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1966 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1967
1968 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1969 }
1970
1971 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1972 unsigned *lds_size)
1973 {
1974 /* If tessellation is all offchip and on-chip GS isn't used, this
1975 * workaround is not needed.
1976 */
1977 return;
1978
1979 /* SPI barrier management bug:
1980 * Make sure we have at least 4k of LDS in use to avoid the bug.
1981 * It applies to workgroup sizes of more than one wavefront.
1982 */
1983 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1984 device->physical_device->rad_info.family == CHIP_KABINI)
1985 *lds_size = MAX2(*lds_size, 8);
1986 }
1987
1988 struct radv_shader_variant *
1989 radv_get_shader(struct radv_pipeline *pipeline,
1990 gl_shader_stage stage)
1991 {
1992 if (stage == MESA_SHADER_VERTEX) {
1993 if (pipeline->shaders[MESA_SHADER_VERTEX])
1994 return pipeline->shaders[MESA_SHADER_VERTEX];
1995 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1996 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1997 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1998 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1999 } else if (stage == MESA_SHADER_TESS_EVAL) {
2000 if (!radv_pipeline_has_tess(pipeline))
2001 return NULL;
2002 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
2003 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
2004 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2005 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2006 }
2007 return pipeline->shaders[stage];
2008 }
2009
2010 static struct radv_tessellation_state
2011 calculate_tess_state(struct radv_pipeline *pipeline,
2012 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2013 {
2014 unsigned num_tcs_input_cp;
2015 unsigned num_tcs_output_cp;
2016 unsigned lds_size;
2017 unsigned num_patches;
2018 struct radv_tessellation_state tess = {0};
2019
2020 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
2021 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
2022 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2023
2024 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
2025
2026 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
2027 assert(lds_size <= 65536);
2028 lds_size = align(lds_size, 512) / 512;
2029 } else {
2030 assert(lds_size <= 32768);
2031 lds_size = align(lds_size, 256) / 256;
2032 }
2033 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
2034
2035 tess.lds_size = lds_size;
2036
2037 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
2038 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
2039 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
2040 tess.num_patches = num_patches;
2041
2042 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
2043 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
2044
2045 switch (tes->info.tes.primitive_mode) {
2046 case GL_TRIANGLES:
2047 type = V_028B6C_TESS_TRIANGLE;
2048 break;
2049 case GL_QUADS:
2050 type = V_028B6C_TESS_QUAD;
2051 break;
2052 case GL_ISOLINES:
2053 type = V_028B6C_TESS_ISOLINE;
2054 break;
2055 }
2056
2057 switch (tes->info.tes.spacing) {
2058 case TESS_SPACING_EQUAL:
2059 partitioning = V_028B6C_PART_INTEGER;
2060 break;
2061 case TESS_SPACING_FRACTIONAL_ODD:
2062 partitioning = V_028B6C_PART_FRAC_ODD;
2063 break;
2064 case TESS_SPACING_FRACTIONAL_EVEN:
2065 partitioning = V_028B6C_PART_FRAC_EVEN;
2066 break;
2067 default:
2068 break;
2069 }
2070
2071 bool ccw = tes->info.tes.ccw;
2072 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2073 vk_find_struct_const(pCreateInfo->pTessellationState,
2074 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2075
2076 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2077 ccw = !ccw;
2078
2079 if (tes->info.tes.point_mode)
2080 topology = V_028B6C_OUTPUT_POINT;
2081 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2082 topology = V_028B6C_OUTPUT_LINE;
2083 else if (ccw)
2084 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2085 else
2086 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2087
2088 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2089 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2090 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2091 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2092 else
2093 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2094 } else
2095 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2096
2097 tess.tf_param = S_028B6C_TYPE(type) |
2098 S_028B6C_PARTITIONING(partitioning) |
2099 S_028B6C_TOPOLOGY(topology) |
2100 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2101
2102 return tess;
2103 }
2104
2105 static const struct radv_prim_vertex_count prim_size_table[] = {
2106 [V_008958_DI_PT_NONE] = {0, 0},
2107 [V_008958_DI_PT_POINTLIST] = {1, 1},
2108 [V_008958_DI_PT_LINELIST] = {2, 2},
2109 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2110 [V_008958_DI_PT_TRILIST] = {3, 3},
2111 [V_008958_DI_PT_TRIFAN] = {3, 1},
2112 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2113 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2114 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2115 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2116 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2117 [V_008958_DI_PT_RECTLIST] = {3, 3},
2118 [V_008958_DI_PT_LINELOOP] = {2, 1},
2119 [V_008958_DI_PT_POLYGON] = {3, 1},
2120 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2121 };
2122
2123 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2124 {
2125 if (radv_pipeline_has_gs(pipeline))
2126 if (radv_pipeline_has_ngg(pipeline))
2127 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2128 else
2129 return &pipeline->gs_copy_shader->info.vs.outinfo;
2130 else if (radv_pipeline_has_tess(pipeline))
2131 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2132 else
2133 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2134 }
2135
2136 static void
2137 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2138 {
2139 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2140 int shader_count = 0;
2141
2142 if(shaders[MESA_SHADER_FRAGMENT]) {
2143 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2144 }
2145 if(shaders[MESA_SHADER_GEOMETRY]) {
2146 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2147 }
2148 if(shaders[MESA_SHADER_TESS_EVAL]) {
2149 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2150 }
2151 if(shaders[MESA_SHADER_TESS_CTRL]) {
2152 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2153 }
2154 if(shaders[MESA_SHADER_VERTEX]) {
2155 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2156 }
2157
2158 if (shader_count > 1) {
2159 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2160 unsigned last = ordered_shaders[0]->info.stage;
2161
2162 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2163 ordered_shaders[1]->info.has_transform_feedback_varyings)
2164 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2165
2166 for (int i = 0; i < shader_count; ++i) {
2167 nir_variable_mode mask = 0;
2168
2169 if (ordered_shaders[i]->info.stage != first)
2170 mask = mask | nir_var_shader_in;
2171
2172 if (ordered_shaders[i]->info.stage != last)
2173 mask = mask | nir_var_shader_out;
2174
2175 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2176 radv_optimize_nir(ordered_shaders[i], false, false);
2177 }
2178 }
2179
2180 for (int i = 1; i < shader_count; ++i) {
2181 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2182 ordered_shaders[i - 1]);
2183
2184 if (nir_link_opt_varyings(ordered_shaders[i],
2185 ordered_shaders[i - 1]))
2186 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2187
2188 nir_remove_dead_variables(ordered_shaders[i],
2189 nir_var_shader_out);
2190 nir_remove_dead_variables(ordered_shaders[i - 1],
2191 nir_var_shader_in);
2192
2193 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2194 ordered_shaders[i - 1]);
2195
2196 nir_compact_varyings(ordered_shaders[i],
2197 ordered_shaders[i - 1], true);
2198
2199 if (progress) {
2200 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2201 ac_lower_indirect_derefs(ordered_shaders[i],
2202 pipeline->device->physical_device->rad_info.chip_class);
2203 }
2204 radv_optimize_nir(ordered_shaders[i], false, false);
2205
2206 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2207 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2208 pipeline->device->physical_device->rad_info.chip_class);
2209 }
2210 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2211 }
2212 }
2213 }
2214
2215 static uint32_t
2216 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2217 uint32_t attrib_binding)
2218 {
2219 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2220 const VkVertexInputBindingDescription *input_binding =
2221 &input_state->pVertexBindingDescriptions[i];
2222
2223 if (input_binding->binding == attrib_binding)
2224 return input_binding->stride;
2225 }
2226
2227 return 0;
2228 }
2229
2230 static struct radv_pipeline_key
2231 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2232 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2233 const struct radv_blend_state *blend,
2234 bool has_view_index)
2235 {
2236 const VkPipelineVertexInputStateCreateInfo *input_state =
2237 pCreateInfo->pVertexInputState;
2238 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2239 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2240
2241 struct radv_pipeline_key key;
2242 memset(&key, 0, sizeof(key));
2243
2244 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2245 key.optimisations_disabled = 1;
2246
2247 key.has_multiview_view_index = has_view_index;
2248
2249 uint32_t binding_input_rate = 0;
2250 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2251 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2252 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2253 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2254 binding_input_rate |= 1u << binding;
2255 instance_rate_divisors[binding] = 1;
2256 }
2257 }
2258 if (divisor_state) {
2259 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2260 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2261 divisor_state->pVertexBindingDivisors[i].divisor;
2262 }
2263 }
2264
2265 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2266 const VkVertexInputAttributeDescription *desc =
2267 &input_state->pVertexAttributeDescriptions[i];
2268 const struct vk_format_description *format_desc;
2269 unsigned location = desc->location;
2270 unsigned binding = desc->binding;
2271 unsigned num_format, data_format;
2272 int first_non_void;
2273
2274 if (binding_input_rate & (1u << binding)) {
2275 key.instance_rate_inputs |= 1u << location;
2276 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2277 }
2278
2279 format_desc = vk_format_description(desc->format);
2280 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2281
2282 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2283 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2284
2285 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2286 key.vertex_attribute_bindings[location] = desc->binding;
2287 key.vertex_attribute_offsets[location] = desc->offset;
2288 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2289
2290 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2291 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2292 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2293 uint64_t adjust;
2294 switch(format) {
2295 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2296 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2297 adjust = RADV_ALPHA_ADJUST_SNORM;
2298 break;
2299 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2300 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2301 adjust = RADV_ALPHA_ADJUST_SSCALED;
2302 break;
2303 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2304 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2305 adjust = RADV_ALPHA_ADJUST_SINT;
2306 break;
2307 default:
2308 adjust = 0;
2309 break;
2310 }
2311 key.vertex_alpha_adjust |= adjust << (2 * location);
2312 }
2313
2314 switch (desc->format) {
2315 case VK_FORMAT_B8G8R8A8_UNORM:
2316 case VK_FORMAT_B8G8R8A8_SNORM:
2317 case VK_FORMAT_B8G8R8A8_USCALED:
2318 case VK_FORMAT_B8G8R8A8_SSCALED:
2319 case VK_FORMAT_B8G8R8A8_UINT:
2320 case VK_FORMAT_B8G8R8A8_SINT:
2321 case VK_FORMAT_B8G8R8A8_SRGB:
2322 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2323 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2324 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2325 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2326 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2327 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2328 key.vertex_post_shuffle |= 1 << location;
2329 break;
2330 default:
2331 break;
2332 }
2333 }
2334
2335 const VkPipelineTessellationStateCreateInfo *tess =
2336 radv_pipeline_get_tessellation_state(pCreateInfo);
2337 if (tess)
2338 key.tess_input_vertices = tess->patchControlPoints;
2339
2340 const VkPipelineMultisampleStateCreateInfo *vkms =
2341 radv_pipeline_get_multisample_state(pCreateInfo);
2342 if (vkms && vkms->rasterizationSamples > 1) {
2343 uint32_t num_samples = vkms->rasterizationSamples;
2344 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2345 key.num_samples = num_samples;
2346 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2347 }
2348
2349 key.col_format = blend->spi_shader_col_format;
2350 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2351 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2352
2353 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2354 key.topology = pCreateInfo->pInputAssemblyState->topology;
2355
2356 return key;
2357 }
2358
2359 static bool
2360 radv_nir_stage_uses_xfb(const nir_shader *nir)
2361 {
2362 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2363 bool uses_xfb = !!xfb;
2364
2365 ralloc_free(xfb);
2366 return uses_xfb;
2367 }
2368
2369 static void
2370 radv_fill_shader_keys(struct radv_device *device,
2371 struct radv_shader_variant_key *keys,
2372 const struct radv_pipeline_key *key,
2373 nir_shader **nir)
2374 {
2375 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2376 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2377 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2378 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2379 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2380 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2381 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2382 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2383 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2384 }
2385 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2386
2387 if (nir[MESA_SHADER_TESS_CTRL]) {
2388 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2389 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2390 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2391 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2392
2393 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2394 }
2395
2396 if (nir[MESA_SHADER_GEOMETRY]) {
2397 if (nir[MESA_SHADER_TESS_CTRL])
2398 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2399 else
2400 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2401 }
2402
2403 if (device->physical_device->use_ngg) {
2404 if (nir[MESA_SHADER_TESS_CTRL]) {
2405 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2406 } else {
2407 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2408 }
2409
2410 if (nir[MESA_SHADER_TESS_CTRL] &&
2411 nir[MESA_SHADER_GEOMETRY] &&
2412 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2413 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2414 /* Fallback to the legacy path if tessellation is
2415 * enabled with extreme geometry because
2416 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2417 * might hang.
2418 */
2419 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2420 }
2421
2422 /*
2423 * Disable NGG with geometry shaders. There are a bunch of
2424 * issues still:
2425 * * GS primitives in pipeline statistic queries do not get
2426 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2427 *
2428 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2429 */
2430 if (nir[MESA_SHADER_GEOMETRY]) {
2431 if (nir[MESA_SHADER_TESS_CTRL])
2432 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2433 else
2434 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2435 }
2436
2437 if (!device->physical_device->use_ngg_streamout) {
2438 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2439
2440 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2441 if (nir[i])
2442 last_xfb_stage = i;
2443 }
2444
2445 if (nir[last_xfb_stage] &&
2446 radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
2447 if (nir[MESA_SHADER_TESS_CTRL])
2448 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2449 else
2450 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2451 }
2452 }
2453 }
2454
2455 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2456 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2457
2458 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2459 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2460 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2461 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2462 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2463
2464 if (nir[MESA_SHADER_COMPUTE]) {
2465 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2466 }
2467 }
2468
2469 static uint8_t
2470 radv_get_wave_size(struct radv_device *device,
2471 const VkPipelineShaderStageCreateInfo *pStage,
2472 gl_shader_stage stage,
2473 const struct radv_shader_variant_key *key)
2474 {
2475 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2476 return 64;
2477 else if (stage == MESA_SHADER_COMPUTE) {
2478 if (key->cs.subgroup_size) {
2479 /* Return the required subgroup size if specified. */
2480 return key->cs.subgroup_size;
2481 }
2482 return device->physical_device->cs_wave_size;
2483 }
2484 else if (stage == MESA_SHADER_FRAGMENT)
2485 return device->physical_device->ps_wave_size;
2486 else
2487 return device->physical_device->ge_wave_size;
2488 }
2489
2490 static void
2491 radv_fill_shader_info(struct radv_pipeline *pipeline,
2492 const VkPipelineShaderStageCreateInfo **pStages,
2493 struct radv_shader_variant_key *keys,
2494 struct radv_shader_info *infos,
2495 nir_shader **nir)
2496 {
2497 unsigned active_stages = 0;
2498 unsigned filled_stages = 0;
2499
2500 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2501 if (nir[i])
2502 active_stages |= (1 << i);
2503 }
2504
2505 if (nir[MESA_SHADER_FRAGMENT]) {
2506 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2507 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2508 pipeline->layout,
2509 &keys[MESA_SHADER_FRAGMENT],
2510 &infos[MESA_SHADER_FRAGMENT]);
2511
2512 /* TODO: These are no longer used as keys we should refactor this */
2513 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2514 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2515 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2516 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2517 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2518 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2519 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2520 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2521 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2522 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2523 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2524 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2525
2526 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2527 }
2528
2529 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2530 nir[MESA_SHADER_TESS_CTRL]) {
2531 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2532 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2533 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2534
2535 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2536
2537 for (int i = 0; i < 2; i++) {
2538 radv_nir_shader_info_pass(combined_nir[i],
2539 pipeline->layout, &key,
2540 &infos[MESA_SHADER_TESS_CTRL]);
2541 }
2542
2543 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2544 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2545 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2546 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2547
2548 filled_stages |= (1 << MESA_SHADER_VERTEX);
2549 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2550 }
2551
2552 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2553 nir[MESA_SHADER_GEOMETRY]) {
2554 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2555 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2556
2557 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2558
2559 for (int i = 0; i < 2; i++) {
2560 radv_nir_shader_info_pass(combined_nir[i],
2561 pipeline->layout,
2562 &keys[pre_stage],
2563 &infos[MESA_SHADER_GEOMETRY]);
2564 }
2565
2566 filled_stages |= (1 << pre_stage);
2567 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2568 }
2569
2570 active_stages ^= filled_stages;
2571 while (active_stages) {
2572 int i = u_bit_scan(&active_stages);
2573
2574 if (i == MESA_SHADER_TESS_CTRL) {
2575 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2576 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2577 }
2578
2579 if (i == MESA_SHADER_TESS_EVAL) {
2580 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2581 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2582 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2583 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2584 }
2585
2586 radv_nir_shader_info_init(&infos[i]);
2587 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2588 &keys[i], &infos[i]);
2589 }
2590
2591 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2592 if (nir[i])
2593 infos[i].wave_size =
2594 radv_get_wave_size(pipeline->device, pStages[i],
2595 i, &keys[i]);
2596 }
2597 }
2598
2599 static void
2600 merge_tess_info(struct shader_info *tes_info,
2601 const struct shader_info *tcs_info)
2602 {
2603 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2604 *
2605 * "PointMode. Controls generation of points rather than triangles
2606 * or lines. This functionality defaults to disabled, and is
2607 * enabled if either shader stage includes the execution mode.
2608 *
2609 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2610 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2611 * and OutputVertices, it says:
2612 *
2613 * "One mode must be set in at least one of the tessellation
2614 * shader stages."
2615 *
2616 * So, the fields can be set in either the TCS or TES, but they must
2617 * agree if set in both. Our backend looks at TES, so bitwise-or in
2618 * the values from the TCS.
2619 */
2620 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2621 tes_info->tess.tcs_vertices_out == 0 ||
2622 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2623 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2624
2625 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2626 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2627 tcs_info->tess.spacing == tes_info->tess.spacing);
2628 tes_info->tess.spacing |= tcs_info->tess.spacing;
2629
2630 assert(tcs_info->tess.primitive_mode == 0 ||
2631 tes_info->tess.primitive_mode == 0 ||
2632 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2633 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2634 tes_info->tess.ccw |= tcs_info->tess.ccw;
2635 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2636 }
2637
2638 static
2639 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2640 {
2641 if (!ext)
2642 return;
2643
2644 if (ext->pPipelineCreationFeedback) {
2645 ext->pPipelineCreationFeedback->flags = 0;
2646 ext->pPipelineCreationFeedback->duration = 0;
2647 }
2648
2649 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2650 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2651 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2652 }
2653 }
2654
2655 static
2656 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2657 {
2658 if (!feedback)
2659 return;
2660
2661 feedback->duration -= radv_get_current_time();
2662 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2663 }
2664
2665 static
2666 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2667 {
2668 if (!feedback)
2669 return;
2670
2671 feedback->duration += radv_get_current_time();
2672 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2673 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2674 }
2675
2676 static
2677 bool radv_aco_supported_stage(gl_shader_stage stage, bool has_gs, bool has_ts)
2678 {
2679 return (stage == MESA_SHADER_VERTEX && !has_gs && !has_ts) ||
2680 stage == MESA_SHADER_FRAGMENT ||
2681 stage == MESA_SHADER_COMPUTE;
2682 }
2683
2684 void radv_create_shaders(struct radv_pipeline *pipeline,
2685 struct radv_device *device,
2686 struct radv_pipeline_cache *cache,
2687 const struct radv_pipeline_key *key,
2688 const VkPipelineShaderStageCreateInfo **pStages,
2689 const VkPipelineCreateFlags flags,
2690 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2691 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2692 {
2693 struct radv_shader_module fs_m = {0};
2694 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2695 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2696 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2697 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2698 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2699 unsigned char hash[20], gs_copy_hash[20];
2700 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2701
2702 radv_start_feedback(pipeline_feedback);
2703
2704 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2705 if (pStages[i]) {
2706 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2707 if (modules[i]->nir)
2708 _mesa_sha1_compute(modules[i]->nir->info.name,
2709 strlen(modules[i]->nir->info.name),
2710 modules[i]->sha1);
2711
2712 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2713 }
2714 }
2715
2716 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2717 memcpy(gs_copy_hash, hash, 20);
2718 gs_copy_hash[0] ^= 1;
2719
2720 bool found_in_application_cache = true;
2721 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
2722 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2723 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2724 &found_in_application_cache);
2725 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2726 }
2727
2728 if (!keep_executable_info &&
2729 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2730 &found_in_application_cache) &&
2731 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2732 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2733 return;
2734 }
2735
2736 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2737 nir_builder fs_b;
2738 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2739 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2740 fs_m.nir = fs_b.shader;
2741 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2742 }
2743
2744 bool has_gs = modules[MESA_SHADER_GEOMETRY];
2745 bool has_ts = modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL];
2746 bool use_aco = device->physical_device->use_aco;
2747
2748 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2749 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2750
2751 if (!modules[i])
2752 continue;
2753
2754 radv_start_feedback(stage_feedbacks[i]);
2755
2756 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2757 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2758 stage ? stage->pName : "main", i,
2759 stage ? stage->pSpecializationInfo : NULL,
2760 flags, pipeline->layout, aco);
2761
2762 /* We don't want to alter meta shaders IR directly so clone it
2763 * first.
2764 */
2765 if (nir[i]->info.name) {
2766 nir[i] = nir_shader_clone(NULL, nir[i]);
2767 }
2768
2769 radv_stop_feedback(stage_feedbacks[i], false);
2770 }
2771
2772 if (nir[MESA_SHADER_TESS_CTRL]) {
2773 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2774 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2775 }
2776
2777 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2778 radv_link_shaders(pipeline, nir);
2779
2780 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2781 if (nir[i]) {
2782 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2783 nir_lower_non_uniform_ubo_access |
2784 nir_lower_non_uniform_ssbo_access |
2785 nir_lower_non_uniform_texture_access |
2786 nir_lower_non_uniform_image_access);
2787
2788 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2789 if (!aco)
2790 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2791 }
2792
2793 if (radv_can_dump_shader(device, modules[i], false))
2794 nir_print_shader(nir[i], stderr);
2795 }
2796
2797 if (nir[MESA_SHADER_FRAGMENT])
2798 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2799
2800 radv_fill_shader_keys(device, keys, key, nir);
2801
2802 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2803
2804 if ((nir[MESA_SHADER_VERTEX] &&
2805 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2806 (nir[MESA_SHADER_TESS_EVAL] &&
2807 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2808 struct gfx10_ngg_info *ngg_info;
2809
2810 if (nir[MESA_SHADER_GEOMETRY])
2811 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2812 else if (nir[MESA_SHADER_TESS_CTRL])
2813 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2814 else
2815 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2816
2817 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2818 } else if (nir[MESA_SHADER_GEOMETRY]) {
2819 struct gfx9_gs_info *gs_info =
2820 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2821
2822 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2823 }
2824
2825 if (nir[MESA_SHADER_FRAGMENT]) {
2826 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2827 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2828
2829 bool aco = use_aco && radv_aco_supported_stage(MESA_SHADER_FRAGMENT, has_gs, has_ts);
2830 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2831 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2832 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2833 infos + MESA_SHADER_FRAGMENT,
2834 keep_executable_info, aco,
2835 &binaries[MESA_SHADER_FRAGMENT]);
2836
2837 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2838 }
2839
2840 /* TODO: These are no longer used as keys we should refactor this */
2841 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2842 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2843 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2844 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2845 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2846 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2847 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2848 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2849 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2850 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2851 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2852 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2853 }
2854
2855 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2856 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2857 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2858 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2859 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2860
2861 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2862
2863 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2864 pipeline->layout,
2865 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2866 false, &binaries[MESA_SHADER_TESS_CTRL]);
2867
2868 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2869 }
2870 modules[MESA_SHADER_VERTEX] = NULL;
2871 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2872 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2873 }
2874
2875 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2876 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2877 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2878 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2879
2880 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2881
2882 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2883 pipeline->layout,
2884 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2885 false, &binaries[MESA_SHADER_GEOMETRY]);
2886
2887 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2888 }
2889 modules[pre_stage] = NULL;
2890 }
2891
2892 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2893 if(modules[i] && !pipeline->shaders[i]) {
2894 if (i == MESA_SHADER_TESS_CTRL) {
2895 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2896 }
2897 if (i == MESA_SHADER_TESS_EVAL) {
2898 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2899 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2900 }
2901
2902 radv_start_feedback(stage_feedbacks[i]);
2903
2904 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2905 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2906 pipeline->layout,
2907 keys + i, infos + i,keep_executable_info,
2908 aco, &binaries[i]);
2909
2910 radv_stop_feedback(stage_feedbacks[i], false);
2911 }
2912 }
2913
2914 if(modules[MESA_SHADER_GEOMETRY]) {
2915 struct radv_shader_binary *gs_copy_binary = NULL;
2916 if (!pipeline->gs_copy_shader &&
2917 !radv_pipeline_has_ngg(pipeline)) {
2918 struct radv_shader_info info = {};
2919 struct radv_shader_variant_key key = {};
2920
2921 key.has_multiview_view_index =
2922 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2923
2924 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2925 pipeline->layout, &key,
2926 &info);
2927 info.wave_size = 64; /* Wave32 not supported. */
2928
2929 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2930 device, nir[MESA_SHADER_GEOMETRY], &info,
2931 &gs_copy_binary, keep_executable_info,
2932 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2933 }
2934
2935 if (!keep_executable_info && pipeline->gs_copy_shader) {
2936 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2937 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2938
2939 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2940 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2941
2942 radv_pipeline_cache_insert_shaders(device, cache,
2943 gs_copy_hash,
2944 variants,
2945 binaries);
2946 }
2947 free(gs_copy_binary);
2948 }
2949
2950 if (!keep_executable_info) {
2951 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2952 binaries);
2953 }
2954
2955 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2956 free(binaries[i]);
2957 if (nir[i]) {
2958 ralloc_free(nir[i]);
2959
2960 if (radv_can_dump_shader_stats(device, modules[i]))
2961 radv_shader_dump_stats(device,
2962 pipeline->shaders[i],
2963 i, stderr);
2964 }
2965 }
2966
2967 if (fs_m.nir)
2968 ralloc_free(fs_m.nir);
2969
2970 radv_stop_feedback(pipeline_feedback, false);
2971 }
2972
2973 static uint32_t
2974 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2975 gl_shader_stage stage, enum chip_class chip_class)
2976 {
2977 bool has_gs = radv_pipeline_has_gs(pipeline);
2978 bool has_tess = radv_pipeline_has_tess(pipeline);
2979 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2980
2981 switch (stage) {
2982 case MESA_SHADER_FRAGMENT:
2983 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2984 case MESA_SHADER_VERTEX:
2985 if (has_tess) {
2986 if (chip_class >= GFX10) {
2987 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2988 } else if (chip_class == GFX9) {
2989 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2990 } else {
2991 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2992 }
2993
2994 }
2995
2996 if (has_gs) {
2997 if (chip_class >= GFX10) {
2998 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2999 } else {
3000 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3001 }
3002 }
3003
3004 if (has_ngg)
3005 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3006
3007 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3008 case MESA_SHADER_GEOMETRY:
3009 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3010 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3011 case MESA_SHADER_COMPUTE:
3012 return R_00B900_COMPUTE_USER_DATA_0;
3013 case MESA_SHADER_TESS_CTRL:
3014 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3015 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3016 case MESA_SHADER_TESS_EVAL:
3017 if (has_gs) {
3018 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3019 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3020 } else if (has_ngg) {
3021 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3022 } else {
3023 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3024 }
3025 default:
3026 unreachable("unknown shader");
3027 }
3028 }
3029
3030 struct radv_bin_size_entry {
3031 unsigned bpp;
3032 VkExtent2D extent;
3033 };
3034
3035 static VkExtent2D
3036 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3037 {
3038 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3039 {
3040 /* One RB / SE */
3041 {
3042 /* One shader engine */
3043 { 0, {128, 128}},
3044 { 1, { 64, 128}},
3045 { 2, { 32, 128}},
3046 { 3, { 16, 128}},
3047 { 17, { 0, 0}},
3048 { UINT_MAX, { 0, 0}},
3049 },
3050 {
3051 /* Two shader engines */
3052 { 0, {128, 128}},
3053 { 2, { 64, 128}},
3054 { 3, { 32, 128}},
3055 { 5, { 16, 128}},
3056 { 17, { 0, 0}},
3057 { UINT_MAX, { 0, 0}},
3058 },
3059 {
3060 /* Four shader engines */
3061 { 0, {128, 128}},
3062 { 3, { 64, 128}},
3063 { 5, { 16, 128}},
3064 { 17, { 0, 0}},
3065 { UINT_MAX, { 0, 0}},
3066 },
3067 },
3068 {
3069 /* Two RB / SE */
3070 {
3071 /* One shader engine */
3072 { 0, {128, 128}},
3073 { 2, { 64, 128}},
3074 { 3, { 32, 128}},
3075 { 5, { 16, 128}},
3076 { 33, { 0, 0}},
3077 { UINT_MAX, { 0, 0}},
3078 },
3079 {
3080 /* Two shader engines */
3081 { 0, {128, 128}},
3082 { 3, { 64, 128}},
3083 { 5, { 32, 128}},
3084 { 9, { 16, 128}},
3085 { 33, { 0, 0}},
3086 { UINT_MAX, { 0, 0}},
3087 },
3088 {
3089 /* Four shader engines */
3090 { 0, {256, 256}},
3091 { 2, {128, 256}},
3092 { 3, {128, 128}},
3093 { 5, { 64, 128}},
3094 { 9, { 16, 128}},
3095 { 33, { 0, 0}},
3096 { UINT_MAX, { 0, 0}},
3097 },
3098 },
3099 {
3100 /* Four RB / SE */
3101 {
3102 /* One shader engine */
3103 { 0, {128, 256}},
3104 { 2, {128, 128}},
3105 { 3, { 64, 128}},
3106 { 5, { 32, 128}},
3107 { 9, { 16, 128}},
3108 { 33, { 0, 0}},
3109 { UINT_MAX, { 0, 0}},
3110 },
3111 {
3112 /* Two shader engines */
3113 { 0, {256, 256}},
3114 { 2, {128, 256}},
3115 { 3, {128, 128}},
3116 { 5, { 64, 128}},
3117 { 9, { 32, 128}},
3118 { 17, { 16, 128}},
3119 { 33, { 0, 0}},
3120 { UINT_MAX, { 0, 0}},
3121 },
3122 {
3123 /* Four shader engines */
3124 { 0, {256, 512}},
3125 { 2, {256, 256}},
3126 { 3, {128, 256}},
3127 { 5, {128, 128}},
3128 { 9, { 64, 128}},
3129 { 17, { 16, 128}},
3130 { 33, { 0, 0}},
3131 { UINT_MAX, { 0, 0}},
3132 },
3133 },
3134 };
3135 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3136 {
3137 // One RB / SE
3138 {
3139 // One shader engine
3140 { 0, {128, 256}},
3141 { 2, {128, 128}},
3142 { 4, { 64, 128}},
3143 { 7, { 32, 128}},
3144 { 13, { 16, 128}},
3145 { 49, { 0, 0}},
3146 { UINT_MAX, { 0, 0}},
3147 },
3148 {
3149 // Two shader engines
3150 { 0, {256, 256}},
3151 { 2, {128, 256}},
3152 { 4, {128, 128}},
3153 { 7, { 64, 128}},
3154 { 13, { 32, 128}},
3155 { 25, { 16, 128}},
3156 { 49, { 0, 0}},
3157 { UINT_MAX, { 0, 0}},
3158 },
3159 {
3160 // Four shader engines
3161 { 0, {256, 512}},
3162 { 2, {256, 256}},
3163 { 4, {128, 256}},
3164 { 7, {128, 128}},
3165 { 13, { 64, 128}},
3166 { 25, { 16, 128}},
3167 { 49, { 0, 0}},
3168 { UINT_MAX, { 0, 0}},
3169 },
3170 },
3171 {
3172 // Two RB / SE
3173 {
3174 // One shader engine
3175 { 0, {256, 256}},
3176 { 2, {128, 256}},
3177 { 4, {128, 128}},
3178 { 7, { 64, 128}},
3179 { 13, { 32, 128}},
3180 { 25, { 16, 128}},
3181 { 97, { 0, 0}},
3182 { UINT_MAX, { 0, 0}},
3183 },
3184 {
3185 // Two shader engines
3186 { 0, {256, 512}},
3187 { 2, {256, 256}},
3188 { 4, {128, 256}},
3189 { 7, {128, 128}},
3190 { 13, { 64, 128}},
3191 { 25, { 32, 128}},
3192 { 49, { 16, 128}},
3193 { 97, { 0, 0}},
3194 { UINT_MAX, { 0, 0}},
3195 },
3196 {
3197 // Four shader engines
3198 { 0, {512, 512}},
3199 { 2, {256, 512}},
3200 { 4, {256, 256}},
3201 { 7, {128, 256}},
3202 { 13, {128, 128}},
3203 { 25, { 64, 128}},
3204 { 49, { 16, 128}},
3205 { 97, { 0, 0}},
3206 { UINT_MAX, { 0, 0}},
3207 },
3208 },
3209 {
3210 // Four RB / SE
3211 {
3212 // One shader engine
3213 { 0, {256, 512}},
3214 { 2, {256, 256}},
3215 { 4, {128, 256}},
3216 { 7, {128, 128}},
3217 { 13, { 64, 128}},
3218 { 25, { 32, 128}},
3219 { 49, { 16, 128}},
3220 { UINT_MAX, { 0, 0}},
3221 },
3222 {
3223 // Two shader engines
3224 { 0, {512, 512}},
3225 { 2, {256, 512}},
3226 { 4, {256, 256}},
3227 { 7, {128, 256}},
3228 { 13, {128, 128}},
3229 { 25, { 64, 128}},
3230 { 49, { 32, 128}},
3231 { 97, { 16, 128}},
3232 { UINT_MAX, { 0, 0}},
3233 },
3234 {
3235 // Four shader engines
3236 { 0, {512, 512}},
3237 { 4, {256, 512}},
3238 { 7, {256, 256}},
3239 { 13, {128, 256}},
3240 { 25, {128, 128}},
3241 { 49, { 64, 128}},
3242 { 97, { 16, 128}},
3243 { UINT_MAX, { 0, 0}},
3244 },
3245 },
3246 };
3247
3248 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3249 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3250 VkExtent2D extent = {512, 512};
3251
3252 unsigned log_num_rb_per_se =
3253 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3254 pipeline->device->physical_device->rad_info.max_se);
3255 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3256
3257 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3258 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3259 unsigned effective_samples = total_samples;
3260 unsigned color_bytes_per_pixel = 0;
3261
3262 const VkPipelineColorBlendStateCreateInfo *vkblend =
3263 radv_pipeline_get_color_blend_state(pCreateInfo);
3264 if (vkblend) {
3265 for (unsigned i = 0; i < subpass->color_count; i++) {
3266 if (!vkblend->pAttachments[i].colorWriteMask)
3267 continue;
3268
3269 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3270 continue;
3271
3272 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3273 color_bytes_per_pixel += vk_format_get_blocksize(format);
3274 }
3275
3276 /* MSAA images typically don't use all samples all the time. */
3277 if (effective_samples >= 2 && ps_iter_samples <= 1)
3278 effective_samples = 2;
3279 color_bytes_per_pixel *= effective_samples;
3280 }
3281
3282 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3283 while(color_entry[1].bpp <= color_bytes_per_pixel)
3284 ++color_entry;
3285
3286 extent = color_entry->extent;
3287
3288 if (subpass->depth_stencil_attachment) {
3289 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3290
3291 /* Coefficients taken from AMDVLK */
3292 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3293 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3294 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3295
3296 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3297 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3298 ++ds_entry;
3299
3300 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3301 extent = ds_entry->extent;
3302 }
3303
3304 return extent;
3305 }
3306
3307 static VkExtent2D
3308 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3309 {
3310 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3311 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3312 VkExtent2D extent = {512, 512};
3313
3314 const unsigned db_tag_size = 64;
3315 const unsigned db_tag_count = 312;
3316 const unsigned color_tag_size = 1024;
3317 const unsigned color_tag_count = 31;
3318 const unsigned fmask_tag_size = 256;
3319 const unsigned fmask_tag_count = 44;
3320
3321 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3322 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3323
3324 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3325 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3326 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3327
3328 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3329 const unsigned samples_log = util_logbase2_ceil(total_samples);
3330
3331 unsigned color_bytes_per_pixel = 0;
3332 unsigned fmask_bytes_per_pixel = 0;
3333
3334 const VkPipelineColorBlendStateCreateInfo *vkblend =
3335 radv_pipeline_get_color_blend_state(pCreateInfo);
3336 if (vkblend) {
3337 for (unsigned i = 0; i < subpass->color_count; i++) {
3338 if (!vkblend->pAttachments[i].colorWriteMask)
3339 continue;
3340
3341 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3342 continue;
3343
3344 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3345 color_bytes_per_pixel += vk_format_get_blocksize(format);
3346
3347 if (total_samples > 1) {
3348 assert(samples_log <= 3);
3349 const unsigned fmask_array[] = {0, 1, 1, 4};
3350 fmask_bytes_per_pixel += fmask_array[samples_log];
3351 }
3352 }
3353
3354 color_bytes_per_pixel *= total_samples;
3355 }
3356 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3357
3358 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3359 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3360 extent.height = 1ull << (color_pixel_count_log / 2);
3361
3362 if (fmask_bytes_per_pixel) {
3363 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3364
3365 const VkExtent2D fmask_extent = (VkExtent2D){
3366 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3367 .height = 1ull << (color_pixel_count_log / 2)
3368 };
3369
3370 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3371 extent = fmask_extent;
3372 }
3373
3374 if (subpass->depth_stencil_attachment) {
3375 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3376
3377 /* Coefficients taken from AMDVLK */
3378 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3379 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3380 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3381
3382 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3383
3384 const VkExtent2D db_extent = (VkExtent2D){
3385 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3386 .height = 1ull << (color_pixel_count_log / 2)
3387 };
3388
3389 if (db_extent.width * db_extent.height < extent.width * extent.height)
3390 extent = db_extent;
3391 }
3392
3393 extent.width = MAX2(extent.width, 128);
3394 extent.height = MAX2(extent.width, 64);
3395
3396 return extent;
3397 }
3398
3399 static void
3400 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3401 struct radv_pipeline *pipeline,
3402 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3403 {
3404 uint32_t pa_sc_binner_cntl_0 =
3405 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3406 S_028C44_DISABLE_START_OF_PRIM(1);
3407 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3408
3409 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3410 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3411 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3412 const VkPipelineColorBlendStateCreateInfo *vkblend =
3413 radv_pipeline_get_color_blend_state(pCreateInfo);
3414 unsigned min_bytes_per_pixel = 0;
3415
3416 if (vkblend) {
3417 for (unsigned i = 0; i < subpass->color_count; i++) {
3418 if (!vkblend->pAttachments[i].colorWriteMask)
3419 continue;
3420
3421 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3422 continue;
3423
3424 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3425 unsigned bytes = vk_format_get_blocksize(format);
3426 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3427 min_bytes_per_pixel = bytes;
3428 }
3429 }
3430
3431 pa_sc_binner_cntl_0 =
3432 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3433 S_028C44_BIN_SIZE_X(0) |
3434 S_028C44_BIN_SIZE_Y(0) |
3435 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3436 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3437 S_028C44_DISABLE_START_OF_PRIM(1);
3438 }
3439
3440 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3441 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3442 }
3443
3444 struct radv_binning_settings
3445 radv_get_binning_settings(const struct radv_physical_device *pdev)
3446 {
3447 struct radv_binning_settings settings;
3448 if (pdev->rad_info.has_dedicated_vram) {
3449 settings.context_states_per_bin = 1;
3450 settings.persistent_states_per_bin = 1;
3451 settings.fpovs_per_batch = 63;
3452 } else {
3453 /* The context states are affected by the scissor bug. */
3454 settings.context_states_per_bin = 6;
3455 /* 32 causes hangs for RAVEN. */
3456 settings.persistent_states_per_bin = 16;
3457 settings.fpovs_per_batch = 63;
3458 }
3459
3460 if (pdev->rad_info.has_gfx9_scissor_bug)
3461 settings.context_states_per_bin = 1;
3462
3463 return settings;
3464 }
3465
3466 static void
3467 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3468 struct radv_pipeline *pipeline,
3469 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3470 const struct radv_blend_state *blend)
3471 {
3472 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3473 return;
3474
3475 VkExtent2D bin_size;
3476 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3477 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3478 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3479 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3480 } else
3481 unreachable("Unhandled generation for binning bin size calculation");
3482
3483 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3484 struct radv_binning_settings settings =
3485 radv_get_binning_settings(pipeline->device->physical_device);
3486
3487 bool disable_start_of_prim = true;
3488 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3489
3490 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3491
3492 if (pipeline->device->dfsm_allowed && ps &&
3493 !ps->info.ps.can_discard &&
3494 !ps->info.ps.writes_memory &&
3495 blend->cb_target_enabled_4bit) {
3496 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3497 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3498 }
3499
3500 const uint32_t pa_sc_binner_cntl_0 =
3501 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3502 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3503 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3504 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3505 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3506 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3507 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3508 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3509 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3510 S_028C44_OPTIMAL_BIN_SELECTION(1);
3511
3512 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3513 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3514 } else
3515 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3516 }
3517
3518
3519 static void
3520 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3521 struct radv_pipeline *pipeline,
3522 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3523 const struct radv_graphics_pipeline_create_info *extra)
3524 {
3525 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3526 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3527 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3528 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3529 struct radv_render_pass_attachment *attachment = NULL;
3530 uint32_t db_depth_control = 0, db_stencil_control = 0;
3531 uint32_t db_render_control = 0, db_render_override2 = 0;
3532 uint32_t db_render_override = 0;
3533
3534 if (subpass->depth_stencil_attachment)
3535 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3536
3537 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3538 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3539
3540 if (vkds && has_depth_attachment) {
3541 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3542 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3543 S_028800_ZFUNC(vkds->depthCompareOp) |
3544 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3545
3546 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3547 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3548 }
3549
3550 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3551 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3552 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3553 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3554 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3555 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3556
3557 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3558 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3559 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3560 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3561 }
3562
3563 if (attachment && extra) {
3564 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3565 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3566
3567 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3568 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3569 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3570 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3571 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3572 }
3573
3574 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3575 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3576
3577 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3578 ps->info.ps.writes_z) {
3579 /* From VK_EXT_depth_range_unrestricted spec:
3580 *
3581 * "The behavior described in Primitive Clipping still applies.
3582 * If depth clamping is disabled the depth values are still
3583 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3584 * depth clamping is enabled the above equation is ignored and
3585 * the depth values are instead clamped to the VkViewport
3586 * minDepth and maxDepth values, which in the case of this
3587 * extension can be outside of the 0.0 to 1.0 range."
3588 */
3589 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3590 }
3591
3592 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3593 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3594
3595 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3596 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3597 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3598 }
3599
3600 static void
3601 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3602 struct radv_pipeline *pipeline,
3603 const struct radv_blend_state *blend)
3604 {
3605 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3606 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3607 8);
3608 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3609 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3610
3611 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3612
3613 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3614 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3615 }
3616
3617 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3618
3619 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3620 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3621
3622 pipeline->graphics.col_format = blend->spi_shader_col_format;
3623 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3624 }
3625
3626 static const VkConservativeRasterizationModeEXT
3627 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3628 {
3629 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3630 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3631
3632 if (!conservative_raster)
3633 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3634 return conservative_raster->conservativeRasterizationMode;
3635 }
3636
3637 static void
3638 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3639 struct radv_pipeline *pipeline,
3640 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3641 {
3642 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3643 const VkConservativeRasterizationModeEXT mode =
3644 radv_get_conservative_raster_mode(vkraster);
3645 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3646 bool depth_clip_disable = vkraster->depthClampEnable;
3647
3648 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3649 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3650 if (depth_clip_state) {
3651 depth_clip_disable = !depth_clip_state->depthClipEnable;
3652 }
3653
3654 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3655 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3656 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3657 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3658 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3659 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3660
3661 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3662 S_0286D4_FLAT_SHADE_ENA(1) |
3663 S_0286D4_PNT_SPRITE_ENA(1) |
3664 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3665 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3666 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3667 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3668 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3669
3670 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3671 S_028BE4_PIX_CENTER(1) | // TODO verify
3672 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3673 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3674
3675 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3676 S_028814_FACE(vkraster->frontFace) |
3677 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3678 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3679 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3680 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3681 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3682 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3683 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3684 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3685
3686 /* Conservative rasterization. */
3687 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3688 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3689
3690 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3691 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3692 S_028804_OVERRASTERIZATION_AMOUNT(4);
3693
3694 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3695 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3696 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3697
3698 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3699 pa_sc_conservative_rast |=
3700 S_028C4C_OVER_RAST_ENABLE(1) |
3701 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3702 S_028C4C_UNDER_RAST_ENABLE(0) |
3703 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3704 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3705 } else {
3706 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3707 pa_sc_conservative_rast |=
3708 S_028C4C_OVER_RAST_ENABLE(0) |
3709 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3710 S_028C4C_UNDER_RAST_ENABLE(1) |
3711 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3712 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3713 }
3714 }
3715
3716 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3717 pa_sc_conservative_rast);
3718 }
3719
3720
3721 static void
3722 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3723 struct radv_pipeline *pipeline)
3724 {
3725 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3726
3727 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3728 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3729 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3730
3731 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3732 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3733 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3734 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
3735 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3736
3737 /* The exclusion bits can be set to improve rasterization efficiency
3738 * if no sample lies on the pixel boundary (-8 sample offset). It's
3739 * currently always TRUE because the driver doesn't support 16 samples.
3740 */
3741 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3742 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3743 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3744 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3745
3746 /* GFX9: Flush DFSM when the AA mode changes. */
3747 if (pipeline->device->dfsm_allowed) {
3748 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3749 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3750 }
3751 }
3752
3753 static void
3754 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3755 struct radv_pipeline *pipeline)
3756 {
3757 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3758 const struct radv_shader_variant *vs =
3759 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3760 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3761 pipeline->shaders[MESA_SHADER_VERTEX];
3762 unsigned vgt_primitiveid_en = 0;
3763 uint32_t vgt_gs_mode = 0;
3764
3765 if (radv_pipeline_has_ngg(pipeline))
3766 return;
3767
3768 if (radv_pipeline_has_gs(pipeline)) {
3769 const struct radv_shader_variant *gs =
3770 pipeline->shaders[MESA_SHADER_GEOMETRY];
3771
3772 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3773 pipeline->device->physical_device->rad_info.chip_class);
3774 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3775 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3776 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3777 }
3778
3779 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3780 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3781 }
3782
3783 static void
3784 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3785 struct radeon_cmdbuf *cs,
3786 struct radv_pipeline *pipeline,
3787 struct radv_shader_variant *shader)
3788 {
3789 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3790
3791 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3792 radeon_emit(cs, va >> 8);
3793 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3794 radeon_emit(cs, shader->config.rsrc1);
3795 radeon_emit(cs, shader->config.rsrc2);
3796
3797 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3798 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3799 clip_dist_mask = outinfo->clip_dist_mask;
3800 cull_dist_mask = outinfo->cull_dist_mask;
3801 total_mask = clip_dist_mask | cull_dist_mask;
3802 bool misc_vec_ena = outinfo->writes_pointsize ||
3803 outinfo->writes_layer ||
3804 outinfo->writes_viewport_index;
3805 unsigned spi_vs_out_config, nparams;
3806
3807 /* VS is required to export at least one param. */
3808 nparams = MAX2(outinfo->param_exports, 1);
3809 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3810
3811 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3812 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3813 }
3814
3815 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3816
3817 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3818 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3819 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3820 V_02870C_SPI_SHADER_4COMP :
3821 V_02870C_SPI_SHADER_NONE) |
3822 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3823 V_02870C_SPI_SHADER_4COMP :
3824 V_02870C_SPI_SHADER_NONE) |
3825 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3826 V_02870C_SPI_SHADER_4COMP :
3827 V_02870C_SPI_SHADER_NONE));
3828
3829 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3830 S_028818_VTX_W0_FMT(1) |
3831 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3832 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3833 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3834
3835 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3836 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3837 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3838 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3839 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3840 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3841 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3842 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3843 cull_dist_mask << 8 |
3844 clip_dist_mask);
3845
3846 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3847 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3848 outinfo->writes_viewport_index);
3849 }
3850
3851 static void
3852 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3853 struct radv_pipeline *pipeline,
3854 struct radv_shader_variant *shader)
3855 {
3856 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3857
3858 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3859 radeon_emit(cs, va >> 8);
3860 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3861 radeon_emit(cs, shader->config.rsrc1);
3862 radeon_emit(cs, shader->config.rsrc2);
3863 }
3864
3865 static void
3866 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3867 struct radv_pipeline *pipeline,
3868 struct radv_shader_variant *shader,
3869 const struct radv_tessellation_state *tess)
3870 {
3871 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3872 uint32_t rsrc2 = shader->config.rsrc2;
3873
3874 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3875 radeon_emit(cs, va >> 8);
3876 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3877
3878 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3879 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3880 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3881 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3882
3883 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3884 radeon_emit(cs, shader->config.rsrc1);
3885 radeon_emit(cs, rsrc2);
3886 }
3887
3888 static void
3889 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3890 struct radeon_cmdbuf *cs,
3891 struct radv_pipeline *pipeline,
3892 struct radv_shader_variant *shader)
3893 {
3894 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3895 gl_shader_stage es_type =
3896 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3897 struct radv_shader_variant *es =
3898 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3899 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3900
3901 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3902 radeon_emit(cs, va >> 8);
3903 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3904 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3905 radeon_emit(cs, shader->config.rsrc1);
3906 radeon_emit(cs, shader->config.rsrc2);
3907
3908 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3909 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3910 clip_dist_mask = outinfo->clip_dist_mask;
3911 cull_dist_mask = outinfo->cull_dist_mask;
3912 total_mask = clip_dist_mask | cull_dist_mask;
3913 bool misc_vec_ena = outinfo->writes_pointsize ||
3914 outinfo->writes_layer ||
3915 outinfo->writes_viewport_index;
3916 bool es_enable_prim_id = outinfo->export_prim_id ||
3917 (es && es->info.uses_prim_id);
3918 bool break_wave_at_eoi = false;
3919 unsigned ge_cntl;
3920 unsigned nparams;
3921
3922 if (es_type == MESA_SHADER_TESS_EVAL) {
3923 struct radv_shader_variant *gs =
3924 pipeline->shaders[MESA_SHADER_GEOMETRY];
3925
3926 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3927 break_wave_at_eoi = true;
3928 }
3929
3930 nparams = MAX2(outinfo->param_exports, 1);
3931 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3932 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3933 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3934
3935 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3936 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3937 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3938 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3939 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3940 V_02870C_SPI_SHADER_4COMP :
3941 V_02870C_SPI_SHADER_NONE) |
3942 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3943 V_02870C_SPI_SHADER_4COMP :
3944 V_02870C_SPI_SHADER_NONE) |
3945 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3946 V_02870C_SPI_SHADER_4COMP :
3947 V_02870C_SPI_SHADER_NONE));
3948
3949 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3950 S_028818_VTX_W0_FMT(1) |
3951 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3952 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3953 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3954 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3955 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3956 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3957 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3958 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3959 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3960 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3961 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3962 cull_dist_mask << 8 |
3963 clip_dist_mask);
3964
3965 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3966 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3967 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
3968
3969 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3970 ngg_state->vgt_esgs_ring_itemsize);
3971
3972 /* NGG specific registers. */
3973 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3974 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3975
3976 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3977 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3978 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3979 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3980 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3981 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3982 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3983 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3984 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3985 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3986 S_028B90_CNT(gs_num_invocations) |
3987 S_028B90_ENABLE(gs_num_invocations > 1) |
3988 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3989
3990 /* User edge flags are set by the pos exports. If user edge flags are
3991 * not used, we must use hw-generated edge flags and pass them via
3992 * the prim export to prevent drawing lines on internal edges of
3993 * decomposed primitives (such as quads) with polygon mode = lines.
3994 *
3995 * TODO: We should combine hw-generated edge flags with user edge
3996 * flags in the shader.
3997 */
3998 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3999 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4000 !radv_pipeline_has_gs(pipeline)));
4001
4002 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4003 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
4004 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4005
4006 /* Bug workaround for a possible hang with non-tessellation cases.
4007 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4008 *
4009 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4010 */
4011 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
4012 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
4013 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
4014 !radv_pipeline_has_tess(pipeline) &&
4015 ngg_state->hw_max_esverts != 256) {
4016 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4017
4018 if (ngg_state->hw_max_esverts > 5) {
4019 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4020 }
4021 }
4022
4023 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4024 }
4025
4026 static void
4027 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4028 struct radv_pipeline *pipeline,
4029 struct radv_shader_variant *shader,
4030 const struct radv_tessellation_state *tess)
4031 {
4032 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4033
4034 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4035 unsigned hs_rsrc2 = shader->config.rsrc2;
4036
4037 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4038 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
4039 } else {
4040 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
4041 }
4042
4043 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4044 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4045 radeon_emit(cs, va >> 8);
4046 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4047 } else {
4048 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4049 radeon_emit(cs, va >> 8);
4050 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4051 }
4052
4053 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4054 radeon_emit(cs, shader->config.rsrc1);
4055 radeon_emit(cs, hs_rsrc2);
4056 } else {
4057 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4058 radeon_emit(cs, va >> 8);
4059 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4060 radeon_emit(cs, shader->config.rsrc1);
4061 radeon_emit(cs, shader->config.rsrc2);
4062 }
4063 }
4064
4065 static void
4066 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4067 struct radeon_cmdbuf *cs,
4068 struct radv_pipeline *pipeline,
4069 const struct radv_tessellation_state *tess)
4070 {
4071 struct radv_shader_variant *vs;
4072
4073 /* Skip shaders merged into HS/GS */
4074 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4075 if (!vs)
4076 return;
4077
4078 if (vs->info.vs.as_ls)
4079 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4080 else if (vs->info.vs.as_es)
4081 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4082 else if (vs->info.is_ngg)
4083 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4084 else
4085 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4086 }
4087
4088 static void
4089 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4090 struct radeon_cmdbuf *cs,
4091 struct radv_pipeline *pipeline,
4092 const struct radv_tessellation_state *tess)
4093 {
4094 if (!radv_pipeline_has_tess(pipeline))
4095 return;
4096
4097 struct radv_shader_variant *tes, *tcs;
4098
4099 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4100 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4101
4102 if (tes) {
4103 if (tes->info.is_ngg) {
4104 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4105 } else if (tes->info.tes.as_es)
4106 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4107 else
4108 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4109 }
4110
4111 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4112
4113 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4114 tess->tf_param);
4115
4116 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4117 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4118 tess->ls_hs_config);
4119 else
4120 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4121 tess->ls_hs_config);
4122
4123 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4124 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4125 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4126 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4127 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4128 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4129 }
4130 }
4131
4132 static void
4133 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4134 struct radeon_cmdbuf *cs,
4135 struct radv_pipeline *pipeline,
4136 struct radv_shader_variant *gs)
4137 {
4138 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4139 unsigned gs_max_out_vertices;
4140 uint8_t *num_components;
4141 uint8_t max_stream;
4142 unsigned offset;
4143 uint64_t va;
4144
4145 gs_max_out_vertices = gs->info.gs.vertices_out;
4146 max_stream = gs->info.gs.max_stream;
4147 num_components = gs->info.gs.num_stream_output_components;
4148
4149 offset = num_components[0] * gs_max_out_vertices;
4150
4151 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4152 radeon_emit(ctx_cs, offset);
4153 if (max_stream >= 1)
4154 offset += num_components[1] * gs_max_out_vertices;
4155 radeon_emit(ctx_cs, offset);
4156 if (max_stream >= 2)
4157 offset += num_components[2] * gs_max_out_vertices;
4158 radeon_emit(ctx_cs, offset);
4159 if (max_stream >= 3)
4160 offset += num_components[3] * gs_max_out_vertices;
4161 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4162
4163 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4164 radeon_emit(ctx_cs, num_components[0]);
4165 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4166 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4167 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4168
4169 uint32_t gs_num_invocations = gs->info.gs.invocations;
4170 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4171 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4172 S_028B90_ENABLE(gs_num_invocations > 0));
4173
4174 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4175 gs_state->vgt_esgs_ring_itemsize);
4176
4177 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4178
4179 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4180 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4181 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4182 radeon_emit(cs, va >> 8);
4183 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4184 } else {
4185 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4186 radeon_emit(cs, va >> 8);
4187 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4188 }
4189
4190 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4191 radeon_emit(cs, gs->config.rsrc1);
4192 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4193
4194 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4195 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4196 } else {
4197 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4198 radeon_emit(cs, va >> 8);
4199 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4200 radeon_emit(cs, gs->config.rsrc1);
4201 radeon_emit(cs, gs->config.rsrc2);
4202 }
4203
4204 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4205 }
4206
4207 static void
4208 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4209 struct radeon_cmdbuf *cs,
4210 struct radv_pipeline *pipeline)
4211 {
4212 struct radv_shader_variant *gs;
4213
4214 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4215 if (!gs)
4216 return;
4217
4218 if (gs->info.is_ngg)
4219 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4220 else
4221 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4222
4223 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4224 gs->info.gs.vertices_out);
4225 }
4226
4227 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
4228 {
4229 uint32_t ps_input_cntl;
4230 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4231 ps_input_cntl = S_028644_OFFSET(offset);
4232 if (flat_shade)
4233 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4234 if (float16) {
4235 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4236 S_028644_ATTR0_VALID(1);
4237 }
4238 } else {
4239 /* The input is a DEFAULT_VAL constant. */
4240 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4241 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4242 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4243 ps_input_cntl = S_028644_OFFSET(0x20) |
4244 S_028644_DEFAULT_VAL(offset);
4245 }
4246 return ps_input_cntl;
4247 }
4248
4249 static void
4250 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4251 struct radv_pipeline *pipeline)
4252 {
4253 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4254 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4255 uint32_t ps_input_cntl[32];
4256
4257 unsigned ps_offset = 0;
4258
4259 if (ps->info.ps.prim_id_input) {
4260 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4261 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4262 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4263 ++ps_offset;
4264 }
4265 }
4266
4267 if (ps->info.ps.layer_input ||
4268 ps->info.needs_multiview_view_index) {
4269 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4270 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4271 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4272 else
4273 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
4274 ++ps_offset;
4275 }
4276
4277 if (ps->info.ps.has_pcoord) {
4278 unsigned val;
4279 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4280 ps_input_cntl[ps_offset] = val;
4281 ps_offset++;
4282 }
4283
4284 if (ps->info.ps.num_input_clips_culls) {
4285 unsigned vs_offset;
4286
4287 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4288 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4289 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4290 ++ps_offset;
4291 }
4292
4293 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4294 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4295 ps->info.ps.num_input_clips_culls > 4) {
4296 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4297 ++ps_offset;
4298 }
4299 }
4300
4301 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4302 unsigned vs_offset;
4303 bool flat_shade;
4304 bool float16;
4305 if (!(ps->info.ps.input_mask & (1u << i)))
4306 continue;
4307
4308 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4309 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4310 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4311 ++ps_offset;
4312 continue;
4313 }
4314
4315 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4316 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4317
4318 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
4319 ++ps_offset;
4320 }
4321
4322 if (ps_offset) {
4323 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4324 for (unsigned i = 0; i < ps_offset; i++) {
4325 radeon_emit(ctx_cs, ps_input_cntl[i]);
4326 }
4327 }
4328 }
4329
4330 static uint32_t
4331 radv_compute_db_shader_control(const struct radv_device *device,
4332 const struct radv_pipeline *pipeline,
4333 const struct radv_shader_variant *ps)
4334 {
4335 unsigned z_order;
4336 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4337 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4338 else
4339 z_order = V_02880C_LATE_Z;
4340
4341 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4342 !device->physical_device->rad_info.rbplus_allowed;
4343
4344 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4345 * but this appears to break Project Cars (DXVK). See
4346 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4347 */
4348 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4349
4350 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4351 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4352 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4353 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4354 S_02880C_Z_ORDER(z_order) |
4355 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4356 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4357 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4358 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4359 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4360 }
4361
4362 static void
4363 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4364 struct radeon_cmdbuf *cs,
4365 struct radv_pipeline *pipeline)
4366 {
4367 struct radv_shader_variant *ps;
4368 uint64_t va;
4369 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4370
4371 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4372 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4373
4374 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4375 radeon_emit(cs, va >> 8);
4376 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4377 radeon_emit(cs, ps->config.rsrc1);
4378 radeon_emit(cs, ps->config.rsrc2);
4379
4380 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4381 radv_compute_db_shader_control(pipeline->device,
4382 pipeline, ps));
4383
4384 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4385 ps->config.spi_ps_input_ena);
4386
4387 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4388 ps->config.spi_ps_input_addr);
4389
4390 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4391 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4392 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4393
4394 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4395
4396 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4397 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4398 ps->info.ps.writes_stencil,
4399 ps->info.ps.writes_sample_mask));
4400
4401 if (pipeline->device->dfsm_allowed) {
4402 /* optimise this? */
4403 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4404 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4405 }
4406 }
4407
4408 static void
4409 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4410 struct radv_pipeline *pipeline)
4411 {
4412 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4413 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4414 return;
4415
4416 unsigned vtx_reuse_depth = 30;
4417 if (radv_pipeline_has_tess(pipeline) &&
4418 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4419 vtx_reuse_depth = 14;
4420 }
4421 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4422 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4423 }
4424
4425 static uint32_t
4426 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4427 {
4428 uint32_t stages = 0;
4429 if (radv_pipeline_has_tess(pipeline)) {
4430 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4431 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4432
4433 if (radv_pipeline_has_gs(pipeline))
4434 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4435 S_028B54_GS_EN(1);
4436 else if (radv_pipeline_has_ngg(pipeline))
4437 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4438 else
4439 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4440 } else if (radv_pipeline_has_gs(pipeline)) {
4441 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4442 S_028B54_GS_EN(1);
4443 } else if (radv_pipeline_has_ngg(pipeline)) {
4444 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4445 }
4446
4447 if (radv_pipeline_has_ngg(pipeline)) {
4448 stages |= S_028B54_PRIMGEN_EN(1);
4449 if (pipeline->streamout_shader)
4450 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4451 } else if (radv_pipeline_has_gs(pipeline)) {
4452 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4453 }
4454
4455 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4456 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4457
4458 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4459 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4460
4461 if (radv_pipeline_has_tess(pipeline))
4462 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4463
4464 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4465 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4466 if (pipeline->gs_copy_shader)
4467 vs_size = pipeline->gs_copy_shader->info.wave_size;
4468 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4469 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4470 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4471 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4472
4473 if (radv_pipeline_has_ngg(pipeline))
4474 gs_size = vs_size;
4475
4476 /* legacy GS only supports Wave64 */
4477 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4478 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4479 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4480 }
4481
4482 return stages;
4483 }
4484
4485 static uint32_t
4486 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4487 {
4488 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4489 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4490
4491 if (!discard_rectangle_info)
4492 return 0xffff;
4493
4494 unsigned mask = 0;
4495
4496 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4497 /* Interpret i as a bitmask, and then set the bit in the mask if
4498 * that combination of rectangles in which the pixel is contained
4499 * should pass the cliprect test. */
4500 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4501
4502 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4503 !relevant_subset)
4504 continue;
4505
4506 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4507 relevant_subset)
4508 continue;
4509
4510 mask |= 1u << i;
4511 }
4512
4513 return mask;
4514 }
4515
4516 static void
4517 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4518 struct radv_pipeline *pipeline,
4519 const struct radv_tessellation_state *tess)
4520 {
4521 bool break_wave_at_eoi = false;
4522 unsigned primgroup_size;
4523 unsigned vertgroup_size;
4524
4525 if (radv_pipeline_has_tess(pipeline)) {
4526 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4527 vertgroup_size = 0;
4528 } else if (radv_pipeline_has_gs(pipeline)) {
4529 const struct gfx9_gs_info *gs_state =
4530 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4531 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4532 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4533 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4534 } else {
4535 primgroup_size = 128; /* recommended without a GS and tess */
4536 vertgroup_size = 0;
4537 }
4538
4539 if (radv_pipeline_has_tess(pipeline)) {
4540 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4541 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4542 break_wave_at_eoi = true;
4543 }
4544
4545 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4546 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4547 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4548 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4549 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4550 }
4551
4552 static void
4553 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4554 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4555 const struct radv_graphics_pipeline_create_info *extra,
4556 const struct radv_blend_state *blend,
4557 const struct radv_tessellation_state *tess,
4558 unsigned prim, unsigned gs_out)
4559 {
4560 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4561 struct radeon_cmdbuf *cs = &pipeline->cs;
4562
4563 cs->max_dw = 64;
4564 ctx_cs->max_dw = 256;
4565 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4566 ctx_cs->buf = cs->buf + cs->max_dw;
4567
4568 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4569 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4570 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4571 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4572 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4573 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4574 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4575 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4576 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4577 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4578 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4579 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4580
4581 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4582 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4583
4584 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4585
4586 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4587 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4588 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4589 } else {
4590 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4591 }
4592 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4593
4594 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4595
4596 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4597
4598 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4599 assert(cs->cdw <= cs->max_dw);
4600 }
4601
4602 static struct radv_ia_multi_vgt_param_helpers
4603 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4604 const struct radv_tessellation_state *tess,
4605 uint32_t prim)
4606 {
4607 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4608 const struct radv_device *device = pipeline->device;
4609
4610 if (radv_pipeline_has_tess(pipeline))
4611 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4612 else if (radv_pipeline_has_gs(pipeline))
4613 ia_multi_vgt_param.primgroup_size = 64;
4614 else
4615 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4616
4617 /* GS requirement. */
4618 ia_multi_vgt_param.partial_es_wave = false;
4619 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4620 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4621 ia_multi_vgt_param.partial_es_wave = true;
4622
4623 ia_multi_vgt_param.wd_switch_on_eop = false;
4624 if (device->physical_device->rad_info.chip_class >= GFX7) {
4625 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4626 * 4 shader engines. Set 1 to pass the assertion below.
4627 * The other cases are hardware requirements. */
4628 if (device->physical_device->rad_info.max_se < 4 ||
4629 prim == V_008958_DI_PT_POLYGON ||
4630 prim == V_008958_DI_PT_LINELOOP ||
4631 prim == V_008958_DI_PT_TRIFAN ||
4632 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4633 (pipeline->graphics.prim_restart_enable &&
4634 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4635 (prim != V_008958_DI_PT_POINTLIST &&
4636 prim != V_008958_DI_PT_LINESTRIP))))
4637 ia_multi_vgt_param.wd_switch_on_eop = true;
4638 }
4639
4640 ia_multi_vgt_param.ia_switch_on_eoi = false;
4641 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4642 ia_multi_vgt_param.ia_switch_on_eoi = true;
4643 if (radv_pipeline_has_gs(pipeline) &&
4644 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4645 ia_multi_vgt_param.ia_switch_on_eoi = true;
4646 if (radv_pipeline_has_tess(pipeline)) {
4647 /* SWITCH_ON_EOI must be set if PrimID is used. */
4648 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4649 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4650 ia_multi_vgt_param.ia_switch_on_eoi = true;
4651 }
4652
4653 ia_multi_vgt_param.partial_vs_wave = false;
4654 if (radv_pipeline_has_tess(pipeline)) {
4655 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4656 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4657 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4658 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4659 radv_pipeline_has_gs(pipeline))
4660 ia_multi_vgt_param.partial_vs_wave = true;
4661 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4662 if (device->physical_device->rad_info.has_distributed_tess) {
4663 if (radv_pipeline_has_gs(pipeline)) {
4664 if (device->physical_device->rad_info.chip_class <= GFX8)
4665 ia_multi_vgt_param.partial_es_wave = true;
4666 } else {
4667 ia_multi_vgt_param.partial_vs_wave = true;
4668 }
4669 }
4670 }
4671
4672 /* Workaround for a VGT hang when strip primitive types are used with
4673 * primitive restart.
4674 */
4675 if (pipeline->graphics.prim_restart_enable &&
4676 (prim == V_008958_DI_PT_LINESTRIP ||
4677 prim == V_008958_DI_PT_TRISTRIP ||
4678 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4679 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4680 ia_multi_vgt_param.partial_vs_wave = true;
4681 }
4682
4683 if (radv_pipeline_has_gs(pipeline)) {
4684 /* On these chips there is the possibility of a hang if the
4685 * pipeline uses a GS and partial_vs_wave is not set.
4686 *
4687 * This mostly does not hit 4-SE chips, as those typically set
4688 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4689 * with GS due to another workaround.
4690 *
4691 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4692 */
4693 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4694 device->physical_device->rad_info.family == CHIP_FIJI ||
4695 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4696 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4697 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4698 device->physical_device->rad_info.family == CHIP_VEGAM) {
4699 ia_multi_vgt_param.partial_vs_wave = true;
4700 }
4701 }
4702
4703 ia_multi_vgt_param.base =
4704 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4705 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4706 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4707 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4708 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4709
4710 return ia_multi_vgt_param;
4711 }
4712
4713
4714 static void
4715 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4716 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4717 {
4718 const VkPipelineVertexInputStateCreateInfo *vi_info =
4719 pCreateInfo->pVertexInputState;
4720 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4721
4722 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4723 const VkVertexInputAttributeDescription *desc =
4724 &vi_info->pVertexAttributeDescriptions[i];
4725 unsigned loc = desc->location;
4726 const struct vk_format_description *format_desc;
4727
4728 format_desc = vk_format_description(desc->format);
4729
4730 velems->format_size[loc] = format_desc->block.bits / 8;
4731 }
4732
4733 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4734 const VkVertexInputBindingDescription *desc =
4735 &vi_info->pVertexBindingDescriptions[i];
4736
4737 pipeline->binding_stride[desc->binding] = desc->stride;
4738 pipeline->num_vertex_bindings =
4739 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4740 }
4741 }
4742
4743 static struct radv_shader_variant *
4744 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4745 {
4746 int i;
4747
4748 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4749 struct radv_shader_variant *shader =
4750 radv_get_shader(pipeline, i);
4751
4752 if (shader && shader->info.so.num_outputs > 0)
4753 return shader;
4754 }
4755
4756 return NULL;
4757 }
4758
4759 static VkResult
4760 radv_secure_compile(struct radv_pipeline *pipeline,
4761 struct radv_device *device,
4762 const struct radv_pipeline_key *key,
4763 const VkPipelineShaderStageCreateInfo **pStages,
4764 const VkPipelineCreateFlags flags,
4765 unsigned num_stages)
4766 {
4767 uint8_t allowed_pipeline_hashes[2][20];
4768 radv_hash_shaders(allowed_pipeline_hashes[0], pStages,
4769 pipeline->layout, key, get_hash_flags(device));
4770
4771 /* Generate the GC copy hash */
4772 memcpy(allowed_pipeline_hashes[1], allowed_pipeline_hashes[0], 20);
4773 allowed_pipeline_hashes[1][0] ^= 1;
4774
4775 uint8_t allowed_hashes[2][20];
4776 for (unsigned i = 0; i < 2; ++i) {
4777 disk_cache_compute_key(device->physical_device->disk_cache,
4778 allowed_pipeline_hashes[i], 20,
4779 allowed_hashes[i]);
4780 }
4781
4782 /* Do an early exit if all cache entries are already there. */
4783 bool may_need_copy_shader = pStages[MESA_SHADER_GEOMETRY];
4784 void *main_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[0], NULL);
4785 void *copy_entry = NULL;
4786 if (may_need_copy_shader)
4787 copy_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[1], NULL);
4788
4789 bool has_all_cache_entries = main_entry && (!may_need_copy_shader || copy_entry);
4790 free(main_entry);
4791 free(copy_entry);
4792
4793 if(has_all_cache_entries)
4794 return VK_SUCCESS;
4795
4796 unsigned process = 0;
4797 uint8_t sc_threads = device->instance->num_sc_threads;
4798 while (true) {
4799 mtx_lock(&device->sc_state->secure_compile_mutex);
4800 if (device->sc_state->secure_compile_thread_counter < sc_threads) {
4801 device->sc_state->secure_compile_thread_counter++;
4802 for (unsigned i = 0; i < sc_threads; i++) {
4803 if (!device->sc_state->secure_compile_processes[i].in_use) {
4804 device->sc_state->secure_compile_processes[i].in_use = true;
4805 process = i;
4806 break;
4807 }
4808 }
4809 mtx_unlock(&device->sc_state->secure_compile_mutex);
4810 break;
4811 }
4812 mtx_unlock(&device->sc_state->secure_compile_mutex);
4813 }
4814
4815 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
4816 int fd_secure_output = device->sc_state->secure_compile_processes[process].fd_secure_output;
4817
4818 /* Fork a copy of the slim untainted secure compile process */
4819 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_FORK_DEVICE;
4820 write(fd_secure_input, &sc_type, sizeof(sc_type));
4821
4822 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true) ||
4823 sc_type != RADV_SC_TYPE_INIT_SUCCESS)
4824 return VK_ERROR_DEVICE_LOST;
4825
4826 fd_secure_input = device->sc_state->secure_compile_processes[process].fd_server;
4827 fd_secure_output = device->sc_state->secure_compile_processes[process].fd_client;
4828
4829 /* Write pipeline / shader module out to secure process via pipe */
4830 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE;
4831 write(fd_secure_input, &sc_type, sizeof(sc_type));
4832
4833 /* Write pipeline layout out to secure process */
4834 struct radv_pipeline_layout *layout = pipeline->layout;
4835 write(fd_secure_input, layout, sizeof(struct radv_pipeline_layout));
4836 write(fd_secure_input, &layout->num_sets, sizeof(uint32_t));
4837 for (uint32_t set = 0; set < layout->num_sets; set++) {
4838 write(fd_secure_input, &layout->set[set].layout->layout_size, sizeof(uint32_t));
4839 write(fd_secure_input, layout->set[set].layout, layout->set[set].layout->layout_size);
4840 }
4841
4842 /* Write pipeline key out to secure process */
4843 write(fd_secure_input, key, sizeof(struct radv_pipeline_key));
4844
4845 /* Write pipeline create flags out to secure process */
4846 write(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags));
4847
4848 /* Write stage and shader information out to secure process */
4849 write(fd_secure_input, &num_stages, sizeof(uint32_t));
4850 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
4851 if (!pStages[i])
4852 continue;
4853
4854 /* Write stage out to secure process */
4855 gl_shader_stage stage = ffs(pStages[i]->stage) - 1;
4856 write(fd_secure_input, &stage, sizeof(gl_shader_stage));
4857
4858 /* Write entry point name out to secure process */
4859 size_t name_size = strlen(pStages[i]->pName) + 1;
4860 write(fd_secure_input, &name_size, sizeof(size_t));
4861 write(fd_secure_input, pStages[i]->pName, name_size);
4862
4863 /* Write shader module out to secure process */
4864 struct radv_shader_module *module = radv_shader_module_from_handle(pStages[i]->module);
4865 assert(!module->nir);
4866 size_t module_size = sizeof(struct radv_shader_module) + module->size;
4867 write(fd_secure_input, &module_size, sizeof(size_t));
4868 write(fd_secure_input, module, module_size);
4869
4870 /* Write specialization info out to secure process */
4871 const VkSpecializationInfo *specInfo = pStages[i]->pSpecializationInfo;
4872 bool has_spec_info = specInfo ? true : false;
4873 write(fd_secure_input, &has_spec_info, sizeof(bool));
4874 if (specInfo) {
4875 write(fd_secure_input, &specInfo->dataSize, sizeof(size_t));
4876 write(fd_secure_input, specInfo->pData, specInfo->dataSize);
4877
4878 write(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t));
4879 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++)
4880 write(fd_secure_input, &specInfo->pMapEntries[j], sizeof(VkSpecializationMapEntry));
4881 }
4882 }
4883
4884 /* Read the data returned from the secure process */
4885 while (sc_type != RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED) {
4886 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true))
4887 return VK_ERROR_DEVICE_LOST;
4888
4889 if (sc_type == RADV_SC_TYPE_WRITE_DISK_CACHE) {
4890 assert(device->physical_device->disk_cache);
4891
4892 uint8_t disk_sha1[20];
4893 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4894 return VK_ERROR_DEVICE_LOST;
4895
4896 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4897 memcmp(disk_sha1, allowed_hashes[1], 20))
4898 return VK_ERROR_DEVICE_LOST;
4899
4900 uint32_t entry_size;
4901 if (!radv_sc_read(fd_secure_output, &entry_size, sizeof(uint32_t), true))
4902 return VK_ERROR_DEVICE_LOST;
4903
4904 struct cache_entry *entry = malloc(entry_size);
4905 if (!radv_sc_read(fd_secure_output, entry, entry_size, true))
4906 return VK_ERROR_DEVICE_LOST;
4907
4908 disk_cache_put(device->physical_device->disk_cache,
4909 disk_sha1, entry, entry_size,
4910 NULL);
4911
4912 free(entry);
4913 } else if (sc_type == RADV_SC_TYPE_READ_DISK_CACHE) {
4914 uint8_t disk_sha1[20];
4915 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4916 return VK_ERROR_DEVICE_LOST;
4917
4918 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4919 memcmp(disk_sha1, allowed_hashes[1], 20))
4920 return VK_ERROR_DEVICE_LOST;
4921
4922 size_t size;
4923 struct cache_entry *entry = (struct cache_entry *)
4924 disk_cache_get(device->physical_device->disk_cache,
4925 disk_sha1, &size);
4926
4927 uint8_t found = entry ? 1 : 0;
4928 write(fd_secure_input, &found, sizeof(uint8_t));
4929
4930 if (found) {
4931 write(fd_secure_input, &size, sizeof(size_t));
4932 write(fd_secure_input, entry, size);
4933 }
4934
4935 free(entry);
4936 }
4937 }
4938
4939 sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
4940 write(fd_secure_input, &sc_type, sizeof(sc_type));
4941
4942 mtx_lock(&device->sc_state->secure_compile_mutex);
4943 device->sc_state->secure_compile_thread_counter--;
4944 device->sc_state->secure_compile_processes[process].in_use = false;
4945 mtx_unlock(&device->sc_state->secure_compile_mutex);
4946
4947 return VK_SUCCESS;
4948 }
4949
4950 static VkResult
4951 radv_pipeline_init(struct radv_pipeline *pipeline,
4952 struct radv_device *device,
4953 struct radv_pipeline_cache *cache,
4954 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4955 const struct radv_graphics_pipeline_create_info *extra)
4956 {
4957 VkResult result;
4958 bool has_view_index = false;
4959
4960 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4961 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4962 if (subpass->view_mask)
4963 has_view_index = true;
4964
4965 pipeline->device = device;
4966 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4967 assert(pipeline->layout);
4968
4969 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4970
4971 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4972 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4973 radv_init_feedback(creation_feedback);
4974
4975 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4976
4977 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4978 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4979 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4980 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4981 pStages[stage] = &pCreateInfo->pStages[i];
4982 if(creation_feedback)
4983 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4984 }
4985
4986 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4987 if (radv_device_use_secure_compile(device->instance)) {
4988 return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
4989 } else {
4990 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4991 }
4992
4993 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4994 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4995 uint32_t gs_out;
4996 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4997
4998 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4999
5000 if (radv_pipeline_has_gs(pipeline)) {
5001 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
5002 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5003 } else if (radv_pipeline_has_tess(pipeline)) {
5004 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
5005 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
5006 else
5007 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
5008 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5009 } else {
5010 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
5011 }
5012 if (extra && extra->use_rectlist) {
5013 prim = V_008958_DI_PT_RECTLIST;
5014 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5015 pipeline->graphics.can_use_guardband = true;
5016 if (radv_pipeline_has_ngg(pipeline))
5017 gs_out = V_028A6C_VGT_OUT_RECT_V0;
5018 }
5019 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
5020 /* prim vertex count will need TESS changes */
5021 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
5022
5023 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
5024
5025 /* Ensure that some export memory is always allocated, for two reasons:
5026 *
5027 * 1) Correctness: The hardware ignores the EXEC mask if no export
5028 * memory is allocated, so KILL and alpha test do not work correctly
5029 * without this.
5030 * 2) Performance: Every shader needs at least a NULL export, even when
5031 * it writes no color/depth output. The NULL export instruction
5032 * stalls without this setting.
5033 *
5034 * Don't add this to CB_SHADER_MASK.
5035 *
5036 * GFX10 supports pixel shaders without exports by setting both the
5037 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5038 * instructions if any are present.
5039 */
5040 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
5041 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
5042 ps->info.ps.can_discard) &&
5043 !blend.spi_shader_col_format) {
5044 if (!ps->info.ps.writes_z &&
5045 !ps->info.ps.writes_stencil &&
5046 !ps->info.ps.writes_sample_mask)
5047 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
5048 }
5049
5050 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
5051 if (pipeline->shaders[i]) {
5052 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
5053 }
5054 }
5055
5056 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
5057 struct radv_shader_variant *gs =
5058 pipeline->shaders[MESA_SHADER_GEOMETRY];
5059
5060 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
5061 }
5062
5063 struct radv_tessellation_state tess = {0};
5064 if (radv_pipeline_has_tess(pipeline)) {
5065 if (prim == V_008958_DI_PT_PATCH) {
5066 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
5067 pipeline->graphics.prim_vertex_count.incr = 1;
5068 }
5069 tess = calculate_tess_state(pipeline, pCreateInfo);
5070 }
5071
5072 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
5073
5074 radv_compute_vertex_input_state(pipeline, pCreateInfo);
5075
5076 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
5077 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
5078
5079 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
5080 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
5081 if (loc->sgpr_idx != -1) {
5082 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
5083 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
5084 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
5085 pipeline->graphics.vtx_emit_num = 3;
5086 else
5087 pipeline->graphics.vtx_emit_num = 2;
5088 }
5089
5090 /* Find the last vertex shader stage that eventually uses streamout. */
5091 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
5092
5093 result = radv_pipeline_scratch_init(device, pipeline);
5094 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
5095
5096 return result;
5097 }
5098
5099 VkResult
5100 radv_graphics_pipeline_create(
5101 VkDevice _device,
5102 VkPipelineCache _cache,
5103 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5104 const struct radv_graphics_pipeline_create_info *extra,
5105 const VkAllocationCallbacks *pAllocator,
5106 VkPipeline *pPipeline)
5107 {
5108 RADV_FROM_HANDLE(radv_device, device, _device);
5109 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5110 struct radv_pipeline *pipeline;
5111 VkResult result;
5112
5113 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5114 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5115 if (pipeline == NULL)
5116 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5117
5118 result = radv_pipeline_init(pipeline, device, cache,
5119 pCreateInfo, extra);
5120 if (result != VK_SUCCESS) {
5121 radv_pipeline_destroy(device, pipeline, pAllocator);
5122 return result;
5123 }
5124
5125 *pPipeline = radv_pipeline_to_handle(pipeline);
5126
5127 return VK_SUCCESS;
5128 }
5129
5130 VkResult radv_CreateGraphicsPipelines(
5131 VkDevice _device,
5132 VkPipelineCache pipelineCache,
5133 uint32_t count,
5134 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5135 const VkAllocationCallbacks* pAllocator,
5136 VkPipeline* pPipelines)
5137 {
5138 VkResult result = VK_SUCCESS;
5139 unsigned i = 0;
5140
5141 for (; i < count; i++) {
5142 VkResult r;
5143 r = radv_graphics_pipeline_create(_device,
5144 pipelineCache,
5145 &pCreateInfos[i],
5146 NULL, pAllocator, &pPipelines[i]);
5147 if (r != VK_SUCCESS) {
5148 result = r;
5149 pPipelines[i] = VK_NULL_HANDLE;
5150 }
5151 }
5152
5153 return result;
5154 }
5155
5156
5157 static void
5158 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5159 {
5160 struct radv_shader_variant *compute_shader;
5161 struct radv_device *device = pipeline->device;
5162 unsigned threads_per_threadgroup;
5163 unsigned threadgroups_per_cu = 1;
5164 unsigned waves_per_threadgroup;
5165 unsigned max_waves_per_sh = 0;
5166 uint64_t va;
5167
5168 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5169 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5170
5171 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5172 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5173
5174 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5175 radeon_emit(&pipeline->cs, va >> 8);
5176 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5177
5178 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5179 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5180 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5181 if (device->physical_device->rad_info.chip_class >= GFX10) {
5182 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5183 }
5184
5185 /* Calculate best compute resource limits. */
5186 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5187 compute_shader->info.cs.block_size[1] *
5188 compute_shader->info.cs.block_size[2];
5189 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5190 compute_shader->info.wave_size);
5191
5192 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5193 waves_per_threadgroup == 1)
5194 threadgroups_per_cu = 2;
5195
5196 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5197 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5198 waves_per_threadgroup,
5199 max_waves_per_sh,
5200 threadgroups_per_cu));
5201
5202 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5203 radeon_emit(&pipeline->cs,
5204 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5205 radeon_emit(&pipeline->cs,
5206 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5207 radeon_emit(&pipeline->cs,
5208 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5209
5210 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5211 }
5212
5213 static struct radv_pipeline_key
5214 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5215 const VkComputePipelineCreateInfo *pCreateInfo)
5216 {
5217 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5218 struct radv_pipeline_key key;
5219 memset(&key, 0, sizeof(key));
5220
5221 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5222 key.optimisations_disabled = 1;
5223
5224 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5225 vk_find_struct_const(stage->pNext,
5226 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5227
5228 if (subgroup_size) {
5229 assert(subgroup_size->requiredSubgroupSize == 32 ||
5230 subgroup_size->requiredSubgroupSize == 64);
5231 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5232 }
5233
5234 return key;
5235 }
5236
5237 static VkResult radv_compute_pipeline_create(
5238 VkDevice _device,
5239 VkPipelineCache _cache,
5240 const VkComputePipelineCreateInfo* pCreateInfo,
5241 const VkAllocationCallbacks* pAllocator,
5242 VkPipeline* pPipeline)
5243 {
5244 RADV_FROM_HANDLE(radv_device, device, _device);
5245 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5246 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5247 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5248 struct radv_pipeline *pipeline;
5249 VkResult result;
5250
5251 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5252 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5253 if (pipeline == NULL)
5254 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5255
5256 pipeline->device = device;
5257 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5258 assert(pipeline->layout);
5259
5260 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5261 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5262 radv_init_feedback(creation_feedback);
5263
5264 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5265 if (creation_feedback)
5266 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5267
5268 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5269
5270 struct radv_pipeline_key key =
5271 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5272
5273 if (radv_device_use_secure_compile(device->instance)) {
5274 result = radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, 1);
5275 *pPipeline = radv_pipeline_to_handle(pipeline);
5276
5277 return result;
5278 } else {
5279 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
5280 }
5281
5282 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5283 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5284 result = radv_pipeline_scratch_init(device, pipeline);
5285 if (result != VK_SUCCESS) {
5286 radv_pipeline_destroy(device, pipeline, pAllocator);
5287 return result;
5288 }
5289
5290 radv_compute_generate_pm4(pipeline);
5291
5292 *pPipeline = radv_pipeline_to_handle(pipeline);
5293
5294 return VK_SUCCESS;
5295 }
5296
5297 VkResult radv_CreateComputePipelines(
5298 VkDevice _device,
5299 VkPipelineCache pipelineCache,
5300 uint32_t count,
5301 const VkComputePipelineCreateInfo* pCreateInfos,
5302 const VkAllocationCallbacks* pAllocator,
5303 VkPipeline* pPipelines)
5304 {
5305 VkResult result = VK_SUCCESS;
5306
5307 unsigned i = 0;
5308 for (; i < count; i++) {
5309 VkResult r;
5310 r = radv_compute_pipeline_create(_device, pipelineCache,
5311 &pCreateInfos[i],
5312 pAllocator, &pPipelines[i]);
5313 if (r != VK_SUCCESS) {
5314 result = r;
5315 pPipelines[i] = VK_NULL_HANDLE;
5316 }
5317 }
5318
5319 return result;
5320 }
5321
5322
5323 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5324 {
5325 uint32_t ret = 0;
5326 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5327 if (!pipeline->shaders[i])
5328 continue;
5329
5330 if (i == MESA_SHADER_GEOMETRY &&
5331 !radv_pipeline_has_ngg(pipeline)) {
5332 ret += 2u;
5333 } else {
5334 ret += 1u;
5335 }
5336
5337 }
5338 return ret;
5339 }
5340
5341 static struct radv_shader_variant *
5342 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5343 {
5344 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5345 if (!pipeline->shaders[i])
5346 continue;
5347 if (!index) {
5348 *stage = i;
5349 return pipeline->shaders[i];
5350 }
5351
5352 --index;
5353
5354 if (i == MESA_SHADER_GEOMETRY &&
5355 !radv_pipeline_has_ngg(pipeline)) {
5356 if (!index) {
5357 *stage = i;
5358 return pipeline->gs_copy_shader;
5359 }
5360 --index;
5361 }
5362 }
5363
5364 *stage = -1;
5365 return NULL;
5366 }
5367
5368 /* Basically strlcpy (which does not exist on linux) specialized for
5369 * descriptions. */
5370 static void desc_copy(char *desc, const char *src) {
5371 int len = strlen(src);
5372 assert(len < VK_MAX_DESCRIPTION_SIZE);
5373 memcpy(desc, src, len);
5374 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5375 }
5376
5377 VkResult radv_GetPipelineExecutablePropertiesKHR(
5378 VkDevice _device,
5379 const VkPipelineInfoKHR* pPipelineInfo,
5380 uint32_t* pExecutableCount,
5381 VkPipelineExecutablePropertiesKHR* pProperties)
5382 {
5383 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5384 const uint32_t total_count = radv_get_executable_count(pipeline);
5385
5386 if (!pProperties) {
5387 *pExecutableCount = total_count;
5388 return VK_SUCCESS;
5389 }
5390
5391 const uint32_t count = MIN2(total_count, *pExecutableCount);
5392 for (unsigned i = 0, executable_idx = 0;
5393 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5394 if (!pipeline->shaders[i])
5395 continue;
5396 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5397 const char *name = NULL;
5398 const char *description = NULL;
5399 switch(i) {
5400 case MESA_SHADER_VERTEX:
5401 name = "Vertex Shader";
5402 description = "Vulkan Vertex Shader";
5403 break;
5404 case MESA_SHADER_TESS_CTRL:
5405 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5406 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5407 name = "Vertex + Tessellation Control Shaders";
5408 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5409 } else {
5410 name = "Tessellation Control Shader";
5411 description = "Vulkan Tessellation Control Shader";
5412 }
5413 break;
5414 case MESA_SHADER_TESS_EVAL:
5415 name = "Tessellation Evaluation Shader";
5416 description = "Vulkan Tessellation Evaluation Shader";
5417 break;
5418 case MESA_SHADER_GEOMETRY:
5419 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5420 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5421 name = "Tessellation Evaluation + Geometry Shaders";
5422 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5423 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5424 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5425 name = "Vertex + Geometry Shader";
5426 description = "Combined Vulkan Vertex and Geometry Shaders";
5427 } else {
5428 name = "Geometry Shader";
5429 description = "Vulkan Geometry Shader";
5430 }
5431 break;
5432 case MESA_SHADER_FRAGMENT:
5433 name = "Fragment Shader";
5434 description = "Vulkan Fragment Shader";
5435 break;
5436 case MESA_SHADER_COMPUTE:
5437 name = "Compute Shader";
5438 description = "Vulkan Compute Shader";
5439 break;
5440 }
5441
5442 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5443 desc_copy(pProperties[executable_idx].name, name);
5444 desc_copy(pProperties[executable_idx].description, description);
5445
5446 ++executable_idx;
5447 if (i == MESA_SHADER_GEOMETRY &&
5448 !radv_pipeline_has_ngg(pipeline)) {
5449 assert(pipeline->gs_copy_shader);
5450 if (executable_idx >= count)
5451 break;
5452
5453 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5454 pProperties[executable_idx].subgroupSize = 64;
5455 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5456 desc_copy(pProperties[executable_idx].description,
5457 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5458
5459 ++executable_idx;
5460 }
5461 }
5462
5463 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5464 *pExecutableCount = count;
5465 return result;
5466 }
5467
5468 VkResult radv_GetPipelineExecutableStatisticsKHR(
5469 VkDevice _device,
5470 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5471 uint32_t* pStatisticCount,
5472 VkPipelineExecutableStatisticKHR* pStatistics)
5473 {
5474 RADV_FROM_HANDLE(radv_device, device, _device);
5475 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5476 gl_shader_stage stage;
5477 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5478
5479 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5480 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5481 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5482
5483 VkPipelineExecutableStatisticKHR *s = pStatistics;
5484 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5485 VkResult result = VK_SUCCESS;
5486
5487 if (s < end) {
5488 desc_copy(s->name, "SGPRs");
5489 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5490 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5491 s->value.u64 = shader->config.num_sgprs;
5492 }
5493 ++s;
5494
5495 if (s < end) {
5496 desc_copy(s->name, "VGPRs");
5497 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5498 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5499 s->value.u64 = shader->config.num_vgprs;
5500 }
5501 ++s;
5502
5503 if (s < end) {
5504 desc_copy(s->name, "Spilled SGPRs");
5505 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5506 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5507 s->value.u64 = shader->config.spilled_sgprs;
5508 }
5509 ++s;
5510
5511 if (s < end) {
5512 desc_copy(s->name, "Spilled VGPRs");
5513 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5514 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5515 s->value.u64 = shader->config.spilled_vgprs;
5516 }
5517 ++s;
5518
5519 if (s < end) {
5520 desc_copy(s->name, "PrivMem VGPRs");
5521 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5522 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5523 s->value.u64 = shader->info.private_mem_vgprs;
5524 }
5525 ++s;
5526
5527 if (s < end) {
5528 desc_copy(s->name, "Code size");
5529 desc_copy(s->description, "Code size in bytes");
5530 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5531 s->value.u64 = shader->exec_size;
5532 }
5533 ++s;
5534
5535 if (s < end) {
5536 desc_copy(s->name, "LDS size");
5537 desc_copy(s->description, "LDS size in bytes per workgroup");
5538 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5539 s->value.u64 = shader->config.lds_size * lds_increment;
5540 }
5541 ++s;
5542
5543 if (s < end) {
5544 desc_copy(s->name, "Scratch size");
5545 desc_copy(s->description, "Private memory in bytes per subgroup");
5546 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5547 s->value.u64 = shader->config.scratch_bytes_per_wave;
5548 }
5549 ++s;
5550
5551 if (s < end) {
5552 desc_copy(s->name, "Subgroups per SIMD");
5553 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5554 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5555 s->value.u64 = max_waves;
5556 }
5557 ++s;
5558
5559 if (!pStatistics)
5560 *pStatisticCount = s - pStatistics;
5561 else if (s > end) {
5562 *pStatisticCount = end - pStatistics;
5563 result = VK_INCOMPLETE;
5564 } else {
5565 *pStatisticCount = s - pStatistics;
5566 }
5567
5568 return result;
5569 }
5570
5571 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5572 {
5573 size_t total_size = strlen(src) + 1;
5574
5575 if (!data) {
5576 *data_size = total_size;
5577 return VK_SUCCESS;
5578 }
5579
5580 size_t size = MIN2(total_size, *data_size);
5581
5582 memcpy(data, src, size);
5583 if (size)
5584 *((char*)data + size - 1) = 0;
5585 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5586 }
5587
5588 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5589 VkDevice device,
5590 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5591 uint32_t* pInternalRepresentationCount,
5592 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5593 {
5594 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5595 gl_shader_stage stage;
5596 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5597
5598 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5599 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5600 VkResult result = VK_SUCCESS;
5601 /* optimized NIR */
5602 if (p < end) {
5603 p->isText = true;
5604 desc_copy(p->name, "NIR Shader(s)");
5605 desc_copy(p->description, "The optimized NIR shader(s)");
5606 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5607 result = VK_INCOMPLETE;
5608 }
5609 ++p;
5610
5611 /* backend IR */
5612 if (p < end) {
5613 p->isText = true;
5614 if (shader->aco_used) {
5615 desc_copy(p->name, "ACO IR");
5616 desc_copy(p->description, "The ACO IR after some optimizations");
5617 } else {
5618 desc_copy(p->name, "LLVM IR");
5619 desc_copy(p->description, "The LLVM IR after some optimizations");
5620 }
5621 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5622 result = VK_INCOMPLETE;
5623 }
5624 ++p;
5625
5626 /* Disassembler */
5627 if (p < end) {
5628 p->isText = true;
5629 desc_copy(p->name, "Assembly");
5630 desc_copy(p->description, "Final Assembly");
5631 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5632 result = VK_INCOMPLETE;
5633 }
5634 ++p;
5635
5636 if (!pInternalRepresentations)
5637 *pInternalRepresentationCount = p - pInternalRepresentations;
5638 else if(p > end) {
5639 result = VK_INCOMPLETE;
5640 *pInternalRepresentationCount = end - pInternalRepresentations;
5641 } else {
5642 *pInternalRepresentationCount = p - pInternalRepresentations;
5643 }
5644
5645 return result;
5646 }