2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
33 #include "radv_shader.h"
35 #include "nir/nir_builder.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 #include <llvm-c/Core.h>
41 #include <llvm-c/TargetMachine.h>
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
53 struct radv_blend_state
{
54 uint32_t blend_enable_4bit
;
55 uint32_t need_src_alpha
;
57 uint32_t cb_color_control
;
58 uint32_t cb_target_mask
;
59 uint32_t cb_target_enabled_4bit
;
60 uint32_t sx_mrt_blend_opt
[8];
61 uint32_t cb_blend_control
[8];
63 uint32_t spi_shader_col_format
;
64 uint32_t cb_shader_mask
;
65 uint32_t db_alpha_to_mask
;
67 uint32_t commutative_4bit
;
69 bool single_cb_enable
;
70 bool mrt0_is_dual_src
;
73 struct radv_dsa_order_invariance
{
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
86 struct radv_tessellation_state
{
87 uint32_t ls_hs_config
;
93 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
95 struct radv_shader_variant
*variant
= NULL
;
96 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
97 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
98 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
99 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
100 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
101 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
104 return variant
->info
.is_ngg
;
107 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
109 if (!radv_pipeline_has_gs(pipeline
))
112 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
113 * On GFX10, it might be required in rare cases if it's not possible to
116 if (radv_pipeline_has_ngg(pipeline
))
119 assert(pipeline
->gs_copy_shader
);
124 radv_pipeline_destroy(struct radv_device
*device
,
125 struct radv_pipeline
*pipeline
,
126 const VkAllocationCallbacks
* allocator
)
128 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
129 if (pipeline
->shaders
[i
])
130 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
132 if (pipeline
->gs_copy_shader
)
133 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
136 free(pipeline
->cs
.buf
);
137 vk_free2(&device
->alloc
, allocator
, pipeline
);
140 void radv_DestroyPipeline(
142 VkPipeline _pipeline
,
143 const VkAllocationCallbacks
* pAllocator
)
145 RADV_FROM_HANDLE(radv_device
, device
, _device
);
146 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
151 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
154 static uint32_t get_hash_flags(struct radv_device
*device
)
156 uint32_t hash_flags
= 0;
158 if (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
)
159 hash_flags
|= RADV_HASH_SHADER_UNSAFE_MATH
;
160 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
161 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
162 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
163 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
164 if (device
->physical_device
->cs_wave_size
== 32)
165 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
166 if (device
->physical_device
->ps_wave_size
== 32)
167 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
168 if (device
->physical_device
->ge_wave_size
== 32)
169 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
174 radv_pipeline_scratch_init(struct radv_device
*device
,
175 struct radv_pipeline
*pipeline
)
177 unsigned scratch_bytes_per_wave
= 0;
178 unsigned max_waves
= 0;
179 unsigned min_waves
= 1;
181 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
182 if (pipeline
->shaders
[i
]) {
183 unsigned max_stage_waves
= device
->scratch_waves
;
185 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
186 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
188 max_stage_waves
= MIN2(max_stage_waves
,
189 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
190 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
191 max_waves
= MAX2(max_waves
, max_stage_waves
);
195 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
196 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
197 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
198 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
199 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
202 if (scratch_bytes_per_wave
)
203 max_waves
= MIN2(max_waves
, 0xffffffffu
/ scratch_bytes_per_wave
);
205 if (scratch_bytes_per_wave
&& max_waves
< min_waves
) {
206 /* Not really true at this moment, but will be true on first
207 * execution. Avoid having hanging shaders. */
208 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
210 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
211 pipeline
->max_waves
= max_waves
;
215 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
218 case VK_LOGIC_OP_CLEAR
:
219 return V_028808_ROP3_CLEAR
;
220 case VK_LOGIC_OP_AND
:
221 return V_028808_ROP3_AND
;
222 case VK_LOGIC_OP_AND_REVERSE
:
223 return V_028808_ROP3_AND_REVERSE
;
224 case VK_LOGIC_OP_COPY
:
225 return V_028808_ROP3_COPY
;
226 case VK_LOGIC_OP_AND_INVERTED
:
227 return V_028808_ROP3_AND_INVERTED
;
228 case VK_LOGIC_OP_NO_OP
:
229 return V_028808_ROP3_NO_OP
;
230 case VK_LOGIC_OP_XOR
:
231 return V_028808_ROP3_XOR
;
233 return V_028808_ROP3_OR
;
234 case VK_LOGIC_OP_NOR
:
235 return V_028808_ROP3_NOR
;
236 case VK_LOGIC_OP_EQUIVALENT
:
237 return V_028808_ROP3_EQUIVALENT
;
238 case VK_LOGIC_OP_INVERT
:
239 return V_028808_ROP3_INVERT
;
240 case VK_LOGIC_OP_OR_REVERSE
:
241 return V_028808_ROP3_OR_REVERSE
;
242 case VK_LOGIC_OP_COPY_INVERTED
:
243 return V_028808_ROP3_COPY_INVERTED
;
244 case VK_LOGIC_OP_OR_INVERTED
:
245 return V_028808_ROP3_OR_INVERTED
;
246 case VK_LOGIC_OP_NAND
:
247 return V_028808_ROP3_NAND
;
248 case VK_LOGIC_OP_SET
:
249 return V_028808_ROP3_SET
;
251 unreachable("Unhandled logic op");
256 static uint32_t si_translate_blend_function(VkBlendOp op
)
259 case VK_BLEND_OP_ADD
:
260 return V_028780_COMB_DST_PLUS_SRC
;
261 case VK_BLEND_OP_SUBTRACT
:
262 return V_028780_COMB_SRC_MINUS_DST
;
263 case VK_BLEND_OP_REVERSE_SUBTRACT
:
264 return V_028780_COMB_DST_MINUS_SRC
;
265 case VK_BLEND_OP_MIN
:
266 return V_028780_COMB_MIN_DST_SRC
;
267 case VK_BLEND_OP_MAX
:
268 return V_028780_COMB_MAX_DST_SRC
;
274 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
277 case VK_BLEND_FACTOR_ZERO
:
278 return V_028780_BLEND_ZERO
;
279 case VK_BLEND_FACTOR_ONE
:
280 return V_028780_BLEND_ONE
;
281 case VK_BLEND_FACTOR_SRC_COLOR
:
282 return V_028780_BLEND_SRC_COLOR
;
283 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
284 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
285 case VK_BLEND_FACTOR_DST_COLOR
:
286 return V_028780_BLEND_DST_COLOR
;
287 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
288 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
289 case VK_BLEND_FACTOR_SRC_ALPHA
:
290 return V_028780_BLEND_SRC_ALPHA
;
291 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
292 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
293 case VK_BLEND_FACTOR_DST_ALPHA
:
294 return V_028780_BLEND_DST_ALPHA
;
295 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
296 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
297 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
298 return V_028780_BLEND_CONSTANT_COLOR
;
299 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
300 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
301 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
302 return V_028780_BLEND_CONSTANT_ALPHA
;
303 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
304 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
305 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
306 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
307 case VK_BLEND_FACTOR_SRC1_COLOR
:
308 return V_028780_BLEND_SRC1_COLOR
;
309 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
310 return V_028780_BLEND_INV_SRC1_COLOR
;
311 case VK_BLEND_FACTOR_SRC1_ALPHA
:
312 return V_028780_BLEND_SRC1_ALPHA
;
313 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
314 return V_028780_BLEND_INV_SRC1_ALPHA
;
320 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
323 case VK_BLEND_OP_ADD
:
324 return V_028760_OPT_COMB_ADD
;
325 case VK_BLEND_OP_SUBTRACT
:
326 return V_028760_OPT_COMB_SUBTRACT
;
327 case VK_BLEND_OP_REVERSE_SUBTRACT
:
328 return V_028760_OPT_COMB_REVSUBTRACT
;
329 case VK_BLEND_OP_MIN
:
330 return V_028760_OPT_COMB_MIN
;
331 case VK_BLEND_OP_MAX
:
332 return V_028760_OPT_COMB_MAX
;
334 return V_028760_OPT_COMB_BLEND_DISABLED
;
338 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
341 case VK_BLEND_FACTOR_ZERO
:
342 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
343 case VK_BLEND_FACTOR_ONE
:
344 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
345 case VK_BLEND_FACTOR_SRC_COLOR
:
346 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
347 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
348 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
349 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
350 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
351 case VK_BLEND_FACTOR_SRC_ALPHA
:
352 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
353 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
354 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
355 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
356 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
357 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
364 * Get rid of DST in the blend factors by commuting the operands:
365 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
367 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
368 unsigned *dst_factor
, unsigned expected_dst
,
369 unsigned replacement_src
)
371 if (*src_factor
== expected_dst
&&
372 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
373 *src_factor
= VK_BLEND_FACTOR_ZERO
;
374 *dst_factor
= replacement_src
;
376 /* Commuting the operands requires reversing subtractions. */
377 if (*func
== VK_BLEND_OP_SUBTRACT
)
378 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
379 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
380 *func
= VK_BLEND_OP_SUBTRACT
;
384 static bool si_blend_factor_uses_dst(unsigned factor
)
386 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
387 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
388 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
389 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
390 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
393 static bool is_dual_src(VkBlendFactor factor
)
396 case VK_BLEND_FACTOR_SRC1_COLOR
:
397 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
398 case VK_BLEND_FACTOR_SRC1_ALPHA
:
399 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
406 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
408 bool blend_need_alpha
)
410 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
411 unsigned format
, ntype
, swap
;
413 /* Alpha is needed for alpha-to-coverage.
414 * Blending may be with or without alpha.
416 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
417 unsigned alpha
= 0; /* exports alpha, but may not support blending */
418 unsigned blend
= 0; /* supports blending, but may not export alpha */
419 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
421 format
= radv_translate_colorformat(vk_format
);
422 ntype
= radv_translate_color_numformat(vk_format
, desc
,
423 vk_format_get_first_non_void_channel(vk_format
));
424 swap
= radv_translate_colorswap(vk_format
, false);
426 /* Choose the SPI color formats. These are required values for Stoney/RB+.
427 * Other chips have multiple choices, though they are not necessarily better.
430 case V_028C70_COLOR_5_6_5
:
431 case V_028C70_COLOR_1_5_5_5
:
432 case V_028C70_COLOR_5_5_5_1
:
433 case V_028C70_COLOR_4_4_4_4
:
434 case V_028C70_COLOR_10_11_11
:
435 case V_028C70_COLOR_11_11_10
:
436 case V_028C70_COLOR_8
:
437 case V_028C70_COLOR_8_8
:
438 case V_028C70_COLOR_8_8_8_8
:
439 case V_028C70_COLOR_10_10_10_2
:
440 case V_028C70_COLOR_2_10_10_10
:
441 if (ntype
== V_028C70_NUMBER_UINT
)
442 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
443 else if (ntype
== V_028C70_NUMBER_SINT
)
444 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
446 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
449 case V_028C70_COLOR_16
:
450 case V_028C70_COLOR_16_16
:
451 case V_028C70_COLOR_16_16_16_16
:
452 if (ntype
== V_028C70_NUMBER_UNORM
||
453 ntype
== V_028C70_NUMBER_SNORM
) {
454 /* UNORM16 and SNORM16 don't support blending */
455 if (ntype
== V_028C70_NUMBER_UNORM
)
456 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
458 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
460 /* Use 32 bits per channel for blending. */
461 if (format
== V_028C70_COLOR_16
) {
462 if (swap
== V_028C70_SWAP_STD
) { /* R */
463 blend
= V_028714_SPI_SHADER_32_R
;
464 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
465 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
466 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
469 } else if (format
== V_028C70_COLOR_16_16
) {
470 if (swap
== V_028C70_SWAP_STD
) { /* RG */
471 blend
= V_028714_SPI_SHADER_32_GR
;
472 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
473 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
474 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
477 } else /* 16_16_16_16 */
478 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
479 } else if (ntype
== V_028C70_NUMBER_UINT
)
480 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
481 else if (ntype
== V_028C70_NUMBER_SINT
)
482 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
483 else if (ntype
== V_028C70_NUMBER_FLOAT
)
484 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
489 case V_028C70_COLOR_32
:
490 if (swap
== V_028C70_SWAP_STD
) { /* R */
491 blend
= normal
= V_028714_SPI_SHADER_32_R
;
492 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
493 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
494 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
499 case V_028C70_COLOR_32_32
:
500 if (swap
== V_028C70_SWAP_STD
) { /* RG */
501 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
502 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
503 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
504 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
509 case V_028C70_COLOR_32_32_32_32
:
510 case V_028C70_COLOR_8_24
:
511 case V_028C70_COLOR_24_8
:
512 case V_028C70_COLOR_X24_8_32_FLOAT
:
513 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
517 unreachable("unhandled blend format");
520 if (blend_enable
&& blend_need_alpha
)
522 else if(blend_need_alpha
)
524 else if(blend_enable
)
531 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
532 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
533 struct radv_blend_state
*blend
)
535 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
536 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
537 unsigned col_format
= 0;
538 unsigned num_targets
;
540 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
543 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
544 cf
= V_028714_SPI_SHADER_ZERO
;
546 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
548 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
550 cf
= si_choose_spi_color_format(attachment
->format
,
552 blend
->need_src_alpha
& (1 << i
));
555 col_format
|= cf
<< (4 * i
);
558 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
559 /* When a subpass doesn't have any color attachments, write the
560 * alpha channel of MRT0 when alpha coverage is enabled because
561 * the depth attachment needs it.
563 col_format
|= V_028714_SPI_SHADER_32_AR
;
566 /* If the i-th target format is set, all previous target formats must
567 * be non-zero to avoid hangs.
569 num_targets
= (util_last_bit(col_format
) + 3) / 4;
570 for (unsigned i
= 0; i
< num_targets
; i
++) {
571 if (!(col_format
& (0xf << (i
* 4)))) {
572 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
576 /* The output for dual source blending should have the same format as
579 if (blend
->mrt0_is_dual_src
)
580 col_format
|= (col_format
& 0xf) << 4;
582 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
583 blend
->spi_shader_col_format
= col_format
;
587 format_is_int8(VkFormat format
)
589 const struct vk_format_description
*desc
= vk_format_description(format
);
590 int channel
= vk_format_get_first_non_void_channel(format
);
592 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
593 desc
->channel
[channel
].size
== 8;
597 format_is_int10(VkFormat format
)
599 const struct vk_format_description
*desc
= vk_format_description(format
);
601 if (desc
->nr_channels
!= 4)
603 for (unsigned i
= 0; i
< 4; i
++) {
604 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
611 * Ordered so that for each i,
612 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
614 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
615 VK_FORMAT_R32_SFLOAT
,
616 VK_FORMAT_R32G32_SFLOAT
,
617 VK_FORMAT_R8G8B8A8_UNORM
,
618 VK_FORMAT_R16G16B16A16_UNORM
,
619 VK_FORMAT_R16G16B16A16_SNORM
,
620 VK_FORMAT_R16G16B16A16_UINT
,
621 VK_FORMAT_R16G16B16A16_SINT
,
622 VK_FORMAT_R32G32B32A32_SFLOAT
,
623 VK_FORMAT_R8G8B8A8_UINT
,
624 VK_FORMAT_R8G8B8A8_SINT
,
625 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
626 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
629 unsigned radv_format_meta_fs_key(VkFormat format
)
631 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
633 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
634 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
635 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
637 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
638 bool is_int8
= format_is_int8(format
);
639 bool is_int10
= format_is_int10(format
);
641 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
645 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
646 unsigned *is_int8
, unsigned *is_int10
)
648 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
649 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
653 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
654 struct radv_render_pass_attachment
*attachment
;
656 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
659 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
661 if (format_is_int8(attachment
->format
))
663 if (format_is_int10(attachment
->format
))
669 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
670 VkBlendOp op
, VkBlendFactor src
,
671 VkBlendFactor dst
, unsigned chanmask
)
673 /* Src factor is allowed when it does not depend on Dst. */
674 static const uint32_t src_allowed
=
675 (1u << VK_BLEND_FACTOR_ONE
) |
676 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
677 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
678 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
679 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
680 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
681 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
682 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
683 (1u << VK_BLEND_FACTOR_ZERO
) |
684 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
685 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
686 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
687 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
688 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
689 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
691 if (dst
== VK_BLEND_FACTOR_ONE
&&
692 (src_allowed
& (1u << src
))) {
693 /* Addition is commutative, but floating point addition isn't
694 * associative: subtle changes can be introduced via different
695 * rounding. Be conservative, only enable for min and max.
697 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
698 blend
->commutative_4bit
|= chanmask
;
702 static struct radv_blend_state
703 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
704 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
705 const struct radv_graphics_pipeline_create_info
*extra
)
707 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
708 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
709 struct radv_blend_state blend
= {0};
710 unsigned mode
= V_028808_CB_NORMAL
;
716 if (extra
&& extra
->custom_blend_mode
) {
717 blend
.single_cb_enable
= true;
718 mode
= extra
->custom_blend_mode
;
720 blend
.cb_color_control
= 0;
721 if (vkblend
->logicOpEnable
)
722 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
724 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
726 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
727 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
728 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
729 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
730 S_028B70_OFFSET_ROUND(1);
732 if (vkms
&& vkms
->alphaToCoverageEnable
) {
733 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
734 blend
.need_src_alpha
|= 0x1;
737 blend
.cb_target_mask
= 0;
738 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
739 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
740 unsigned blend_cntl
= 0;
741 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
742 VkBlendOp eqRGB
= att
->colorBlendOp
;
743 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
744 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
745 VkBlendOp eqA
= att
->alphaBlendOp
;
746 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
747 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
749 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
751 if (!att
->colorWriteMask
)
754 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
755 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
756 if (!att
->blendEnable
) {
757 blend
.cb_blend_control
[i
] = blend_cntl
;
761 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
763 blend
.mrt0_is_dual_src
= true;
765 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
766 srcRGB
= VK_BLEND_FACTOR_ONE
;
767 dstRGB
= VK_BLEND_FACTOR_ONE
;
769 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
770 srcA
= VK_BLEND_FACTOR_ONE
;
771 dstA
= VK_BLEND_FACTOR_ONE
;
774 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
776 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
779 /* Blending optimizations for RB+.
780 * These transformations don't change the behavior.
782 * First, get rid of DST in the blend factors:
783 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
785 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
786 VK_BLEND_FACTOR_DST_COLOR
,
787 VK_BLEND_FACTOR_SRC_COLOR
);
789 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
790 VK_BLEND_FACTOR_DST_COLOR
,
791 VK_BLEND_FACTOR_SRC_COLOR
);
793 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
794 VK_BLEND_FACTOR_DST_ALPHA
,
795 VK_BLEND_FACTOR_SRC_ALPHA
);
797 /* Look up the ideal settings from tables. */
798 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
799 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
800 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
801 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
803 /* Handle interdependencies. */
804 if (si_blend_factor_uses_dst(srcRGB
))
805 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
806 if (si_blend_factor_uses_dst(srcA
))
807 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
809 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
810 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
811 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
812 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
813 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
815 /* Set the final value. */
816 blend
.sx_mrt_blend_opt
[i
] =
817 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
818 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
819 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
820 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
821 S_028760_ALPHA_DST_OPT(dstA_opt
) |
822 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
823 blend_cntl
|= S_028780_ENABLE(1);
825 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
826 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
827 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
828 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
829 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
830 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
831 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
832 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
834 blend
.cb_blend_control
[i
] = blend_cntl
;
836 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
838 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
839 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
840 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
841 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
842 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
843 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
844 blend
.need_src_alpha
|= 1 << i
;
846 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
847 blend
.cb_blend_control
[i
] = 0;
848 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
851 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
852 /* Disable RB+ blend optimizations for dual source blending. */
853 if (blend
.mrt0_is_dual_src
) {
854 for (i
= 0; i
< 8; i
++) {
855 blend
.sx_mrt_blend_opt
[i
] =
856 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
857 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
861 /* RB+ doesn't work with dual source blending, logic op and
864 if (blend
.mrt0_is_dual_src
|| vkblend
->logicOpEnable
||
865 mode
== V_028808_CB_RESOLVE
)
866 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
869 if (blend
.cb_target_mask
)
870 blend
.cb_color_control
|= S_028808_MODE(mode
);
872 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
874 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
878 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
881 case VK_STENCIL_OP_KEEP
:
882 return V_02842C_STENCIL_KEEP
;
883 case VK_STENCIL_OP_ZERO
:
884 return V_02842C_STENCIL_ZERO
;
885 case VK_STENCIL_OP_REPLACE
:
886 return V_02842C_STENCIL_REPLACE_TEST
;
887 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
888 return V_02842C_STENCIL_ADD_CLAMP
;
889 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
890 return V_02842C_STENCIL_SUB_CLAMP
;
891 case VK_STENCIL_OP_INVERT
:
892 return V_02842C_STENCIL_INVERT
;
893 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
894 return V_02842C_STENCIL_ADD_WRAP
;
895 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
896 return V_02842C_STENCIL_SUB_WRAP
;
902 static uint32_t si_translate_fill(VkPolygonMode func
)
905 case VK_POLYGON_MODE_FILL
:
906 return V_028814_X_DRAW_TRIANGLES
;
907 case VK_POLYGON_MODE_LINE
:
908 return V_028814_X_DRAW_LINES
;
909 case VK_POLYGON_MODE_POINT
:
910 return V_028814_X_DRAW_POINTS
;
913 return V_028814_X_DRAW_POINTS
;
917 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo
*vkms
)
919 uint32_t num_samples
= vkms
->rasterizationSamples
;
920 uint32_t ps_iter_samples
= 1;
922 if (vkms
->sampleShadingEnable
) {
923 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
924 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
926 return ps_iter_samples
;
930 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
932 return pCreateInfo
->depthTestEnable
&&
933 pCreateInfo
->depthWriteEnable
&&
934 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
938 radv_writes_stencil(const VkStencilOpState
*state
)
940 return state
->writeMask
&&
941 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
942 state
->passOp
!= VK_STENCIL_OP_KEEP
||
943 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
947 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
949 return pCreateInfo
->stencilTestEnable
&&
950 (radv_writes_stencil(&pCreateInfo
->front
) ||
951 radv_writes_stencil(&pCreateInfo
->back
));
955 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
957 return radv_is_depth_write_enabled(pCreateInfo
) ||
958 radv_is_stencil_write_enabled(pCreateInfo
);
962 radv_order_invariant_stencil_op(VkStencilOp op
)
964 /* REPLACE is normally order invariant, except when the stencil
965 * reference value is written by the fragment shader. Tracking this
966 * interaction does not seem worth the effort, so be conservative.
968 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
969 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
970 op
!= VK_STENCIL_OP_REPLACE
;
974 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
976 /* Compute whether, assuming Z writes are disabled, this stencil state
977 * is order invariant in the sense that the set of passing fragments as
978 * well as the final stencil buffer result does not depend on the order
981 return !state
->writeMask
||
982 /* The following assumes that Z writes are disabled. */
983 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
984 radv_order_invariant_stencil_op(state
->passOp
) &&
985 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
986 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
987 radv_order_invariant_stencil_op(state
->failOp
));
991 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
992 struct radv_blend_state
*blend
,
993 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
995 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
996 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
997 unsigned colormask
= blend
->cb_target_enabled_4bit
;
999 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
1002 /* Be conservative if a logic operation is enabled with color buffers. */
1003 if (colormask
&& pCreateInfo
->pColorBlendState
->logicOpEnable
)
1006 /* Default depth/stencil invariance when no attachment is bound. */
1007 struct radv_dsa_order_invariance dsa_order_invariant
= {
1008 .zs
= true, .pass_set
= true
1011 if (pCreateInfo
->pDepthStencilState
&&
1012 subpass
->depth_stencil_attachment
) {
1013 const VkPipelineDepthStencilStateCreateInfo
*vkds
=
1014 pCreateInfo
->pDepthStencilState
;
1015 struct radv_render_pass_attachment
*attachment
=
1016 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
1017 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
1018 struct radv_dsa_order_invariance order_invariance
[2];
1019 struct radv_shader_variant
*ps
=
1020 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1022 /* Compute depth/stencil order invariance in order to know if
1023 * it's safe to enable out-of-order.
1025 bool zfunc_is_ordered
=
1026 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
1027 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
1028 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
1029 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
1030 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1032 bool nozwrite_and_order_invariant_stencil
=
1033 !radv_is_ds_write_enabled(vkds
) ||
1034 (!radv_is_depth_write_enabled(vkds
) &&
1035 radv_order_invariant_stencil_state(&vkds
->front
) &&
1036 radv_order_invariant_stencil_state(&vkds
->back
));
1038 order_invariance
[1].zs
=
1039 nozwrite_and_order_invariant_stencil
||
1040 (!radv_is_stencil_write_enabled(vkds
) &&
1042 order_invariance
[0].zs
=
1043 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1045 order_invariance
[1].pass_set
=
1046 nozwrite_and_order_invariant_stencil
||
1047 (!radv_is_stencil_write_enabled(vkds
) &&
1048 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1049 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1050 order_invariance
[0].pass_set
=
1051 !radv_is_depth_write_enabled(vkds
) ||
1052 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1053 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1055 dsa_order_invariant
= order_invariance
[has_stencil
];
1056 if (!dsa_order_invariant
.zs
)
1059 /* The set of PS invocations is always order invariant,
1060 * except when early Z/S tests are requested.
1063 ps
->info
.ps
.writes_memory
&&
1064 ps
->info
.ps
.early_fragment_test
&&
1065 !dsa_order_invariant
.pass_set
)
1068 /* Determine if out-of-order rasterization should be disabled
1069 * when occlusion queries are used.
1071 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1072 !dsa_order_invariant
.pass_set
;
1075 /* No color buffers are enabled for writing. */
1079 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1082 /* Only commutative blending. */
1083 if (blendmask
& ~blend
->commutative_4bit
)
1086 if (!dsa_order_invariant
.pass_set
)
1090 if (colormask
& ~blendmask
)
1097 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1098 struct radv_blend_state
*blend
,
1099 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1101 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
1102 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1103 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1104 bool out_of_order_rast
= false;
1105 int ps_iter_samples
= 1;
1106 uint32_t mask
= 0xffff;
1109 ms
->num_samples
= vkms
->rasterizationSamples
;
1111 ms
->num_samples
= 1;
1114 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
1115 if (vkms
&& !vkms
->sampleShadingEnable
&& pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1116 ps_iter_samples
= ms
->num_samples
;
1119 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1120 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1121 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1122 /* Out-of-order rasterization is explicitly enabled by the
1125 out_of_order_rast
= true;
1127 /* Determine if the driver can enable out-of-order
1128 * rasterization internally.
1131 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1134 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1135 ms
->pa_sc_aa_config
= 0;
1136 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1137 S_028804_INCOHERENT_EQAA_READS(1) |
1138 S_028804_INTERPOLATE_COMP_Z(1) |
1139 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1140 ms
->pa_sc_mode_cntl_1
=
1141 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1142 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1143 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1144 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1146 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1147 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1148 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1149 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1150 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1151 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1152 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1153 S_028A48_VPORT_SCISSOR_ENABLE(1);
1155 if (ms
->num_samples
> 1) {
1156 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1157 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1158 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1159 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1160 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1161 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1162 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1163 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1164 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1165 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1166 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1167 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1168 if (ps_iter_samples
> 1)
1169 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1172 if (vkms
&& vkms
->pSampleMask
) {
1173 mask
= vkms
->pSampleMask
[0] & 0xffff;
1176 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1177 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1181 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1184 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1187 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1188 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1193 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1194 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1195 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1198 unreachable("unhandled primitive type");
1203 si_translate_prim(enum VkPrimitiveTopology topology
)
1206 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1207 return V_008958_DI_PT_POINTLIST
;
1208 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1209 return V_008958_DI_PT_LINELIST
;
1210 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1211 return V_008958_DI_PT_LINESTRIP
;
1212 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1213 return V_008958_DI_PT_TRILIST
;
1214 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1215 return V_008958_DI_PT_TRISTRIP
;
1216 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1217 return V_008958_DI_PT_TRIFAN
;
1218 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1219 return V_008958_DI_PT_LINELIST_ADJ
;
1220 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1221 return V_008958_DI_PT_LINESTRIP_ADJ
;
1222 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1223 return V_008958_DI_PT_TRILIST_ADJ
;
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1225 return V_008958_DI_PT_TRISTRIP_ADJ
;
1226 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1227 return V_008958_DI_PT_PATCH
;
1235 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1238 case 0: /* GL_POINTS */
1239 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1240 case 1: /* GL_LINES */
1241 case 3: /* GL_LINE_STRIP */
1242 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1243 case 0x8E7A: /* GL_ISOLINES */
1244 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1246 case 4: /* GL_TRIANGLES */
1247 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1248 case 5: /* GL_TRIANGLE_STRIP */
1249 case 7: /* GL_QUADS */
1250 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1258 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1261 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1262 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1263 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1264 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1265 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1266 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1267 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1268 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1269 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1270 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1271 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1272 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1273 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1274 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1281 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1284 case VK_DYNAMIC_STATE_VIEWPORT
:
1285 return RADV_DYNAMIC_VIEWPORT
;
1286 case VK_DYNAMIC_STATE_SCISSOR
:
1287 return RADV_DYNAMIC_SCISSOR
;
1288 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1289 return RADV_DYNAMIC_LINE_WIDTH
;
1290 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1291 return RADV_DYNAMIC_DEPTH_BIAS
;
1292 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1293 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1294 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1295 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1296 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1297 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1298 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1299 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1300 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1301 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1302 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1303 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1304 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1305 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1307 unreachable("Unhandled dynamic state");
1311 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1313 uint32_t states
= RADV_DYNAMIC_ALL
;
1315 /* If rasterization is disabled we do not care about any of the dynamic states,
1316 * since they are all rasterization related only. */
1317 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1320 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1321 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1323 if (!pCreateInfo
->pDepthStencilState
||
1324 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1325 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1327 if (!pCreateInfo
->pDepthStencilState
||
1328 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1329 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1330 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1331 RADV_DYNAMIC_STENCIL_REFERENCE
);
1333 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1334 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1336 if (!pCreateInfo
->pMultisampleState
||
1337 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1338 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1339 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1341 /* TODO: blend constants & line width. */
1348 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1349 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1351 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1352 uint32_t states
= needed_states
;
1353 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1354 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1356 pipeline
->dynamic_state
= default_dynamic_state
;
1357 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1359 if (pCreateInfo
->pDynamicState
) {
1360 /* Remove all of the states that are marked as dynamic */
1361 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1362 for (uint32_t s
= 0; s
< count
; s
++)
1363 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1366 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1368 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1369 assert(pCreateInfo
->pViewportState
);
1371 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1372 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1373 typed_memcpy(dynamic
->viewport
.viewports
,
1374 pCreateInfo
->pViewportState
->pViewports
,
1375 pCreateInfo
->pViewportState
->viewportCount
);
1379 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1380 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1381 if (states
& RADV_DYNAMIC_SCISSOR
) {
1382 typed_memcpy(dynamic
->scissor
.scissors
,
1383 pCreateInfo
->pViewportState
->pScissors
,
1384 pCreateInfo
->pViewportState
->scissorCount
);
1388 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1389 assert(pCreateInfo
->pRasterizationState
);
1390 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1393 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1394 assert(pCreateInfo
->pRasterizationState
);
1395 dynamic
->depth_bias
.bias
=
1396 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1397 dynamic
->depth_bias
.clamp
=
1398 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1399 dynamic
->depth_bias
.slope
=
1400 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1403 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1405 * pColorBlendState is [...] NULL if the pipeline has rasterization
1406 * disabled or if the subpass of the render pass the pipeline is
1407 * created against does not use any color attachments.
1409 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1410 assert(pCreateInfo
->pColorBlendState
);
1411 typed_memcpy(dynamic
->blend_constants
,
1412 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1415 /* If there is no depthstencil attachment, then don't read
1416 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1417 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1418 * no need to override the depthstencil defaults in
1419 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1421 * Section 9.2 of the Vulkan 1.0.15 spec says:
1423 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1424 * disabled or if the subpass of the render pass the pipeline is created
1425 * against does not use a depth/stencil attachment.
1427 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1428 assert(pCreateInfo
->pDepthStencilState
);
1430 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1431 dynamic
->depth_bounds
.min
=
1432 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1433 dynamic
->depth_bounds
.max
=
1434 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1437 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1438 dynamic
->stencil_compare_mask
.front
=
1439 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1440 dynamic
->stencil_compare_mask
.back
=
1441 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1444 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1445 dynamic
->stencil_write_mask
.front
=
1446 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1447 dynamic
->stencil_write_mask
.back
=
1448 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1451 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1452 dynamic
->stencil_reference
.front
=
1453 pCreateInfo
->pDepthStencilState
->front
.reference
;
1454 dynamic
->stencil_reference
.back
=
1455 pCreateInfo
->pDepthStencilState
->back
.reference
;
1459 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1460 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1461 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1462 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1463 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1464 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1465 discard_rectangle_info
->pDiscardRectangles
,
1466 discard_rectangle_info
->discardRectangleCount
);
1470 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1471 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1472 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1473 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1474 /* If sampleLocationsEnable is VK_FALSE, the default sample
1475 * locations are used and the values specified in
1476 * sampleLocationsInfo are ignored.
1478 if (sample_location_info
->sampleLocationsEnable
) {
1479 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1480 &sample_location_info
->sampleLocationsInfo
;
1482 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1484 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1485 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1486 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1487 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1488 pSampleLocationsInfo
->pSampleLocations
,
1489 pSampleLocationsInfo
->sampleLocationsCount
);
1493 pipeline
->dynamic_state
.mask
= states
;
1497 gfx9_get_gs_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1498 const struct radv_pipeline
*pipeline
,
1500 struct radv_shader_info
*infos
,
1501 struct gfx9_gs_info
*out
)
1503 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1504 struct radv_es_output_info
*es_info
;
1505 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1506 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1508 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1509 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1510 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1512 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1513 bool uses_adjacency
;
1514 switch(pCreateInfo
->pInputAssemblyState
->topology
) {
1515 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1516 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1517 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1518 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1519 uses_adjacency
= true;
1522 uses_adjacency
= false;
1526 /* All these are in dwords: */
1527 /* We can't allow using the whole LDS, because GS waves compete with
1528 * other shader stages for LDS space. */
1529 const unsigned max_lds_size
= 8 * 1024;
1530 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1531 unsigned esgs_lds_size
;
1533 /* All these are per subgroup: */
1534 const unsigned max_out_prims
= 32 * 1024;
1535 const unsigned max_es_verts
= 255;
1536 const unsigned ideal_gs_prims
= 64;
1537 unsigned max_gs_prims
, gs_prims
;
1538 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1540 if (uses_adjacency
|| gs_num_invocations
> 1)
1541 max_gs_prims
= 127 / gs_num_invocations
;
1545 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1546 * Make sure we don't go over the maximum value.
1548 if (gs_info
->gs
.vertices_out
> 0) {
1549 max_gs_prims
= MIN2(max_gs_prims
,
1551 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1553 assert(max_gs_prims
> 0);
1555 /* If the primitive has adjacency, halve the number of vertices
1556 * that will be reused in multiple primitives.
1558 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1560 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1561 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1563 /* Compute ESGS LDS size based on the worst case number of ES vertices
1564 * needed to create the target number of GS prims per subgroup.
1566 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1568 /* If total LDS usage is too big, refactor partitions based on ratio
1569 * of ESGS item sizes.
1571 if (esgs_lds_size
> max_lds_size
) {
1572 /* Our target GS Prims Per Subgroup was too large. Calculate
1573 * the maximum number of GS Prims Per Subgroup that will fit
1574 * into LDS, capped by the maximum that the hardware can support.
1576 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1578 assert(gs_prims
> 0);
1579 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1582 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1583 assert(esgs_lds_size
<= max_lds_size
);
1586 /* Now calculate remaining ESGS information. */
1588 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1590 es_verts
= max_es_verts
;
1592 /* Vertices for adjacency primitives are not always reused, so restore
1593 * it for ES_VERTS_PER_SUBGRP.
1595 min_es_verts
= gs_info
->gs
.vertices_in
;
1597 /* For normal primitives, the VGT only checks if they are past the ES
1598 * verts per subgroup after allocating a full GS primitive and if they
1599 * are, kick off a new subgroup. But if those additional ES verts are
1600 * unique (e.g. not reused) we need to make sure there is enough LDS
1601 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1603 es_verts
-= min_es_verts
- 1;
1605 uint32_t es_verts_per_subgroup
= es_verts
;
1606 uint32_t gs_prims_per_subgroup
= gs_prims
;
1607 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1608 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1609 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1610 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1611 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1612 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1613 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1614 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1615 assert(max_prims_per_subgroup
<= max_out_prims
);
1618 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1619 unsigned min_verts_per_prim
, bool use_adjacency
)
1621 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1624 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1628 radv_get_num_input_vertices(nir_shader
**nir
)
1630 if (nir
[MESA_SHADER_GEOMETRY
]) {
1631 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1633 return gs
->info
.gs
.vertices_in
;
1636 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1637 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1639 if (tes
->info
.tess
.point_mode
)
1641 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1650 gfx10_get_ngg_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1651 struct radv_pipeline
*pipeline
,
1653 struct radv_shader_info
*infos
,
1654 struct gfx10_ngg_info
*ngg
)
1656 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1657 struct radv_es_output_info
*es_info
=
1658 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1659 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1660 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1661 unsigned min_verts_per_prim
=
1662 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1663 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1664 bool uses_adjacency
;
1665 switch(pCreateInfo
->pInputAssemblyState
->topology
) {
1666 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1667 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1668 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1669 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1670 uses_adjacency
= true;
1673 uses_adjacency
= false;
1677 /* All these are in dwords: */
1678 /* We can't allow using the whole LDS, because GS waves compete with
1679 * other shader stages for LDS space.
1681 * TODO: We should really take the shader's internal LDS use into
1682 * account. The linker will fail if the size is greater than
1685 const unsigned max_lds_size
= 8 * 1024 - 768;
1686 const unsigned target_lds_size
= max_lds_size
;
1687 unsigned esvert_lds_size
= 0;
1688 unsigned gsprim_lds_size
= 0;
1690 /* All these are per subgroup: */
1691 bool max_vert_out_per_gs_instance
= false;
1692 unsigned max_esverts_base
= 256;
1693 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1695 /* Hardware has the following non-natural restrictions on the value
1696 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1698 * - at most 252 for any line input primitive type
1699 * - at most 251 for any quad input primitive type
1700 * - at most 251 for triangle strips with adjacency (this happens to
1701 * be the natural limit for triangle *lists* with adjacency)
1703 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1705 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1706 unsigned max_out_verts_per_gsprim
=
1707 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1709 if (max_out_verts_per_gsprim
<= 256) {
1710 if (max_out_verts_per_gsprim
) {
1711 max_gsprims_base
= MIN2(max_gsprims_base
,
1712 256 / max_out_verts_per_gsprim
);
1715 /* Use special multi-cycling mode in which each GS
1716 * instance gets its own subgroup. Does not work with
1718 max_vert_out_per_gs_instance
= true;
1719 max_gsprims_base
= 1;
1720 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1723 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1724 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1727 /* LDS size for passing data from GS to ES. */
1728 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1729 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1730 : &infos
[MESA_SHADER_VERTEX
].so
;
1732 if (so_info
->num_outputs
)
1733 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1735 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1736 * corresponding to the ES thread of the provoking vertex. All
1737 * ES threads load and export PrimitiveID for their thread.
1739 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1740 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1741 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1744 unsigned max_gsprims
= max_gsprims_base
;
1745 unsigned max_esverts
= max_esverts_base
;
1747 if (esvert_lds_size
)
1748 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1749 if (gsprim_lds_size
)
1750 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1752 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1753 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1754 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1756 if (esvert_lds_size
|| gsprim_lds_size
) {
1757 /* Now that we have a rough proportionality between esverts
1758 * and gsprims based on the primitive type, scale both of them
1759 * down simultaneously based on required LDS space.
1761 * We could be smarter about this if we knew how much vertex
1764 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1765 max_gsprims
* gsprim_lds_size
;
1766 if (lds_total
> target_lds_size
) {
1767 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1768 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1770 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1771 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1772 min_verts_per_prim
, uses_adjacency
);
1773 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1777 /* Round up towards full wave sizes for better ALU utilization. */
1778 if (!max_vert_out_per_gs_instance
) {
1779 const unsigned wavesize
= pipeline
->device
->physical_device
->ge_wave_size
;
1780 unsigned orig_max_esverts
;
1781 unsigned orig_max_gsprims
;
1783 orig_max_esverts
= max_esverts
;
1784 orig_max_gsprims
= max_gsprims
;
1786 max_esverts
= align(max_esverts
, wavesize
);
1787 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1788 if (esvert_lds_size
)
1789 max_esverts
= MIN2(max_esverts
,
1790 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1792 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1794 max_gsprims
= align(max_gsprims
, wavesize
);
1795 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1796 if (gsprim_lds_size
)
1797 max_gsprims
= MIN2(max_gsprims
,
1798 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1800 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1801 min_verts_per_prim
, uses_adjacency
);
1802 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1803 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1806 /* Hardware restriction: minimum value of max_esverts */
1807 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1809 unsigned max_out_vertices
=
1810 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1811 gs_type
== MESA_SHADER_GEOMETRY
?
1812 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1814 assert(max_out_vertices
<= 256);
1816 unsigned prim_amp_factor
= 1;
1817 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1818 /* Number of output primitives per GS input primitive after
1820 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1823 /* The GE only checks against the maximum number of ES verts after
1824 * allocating a full GS primitive. So we need to ensure that whenever
1825 * this check passes, there is enough space for a full primitive without
1828 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1829 ngg
->max_gsprims
= max_gsprims
;
1830 ngg
->max_out_verts
= max_out_vertices
;
1831 ngg
->prim_amp_factor
= prim_amp_factor
;
1832 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1833 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1834 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1836 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1837 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1839 ngg
->vgt_esgs_ring_itemsize
= 1;
1842 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1844 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1848 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1849 const struct gfx9_gs_info
*gs
)
1851 struct radv_device
*device
= pipeline
->device
;
1852 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1853 unsigned wave_size
= 64;
1854 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1855 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1856 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1858 unsigned gs_vertex_reuse
=
1859 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1860 unsigned alignment
= 256 * num_se
;
1861 /* The maximum size is 63.999 MB per SE. */
1862 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1863 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1865 /* Calculate the minimum size. */
1866 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1867 wave_size
, alignment
);
1868 /* These are recommended sizes, not minimum sizes. */
1869 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1870 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1871 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1872 gs_info
->gs
.max_gsvs_emit_size
;
1874 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1875 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1876 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1878 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1879 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1881 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1884 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1887 /* If tessellation is all offchip and on-chip GS isn't used, this
1888 * workaround is not needed.
1892 /* SPI barrier management bug:
1893 * Make sure we have at least 4k of LDS in use to avoid the bug.
1894 * It applies to workgroup sizes of more than one wavefront.
1896 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1897 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1898 *lds_size
= MAX2(*lds_size
, 8);
1901 struct radv_shader_variant
*
1902 radv_get_shader(struct radv_pipeline
*pipeline
,
1903 gl_shader_stage stage
)
1905 if (stage
== MESA_SHADER_VERTEX
) {
1906 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1907 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1908 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1909 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1910 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1911 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1912 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1913 if (!radv_pipeline_has_tess(pipeline
))
1915 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1916 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1917 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1918 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1920 return pipeline
->shaders
[stage
];
1923 static struct radv_tessellation_state
1924 calculate_tess_state(struct radv_pipeline
*pipeline
,
1925 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1927 unsigned num_tcs_input_cp
;
1928 unsigned num_tcs_output_cp
;
1930 unsigned num_patches
;
1931 struct radv_tessellation_state tess
= {0};
1933 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1934 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1935 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1937 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1939 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1940 assert(lds_size
<= 65536);
1941 lds_size
= align(lds_size
, 512) / 512;
1943 assert(lds_size
<= 32768);
1944 lds_size
= align(lds_size
, 256) / 256;
1946 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1948 tess
.lds_size
= lds_size
;
1950 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1951 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1952 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1953 tess
.num_patches
= num_patches
;
1955 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1956 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1958 switch (tes
->info
.tes
.primitive_mode
) {
1960 type
= V_028B6C_TESS_TRIANGLE
;
1963 type
= V_028B6C_TESS_QUAD
;
1966 type
= V_028B6C_TESS_ISOLINE
;
1970 switch (tes
->info
.tes
.spacing
) {
1971 case TESS_SPACING_EQUAL
:
1972 partitioning
= V_028B6C_PART_INTEGER
;
1974 case TESS_SPACING_FRACTIONAL_ODD
:
1975 partitioning
= V_028B6C_PART_FRAC_ODD
;
1977 case TESS_SPACING_FRACTIONAL_EVEN
:
1978 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1984 bool ccw
= tes
->info
.tes
.ccw
;
1985 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
1986 vk_find_struct_const(pCreateInfo
->pTessellationState
,
1987 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
1989 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
1992 if (tes
->info
.tes
.point_mode
)
1993 topology
= V_028B6C_OUTPUT_POINT
;
1994 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
1995 topology
= V_028B6C_OUTPUT_LINE
;
1997 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
1999 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2001 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2002 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2003 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2004 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2006 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2008 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2010 tess
.tf_param
= S_028B6C_TYPE(type
) |
2011 S_028B6C_PARTITIONING(partitioning
) |
2012 S_028B6C_TOPOLOGY(topology
) |
2013 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2018 static const struct radv_prim_vertex_count prim_size_table
[] = {
2019 [V_008958_DI_PT_NONE
] = {0, 0},
2020 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2021 [V_008958_DI_PT_LINELIST
] = {2, 2},
2022 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2023 [V_008958_DI_PT_TRILIST
] = {3, 3},
2024 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2025 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2026 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2027 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2028 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2029 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2030 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2031 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2032 [V_008958_DI_PT_POLYGON
] = {3, 1},
2033 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2036 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2038 if (radv_pipeline_has_gs(pipeline
))
2039 if (radv_pipeline_has_ngg(pipeline
))
2040 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2042 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2043 else if (radv_pipeline_has_tess(pipeline
))
2044 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2046 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2050 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2052 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2053 int shader_count
= 0;
2055 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2056 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2058 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2059 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2061 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2062 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2064 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2065 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2067 if(shaders
[MESA_SHADER_VERTEX
]) {
2068 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2071 if (shader_count
> 1) {
2072 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2073 unsigned last
= ordered_shaders
[0]->info
.stage
;
2075 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2076 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2077 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2079 for (int i
= 0; i
< shader_count
; ++i
) {
2080 nir_variable_mode mask
= 0;
2082 if (ordered_shaders
[i
]->info
.stage
!= first
)
2083 mask
= mask
| nir_var_shader_in
;
2085 if (ordered_shaders
[i
]->info
.stage
!= last
)
2086 mask
= mask
| nir_var_shader_out
;
2088 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2089 radv_optimize_nir(ordered_shaders
[i
], false, false);
2093 for (int i
= 1; i
< shader_count
; ++i
) {
2094 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2095 ordered_shaders
[i
- 1]);
2097 if (nir_link_opt_varyings(ordered_shaders
[i
],
2098 ordered_shaders
[i
- 1]))
2099 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2101 nir_remove_dead_variables(ordered_shaders
[i
],
2102 nir_var_shader_out
);
2103 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2106 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2107 ordered_shaders
[i
- 1]);
2109 nir_compact_varyings(ordered_shaders
[i
],
2110 ordered_shaders
[i
- 1], true);
2113 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2114 ac_lower_indirect_derefs(ordered_shaders
[i
],
2115 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2117 radv_optimize_nir(ordered_shaders
[i
], false, false);
2119 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2120 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2121 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2123 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2129 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2130 uint32_t attrib_binding
)
2132 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2133 const VkVertexInputBindingDescription
*input_binding
=
2134 &input_state
->pVertexBindingDescriptions
[i
];
2136 if (input_binding
->binding
== attrib_binding
)
2137 return input_binding
->stride
;
2143 static struct radv_pipeline_key
2144 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2145 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2146 const struct radv_blend_state
*blend
,
2147 bool has_view_index
)
2149 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2150 pCreateInfo
->pVertexInputState
;
2151 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2152 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2154 struct radv_pipeline_key key
;
2155 memset(&key
, 0, sizeof(key
));
2157 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2158 key
.optimisations_disabled
= 1;
2160 key
.has_multiview_view_index
= has_view_index
;
2162 uint32_t binding_input_rate
= 0;
2163 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2164 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2165 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2166 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2167 binding_input_rate
|= 1u << binding
;
2168 instance_rate_divisors
[binding
] = 1;
2171 if (divisor_state
) {
2172 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2173 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2174 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2178 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2179 const VkVertexInputAttributeDescription
*desc
=
2180 &input_state
->pVertexAttributeDescriptions
[i
];
2181 const struct vk_format_description
*format_desc
;
2182 unsigned location
= desc
->location
;
2183 unsigned binding
= desc
->binding
;
2184 unsigned num_format
, data_format
;
2187 if (binding_input_rate
& (1u << binding
)) {
2188 key
.instance_rate_inputs
|= 1u << location
;
2189 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2192 format_desc
= vk_format_description(desc
->format
);
2193 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2195 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2196 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2198 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2199 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2200 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2201 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2203 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2204 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2205 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2208 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2209 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2210 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2212 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2213 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2214 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2216 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2217 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2218 adjust
= RADV_ALPHA_ADJUST_SINT
;
2224 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2227 switch (desc
->format
) {
2228 case VK_FORMAT_B8G8R8A8_UNORM
:
2229 case VK_FORMAT_B8G8R8A8_SNORM
:
2230 case VK_FORMAT_B8G8R8A8_USCALED
:
2231 case VK_FORMAT_B8G8R8A8_SSCALED
:
2232 case VK_FORMAT_B8G8R8A8_UINT
:
2233 case VK_FORMAT_B8G8R8A8_SINT
:
2234 case VK_FORMAT_B8G8R8A8_SRGB
:
2235 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2236 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2237 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2238 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2239 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2240 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2241 key
.vertex_post_shuffle
|= 1 << location
;
2248 if (pCreateInfo
->pTessellationState
)
2249 key
.tess_input_vertices
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2252 if (pCreateInfo
->pMultisampleState
&&
2253 pCreateInfo
->pMultisampleState
->rasterizationSamples
> 1) {
2254 uint32_t num_samples
= pCreateInfo
->pMultisampleState
->rasterizationSamples
;
2255 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
->pMultisampleState
);
2256 key
.num_samples
= num_samples
;
2257 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2260 key
.col_format
= blend
->spi_shader_col_format
;
2261 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2262 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2268 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2270 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2271 bool uses_xfb
= !!xfb
;
2278 radv_fill_shader_keys(struct radv_device
*device
,
2279 struct radv_shader_variant_key
*keys
,
2280 const struct radv_pipeline_key
*key
,
2283 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2284 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2285 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2286 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2287 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2288 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2289 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2290 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2291 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2294 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2295 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2296 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2297 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2298 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2300 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2303 if (nir
[MESA_SHADER_GEOMETRY
]) {
2304 if (nir
[MESA_SHADER_TESS_CTRL
])
2305 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2307 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2310 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
2311 device
->physical_device
->rad_info
.family
!= CHIP_NAVI14
&&
2312 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)) {
2313 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2314 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2316 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2319 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2320 nir
[MESA_SHADER_GEOMETRY
] &&
2321 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2322 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2323 /* Fallback to the legacy path if tessellation is
2324 * enabled with extreme geometry because
2325 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2328 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2332 * Disable NGG with geometry shaders. There are a bunch of
2334 * * GS primitives in pipeline statistic queries do not get
2335 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2336 * * General issues with the last primitive missing/corrupt:
2337 * https://bugs.freedesktop.org/show_bug.cgi?id=111248
2339 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2341 if (nir
[MESA_SHADER_GEOMETRY
]) {
2342 if (nir
[MESA_SHADER_TESS_CTRL
])
2343 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2345 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2348 if (!device
->physical_device
->use_ngg_streamout
) {
2349 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2351 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2356 if (nir
[last_xfb_stage
] &&
2357 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
])) {
2358 if (nir
[MESA_SHADER_TESS_CTRL
])
2359 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2361 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2366 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2367 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2369 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2370 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2371 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2372 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2373 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2377 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2378 struct radv_shader_variant_key
*keys
,
2379 struct radv_shader_info
*infos
,
2382 unsigned active_stages
= 0;
2383 unsigned filled_stages
= 0;
2385 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2387 active_stages
|= (1 << i
);
2390 if (nir
[MESA_SHADER_FRAGMENT
]) {
2391 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2392 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2394 &keys
[MESA_SHADER_FRAGMENT
],
2395 &infos
[MESA_SHADER_FRAGMENT
]);
2397 /* TODO: These are no longer used as keys we should refactor this */
2398 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2399 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2400 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2401 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2402 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2403 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2404 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2405 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2406 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2407 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2408 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2409 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2411 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2414 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2415 nir
[MESA_SHADER_TESS_CTRL
]) {
2416 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2417 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2418 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2420 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2422 for (int i
= 0; i
< 2; i
++) {
2423 radv_nir_shader_info_pass(combined_nir
[i
],
2424 pipeline
->layout
, &key
,
2425 &infos
[MESA_SHADER_TESS_CTRL
]);
2428 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2429 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2430 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2431 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2433 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2434 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2437 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2438 nir
[MESA_SHADER_GEOMETRY
]) {
2439 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2440 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2442 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2444 for (int i
= 0; i
< 2; i
++) {
2445 radv_nir_shader_info_pass(combined_nir
[i
],
2448 &infos
[MESA_SHADER_GEOMETRY
]);
2451 filled_stages
|= (1 << pre_stage
);
2452 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2455 active_stages
^= filled_stages
;
2456 while (active_stages
) {
2457 int i
= u_bit_scan(&active_stages
);
2459 if (i
== MESA_SHADER_TESS_CTRL
) {
2460 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2461 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2464 if (i
== MESA_SHADER_TESS_EVAL
) {
2465 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2466 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2467 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2468 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2471 radv_nir_shader_info_init(&infos
[i
]);
2472 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2473 &keys
[i
], &infos
[i
]);
2478 merge_tess_info(struct shader_info
*tes_info
,
2479 const struct shader_info
*tcs_info
)
2481 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2483 * "PointMode. Controls generation of points rather than triangles
2484 * or lines. This functionality defaults to disabled, and is
2485 * enabled if either shader stage includes the execution mode.
2487 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2488 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2489 * and OutputVertices, it says:
2491 * "One mode must be set in at least one of the tessellation
2494 * So, the fields can be set in either the TCS or TES, but they must
2495 * agree if set in both. Our backend looks at TES, so bitwise-or in
2496 * the values from the TCS.
2498 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2499 tes_info
->tess
.tcs_vertices_out
== 0 ||
2500 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2501 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2503 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2504 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2505 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2506 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2508 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2509 tes_info
->tess
.primitive_mode
== 0 ||
2510 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2511 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2512 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2513 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2517 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2522 if (ext
->pPipelineCreationFeedback
) {
2523 ext
->pPipelineCreationFeedback
->flags
= 0;
2524 ext
->pPipelineCreationFeedback
->duration
= 0;
2527 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2528 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2529 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2534 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2539 feedback
->duration
-= radv_get_current_time();
2540 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2544 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2549 feedback
->duration
+= radv_get_current_time();
2550 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2551 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2555 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2556 struct radv_device
*device
,
2557 struct radv_pipeline_cache
*cache
,
2558 const struct radv_pipeline_key
*key
,
2559 const VkPipelineShaderStageCreateInfo
**pStages
,
2560 const VkPipelineCreateFlags flags
,
2561 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2562 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2563 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2565 struct radv_shader_module fs_m
= {0};
2566 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2567 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2568 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2569 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2570 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2571 unsigned char hash
[20], gs_copy_hash
[20];
2572 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2574 radv_start_feedback(pipeline_feedback
);
2576 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2578 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2579 if (modules
[i
]->nir
)
2580 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2581 strlen(modules
[i
]->nir
->info
.name
),
2584 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2588 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2589 memcpy(gs_copy_hash
, hash
, 20);
2590 gs_copy_hash
[0] ^= 1;
2592 bool found_in_application_cache
= true;
2593 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
) {
2594 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2595 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2596 &found_in_application_cache
);
2597 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2600 if (!keep_executable_info
&&
2601 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2602 &found_in_application_cache
) &&
2603 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2604 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2608 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2610 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2611 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2612 fs_m
.nir
= fs_b
.shader
;
2613 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2616 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2617 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2622 radv_start_feedback(stage_feedbacks
[i
]);
2624 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2625 stage
? stage
->pName
: "main", i
,
2626 stage
? stage
->pSpecializationInfo
: NULL
,
2627 flags
, pipeline
->layout
);
2629 /* We don't want to alter meta shaders IR directly so clone it
2632 if (nir
[i
]->info
.name
) {
2633 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2636 radv_stop_feedback(stage_feedbacks
[i
], false);
2639 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2640 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2641 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2644 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2645 radv_link_shaders(pipeline
, nir
);
2647 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2649 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2650 nir_lower_non_uniform_ubo_access
|
2651 nir_lower_non_uniform_ssbo_access
|
2652 nir_lower_non_uniform_texture_access
|
2653 nir_lower_non_uniform_image_access
);
2654 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2657 if (radv_can_dump_shader(device
, modules
[i
], false))
2658 nir_print_shader(nir
[i
], stderr
);
2661 if (nir
[MESA_SHADER_FRAGMENT
])
2662 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2664 radv_fill_shader_keys(device
, keys
, key
, nir
);
2666 radv_fill_shader_info(pipeline
, keys
, infos
, nir
);
2668 if ((nir
[MESA_SHADER_VERTEX
] &&
2669 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2670 (nir
[MESA_SHADER_TESS_EVAL
] &&
2671 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2672 struct gfx10_ngg_info
*ngg_info
;
2674 if (nir
[MESA_SHADER_GEOMETRY
])
2675 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2676 else if (nir
[MESA_SHADER_TESS_CTRL
])
2677 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2679 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2681 gfx10_get_ngg_info(pCreateInfo
, pipeline
, nir
, infos
, ngg_info
);
2682 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2683 struct gfx9_gs_info
*gs_info
=
2684 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2686 gfx9_get_gs_info(pCreateInfo
, pipeline
, nir
, infos
, gs_info
);
2689 if (nir
[MESA_SHADER_FRAGMENT
]) {
2690 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2691 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2693 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2694 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2695 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2696 infos
+ MESA_SHADER_FRAGMENT
,
2697 keep_executable_info
, &binaries
[MESA_SHADER_FRAGMENT
]);
2699 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2702 /* TODO: These are no longer used as keys we should refactor this */
2703 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2704 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
;
2705 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2706 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.layer_input
;
2707 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2708 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.num_input_clips_culls
;
2709 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2710 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
;
2711 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2712 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.layer_input
;
2713 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2714 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.num_input_clips_culls
;
2717 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2718 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2719 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2720 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2721 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2723 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2725 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2727 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2728 &binaries
[MESA_SHADER_TESS_CTRL
]);
2730 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2732 modules
[MESA_SHADER_VERTEX
] = NULL
;
2733 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2734 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2737 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2738 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2739 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2740 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2742 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2744 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2746 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2747 &binaries
[MESA_SHADER_GEOMETRY
]);
2749 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2751 modules
[pre_stage
] = NULL
;
2754 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2755 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2756 if (i
== MESA_SHADER_TESS_CTRL
) {
2757 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2759 if (i
== MESA_SHADER_TESS_EVAL
) {
2760 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2761 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2764 radv_start_feedback(stage_feedbacks
[i
]);
2766 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2768 keys
+ i
, infos
+ i
,keep_executable_info
,
2771 radv_stop_feedback(stage_feedbacks
[i
], false);
2775 if(modules
[MESA_SHADER_GEOMETRY
]) {
2776 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2777 if (!pipeline
->gs_copy_shader
&&
2778 !radv_pipeline_has_ngg(pipeline
)) {
2779 struct radv_shader_info info
= {};
2780 struct radv_shader_variant_key key
= {};
2782 key
.has_multiview_view_index
=
2783 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2785 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2786 pipeline
->layout
, &key
,
2789 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2790 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2791 &gs_copy_binary
, keep_executable_info
,
2792 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2795 if (!keep_executable_info
&& pipeline
->gs_copy_shader
) {
2796 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2797 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2799 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2800 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2802 radv_pipeline_cache_insert_shaders(device
, cache
,
2807 free(gs_copy_binary
);
2810 if (!keep_executable_info
) {
2811 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2815 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2818 ralloc_free(nir
[i
]);
2820 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2821 radv_shader_dump_stats(device
,
2822 pipeline
->shaders
[i
],
2828 ralloc_free(fs_m
.nir
);
2830 radv_stop_feedback(pipeline_feedback
, false);
2834 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2835 gl_shader_stage stage
, enum chip_class chip_class
)
2837 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2838 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2839 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
2842 case MESA_SHADER_FRAGMENT
:
2843 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2844 case MESA_SHADER_VERTEX
:
2846 if (chip_class
>= GFX10
) {
2847 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2848 } else if (chip_class
== GFX9
) {
2849 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
2851 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
2857 if (chip_class
>= GFX10
) {
2858 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2860 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2865 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2867 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2868 case MESA_SHADER_GEOMETRY
:
2869 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2870 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2871 case MESA_SHADER_COMPUTE
:
2872 return R_00B900_COMPUTE_USER_DATA_0
;
2873 case MESA_SHADER_TESS_CTRL
:
2874 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2875 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2876 case MESA_SHADER_TESS_EVAL
:
2878 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
2879 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2880 } else if (has_ngg
) {
2881 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2883 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2886 unreachable("unknown shader");
2890 struct radv_bin_size_entry
{
2896 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2898 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
2902 /* One shader engine */
2908 { UINT_MAX
, { 0, 0}},
2911 /* Two shader engines */
2917 { UINT_MAX
, { 0, 0}},
2920 /* Four shader engines */
2925 { UINT_MAX
, { 0, 0}},
2931 /* One shader engine */
2937 { UINT_MAX
, { 0, 0}},
2940 /* Two shader engines */
2946 { UINT_MAX
, { 0, 0}},
2949 /* Four shader engines */
2956 { UINT_MAX
, { 0, 0}},
2962 /* One shader engine */
2969 { UINT_MAX
, { 0, 0}},
2972 /* Two shader engines */
2980 { UINT_MAX
, { 0, 0}},
2983 /* Four shader engines */
2991 { UINT_MAX
, { 0, 0}},
2995 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
2999 // One shader engine
3006 { UINT_MAX
, { 0, 0}},
3009 // Two shader engines
3017 { UINT_MAX
, { 0, 0}},
3020 // Four shader engines
3028 { UINT_MAX
, { 0, 0}},
3034 // One shader engine
3042 { UINT_MAX
, { 0, 0}},
3045 // Two shader engines
3054 { UINT_MAX
, { 0, 0}},
3057 // Four shader engines
3066 { UINT_MAX
, { 0, 0}},
3072 // One shader engine
3080 { UINT_MAX
, { 0, 0}},
3083 // Two shader engines
3092 { UINT_MAX
, { 0, 0}},
3095 // Four shader engines
3103 { UINT_MAX
, { 0, 0}},
3108 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3109 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3110 VkExtent2D extent
= {512, 512};
3112 unsigned log_num_rb_per_se
=
3113 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3114 pipeline
->device
->physical_device
->rad_info
.max_se
);
3115 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3117 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3118 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3119 unsigned effective_samples
= total_samples
;
3120 unsigned color_bytes_per_pixel
= 0;
3122 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3124 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3125 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3128 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3131 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3132 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3135 /* MSAA images typically don't use all samples all the time. */
3136 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3137 effective_samples
= 2;
3138 color_bytes_per_pixel
*= effective_samples
;
3141 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3142 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3145 extent
= color_entry
->extent
;
3147 if (subpass
->depth_stencil_attachment
) {
3148 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3150 /* Coefficients taken from AMDVLK */
3151 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3152 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3153 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3155 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3156 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3159 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3160 extent
= ds_entry
->extent
;
3167 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3169 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3170 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3171 VkExtent2D extent
= {512, 512};
3173 unsigned sdp_interface_count
;
3175 switch(pipeline
->device
->physical_device
->rad_info
.family
) {
3178 sdp_interface_count
= 16;
3181 sdp_interface_count
= 8;
3184 unreachable("Unhandled GFX10 chip");
3187 const unsigned db_tag_size
= 64;
3188 const unsigned db_tag_count
= 312;
3189 const unsigned color_tag_size
= 1024;
3190 const unsigned color_tag_count
= 31;
3191 const unsigned fmask_tag_size
= 256;
3192 const unsigned fmask_tag_count
= 44;
3194 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3195 const unsigned pipe_count
= MAX2(rb_count
, sdp_interface_count
);
3197 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3198 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3199 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3201 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3202 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3204 unsigned color_bytes_per_pixel
= 0;
3205 unsigned fmask_bytes_per_pixel
= 0;
3207 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3209 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3210 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3213 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3216 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3217 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3219 if (total_samples
> 1) {
3220 const unsigned fmask_array
[] = {0, 1, 1, 4};
3221 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3225 color_bytes_per_pixel
*= total_samples
;
3227 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3229 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3230 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3231 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3233 if (fmask_bytes_per_pixel
) {
3234 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3236 const VkExtent2D fmask_extent
= (VkExtent2D
){
3237 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3238 .height
= 1ull << (color_pixel_count_log
/ 2)
3241 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3242 extent
= fmask_extent
;
3245 if (subpass
->depth_stencil_attachment
) {
3246 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3248 /* Coefficients taken from AMDVLK */
3249 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3250 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3251 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3253 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3255 const VkExtent2D db_extent
= (VkExtent2D
){
3256 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3257 .height
= 1ull << (color_pixel_count_log
/ 2)
3260 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3264 extent
.width
= MAX2(extent
.width
, 128);
3265 extent
.height
= MAX2(extent
.width
, 64);
3271 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3272 struct radv_pipeline
*pipeline
,
3273 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3275 uint32_t pa_sc_binner_cntl_0
=
3276 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3277 S_028C44_DISABLE_START_OF_PRIM(1);
3278 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3280 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3281 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3282 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3283 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3284 unsigned min_bytes_per_pixel
= 0;
3287 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3288 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3291 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3294 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3295 unsigned bytes
= vk_format_get_blocksize(format
);
3296 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3297 min_bytes_per_pixel
= bytes
;
3301 pa_sc_binner_cntl_0
=
3302 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3303 S_028C44_BIN_SIZE_X(0) |
3304 S_028C44_BIN_SIZE_Y(0) |
3305 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3306 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3307 S_028C44_DISABLE_START_OF_PRIM(1);
3310 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3311 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3315 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3316 struct radv_pipeline
*pipeline
,
3317 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3319 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3322 VkExtent2D bin_size
;
3323 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3324 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3325 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3326 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3328 unreachable("Unhandled generation for binning bin size calculation");
3330 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3331 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
3332 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
3333 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
3335 if (pipeline
->device
->physical_device
->rad_info
.has_dedicated_vram
) {
3336 context_states_per_bin
= 1;
3337 persistent_states_per_bin
= 1;
3338 fpovs_per_batch
= 63;
3340 /* The context states are affected by the scissor bug. */
3341 context_states_per_bin
= pipeline
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
? 1 : 6;
3342 /* 32 causes hangs for RAVEN. */
3343 persistent_states_per_bin
= 16;
3344 fpovs_per_batch
= 63;
3347 const uint32_t pa_sc_binner_cntl_0
=
3348 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3349 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3350 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3351 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3352 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3353 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
- 1) |
3354 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
- 1) |
3355 S_028C44_DISABLE_START_OF_PRIM(1) |
3356 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
3357 S_028C44_OPTIMAL_BIN_SELECTION(1);
3359 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3361 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3362 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3364 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3369 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3370 struct radv_pipeline
*pipeline
,
3371 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3372 const struct radv_graphics_pipeline_create_info
*extra
)
3374 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
3375 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3376 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3377 struct radv_render_pass_attachment
*attachment
= NULL
;
3378 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3379 uint32_t db_render_control
= 0, db_render_override2
= 0;
3380 uint32_t db_render_override
= 0;
3382 if (subpass
->depth_stencil_attachment
)
3383 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3385 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3386 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3388 if (vkds
&& has_depth_attachment
) {
3389 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3390 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3391 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3392 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3394 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3395 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3398 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3399 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3400 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3401 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3402 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3403 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3405 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3406 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3407 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3408 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3411 if (attachment
&& extra
) {
3412 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3413 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3415 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
3416 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
3417 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
3418 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3419 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3422 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3423 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3425 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
) {
3426 /* From VK_EXT_depth_range_unrestricted spec:
3428 * "The behavior described in Primitive Clipping still applies.
3429 * If depth clamping is disabled the depth values are still
3430 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3431 * depth clamping is enabled the above equation is ignored and
3432 * the depth values are instead clamped to the VkViewport
3433 * minDepth and maxDepth values, which in the case of this
3434 * extension can be outside of the 0.0 to 1.0 range."
3436 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3439 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3440 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3442 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3443 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3444 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3448 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3449 struct radv_pipeline
*pipeline
,
3450 const struct radv_blend_state
*blend
)
3452 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3453 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3455 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3456 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3458 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3460 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3461 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3464 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3466 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3467 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3469 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3470 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3473 static const VkConservativeRasterizationModeEXT
3474 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3476 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3477 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3479 if (!conservative_raster
)
3480 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3481 return conservative_raster
->conservativeRasterizationMode
;
3485 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3486 struct radv_pipeline
*pipeline
,
3487 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3489 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3490 const VkConservativeRasterizationModeEXT mode
=
3491 radv_get_conservative_raster_mode(vkraster
);
3492 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3493 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3495 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3496 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3497 if (depth_clip_state
) {
3498 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3501 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3502 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3503 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3504 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3505 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3506 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3508 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3509 S_0286D4_FLAT_SHADE_ENA(1) |
3510 S_0286D4_PNT_SPRITE_ENA(1) |
3511 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3512 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3513 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3514 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3515 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3517 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3518 S_028BE4_PIX_CENTER(1) | // TODO verify
3519 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3520 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3522 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3523 S_028814_FACE(vkraster
->frontFace
) |
3524 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3525 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3526 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3527 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3528 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3529 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3530 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3531 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3533 /* Conservative rasterization. */
3534 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3535 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3537 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3538 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3539 S_028804_OVERRASTERIZATION_AMOUNT(4);
3541 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3542 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3543 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3545 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3546 pa_sc_conservative_rast
|=
3547 S_028C4C_OVER_RAST_ENABLE(1) |
3548 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3549 S_028C4C_UNDER_RAST_ENABLE(0) |
3550 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3551 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3553 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3554 pa_sc_conservative_rast
|=
3555 S_028C4C_OVER_RAST_ENABLE(0) |
3556 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3557 S_028C4C_UNDER_RAST_ENABLE(1) |
3558 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3559 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3563 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3564 pa_sc_conservative_rast
);
3569 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3570 struct radv_pipeline
*pipeline
)
3572 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3574 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3575 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3576 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3578 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3579 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3581 /* The exclusion bits can be set to improve rasterization efficiency
3582 * if no sample lies on the pixel boundary (-8 sample offset). It's
3583 * currently always TRUE because the driver doesn't support 16 samples.
3585 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3586 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3587 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3588 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3592 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3593 struct radv_pipeline
*pipeline
)
3595 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3596 const struct radv_shader_variant
*vs
=
3597 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3598 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3599 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3600 unsigned vgt_primitiveid_en
= 0;
3601 uint32_t vgt_gs_mode
= 0;
3603 if (radv_pipeline_has_ngg(pipeline
))
3606 if (radv_pipeline_has_gs(pipeline
)) {
3607 const struct radv_shader_variant
*gs
=
3608 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3610 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3611 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3612 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3613 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3614 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3617 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3618 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3622 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3623 struct radeon_cmdbuf
*cs
,
3624 struct radv_pipeline
*pipeline
,
3625 struct radv_shader_variant
*shader
)
3627 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3629 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3630 radeon_emit(cs
, va
>> 8);
3631 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3632 radeon_emit(cs
, shader
->config
.rsrc1
);
3633 radeon_emit(cs
, shader
->config
.rsrc2
);
3635 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3636 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3637 clip_dist_mask
= outinfo
->clip_dist_mask
;
3638 cull_dist_mask
= outinfo
->cull_dist_mask
;
3639 total_mask
= clip_dist_mask
| cull_dist_mask
;
3640 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3641 outinfo
->writes_layer
||
3642 outinfo
->writes_viewport_index
;
3643 unsigned spi_vs_out_config
, nparams
;
3645 /* VS is required to export at least one param. */
3646 nparams
= MAX2(outinfo
->param_exports
, 1);
3647 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3649 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3650 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3653 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3655 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3656 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3657 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3658 V_02870C_SPI_SHADER_4COMP
:
3659 V_02870C_SPI_SHADER_NONE
) |
3660 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3661 V_02870C_SPI_SHADER_4COMP
:
3662 V_02870C_SPI_SHADER_NONE
) |
3663 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3664 V_02870C_SPI_SHADER_4COMP
:
3665 V_02870C_SPI_SHADER_NONE
));
3667 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3668 S_028818_VTX_W0_FMT(1) |
3669 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3670 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3671 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3673 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3674 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3675 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3676 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3677 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3678 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3679 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3680 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3681 cull_dist_mask
<< 8 |
3684 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3685 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3686 outinfo
->writes_viewport_index
);
3690 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3691 struct radv_pipeline
*pipeline
,
3692 struct radv_shader_variant
*shader
)
3694 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3696 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3697 radeon_emit(cs
, va
>> 8);
3698 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3699 radeon_emit(cs
, shader
->config
.rsrc1
);
3700 radeon_emit(cs
, shader
->config
.rsrc2
);
3704 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3705 struct radv_pipeline
*pipeline
,
3706 struct radv_shader_variant
*shader
,
3707 const struct radv_tessellation_state
*tess
)
3709 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3710 uint32_t rsrc2
= shader
->config
.rsrc2
;
3712 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3713 radeon_emit(cs
, va
>> 8);
3714 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3716 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3717 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3718 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3719 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3721 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3722 radeon_emit(cs
, shader
->config
.rsrc1
);
3723 radeon_emit(cs
, rsrc2
);
3727 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3728 struct radeon_cmdbuf
*cs
,
3729 struct radv_pipeline
*pipeline
,
3730 struct radv_shader_variant
*shader
)
3732 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3733 gl_shader_stage es_type
=
3734 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3735 struct radv_shader_variant
*es
=
3736 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3737 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3739 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3740 radeon_emit(cs
, va
>> 8);
3741 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3742 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3743 radeon_emit(cs
, shader
->config
.rsrc1
);
3744 radeon_emit(cs
, shader
->config
.rsrc2
);
3746 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3747 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3748 clip_dist_mask
= outinfo
->clip_dist_mask
;
3749 cull_dist_mask
= outinfo
->cull_dist_mask
;
3750 total_mask
= clip_dist_mask
| cull_dist_mask
;
3751 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3752 outinfo
->writes_layer
||
3753 outinfo
->writes_viewport_index
;
3754 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3755 (es
&& es
->info
.uses_prim_id
);
3756 bool break_wave_at_eoi
= false;
3760 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3761 struct radv_shader_variant
*gs
=
3762 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3764 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3765 break_wave_at_eoi
= true;
3768 nparams
= MAX2(outinfo
->param_exports
, 1);
3769 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3770 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3771 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3773 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3774 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3775 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3776 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3777 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3778 V_02870C_SPI_SHADER_4COMP
:
3779 V_02870C_SPI_SHADER_NONE
) |
3780 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3781 V_02870C_SPI_SHADER_4COMP
:
3782 V_02870C_SPI_SHADER_NONE
) |
3783 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3784 V_02870C_SPI_SHADER_4COMP
:
3785 V_02870C_SPI_SHADER_NONE
));
3787 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3788 S_028818_VTX_W0_FMT(1) |
3789 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3790 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3791 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3792 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3793 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3794 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3795 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3796 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3797 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3798 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3799 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3800 cull_dist_mask
<< 8 |
3803 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3804 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3805 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
));
3807 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3808 ngg_state
->vgt_esgs_ring_itemsize
);
3810 /* NGG specific registers. */
3811 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3812 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
3814 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3815 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
3816 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
3817 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
3818 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
3819 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
3820 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
3821 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
3822 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3823 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
3824 S_028B90_CNT(gs_num_invocations
) |
3825 S_028B90_ENABLE(gs_num_invocations
> 1) |
3826 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
3828 /* User edge flags are set by the pos exports. If user edge flags are
3829 * not used, we must use hw-generated edge flags and pass them via
3830 * the prim export to prevent drawing lines on internal edges of
3831 * decomposed primitives (such as quads) with polygon mode = lines.
3833 * TODO: We should combine hw-generated edge flags with user edge
3834 * flags in the shader.
3836 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
3837 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
3838 !radv_pipeline_has_gs(pipeline
)));
3840 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
3841 S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
) |
3842 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
3844 /* Bug workaround for a possible hang with non-tessellation cases.
3845 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3847 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3849 if ((pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
3850 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
3851 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
3852 !radv_pipeline_has_tess(pipeline
) &&
3853 ngg_state
->hw_max_esverts
!= 256) {
3854 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
3856 if (ngg_state
->hw_max_esverts
> 5) {
3857 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
3861 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
3865 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
3866 struct radv_pipeline
*pipeline
,
3867 struct radv_shader_variant
*shader
,
3868 const struct radv_tessellation_state
*tess
)
3870 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3872 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3873 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
3875 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3876 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
3878 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
3881 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3882 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3883 radeon_emit(cs
, va
>> 8);
3884 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3886 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
3887 radeon_emit(cs
, va
>> 8);
3888 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
3891 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
3892 radeon_emit(cs
, shader
->config
.rsrc1
);
3893 radeon_emit(cs
, hs_rsrc2
);
3895 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
3896 radeon_emit(cs
, va
>> 8);
3897 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
3898 radeon_emit(cs
, shader
->config
.rsrc1
);
3899 radeon_emit(cs
, shader
->config
.rsrc2
);
3904 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
3905 struct radeon_cmdbuf
*cs
,
3906 struct radv_pipeline
*pipeline
,
3907 const struct radv_tessellation_state
*tess
)
3909 struct radv_shader_variant
*vs
;
3911 /* Skip shaders merged into HS/GS */
3912 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
3916 if (vs
->info
.vs
.as_ls
)
3917 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
3918 else if (vs
->info
.vs
.as_es
)
3919 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
3920 else if (vs
->info
.is_ngg
)
3921 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
3923 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
3927 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
3928 struct radeon_cmdbuf
*cs
,
3929 struct radv_pipeline
*pipeline
,
3930 const struct radv_tessellation_state
*tess
)
3932 if (!radv_pipeline_has_tess(pipeline
))
3935 struct radv_shader_variant
*tes
, *tcs
;
3937 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
3938 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
3941 if (tes
->info
.is_ngg
) {
3942 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
3943 } else if (tes
->info
.tes
.as_es
)
3944 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
3946 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
3949 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
3951 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
3954 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
3955 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
3956 tess
->ls_hs_config
);
3958 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
3959 tess
->ls_hs_config
);
3961 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
3962 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
3963 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3964 S_028A44_ES_VERTS_PER_SUBGRP(250) |
3965 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
3966 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
3971 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
3972 struct radeon_cmdbuf
*cs
,
3973 struct radv_pipeline
*pipeline
,
3974 struct radv_shader_variant
*gs
)
3976 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
3977 unsigned gs_max_out_vertices
;
3978 uint8_t *num_components
;
3983 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
3984 max_stream
= gs
->info
.gs
.max_stream
;
3985 num_components
= gs
->info
.gs
.num_stream_output_components
;
3987 offset
= num_components
[0] * gs_max_out_vertices
;
3989 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
3990 radeon_emit(ctx_cs
, offset
);
3991 if (max_stream
>= 1)
3992 offset
+= num_components
[1] * gs_max_out_vertices
;
3993 radeon_emit(ctx_cs
, offset
);
3994 if (max_stream
>= 2)
3995 offset
+= num_components
[2] * gs_max_out_vertices
;
3996 radeon_emit(ctx_cs
, offset
);
3997 if (max_stream
>= 3)
3998 offset
+= num_components
[3] * gs_max_out_vertices
;
3999 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4001 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4002 radeon_emit(ctx_cs
, num_components
[0]);
4003 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4004 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4005 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4007 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4008 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4009 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4010 S_028B90_ENABLE(gs_num_invocations
> 0));
4012 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4013 gs_state
->vgt_esgs_ring_itemsize
);
4015 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4017 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4018 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4019 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4020 radeon_emit(cs
, va
>> 8);
4021 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4023 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4024 radeon_emit(cs
, va
>> 8);
4025 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4028 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4029 radeon_emit(cs
, gs
->config
.rsrc1
);
4030 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4032 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4033 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4035 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4036 radeon_emit(cs
, va
>> 8);
4037 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4038 radeon_emit(cs
, gs
->config
.rsrc1
);
4039 radeon_emit(cs
, gs
->config
.rsrc2
);
4042 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4046 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4047 struct radeon_cmdbuf
*cs
,
4048 struct radv_pipeline
*pipeline
)
4050 struct radv_shader_variant
*gs
;
4052 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4056 if (gs
->info
.is_ngg
)
4057 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4059 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4061 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4062 gs
->info
.gs
.vertices_out
);
4065 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
, bool float16
)
4067 uint32_t ps_input_cntl
;
4068 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4069 ps_input_cntl
= S_028644_OFFSET(offset
);
4071 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4073 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4074 S_028644_ATTR0_VALID(1);
4077 /* The input is a DEFAULT_VAL constant. */
4078 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4079 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4080 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4081 ps_input_cntl
= S_028644_OFFSET(0x20) |
4082 S_028644_DEFAULT_VAL(offset
);
4084 return ps_input_cntl
;
4088 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4089 struct radv_pipeline
*pipeline
)
4091 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4092 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4093 uint32_t ps_input_cntl
[32];
4095 unsigned ps_offset
= 0;
4097 if (ps
->info
.ps
.prim_id_input
) {
4098 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4099 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4100 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4105 if (ps
->info
.ps
.layer_input
||
4106 ps
->info
.needs_multiview_view_index
) {
4107 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4108 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4109 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4111 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false);
4115 if (ps
->info
.ps
.has_pcoord
) {
4117 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4118 ps_input_cntl
[ps_offset
] = val
;
4122 if (ps
->info
.ps
.num_input_clips_culls
) {
4125 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4126 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4127 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4131 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4132 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4133 ps
->info
.ps
.num_input_clips_culls
> 4) {
4134 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4139 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4143 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4146 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4147 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4148 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4153 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4154 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4156 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, float16
);
4161 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4162 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4163 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4169 radv_compute_db_shader_control(const struct radv_device
*device
,
4170 const struct radv_pipeline
*pipeline
,
4171 const struct radv_shader_variant
*ps
)
4174 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4175 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4177 z_order
= V_02880C_LATE_Z
;
4179 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4180 !device
->physical_device
->rad_info
.rbplus_allowed
;
4182 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4183 * but this appears to break Project Cars (DXVK). See
4184 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4186 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4188 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4189 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4190 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4191 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4192 S_02880C_Z_ORDER(z_order
) |
4193 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4194 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4195 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4196 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4197 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4201 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4202 struct radeon_cmdbuf
*cs
,
4203 struct radv_pipeline
*pipeline
)
4205 struct radv_shader_variant
*ps
;
4207 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4209 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4210 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4212 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4213 radeon_emit(cs
, va
>> 8);
4214 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4215 radeon_emit(cs
, ps
->config
.rsrc1
);
4216 radeon_emit(cs
, ps
->config
.rsrc2
);
4218 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4219 radv_compute_db_shader_control(pipeline
->device
,
4222 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4223 ps
->config
.spi_ps_input_ena
);
4225 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4226 ps
->config
.spi_ps_input_addr
);
4228 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4229 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4230 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4232 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4234 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4235 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4236 ps
->info
.ps
.writes_stencil
,
4237 ps
->info
.ps
.writes_sample_mask
));
4239 if (pipeline
->device
->dfsm_allowed
) {
4240 /* optimise this? */
4241 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4242 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4247 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4248 struct radv_pipeline
*pipeline
)
4250 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4251 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4254 unsigned vtx_reuse_depth
= 30;
4255 if (radv_pipeline_has_tess(pipeline
) &&
4256 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4257 vtx_reuse_depth
= 14;
4259 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4260 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4264 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4266 uint32_t stages
= 0;
4267 if (radv_pipeline_has_tess(pipeline
)) {
4268 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4269 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4271 if (radv_pipeline_has_gs(pipeline
))
4272 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4274 else if (radv_pipeline_has_ngg(pipeline
))
4275 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4277 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4278 } else if (radv_pipeline_has_gs(pipeline
)) {
4279 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4281 } else if (radv_pipeline_has_ngg(pipeline
)) {
4282 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4285 if (radv_pipeline_has_ngg(pipeline
)) {
4286 stages
|= S_028B54_PRIMGEN_EN(1);
4287 } else if (radv_pipeline_has_gs(pipeline
)) {
4288 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4291 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4292 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4294 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4295 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4297 if (radv_pipeline_has_tess(pipeline
))
4298 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4300 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4301 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4302 if (pipeline
->gs_copy_shader
)
4303 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4304 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4305 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4306 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4307 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4309 if (radv_pipeline_has_ngg(pipeline
))
4312 /* legacy GS only supports Wave64 */
4313 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4314 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4315 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4322 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4324 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4325 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4327 if (!discard_rectangle_info
)
4332 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4333 /* Interpret i as a bitmask, and then set the bit in the mask if
4334 * that combination of rectangles in which the pixel is contained
4335 * should pass the cliprect test. */
4336 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4338 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4342 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4353 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4354 struct radv_pipeline
*pipeline
,
4355 const struct radv_tessellation_state
*tess
)
4357 bool break_wave_at_eoi
= false;
4358 unsigned primgroup_size
;
4359 unsigned vertgroup_size
;
4361 if (radv_pipeline_has_tess(pipeline
)) {
4362 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4364 } else if (radv_pipeline_has_gs(pipeline
)) {
4365 const struct gfx9_gs_info
*gs_state
=
4366 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4367 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4368 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4369 vertgroup_size
= G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4371 primgroup_size
= 128; /* recommended without a GS and tess */
4375 if (radv_pipeline_has_tess(pipeline
)) {
4376 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4377 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4378 break_wave_at_eoi
= true;
4381 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4382 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4383 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4384 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4385 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4389 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4390 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4391 const struct radv_graphics_pipeline_create_info
*extra
,
4392 const struct radv_blend_state
*blend
,
4393 const struct radv_tessellation_state
*tess
,
4394 unsigned prim
, unsigned gs_out
)
4396 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4397 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4400 ctx_cs
->max_dw
= 256;
4401 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4402 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4404 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4405 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4406 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4407 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4408 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4409 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4410 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4411 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4412 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4413 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4414 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4415 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
4417 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4418 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4420 radeon_set_context_reg(ctx_cs
, R_0286E8_SPI_TMPRING_SIZE
,
4421 S_0286E8_WAVES(pipeline
->max_waves
) |
4422 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
4424 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4426 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4427 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4428 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4430 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4432 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4434 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4436 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4438 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4439 assert(cs
->cdw
<= cs
->max_dw
);
4442 static struct radv_ia_multi_vgt_param_helpers
4443 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4444 const struct radv_tessellation_state
*tess
,
4447 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4448 const struct radv_device
*device
= pipeline
->device
;
4450 if (radv_pipeline_has_tess(pipeline
))
4451 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4452 else if (radv_pipeline_has_gs(pipeline
))
4453 ia_multi_vgt_param
.primgroup_size
= 64;
4455 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4457 /* GS requirement. */
4458 ia_multi_vgt_param
.partial_es_wave
= false;
4459 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4460 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4461 ia_multi_vgt_param
.partial_es_wave
= true;
4463 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4464 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4465 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4466 * 4 shader engines. Set 1 to pass the assertion below.
4467 * The other cases are hardware requirements. */
4468 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4469 prim
== V_008958_DI_PT_POLYGON
||
4470 prim
== V_008958_DI_PT_LINELOOP
||
4471 prim
== V_008958_DI_PT_TRIFAN
||
4472 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4473 (pipeline
->graphics
.prim_restart_enable
&&
4474 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4475 (prim
!= V_008958_DI_PT_POINTLIST
&&
4476 prim
!= V_008958_DI_PT_LINESTRIP
))))
4477 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4480 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4481 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4482 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4483 if (radv_pipeline_has_gs(pipeline
) &&
4484 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4485 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4486 if (radv_pipeline_has_tess(pipeline
)) {
4487 /* SWITCH_ON_EOI must be set if PrimID is used. */
4488 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4489 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4490 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4493 ia_multi_vgt_param
.partial_vs_wave
= false;
4494 if (radv_pipeline_has_tess(pipeline
)) {
4495 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4496 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4497 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4498 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4499 radv_pipeline_has_gs(pipeline
))
4500 ia_multi_vgt_param
.partial_vs_wave
= true;
4501 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4502 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4503 if (radv_pipeline_has_gs(pipeline
)) {
4504 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4505 ia_multi_vgt_param
.partial_es_wave
= true;
4507 ia_multi_vgt_param
.partial_vs_wave
= true;
4512 /* Workaround for a VGT hang when strip primitive types are used with
4513 * primitive restart.
4515 if (pipeline
->graphics
.prim_restart_enable
&&
4516 (prim
== V_008958_DI_PT_LINESTRIP
||
4517 prim
== V_008958_DI_PT_TRISTRIP
||
4518 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4519 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4520 ia_multi_vgt_param
.partial_vs_wave
= true;
4523 if (radv_pipeline_has_gs(pipeline
)) {
4524 /* On these chips there is the possibility of a hang if the
4525 * pipeline uses a GS and partial_vs_wave is not set.
4527 * This mostly does not hit 4-SE chips, as those typically set
4528 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4529 * with GS due to another workaround.
4531 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4533 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4534 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4535 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4536 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4537 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4538 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4539 ia_multi_vgt_param
.partial_vs_wave
= true;
4543 ia_multi_vgt_param
.base
=
4544 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4545 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4546 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4547 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4548 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4550 return ia_multi_vgt_param
;
4555 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4556 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4558 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4559 pCreateInfo
->pVertexInputState
;
4560 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4562 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4563 const VkVertexInputAttributeDescription
*desc
=
4564 &vi_info
->pVertexAttributeDescriptions
[i
];
4565 unsigned loc
= desc
->location
;
4566 const struct vk_format_description
*format_desc
;
4568 format_desc
= vk_format_description(desc
->format
);
4570 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4573 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4574 const VkVertexInputBindingDescription
*desc
=
4575 &vi_info
->pVertexBindingDescriptions
[i
];
4577 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4578 pipeline
->num_vertex_bindings
=
4579 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4583 static struct radv_shader_variant
*
4584 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4588 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4589 struct radv_shader_variant
*shader
=
4590 radv_get_shader(pipeline
, i
);
4592 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4600 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4601 struct radv_device
*device
,
4602 struct radv_pipeline_cache
*cache
,
4603 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4604 const struct radv_graphics_pipeline_create_info
*extra
)
4607 bool has_view_index
= false;
4609 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
4610 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
4611 if (subpass
->view_mask
)
4612 has_view_index
= true;
4614 pipeline
->device
= device
;
4615 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4616 assert(pipeline
->layout
);
4618 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4620 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4621 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4622 radv_init_feedback(creation_feedback
);
4624 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4626 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4627 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4628 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4629 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4630 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4631 if(creation_feedback
)
4632 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4635 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
4636 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
, pipeline_feedback
, stage_feedbacks
);
4638 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4639 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4641 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
4643 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
4645 if (radv_pipeline_has_gs(pipeline
)) {
4646 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4647 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4648 } else if (radv_pipeline_has_tess(pipeline
)) {
4649 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
4650 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4652 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4653 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4655 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4657 if (extra
&& extra
->use_rectlist
) {
4658 prim
= V_008958_DI_PT_RECTLIST
;
4659 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4660 pipeline
->graphics
.can_use_guardband
= true;
4661 if (radv_pipeline_has_ngg(pipeline
))
4662 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4664 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
4665 /* prim vertex count will need TESS changes */
4666 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
4668 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
4670 /* Ensure that some export memory is always allocated, for two reasons:
4672 * 1) Correctness: The hardware ignores the EXEC mask if no export
4673 * memory is allocated, so KILL and alpha test do not work correctly
4675 * 2) Performance: Every shader needs at least a NULL export, even when
4676 * it writes no color/depth output. The NULL export instruction
4677 * stalls without this setting.
4679 * Don't add this to CB_SHADER_MASK.
4681 * GFX10 supports pixel shaders without exports by setting both the
4682 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4683 * instructions if any are present.
4685 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4686 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
4687 ps
->info
.ps
.can_discard
) &&
4688 !blend
.spi_shader_col_format
) {
4689 if (!ps
->info
.ps
.writes_z
&&
4690 !ps
->info
.ps
.writes_stencil
&&
4691 !ps
->info
.ps
.writes_sample_mask
)
4692 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
4695 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4696 if (pipeline
->shaders
[i
]) {
4697 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
4701 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4702 struct radv_shader_variant
*gs
=
4703 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4705 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
4708 struct radv_tessellation_state tess
= {0};
4709 if (radv_pipeline_has_tess(pipeline
)) {
4710 if (prim
== V_008958_DI_PT_PATCH
) {
4711 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
4712 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
4714 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
4717 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
4719 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
4721 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
4722 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
4724 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
4725 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
4726 if (loc
->sgpr_idx
!= -1) {
4727 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
4728 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
4729 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
4730 pipeline
->graphics
.vtx_emit_num
= 3;
4732 pipeline
->graphics
.vtx_emit_num
= 2;
4735 /* Find the last vertex shader stage that eventually uses streamout. */
4736 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
4738 result
= radv_pipeline_scratch_init(device
, pipeline
);
4739 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
4745 radv_graphics_pipeline_create(
4747 VkPipelineCache _cache
,
4748 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4749 const struct radv_graphics_pipeline_create_info
*extra
,
4750 const VkAllocationCallbacks
*pAllocator
,
4751 VkPipeline
*pPipeline
)
4753 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4754 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4755 struct radv_pipeline
*pipeline
;
4758 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
4759 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4760 if (pipeline
== NULL
)
4761 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4763 result
= radv_pipeline_init(pipeline
, device
, cache
,
4764 pCreateInfo
, extra
);
4765 if (result
!= VK_SUCCESS
) {
4766 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
4770 *pPipeline
= radv_pipeline_to_handle(pipeline
);
4775 VkResult
radv_CreateGraphicsPipelines(
4777 VkPipelineCache pipelineCache
,
4779 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
4780 const VkAllocationCallbacks
* pAllocator
,
4781 VkPipeline
* pPipelines
)
4783 VkResult result
= VK_SUCCESS
;
4786 for (; i
< count
; i
++) {
4788 r
= radv_graphics_pipeline_create(_device
,
4791 NULL
, pAllocator
, &pPipelines
[i
]);
4792 if (r
!= VK_SUCCESS
) {
4794 pPipelines
[i
] = VK_NULL_HANDLE
;
4803 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
4805 struct radv_shader_variant
*compute_shader
;
4806 struct radv_device
*device
= pipeline
->device
;
4807 unsigned threads_per_threadgroup
;
4808 unsigned threadgroups_per_cu
= 1;
4809 unsigned waves_per_threadgroup
;
4810 unsigned max_waves_per_sh
= 0;
4813 pipeline
->cs
.buf
= malloc(20 * 4);
4814 pipeline
->cs
.max_dw
= 20;
4816 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4817 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
4819 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
4820 radeon_emit(&pipeline
->cs
, va
>> 8);
4821 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
4823 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
4824 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
4825 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
4827 radeon_set_sh_reg(&pipeline
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
4828 S_00B860_WAVES(pipeline
->max_waves
) |
4829 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
4831 /* Calculate best compute resource limits. */
4832 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
4833 compute_shader
->info
.cs
.block_size
[1] *
4834 compute_shader
->info
.cs
.block_size
[2];
4835 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
4836 device
->physical_device
->cs_wave_size
);
4838 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4839 waves_per_threadgroup
== 1)
4840 threadgroups_per_cu
= 2;
4842 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
4843 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
4844 waves_per_threadgroup
,
4846 threadgroups_per_cu
));
4848 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4849 radeon_emit(&pipeline
->cs
,
4850 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
4851 radeon_emit(&pipeline
->cs
,
4852 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
4853 radeon_emit(&pipeline
->cs
,
4854 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
4856 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
4859 static VkResult
radv_compute_pipeline_create(
4861 VkPipelineCache _cache
,
4862 const VkComputePipelineCreateInfo
* pCreateInfo
,
4863 const VkAllocationCallbacks
* pAllocator
,
4864 VkPipeline
* pPipeline
)
4866 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4867 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4868 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4869 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4870 struct radv_pipeline
*pipeline
;
4873 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
4874 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4875 if (pipeline
== NULL
)
4876 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4878 pipeline
->device
= device
;
4879 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4880 assert(pipeline
->layout
);
4882 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4883 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4884 radv_init_feedback(creation_feedback
);
4886 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4887 if (creation_feedback
)
4888 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
4890 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
4891 radv_create_shaders(pipeline
, device
, cache
, &(struct radv_pipeline_key
) {0}, pStages
, pCreateInfo
->flags
, NULL
, pipeline_feedback
, stage_feedbacks
);
4893 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
4894 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
4895 result
= radv_pipeline_scratch_init(device
, pipeline
);
4896 if (result
!= VK_SUCCESS
) {
4897 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
4901 radv_compute_generate_pm4(pipeline
);
4903 *pPipeline
= radv_pipeline_to_handle(pipeline
);
4908 VkResult
radv_CreateComputePipelines(
4910 VkPipelineCache pipelineCache
,
4912 const VkComputePipelineCreateInfo
* pCreateInfos
,
4913 const VkAllocationCallbacks
* pAllocator
,
4914 VkPipeline
* pPipelines
)
4916 VkResult result
= VK_SUCCESS
;
4919 for (; i
< count
; i
++) {
4921 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
4923 pAllocator
, &pPipelines
[i
]);
4924 if (r
!= VK_SUCCESS
) {
4926 pPipelines
[i
] = VK_NULL_HANDLE
;
4934 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
4937 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
4938 if (pipeline
->shaders
[i
])
4939 ret
+= i
== MESA_SHADER_GEOMETRY
? 2u : 1u;
4945 static struct radv_shader_variant
*
4946 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
4948 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
4949 if (!pipeline
->shaders
[i
])
4953 return pipeline
->shaders
[i
];
4958 if (i
== MESA_SHADER_GEOMETRY
) {
4961 return pipeline
->gs_copy_shader
;
4971 /* Basically strlcpy (which does not exist on linux) specialized for
4973 static void desc_copy(char *desc
, const char *src
) {
4974 int len
= strlen(src
);
4975 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
4976 memcpy(desc
, src
, len
);
4977 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
4980 VkResult
radv_GetPipelineExecutablePropertiesKHR(
4982 const VkPipelineInfoKHR
* pPipelineInfo
,
4983 uint32_t* pExecutableCount
,
4984 VkPipelineExecutablePropertiesKHR
* pProperties
)
4986 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
4987 const uint32_t total_count
= radv_get_executable_count(pipeline
);
4990 *pExecutableCount
= total_count
;
4994 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
4995 for (unsigned i
= 0, executable_idx
= 0;
4996 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
4997 if (!pipeline
->shaders
[i
])
4999 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5000 const char *name
= NULL
;
5001 const char *description
= NULL
;
5003 case MESA_SHADER_VERTEX
:
5004 name
= "Vertex Shader";
5005 description
= "Vulkan Vertex Shader";
5007 case MESA_SHADER_TESS_CTRL
:
5008 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5009 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5010 name
= "Vertex + Tessellation Control Shaders";
5011 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5013 name
= "Tessellation Control Shader";
5014 description
= "Vulkan Tessellation Control Shader";
5017 case MESA_SHADER_TESS_EVAL
:
5018 name
= "Tessellation Evaluation Shader";
5019 description
= "Vulkan Tessellation Evaluation Shader";
5021 case MESA_SHADER_GEOMETRY
:
5022 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5023 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5024 name
= "Tessellation Evaluation + Geometry Shaders";
5025 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5026 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5027 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5028 name
= "Vertex + Geometry Shader";
5029 description
= "Combined Vulkan Vertex and Geometry Shaders";
5031 name
= "Geometry Shader";
5032 description
= "Vulkan Geometry Shader";
5035 case MESA_SHADER_FRAGMENT
:
5036 name
= "Fragment Shader";
5037 description
= "Vulkan Fragment Shader";
5039 case MESA_SHADER_COMPUTE
:
5040 name
= "Compute Shader";
5041 description
= "Vulkan Compute Shader";
5045 desc_copy(pProperties
[executable_idx
].name
, name
);
5046 desc_copy(pProperties
[executable_idx
].description
, description
);
5049 if (i
== MESA_SHADER_GEOMETRY
) {
5050 assert(pipeline
->gs_copy_shader
);
5051 if (executable_idx
>= count
)
5054 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5055 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5056 desc_copy(pProperties
[executable_idx
].description
,
5057 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5063 for (unsigned i
= 0; i
< count
; ++i
)
5064 pProperties
[i
].subgroupSize
= 64;
5066 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5067 *pExecutableCount
= count
;
5071 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5073 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5074 uint32_t* pStatisticCount
,
5075 VkPipelineExecutableStatisticKHR
* pStatistics
)
5077 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5078 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5079 gl_shader_stage stage
;
5080 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5082 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5083 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5084 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5086 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5087 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5088 VkResult result
= VK_SUCCESS
;
5091 desc_copy(s
->name
, "SGPRs");
5092 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5093 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5094 s
->value
.u64
= shader
->config
.num_sgprs
;
5099 desc_copy(s
->name
, "VGPRs");
5100 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5101 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5102 s
->value
.u64
= shader
->config
.num_vgprs
;
5107 desc_copy(s
->name
, "Spilled SGPRs");
5108 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5109 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5110 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5115 desc_copy(s
->name
, "Spilled VGPRs");
5116 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5117 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5118 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5123 desc_copy(s
->name
, "PrivMem VGPRs");
5124 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5125 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5126 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5131 desc_copy(s
->name
, "Code size");
5132 desc_copy(s
->description
, "Code size in bytes");
5133 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5134 s
->value
.u64
= shader
->exec_size
;
5139 desc_copy(s
->name
, "LDS size");
5140 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5141 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5142 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5147 desc_copy(s
->name
, "Scratch size");
5148 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5149 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5150 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5155 desc_copy(s
->name
, "Subgroups per SIMD");
5156 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5157 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5158 s
->value
.u64
= max_waves
;
5163 *pStatisticCount
= s
- pStatistics
;
5165 *pStatisticCount
= end
- pStatistics
;
5166 result
= VK_INCOMPLETE
;
5168 *pStatisticCount
= s
- pStatistics
;
5174 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5176 size_t total_size
= strlen(src
) + 1;
5179 *data_size
= total_size
;
5183 size_t size
= MIN2(total_size
, *data_size
);
5185 memcpy(data
, src
, size
);
5187 *((char*)data
+ size
- 1) = 0;
5188 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5191 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5193 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5194 uint32_t* pInternalRepresentationCount
,
5195 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5197 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5198 gl_shader_stage stage
;
5199 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5201 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5202 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5203 VkResult result
= VK_SUCCESS
;
5207 desc_copy(p
->name
, "NIR Shader(s)");
5208 desc_copy(p
->description
, "The optimized NIR shader(s)");
5209 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5210 result
= VK_INCOMPLETE
;
5217 desc_copy(p
->name
, "LLVM IR");
5218 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5219 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->llvm_ir_string
) != VK_SUCCESS
)
5220 result
= VK_INCOMPLETE
;
5227 desc_copy(p
->name
, "Assembly");
5228 desc_copy(p
->description
, "Final Assembly");
5229 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5230 result
= VK_INCOMPLETE
;
5234 if (!pInternalRepresentations
)
5235 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5237 result
= VK_INCOMPLETE
;
5238 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5240 *pInternalRepresentationCount
= p
- pInternalRepresentations
;