2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
33 #include "radv_shader.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
49 #include "ac_shader_util.h"
50 #include "main/menums.h"
52 struct radv_blend_state
{
53 uint32_t blend_enable_4bit
;
54 uint32_t need_src_alpha
;
56 uint32_t cb_color_control
;
57 uint32_t cb_target_mask
;
58 uint32_t cb_target_enabled_4bit
;
59 uint32_t sx_mrt_blend_opt
[8];
60 uint32_t cb_blend_control
[8];
62 uint32_t spi_shader_col_format
;
63 uint32_t cb_shader_mask
;
64 uint32_t db_alpha_to_mask
;
66 uint32_t commutative_4bit
;
68 bool single_cb_enable
;
69 bool mrt0_is_dual_src
;
72 struct radv_dsa_order_invariance
{
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
85 struct radv_tessellation_state
{
86 uint32_t ls_hs_config
;
92 struct radv_gs_state
{
93 uint32_t vgt_gs_onchip_cntl
;
94 uint32_t vgt_gs_max_prims_per_subgroup
;
95 uint32_t vgt_esgs_ring_itemsize
;
100 radv_pipeline_destroy(struct radv_device
*device
,
101 struct radv_pipeline
*pipeline
,
102 const VkAllocationCallbacks
* allocator
)
104 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
105 if (pipeline
->shaders
[i
])
106 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
108 if (pipeline
->gs_copy_shader
)
109 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
112 free(pipeline
->cs
.buf
);
113 vk_free2(&device
->alloc
, allocator
, pipeline
);
116 void radv_DestroyPipeline(
118 VkPipeline _pipeline
,
119 const VkAllocationCallbacks
* pAllocator
)
121 RADV_FROM_HANDLE(radv_device
, device
, _device
);
122 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
127 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
130 static uint32_t get_hash_flags(struct radv_device
*device
)
132 uint32_t hash_flags
= 0;
134 if (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
)
135 hash_flags
|= RADV_HASH_SHADER_UNSAFE_MATH
;
136 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
137 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
142 radv_pipeline_scratch_init(struct radv_device
*device
,
143 struct radv_pipeline
*pipeline
)
145 unsigned scratch_bytes_per_wave
= 0;
146 unsigned max_waves
= 0;
147 unsigned min_waves
= 1;
149 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
150 if (pipeline
->shaders
[i
]) {
151 unsigned max_stage_waves
= device
->scratch_waves
;
153 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
154 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
156 max_stage_waves
= MIN2(max_stage_waves
,
157 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
158 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
159 max_waves
= MAX2(max_waves
, max_stage_waves
);
163 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
164 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
165 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
166 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
167 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
170 if (scratch_bytes_per_wave
)
171 max_waves
= MIN2(max_waves
, 0xffffffffu
/ scratch_bytes_per_wave
);
173 if (scratch_bytes_per_wave
&& max_waves
< min_waves
) {
174 /* Not really true at this moment, but will be true on first
175 * execution. Avoid having hanging shaders. */
176 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
178 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
179 pipeline
->max_waves
= max_waves
;
183 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
186 case VK_LOGIC_OP_CLEAR
:
187 return V_028808_ROP3_CLEAR
;
188 case VK_LOGIC_OP_AND
:
189 return V_028808_ROP3_AND
;
190 case VK_LOGIC_OP_AND_REVERSE
:
191 return V_028808_ROP3_AND_REVERSE
;
192 case VK_LOGIC_OP_COPY
:
193 return V_028808_ROP3_COPY
;
194 case VK_LOGIC_OP_AND_INVERTED
:
195 return V_028808_ROP3_AND_INVERTED
;
196 case VK_LOGIC_OP_NO_OP
:
197 return V_028808_ROP3_NO_OP
;
198 case VK_LOGIC_OP_XOR
:
199 return V_028808_ROP3_XOR
;
201 return V_028808_ROP3_OR
;
202 case VK_LOGIC_OP_NOR
:
203 return V_028808_ROP3_NOR
;
204 case VK_LOGIC_OP_EQUIVALENT
:
205 return V_028808_ROP3_EQUIVALENT
;
206 case VK_LOGIC_OP_INVERT
:
207 return V_028808_ROP3_INVERT
;
208 case VK_LOGIC_OP_OR_REVERSE
:
209 return V_028808_ROP3_OR_REVERSE
;
210 case VK_LOGIC_OP_COPY_INVERTED
:
211 return V_028808_ROP3_COPY_INVERTED
;
212 case VK_LOGIC_OP_OR_INVERTED
:
213 return V_028808_ROP3_OR_INVERTED
;
214 case VK_LOGIC_OP_NAND
:
215 return V_028808_ROP3_NAND
;
216 case VK_LOGIC_OP_SET
:
217 return V_028808_ROP3_SET
;
219 unreachable("Unhandled logic op");
224 static uint32_t si_translate_blend_function(VkBlendOp op
)
227 case VK_BLEND_OP_ADD
:
228 return V_028780_COMB_DST_PLUS_SRC
;
229 case VK_BLEND_OP_SUBTRACT
:
230 return V_028780_COMB_SRC_MINUS_DST
;
231 case VK_BLEND_OP_REVERSE_SUBTRACT
:
232 return V_028780_COMB_DST_MINUS_SRC
;
233 case VK_BLEND_OP_MIN
:
234 return V_028780_COMB_MIN_DST_SRC
;
235 case VK_BLEND_OP_MAX
:
236 return V_028780_COMB_MAX_DST_SRC
;
242 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
245 case VK_BLEND_FACTOR_ZERO
:
246 return V_028780_BLEND_ZERO
;
247 case VK_BLEND_FACTOR_ONE
:
248 return V_028780_BLEND_ONE
;
249 case VK_BLEND_FACTOR_SRC_COLOR
:
250 return V_028780_BLEND_SRC_COLOR
;
251 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
252 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
253 case VK_BLEND_FACTOR_DST_COLOR
:
254 return V_028780_BLEND_DST_COLOR
;
255 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
256 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
257 case VK_BLEND_FACTOR_SRC_ALPHA
:
258 return V_028780_BLEND_SRC_ALPHA
;
259 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
260 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
261 case VK_BLEND_FACTOR_DST_ALPHA
:
262 return V_028780_BLEND_DST_ALPHA
;
263 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
264 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
265 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
266 return V_028780_BLEND_CONSTANT_COLOR
;
267 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
268 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
269 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
270 return V_028780_BLEND_CONSTANT_ALPHA
;
271 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
272 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
273 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
274 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
275 case VK_BLEND_FACTOR_SRC1_COLOR
:
276 return V_028780_BLEND_SRC1_COLOR
;
277 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
278 return V_028780_BLEND_INV_SRC1_COLOR
;
279 case VK_BLEND_FACTOR_SRC1_ALPHA
:
280 return V_028780_BLEND_SRC1_ALPHA
;
281 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
282 return V_028780_BLEND_INV_SRC1_ALPHA
;
288 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
291 case VK_BLEND_OP_ADD
:
292 return V_028760_OPT_COMB_ADD
;
293 case VK_BLEND_OP_SUBTRACT
:
294 return V_028760_OPT_COMB_SUBTRACT
;
295 case VK_BLEND_OP_REVERSE_SUBTRACT
:
296 return V_028760_OPT_COMB_REVSUBTRACT
;
297 case VK_BLEND_OP_MIN
:
298 return V_028760_OPT_COMB_MIN
;
299 case VK_BLEND_OP_MAX
:
300 return V_028760_OPT_COMB_MAX
;
302 return V_028760_OPT_COMB_BLEND_DISABLED
;
306 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
309 case VK_BLEND_FACTOR_ZERO
:
310 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
311 case VK_BLEND_FACTOR_ONE
:
312 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
313 case VK_BLEND_FACTOR_SRC_COLOR
:
314 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
315 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
316 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
317 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
318 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
319 case VK_BLEND_FACTOR_SRC_ALPHA
:
320 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
321 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
322 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
323 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
324 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
325 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
327 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
332 * Get rid of DST in the blend factors by commuting the operands:
333 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
335 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
336 unsigned *dst_factor
, unsigned expected_dst
,
337 unsigned replacement_src
)
339 if (*src_factor
== expected_dst
&&
340 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
341 *src_factor
= VK_BLEND_FACTOR_ZERO
;
342 *dst_factor
= replacement_src
;
344 /* Commuting the operands requires reversing subtractions. */
345 if (*func
== VK_BLEND_OP_SUBTRACT
)
346 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
347 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
348 *func
= VK_BLEND_OP_SUBTRACT
;
352 static bool si_blend_factor_uses_dst(unsigned factor
)
354 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
355 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
356 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
357 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
358 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
361 static bool is_dual_src(VkBlendFactor factor
)
364 case VK_BLEND_FACTOR_SRC1_COLOR
:
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
366 case VK_BLEND_FACTOR_SRC1_ALPHA
:
367 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
374 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
376 bool blend_need_alpha
)
378 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
379 unsigned format
, ntype
, swap
;
381 /* Alpha is needed for alpha-to-coverage.
382 * Blending may be with or without alpha.
384 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
385 unsigned alpha
= 0; /* exports alpha, but may not support blending */
386 unsigned blend
= 0; /* supports blending, but may not export alpha */
387 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
389 format
= radv_translate_colorformat(vk_format
);
390 ntype
= radv_translate_color_numformat(vk_format
, desc
,
391 vk_format_get_first_non_void_channel(vk_format
));
392 swap
= radv_translate_colorswap(vk_format
, false);
394 /* Choose the SPI color formats. These are required values for Stoney/RB+.
395 * Other chips have multiple choices, though they are not necessarily better.
398 case V_028C70_COLOR_5_6_5
:
399 case V_028C70_COLOR_1_5_5_5
:
400 case V_028C70_COLOR_5_5_5_1
:
401 case V_028C70_COLOR_4_4_4_4
:
402 case V_028C70_COLOR_10_11_11
:
403 case V_028C70_COLOR_11_11_10
:
404 case V_028C70_COLOR_8
:
405 case V_028C70_COLOR_8_8
:
406 case V_028C70_COLOR_8_8_8_8
:
407 case V_028C70_COLOR_10_10_10_2
:
408 case V_028C70_COLOR_2_10_10_10
:
409 if (ntype
== V_028C70_NUMBER_UINT
)
410 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
411 else if (ntype
== V_028C70_NUMBER_SINT
)
412 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
414 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
417 case V_028C70_COLOR_16
:
418 case V_028C70_COLOR_16_16
:
419 case V_028C70_COLOR_16_16_16_16
:
420 if (ntype
== V_028C70_NUMBER_UNORM
||
421 ntype
== V_028C70_NUMBER_SNORM
) {
422 /* UNORM16 and SNORM16 don't support blending */
423 if (ntype
== V_028C70_NUMBER_UNORM
)
424 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
426 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
428 /* Use 32 bits per channel for blending. */
429 if (format
== V_028C70_COLOR_16
) {
430 if (swap
== V_028C70_SWAP_STD
) { /* R */
431 blend
= V_028714_SPI_SHADER_32_R
;
432 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
433 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
434 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
437 } else if (format
== V_028C70_COLOR_16_16
) {
438 if (swap
== V_028C70_SWAP_STD
) { /* RG */
439 blend
= V_028714_SPI_SHADER_32_GR
;
440 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
441 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
442 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
445 } else /* 16_16_16_16 */
446 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
447 } else if (ntype
== V_028C70_NUMBER_UINT
)
448 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
449 else if (ntype
== V_028C70_NUMBER_SINT
)
450 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
451 else if (ntype
== V_028C70_NUMBER_FLOAT
)
452 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
457 case V_028C70_COLOR_32
:
458 if (swap
== V_028C70_SWAP_STD
) { /* R */
459 blend
= normal
= V_028714_SPI_SHADER_32_R
;
460 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
461 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
462 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
467 case V_028C70_COLOR_32_32
:
468 if (swap
== V_028C70_SWAP_STD
) { /* RG */
469 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
470 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
471 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
472 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
477 case V_028C70_COLOR_32_32_32_32
:
478 case V_028C70_COLOR_8_24
:
479 case V_028C70_COLOR_24_8
:
480 case V_028C70_COLOR_X24_8_32_FLOAT
:
481 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
485 unreachable("unhandled blend format");
488 if (blend_enable
&& blend_need_alpha
)
490 else if(blend_need_alpha
)
492 else if(blend_enable
)
499 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
500 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
501 struct radv_blend_state
*blend
)
503 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
504 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
505 unsigned col_format
= 0;
506 unsigned num_targets
;
508 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
511 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
512 cf
= V_028714_SPI_SHADER_ZERO
;
514 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
516 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
518 cf
= si_choose_spi_color_format(attachment
->format
,
520 blend
->need_src_alpha
& (1 << i
));
523 col_format
|= cf
<< (4 * i
);
526 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
527 /* When a subpass doesn't have any color attachments, write the
528 * alpha channel of MRT0 when alpha coverage is enabled because
529 * the depth attachment needs it.
531 col_format
|= V_028714_SPI_SHADER_32_AR
;
534 /* If the i-th target format is set, all previous target formats must
535 * be non-zero to avoid hangs.
537 num_targets
= (util_last_bit(col_format
) + 3) / 4;
538 for (unsigned i
= 0; i
< num_targets
; i
++) {
539 if (!(col_format
& (0xf << (i
* 4)))) {
540 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
544 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
546 if (blend
->mrt0_is_dual_src
)
547 col_format
|= (col_format
& 0xf) << 4;
548 blend
->spi_shader_col_format
= col_format
;
552 format_is_int8(VkFormat format
)
554 const struct vk_format_description
*desc
= vk_format_description(format
);
555 int channel
= vk_format_get_first_non_void_channel(format
);
557 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
558 desc
->channel
[channel
].size
== 8;
562 format_is_int10(VkFormat format
)
564 const struct vk_format_description
*desc
= vk_format_description(format
);
566 if (desc
->nr_channels
!= 4)
568 for (unsigned i
= 0; i
< 4; i
++) {
569 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
576 * Ordered so that for each i,
577 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
579 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
580 VK_FORMAT_R32_SFLOAT
,
581 VK_FORMAT_R32G32_SFLOAT
,
582 VK_FORMAT_R8G8B8A8_UNORM
,
583 VK_FORMAT_R16G16B16A16_UNORM
,
584 VK_FORMAT_R16G16B16A16_SNORM
,
585 VK_FORMAT_R16G16B16A16_UINT
,
586 VK_FORMAT_R16G16B16A16_SINT
,
587 VK_FORMAT_R32G32B32A32_SFLOAT
,
588 VK_FORMAT_R8G8B8A8_UINT
,
589 VK_FORMAT_R8G8B8A8_SINT
,
590 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
591 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
594 unsigned radv_format_meta_fs_key(VkFormat format
)
596 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
598 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
599 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
600 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
602 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
603 bool is_int8
= format_is_int8(format
);
604 bool is_int10
= format_is_int10(format
);
606 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
610 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
611 unsigned *is_int8
, unsigned *is_int10
)
613 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
614 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
618 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
619 struct radv_render_pass_attachment
*attachment
;
621 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
624 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
626 if (format_is_int8(attachment
->format
))
628 if (format_is_int10(attachment
->format
))
634 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
635 VkBlendOp op
, VkBlendFactor src
,
636 VkBlendFactor dst
, unsigned chanmask
)
638 /* Src factor is allowed when it does not depend on Dst. */
639 static const uint32_t src_allowed
=
640 (1u << VK_BLEND_FACTOR_ONE
) |
641 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
642 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
643 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
644 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
645 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
646 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
647 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
648 (1u << VK_BLEND_FACTOR_ZERO
) |
649 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
650 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
651 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
652 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
653 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
654 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
656 if (dst
== VK_BLEND_FACTOR_ONE
&&
657 (src_allowed
& (1u << src
))) {
658 /* Addition is commutative, but floating point addition isn't
659 * associative: subtle changes can be introduced via different
660 * rounding. Be conservative, only enable for min and max.
662 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
663 blend
->commutative_4bit
|= chanmask
;
667 static struct radv_blend_state
668 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
669 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
670 const struct radv_graphics_pipeline_create_info
*extra
)
672 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
673 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
674 struct radv_blend_state blend
= {0};
675 unsigned mode
= V_028808_CB_NORMAL
;
681 if (extra
&& extra
->custom_blend_mode
) {
682 blend
.single_cb_enable
= true;
683 mode
= extra
->custom_blend_mode
;
685 blend
.cb_color_control
= 0;
686 if (vkblend
->logicOpEnable
)
687 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
689 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
691 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
692 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
693 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
694 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
695 S_028B70_OFFSET_ROUND(1);
697 if (vkms
&& vkms
->alphaToCoverageEnable
) {
698 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
699 blend
.need_src_alpha
|= 0x1;
702 blend
.cb_target_mask
= 0;
703 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
704 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
705 unsigned blend_cntl
= 0;
706 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
707 VkBlendOp eqRGB
= att
->colorBlendOp
;
708 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
709 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
710 VkBlendOp eqA
= att
->alphaBlendOp
;
711 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
712 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
714 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
716 if (!att
->colorWriteMask
)
719 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
720 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
721 if (!att
->blendEnable
) {
722 blend
.cb_blend_control
[i
] = blend_cntl
;
726 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
728 blend
.mrt0_is_dual_src
= true;
730 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
731 srcRGB
= VK_BLEND_FACTOR_ONE
;
732 dstRGB
= VK_BLEND_FACTOR_ONE
;
734 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
735 srcA
= VK_BLEND_FACTOR_ONE
;
736 dstA
= VK_BLEND_FACTOR_ONE
;
739 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
741 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
744 /* Blending optimizations for RB+.
745 * These transformations don't change the behavior.
747 * First, get rid of DST in the blend factors:
748 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
750 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
751 VK_BLEND_FACTOR_DST_COLOR
,
752 VK_BLEND_FACTOR_SRC_COLOR
);
754 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
755 VK_BLEND_FACTOR_DST_COLOR
,
756 VK_BLEND_FACTOR_SRC_COLOR
);
758 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
759 VK_BLEND_FACTOR_DST_ALPHA
,
760 VK_BLEND_FACTOR_SRC_ALPHA
);
762 /* Look up the ideal settings from tables. */
763 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
764 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
765 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
766 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
768 /* Handle interdependencies. */
769 if (si_blend_factor_uses_dst(srcRGB
))
770 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
771 if (si_blend_factor_uses_dst(srcA
))
772 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
774 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
775 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
776 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
777 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
778 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
780 /* Set the final value. */
781 blend
.sx_mrt_blend_opt
[i
] =
782 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
783 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
784 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
785 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
786 S_028760_ALPHA_DST_OPT(dstA_opt
) |
787 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
788 blend_cntl
|= S_028780_ENABLE(1);
790 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
791 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
792 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
793 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
794 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
795 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
796 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
797 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
799 blend
.cb_blend_control
[i
] = blend_cntl
;
801 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
803 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
804 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
805 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
806 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
807 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
808 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
809 blend
.need_src_alpha
|= 1 << i
;
811 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
812 blend
.cb_blend_control
[i
] = 0;
813 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
816 if (pipeline
->device
->physical_device
->has_rbplus
) {
817 /* Disable RB+ blend optimizations for dual source blending. */
818 if (blend
.mrt0_is_dual_src
) {
819 for (i
= 0; i
< 8; i
++) {
820 blend
.sx_mrt_blend_opt
[i
] =
821 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
822 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
826 /* RB+ doesn't work with dual source blending, logic op and
829 if (blend
.mrt0_is_dual_src
|| vkblend
->logicOpEnable
||
830 mode
== V_028808_CB_RESOLVE
)
831 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
834 if (blend
.cb_target_mask
)
835 blend
.cb_color_control
|= S_028808_MODE(mode
);
837 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
839 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
843 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
846 case VK_STENCIL_OP_KEEP
:
847 return V_02842C_STENCIL_KEEP
;
848 case VK_STENCIL_OP_ZERO
:
849 return V_02842C_STENCIL_ZERO
;
850 case VK_STENCIL_OP_REPLACE
:
851 return V_02842C_STENCIL_REPLACE_TEST
;
852 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
853 return V_02842C_STENCIL_ADD_CLAMP
;
854 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
855 return V_02842C_STENCIL_SUB_CLAMP
;
856 case VK_STENCIL_OP_INVERT
:
857 return V_02842C_STENCIL_INVERT
;
858 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
859 return V_02842C_STENCIL_ADD_WRAP
;
860 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
861 return V_02842C_STENCIL_SUB_WRAP
;
867 static uint32_t si_translate_fill(VkPolygonMode func
)
870 case VK_POLYGON_MODE_FILL
:
871 return V_028814_X_DRAW_TRIANGLES
;
872 case VK_POLYGON_MODE_LINE
:
873 return V_028814_X_DRAW_LINES
;
874 case VK_POLYGON_MODE_POINT
:
875 return V_028814_X_DRAW_POINTS
;
878 return V_028814_X_DRAW_POINTS
;
882 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo
*vkms
)
884 uint32_t num_samples
= vkms
->rasterizationSamples
;
885 uint32_t ps_iter_samples
= 1;
887 if (vkms
->sampleShadingEnable
) {
888 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
889 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
891 return ps_iter_samples
;
895 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
897 return pCreateInfo
->depthTestEnable
&&
898 pCreateInfo
->depthWriteEnable
&&
899 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
903 radv_writes_stencil(const VkStencilOpState
*state
)
905 return state
->writeMask
&&
906 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
907 state
->passOp
!= VK_STENCIL_OP_KEEP
||
908 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
912 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
914 return pCreateInfo
->stencilTestEnable
&&
915 (radv_writes_stencil(&pCreateInfo
->front
) ||
916 radv_writes_stencil(&pCreateInfo
->back
));
920 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
922 return radv_is_depth_write_enabled(pCreateInfo
) ||
923 radv_is_stencil_write_enabled(pCreateInfo
);
927 radv_order_invariant_stencil_op(VkStencilOp op
)
929 /* REPLACE is normally order invariant, except when the stencil
930 * reference value is written by the fragment shader. Tracking this
931 * interaction does not seem worth the effort, so be conservative.
933 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
934 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
935 op
!= VK_STENCIL_OP_REPLACE
;
939 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
941 /* Compute whether, assuming Z writes are disabled, this stencil state
942 * is order invariant in the sense that the set of passing fragments as
943 * well as the final stencil buffer result does not depend on the order
946 return !state
->writeMask
||
947 /* The following assumes that Z writes are disabled. */
948 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
949 radv_order_invariant_stencil_op(state
->passOp
) &&
950 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
951 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
952 radv_order_invariant_stencil_op(state
->failOp
));
956 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
957 struct radv_blend_state
*blend
,
958 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
960 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
961 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
962 unsigned colormask
= blend
->cb_target_enabled_4bit
;
964 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
967 /* Be conservative if a logic operation is enabled with color buffers. */
968 if (colormask
&& pCreateInfo
->pColorBlendState
->logicOpEnable
)
971 /* Default depth/stencil invariance when no attachment is bound. */
972 struct radv_dsa_order_invariance dsa_order_invariant
= {
973 .zs
= true, .pass_set
= true
976 if (pCreateInfo
->pDepthStencilState
&&
977 subpass
->depth_stencil_attachment
) {
978 const VkPipelineDepthStencilStateCreateInfo
*vkds
=
979 pCreateInfo
->pDepthStencilState
;
980 struct radv_render_pass_attachment
*attachment
=
981 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
982 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
983 struct radv_dsa_order_invariance order_invariance
[2];
984 struct radv_shader_variant
*ps
=
985 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
987 /* Compute depth/stencil order invariance in order to know if
988 * it's safe to enable out-of-order.
990 bool zfunc_is_ordered
=
991 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
992 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
993 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
994 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
995 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
997 bool nozwrite_and_order_invariant_stencil
=
998 !radv_is_ds_write_enabled(vkds
) ||
999 (!radv_is_depth_write_enabled(vkds
) &&
1000 radv_order_invariant_stencil_state(&vkds
->front
) &&
1001 radv_order_invariant_stencil_state(&vkds
->back
));
1003 order_invariance
[1].zs
=
1004 nozwrite_and_order_invariant_stencil
||
1005 (!radv_is_stencil_write_enabled(vkds
) &&
1007 order_invariance
[0].zs
=
1008 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1010 order_invariance
[1].pass_set
=
1011 nozwrite_and_order_invariant_stencil
||
1012 (!radv_is_stencil_write_enabled(vkds
) &&
1013 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1014 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1015 order_invariance
[0].pass_set
=
1016 !radv_is_depth_write_enabled(vkds
) ||
1017 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1018 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1020 dsa_order_invariant
= order_invariance
[has_stencil
];
1021 if (!dsa_order_invariant
.zs
)
1024 /* The set of PS invocations is always order invariant,
1025 * except when early Z/S tests are requested.
1028 ps
->info
.info
.ps
.writes_memory
&&
1029 ps
->info
.fs
.early_fragment_test
&&
1030 !dsa_order_invariant
.pass_set
)
1033 /* Determine if out-of-order rasterization should be disabled
1034 * when occlusion queries are used.
1036 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1037 !dsa_order_invariant
.pass_set
;
1040 /* No color buffers are enabled for writing. */
1044 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1047 /* Only commutative blending. */
1048 if (blendmask
& ~blend
->commutative_4bit
)
1051 if (!dsa_order_invariant
.pass_set
)
1055 if (colormask
& ~blendmask
)
1062 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1063 struct radv_blend_state
*blend
,
1064 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1066 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
1067 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1068 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1069 bool out_of_order_rast
= false;
1070 int ps_iter_samples
= 1;
1071 uint32_t mask
= 0xffff;
1074 ms
->num_samples
= vkms
->rasterizationSamples
;
1076 ms
->num_samples
= 1;
1079 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
1080 if (vkms
&& !vkms
->sampleShadingEnable
&& pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.force_persample
) {
1081 ps_iter_samples
= ms
->num_samples
;
1084 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1085 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1086 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1087 /* Out-of-order rasterization is explicitly enabled by the
1090 out_of_order_rast
= true;
1092 /* Determine if the driver can enable out-of-order
1093 * rasterization internally.
1096 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1099 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1100 ms
->pa_sc_aa_config
= 0;
1101 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1102 S_028804_INCOHERENT_EQAA_READS(1) |
1103 S_028804_INTERPOLATE_COMP_Z(1) |
1104 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1105 ms
->pa_sc_mode_cntl_1
=
1106 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1107 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1108 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1109 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1111 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1112 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1113 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1114 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1115 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1116 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1117 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1118 S_028A48_VPORT_SCISSOR_ENABLE(1);
1120 if (ms
->num_samples
> 1) {
1121 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1122 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1123 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1124 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1125 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1126 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1127 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1128 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1129 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1130 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1131 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1132 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1133 if (ps_iter_samples
> 1)
1134 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1137 if (vkms
&& vkms
->pSampleMask
) {
1138 mask
= vkms
->pSampleMask
[0] & 0xffff;
1141 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1142 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1146 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1149 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1150 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1151 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1152 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1153 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1155 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1156 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1157 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1158 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1159 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1160 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1163 unreachable("unhandled primitive type");
1168 si_translate_prim(enum VkPrimitiveTopology topology
)
1171 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1172 return V_008958_DI_PT_POINTLIST
;
1173 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1174 return V_008958_DI_PT_LINELIST
;
1175 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1176 return V_008958_DI_PT_LINESTRIP
;
1177 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1178 return V_008958_DI_PT_TRILIST
;
1179 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1180 return V_008958_DI_PT_TRISTRIP
;
1181 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1182 return V_008958_DI_PT_TRIFAN
;
1183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1184 return V_008958_DI_PT_LINELIST_ADJ
;
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1186 return V_008958_DI_PT_LINESTRIP_ADJ
;
1187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1188 return V_008958_DI_PT_TRILIST_ADJ
;
1189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1190 return V_008958_DI_PT_TRISTRIP_ADJ
;
1191 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1192 return V_008958_DI_PT_PATCH
;
1200 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1203 case 0: /* GL_POINTS */
1204 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1205 case 1: /* GL_LINES */
1206 case 3: /* GL_LINE_STRIP */
1207 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1208 case 0x8E7A: /* GL_ISOLINES */
1209 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1211 case 4: /* GL_TRIANGLES */
1212 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1213 case 5: /* GL_TRIANGLE_STRIP */
1214 case 7: /* GL_QUADS */
1215 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1223 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1226 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1227 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1228 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1229 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1230 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1233 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1234 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1236 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1238 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1239 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1246 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1249 case VK_DYNAMIC_STATE_VIEWPORT
:
1250 return RADV_DYNAMIC_VIEWPORT
;
1251 case VK_DYNAMIC_STATE_SCISSOR
:
1252 return RADV_DYNAMIC_SCISSOR
;
1253 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1254 return RADV_DYNAMIC_LINE_WIDTH
;
1255 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1256 return RADV_DYNAMIC_DEPTH_BIAS
;
1257 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1258 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1259 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1260 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1261 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1262 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1263 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1264 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1265 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1266 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1267 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1268 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1269 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1270 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1272 unreachable("Unhandled dynamic state");
1276 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1278 uint32_t states
= RADV_DYNAMIC_ALL
;
1280 /* If rasterization is disabled we do not care about any of the dynamic states,
1281 * since they are all rasterization related only. */
1282 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1285 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1286 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1288 if (!pCreateInfo
->pDepthStencilState
||
1289 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1290 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1292 if (!pCreateInfo
->pDepthStencilState
||
1293 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1294 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1295 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1296 RADV_DYNAMIC_STENCIL_REFERENCE
);
1298 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1299 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1301 if (!pCreateInfo
->pMultisampleState
||
1302 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1303 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1304 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1306 /* TODO: blend constants & line width. */
1313 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1314 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1316 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1317 uint32_t states
= needed_states
;
1318 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1319 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1321 pipeline
->dynamic_state
= default_dynamic_state
;
1322 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1324 if (pCreateInfo
->pDynamicState
) {
1325 /* Remove all of the states that are marked as dynamic */
1326 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1327 for (uint32_t s
= 0; s
< count
; s
++)
1328 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1331 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1333 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1334 assert(pCreateInfo
->pViewportState
);
1336 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1337 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1338 typed_memcpy(dynamic
->viewport
.viewports
,
1339 pCreateInfo
->pViewportState
->pViewports
,
1340 pCreateInfo
->pViewportState
->viewportCount
);
1344 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1345 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1346 if (states
& RADV_DYNAMIC_SCISSOR
) {
1347 typed_memcpy(dynamic
->scissor
.scissors
,
1348 pCreateInfo
->pViewportState
->pScissors
,
1349 pCreateInfo
->pViewportState
->scissorCount
);
1353 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1354 assert(pCreateInfo
->pRasterizationState
);
1355 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1358 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1359 assert(pCreateInfo
->pRasterizationState
);
1360 dynamic
->depth_bias
.bias
=
1361 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1362 dynamic
->depth_bias
.clamp
=
1363 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1364 dynamic
->depth_bias
.slope
=
1365 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1368 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1370 * pColorBlendState is [...] NULL if the pipeline has rasterization
1371 * disabled or if the subpass of the render pass the pipeline is
1372 * created against does not use any color attachments.
1374 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1375 assert(pCreateInfo
->pColorBlendState
);
1376 typed_memcpy(dynamic
->blend_constants
,
1377 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1380 /* If there is no depthstencil attachment, then don't read
1381 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1382 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1383 * no need to override the depthstencil defaults in
1384 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1386 * Section 9.2 of the Vulkan 1.0.15 spec says:
1388 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1389 * disabled or if the subpass of the render pass the pipeline is created
1390 * against does not use a depth/stencil attachment.
1392 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1393 assert(pCreateInfo
->pDepthStencilState
);
1395 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1396 dynamic
->depth_bounds
.min
=
1397 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1398 dynamic
->depth_bounds
.max
=
1399 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1402 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1403 dynamic
->stencil_compare_mask
.front
=
1404 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1405 dynamic
->stencil_compare_mask
.back
=
1406 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1409 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1410 dynamic
->stencil_write_mask
.front
=
1411 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1412 dynamic
->stencil_write_mask
.back
=
1413 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1416 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1417 dynamic
->stencil_reference
.front
=
1418 pCreateInfo
->pDepthStencilState
->front
.reference
;
1419 dynamic
->stencil_reference
.back
=
1420 pCreateInfo
->pDepthStencilState
->back
.reference
;
1424 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1425 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1426 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1427 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1428 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1429 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1430 discard_rectangle_info
->pDiscardRectangles
,
1431 discard_rectangle_info
->discardRectangleCount
);
1435 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1436 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1437 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1438 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1439 /* If sampleLocationsEnable is VK_FALSE, the default sample
1440 * locations are used and the values specified in
1441 * sampleLocationsInfo are ignored.
1443 if (sample_location_info
->sampleLocationsEnable
) {
1444 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1445 &sample_location_info
->sampleLocationsInfo
;
1447 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1449 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1450 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1451 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1452 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1453 pSampleLocationsInfo
->pSampleLocations
,
1454 pSampleLocationsInfo
->sampleLocationsCount
);
1458 pipeline
->dynamic_state
.mask
= states
;
1461 static struct radv_gs_state
1462 calculate_gs_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1463 const struct radv_pipeline
*pipeline
)
1465 struct radv_gs_state gs
= {0};
1466 struct radv_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1467 struct radv_es_output_info
*es_info
;
1468 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1469 es_info
= radv_pipeline_has_tess(pipeline
) ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1471 es_info
= radv_pipeline_has_tess(pipeline
) ?
1472 &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.es_info
:
1473 &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.es_info
;
1475 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1476 bool uses_adjacency
;
1477 switch(pCreateInfo
->pInputAssemblyState
->topology
) {
1478 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1479 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1480 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1481 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1482 uses_adjacency
= true;
1485 uses_adjacency
= false;
1489 /* All these are in dwords: */
1490 /* We can't allow using the whole LDS, because GS waves compete with
1491 * other shader stages for LDS space. */
1492 const unsigned max_lds_size
= 8 * 1024;
1493 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1494 unsigned esgs_lds_size
;
1496 /* All these are per subgroup: */
1497 const unsigned max_out_prims
= 32 * 1024;
1498 const unsigned max_es_verts
= 255;
1499 const unsigned ideal_gs_prims
= 64;
1500 unsigned max_gs_prims
, gs_prims
;
1501 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1503 if (uses_adjacency
|| gs_num_invocations
> 1)
1504 max_gs_prims
= 127 / gs_num_invocations
;
1508 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1509 * Make sure we don't go over the maximum value.
1511 if (gs_info
->gs
.vertices_out
> 0) {
1512 max_gs_prims
= MIN2(max_gs_prims
,
1514 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1516 assert(max_gs_prims
> 0);
1518 /* If the primitive has adjacency, halve the number of vertices
1519 * that will be reused in multiple primitives.
1521 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1523 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1524 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1526 /* Compute ESGS LDS size based on the worst case number of ES vertices
1527 * needed to create the target number of GS prims per subgroup.
1529 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1531 /* If total LDS usage is too big, refactor partitions based on ratio
1532 * of ESGS item sizes.
1534 if (esgs_lds_size
> max_lds_size
) {
1535 /* Our target GS Prims Per Subgroup was too large. Calculate
1536 * the maximum number of GS Prims Per Subgroup that will fit
1537 * into LDS, capped by the maximum that the hardware can support.
1539 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1541 assert(gs_prims
> 0);
1542 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1545 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1546 assert(esgs_lds_size
<= max_lds_size
);
1549 /* Now calculate remaining ESGS information. */
1551 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1553 es_verts
= max_es_verts
;
1555 /* Vertices for adjacency primitives are not always reused, so restore
1556 * it for ES_VERTS_PER_SUBGRP.
1558 min_es_verts
= gs_info
->gs
.vertices_in
;
1560 /* For normal primitives, the VGT only checks if they are past the ES
1561 * verts per subgroup after allocating a full GS primitive and if they
1562 * are, kick off a new subgroup. But if those additional ES verts are
1563 * unique (e.g. not reused) we need to make sure there is enough LDS
1564 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1566 es_verts
-= min_es_verts
- 1;
1568 uint32_t es_verts_per_subgroup
= es_verts
;
1569 uint32_t gs_prims_per_subgroup
= gs_prims
;
1570 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1571 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1572 gs
.lds_size
= align(esgs_lds_size
, 128) / 128;
1573 gs
.vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1574 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1575 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1576 gs
.vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1577 gs
.vgt_esgs_ring_itemsize
= esgs_itemsize
;
1578 assert(max_prims_per_subgroup
<= max_out_prims
);
1584 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
, const struct radv_gs_state
*gs
)
1586 struct radv_device
*device
= pipeline
->device
;
1587 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1588 unsigned wave_size
= 64;
1589 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1590 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1591 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1593 unsigned gs_vertex_reuse
=
1594 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1595 unsigned alignment
= 256 * num_se
;
1596 /* The maximum size is 63.999 MB per SE. */
1597 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1598 struct radv_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1600 /* Calculate the minimum size. */
1601 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1602 wave_size
, alignment
);
1603 /* These are recommended sizes, not minimum sizes. */
1604 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1605 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1606 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1607 gs_info
->gs
.max_gsvs_emit_size
;
1609 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1610 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1611 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1613 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1614 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1616 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1619 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1622 /* If tessellation is all offchip and on-chip GS isn't used, this
1623 * workaround is not needed.
1627 /* SPI barrier management bug:
1628 * Make sure we have at least 4k of LDS in use to avoid the bug.
1629 * It applies to workgroup sizes of more than one wavefront.
1631 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1632 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1633 *lds_size
= MAX2(*lds_size
, 8);
1636 struct radv_shader_variant
*
1637 radv_get_shader(struct radv_pipeline
*pipeline
,
1638 gl_shader_stage stage
)
1640 if (stage
== MESA_SHADER_VERTEX
) {
1641 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1642 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1643 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1644 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1645 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1646 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1647 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1648 if (!radv_pipeline_has_tess(pipeline
))
1650 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1651 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1652 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1653 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1655 return pipeline
->shaders
[stage
];
1658 static struct radv_tessellation_state
1659 calculate_tess_state(struct radv_pipeline
*pipeline
,
1660 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1662 unsigned num_tcs_input_cp
;
1663 unsigned num_tcs_output_cp
;
1665 unsigned num_patches
;
1666 struct radv_tessellation_state tess
= {0};
1668 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1669 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1670 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1672 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1674 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1675 assert(lds_size
<= 65536);
1676 lds_size
= align(lds_size
, 512) / 512;
1678 assert(lds_size
<= 32768);
1679 lds_size
= align(lds_size
, 256) / 256;
1681 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1683 tess
.lds_size
= lds_size
;
1685 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1686 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1687 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1688 tess
.num_patches
= num_patches
;
1690 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1691 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1693 switch (tes
->info
.tes
.primitive_mode
) {
1695 type
= V_028B6C_TESS_TRIANGLE
;
1698 type
= V_028B6C_TESS_QUAD
;
1701 type
= V_028B6C_TESS_ISOLINE
;
1705 switch (tes
->info
.tes
.spacing
) {
1706 case TESS_SPACING_EQUAL
:
1707 partitioning
= V_028B6C_PART_INTEGER
;
1709 case TESS_SPACING_FRACTIONAL_ODD
:
1710 partitioning
= V_028B6C_PART_FRAC_ODD
;
1712 case TESS_SPACING_FRACTIONAL_EVEN
:
1713 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1719 bool ccw
= tes
->info
.tes
.ccw
;
1720 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
1721 vk_find_struct_const(pCreateInfo
->pTessellationState
,
1722 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
1724 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
1727 if (tes
->info
.tes
.point_mode
)
1728 topology
= V_028B6C_OUTPUT_POINT
;
1729 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
1730 topology
= V_028B6C_OUTPUT_LINE
;
1732 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
1734 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
1736 if (pipeline
->device
->has_distributed_tess
) {
1737 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
1738 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
1739 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
1741 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
1743 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
1745 tess
.tf_param
= S_028B6C_TYPE(type
) |
1746 S_028B6C_PARTITIONING(partitioning
) |
1747 S_028B6C_TOPOLOGY(topology
) |
1748 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
1753 static const struct radv_prim_vertex_count prim_size_table
[] = {
1754 [V_008958_DI_PT_NONE
] = {0, 0},
1755 [V_008958_DI_PT_POINTLIST
] = {1, 1},
1756 [V_008958_DI_PT_LINELIST
] = {2, 2},
1757 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
1758 [V_008958_DI_PT_TRILIST
] = {3, 3},
1759 [V_008958_DI_PT_TRIFAN
] = {3, 1},
1760 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
1761 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
1762 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
1763 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
1764 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
1765 [V_008958_DI_PT_RECTLIST
] = {3, 3},
1766 [V_008958_DI_PT_LINELOOP
] = {2, 1},
1767 [V_008958_DI_PT_POLYGON
] = {3, 1},
1768 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
1771 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
1773 if (radv_pipeline_has_gs(pipeline
))
1774 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
1775 else if (radv_pipeline_has_tess(pipeline
))
1776 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
1778 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
1782 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
1784 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
1785 int shader_count
= 0;
1787 if(shaders
[MESA_SHADER_FRAGMENT
]) {
1788 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
1790 if(shaders
[MESA_SHADER_GEOMETRY
]) {
1791 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
1793 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
1794 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
1796 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
1797 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
1799 if(shaders
[MESA_SHADER_VERTEX
]) {
1800 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
1803 if (shader_count
> 1) {
1804 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
1805 unsigned last
= ordered_shaders
[0]->info
.stage
;
1807 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
1808 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
1809 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
1811 for (int i
= 0; i
< shader_count
; ++i
) {
1812 nir_variable_mode mask
= 0;
1814 if (ordered_shaders
[i
]->info
.stage
!= first
)
1815 mask
= mask
| nir_var_shader_in
;
1817 if (ordered_shaders
[i
]->info
.stage
!= last
)
1818 mask
= mask
| nir_var_shader_out
;
1820 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
1821 radv_optimize_nir(ordered_shaders
[i
], false, false);
1825 for (int i
= 1; i
< shader_count
; ++i
) {
1826 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
1827 ordered_shaders
[i
- 1]);
1829 if (nir_link_opt_varyings(ordered_shaders
[i
],
1830 ordered_shaders
[i
- 1]))
1831 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
1833 nir_remove_dead_variables(ordered_shaders
[i
],
1834 nir_var_shader_out
);
1835 nir_remove_dead_variables(ordered_shaders
[i
- 1],
1838 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
1839 ordered_shaders
[i
- 1]);
1841 nir_compact_varyings(ordered_shaders
[i
],
1842 ordered_shaders
[i
- 1], true);
1845 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
1846 ac_lower_indirect_derefs(ordered_shaders
[i
],
1847 pipeline
->device
->physical_device
->rad_info
.chip_class
);
1849 radv_optimize_nir(ordered_shaders
[i
], false, false);
1851 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
1852 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
1853 pipeline
->device
->physical_device
->rad_info
.chip_class
);
1855 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
1861 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
1862 uint32_t attrib_binding
)
1864 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
1865 const VkVertexInputBindingDescription
*input_binding
=
1866 &input_state
->pVertexBindingDescriptions
[i
];
1868 if (input_binding
->binding
== attrib_binding
)
1869 return input_binding
->stride
;
1875 static struct radv_pipeline_key
1876 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
1877 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1878 const struct radv_blend_state
*blend
,
1879 bool has_view_index
)
1881 const VkPipelineVertexInputStateCreateInfo
*input_state
=
1882 pCreateInfo
->pVertexInputState
;
1883 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
1884 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1886 struct radv_pipeline_key key
;
1887 memset(&key
, 0, sizeof(key
));
1889 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
1890 key
.optimisations_disabled
= 1;
1892 key
.has_multiview_view_index
= has_view_index
;
1894 uint32_t binding_input_rate
= 0;
1895 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
1896 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
1897 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
1898 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
1899 binding_input_rate
|= 1u << binding
;
1900 instance_rate_divisors
[binding
] = 1;
1903 if (divisor_state
) {
1904 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
1905 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
1906 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
1910 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
1911 const VkVertexInputAttributeDescription
*desc
=
1912 &input_state
->pVertexAttributeDescriptions
[i
];
1913 const struct vk_format_description
*format_desc
;
1914 unsigned location
= desc
->location
;
1915 unsigned binding
= desc
->binding
;
1916 unsigned num_format
, data_format
;
1919 if (binding_input_rate
& (1u << binding
)) {
1920 key
.instance_rate_inputs
|= 1u << location
;
1921 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
1924 format_desc
= vk_format_description(desc
->format
);
1925 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
1927 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
1928 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
1930 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
1931 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
1932 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
1933 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
1935 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
1936 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
1937 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
1940 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
1941 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
1942 adjust
= RADV_ALPHA_ADJUST_SNORM
;
1944 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
1945 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
1946 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
1948 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
1949 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
1950 adjust
= RADV_ALPHA_ADJUST_SINT
;
1956 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
1959 switch (desc
->format
) {
1960 case VK_FORMAT_B8G8R8A8_UNORM
:
1961 case VK_FORMAT_B8G8R8A8_SNORM
:
1962 case VK_FORMAT_B8G8R8A8_USCALED
:
1963 case VK_FORMAT_B8G8R8A8_SSCALED
:
1964 case VK_FORMAT_B8G8R8A8_UINT
:
1965 case VK_FORMAT_B8G8R8A8_SINT
:
1966 case VK_FORMAT_B8G8R8A8_SRGB
:
1967 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
1968 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
1969 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
1970 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
1971 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
1972 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
1973 key
.vertex_post_shuffle
|= 1 << location
;
1980 if (pCreateInfo
->pTessellationState
)
1981 key
.tess_input_vertices
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1984 if (pCreateInfo
->pMultisampleState
&&
1985 pCreateInfo
->pMultisampleState
->rasterizationSamples
> 1) {
1986 uint32_t num_samples
= pCreateInfo
->pMultisampleState
->rasterizationSamples
;
1987 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
->pMultisampleState
);
1988 key
.num_samples
= num_samples
;
1989 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1992 key
.col_format
= blend
->spi_shader_col_format
;
1993 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
1994 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2000 radv_fill_shader_keys(struct radv_shader_variant_key
*keys
,
2001 const struct radv_pipeline_key
*key
,
2004 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2005 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2006 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2007 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2008 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2009 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2010 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2011 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2012 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2015 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2016 keys
[MESA_SHADER_VERTEX
].vs
.as_ls
= true;
2017 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2018 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2019 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2021 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2024 if (nir
[MESA_SHADER_GEOMETRY
]) {
2025 if (nir
[MESA_SHADER_TESS_CTRL
])
2026 keys
[MESA_SHADER_TESS_EVAL
].tes
.as_es
= true;
2028 keys
[MESA_SHADER_VERTEX
].vs
.as_es
= true;
2031 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2032 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2034 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2035 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2036 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2037 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2038 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2042 merge_tess_info(struct shader_info
*tes_info
,
2043 const struct shader_info
*tcs_info
)
2045 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2047 * "PointMode. Controls generation of points rather than triangles
2048 * or lines. This functionality defaults to disabled, and is
2049 * enabled if either shader stage includes the execution mode.
2051 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2052 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2053 * and OutputVertices, it says:
2055 * "One mode must be set in at least one of the tessellation
2058 * So, the fields can be set in either the TCS or TES, but they must
2059 * agree if set in both. Our backend looks at TES, so bitwise-or in
2060 * the values from the TCS.
2062 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2063 tes_info
->tess
.tcs_vertices_out
== 0 ||
2064 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2065 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2067 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2068 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2069 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2070 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2072 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2073 tes_info
->tess
.primitive_mode
== 0 ||
2074 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2075 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2076 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2077 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2081 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2086 if (ext
->pPipelineCreationFeedback
) {
2087 ext
->pPipelineCreationFeedback
->flags
= 0;
2088 ext
->pPipelineCreationFeedback
->duration
= 0;
2091 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2092 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2093 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2098 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2103 feedback
->duration
-= radv_get_current_time();
2104 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2108 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2113 feedback
->duration
+= radv_get_current_time();
2114 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2115 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2119 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2120 struct radv_device
*device
,
2121 struct radv_pipeline_cache
*cache
,
2122 const struct radv_pipeline_key
*key
,
2123 const VkPipelineShaderStageCreateInfo
**pStages
,
2124 const VkPipelineCreateFlags flags
,
2125 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2126 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2128 struct radv_shader_module fs_m
= {0};
2129 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2130 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2131 void *codes
[MESA_SHADER_STAGES
] = {0};
2132 unsigned code_sizes
[MESA_SHADER_STAGES
] = {0};
2133 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{0}}}};
2134 unsigned char hash
[20], gs_copy_hash
[20];
2136 radv_start_feedback(pipeline_feedback
);
2138 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2140 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2141 if (modules
[i
]->nir
)
2142 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2143 strlen(modules
[i
]->nir
->info
.name
),
2146 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2150 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2151 memcpy(gs_copy_hash
, hash
, 20);
2152 gs_copy_hash
[0] ^= 1;
2154 bool found_in_application_cache
= true;
2155 if (modules
[MESA_SHADER_GEOMETRY
]) {
2156 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2157 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2158 &found_in_application_cache
);
2159 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2162 if (radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2163 &found_in_application_cache
) &&
2164 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2165 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2169 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2171 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2172 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2173 fs_m
.nir
= fs_b
.shader
;
2174 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2177 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2178 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2183 radv_start_feedback(stage_feedbacks
[i
]);
2185 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2186 stage
? stage
->pName
: "main", i
,
2187 stage
? stage
->pSpecializationInfo
: NULL
,
2188 flags
, pipeline
->layout
);
2190 /* We don't want to alter meta shaders IR directly so clone it
2193 if (nir
[i
]->info
.name
) {
2194 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2197 radv_stop_feedback(stage_feedbacks
[i
], false);
2200 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2201 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2202 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2205 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2206 radv_link_shaders(pipeline
, nir
);
2208 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2210 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2211 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2212 nir_lower_non_uniform_ubo_access
|
2213 nir_lower_non_uniform_ssbo_access
|
2214 nir_lower_non_uniform_texture_access
|
2215 nir_lower_non_uniform_image_access
);
2218 if (radv_can_dump_shader(device
, modules
[i
], false))
2219 nir_print_shader(nir
[i
], stderr
);
2222 radv_fill_shader_keys(keys
, key
, nir
);
2224 if (nir
[MESA_SHADER_FRAGMENT
]) {
2225 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2226 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2228 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2229 radv_shader_variant_create(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2230 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2231 &codes
[MESA_SHADER_FRAGMENT
], &code_sizes
[MESA_SHADER_FRAGMENT
]);
2233 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2236 /* TODO: These are no longer used as keys we should refactor this */
2237 keys
[MESA_SHADER_VERTEX
].vs
.export_prim_id
=
2238 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
;
2239 keys
[MESA_SHADER_VERTEX
].vs
.export_layer_id
=
2240 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.layer_input
;
2241 keys
[MESA_SHADER_TESS_EVAL
].tes
.export_prim_id
=
2242 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
;
2243 keys
[MESA_SHADER_TESS_EVAL
].tes
.export_layer_id
=
2244 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.layer_input
;
2247 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2248 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2249 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2250 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2251 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2253 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2255 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_create(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2257 &key
, &codes
[MESA_SHADER_TESS_CTRL
],
2258 &code_sizes
[MESA_SHADER_TESS_CTRL
]);
2260 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2262 modules
[MESA_SHADER_VERTEX
] = NULL
;
2263 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2264 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.tcs
.outputs_written
);
2267 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2268 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2269 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2270 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2272 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2274 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_create(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2276 &keys
[pre_stage
] , &codes
[MESA_SHADER_GEOMETRY
],
2277 &code_sizes
[MESA_SHADER_GEOMETRY
]);
2279 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2281 modules
[pre_stage
] = NULL
;
2284 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2285 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2286 if (i
== MESA_SHADER_TESS_CTRL
) {
2287 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.ls_outputs_written
);
2289 if (i
== MESA_SHADER_TESS_EVAL
) {
2290 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2291 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.tcs
.outputs_written
);
2294 radv_start_feedback(stage_feedbacks
[i
]);
2296 pipeline
->shaders
[i
] = radv_shader_variant_create(device
, modules
[i
], &nir
[i
], 1,
2298 keys
+ i
, &codes
[i
],
2301 radv_stop_feedback(stage_feedbacks
[i
], false);
2305 if(modules
[MESA_SHADER_GEOMETRY
]) {
2306 void *gs_copy_code
= NULL
;
2307 unsigned gs_copy_code_size
= 0;
2308 if (!pipeline
->gs_copy_shader
) {
2309 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2310 device
, nir
[MESA_SHADER_GEOMETRY
], &gs_copy_code
,
2312 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2315 if (pipeline
->gs_copy_shader
) {
2316 void *code
[MESA_SHADER_STAGES
] = {0};
2317 unsigned code_size
[MESA_SHADER_STAGES
] = {0};
2318 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2320 code
[MESA_SHADER_GEOMETRY
] = gs_copy_code
;
2321 code_size
[MESA_SHADER_GEOMETRY
] = gs_copy_code_size
;
2322 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2324 radv_pipeline_cache_insert_shaders(device
, cache
,
2333 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2334 (const void**)codes
, code_sizes
);
2336 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2339 if (!pipeline
->device
->keep_shader_info
)
2340 ralloc_free(nir
[i
]);
2342 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2343 radv_shader_dump_stats(device
,
2344 pipeline
->shaders
[i
],
2350 ralloc_free(fs_m
.nir
);
2352 radv_stop_feedback(pipeline_feedback
, false);
2356 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2357 gl_shader_stage stage
, enum chip_class chip_class
)
2359 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2360 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2362 case MESA_SHADER_FRAGMENT
:
2363 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2364 case MESA_SHADER_VERTEX
:
2365 if (chip_class
>= GFX9
) {
2366 return has_tess
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2367 has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2368 R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2371 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
2373 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
: R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2374 case MESA_SHADER_GEOMETRY
:
2375 return chip_class
>= GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2376 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2377 case MESA_SHADER_COMPUTE
:
2378 return R_00B900_COMPUTE_USER_DATA_0
;
2379 case MESA_SHADER_TESS_CTRL
:
2380 return chip_class
>= GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2381 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2382 case MESA_SHADER_TESS_EVAL
:
2383 if (chip_class
>= GFX9
) {
2384 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2385 R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2388 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2390 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2392 unreachable("unknown shader");
2396 struct radv_bin_size_entry
{
2402 radv_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2404 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
2408 /* One shader engine */
2414 { UINT_MAX
, { 0, 0}},
2417 /* Two shader engines */
2423 { UINT_MAX
, { 0, 0}},
2426 /* Four shader engines */
2431 { UINT_MAX
, { 0, 0}},
2437 /* One shader engine */
2443 { UINT_MAX
, { 0, 0}},
2446 /* Two shader engines */
2452 { UINT_MAX
, { 0, 0}},
2455 /* Four shader engines */
2462 { UINT_MAX
, { 0, 0}},
2468 /* One shader engine */
2475 { UINT_MAX
, { 0, 0}},
2478 /* Two shader engines */
2486 { UINT_MAX
, { 0, 0}},
2489 /* Four shader engines */
2497 { UINT_MAX
, { 0, 0}},
2501 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
2505 // One shader engine
2512 { UINT_MAX
, { 0, 0}},
2515 // Two shader engines
2523 { UINT_MAX
, { 0, 0}},
2526 // Four shader engines
2534 { UINT_MAX
, { 0, 0}},
2540 // One shader engine
2548 { UINT_MAX
, { 0, 0}},
2551 // Two shader engines
2560 { UINT_MAX
, { 0, 0}},
2563 // Four shader engines
2572 { UINT_MAX
, { 0, 0}},
2578 // One shader engine
2586 { UINT_MAX
, { 0, 0}},
2589 // Two shader engines
2598 { UINT_MAX
, { 0, 0}},
2601 // Four shader engines
2609 { UINT_MAX
, { 0, 0}},
2614 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2615 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2616 VkExtent2D extent
= {512, 512};
2618 unsigned log_num_rb_per_se
=
2619 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
2620 pipeline
->device
->physical_device
->rad_info
.max_se
);
2621 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
2623 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
2624 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
2625 unsigned effective_samples
= total_samples
;
2626 unsigned color_bytes_per_pixel
= 0;
2628 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
2630 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2631 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
2634 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
2637 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
2638 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
2641 /* MSAA images typically don't use all samples all the time. */
2642 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
2643 effective_samples
= 2;
2644 color_bytes_per_pixel
*= effective_samples
;
2647 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
2648 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
2651 extent
= color_entry
->extent
;
2653 if (subpass
->depth_stencil_attachment
) {
2654 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
2656 /* Coefficients taken from AMDVLK */
2657 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
2658 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
2659 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
2661 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
2662 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
2665 extent
.width
= MIN2(extent
.width
, ds_entry
->extent
.width
);
2666 extent
.height
= MIN2(extent
.height
, ds_entry
->extent
.height
);
2673 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
2674 struct radv_pipeline
*pipeline
,
2675 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2677 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
2680 uint32_t pa_sc_binner_cntl_0
=
2681 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
2682 S_028C44_DISABLE_START_OF_PRIM(1);
2683 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
2685 VkExtent2D bin_size
= radv_compute_bin_size(pipeline
, pCreateInfo
);
2687 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
2688 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
2689 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
2691 switch (pipeline
->device
->physical_device
->rad_info
.family
) {
2695 context_states_per_bin
= 1;
2696 persistent_states_per_bin
= 1;
2697 fpovs_per_batch
= 63;
2701 context_states_per_bin
= 6;
2702 persistent_states_per_bin
= 32;
2703 fpovs_per_batch
= 63;
2706 unreachable("unhandled family while determining binning state.");
2709 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
2710 pa_sc_binner_cntl_0
=
2711 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
2712 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
2713 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
2714 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
2715 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
2716 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
- 1) |
2717 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
- 1) |
2718 S_028C44_DISABLE_START_OF_PRIM(1) |
2719 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
2720 S_028C44_OPTIMAL_BIN_SELECTION(1);
2723 radeon_set_context_reg(ctx_cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
2724 pa_sc_binner_cntl_0
);
2725 radeon_set_context_reg(ctx_cs
, R_028060_DB_DFSM_CONTROL
,
2731 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
2732 struct radv_pipeline
*pipeline
,
2733 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2734 const struct radv_graphics_pipeline_create_info
*extra
)
2736 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
2737 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2738 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2739 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
2740 struct radv_render_pass_attachment
*attachment
= NULL
;
2741 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
2742 uint32_t db_render_control
= 0, db_render_override2
= 0;
2743 uint32_t db_render_override
= 0;
2745 if (subpass
->depth_stencil_attachment
)
2746 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
2748 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
2749 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
2751 if (vkds
&& has_depth_attachment
) {
2752 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
2753 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
2754 S_028800_ZFUNC(vkds
->depthCompareOp
) |
2755 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
2757 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2758 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
2761 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
2762 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2763 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
2764 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
2765 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
2766 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
2768 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
2769 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
2770 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
2771 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
2774 if (attachment
&& extra
) {
2775 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
2776 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
2778 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
2779 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
2780 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
2781 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
2782 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
2785 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
2786 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
2788 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
2789 ps
->info
.info
.ps
.writes_z
) {
2790 /* From VK_EXT_depth_range_unrestricted spec:
2792 * "The behavior described in Primitive Clipping still applies.
2793 * If depth clamping is disabled the depth values are still
2794 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2795 * depth clamping is enabled the above equation is ignored and
2796 * the depth values are instead clamped to the VkViewport
2797 * minDepth and maxDepth values, which in the case of this
2798 * extension can be outside of the 0.0 to 1.0 range."
2800 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2803 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
2804 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
2806 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
2807 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
2808 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
2812 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
2813 struct radv_pipeline
*pipeline
,
2814 const struct radv_blend_state
*blend
)
2816 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
2817 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
2819 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
2820 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
2822 if (pipeline
->device
->physical_device
->has_rbplus
) {
2824 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
2825 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
2828 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
2830 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
2831 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
2833 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
2834 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
2837 static const VkConservativeRasterizationModeEXT
2838 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
2840 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
2841 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
2843 if (!conservative_raster
)
2844 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
2845 return conservative_raster
->conservativeRasterizationMode
;
2849 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
2850 struct radv_pipeline
*pipeline
,
2851 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2853 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
2854 const VkConservativeRasterizationModeEXT mode
=
2855 radv_get_conservative_raster_mode(vkraster
);
2856 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
2857 bool depth_clip_disable
= vkraster
->depthClampEnable
;
2859 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
2860 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
2861 if (depth_clip_state
) {
2862 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
2865 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
2866 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2867 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
2868 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
2869 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
2870 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2872 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
2873 S_0286D4_FLAT_SHADE_ENA(1) |
2874 S_0286D4_PNT_SPRITE_ENA(1) |
2875 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
2876 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
2877 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
2878 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
2879 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2881 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
2882 S_028BE4_PIX_CENTER(1) | // TODO verify
2883 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
2884 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
2886 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
2887 S_028814_FACE(vkraster
->frontFace
) |
2888 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
2889 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
2890 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
2891 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
2892 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
2893 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
2894 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
2895 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
2897 /* Conservative rasterization. */
2898 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
2899 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
2901 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
2902 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
2903 S_028804_OVERRASTERIZATION_AMOUNT(4);
2905 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
2906 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
2907 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
2909 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
2910 pa_sc_conservative_rast
|=
2911 S_028C4C_OVER_RAST_ENABLE(1) |
2912 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
2913 S_028C4C_UNDER_RAST_ENABLE(0) |
2914 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
2915 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
2917 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
2918 pa_sc_conservative_rast
|=
2919 S_028C4C_OVER_RAST_ENABLE(0) |
2920 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
2921 S_028C4C_UNDER_RAST_ENABLE(1) |
2922 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
2923 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
2927 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
2928 pa_sc_conservative_rast
);
2933 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
2934 struct radv_pipeline
*pipeline
)
2936 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
2938 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2939 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
2940 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
2942 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
2943 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
2945 /* The exclusion bits can be set to improve rasterization efficiency
2946 * if no sample lies on the pixel boundary (-8 sample offset). It's
2947 * currently always TRUE because the driver doesn't support 16 samples.
2949 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
2950 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
2951 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
2952 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
2956 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
2957 struct radv_pipeline
*pipeline
)
2959 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
2961 uint32_t vgt_primitiveid_en
= false;
2962 uint32_t vgt_gs_mode
= 0;
2964 if (radv_pipeline_has_gs(pipeline
)) {
2965 const struct radv_shader_variant
*gs
=
2966 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2968 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
2969 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2970 } else if (outinfo
->export_prim_id
) {
2971 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
2972 vgt_primitiveid_en
= true;
2975 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
2976 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
2980 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
2981 struct radeon_cmdbuf
*cs
,
2982 struct radv_pipeline
*pipeline
,
2983 struct radv_shader_variant
*shader
)
2985 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2987 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
2988 radeon_emit(cs
, va
>> 8);
2989 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
2990 radeon_emit(cs
, shader
->rsrc1
);
2991 radeon_emit(cs
, shader
->rsrc2
);
2993 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
2994 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
2995 clip_dist_mask
= outinfo
->clip_dist_mask
;
2996 cull_dist_mask
= outinfo
->cull_dist_mask
;
2997 total_mask
= clip_dist_mask
| cull_dist_mask
;
2998 bool misc_vec_ena
= outinfo
->writes_pointsize
||
2999 outinfo
->writes_layer
||
3000 outinfo
->writes_viewport_index
;
3002 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3003 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo
->param_exports
) - 1));
3005 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3006 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3007 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3008 V_02870C_SPI_SHADER_4COMP
:
3009 V_02870C_SPI_SHADER_NONE
) |
3010 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3011 V_02870C_SPI_SHADER_4COMP
:
3012 V_02870C_SPI_SHADER_NONE
) |
3013 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3014 V_02870C_SPI_SHADER_4COMP
:
3015 V_02870C_SPI_SHADER_NONE
));
3017 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3018 S_028818_VTX_W0_FMT(1) |
3019 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3020 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3021 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3023 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3024 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3025 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3026 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3027 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3028 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3029 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3030 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3031 cull_dist_mask
<< 8 |
3034 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3035 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3036 outinfo
->writes_viewport_index
);
3040 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3041 struct radv_pipeline
*pipeline
,
3042 struct radv_shader_variant
*shader
)
3044 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3046 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3047 radeon_emit(cs
, va
>> 8);
3048 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3049 radeon_emit(cs
, shader
->rsrc1
);
3050 radeon_emit(cs
, shader
->rsrc2
);
3054 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3055 struct radv_pipeline
*pipeline
,
3056 struct radv_shader_variant
*shader
,
3057 const struct radv_tessellation_state
*tess
)
3059 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3060 uint32_t rsrc2
= shader
->rsrc2
;
3062 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3063 radeon_emit(cs
, va
>> 8);
3064 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3066 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3067 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3068 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3069 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3071 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3072 radeon_emit(cs
, shader
->rsrc1
);
3073 radeon_emit(cs
, rsrc2
);
3077 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
3078 struct radv_pipeline
*pipeline
,
3079 struct radv_shader_variant
*shader
,
3080 const struct radv_tessellation_state
*tess
)
3082 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3084 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3085 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
3086 radeon_emit(cs
, va
>> 8);
3087 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
3089 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
3090 radeon_emit(cs
, shader
->rsrc1
);
3091 radeon_emit(cs
, shader
->rsrc2
|
3092 S_00B42C_LDS_SIZE(tess
->lds_size
));
3094 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
3095 radeon_emit(cs
, va
>> 8);
3096 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
3097 radeon_emit(cs
, shader
->rsrc1
);
3098 radeon_emit(cs
, shader
->rsrc2
);
3103 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
3104 struct radeon_cmdbuf
*cs
,
3105 struct radv_pipeline
*pipeline
,
3106 const struct radv_tessellation_state
*tess
)
3108 struct radv_shader_variant
*vs
;
3110 /* Skip shaders merged into HS/GS */
3111 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
3115 if (vs
->info
.vs
.as_ls
)
3116 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
3117 else if (vs
->info
.vs
.as_es
)
3118 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
3120 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
3124 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
3125 struct radeon_cmdbuf
*cs
,
3126 struct radv_pipeline
*pipeline
,
3127 const struct radv_tessellation_state
*tess
)
3129 if (!radv_pipeline_has_tess(pipeline
))
3132 struct radv_shader_variant
*tes
, *tcs
;
3134 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
3135 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
3138 if (tes
->info
.tes
.as_es
)
3139 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
3141 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
3144 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
3146 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
3149 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
3150 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
3151 tess
->ls_hs_config
);
3153 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
3154 tess
->ls_hs_config
);
3158 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
3159 struct radeon_cmdbuf
*cs
,
3160 struct radv_pipeline
*pipeline
,
3161 const struct radv_gs_state
*gs_state
)
3163 struct radv_shader_variant
*gs
;
3164 unsigned gs_max_out_vertices
;
3165 uint8_t *num_components
;
3170 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3174 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
3175 max_stream
= gs
->info
.info
.gs
.max_stream
;
3176 num_components
= gs
->info
.info
.gs
.num_stream_output_components
;
3178 offset
= num_components
[0] * gs_max_out_vertices
;
3180 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
3181 radeon_emit(ctx_cs
, offset
);
3182 if (max_stream
>= 1)
3183 offset
+= num_components
[1] * gs_max_out_vertices
;
3184 radeon_emit(ctx_cs
, offset
);
3185 if (max_stream
>= 2)
3186 offset
+= num_components
[2] * gs_max_out_vertices
;
3187 radeon_emit(ctx_cs
, offset
);
3188 if (max_stream
>= 3)
3189 offset
+= num_components
[3] * gs_max_out_vertices
;
3190 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
3192 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
3194 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
3195 radeon_emit(ctx_cs
, num_components
[0]);
3196 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
3197 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
3198 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
3200 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
3201 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
3202 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
3203 S_028B90_ENABLE(gs_num_invocations
> 0));
3205 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3206 gs_state
->vgt_esgs_ring_itemsize
);
3208 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
3210 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3211 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
3212 radeon_emit(cs
, va
>> 8);
3213 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
3215 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3216 radeon_emit(cs
, gs
->rsrc1
);
3217 radeon_emit(cs
, gs
->rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
3219 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
3220 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
3222 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
3223 radeon_emit(cs
, va
>> 8);
3224 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
3225 radeon_emit(cs
, gs
->rsrc1
);
3226 radeon_emit(cs
, gs
->rsrc2
);
3229 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
3232 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
, bool float16
)
3234 uint32_t ps_input_cntl
;
3235 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3236 ps_input_cntl
= S_028644_OFFSET(offset
);
3238 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3240 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
3241 S_028644_ATTR0_VALID(1);
3244 /* The input is a DEFAULT_VAL constant. */
3245 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3246 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3247 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3248 ps_input_cntl
= S_028644_OFFSET(0x20) |
3249 S_028644_DEFAULT_VAL(offset
);
3251 return ps_input_cntl
;
3255 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
3256 struct radv_pipeline
*pipeline
)
3258 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3259 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3260 uint32_t ps_input_cntl
[32];
3262 unsigned ps_offset
= 0;
3264 if (ps
->info
.info
.ps
.prim_id_input
) {
3265 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
3266 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
3267 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
3272 if (ps
->info
.info
.ps
.layer_input
||
3273 ps
->info
.info
.ps
.uses_input_attachments
||
3274 ps
->info
.info
.needs_multiview_view_index
) {
3275 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
3276 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
3277 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
3279 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false);
3283 if (ps
->info
.info
.ps
.has_pcoord
) {
3285 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3286 ps_input_cntl
[ps_offset
] = val
;
3290 if (ps
->info
.info
.ps
.num_input_clips_culls
) {
3293 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
3294 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
3295 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
3299 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
3300 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
3301 ps
->info
.info
.ps
.num_input_clips_culls
> 4) {
3302 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
3307 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.fs
.input_mask
; ++i
) {
3311 if (!(ps
->info
.fs
.input_mask
& (1u << i
)))
3314 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
3315 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
3316 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
3321 flat_shade
= !!(ps
->info
.fs
.flat_shaded_mask
& (1u << ps_offset
));
3322 float16
= !!(ps
->info
.fs
.float16_shaded_mask
& (1u << ps_offset
));
3324 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, float16
);
3329 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
3330 for (unsigned i
= 0; i
< ps_offset
; i
++) {
3331 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
3337 radv_compute_db_shader_control(const struct radv_device
*device
,
3338 const struct radv_pipeline
*pipeline
,
3339 const struct radv_shader_variant
*ps
)
3342 if (ps
->info
.fs
.early_fragment_test
|| !ps
->info
.info
.ps
.writes_memory
)
3343 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
3345 z_order
= V_02880C_LATE_Z
;
3347 bool disable_rbplus
= device
->physical_device
->has_rbplus
&&
3348 !device
->physical_device
->rbplus_allowed
;
3350 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
3351 * but this appears to break Project Cars (DXVK). See
3352 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
3354 bool mask_export_enable
= ps
->info
.info
.ps
.writes_sample_mask
;
3356 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.info
.ps
.writes_z
) |
3357 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.info
.ps
.writes_stencil
) |
3358 S_02880C_KILL_ENABLE(!!ps
->info
.fs
.can_discard
) |
3359 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
3360 S_02880C_Z_ORDER(z_order
) |
3361 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.fs
.early_fragment_test
) |
3362 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.info
.ps
.writes_memory
) |
3363 S_02880C_EXEC_ON_NOOP(ps
->info
.info
.ps
.writes_memory
) |
3364 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
3368 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
3369 struct radeon_cmdbuf
*cs
,
3370 struct radv_pipeline
*pipeline
)
3372 struct radv_shader_variant
*ps
;
3374 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
3376 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3377 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
3379 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
3380 radeon_emit(cs
, va
>> 8);
3381 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
3382 radeon_emit(cs
, ps
->rsrc1
);
3383 radeon_emit(cs
, ps
->rsrc2
);
3385 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
3386 radv_compute_db_shader_control(pipeline
->device
,
3389 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
3390 ps
->config
.spi_ps_input_ena
);
3392 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
3393 ps
->config
.spi_ps_input_addr
);
3395 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
3396 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
3398 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
3400 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
3401 ac_get_spi_shader_z_format(ps
->info
.info
.ps
.writes_z
,
3402 ps
->info
.info
.ps
.writes_stencil
,
3403 ps
->info
.info
.ps
.writes_sample_mask
));
3405 if (pipeline
->device
->dfsm_allowed
) {
3406 /* optimise this? */
3407 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3408 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3413 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
3414 struct radv_pipeline
*pipeline
)
3416 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
3419 unsigned vtx_reuse_depth
= 30;
3420 if (radv_pipeline_has_tess(pipeline
) &&
3421 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
3422 vtx_reuse_depth
= 14;
3424 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
3425 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
3429 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
3431 uint32_t stages
= 0;
3432 if (radv_pipeline_has_tess(pipeline
)) {
3433 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3434 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3436 if (radv_pipeline_has_gs(pipeline
))
3437 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3439 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3441 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3443 } else if (radv_pipeline_has_gs(pipeline
))
3444 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3446 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3448 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
3449 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3455 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3457 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
3458 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
3460 if (!discard_rectangle_info
)
3465 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
3466 /* Interpret i as a bitmask, and then set the bit in the mask if
3467 * that combination of rectangles in which the pixel is contained
3468 * should pass the cliprect test. */
3469 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
3471 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
3475 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
3486 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
3487 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3488 const struct radv_graphics_pipeline_create_info
*extra
,
3489 const struct radv_blend_state
*blend
,
3490 const struct radv_tessellation_state
*tess
,
3491 const struct radv_gs_state
*gs
,
3492 unsigned prim
, unsigned gs_out
)
3494 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
3495 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
3498 ctx_cs
->max_dw
= 256;
3499 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
3500 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
3502 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
3503 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
3504 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
3505 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
3506 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
3507 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
3508 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
3509 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
, gs
);
3510 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
3511 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
3512 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
3513 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3515 radeon_set_context_reg(ctx_cs
, R_0286E8_SPI_TMPRING_SIZE
,
3516 S_0286E8_WAVES(pipeline
->max_waves
) |
3517 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
3519 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
3521 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3522 radeon_set_uconfig_reg_idx(cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
3524 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
3526 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
3528 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
3530 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
3532 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
3533 assert(cs
->cdw
<= cs
->max_dw
);
3536 static struct radv_ia_multi_vgt_param_helpers
3537 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
3538 const struct radv_tessellation_state
*tess
,
3541 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
3542 const struct radv_device
*device
= pipeline
->device
;
3544 if (radv_pipeline_has_tess(pipeline
))
3545 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
3546 else if (radv_pipeline_has_gs(pipeline
))
3547 ia_multi_vgt_param
.primgroup_size
= 64;
3549 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
3551 /* GS requirement. */
3552 ia_multi_vgt_param
.partial_es_wave
= false;
3553 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3554 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
3555 ia_multi_vgt_param
.partial_es_wave
= true;
3557 ia_multi_vgt_param
.wd_switch_on_eop
= false;
3558 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3559 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3560 * 4 shader engines. Set 1 to pass the assertion below.
3561 * The other cases are hardware requirements. */
3562 if (device
->physical_device
->rad_info
.max_se
< 4 ||
3563 prim
== V_008958_DI_PT_POLYGON
||
3564 prim
== V_008958_DI_PT_LINELOOP
||
3565 prim
== V_008958_DI_PT_TRIFAN
||
3566 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
3567 (pipeline
->graphics
.prim_restart_enable
&&
3568 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
3569 (prim
!= V_008958_DI_PT_POINTLIST
&&
3570 prim
!= V_008958_DI_PT_LINESTRIP
))))
3571 ia_multi_vgt_param
.wd_switch_on_eop
= true;
3574 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
3575 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
)
3576 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3577 if (radv_pipeline_has_gs(pipeline
) &&
3578 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.info
.uses_prim_id
)
3579 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3580 if (radv_pipeline_has_tess(pipeline
)) {
3581 /* SWITCH_ON_EOI must be set if PrimID is used. */
3582 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.uses_prim_id
||
3583 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.info
.uses_prim_id
)
3584 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3587 ia_multi_vgt_param
.partial_vs_wave
= false;
3588 if (radv_pipeline_has_tess(pipeline
)) {
3589 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3590 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
3591 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
3592 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
3593 radv_pipeline_has_gs(pipeline
))
3594 ia_multi_vgt_param
.partial_vs_wave
= true;
3595 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3596 if (device
->has_distributed_tess
) {
3597 if (radv_pipeline_has_gs(pipeline
)) {
3598 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3599 ia_multi_vgt_param
.partial_es_wave
= true;
3601 ia_multi_vgt_param
.partial_vs_wave
= true;
3606 /* Workaround for a VGT hang when strip primitive types are used with
3607 * primitive restart.
3609 if (pipeline
->graphics
.prim_restart_enable
&&
3610 (prim
== V_008958_DI_PT_LINESTRIP
||
3611 prim
== V_008958_DI_PT_TRISTRIP
||
3612 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
3613 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
3614 ia_multi_vgt_param
.partial_vs_wave
= true;
3617 if (radv_pipeline_has_gs(pipeline
)) {
3618 /* On these chips there is the possibility of a hang if the
3619 * pipeline uses a GS and partial_vs_wave is not set.
3621 * This mostly does not hit 4-SE chips, as those typically set
3622 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
3623 * with GS due to another workaround.
3625 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
3627 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
3628 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
3629 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
3630 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
3631 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
3632 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
3633 ia_multi_vgt_param
.partial_vs_wave
= true;
3637 ia_multi_vgt_param
.base
=
3638 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
3639 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3640 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
3641 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
3642 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
3644 return ia_multi_vgt_param
;
3649 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
3650 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3652 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
3653 pCreateInfo
->pVertexInputState
;
3654 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
3656 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
3657 const VkVertexInputAttributeDescription
*desc
=
3658 &vi_info
->pVertexAttributeDescriptions
[i
];
3659 unsigned loc
= desc
->location
;
3660 const struct vk_format_description
*format_desc
;
3662 format_desc
= vk_format_description(desc
->format
);
3664 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
3667 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
3668 const VkVertexInputBindingDescription
*desc
=
3669 &vi_info
->pVertexBindingDescriptions
[i
];
3671 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
3672 pipeline
->num_vertex_bindings
=
3673 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
3677 static struct radv_shader_variant
*
3678 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
3682 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
3683 struct radv_shader_variant
*shader
=
3684 radv_get_shader(pipeline
, i
);
3686 if (shader
&& shader
->info
.info
.so
.num_outputs
> 0)
3694 radv_pipeline_init(struct radv_pipeline
*pipeline
,
3695 struct radv_device
*device
,
3696 struct radv_pipeline_cache
*cache
,
3697 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3698 const struct radv_graphics_pipeline_create_info
*extra
)
3701 bool has_view_index
= false;
3703 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3704 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3705 if (subpass
->view_mask
)
3706 has_view_index
= true;
3708 pipeline
->device
= device
;
3709 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
3710 assert(pipeline
->layout
);
3712 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
3714 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
3715 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
3716 radv_init_feedback(creation_feedback
);
3718 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
3720 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
3721 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
3722 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
3723 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
3724 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
3725 if(creation_feedback
)
3726 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
3729 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
3730 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
3732 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
3733 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
3735 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
3737 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
3739 if (radv_pipeline_has_gs(pipeline
)) {
3740 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
3741 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
3743 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
3745 if (extra
&& extra
->use_rectlist
) {
3746 prim
= V_008958_DI_PT_RECTLIST
;
3747 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
3748 pipeline
->graphics
.can_use_guardband
= true;
3750 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
3751 /* prim vertex count will need TESS changes */
3752 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
3754 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
3756 /* Ensure that some export memory is always allocated, for two reasons:
3758 * 1) Correctness: The hardware ignores the EXEC mask if no export
3759 * memory is allocated, so KILL and alpha test do not work correctly
3761 * 2) Performance: Every shader needs at least a NULL export, even when
3762 * it writes no color/depth output. The NULL export instruction
3763 * stalls without this setting.
3765 * Don't add this to CB_SHADER_MASK.
3767 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3768 if (!blend
.spi_shader_col_format
) {
3769 if (!ps
->info
.info
.ps
.writes_z
&&
3770 !ps
->info
.info
.ps
.writes_stencil
&&
3771 !ps
->info
.info
.ps
.writes_sample_mask
)
3772 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
3775 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
3776 if (pipeline
->shaders
[i
]) {
3777 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
3781 struct radv_gs_state gs
= {0};
3782 if (radv_pipeline_has_gs(pipeline
)) {
3783 gs
= calculate_gs_info(pCreateInfo
, pipeline
);
3784 calculate_gs_ring_sizes(pipeline
, &gs
);
3787 struct radv_tessellation_state tess
= {0};
3788 if (radv_pipeline_has_tess(pipeline
)) {
3789 if (prim
== V_008958_DI_PT_PATCH
) {
3790 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
3791 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
3793 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
3796 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
3798 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
3800 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
3801 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
3803 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
3804 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
3805 if (loc
->sgpr_idx
!= -1) {
3806 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
3807 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
3808 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
)
3809 pipeline
->graphics
.vtx_emit_num
= 3;
3811 pipeline
->graphics
.vtx_emit_num
= 2;
3814 /* Find the last vertex shader stage that eventually uses streamout. */
3815 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
3817 result
= radv_pipeline_scratch_init(device
, pipeline
);
3818 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, &gs
, prim
, gs_out
);
3824 radv_graphics_pipeline_create(
3826 VkPipelineCache _cache
,
3827 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3828 const struct radv_graphics_pipeline_create_info
*extra
,
3829 const VkAllocationCallbacks
*pAllocator
,
3830 VkPipeline
*pPipeline
)
3832 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3833 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
3834 struct radv_pipeline
*pipeline
;
3837 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
3838 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3839 if (pipeline
== NULL
)
3840 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3842 result
= radv_pipeline_init(pipeline
, device
, cache
,
3843 pCreateInfo
, extra
);
3844 if (result
!= VK_SUCCESS
) {
3845 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
3849 *pPipeline
= radv_pipeline_to_handle(pipeline
);
3854 VkResult
radv_CreateGraphicsPipelines(
3856 VkPipelineCache pipelineCache
,
3858 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
3859 const VkAllocationCallbacks
* pAllocator
,
3860 VkPipeline
* pPipelines
)
3862 VkResult result
= VK_SUCCESS
;
3865 for (; i
< count
; i
++) {
3867 r
= radv_graphics_pipeline_create(_device
,
3870 NULL
, pAllocator
, &pPipelines
[i
]);
3871 if (r
!= VK_SUCCESS
) {
3873 pPipelines
[i
] = VK_NULL_HANDLE
;
3882 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
3884 struct radv_shader_variant
*compute_shader
;
3885 struct radv_device
*device
= pipeline
->device
;
3886 unsigned compute_resource_limits
;
3887 unsigned waves_per_threadgroup
;
3890 pipeline
->cs
.buf
= malloc(20 * 4);
3891 pipeline
->cs
.max_dw
= 20;
3893 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3894 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
3896 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
3897 radeon_emit(&pipeline
->cs
, va
>> 8);
3898 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
3900 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
3901 radeon_emit(&pipeline
->cs
, compute_shader
->rsrc1
);
3902 radeon_emit(&pipeline
->cs
, compute_shader
->rsrc2
);
3904 radeon_set_sh_reg(&pipeline
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3905 S_00B860_WAVES(pipeline
->max_waves
) |
3906 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
3908 /* Calculate best compute resource limits. */
3909 waves_per_threadgroup
=
3910 DIV_ROUND_UP(compute_shader
->info
.cs
.block_size
[0] *
3911 compute_shader
->info
.cs
.block_size
[1] *
3912 compute_shader
->info
.cs
.block_size
[2], 64);
3913 compute_resource_limits
=
3914 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0);
3916 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3917 unsigned num_cu_per_se
=
3918 device
->physical_device
->rad_info
.num_good_compute_units
/
3919 device
->physical_device
->rad_info
.max_se
;
3921 /* Force even distribution on all SIMDs in CU if the workgroup
3922 * size is 64. This has shown some good improvements if # of
3923 * CUs per SE is not a multiple of 4.
3925 if (num_cu_per_se
% 4 && waves_per_threadgroup
== 1)
3926 compute_resource_limits
|= S_00B854_FORCE_SIMD_DIST(1);
3929 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
3930 compute_resource_limits
);
3932 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3933 radeon_emit(&pipeline
->cs
,
3934 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
3935 radeon_emit(&pipeline
->cs
,
3936 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
3937 radeon_emit(&pipeline
->cs
,
3938 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
3940 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
3943 static VkResult
radv_compute_pipeline_create(
3945 VkPipelineCache _cache
,
3946 const VkComputePipelineCreateInfo
* pCreateInfo
,
3947 const VkAllocationCallbacks
* pAllocator
,
3948 VkPipeline
* pPipeline
)
3950 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3951 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
3952 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
3953 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
3954 struct radv_pipeline
*pipeline
;
3957 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
3958 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3959 if (pipeline
== NULL
)
3960 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3962 pipeline
->device
= device
;
3963 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
3964 assert(pipeline
->layout
);
3966 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
3967 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
3968 radv_init_feedback(creation_feedback
);
3970 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
3971 if (creation_feedback
)
3972 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
3974 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
3975 radv_create_shaders(pipeline
, device
, cache
, &(struct radv_pipeline_key
) {0}, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
3977 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
3978 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
3979 result
= radv_pipeline_scratch_init(device
, pipeline
);
3980 if (result
!= VK_SUCCESS
) {
3981 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
3985 radv_compute_generate_pm4(pipeline
);
3987 *pPipeline
= radv_pipeline_to_handle(pipeline
);
3992 VkResult
radv_CreateComputePipelines(
3994 VkPipelineCache pipelineCache
,
3996 const VkComputePipelineCreateInfo
* pCreateInfos
,
3997 const VkAllocationCallbacks
* pAllocator
,
3998 VkPipeline
* pPipelines
)
4000 VkResult result
= VK_SUCCESS
;
4003 for (; i
< count
; i
++) {
4005 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
4007 pAllocator
, &pPipelines
[i
]);
4008 if (r
!= VK_SUCCESS
) {
4010 pPipelines
[i
] = VK_NULL_HANDLE
;