2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
50 struct radv_blend_state
{
51 uint32_t blend_enable_4bit
;
52 uint32_t need_src_alpha
;
54 uint32_t cb_color_control
;
55 uint32_t cb_target_mask
;
56 uint32_t cb_target_enabled_4bit
;
57 uint32_t sx_mrt_blend_opt
[8];
58 uint32_t cb_blend_control
[8];
60 uint32_t spi_shader_col_format
;
61 uint32_t col_format_is_int8
;
62 uint32_t col_format_is_int10
;
63 uint32_t cb_shader_mask
;
64 uint32_t db_alpha_to_mask
;
66 uint32_t commutative_4bit
;
68 bool single_cb_enable
;
69 bool mrt0_is_dual_src
;
72 struct radv_dsa_order_invariance
{
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
85 struct radv_tessellation_state
{
86 uint32_t ls_hs_config
;
92 static const VkPipelineMultisampleStateCreateInfo
*
93 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
95 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
96 return pCreateInfo
->pMultisampleState
;
100 static const VkPipelineTessellationStateCreateInfo
*
101 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
103 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
104 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
105 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
106 return pCreateInfo
->pTessellationState
;
112 static const VkPipelineDepthStencilStateCreateInfo
*
113 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
115 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
116 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
118 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
119 subpass
->depth_stencil_attachment
)
120 return pCreateInfo
->pDepthStencilState
;
124 static const VkPipelineColorBlendStateCreateInfo
*
125 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
127 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
128 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
130 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
131 subpass
->has_color_att
)
132 return pCreateInfo
->pColorBlendState
;
136 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
138 struct radv_shader_variant
*variant
= NULL
;
139 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
140 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
141 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
142 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
143 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
144 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
147 return variant
->info
.is_ngg
;
150 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
152 assert(radv_pipeline_has_ngg(pipeline
));
154 struct radv_shader_variant
*variant
= NULL
;
155 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
156 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
157 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
158 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
159 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
160 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
163 return variant
->info
.is_ngg_passthrough
;
166 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
168 if (!radv_pipeline_has_gs(pipeline
))
171 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
172 * On GFX10, it might be required in rare cases if it's not possible to
175 if (radv_pipeline_has_ngg(pipeline
))
178 assert(pipeline
->gs_copy_shader
);
183 radv_pipeline_destroy(struct radv_device
*device
,
184 struct radv_pipeline
*pipeline
,
185 const VkAllocationCallbacks
* allocator
)
187 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
188 if (pipeline
->shaders
[i
])
189 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
191 if (pipeline
->gs_copy_shader
)
192 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
195 free(pipeline
->cs
.buf
);
197 vk_object_base_finish(&pipeline
->base
);
198 vk_free2(&device
->vk
.alloc
, allocator
, pipeline
);
201 void radv_DestroyPipeline(
203 VkPipeline _pipeline
,
204 const VkAllocationCallbacks
* pAllocator
)
206 RADV_FROM_HANDLE(radv_device
, device
, _device
);
207 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
212 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
215 static uint32_t get_hash_flags(struct radv_device
*device
)
217 uint32_t hash_flags
= 0;
219 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
220 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
221 if (device
->physical_device
->cs_wave_size
== 32)
222 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
223 if (device
->physical_device
->ps_wave_size
== 32)
224 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
225 if (device
->physical_device
->ge_wave_size
== 32)
226 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
227 if (device
->physical_device
->use_llvm
)
228 hash_flags
|= RADV_HASH_SHADER_LLVM
;
233 radv_pipeline_scratch_init(struct radv_device
*device
,
234 struct radv_pipeline
*pipeline
)
236 unsigned scratch_bytes_per_wave
= 0;
237 unsigned max_waves
= 0;
238 unsigned min_waves
= 1;
240 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
241 if (pipeline
->shaders
[i
] &&
242 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
243 unsigned max_stage_waves
= device
->scratch_waves
;
245 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
246 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
248 max_stage_waves
= MIN2(max_stage_waves
,
249 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
250 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
251 max_waves
= MAX2(max_waves
, max_stage_waves
);
255 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
256 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
257 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
258 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
259 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
262 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
263 pipeline
->max_waves
= max_waves
;
267 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
270 case VK_LOGIC_OP_CLEAR
:
271 return V_028808_ROP3_CLEAR
;
272 case VK_LOGIC_OP_AND
:
273 return V_028808_ROP3_AND
;
274 case VK_LOGIC_OP_AND_REVERSE
:
275 return V_028808_ROP3_AND_REVERSE
;
276 case VK_LOGIC_OP_COPY
:
277 return V_028808_ROP3_COPY
;
278 case VK_LOGIC_OP_AND_INVERTED
:
279 return V_028808_ROP3_AND_INVERTED
;
280 case VK_LOGIC_OP_NO_OP
:
281 return V_028808_ROP3_NO_OP
;
282 case VK_LOGIC_OP_XOR
:
283 return V_028808_ROP3_XOR
;
285 return V_028808_ROP3_OR
;
286 case VK_LOGIC_OP_NOR
:
287 return V_028808_ROP3_NOR
;
288 case VK_LOGIC_OP_EQUIVALENT
:
289 return V_028808_ROP3_EQUIVALENT
;
290 case VK_LOGIC_OP_INVERT
:
291 return V_028808_ROP3_INVERT
;
292 case VK_LOGIC_OP_OR_REVERSE
:
293 return V_028808_ROP3_OR_REVERSE
;
294 case VK_LOGIC_OP_COPY_INVERTED
:
295 return V_028808_ROP3_COPY_INVERTED
;
296 case VK_LOGIC_OP_OR_INVERTED
:
297 return V_028808_ROP3_OR_INVERTED
;
298 case VK_LOGIC_OP_NAND
:
299 return V_028808_ROP3_NAND
;
300 case VK_LOGIC_OP_SET
:
301 return V_028808_ROP3_SET
;
303 unreachable("Unhandled logic op");
308 static uint32_t si_translate_blend_function(VkBlendOp op
)
311 case VK_BLEND_OP_ADD
:
312 return V_028780_COMB_DST_PLUS_SRC
;
313 case VK_BLEND_OP_SUBTRACT
:
314 return V_028780_COMB_SRC_MINUS_DST
;
315 case VK_BLEND_OP_REVERSE_SUBTRACT
:
316 return V_028780_COMB_DST_MINUS_SRC
;
317 case VK_BLEND_OP_MIN
:
318 return V_028780_COMB_MIN_DST_SRC
;
319 case VK_BLEND_OP_MAX
:
320 return V_028780_COMB_MAX_DST_SRC
;
326 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
329 case VK_BLEND_FACTOR_ZERO
:
330 return V_028780_BLEND_ZERO
;
331 case VK_BLEND_FACTOR_ONE
:
332 return V_028780_BLEND_ONE
;
333 case VK_BLEND_FACTOR_SRC_COLOR
:
334 return V_028780_BLEND_SRC_COLOR
;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
336 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
337 case VK_BLEND_FACTOR_DST_COLOR
:
338 return V_028780_BLEND_DST_COLOR
;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
340 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
341 case VK_BLEND_FACTOR_SRC_ALPHA
:
342 return V_028780_BLEND_SRC_ALPHA
;
343 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
344 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
345 case VK_BLEND_FACTOR_DST_ALPHA
:
346 return V_028780_BLEND_DST_ALPHA
;
347 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
348 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
349 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
350 return V_028780_BLEND_CONSTANT_COLOR
;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
353 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
354 return V_028780_BLEND_CONSTANT_ALPHA
;
355 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
356 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
358 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
359 case VK_BLEND_FACTOR_SRC1_COLOR
:
360 return V_028780_BLEND_SRC1_COLOR
;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
362 return V_028780_BLEND_INV_SRC1_COLOR
;
363 case VK_BLEND_FACTOR_SRC1_ALPHA
:
364 return V_028780_BLEND_SRC1_ALPHA
;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
366 return V_028780_BLEND_INV_SRC1_ALPHA
;
372 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
375 case VK_BLEND_OP_ADD
:
376 return V_028760_OPT_COMB_ADD
;
377 case VK_BLEND_OP_SUBTRACT
:
378 return V_028760_OPT_COMB_SUBTRACT
;
379 case VK_BLEND_OP_REVERSE_SUBTRACT
:
380 return V_028760_OPT_COMB_REVSUBTRACT
;
381 case VK_BLEND_OP_MIN
:
382 return V_028760_OPT_COMB_MIN
;
383 case VK_BLEND_OP_MAX
:
384 return V_028760_OPT_COMB_MAX
;
386 return V_028760_OPT_COMB_BLEND_DISABLED
;
390 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
393 case VK_BLEND_FACTOR_ZERO
:
394 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
395 case VK_BLEND_FACTOR_ONE
:
396 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
397 case VK_BLEND_FACTOR_SRC_COLOR
:
398 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
399 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
400 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
401 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
402 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
403 case VK_BLEND_FACTOR_SRC_ALPHA
:
404 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
405 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
406 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
407 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
408 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
409 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
411 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
419 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
420 unsigned *dst_factor
, unsigned expected_dst
,
421 unsigned replacement_src
)
423 if (*src_factor
== expected_dst
&&
424 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
425 *src_factor
= VK_BLEND_FACTOR_ZERO
;
426 *dst_factor
= replacement_src
;
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func
== VK_BLEND_OP_SUBTRACT
)
430 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
431 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
432 *func
= VK_BLEND_OP_SUBTRACT
;
436 static bool si_blend_factor_uses_dst(unsigned factor
)
438 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
439 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
440 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
441 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
442 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
445 static bool is_dual_src(VkBlendFactor factor
)
448 case VK_BLEND_FACTOR_SRC1_COLOR
:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
450 case VK_BLEND_FACTOR_SRC1_ALPHA
:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
458 static unsigned radv_choose_spi_color_format(VkFormat vk_format
,
460 bool blend_need_alpha
)
462 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
463 struct ac_spi_color_formats formats
= {};
464 unsigned format
, ntype
, swap
;
466 format
= radv_translate_colorformat(vk_format
);
467 ntype
= radv_translate_color_numformat(vk_format
, desc
,
468 vk_format_get_first_non_void_channel(vk_format
));
469 swap
= radv_translate_colorswap(vk_format
, false);
471 ac_choose_spi_color_formats(format
, swap
, ntype
, false, &formats
);
473 if (blend_enable
&& blend_need_alpha
)
474 return formats
.blend_alpha
;
475 else if(blend_need_alpha
)
476 return formats
.alpha
;
477 else if(blend_enable
)
478 return formats
.blend
;
480 return formats
.normal
;
484 format_is_int8(VkFormat format
)
486 const struct vk_format_description
*desc
= vk_format_description(format
);
487 int channel
= vk_format_get_first_non_void_channel(format
);
489 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
490 desc
->channel
[channel
].size
== 8;
494 format_is_int10(VkFormat format
)
496 const struct vk_format_description
*desc
= vk_format_description(format
);
498 if (desc
->nr_channels
!= 4)
500 for (unsigned i
= 0; i
< 4; i
++) {
501 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
508 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
509 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
510 struct radv_blend_state
*blend
)
512 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
513 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
514 unsigned col_format
= 0, is_int8
= 0, is_int10
= 0;
515 unsigned num_targets
;
517 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
520 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
||
521 !(blend
->cb_target_mask
& (0xfu
<< (i
* 4)))) {
522 cf
= V_028714_SPI_SHADER_ZERO
;
524 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
526 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
528 cf
= radv_choose_spi_color_format(attachment
->format
,
530 blend
->need_src_alpha
& (1 << i
));
532 if (format_is_int8(attachment
->format
))
534 if (format_is_int10(attachment
->format
))
538 col_format
|= cf
<< (4 * i
);
541 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
542 /* When a subpass doesn't have any color attachments, write the
543 * alpha channel of MRT0 when alpha coverage is enabled because
544 * the depth attachment needs it.
546 col_format
|= V_028714_SPI_SHADER_32_AR
;
549 /* If the i-th target format is set, all previous target formats must
550 * be non-zero to avoid hangs.
552 num_targets
= (util_last_bit(col_format
) + 3) / 4;
553 for (unsigned i
= 0; i
< num_targets
; i
++) {
554 if (!(col_format
& (0xf << (i
* 4)))) {
555 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
559 /* The output for dual source blending should have the same format as
562 if (blend
->mrt0_is_dual_src
)
563 col_format
|= (col_format
& 0xf) << 4;
565 blend
->spi_shader_col_format
= col_format
;
566 blend
->col_format_is_int8
= is_int8
;
567 blend
->col_format_is_int10
= is_int10
;
571 * Ordered so that for each i,
572 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
574 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
575 VK_FORMAT_R32_SFLOAT
,
576 VK_FORMAT_R32G32_SFLOAT
,
577 VK_FORMAT_R8G8B8A8_UNORM
,
578 VK_FORMAT_R16G16B16A16_UNORM
,
579 VK_FORMAT_R16G16B16A16_SNORM
,
580 VK_FORMAT_R16G16B16A16_UINT
,
581 VK_FORMAT_R16G16B16A16_SINT
,
582 VK_FORMAT_R32G32B32A32_SFLOAT
,
583 VK_FORMAT_R8G8B8A8_UINT
,
584 VK_FORMAT_R8G8B8A8_SINT
,
585 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
586 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
589 unsigned radv_format_meta_fs_key(VkFormat format
)
591 unsigned col_format
= radv_choose_spi_color_format(format
, false, false);
593 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
594 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
595 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
597 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
598 bool is_int8
= format_is_int8(format
);
599 bool is_int10
= format_is_int10(format
);
601 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
605 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
606 VkBlendOp op
, VkBlendFactor src
,
607 VkBlendFactor dst
, unsigned chanmask
)
609 /* Src factor is allowed when it does not depend on Dst. */
610 static const uint32_t src_allowed
=
611 (1u << VK_BLEND_FACTOR_ONE
) |
612 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
613 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
614 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
615 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
616 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
617 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
618 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
619 (1u << VK_BLEND_FACTOR_ZERO
) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
623 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
624 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
625 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
627 if (dst
== VK_BLEND_FACTOR_ONE
&&
628 (src_allowed
& (1u << src
))) {
629 /* Addition is commutative, but floating point addition isn't
630 * associative: subtle changes can be introduced via different
631 * rounding. Be conservative, only enable for min and max.
633 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
634 blend
->commutative_4bit
|= chanmask
;
638 static struct radv_blend_state
639 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
640 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
641 const struct radv_graphics_pipeline_create_info
*extra
)
643 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
644 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
645 struct radv_blend_state blend
= {0};
646 unsigned mode
= V_028808_CB_NORMAL
;
649 if (extra
&& extra
->custom_blend_mode
) {
650 blend
.single_cb_enable
= true;
651 mode
= extra
->custom_blend_mode
;
654 blend
.cb_color_control
= 0;
656 if (vkblend
->logicOpEnable
)
657 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
659 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
662 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
663 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
664 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
665 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
666 S_028B70_OFFSET_ROUND(1);
668 if (vkms
&& vkms
->alphaToCoverageEnable
) {
669 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
670 blend
.need_src_alpha
|= 0x1;
673 blend
.cb_target_mask
= 0;
675 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
676 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
677 unsigned blend_cntl
= 0;
678 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
679 VkBlendOp eqRGB
= att
->colorBlendOp
;
680 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
681 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
682 VkBlendOp eqA
= att
->alphaBlendOp
;
683 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
684 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
686 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
688 if (!att
->colorWriteMask
)
691 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
692 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
693 if (!att
->blendEnable
) {
694 blend
.cb_blend_control
[i
] = blend_cntl
;
698 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
700 blend
.mrt0_is_dual_src
= true;
702 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
703 srcRGB
= VK_BLEND_FACTOR_ONE
;
704 dstRGB
= VK_BLEND_FACTOR_ONE
;
706 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
707 srcA
= VK_BLEND_FACTOR_ONE
;
708 dstA
= VK_BLEND_FACTOR_ONE
;
711 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
713 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
716 /* Blending optimizations for RB+.
717 * These transformations don't change the behavior.
719 * First, get rid of DST in the blend factors:
720 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
722 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
723 VK_BLEND_FACTOR_DST_COLOR
,
724 VK_BLEND_FACTOR_SRC_COLOR
);
726 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
727 VK_BLEND_FACTOR_DST_COLOR
,
728 VK_BLEND_FACTOR_SRC_COLOR
);
730 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
731 VK_BLEND_FACTOR_DST_ALPHA
,
732 VK_BLEND_FACTOR_SRC_ALPHA
);
734 /* Look up the ideal settings from tables. */
735 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
736 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
737 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
738 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
740 /* Handle interdependencies. */
741 if (si_blend_factor_uses_dst(srcRGB
))
742 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
743 if (si_blend_factor_uses_dst(srcA
))
744 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
746 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
747 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
748 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
749 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
750 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
752 /* Set the final value. */
753 blend
.sx_mrt_blend_opt
[i
] =
754 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
755 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
756 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
757 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
758 S_028760_ALPHA_DST_OPT(dstA_opt
) |
759 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
760 blend_cntl
|= S_028780_ENABLE(1);
762 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
763 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
764 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
765 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
766 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
767 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
768 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
769 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
771 blend
.cb_blend_control
[i
] = blend_cntl
;
773 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
775 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
776 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
777 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
778 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
779 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
780 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
781 blend
.need_src_alpha
|= 1 << i
;
783 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
784 blend
.cb_blend_control
[i
] = 0;
785 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
789 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
790 /* Disable RB+ blend optimizations for dual source blending. */
791 if (blend
.mrt0_is_dual_src
) {
792 for (i
= 0; i
< 8; i
++) {
793 blend
.sx_mrt_blend_opt
[i
] =
794 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
795 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
799 /* RB+ doesn't work with dual source blending, logic op and
802 if (blend
.mrt0_is_dual_src
||
803 (vkblend
&& vkblend
->logicOpEnable
) ||
804 mode
== V_028808_CB_RESOLVE
)
805 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
808 if (blend
.cb_target_mask
)
809 blend
.cb_color_control
|= S_028808_MODE(mode
);
811 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
813 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
817 static uint32_t si_translate_fill(VkPolygonMode func
)
820 case VK_POLYGON_MODE_FILL
:
821 return V_028814_X_DRAW_TRIANGLES
;
822 case VK_POLYGON_MODE_LINE
:
823 return V_028814_X_DRAW_LINES
;
824 case VK_POLYGON_MODE_POINT
:
825 return V_028814_X_DRAW_POINTS
;
828 return V_028814_X_DRAW_POINTS
;
832 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
834 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
835 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
836 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
837 uint32_t ps_iter_samples
= 1;
838 uint32_t num_samples
;
840 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
842 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
843 * subpass uses color attachments, totalSamples is the number of
844 * samples of the color attachments. Otherwise, totalSamples is the
845 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
846 * specified at pipeline creation time."
848 if (subpass
->has_color_att
) {
849 num_samples
= subpass
->color_sample_count
;
851 num_samples
= vkms
->rasterizationSamples
;
854 if (vkms
->sampleShadingEnable
) {
855 ps_iter_samples
= ceilf(vkms
->minSampleShading
* num_samples
);
856 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
858 return ps_iter_samples
;
862 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
864 return pCreateInfo
->depthTestEnable
&&
865 pCreateInfo
->depthWriteEnable
&&
866 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
870 radv_writes_stencil(const VkStencilOpState
*state
)
872 return state
->writeMask
&&
873 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
874 state
->passOp
!= VK_STENCIL_OP_KEEP
||
875 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
879 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
881 return pCreateInfo
->stencilTestEnable
&&
882 (radv_writes_stencil(&pCreateInfo
->front
) ||
883 radv_writes_stencil(&pCreateInfo
->back
));
887 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
889 return radv_is_depth_write_enabled(pCreateInfo
) ||
890 radv_is_stencil_write_enabled(pCreateInfo
);
894 radv_order_invariant_stencil_op(VkStencilOp op
)
896 /* REPLACE is normally order invariant, except when the stencil
897 * reference value is written by the fragment shader. Tracking this
898 * interaction does not seem worth the effort, so be conservative.
900 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
901 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
902 op
!= VK_STENCIL_OP_REPLACE
;
906 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
908 /* Compute whether, assuming Z writes are disabled, this stencil state
909 * is order invariant in the sense that the set of passing fragments as
910 * well as the final stencil buffer result does not depend on the order
913 return !state
->writeMask
||
914 /* The following assumes that Z writes are disabled. */
915 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
916 radv_order_invariant_stencil_op(state
->passOp
) &&
917 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
918 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
919 radv_order_invariant_stencil_op(state
->failOp
));
923 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
925 VkDynamicState ds_states
[] = {
926 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT
,
927 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT
,
928 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT
,
929 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT
,
930 VK_DYNAMIC_STATE_STENCIL_OP_EXT
,
933 if (pCreateInfo
->pDynamicState
) {
934 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
935 for (uint32_t i
= 0; i
< count
; i
++) {
936 for (uint32_t j
= 0; j
< ARRAY_SIZE(ds_states
); j
++) {
937 if (pCreateInfo
->pDynamicState
->pDynamicStates
[i
] == ds_states
[j
])
947 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
948 struct radv_blend_state
*blend
,
949 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
951 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
952 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
953 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
954 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
955 unsigned colormask
= blend
->cb_target_enabled_4bit
;
957 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
960 /* Be conservative if a logic operation is enabled with color buffers. */
961 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
964 /* Be conservative if an extended dynamic depth/stencil state is
965 * enabled because the driver can't update out-of-order rasterization
968 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo
))
971 /* Default depth/stencil invariance when no attachment is bound. */
972 struct radv_dsa_order_invariance dsa_order_invariant
= {
973 .zs
= true, .pass_set
= true
977 struct radv_render_pass_attachment
*attachment
=
978 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
979 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
980 struct radv_dsa_order_invariance order_invariance
[2];
981 struct radv_shader_variant
*ps
=
982 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
984 /* Compute depth/stencil order invariance in order to know if
985 * it's safe to enable out-of-order.
987 bool zfunc_is_ordered
=
988 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
989 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
990 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
991 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
992 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
994 bool nozwrite_and_order_invariant_stencil
=
995 !radv_is_ds_write_enabled(vkds
) ||
996 (!radv_is_depth_write_enabled(vkds
) &&
997 radv_order_invariant_stencil_state(&vkds
->front
) &&
998 radv_order_invariant_stencil_state(&vkds
->back
));
1000 order_invariance
[1].zs
=
1001 nozwrite_and_order_invariant_stencil
||
1002 (!radv_is_stencil_write_enabled(vkds
) &&
1004 order_invariance
[0].zs
=
1005 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1007 order_invariance
[1].pass_set
=
1008 nozwrite_and_order_invariant_stencil
||
1009 (!radv_is_stencil_write_enabled(vkds
) &&
1010 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1011 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1012 order_invariance
[0].pass_set
=
1013 !radv_is_depth_write_enabled(vkds
) ||
1014 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1015 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1017 dsa_order_invariant
= order_invariance
[has_stencil
];
1018 if (!dsa_order_invariant
.zs
)
1021 /* The set of PS invocations is always order invariant,
1022 * except when early Z/S tests are requested.
1025 ps
->info
.ps
.writes_memory
&&
1026 ps
->info
.ps
.early_fragment_test
&&
1027 !dsa_order_invariant
.pass_set
)
1030 /* Determine if out-of-order rasterization should be disabled
1031 * when occlusion queries are used.
1033 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1034 !dsa_order_invariant
.pass_set
;
1037 /* No color buffers are enabled for writing. */
1041 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1044 /* Only commutative blending. */
1045 if (blendmask
& ~blend
->commutative_4bit
)
1048 if (!dsa_order_invariant
.pass_set
)
1052 if (colormask
& ~blendmask
)
1059 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1060 struct radv_blend_state
*blend
,
1061 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1063 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1064 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1065 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1066 bool out_of_order_rast
= false;
1067 int ps_iter_samples
= 1;
1068 uint32_t mask
= 0xffff;
1071 ms
->num_samples
= vkms
->rasterizationSamples
;
1073 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1075 * "Sample shading is enabled for a graphics pipeline:
1077 * - If the interface of the fragment shader entry point of the
1078 * graphics pipeline includes an input variable decorated
1079 * with SampleId or SamplePosition. In this case
1080 * minSampleShadingFactor takes the value 1.0.
1081 * - Else if the sampleShadingEnable member of the
1082 * VkPipelineMultisampleStateCreateInfo structure specified
1083 * when creating the graphics pipeline is set to VK_TRUE. In
1084 * this case minSampleShadingFactor takes the value of
1085 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1087 * Otherwise, sample shading is considered disabled."
1089 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1090 ps_iter_samples
= ms
->num_samples
;
1092 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1095 ms
->num_samples
= 1;
1098 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1099 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1100 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1101 /* Out-of-order rasterization is explicitly enabled by the
1104 out_of_order_rast
= true;
1106 /* Determine if the driver can enable out-of-order
1107 * rasterization internally.
1110 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1113 ms
->pa_sc_aa_config
= 0;
1114 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1115 S_028804_INCOHERENT_EQAA_READS(1) |
1116 S_028804_INTERPOLATE_COMP_Z(1) |
1117 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1118 ms
->pa_sc_mode_cntl_1
=
1119 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1120 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1121 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1122 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1124 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1125 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1126 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1127 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1128 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1129 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1130 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1131 S_028A48_VPORT_SCISSOR_ENABLE(1);
1133 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1134 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1135 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1137 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1138 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1139 /* From the Vulkan spec 1.1.129:
1141 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1142 * are being rasterized, sample locations may all be
1143 * treated as being at the pixel center (this may
1144 * affect attribute and depth interpolation)."
1146 ms
->num_samples
= 1;
1150 if (ms
->num_samples
> 1) {
1151 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1152 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1153 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1154 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1155 unsigned log_z_samples
= util_logbase2(z_samples
);
1156 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1157 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1158 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1159 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1160 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1161 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1162 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1163 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1164 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1165 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
);
1166 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1167 if (ps_iter_samples
> 1)
1168 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1171 if (vkms
&& vkms
->pSampleMask
) {
1172 mask
= vkms
->pSampleMask
[0] & 0xffff;
1175 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1176 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1180 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1183 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1184 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1187 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1193 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1194 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1197 unreachable("unhandled primitive type");
1202 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1205 case 0: /* GL_POINTS */
1206 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1207 case 1: /* GL_LINES */
1208 case 3: /* GL_LINE_STRIP */
1209 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1210 case 0x8E7A: /* GL_ISOLINES */
1211 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1213 case 4: /* GL_TRIANGLES */
1214 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1215 case 5: /* GL_TRIANGLE_STRIP */
1216 case 7: /* GL_QUADS */
1217 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1225 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1228 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1229 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1230 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1233 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1234 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1235 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1236 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1238 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1240 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1241 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1248 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1251 case VK_DYNAMIC_STATE_VIEWPORT
:
1252 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT
:
1253 return RADV_DYNAMIC_VIEWPORT
;
1254 case VK_DYNAMIC_STATE_SCISSOR
:
1255 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT
:
1256 return RADV_DYNAMIC_SCISSOR
;
1257 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1258 return RADV_DYNAMIC_LINE_WIDTH
;
1259 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1260 return RADV_DYNAMIC_DEPTH_BIAS
;
1261 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1262 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1263 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1264 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1265 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1266 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1267 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1268 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1269 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1270 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1271 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1272 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1273 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1274 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1275 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1276 return RADV_DYNAMIC_LINE_STIPPLE
;
1277 case VK_DYNAMIC_STATE_CULL_MODE_EXT
:
1278 return RADV_DYNAMIC_CULL_MODE
;
1279 case VK_DYNAMIC_STATE_FRONT_FACE_EXT
:
1280 return RADV_DYNAMIC_FRONT_FACE
;
1281 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT
:
1282 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
;
1283 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT
:
1284 return RADV_DYNAMIC_DEPTH_TEST_ENABLE
;
1285 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT
:
1286 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE
;
1287 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT
:
1288 return RADV_DYNAMIC_DEPTH_COMPARE_OP
;
1289 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT
:
1290 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
;
1291 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT
:
1292 return RADV_DYNAMIC_STENCIL_TEST_ENABLE
;
1293 case VK_DYNAMIC_STATE_STENCIL_OP_EXT
:
1294 return RADV_DYNAMIC_STENCIL_OP
;
1295 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT
:
1296 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
;
1298 unreachable("Unhandled dynamic state");
1302 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1304 uint32_t states
= RADV_DYNAMIC_ALL
;
1306 /* If rasterization is disabled we do not care about any of the
1307 * dynamic states, since they are all rasterization related only,
1308 * except primitive topology and vertex binding stride.
1310 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1311 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
|
1312 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
;
1314 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1315 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1317 if (!pCreateInfo
->pDepthStencilState
||
1318 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1319 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1321 if (!pCreateInfo
->pDepthStencilState
||
1322 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1323 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1324 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1325 RADV_DYNAMIC_STENCIL_REFERENCE
);
1327 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1328 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1330 if (!pCreateInfo
->pMultisampleState
||
1331 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1332 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1333 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1335 if (!pCreateInfo
->pRasterizationState
||
1336 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1337 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1338 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1340 /* TODO: blend constants & line width. */
1347 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1348 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1349 const struct radv_graphics_pipeline_create_info
*extra
)
1351 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1352 uint32_t states
= needed_states
;
1353 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1354 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1356 pipeline
->dynamic_state
= default_dynamic_state
;
1357 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1359 if (pCreateInfo
->pDynamicState
) {
1360 /* Remove all of the states that are marked as dynamic */
1361 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1362 for (uint32_t s
= 0; s
< count
; s
++)
1363 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1366 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1368 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1369 assert(pCreateInfo
->pViewportState
);
1371 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1372 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1373 typed_memcpy(dynamic
->viewport
.viewports
,
1374 pCreateInfo
->pViewportState
->pViewports
,
1375 pCreateInfo
->pViewportState
->viewportCount
);
1379 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1380 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1381 if (states
& RADV_DYNAMIC_SCISSOR
) {
1382 typed_memcpy(dynamic
->scissor
.scissors
,
1383 pCreateInfo
->pViewportState
->pScissors
,
1384 pCreateInfo
->pViewportState
->scissorCount
);
1388 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1389 assert(pCreateInfo
->pRasterizationState
);
1390 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1393 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1394 assert(pCreateInfo
->pRasterizationState
);
1395 dynamic
->depth_bias
.bias
=
1396 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1397 dynamic
->depth_bias
.clamp
=
1398 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1399 dynamic
->depth_bias
.slope
=
1400 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1403 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1405 * pColorBlendState is [...] NULL if the pipeline has rasterization
1406 * disabled or if the subpass of the render pass the pipeline is
1407 * created against does not use any color attachments.
1409 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1410 assert(pCreateInfo
->pColorBlendState
);
1411 typed_memcpy(dynamic
->blend_constants
,
1412 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1415 if (states
& RADV_DYNAMIC_CULL_MODE
) {
1416 dynamic
->cull_mode
=
1417 pCreateInfo
->pRasterizationState
->cullMode
;
1420 if (states
& RADV_DYNAMIC_FRONT_FACE
) {
1421 dynamic
->front_face
=
1422 pCreateInfo
->pRasterizationState
->frontFace
;
1425 if (states
& RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
) {
1426 dynamic
->primitive_topology
=
1427 si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
1428 if (extra
&& extra
->use_rectlist
) {
1429 dynamic
->primitive_topology
= V_008958_DI_PT_RECTLIST
;
1433 /* If there is no depthstencil attachment, then don't read
1434 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1435 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1436 * no need to override the depthstencil defaults in
1437 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1439 * Section 9.2 of the Vulkan 1.0.15 spec says:
1441 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1442 * disabled or if the subpass of the render pass the pipeline is created
1443 * against does not use a depth/stencil attachment.
1445 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1446 assert(pCreateInfo
->pDepthStencilState
);
1448 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1449 dynamic
->depth_bounds
.min
=
1450 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1451 dynamic
->depth_bounds
.max
=
1452 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1455 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1456 dynamic
->stencil_compare_mask
.front
=
1457 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1458 dynamic
->stencil_compare_mask
.back
=
1459 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1462 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1463 dynamic
->stencil_write_mask
.front
=
1464 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1465 dynamic
->stencil_write_mask
.back
=
1466 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1469 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1470 dynamic
->stencil_reference
.front
=
1471 pCreateInfo
->pDepthStencilState
->front
.reference
;
1472 dynamic
->stencil_reference
.back
=
1473 pCreateInfo
->pDepthStencilState
->back
.reference
;
1476 if (states
& RADV_DYNAMIC_DEPTH_TEST_ENABLE
) {
1477 dynamic
->depth_test_enable
=
1478 pCreateInfo
->pDepthStencilState
->depthTestEnable
;
1481 if (states
& RADV_DYNAMIC_DEPTH_WRITE_ENABLE
) {
1482 dynamic
->depth_write_enable
=
1483 pCreateInfo
->pDepthStencilState
->depthWriteEnable
;
1486 if (states
& RADV_DYNAMIC_DEPTH_COMPARE_OP
) {
1487 dynamic
->depth_compare_op
=
1488 pCreateInfo
->pDepthStencilState
->depthCompareOp
;
1491 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
) {
1492 dynamic
->depth_bounds_test_enable
=
1493 pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
;
1496 if (states
& RADV_DYNAMIC_STENCIL_TEST_ENABLE
) {
1497 dynamic
->stencil_test_enable
=
1498 pCreateInfo
->pDepthStencilState
->stencilTestEnable
;
1501 if (states
& RADV_DYNAMIC_STENCIL_OP
) {
1502 dynamic
->stencil_op
.front
.compare_op
=
1503 pCreateInfo
->pDepthStencilState
->front
.compareOp
;
1504 dynamic
->stencil_op
.front
.fail_op
=
1505 pCreateInfo
->pDepthStencilState
->front
.failOp
;
1506 dynamic
->stencil_op
.front
.pass_op
=
1507 pCreateInfo
->pDepthStencilState
->front
.passOp
;
1508 dynamic
->stencil_op
.front
.depth_fail_op
=
1509 pCreateInfo
->pDepthStencilState
->front
.depthFailOp
;
1511 dynamic
->stencil_op
.back
.compare_op
=
1512 pCreateInfo
->pDepthStencilState
->back
.compareOp
;
1513 dynamic
->stencil_op
.back
.fail_op
=
1514 pCreateInfo
->pDepthStencilState
->back
.failOp
;
1515 dynamic
->stencil_op
.back
.pass_op
=
1516 pCreateInfo
->pDepthStencilState
->back
.passOp
;
1517 dynamic
->stencil_op
.back
.depth_fail_op
=
1518 pCreateInfo
->pDepthStencilState
->back
.depthFailOp
;
1522 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1523 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1524 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1525 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1526 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1527 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1528 discard_rectangle_info
->pDiscardRectangles
,
1529 discard_rectangle_info
->discardRectangleCount
);
1533 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1534 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1535 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1536 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1537 /* If sampleLocationsEnable is VK_FALSE, the default sample
1538 * locations are used and the values specified in
1539 * sampleLocationsInfo are ignored.
1541 if (sample_location_info
->sampleLocationsEnable
) {
1542 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1543 &sample_location_info
->sampleLocationsInfo
;
1545 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1547 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1548 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1549 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1550 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1551 pSampleLocationsInfo
->pSampleLocations
,
1552 pSampleLocationsInfo
->sampleLocationsCount
);
1556 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1557 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1558 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1559 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1560 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1561 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1564 if (!(states
& RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
))
1565 pipeline
->graphics
.uses_dynamic_stride
= true;
1567 pipeline
->dynamic_state
.mask
= states
;
1571 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1572 const struct radv_pipeline
*pipeline
,
1574 struct radv_shader_info
*infos
,
1575 struct gfx9_gs_info
*out
)
1577 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1578 struct radv_es_output_info
*es_info
;
1579 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1580 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1582 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1583 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1584 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1586 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1587 bool uses_adjacency
;
1588 switch(key
->topology
) {
1589 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1590 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1591 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1592 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1593 uses_adjacency
= true;
1596 uses_adjacency
= false;
1600 /* All these are in dwords: */
1601 /* We can't allow using the whole LDS, because GS waves compete with
1602 * other shader stages for LDS space. */
1603 const unsigned max_lds_size
= 8 * 1024;
1604 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1605 unsigned esgs_lds_size
;
1607 /* All these are per subgroup: */
1608 const unsigned max_out_prims
= 32 * 1024;
1609 const unsigned max_es_verts
= 255;
1610 const unsigned ideal_gs_prims
= 64;
1611 unsigned max_gs_prims
, gs_prims
;
1612 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1614 if (uses_adjacency
|| gs_num_invocations
> 1)
1615 max_gs_prims
= 127 / gs_num_invocations
;
1619 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1620 * Make sure we don't go over the maximum value.
1622 if (gs_info
->gs
.vertices_out
> 0) {
1623 max_gs_prims
= MIN2(max_gs_prims
,
1625 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1627 assert(max_gs_prims
> 0);
1629 /* If the primitive has adjacency, halve the number of vertices
1630 * that will be reused in multiple primitives.
1632 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1634 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1635 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1637 /* Compute ESGS LDS size based on the worst case number of ES vertices
1638 * needed to create the target number of GS prims per subgroup.
1640 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1642 /* If total LDS usage is too big, refactor partitions based on ratio
1643 * of ESGS item sizes.
1645 if (esgs_lds_size
> max_lds_size
) {
1646 /* Our target GS Prims Per Subgroup was too large. Calculate
1647 * the maximum number of GS Prims Per Subgroup that will fit
1648 * into LDS, capped by the maximum that the hardware can support.
1650 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1652 assert(gs_prims
> 0);
1653 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1656 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1657 assert(esgs_lds_size
<= max_lds_size
);
1660 /* Now calculate remaining ESGS information. */
1662 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1664 es_verts
= max_es_verts
;
1666 /* Vertices for adjacency primitives are not always reused, so restore
1667 * it for ES_VERTS_PER_SUBGRP.
1669 min_es_verts
= gs_info
->gs
.vertices_in
;
1671 /* For normal primitives, the VGT only checks if they are past the ES
1672 * verts per subgroup after allocating a full GS primitive and if they
1673 * are, kick off a new subgroup. But if those additional ES verts are
1674 * unique (e.g. not reused) we need to make sure there is enough LDS
1675 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1677 es_verts
-= min_es_verts
- 1;
1679 uint32_t es_verts_per_subgroup
= es_verts
;
1680 uint32_t gs_prims_per_subgroup
= gs_prims
;
1681 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1682 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1683 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1684 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1685 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1686 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1687 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1688 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1689 assert(max_prims_per_subgroup
<= max_out_prims
);
1692 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1693 unsigned min_verts_per_prim
, bool use_adjacency
)
1695 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1698 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1702 radv_get_num_input_vertices(nir_shader
**nir
)
1704 if (nir
[MESA_SHADER_GEOMETRY
]) {
1705 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1707 return gs
->info
.gs
.vertices_in
;
1710 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1711 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1713 if (tes
->info
.tess
.point_mode
)
1715 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1724 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1725 struct radv_pipeline
*pipeline
,
1727 struct radv_shader_info
*infos
,
1728 struct gfx10_ngg_info
*ngg
)
1730 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1731 struct radv_es_output_info
*es_info
=
1732 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1733 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1734 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1735 unsigned min_verts_per_prim
=
1736 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1737 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1738 bool uses_adjacency
;
1739 switch(key
->topology
) {
1740 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1741 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1742 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1743 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1744 uses_adjacency
= true;
1747 uses_adjacency
= false;
1751 /* All these are in dwords: */
1752 /* We can't allow using the whole LDS, because GS waves compete with
1753 * other shader stages for LDS space.
1755 * TODO: We should really take the shader's internal LDS use into
1756 * account. The linker will fail if the size is greater than
1759 const unsigned max_lds_size
= 8 * 1024 - 768;
1760 const unsigned target_lds_size
= max_lds_size
;
1761 unsigned esvert_lds_size
= 0;
1762 unsigned gsprim_lds_size
= 0;
1764 /* All these are per subgroup: */
1765 bool max_vert_out_per_gs_instance
= false;
1766 unsigned max_esverts_base
= 256;
1767 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1769 /* Hardware has the following non-natural restrictions on the value
1770 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1772 * - at most 252 for any line input primitive type
1773 * - at most 251 for any quad input primitive type
1774 * - at most 251 for triangle strips with adjacency (this happens to
1775 * be the natural limit for triangle *lists* with adjacency)
1777 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1779 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1780 unsigned max_out_verts_per_gsprim
=
1781 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1783 if (max_out_verts_per_gsprim
<= 256) {
1784 if (max_out_verts_per_gsprim
) {
1785 max_gsprims_base
= MIN2(max_gsprims_base
,
1786 256 / max_out_verts_per_gsprim
);
1789 /* Use special multi-cycling mode in which each GS
1790 * instance gets its own subgroup. Does not work with
1792 max_vert_out_per_gs_instance
= true;
1793 max_gsprims_base
= 1;
1794 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1797 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1798 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1801 /* LDS size for passing data from GS to ES. */
1802 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1803 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1804 : &infos
[MESA_SHADER_VERTEX
].so
;
1806 if (so_info
->num_outputs
)
1807 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1809 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1810 * corresponding to the ES thread of the provoking vertex. All
1811 * ES threads load and export PrimitiveID for their thread.
1813 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1814 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1815 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1818 unsigned max_gsprims
= max_gsprims_base
;
1819 unsigned max_esverts
= max_esverts_base
;
1821 if (esvert_lds_size
)
1822 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1823 if (gsprim_lds_size
)
1824 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1826 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1827 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1828 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1830 if (esvert_lds_size
|| gsprim_lds_size
) {
1831 /* Now that we have a rough proportionality between esverts
1832 * and gsprims based on the primitive type, scale both of them
1833 * down simultaneously based on required LDS space.
1835 * We could be smarter about this if we knew how much vertex
1838 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1839 max_gsprims
* gsprim_lds_size
;
1840 if (lds_total
> target_lds_size
) {
1841 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1842 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1844 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1845 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1846 min_verts_per_prim
, uses_adjacency
);
1847 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1851 /* Round up towards full wave sizes for better ALU utilization. */
1852 if (!max_vert_out_per_gs_instance
) {
1853 unsigned orig_max_esverts
;
1854 unsigned orig_max_gsprims
;
1857 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1858 wavesize
= gs_info
->wave_size
;
1860 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1861 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1862 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1866 orig_max_esverts
= max_esverts
;
1867 orig_max_gsprims
= max_gsprims
;
1869 max_esverts
= align(max_esverts
, wavesize
);
1870 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1871 if (esvert_lds_size
)
1872 max_esverts
= MIN2(max_esverts
,
1873 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1875 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1877 max_gsprims
= align(max_gsprims
, wavesize
);
1878 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1879 if (gsprim_lds_size
)
1880 max_gsprims
= MIN2(max_gsprims
,
1881 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1883 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1884 min_verts_per_prim
, uses_adjacency
);
1885 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1886 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1889 /* Hardware restriction: minimum value of max_esverts */
1890 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1892 unsigned max_out_vertices
=
1893 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1894 gs_type
== MESA_SHADER_GEOMETRY
?
1895 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1897 assert(max_out_vertices
<= 256);
1899 unsigned prim_amp_factor
= 1;
1900 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1901 /* Number of output primitives per GS input primitive after
1903 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1906 /* The GE only checks against the maximum number of ES verts after
1907 * allocating a full GS primitive. So we need to ensure that whenever
1908 * this check passes, there is enough space for a full primitive without
1911 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1912 ngg
->max_gsprims
= max_gsprims
;
1913 ngg
->max_out_verts
= max_out_vertices
;
1914 ngg
->prim_amp_factor
= prim_amp_factor
;
1915 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1916 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1917 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1919 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1920 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1922 ngg
->vgt_esgs_ring_itemsize
= 1;
1925 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1927 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1931 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1932 const struct gfx9_gs_info
*gs
)
1934 struct radv_device
*device
= pipeline
->device
;
1935 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1936 unsigned wave_size
= 64;
1937 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1938 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1939 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1941 unsigned gs_vertex_reuse
=
1942 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1943 unsigned alignment
= 256 * num_se
;
1944 /* The maximum size is 63.999 MB per SE. */
1945 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1946 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1948 /* Calculate the minimum size. */
1949 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1950 wave_size
, alignment
);
1951 /* These are recommended sizes, not minimum sizes. */
1952 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1953 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1954 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1955 gs_info
->gs
.max_gsvs_emit_size
;
1957 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1958 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1959 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1961 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1962 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1964 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1967 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1970 /* If tessellation is all offchip and on-chip GS isn't used, this
1971 * workaround is not needed.
1975 /* SPI barrier management bug:
1976 * Make sure we have at least 4k of LDS in use to avoid the bug.
1977 * It applies to workgroup sizes of more than one wavefront.
1979 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1980 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1981 *lds_size
= MAX2(*lds_size
, 8);
1984 struct radv_shader_variant
*
1985 radv_get_shader(struct radv_pipeline
*pipeline
,
1986 gl_shader_stage stage
)
1988 if (stage
== MESA_SHADER_VERTEX
) {
1989 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1990 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1991 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1992 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1993 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1994 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1995 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1996 if (!radv_pipeline_has_tess(pipeline
))
1998 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1999 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
2000 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
2001 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2003 return pipeline
->shaders
[stage
];
2006 static struct radv_tessellation_state
2007 calculate_tess_state(struct radv_pipeline
*pipeline
,
2008 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2010 unsigned num_tcs_input_cp
;
2011 unsigned num_tcs_output_cp
;
2013 unsigned num_patches
;
2014 struct radv_tessellation_state tess
= {0};
2016 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2017 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
2018 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2020 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
2022 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2023 assert(lds_size
<= 65536);
2024 lds_size
= align(lds_size
, 512) / 512;
2026 assert(lds_size
<= 32768);
2027 lds_size
= align(lds_size
, 256) / 256;
2029 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
2031 tess
.lds_size
= lds_size
;
2033 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
2034 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
2035 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
2036 tess
.num_patches
= num_patches
;
2038 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
2039 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
2041 switch (tes
->info
.tes
.primitive_mode
) {
2043 type
= V_028B6C_TESS_TRIANGLE
;
2046 type
= V_028B6C_TESS_QUAD
;
2049 type
= V_028B6C_TESS_ISOLINE
;
2053 switch (tes
->info
.tes
.spacing
) {
2054 case TESS_SPACING_EQUAL
:
2055 partitioning
= V_028B6C_PART_INTEGER
;
2057 case TESS_SPACING_FRACTIONAL_ODD
:
2058 partitioning
= V_028B6C_PART_FRAC_ODD
;
2060 case TESS_SPACING_FRACTIONAL_EVEN
:
2061 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2067 bool ccw
= tes
->info
.tes
.ccw
;
2068 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2069 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2070 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2072 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2075 if (tes
->info
.tes
.point_mode
)
2076 topology
= V_028B6C_OUTPUT_POINT
;
2077 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2078 topology
= V_028B6C_OUTPUT_LINE
;
2080 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2082 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2084 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2085 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2086 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2087 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2089 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2091 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2093 tess
.tf_param
= S_028B6C_TYPE(type
) |
2094 S_028B6C_PARTITIONING(partitioning
) |
2095 S_028B6C_TOPOLOGY(topology
) |
2096 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2101 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2103 if (radv_pipeline_has_gs(pipeline
))
2104 if (radv_pipeline_has_ngg(pipeline
))
2105 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2107 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2108 else if (radv_pipeline_has_tess(pipeline
))
2109 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2111 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2115 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2117 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2118 int shader_count
= 0;
2120 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2121 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2123 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2124 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2126 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2127 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2129 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2130 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2132 if(shaders
[MESA_SHADER_VERTEX
]) {
2133 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2136 if (shader_count
> 1) {
2137 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2138 unsigned last
= ordered_shaders
[0]->info
.stage
;
2140 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2141 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2142 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2144 for (int i
= 0; i
< shader_count
; ++i
) {
2145 nir_variable_mode mask
= 0;
2147 if (ordered_shaders
[i
]->info
.stage
!= first
)
2148 mask
= mask
| nir_var_shader_in
;
2150 if (ordered_shaders
[i
]->info
.stage
!= last
)
2151 mask
= mask
| nir_var_shader_out
;
2153 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2154 radv_optimize_nir(ordered_shaders
[i
], false, false);
2158 for (int i
= 1; i
< shader_count
; ++i
) {
2159 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2160 ordered_shaders
[i
- 1]);
2162 if (nir_link_opt_varyings(ordered_shaders
[i
],
2163 ordered_shaders
[i
- 1]))
2164 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2166 nir_remove_dead_variables(ordered_shaders
[i
],
2167 nir_var_shader_out
, NULL
);
2168 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2169 nir_var_shader_in
, NULL
);
2171 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2172 ordered_shaders
[i
- 1]);
2174 nir_compact_varyings(ordered_shaders
[i
],
2175 ordered_shaders
[i
- 1], true);
2178 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2179 ac_lower_indirect_derefs(ordered_shaders
[i
],
2180 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2182 radv_optimize_nir(ordered_shaders
[i
], false, false);
2184 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2185 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2186 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2188 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2194 radv_set_linked_driver_locations(struct radv_pipeline
*pipeline
, nir_shader
**shaders
,
2195 struct radv_shader_info infos
[MESA_SHADER_STAGES
])
2197 bool has_tess
= shaders
[MESA_SHADER_TESS_CTRL
];
2198 bool has_gs
= shaders
[MESA_SHADER_GEOMETRY
];
2200 if (!has_tess
&& !has_gs
)
2203 unsigned vs_info_idx
= MESA_SHADER_VERTEX
;
2204 unsigned tes_info_idx
= MESA_SHADER_TESS_EVAL
;
2206 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2207 /* These are merged into the next stage */
2208 vs_info_idx
= has_tess
? MESA_SHADER_TESS_CTRL
: MESA_SHADER_GEOMETRY
;
2209 tes_info_idx
= has_gs
? MESA_SHADER_GEOMETRY
: MESA_SHADER_TESS_EVAL
;
2213 nir_linked_io_var_info vs2tcs
=
2214 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_TESS_CTRL
]);
2215 nir_linked_io_var_info tcs2tes
=
2216 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_CTRL
], shaders
[MESA_SHADER_TESS_EVAL
]);
2218 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2tcs
.num_linked_io_vars
;
2219 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_inputs
= vs2tcs
.num_linked_io_vars
;
2220 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_outputs
= tcs2tes
.num_linked_io_vars
;
2221 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_patch_outputs
= tcs2tes
.num_linked_patch_io_vars
;
2222 infos
[tes_info_idx
].tes
.num_linked_inputs
= tcs2tes
.num_linked_io_vars
;
2223 infos
[tes_info_idx
].tes
.num_linked_patch_inputs
= tcs2tes
.num_linked_patch_io_vars
;
2226 nir_linked_io_var_info tes2gs
=
2227 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_EVAL
], shaders
[MESA_SHADER_GEOMETRY
]);
2229 infos
[tes_info_idx
].tes
.num_linked_outputs
= tes2gs
.num_linked_io_vars
;
2230 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= tes2gs
.num_linked_io_vars
;
2232 } else if (has_gs
) {
2233 nir_linked_io_var_info vs2gs
=
2234 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_GEOMETRY
]);
2236 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2gs
.num_linked_io_vars
;
2237 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= vs2gs
.num_linked_io_vars
;
2242 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2243 uint32_t attrib_binding
)
2245 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2246 const VkVertexInputBindingDescription
*input_binding
=
2247 &input_state
->pVertexBindingDescriptions
[i
];
2249 if (input_binding
->binding
== attrib_binding
)
2250 return input_binding
->stride
;
2256 static struct radv_pipeline_key
2257 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2258 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2259 const struct radv_blend_state
*blend
,
2260 bool has_view_index
)
2262 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2263 pCreateInfo
->pVertexInputState
;
2264 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2265 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2267 struct radv_pipeline_key key
;
2268 memset(&key
, 0, sizeof(key
));
2270 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2271 key
.optimisations_disabled
= 1;
2273 key
.has_multiview_view_index
= has_view_index
;
2275 uint32_t binding_input_rate
= 0;
2276 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2277 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2278 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2279 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2280 binding_input_rate
|= 1u << binding
;
2281 instance_rate_divisors
[binding
] = 1;
2284 if (divisor_state
) {
2285 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2286 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2287 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2291 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2292 const VkVertexInputAttributeDescription
*desc
=
2293 &input_state
->pVertexAttributeDescriptions
[i
];
2294 const struct vk_format_description
*format_desc
;
2295 unsigned location
= desc
->location
;
2296 unsigned binding
= desc
->binding
;
2297 unsigned num_format
, data_format
;
2300 if (binding_input_rate
& (1u << binding
)) {
2301 key
.instance_rate_inputs
|= 1u << location
;
2302 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2305 format_desc
= vk_format_description(desc
->format
);
2306 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2308 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2309 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2311 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2312 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2313 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2314 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2316 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2317 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2318 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2321 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2322 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2323 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2325 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2326 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2327 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2329 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2330 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2331 adjust
= RADV_ALPHA_ADJUST_SINT
;
2337 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2340 switch (desc
->format
) {
2341 case VK_FORMAT_B8G8R8A8_UNORM
:
2342 case VK_FORMAT_B8G8R8A8_SNORM
:
2343 case VK_FORMAT_B8G8R8A8_USCALED
:
2344 case VK_FORMAT_B8G8R8A8_SSCALED
:
2345 case VK_FORMAT_B8G8R8A8_UINT
:
2346 case VK_FORMAT_B8G8R8A8_SINT
:
2347 case VK_FORMAT_B8G8R8A8_SRGB
:
2348 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2349 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2350 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2351 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2352 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2353 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2354 key
.vertex_post_shuffle
|= 1 << location
;
2361 const VkPipelineTessellationStateCreateInfo
*tess
=
2362 radv_pipeline_get_tessellation_state(pCreateInfo
);
2364 key
.tess_input_vertices
= tess
->patchControlPoints
;
2366 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2367 radv_pipeline_get_multisample_state(pCreateInfo
);
2368 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2369 uint32_t num_samples
= vkms
->rasterizationSamples
;
2370 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2371 key
.num_samples
= num_samples
;
2372 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2375 key
.col_format
= blend
->spi_shader_col_format
;
2376 key
.is_dual_src
= blend
->mrt0_is_dual_src
;
2377 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
) {
2378 key
.is_int8
= blend
->col_format_is_int8
;
2379 key
.is_int10
= blend
->col_format_is_int10
;
2382 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2383 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2389 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2391 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2392 bool uses_xfb
= !!xfb
;
2399 radv_fill_shader_keys(struct radv_device
*device
,
2400 struct radv_shader_variant_key
*keys
,
2401 const struct radv_pipeline_key
*key
,
2404 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2405 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2406 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2407 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2408 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2409 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2410 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2411 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2412 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2414 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2416 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2417 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2418 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2419 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2420 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2422 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2425 if (nir
[MESA_SHADER_GEOMETRY
]) {
2426 if (nir
[MESA_SHADER_TESS_CTRL
])
2427 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2429 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2432 if (device
->physical_device
->use_ngg
) {
2433 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2434 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2436 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2439 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2440 nir
[MESA_SHADER_GEOMETRY
] &&
2441 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2442 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2443 /* Fallback to the legacy path if tessellation is
2444 * enabled with extreme geometry because
2445 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2448 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2451 if (!device
->physical_device
->use_ngg_gs
) {
2452 if (nir
[MESA_SHADER_GEOMETRY
]) {
2453 if (nir
[MESA_SHADER_TESS_CTRL
])
2454 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2456 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2460 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2462 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2467 bool uses_xfb
= nir
[last_xfb_stage
] &&
2468 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2470 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2471 if (nir
[MESA_SHADER_TESS_CTRL
])
2472 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2474 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2477 /* Determine if the pipeline is eligible for the NGG passthrough
2478 * mode. It can't be enabled for geometry shaders, for NGG
2479 * streamout or for vertex shaders that export the primitive ID
2480 * (this is checked later because we don't have the info here.)
2482 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2483 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2484 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2485 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2486 } else if (nir
[MESA_SHADER_VERTEX
] &&
2487 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2488 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2493 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2494 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2496 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2497 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2498 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2499 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2500 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2501 keys
[MESA_SHADER_FRAGMENT
].fs
.is_dual_src
= key
->is_dual_src
;
2503 if (nir
[MESA_SHADER_COMPUTE
]) {
2504 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2509 radv_get_wave_size(struct radv_device
*device
,
2510 const VkPipelineShaderStageCreateInfo
*pStage
,
2511 gl_shader_stage stage
,
2512 const struct radv_shader_variant_key
*key
)
2514 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2516 else if (stage
== MESA_SHADER_COMPUTE
) {
2517 if (key
->cs
.subgroup_size
) {
2518 /* Return the required subgroup size if specified. */
2519 return key
->cs
.subgroup_size
;
2521 return device
->physical_device
->cs_wave_size
;
2523 else if (stage
== MESA_SHADER_FRAGMENT
)
2524 return device
->physical_device
->ps_wave_size
;
2526 return device
->physical_device
->ge_wave_size
;
2530 radv_get_ballot_bit_size(struct radv_device
*device
,
2531 const VkPipelineShaderStageCreateInfo
*pStage
,
2532 gl_shader_stage stage
,
2533 const struct radv_shader_variant_key
*key
)
2535 if (stage
== MESA_SHADER_COMPUTE
&& key
->cs
.subgroup_size
)
2536 return key
->cs
.subgroup_size
;
2541 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2542 const VkPipelineShaderStageCreateInfo
**pStages
,
2543 struct radv_shader_variant_key
*keys
,
2544 struct radv_shader_info
*infos
,
2547 unsigned active_stages
= 0;
2548 unsigned filled_stages
= 0;
2550 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2552 active_stages
|= (1 << i
);
2555 if (nir
[MESA_SHADER_FRAGMENT
]) {
2556 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2557 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2559 &keys
[MESA_SHADER_FRAGMENT
],
2560 &infos
[MESA_SHADER_FRAGMENT
],
2561 pipeline
->device
->physical_device
->use_llvm
);
2563 /* TODO: These are no longer used as keys we should refactor this */
2564 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2565 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2566 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2567 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2568 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2569 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2570 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_viewport_index
=
2571 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2572 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2573 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2574 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2575 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2576 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2577 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2578 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_viewport_index
=
2579 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2581 /* NGG passthrough mode can't be enabled for vertex shaders
2582 * that export the primitive ID.
2584 * TODO: I should really refactor the keys logic.
2586 if (nir
[MESA_SHADER_VERTEX
] &&
2587 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2588 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2591 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2594 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2595 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_inputs_read
=
2596 nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
;
2597 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_patch_inputs_read
=
2598 nir
[MESA_SHADER_TESS_EVAL
]->info
.patch_inputs_read
;
2601 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2602 nir
[MESA_SHADER_TESS_CTRL
]) {
2603 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2604 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2605 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2607 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2609 for (int i
= 0; i
< 2; i
++) {
2610 radv_nir_shader_info_pass(combined_nir
[i
],
2611 pipeline
->layout
, &key
,
2612 &infos
[MESA_SHADER_TESS_CTRL
],
2613 pipeline
->device
->physical_device
->use_llvm
);
2616 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2617 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2618 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2619 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2621 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2622 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2625 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2626 nir
[MESA_SHADER_GEOMETRY
]) {
2627 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2628 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2630 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2632 for (int i
= 0; i
< 2; i
++) {
2633 radv_nir_shader_info_pass(combined_nir
[i
],
2636 &infos
[MESA_SHADER_GEOMETRY
],
2637 pipeline
->device
->physical_device
->use_llvm
);
2640 filled_stages
|= (1 << pre_stage
);
2641 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2644 active_stages
^= filled_stages
;
2645 while (active_stages
) {
2646 int i
= u_bit_scan(&active_stages
);
2648 if (i
== MESA_SHADER_TESS_CTRL
) {
2649 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2650 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2653 if (i
== MESA_SHADER_TESS_EVAL
) {
2654 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2655 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2656 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2657 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2660 radv_nir_shader_info_init(&infos
[i
]);
2661 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2662 &keys
[i
], &infos
[i
], pipeline
->device
->physical_device
->use_llvm
);
2665 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2667 infos
[i
].wave_size
=
2668 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2670 infos
[i
].ballot_bit_size
=
2671 radv_get_ballot_bit_size(pipeline
->device
,
2679 merge_tess_info(struct shader_info
*tes_info
,
2680 const struct shader_info
*tcs_info
)
2682 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2684 * "PointMode. Controls generation of points rather than triangles
2685 * or lines. This functionality defaults to disabled, and is
2686 * enabled if either shader stage includes the execution mode.
2688 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2689 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2690 * and OutputVertices, it says:
2692 * "One mode must be set in at least one of the tessellation
2695 * So, the fields can be set in either the TCS or TES, but they must
2696 * agree if set in both. Our backend looks at TES, so bitwise-or in
2697 * the values from the TCS.
2699 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2700 tes_info
->tess
.tcs_vertices_out
== 0 ||
2701 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2702 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2704 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2705 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2706 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2707 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2709 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2710 tes_info
->tess
.primitive_mode
== 0 ||
2711 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2712 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2713 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2714 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2718 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2723 if (ext
->pPipelineCreationFeedback
) {
2724 ext
->pPipelineCreationFeedback
->flags
= 0;
2725 ext
->pPipelineCreationFeedback
->duration
= 0;
2728 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2729 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2730 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2735 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2740 feedback
->duration
-= radv_get_current_time();
2741 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2745 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2750 feedback
->duration
+= radv_get_current_time();
2751 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2752 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2755 VkResult
radv_create_shaders(struct radv_pipeline
*pipeline
,
2756 struct radv_device
*device
,
2757 struct radv_pipeline_cache
*cache
,
2758 const struct radv_pipeline_key
*key
,
2759 const VkPipelineShaderStageCreateInfo
**pStages
,
2760 const VkPipelineCreateFlags flags
,
2761 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2762 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2764 struct radv_shader_module fs_m
= {0};
2765 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2766 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2767 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2768 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2769 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2770 unsigned char hash
[20], gs_copy_hash
[20];
2771 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2772 bool keep_statistic_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR
) ||
2773 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) ||
2774 device
->keep_shader_info
;
2776 radv_start_feedback(pipeline_feedback
);
2778 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2780 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2781 if (modules
[i
]->nir
)
2782 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2783 strlen(modules
[i
]->nir
->info
.name
),
2786 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2790 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2791 memcpy(gs_copy_hash
, hash
, 20);
2792 gs_copy_hash
[0] ^= 1;
2794 bool found_in_application_cache
= true;
2795 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
&& !keep_statistic_info
) {
2796 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2797 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2798 &found_in_application_cache
);
2799 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2802 if (!keep_executable_info
&& !keep_statistic_info
&&
2803 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2804 &found_in_application_cache
) &&
2805 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2806 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2810 if (flags
& VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT
) {
2811 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2812 return VK_PIPELINE_COMPILE_REQUIRED_EXT
;
2815 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2817 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2818 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2819 fs_m
.nir
= fs_b
.shader
;
2820 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2823 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2824 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2825 unsigned subgroup_size
= 64, ballot_bit_size
= 64;
2830 radv_start_feedback(stage_feedbacks
[i
]);
2832 if (key
->compute_subgroup_size
) {
2833 /* Only compute shaders currently support requiring a
2834 * specific subgroup size.
2836 assert(i
== MESA_SHADER_COMPUTE
);
2837 subgroup_size
= key
->compute_subgroup_size
;
2838 ballot_bit_size
= key
->compute_subgroup_size
;
2841 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2842 stage
? stage
->pName
: "main", i
,
2843 stage
? stage
->pSpecializationInfo
: NULL
,
2844 flags
, pipeline
->layout
,
2845 subgroup_size
, ballot_bit_size
);
2847 /* We don't want to alter meta shaders IR directly so clone it
2850 if (nir
[i
]->info
.name
) {
2851 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2854 radv_stop_feedback(stage_feedbacks
[i
], false);
2857 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2858 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2859 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2862 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2863 radv_link_shaders(pipeline
, nir
);
2865 radv_set_linked_driver_locations(pipeline
, nir
, infos
);
2867 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2869 /* do this again since information such as outputs_read can be out-of-date */
2870 nir_shader_gather_info(nir
[i
], nir_shader_get_entrypoint(nir
[i
]));
2872 if (device
->physical_device
->use_llvm
) {
2873 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2875 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2876 nir_lower_non_uniform_ubo_access
|
2877 nir_lower_non_uniform_ssbo_access
|
2878 nir_lower_non_uniform_texture_access
|
2879 nir_lower_non_uniform_image_access
);
2884 if (nir
[MESA_SHADER_FRAGMENT
])
2885 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2887 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2888 if (radv_can_dump_shader(device
, modules
[i
], false))
2889 nir_print_shader(nir
[i
], stderr
);
2892 radv_fill_shader_keys(device
, keys
, key
, nir
);
2894 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2896 if ((nir
[MESA_SHADER_VERTEX
] &&
2897 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2898 (nir
[MESA_SHADER_TESS_EVAL
] &&
2899 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2900 struct gfx10_ngg_info
*ngg_info
;
2902 if (nir
[MESA_SHADER_GEOMETRY
])
2903 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2904 else if (nir
[MESA_SHADER_TESS_CTRL
])
2905 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2907 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2909 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2910 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2911 struct gfx9_gs_info
*gs_info
=
2912 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2914 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2917 if(modules
[MESA_SHADER_GEOMETRY
]) {
2918 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2919 if (!pipeline
->gs_copy_shader
&&
2920 !radv_pipeline_has_ngg(pipeline
)) {
2921 struct radv_shader_info info
= {};
2922 struct radv_shader_variant_key key
= {};
2924 key
.has_multiview_view_index
=
2925 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2927 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2928 pipeline
->layout
, &key
,
2929 &info
, pipeline
->device
->physical_device
->use_llvm
);
2930 info
.wave_size
= 64; /* Wave32 not supported. */
2931 info
.ballot_bit_size
= 64;
2933 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2934 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2935 &gs_copy_binary
, keep_executable_info
, keep_statistic_info
,
2936 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2939 if (!keep_executable_info
&& !keep_statistic_info
&& pipeline
->gs_copy_shader
) {
2940 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2941 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2943 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2944 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2946 radv_pipeline_cache_insert_shaders(device
, cache
,
2951 free(gs_copy_binary
);
2954 if (nir
[MESA_SHADER_FRAGMENT
]) {
2955 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2956 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2958 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2959 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2960 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2961 infos
+ MESA_SHADER_FRAGMENT
,
2962 keep_executable_info
, keep_statistic_info
,
2963 &binaries
[MESA_SHADER_FRAGMENT
]);
2965 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2969 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2970 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2971 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2972 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2973 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2975 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2977 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2979 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2980 keep_statistic_info
, &binaries
[MESA_SHADER_TESS_CTRL
]);
2982 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2984 modules
[MESA_SHADER_VERTEX
] = NULL
;
2985 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2986 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2989 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2990 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2991 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2992 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2994 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2996 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2998 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2999 keep_statistic_info
, &binaries
[MESA_SHADER_GEOMETRY
]);
3001 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
3003 modules
[pre_stage
] = NULL
;
3006 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
3007 if(modules
[i
] && !pipeline
->shaders
[i
]) {
3008 if (i
== MESA_SHADER_TESS_CTRL
) {
3009 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
3011 if (i
== MESA_SHADER_TESS_EVAL
) {
3012 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
3013 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
3016 radv_start_feedback(stage_feedbacks
[i
]);
3018 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
3020 keys
+ i
, infos
+ i
, keep_executable_info
,
3021 keep_statistic_info
, &binaries
[i
]);
3023 radv_stop_feedback(stage_feedbacks
[i
], false);
3027 if (!keep_executable_info
&& !keep_statistic_info
) {
3028 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
3032 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
3035 ralloc_free(nir
[i
]);
3037 if (radv_can_dump_shader_stats(device
, modules
[i
]))
3038 radv_shader_dump_stats(device
,
3039 pipeline
->shaders
[i
],
3045 ralloc_free(fs_m
.nir
);
3047 radv_stop_feedback(pipeline_feedback
, false);
3052 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
3053 gl_shader_stage stage
, enum chip_class chip_class
)
3055 bool has_gs
= radv_pipeline_has_gs(pipeline
);
3056 bool has_tess
= radv_pipeline_has_tess(pipeline
);
3057 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
3060 case MESA_SHADER_FRAGMENT
:
3061 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
3062 case MESA_SHADER_VERTEX
:
3064 if (chip_class
>= GFX10
) {
3065 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3066 } else if (chip_class
== GFX9
) {
3067 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3069 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3075 if (chip_class
>= GFX10
) {
3076 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3078 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3083 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3085 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3086 case MESA_SHADER_GEOMETRY
:
3087 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3088 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3089 case MESA_SHADER_COMPUTE
:
3090 return R_00B900_COMPUTE_USER_DATA_0
;
3091 case MESA_SHADER_TESS_CTRL
:
3092 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3093 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3094 case MESA_SHADER_TESS_EVAL
:
3096 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3097 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3098 } else if (has_ngg
) {
3099 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3101 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3104 unreachable("unknown shader");
3108 struct radv_bin_size_entry
{
3114 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3116 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3120 /* One shader engine */
3126 { UINT_MAX
, { 0, 0}},
3129 /* Two shader engines */
3135 { UINT_MAX
, { 0, 0}},
3138 /* Four shader engines */
3143 { UINT_MAX
, { 0, 0}},
3149 /* One shader engine */
3155 { UINT_MAX
, { 0, 0}},
3158 /* Two shader engines */
3164 { UINT_MAX
, { 0, 0}},
3167 /* Four shader engines */
3174 { UINT_MAX
, { 0, 0}},
3180 /* One shader engine */
3187 { UINT_MAX
, { 0, 0}},
3190 /* Two shader engines */
3198 { UINT_MAX
, { 0, 0}},
3201 /* Four shader engines */
3209 { UINT_MAX
, { 0, 0}},
3213 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3217 // One shader engine
3224 { UINT_MAX
, { 0, 0}},
3227 // Two shader engines
3235 { UINT_MAX
, { 0, 0}},
3238 // Four shader engines
3246 { UINT_MAX
, { 0, 0}},
3252 // One shader engine
3260 { UINT_MAX
, { 0, 0}},
3263 // Two shader engines
3272 { UINT_MAX
, { 0, 0}},
3275 // Four shader engines
3284 { UINT_MAX
, { 0, 0}},
3290 // One shader engine
3298 { UINT_MAX
, { 0, 0}},
3301 // Two shader engines
3310 { UINT_MAX
, { 0, 0}},
3313 // Four shader engines
3321 { UINT_MAX
, { 0, 0}},
3326 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3327 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3328 VkExtent2D extent
= {512, 512};
3330 unsigned log_num_rb_per_se
=
3331 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3332 pipeline
->device
->physical_device
->rad_info
.max_se
);
3333 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3335 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3336 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3337 unsigned effective_samples
= total_samples
;
3338 unsigned color_bytes_per_pixel
= 0;
3340 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3341 radv_pipeline_get_color_blend_state(pCreateInfo
);
3343 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3344 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3347 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3350 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3351 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3354 /* MSAA images typically don't use all samples all the time. */
3355 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3356 effective_samples
= 2;
3357 color_bytes_per_pixel
*= effective_samples
;
3360 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3361 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3364 extent
= color_entry
->extent
;
3366 if (subpass
->depth_stencil_attachment
) {
3367 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3369 /* Coefficients taken from AMDVLK */
3370 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3371 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3372 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3374 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3375 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3378 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3379 extent
= ds_entry
->extent
;
3386 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3388 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3389 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3390 VkExtent2D extent
= {512, 512};
3392 const unsigned db_tag_size
= 64;
3393 const unsigned db_tag_count
= 312;
3394 const unsigned color_tag_size
= 1024;
3395 const unsigned color_tag_count
= 31;
3396 const unsigned fmask_tag_size
= 256;
3397 const unsigned fmask_tag_count
= 44;
3399 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3400 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3402 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3403 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3404 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3406 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3407 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3409 unsigned color_bytes_per_pixel
= 0;
3410 unsigned fmask_bytes_per_pixel
= 0;
3412 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3413 radv_pipeline_get_color_blend_state(pCreateInfo
);
3415 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3416 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3419 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3422 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3423 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3425 if (total_samples
> 1) {
3426 assert(samples_log
<= 3);
3427 const unsigned fmask_array
[] = {0, 1, 1, 4};
3428 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3432 color_bytes_per_pixel
*= total_samples
;
3434 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3436 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3437 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3438 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3440 if (fmask_bytes_per_pixel
) {
3441 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3443 const VkExtent2D fmask_extent
= (VkExtent2D
){
3444 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3445 .height
= 1ull << (color_pixel_count_log
/ 2)
3448 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3449 extent
= fmask_extent
;
3452 if (subpass
->depth_stencil_attachment
) {
3453 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3455 /* Coefficients taken from AMDVLK */
3456 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3457 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3458 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3460 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3462 const VkExtent2D db_extent
= (VkExtent2D
){
3463 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3464 .height
= 1ull << (color_pixel_count_log
/ 2)
3467 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3471 extent
.width
= MAX2(extent
.width
, 128);
3472 extent
.height
= MAX2(extent
.width
, 64);
3478 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3479 struct radv_pipeline
*pipeline
,
3480 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3482 uint32_t pa_sc_binner_cntl_0
=
3483 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3484 S_028C44_DISABLE_START_OF_PRIM(1);
3485 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3487 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3488 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3489 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3490 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3491 radv_pipeline_get_color_blend_state(pCreateInfo
);
3492 unsigned min_bytes_per_pixel
= 0;
3495 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3496 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3499 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3502 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3503 unsigned bytes
= vk_format_get_blocksize(format
);
3504 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3505 min_bytes_per_pixel
= bytes
;
3509 pa_sc_binner_cntl_0
=
3510 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3511 S_028C44_BIN_SIZE_X(0) |
3512 S_028C44_BIN_SIZE_Y(0) |
3513 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3514 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3515 S_028C44_DISABLE_START_OF_PRIM(1);
3518 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3519 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3522 struct radv_binning_settings
3523 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3525 struct radv_binning_settings settings
;
3526 if (pdev
->rad_info
.has_dedicated_vram
) {
3527 if (pdev
->rad_info
.num_render_backends
> 4) {
3528 settings
.context_states_per_bin
= 1;
3529 settings
.persistent_states_per_bin
= 1;
3531 settings
.context_states_per_bin
= 3;
3532 settings
.persistent_states_per_bin
= 8;
3534 settings
.fpovs_per_batch
= 63;
3536 /* The context states are affected by the scissor bug. */
3537 settings
.context_states_per_bin
= 6;
3538 /* 32 causes hangs for RAVEN. */
3539 settings
.persistent_states_per_bin
= 16;
3540 settings
.fpovs_per_batch
= 63;
3543 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3544 settings
.context_states_per_bin
= 1;
3550 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3551 struct radv_pipeline
*pipeline
,
3552 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3553 const struct radv_blend_state
*blend
)
3555 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3558 VkExtent2D bin_size
;
3559 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3560 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3561 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3562 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3564 unreachable("Unhandled generation for binning bin size calculation");
3566 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3567 struct radv_binning_settings settings
=
3568 radv_get_binning_settings(pipeline
->device
->physical_device
);
3570 bool disable_start_of_prim
= true;
3571 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3573 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3575 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3576 !ps
->info
.ps
.can_discard
&&
3577 !ps
->info
.ps
.writes_memory
&&
3578 blend
->cb_target_enabled_4bit
) {
3579 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3580 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3583 const uint32_t pa_sc_binner_cntl_0
=
3584 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3585 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3586 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3587 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3588 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3589 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3590 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3591 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3592 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3593 S_028C44_OPTIMAL_BIN_SELECTION(1);
3595 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3596 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3598 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3603 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3604 struct radv_pipeline
*pipeline
,
3605 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3606 const struct radv_graphics_pipeline_create_info
*extra
)
3608 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3609 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3610 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3611 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3612 struct radv_render_pass_attachment
*attachment
= NULL
;
3613 uint32_t db_depth_control
= 0;
3614 uint32_t db_render_control
= 0, db_render_override2
= 0;
3615 uint32_t db_render_override
= 0;
3617 if (subpass
->depth_stencil_attachment
)
3618 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3620 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3621 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3623 if (vkds
&& has_depth_attachment
) {
3624 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3625 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3626 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3627 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3629 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3630 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3632 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
)
3633 db_render_override2
|= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3636 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3637 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3638 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3640 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3643 if (attachment
&& extra
) {
3644 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3645 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3647 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->resummarize_enable
);
3648 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->depth_compress_disable
);
3649 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->stencil_compress_disable
);
3650 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3651 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3654 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3655 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3657 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3658 ps
->info
.ps
.writes_z
) {
3659 /* From VK_EXT_depth_range_unrestricted spec:
3661 * "The behavior described in Primitive Clipping still applies.
3662 * If depth clamping is disabled the depth values are still
3663 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3664 * depth clamping is enabled the above equation is ignored and
3665 * the depth values are instead clamped to the VkViewport
3666 * minDepth and maxDepth values, which in the case of this
3667 * extension can be outside of the 0.0 to 1.0 range."
3669 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3672 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3673 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3674 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3676 pipeline
->graphics
.db_depth_control
= db_depth_control
;
3680 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3681 struct radv_pipeline
*pipeline
,
3682 const struct radv_blend_state
*blend
)
3684 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3685 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3687 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3688 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3690 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3692 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3693 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3696 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3698 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3699 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3701 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3702 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3705 static const VkConservativeRasterizationModeEXT
3706 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3708 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3709 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3711 if (!conservative_raster
)
3712 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3713 return conservative_raster
->conservativeRasterizationMode
;
3717 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3718 struct radv_pipeline
*pipeline
,
3719 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3721 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3722 const VkConservativeRasterizationModeEXT mode
=
3723 radv_get_conservative_raster_mode(vkraster
);
3724 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3725 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3727 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3728 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3729 if (depth_clip_state
) {
3730 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3733 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3734 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3735 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3736 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3737 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3738 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3740 pipeline
->graphics
.pa_su_sc_mode_cntl
=
3741 S_028814_FACE(vkraster
->frontFace
) |
3742 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3743 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3744 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3745 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3746 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3747 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3748 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3749 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0);
3751 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
,
3752 S_028BDC_DX10_DIAMOND_TEST_ENA(1));
3754 /* Conservative rasterization. */
3755 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3756 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3758 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3759 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3760 S_028804_OVERRASTERIZATION_AMOUNT(4);
3762 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3763 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3764 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3766 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3767 pa_sc_conservative_rast
|=
3768 S_028C4C_OVER_RAST_ENABLE(1) |
3769 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3770 S_028C4C_UNDER_RAST_ENABLE(0) |
3771 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3772 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3774 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3775 pa_sc_conservative_rast
|=
3776 S_028C4C_OVER_RAST_ENABLE(0) |
3777 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3778 S_028C4C_UNDER_RAST_ENABLE(1) |
3779 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3780 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3784 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3785 pa_sc_conservative_rast
);
3790 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3791 struct radv_pipeline
*pipeline
)
3793 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3795 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3796 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3797 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3799 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3800 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3801 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3802 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3804 /* The exclusion bits can be set to improve rasterization efficiency
3805 * if no sample lies on the pixel boundary (-8 sample offset). It's
3806 * currently always TRUE because the driver doesn't support 16 samples.
3808 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3809 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3810 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3811 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3813 /* GFX9: Flush DFSM when the AA mode changes. */
3814 if (pipeline
->device
->dfsm_allowed
) {
3815 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3816 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3821 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3822 struct radv_pipeline
*pipeline
)
3824 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3825 const struct radv_shader_variant
*vs
=
3826 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3827 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3828 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3829 unsigned vgt_primitiveid_en
= 0;
3830 uint32_t vgt_gs_mode
= 0;
3832 if (radv_pipeline_has_ngg(pipeline
))
3835 if (radv_pipeline_has_gs(pipeline
)) {
3836 const struct radv_shader_variant
*gs
=
3837 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3839 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3840 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3841 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3842 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3843 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3846 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3847 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3851 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3852 struct radeon_cmdbuf
*cs
,
3853 struct radv_pipeline
*pipeline
,
3854 struct radv_shader_variant
*shader
)
3856 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3858 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3859 radeon_emit(cs
, va
>> 8);
3860 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3861 radeon_emit(cs
, shader
->config
.rsrc1
);
3862 radeon_emit(cs
, shader
->config
.rsrc2
);
3864 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3865 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3866 clip_dist_mask
= outinfo
->clip_dist_mask
;
3867 cull_dist_mask
= outinfo
->cull_dist_mask
;
3868 total_mask
= clip_dist_mask
| cull_dist_mask
;
3869 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3870 outinfo
->writes_layer
||
3871 outinfo
->writes_viewport_index
;
3872 unsigned spi_vs_out_config
, nparams
;
3874 /* VS is required to export at least one param. */
3875 nparams
= MAX2(outinfo
->param_exports
, 1);
3876 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3878 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3879 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3882 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3884 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3885 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3886 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3887 V_02870C_SPI_SHADER_4COMP
:
3888 V_02870C_SPI_SHADER_NONE
) |
3889 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3890 V_02870C_SPI_SHADER_4COMP
:
3891 V_02870C_SPI_SHADER_NONE
) |
3892 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3893 V_02870C_SPI_SHADER_4COMP
:
3894 V_02870C_SPI_SHADER_NONE
));
3896 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3897 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3898 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3899 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3900 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3901 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3902 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3903 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3904 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3905 cull_dist_mask
<< 8 |
3908 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3909 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3910 outinfo
->writes_viewport_index
);
3914 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3915 struct radv_pipeline
*pipeline
,
3916 struct radv_shader_variant
*shader
)
3918 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3920 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3921 radeon_emit(cs
, va
>> 8);
3922 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3923 radeon_emit(cs
, shader
->config
.rsrc1
);
3924 radeon_emit(cs
, shader
->config
.rsrc2
);
3928 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3929 struct radv_pipeline
*pipeline
,
3930 struct radv_shader_variant
*shader
,
3931 const struct radv_tessellation_state
*tess
)
3933 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3934 uint32_t rsrc2
= shader
->config
.rsrc2
;
3936 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3937 radeon_emit(cs
, va
>> 8);
3938 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3940 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3941 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3942 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3943 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3945 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3946 radeon_emit(cs
, shader
->config
.rsrc1
);
3947 radeon_emit(cs
, rsrc2
);
3951 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3952 struct radeon_cmdbuf
*cs
,
3953 struct radv_pipeline
*pipeline
,
3954 struct radv_shader_variant
*shader
)
3956 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3957 gl_shader_stage es_type
=
3958 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3959 struct radv_shader_variant
*es
=
3960 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3961 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3963 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3964 radeon_emit(cs
, va
>> 8);
3965 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3966 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3967 radeon_emit(cs
, shader
->config
.rsrc1
);
3968 radeon_emit(cs
, shader
->config
.rsrc2
);
3970 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3971 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3972 clip_dist_mask
= outinfo
->clip_dist_mask
;
3973 cull_dist_mask
= outinfo
->cull_dist_mask
;
3974 total_mask
= clip_dist_mask
| cull_dist_mask
;
3975 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3976 outinfo
->writes_layer
||
3977 outinfo
->writes_viewport_index
;
3978 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3979 (es
&& es
->info
.uses_prim_id
);
3980 bool break_wave_at_eoi
= false;
3984 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3985 struct radv_shader_variant
*gs
=
3986 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3988 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3989 break_wave_at_eoi
= true;
3992 nparams
= MAX2(outinfo
->param_exports
, 1);
3993 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3994 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3995 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3997 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3998 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3999 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
4000 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
4001 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
4002 V_02870C_SPI_SHADER_4COMP
:
4003 V_02870C_SPI_SHADER_NONE
) |
4004 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
4005 V_02870C_SPI_SHADER_4COMP
:
4006 V_02870C_SPI_SHADER_NONE
) |
4007 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
4008 V_02870C_SPI_SHADER_4COMP
:
4009 V_02870C_SPI_SHADER_NONE
));
4011 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
4012 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
4013 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
4014 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
4015 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
4016 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
4017 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
4018 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
4019 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
4020 cull_dist_mask
<< 8 |
4023 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
4024 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
4025 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
4027 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4028 ngg_state
->vgt_esgs_ring_itemsize
);
4030 /* NGG specific registers. */
4031 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4032 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
4034 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4035 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
4036 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
4037 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
4038 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
4039 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
4040 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4041 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4042 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4043 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4044 S_028B90_CNT(gs_num_invocations
) |
4045 S_028B90_ENABLE(gs_num_invocations
> 1) |
4046 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4048 /* User edge flags are set by the pos exports. If user edge flags are
4049 * not used, we must use hw-generated edge flags and pass them via
4050 * the prim export to prevent drawing lines on internal edges of
4051 * decomposed primitives (such as quads) with polygon mode = lines.
4053 * TODO: We should combine hw-generated edge flags with user edge
4054 * flags in the shader.
4056 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4057 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4058 !radv_pipeline_has_gs(pipeline
)) |
4059 /* Reuse for NGG. */
4060 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
? 30 : 0));
4062 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4063 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4064 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4066 /* Bug workaround for a possible hang with non-tessellation cases.
4067 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4069 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4071 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
4072 !radv_pipeline_has_tess(pipeline
) &&
4073 ngg_state
->hw_max_esverts
!= 256) {
4074 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4076 if (ngg_state
->hw_max_esverts
> 5) {
4077 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4081 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4085 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4086 struct radv_pipeline
*pipeline
,
4087 struct radv_shader_variant
*shader
,
4088 const struct radv_tessellation_state
*tess
)
4090 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4092 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4093 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4095 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4096 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
4098 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
4101 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4102 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4103 radeon_emit(cs
, va
>> 8);
4104 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4106 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4107 radeon_emit(cs
, va
>> 8);
4108 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4111 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4112 radeon_emit(cs
, shader
->config
.rsrc1
);
4113 radeon_emit(cs
, hs_rsrc2
);
4115 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4116 radeon_emit(cs
, va
>> 8);
4117 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4118 radeon_emit(cs
, shader
->config
.rsrc1
);
4119 radeon_emit(cs
, shader
->config
.rsrc2
);
4124 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4125 struct radeon_cmdbuf
*cs
,
4126 struct radv_pipeline
*pipeline
,
4127 const struct radv_tessellation_state
*tess
)
4129 struct radv_shader_variant
*vs
;
4131 /* Skip shaders merged into HS/GS */
4132 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4136 if (vs
->info
.vs
.as_ls
)
4137 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4138 else if (vs
->info
.vs
.as_es
)
4139 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4140 else if (vs
->info
.is_ngg
)
4141 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4143 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4147 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4148 struct radeon_cmdbuf
*cs
,
4149 struct radv_pipeline
*pipeline
,
4150 const struct radv_tessellation_state
*tess
)
4152 if (!radv_pipeline_has_tess(pipeline
))
4155 struct radv_shader_variant
*tes
, *tcs
;
4157 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4158 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4161 if (tes
->info
.is_ngg
) {
4162 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4163 } else if (tes
->info
.tes
.as_es
)
4164 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4166 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4169 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4171 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4174 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4175 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4176 tess
->ls_hs_config
);
4178 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4179 tess
->ls_hs_config
);
4181 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4182 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4183 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4184 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4185 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4186 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4191 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4192 struct radeon_cmdbuf
*cs
,
4193 struct radv_pipeline
*pipeline
,
4194 struct radv_shader_variant
*gs
)
4196 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4197 unsigned gs_max_out_vertices
;
4198 uint8_t *num_components
;
4203 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4204 max_stream
= gs
->info
.gs
.max_stream
;
4205 num_components
= gs
->info
.gs
.num_stream_output_components
;
4207 offset
= num_components
[0] * gs_max_out_vertices
;
4209 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4210 radeon_emit(ctx_cs
, offset
);
4211 if (max_stream
>= 1)
4212 offset
+= num_components
[1] * gs_max_out_vertices
;
4213 radeon_emit(ctx_cs
, offset
);
4214 if (max_stream
>= 2)
4215 offset
+= num_components
[2] * gs_max_out_vertices
;
4216 radeon_emit(ctx_cs
, offset
);
4217 if (max_stream
>= 3)
4218 offset
+= num_components
[3] * gs_max_out_vertices
;
4219 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4221 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4222 radeon_emit(ctx_cs
, num_components
[0]);
4223 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4224 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4225 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4227 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4228 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4229 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4230 S_028B90_ENABLE(gs_num_invocations
> 0));
4232 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4233 gs_state
->vgt_esgs_ring_itemsize
);
4235 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4237 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4238 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4239 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4240 radeon_emit(cs
, va
>> 8);
4241 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4243 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4244 radeon_emit(cs
, va
>> 8);
4245 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4248 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4249 radeon_emit(cs
, gs
->config
.rsrc1
);
4250 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4252 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4253 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4255 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4256 radeon_emit(cs
, va
>> 8);
4257 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4258 radeon_emit(cs
, gs
->config
.rsrc1
);
4259 radeon_emit(cs
, gs
->config
.rsrc2
);
4262 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4266 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4267 struct radeon_cmdbuf
*cs
,
4268 struct radv_pipeline
*pipeline
)
4270 struct radv_shader_variant
*gs
;
4272 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4276 if (gs
->info
.is_ngg
)
4277 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4279 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4281 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4282 gs
->info
.gs
.vertices_out
);
4285 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4286 bool explicit, bool float16
)
4288 uint32_t ps_input_cntl
;
4289 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4290 ps_input_cntl
= S_028644_OFFSET(offset
);
4291 if (flat_shade
|| explicit)
4292 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4294 /* Force parameter cache to be read in passthrough
4297 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4300 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4301 S_028644_ATTR0_VALID(1);
4304 /* The input is a DEFAULT_VAL constant. */
4305 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4306 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4307 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4308 ps_input_cntl
= S_028644_OFFSET(0x20) |
4309 S_028644_DEFAULT_VAL(offset
);
4311 return ps_input_cntl
;
4315 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4316 struct radv_pipeline
*pipeline
)
4318 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4319 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4320 uint32_t ps_input_cntl
[32];
4322 unsigned ps_offset
= 0;
4324 if (ps
->info
.ps
.prim_id_input
) {
4325 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4326 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4327 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4332 if (ps
->info
.ps
.layer_input
||
4333 ps
->info
.needs_multiview_view_index
) {
4334 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4335 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4336 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4338 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4342 if (ps
->info
.ps
.viewport_index_input
) {
4343 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VIEWPORT
];
4344 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4345 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4347 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4351 if (ps
->info
.ps
.has_pcoord
) {
4353 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4354 ps_input_cntl
[ps_offset
] = val
;
4358 if (ps
->info
.ps
.num_input_clips_culls
) {
4361 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4362 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4363 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4367 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4368 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4369 ps
->info
.ps
.num_input_clips_culls
> 4) {
4370 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4375 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4380 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4383 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4384 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4385 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4390 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4391 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4392 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4394 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4399 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4400 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4401 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4407 radv_compute_db_shader_control(const struct radv_device
*device
,
4408 const struct radv_pipeline
*pipeline
,
4409 const struct radv_shader_variant
*ps
)
4411 unsigned conservative_z_export
= V_02880C_EXPORT_ANY_Z
;
4413 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4414 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4416 z_order
= V_02880C_LATE_Z
;
4418 if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_GREATER
)
4419 conservative_z_export
= V_02880C_EXPORT_GREATER_THAN_Z
;
4420 else if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_LESS
)
4421 conservative_z_export
= V_02880C_EXPORT_LESS_THAN_Z
;
4423 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4424 !device
->physical_device
->rad_info
.rbplus_allowed
;
4426 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4427 * but this appears to break Project Cars (DXVK). See
4428 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4430 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4432 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4433 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4434 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4435 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4436 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export
) |
4437 S_02880C_Z_ORDER(z_order
) |
4438 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4439 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4440 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4441 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4442 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4446 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4447 struct radeon_cmdbuf
*cs
,
4448 struct radv_pipeline
*pipeline
)
4450 struct radv_shader_variant
*ps
;
4452 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4454 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4455 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4457 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4458 radeon_emit(cs
, va
>> 8);
4459 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4460 radeon_emit(cs
, ps
->config
.rsrc1
);
4461 radeon_emit(cs
, ps
->config
.rsrc2
);
4463 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4464 radv_compute_db_shader_control(pipeline
->device
,
4467 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4468 ps
->config
.spi_ps_input_ena
);
4470 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4471 ps
->config
.spi_ps_input_addr
);
4473 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4474 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4475 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4477 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4479 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4480 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4481 ps
->info
.ps
.writes_stencil
,
4482 ps
->info
.ps
.writes_sample_mask
));
4484 if (pipeline
->device
->dfsm_allowed
) {
4485 /* optimise this? */
4486 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4487 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4492 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4493 struct radv_pipeline
*pipeline
)
4495 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4496 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4499 unsigned vtx_reuse_depth
= 30;
4500 if (radv_pipeline_has_tess(pipeline
) &&
4501 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4502 vtx_reuse_depth
= 14;
4504 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4505 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4509 radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf
*ctx_cs
,
4510 const struct radv_pipeline
*pipeline
)
4512 uint32_t stages
= 0;
4513 if (radv_pipeline_has_tess(pipeline
)) {
4514 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4515 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4517 if (radv_pipeline_has_gs(pipeline
))
4518 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4520 else if (radv_pipeline_has_ngg(pipeline
))
4521 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4523 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4524 } else if (radv_pipeline_has_gs(pipeline
)) {
4525 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4527 } else if (radv_pipeline_has_ngg(pipeline
)) {
4528 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4531 if (radv_pipeline_has_ngg(pipeline
)) {
4532 stages
|= S_028B54_PRIMGEN_EN(1);
4533 if (pipeline
->streamout_shader
)
4534 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4535 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4536 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4537 } else if (radv_pipeline_has_gs(pipeline
)) {
4538 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4541 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4542 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4544 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4545 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4547 if (radv_pipeline_has_tess(pipeline
))
4548 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4550 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4551 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4552 if (pipeline
->gs_copy_shader
)
4553 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4554 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4555 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4556 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4557 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4559 if (radv_pipeline_has_ngg(pipeline
))
4562 /* legacy GS only supports Wave64 */
4563 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4564 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4565 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4568 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
4572 radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf
*ctx_cs
,
4573 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4575 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4576 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4577 uint32_t cliprect_rule
= 0;
4579 if (!discard_rectangle_info
) {
4580 cliprect_rule
= 0xffff;
4582 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4583 /* Interpret i as a bitmask, and then set the bit in
4584 * the mask if that combination of rectangles in which
4585 * the pixel is contained should pass the cliprect
4588 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4590 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4594 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4598 cliprect_rule
|= 1u << i
;
4602 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, cliprect_rule
);
4606 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4607 struct radv_pipeline
*pipeline
,
4608 const struct radv_tessellation_state
*tess
)
4610 bool break_wave_at_eoi
= false;
4611 unsigned primgroup_size
;
4612 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4614 if (radv_pipeline_has_tess(pipeline
)) {
4615 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4616 } else if (radv_pipeline_has_gs(pipeline
)) {
4617 const struct gfx9_gs_info
*gs_state
=
4618 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4619 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4620 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4622 primgroup_size
= 128; /* recommended without a GS and tess */
4625 if (radv_pipeline_has_tess(pipeline
)) {
4626 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4627 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4628 break_wave_at_eoi
= true;
4631 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4632 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4633 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4634 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4635 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4639 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4640 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4641 const struct radv_graphics_pipeline_create_info
*extra
,
4642 const struct radv_blend_state
*blend
,
4643 const struct radv_tessellation_state
*tess
,
4646 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4647 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4650 ctx_cs
->max_dw
= 256;
4651 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4652 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4654 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4655 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4656 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4657 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4658 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4659 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4660 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4661 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4662 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4663 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4664 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4665 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4666 radv_pipeline_generate_vgt_shader_config(ctx_cs
, pipeline
);
4667 radv_pipeline_generate_cliprect_rule(ctx_cs
, pCreateInfo
);
4669 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4670 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4672 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4674 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4676 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4677 assert(cs
->cdw
<= cs
->max_dw
);
4680 static struct radv_ia_multi_vgt_param_helpers
4681 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4682 const struct radv_tessellation_state
*tess
)
4684 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4685 const struct radv_device
*device
= pipeline
->device
;
4687 if (radv_pipeline_has_tess(pipeline
))
4688 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4689 else if (radv_pipeline_has_gs(pipeline
))
4690 ia_multi_vgt_param
.primgroup_size
= 64;
4692 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4694 /* GS requirement. */
4695 ia_multi_vgt_param
.partial_es_wave
= false;
4696 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4697 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4698 ia_multi_vgt_param
.partial_es_wave
= true;
4700 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4701 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4702 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4703 if (radv_pipeline_has_gs(pipeline
) &&
4704 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4705 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4706 if (radv_pipeline_has_tess(pipeline
)) {
4707 /* SWITCH_ON_EOI must be set if PrimID is used. */
4708 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4709 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4710 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4713 ia_multi_vgt_param
.partial_vs_wave
= false;
4714 if (radv_pipeline_has_tess(pipeline
)) {
4715 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4716 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4717 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4718 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4719 radv_pipeline_has_gs(pipeline
))
4720 ia_multi_vgt_param
.partial_vs_wave
= true;
4721 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4722 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4723 if (radv_pipeline_has_gs(pipeline
)) {
4724 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4725 ia_multi_vgt_param
.partial_es_wave
= true;
4727 ia_multi_vgt_param
.partial_vs_wave
= true;
4732 if (radv_pipeline_has_gs(pipeline
)) {
4733 /* On these chips there is the possibility of a hang if the
4734 * pipeline uses a GS and partial_vs_wave is not set.
4736 * This mostly does not hit 4-SE chips, as those typically set
4737 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4738 * with GS due to another workaround.
4740 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4742 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4743 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4744 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4745 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4746 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4747 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4748 ia_multi_vgt_param
.partial_vs_wave
= true;
4752 ia_multi_vgt_param
.base
=
4753 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4754 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4755 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4756 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4757 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4759 return ia_multi_vgt_param
;
4764 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4765 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4767 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4768 pCreateInfo
->pVertexInputState
;
4770 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4771 const VkVertexInputBindingDescription
*desc
=
4772 &vi_info
->pVertexBindingDescriptions
[i
];
4774 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4775 pipeline
->num_vertex_bindings
=
4776 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4780 static struct radv_shader_variant
*
4781 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4785 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4786 struct radv_shader_variant
*shader
=
4787 radv_get_shader(pipeline
, i
);
4789 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4797 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4798 struct radv_device
*device
,
4799 struct radv_pipeline_cache
*cache
,
4800 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4801 const struct radv_graphics_pipeline_create_info
*extra
)
4804 bool has_view_index
= false;
4806 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
4807 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
4808 if (subpass
->view_mask
)
4809 has_view_index
= true;
4811 pipeline
->device
= device
;
4812 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4813 assert(pipeline
->layout
);
4815 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4817 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4818 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4819 radv_init_feedback(creation_feedback
);
4821 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4823 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4824 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4825 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4826 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4827 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4828 if(creation_feedback
)
4829 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4832 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
4834 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
4835 pCreateInfo
->flags
, pipeline_feedback
,
4837 if (result
!= VK_SUCCESS
)
4840 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4841 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4844 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
4846 if (radv_pipeline_has_gs(pipeline
)) {
4847 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4848 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4849 } else if (radv_pipeline_has_tess(pipeline
)) {
4850 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
4851 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4853 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4854 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4856 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4858 if (extra
&& extra
->use_rectlist
) {
4859 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4860 pipeline
->graphics
.can_use_guardband
= true;
4861 if (radv_pipeline_has_ngg(pipeline
))
4862 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4864 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
4866 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
, extra
);
4868 /* Ensure that some export memory is always allocated, for two reasons:
4870 * 1) Correctness: The hardware ignores the EXEC mask if no export
4871 * memory is allocated, so KILL and alpha test do not work correctly
4873 * 2) Performance: Every shader needs at least a NULL export, even when
4874 * it writes no color/depth output. The NULL export instruction
4875 * stalls without this setting.
4877 * Don't add this to CB_SHADER_MASK.
4879 * GFX10 supports pixel shaders without exports by setting both the
4880 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4881 * instructions if any are present.
4883 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4884 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
4885 ps
->info
.ps
.can_discard
) &&
4886 !blend
.spi_shader_col_format
) {
4887 if (!ps
->info
.ps
.writes_z
&&
4888 !ps
->info
.ps
.writes_stencil
&&
4889 !ps
->info
.ps
.writes_sample_mask
)
4890 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
4893 blend
.cb_shader_mask
= ps
->info
.ps
.cb_shader_mask
;
4896 (extra
->custom_blend_mode
== V_028808_CB_ELIMINATE_FAST_CLEAR
||
4897 extra
->custom_blend_mode
== V_028808_CB_FMASK_DECOMPRESS
||
4898 extra
->custom_blend_mode
== V_028808_CB_DCC_DECOMPRESS
||
4899 extra
->custom_blend_mode
== V_028808_CB_RESOLVE
)) {
4900 /* According to the CB spec states, CB_SHADER_MASK should be
4901 * set to enable writes to all four channels of MRT0.
4903 blend
.cb_shader_mask
= 0xf;
4906 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4907 if (pipeline
->shaders
[i
]) {
4908 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
4912 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4913 struct radv_shader_variant
*gs
=
4914 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4916 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
4919 struct radv_tessellation_state tess
= {0};
4920 if (radv_pipeline_has_tess(pipeline
)) {
4921 pipeline
->graphics
.tess_patch_control_points
=
4922 pCreateInfo
->pTessellationState
->patchControlPoints
;
4923 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
4926 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
);
4928 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
4930 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
4931 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
4933 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
4934 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
4935 if (loc
->sgpr_idx
!= -1) {
4936 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
4937 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
4938 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
4939 pipeline
->graphics
.vtx_emit_num
= 3;
4941 pipeline
->graphics
.vtx_emit_num
= 2;
4944 /* Find the last vertex shader stage that eventually uses streamout. */
4945 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
4947 result
= radv_pipeline_scratch_init(device
, pipeline
);
4948 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, gs_out
);
4954 radv_graphics_pipeline_create(
4956 VkPipelineCache _cache
,
4957 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4958 const struct radv_graphics_pipeline_create_info
*extra
,
4959 const VkAllocationCallbacks
*pAllocator
,
4960 VkPipeline
*pPipeline
)
4962 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4963 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4964 struct radv_pipeline
*pipeline
;
4967 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
4968 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4969 if (pipeline
== NULL
)
4970 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4972 vk_object_base_init(&device
->vk
, &pipeline
->base
,
4973 VK_OBJECT_TYPE_PIPELINE
);
4975 result
= radv_pipeline_init(pipeline
, device
, cache
,
4976 pCreateInfo
, extra
);
4977 if (result
!= VK_SUCCESS
) {
4978 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
4982 *pPipeline
= radv_pipeline_to_handle(pipeline
);
4987 VkResult
radv_CreateGraphicsPipelines(
4989 VkPipelineCache pipelineCache
,
4991 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
4992 const VkAllocationCallbacks
* pAllocator
,
4993 VkPipeline
* pPipelines
)
4995 VkResult result
= VK_SUCCESS
;
4998 for (; i
< count
; i
++) {
5000 r
= radv_graphics_pipeline_create(_device
,
5003 NULL
, pAllocator
, &pPipelines
[i
]);
5004 if (r
!= VK_SUCCESS
) {
5006 pPipelines
[i
] = VK_NULL_HANDLE
;
5008 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5013 for (; i
< count
; ++i
)
5014 pPipelines
[i
] = VK_NULL_HANDLE
;
5021 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5023 struct radv_shader_variant
*compute_shader
;
5024 struct radv_device
*device
= pipeline
->device
;
5025 unsigned threads_per_threadgroup
;
5026 unsigned threadgroups_per_cu
= 1;
5027 unsigned waves_per_threadgroup
;
5028 unsigned max_waves_per_sh
= 0;
5031 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5032 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5034 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5035 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5037 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5038 radeon_emit(&pipeline
->cs
, va
>> 8);
5039 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5041 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5042 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5043 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5044 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5045 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5048 /* Calculate best compute resource limits. */
5049 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5050 compute_shader
->info
.cs
.block_size
[1] *
5051 compute_shader
->info
.cs
.block_size
[2];
5052 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5053 compute_shader
->info
.wave_size
);
5055 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5056 waves_per_threadgroup
== 1)
5057 threadgroups_per_cu
= 2;
5059 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5060 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5061 waves_per_threadgroup
,
5063 threadgroups_per_cu
));
5065 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5066 radeon_emit(&pipeline
->cs
,
5067 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5068 radeon_emit(&pipeline
->cs
,
5069 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5070 radeon_emit(&pipeline
->cs
,
5071 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5073 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5076 static struct radv_pipeline_key
5077 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5078 const VkComputePipelineCreateInfo
*pCreateInfo
)
5080 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5081 struct radv_pipeline_key key
;
5082 memset(&key
, 0, sizeof(key
));
5084 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5085 key
.optimisations_disabled
= 1;
5087 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5088 vk_find_struct_const(stage
->pNext
,
5089 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5091 if (subgroup_size
) {
5092 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5093 subgroup_size
->requiredSubgroupSize
== 64);
5094 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5100 static VkResult
radv_compute_pipeline_create(
5102 VkPipelineCache _cache
,
5103 const VkComputePipelineCreateInfo
* pCreateInfo
,
5104 const VkAllocationCallbacks
* pAllocator
,
5105 VkPipeline
* pPipeline
)
5107 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5108 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5109 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5110 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5111 struct radv_pipeline
*pipeline
;
5114 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5115 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5116 if (pipeline
== NULL
)
5117 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5119 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5120 VK_OBJECT_TYPE_PIPELINE
);
5122 pipeline
->device
= device
;
5123 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5124 assert(pipeline
->layout
);
5126 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5127 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5128 radv_init_feedback(creation_feedback
);
5130 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5131 if (creation_feedback
)
5132 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5134 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5136 struct radv_pipeline_key key
=
5137 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5139 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5140 pCreateInfo
->flags
, pipeline_feedback
,
5142 if (result
!= VK_SUCCESS
) {
5143 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5147 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5148 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5149 result
= radv_pipeline_scratch_init(device
, pipeline
);
5150 if (result
!= VK_SUCCESS
) {
5151 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5155 radv_compute_generate_pm4(pipeline
);
5157 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5162 VkResult
radv_CreateComputePipelines(
5164 VkPipelineCache pipelineCache
,
5166 const VkComputePipelineCreateInfo
* pCreateInfos
,
5167 const VkAllocationCallbacks
* pAllocator
,
5168 VkPipeline
* pPipelines
)
5170 VkResult result
= VK_SUCCESS
;
5173 for (; i
< count
; i
++) {
5175 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5177 pAllocator
, &pPipelines
[i
]);
5178 if (r
!= VK_SUCCESS
) {
5180 pPipelines
[i
] = VK_NULL_HANDLE
;
5182 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5187 for (; i
< count
; ++i
)
5188 pPipelines
[i
] = VK_NULL_HANDLE
;
5194 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5197 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5198 if (!pipeline
->shaders
[i
])
5201 if (i
== MESA_SHADER_GEOMETRY
&&
5202 !radv_pipeline_has_ngg(pipeline
)) {
5212 static struct radv_shader_variant
*
5213 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5215 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5216 if (!pipeline
->shaders
[i
])
5220 return pipeline
->shaders
[i
];
5225 if (i
== MESA_SHADER_GEOMETRY
&&
5226 !radv_pipeline_has_ngg(pipeline
)) {
5229 return pipeline
->gs_copy_shader
;
5239 /* Basically strlcpy (which does not exist on linux) specialized for
5241 static void desc_copy(char *desc
, const char *src
) {
5242 int len
= strlen(src
);
5243 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5244 memcpy(desc
, src
, len
);
5245 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5248 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5250 const VkPipelineInfoKHR
* pPipelineInfo
,
5251 uint32_t* pExecutableCount
,
5252 VkPipelineExecutablePropertiesKHR
* pProperties
)
5254 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5255 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5258 *pExecutableCount
= total_count
;
5262 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5263 for (unsigned i
= 0, executable_idx
= 0;
5264 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5265 if (!pipeline
->shaders
[i
])
5267 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5268 const char *name
= NULL
;
5269 const char *description
= NULL
;
5271 case MESA_SHADER_VERTEX
:
5272 name
= "Vertex Shader";
5273 description
= "Vulkan Vertex Shader";
5275 case MESA_SHADER_TESS_CTRL
:
5276 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5277 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5278 name
= "Vertex + Tessellation Control Shaders";
5279 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5281 name
= "Tessellation Control Shader";
5282 description
= "Vulkan Tessellation Control Shader";
5285 case MESA_SHADER_TESS_EVAL
:
5286 name
= "Tessellation Evaluation Shader";
5287 description
= "Vulkan Tessellation Evaluation Shader";
5289 case MESA_SHADER_GEOMETRY
:
5290 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5291 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5292 name
= "Tessellation Evaluation + Geometry Shaders";
5293 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5294 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5295 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5296 name
= "Vertex + Geometry Shader";
5297 description
= "Combined Vulkan Vertex and Geometry Shaders";
5299 name
= "Geometry Shader";
5300 description
= "Vulkan Geometry Shader";
5303 case MESA_SHADER_FRAGMENT
:
5304 name
= "Fragment Shader";
5305 description
= "Vulkan Fragment Shader";
5307 case MESA_SHADER_COMPUTE
:
5308 name
= "Compute Shader";
5309 description
= "Vulkan Compute Shader";
5313 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5314 desc_copy(pProperties
[executable_idx
].name
, name
);
5315 desc_copy(pProperties
[executable_idx
].description
, description
);
5318 if (i
== MESA_SHADER_GEOMETRY
&&
5319 !radv_pipeline_has_ngg(pipeline
)) {
5320 assert(pipeline
->gs_copy_shader
);
5321 if (executable_idx
>= count
)
5324 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5325 pProperties
[executable_idx
].subgroupSize
= 64;
5326 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5327 desc_copy(pProperties
[executable_idx
].description
,
5328 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5334 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5335 *pExecutableCount
= count
;
5339 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5341 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5342 uint32_t* pStatisticCount
,
5343 VkPipelineExecutableStatisticKHR
* pStatistics
)
5345 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5346 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5347 gl_shader_stage stage
;
5348 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5350 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5351 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5352 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5354 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5355 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5356 VkResult result
= VK_SUCCESS
;
5359 desc_copy(s
->name
, "SGPRs");
5360 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5361 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5362 s
->value
.u64
= shader
->config
.num_sgprs
;
5367 desc_copy(s
->name
, "VGPRs");
5368 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5369 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5370 s
->value
.u64
= shader
->config
.num_vgprs
;
5375 desc_copy(s
->name
, "Spilled SGPRs");
5376 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5377 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5378 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5383 desc_copy(s
->name
, "Spilled VGPRs");
5384 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5385 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5386 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5391 desc_copy(s
->name
, "PrivMem VGPRs");
5392 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5393 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5394 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5399 desc_copy(s
->name
, "Code size");
5400 desc_copy(s
->description
, "Code size in bytes");
5401 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5402 s
->value
.u64
= shader
->exec_size
;
5407 desc_copy(s
->name
, "LDS size");
5408 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5409 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5410 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5415 desc_copy(s
->name
, "Scratch size");
5416 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5417 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5418 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5423 desc_copy(s
->name
, "Subgroups per SIMD");
5424 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5425 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5426 s
->value
.u64
= max_waves
;
5430 if (shader
->statistics
) {
5431 for (unsigned i
= 0; i
< shader
->statistics
->count
; i
++) {
5432 struct radv_compiler_statistic_info
*info
= &shader
->statistics
->infos
[i
];
5433 uint32_t value
= shader
->statistics
->values
[i
];
5435 desc_copy(s
->name
, info
->name
);
5436 desc_copy(s
->description
, info
->desc
);
5437 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5438 s
->value
.u64
= value
;
5445 *pStatisticCount
= s
- pStatistics
;
5447 *pStatisticCount
= end
- pStatistics
;
5448 result
= VK_INCOMPLETE
;
5450 *pStatisticCount
= s
- pStatistics
;
5456 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5458 size_t total_size
= strlen(src
) + 1;
5461 *data_size
= total_size
;
5465 size_t size
= MIN2(total_size
, *data_size
);
5467 memcpy(data
, src
, size
);
5469 *((char*)data
+ size
- 1) = 0;
5470 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5473 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5475 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5476 uint32_t* pInternalRepresentationCount
,
5477 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5479 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5480 gl_shader_stage stage
;
5481 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5483 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5484 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5485 VkResult result
= VK_SUCCESS
;
5489 desc_copy(p
->name
, "NIR Shader(s)");
5490 desc_copy(p
->description
, "The optimized NIR shader(s)");
5491 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5492 result
= VK_INCOMPLETE
;
5499 if (pipeline
->device
->physical_device
->use_llvm
) {
5500 desc_copy(p
->name
, "LLVM IR");
5501 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5503 desc_copy(p
->name
, "ACO IR");
5504 desc_copy(p
->description
, "The ACO IR after some optimizations");
5506 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5507 result
= VK_INCOMPLETE
;
5514 desc_copy(p
->name
, "Assembly");
5515 desc_copy(p
->description
, "Final Assembly");
5516 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5517 result
= VK_INCOMPLETE
;
5521 if (!pInternalRepresentations
)
5522 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5524 result
= VK_INCOMPLETE
;
5525 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5527 *pInternalRepresentationCount
= p
- pInternalRepresentations
;