projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: Fix output for sparse MRTs.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
52
53 struct radv_blend_state {
54 uint32_t blend_enable_4bit;
55 uint32_t need_src_alpha;
56
57 uint32_t cb_color_control;
58 uint32_t cb_target_mask;
59 uint32_t cb_target_enabled_4bit;
60 uint32_t sx_mrt_blend_opt[8];
61 uint32_t cb_blend_control[8];
62
63 uint32_t spi_shader_col_format;
64 uint32_t cb_shader_mask;
65 uint32_t db_alpha_to_mask;
66
67 uint32_t commutative_4bit;
68
69 bool single_cb_enable;
70 bool mrt0_is_dual_src;
71 };
72
73 struct radv_dsa_order_invariance {
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
76 */
77 bool zs;
78
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
81 * fragments arrive.
82 */
83 bool pass_set;
84 };
85
86 struct radv_tessellation_state {
87 uint32_t ls_hs_config;
88 unsigned num_patches;
89 unsigned lds_size;
90 uint32_t tf_param;
91 };
92
93 struct radv_gs_state {
94 uint32_t vgt_gs_onchip_cntl;
95 uint32_t vgt_gs_max_prims_per_subgroup;
96 uint32_t vgt_esgs_ring_itemsize;
97 uint32_t lds_size;
98 };
99
100 static void
101 radv_pipeline_destroy(struct radv_device *device,
102 struct radv_pipeline *pipeline,
103 const VkAllocationCallbacks* allocator)
104 {
105 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
106 if (pipeline->shaders[i])
107 radv_shader_variant_destroy(device, pipeline->shaders[i]);
108
109 if (pipeline->gs_copy_shader)
110 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
111
112 if(pipeline->cs.buf)
113 free(pipeline->cs.buf);
114 vk_free2(&device->alloc, allocator, pipeline);
115 }
116
117 void radv_DestroyPipeline(
118 VkDevice _device,
119 VkPipeline _pipeline,
120 const VkAllocationCallbacks* pAllocator)
121 {
122 RADV_FROM_HANDLE(radv_device, device, _device);
123 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
124
125 if (!_pipeline)
126 return;
127
128 radv_pipeline_destroy(device, pipeline, pAllocator);
129 }
130
131 static uint32_t get_hash_flags(struct radv_device *device)
132 {
133 uint32_t hash_flags = 0;
134
135 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
136 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
137 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
138 hash_flags |= RADV_HASH_SHADER_SISCHED;
139 return hash_flags;
140 }
141
142 static VkResult
143 radv_pipeline_scratch_init(struct radv_device *device,
144 struct radv_pipeline *pipeline)
145 {
146 unsigned scratch_bytes_per_wave = 0;
147 unsigned max_waves = 0;
148 unsigned min_waves = 1;
149
150 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
151 if (pipeline->shaders[i]) {
152 unsigned max_stage_waves = device->scratch_waves;
153
154 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
155 pipeline->shaders[i]->config.scratch_bytes_per_wave);
156
157 max_stage_waves = MIN2(max_stage_waves,
158 4 * device->physical_device->rad_info.num_good_compute_units *
159 (256 / pipeline->shaders[i]->config.num_vgprs));
160 max_waves = MAX2(max_waves, max_stage_waves);
161 }
162 }
163
164 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
165 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
166 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
167 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
168 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
169 }
170
171 if (scratch_bytes_per_wave)
172 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
173
174 if (scratch_bytes_per_wave && max_waves < min_waves) {
175 /* Not really true at this moment, but will be true on first
176 * execution. Avoid having hanging shaders. */
177 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
178 }
179 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
180 pipeline->max_waves = max_waves;
181 return VK_SUCCESS;
182 }
183
184 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
185 {
186 switch (op) {
187 case VK_LOGIC_OP_CLEAR:
188 return V_028808_ROP3_CLEAR;
189 case VK_LOGIC_OP_AND:
190 return V_028808_ROP3_AND;
191 case VK_LOGIC_OP_AND_REVERSE:
192 return V_028808_ROP3_AND_REVERSE;
193 case VK_LOGIC_OP_COPY:
194 return V_028808_ROP3_COPY;
195 case VK_LOGIC_OP_AND_INVERTED:
196 return V_028808_ROP3_AND_INVERTED;
197 case VK_LOGIC_OP_NO_OP:
198 return V_028808_ROP3_NO_OP;
199 case VK_LOGIC_OP_XOR:
200 return V_028808_ROP3_XOR;
201 case VK_LOGIC_OP_OR:
202 return V_028808_ROP3_OR;
203 case VK_LOGIC_OP_NOR:
204 return V_028808_ROP3_NOR;
205 case VK_LOGIC_OP_EQUIVALENT:
206 return V_028808_ROP3_EQUIVALENT;
207 case VK_LOGIC_OP_INVERT:
208 return V_028808_ROP3_INVERT;
209 case VK_LOGIC_OP_OR_REVERSE:
210 return V_028808_ROP3_OR_REVERSE;
211 case VK_LOGIC_OP_COPY_INVERTED:
212 return V_028808_ROP3_COPY_INVERTED;
213 case VK_LOGIC_OP_OR_INVERTED:
214 return V_028808_ROP3_OR_INVERTED;
215 case VK_LOGIC_OP_NAND:
216 return V_028808_ROP3_NAND;
217 case VK_LOGIC_OP_SET:
218 return V_028808_ROP3_SET;
219 default:
220 unreachable("Unhandled logic op");
221 }
222 }
223
224
225 static uint32_t si_translate_blend_function(VkBlendOp op)
226 {
227 switch (op) {
228 case VK_BLEND_OP_ADD:
229 return V_028780_COMB_DST_PLUS_SRC;
230 case VK_BLEND_OP_SUBTRACT:
231 return V_028780_COMB_SRC_MINUS_DST;
232 case VK_BLEND_OP_REVERSE_SUBTRACT:
233 return V_028780_COMB_DST_MINUS_SRC;
234 case VK_BLEND_OP_MIN:
235 return V_028780_COMB_MIN_DST_SRC;
236 case VK_BLEND_OP_MAX:
237 return V_028780_COMB_MAX_DST_SRC;
238 default:
239 return 0;
240 }
241 }
242
243 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
244 {
245 switch (factor) {
246 case VK_BLEND_FACTOR_ZERO:
247 return V_028780_BLEND_ZERO;
248 case VK_BLEND_FACTOR_ONE:
249 return V_028780_BLEND_ONE;
250 case VK_BLEND_FACTOR_SRC_COLOR:
251 return V_028780_BLEND_SRC_COLOR;
252 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
253 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
254 case VK_BLEND_FACTOR_DST_COLOR:
255 return V_028780_BLEND_DST_COLOR;
256 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
257 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
258 case VK_BLEND_FACTOR_SRC_ALPHA:
259 return V_028780_BLEND_SRC_ALPHA;
260 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
261 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
262 case VK_BLEND_FACTOR_DST_ALPHA:
263 return V_028780_BLEND_DST_ALPHA;
264 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
265 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
266 case VK_BLEND_FACTOR_CONSTANT_COLOR:
267 return V_028780_BLEND_CONSTANT_COLOR;
268 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
269 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
270 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
271 return V_028780_BLEND_CONSTANT_ALPHA;
272 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
273 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
274 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
275 return V_028780_BLEND_SRC_ALPHA_SATURATE;
276 case VK_BLEND_FACTOR_SRC1_COLOR:
277 return V_028780_BLEND_SRC1_COLOR;
278 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
279 return V_028780_BLEND_INV_SRC1_COLOR;
280 case VK_BLEND_FACTOR_SRC1_ALPHA:
281 return V_028780_BLEND_SRC1_ALPHA;
282 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
283 return V_028780_BLEND_INV_SRC1_ALPHA;
284 default:
285 return 0;
286 }
287 }
288
289 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
290 {
291 switch (op) {
292 case VK_BLEND_OP_ADD:
293 return V_028760_OPT_COMB_ADD;
294 case VK_BLEND_OP_SUBTRACT:
295 return V_028760_OPT_COMB_SUBTRACT;
296 case VK_BLEND_OP_REVERSE_SUBTRACT:
297 return V_028760_OPT_COMB_REVSUBTRACT;
298 case VK_BLEND_OP_MIN:
299 return V_028760_OPT_COMB_MIN;
300 case VK_BLEND_OP_MAX:
301 return V_028760_OPT_COMB_MAX;
302 default:
303 return V_028760_OPT_COMB_BLEND_DISABLED;
304 }
305 }
306
307 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
308 {
309 switch (factor) {
310 case VK_BLEND_FACTOR_ZERO:
311 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
312 case VK_BLEND_FACTOR_ONE:
313 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
314 case VK_BLEND_FACTOR_SRC_COLOR:
315 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
316 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
317 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
318 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
319 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
320 case VK_BLEND_FACTOR_SRC_ALPHA:
321 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
322 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
323 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
325 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
326 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
327 default:
328 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
329 }
330 }
331
332 /**
333 * Get rid of DST in the blend factors by commuting the operands:
334 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
335 */
336 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
337 unsigned *dst_factor, unsigned expected_dst,
338 unsigned replacement_src)
339 {
340 if (*src_factor == expected_dst &&
341 *dst_factor == VK_BLEND_FACTOR_ZERO) {
342 *src_factor = VK_BLEND_FACTOR_ZERO;
343 *dst_factor = replacement_src;
344
345 /* Commuting the operands requires reversing subtractions. */
346 if (*func == VK_BLEND_OP_SUBTRACT)
347 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
348 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
349 *func = VK_BLEND_OP_SUBTRACT;
350 }
351 }
352
353 static bool si_blend_factor_uses_dst(unsigned factor)
354 {
355 return factor == VK_BLEND_FACTOR_DST_COLOR ||
356 factor == VK_BLEND_FACTOR_DST_ALPHA ||
357 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
358 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
359 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
360 }
361
362 static bool is_dual_src(VkBlendFactor factor)
363 {
364 switch (factor) {
365 case VK_BLEND_FACTOR_SRC1_COLOR:
366 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
367 case VK_BLEND_FACTOR_SRC1_ALPHA:
368 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
369 return true;
370 default:
371 return false;
372 }
373 }
374
375 static unsigned si_choose_spi_color_format(VkFormat vk_format,
376 bool blend_enable,
377 bool blend_need_alpha)
378 {
379 const struct vk_format_description *desc = vk_format_description(vk_format);
380 unsigned format, ntype, swap;
381
382 /* Alpha is needed for alpha-to-coverage.
383 * Blending may be with or without alpha.
384 */
385 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
386 unsigned alpha = 0; /* exports alpha, but may not support blending */
387 unsigned blend = 0; /* supports blending, but may not export alpha */
388 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
389
390 format = radv_translate_colorformat(vk_format);
391 ntype = radv_translate_color_numformat(vk_format, desc,
392 vk_format_get_first_non_void_channel(vk_format));
393 swap = radv_translate_colorswap(vk_format, false);
394
395 /* Choose the SPI color formats. These are required values for Stoney/RB+.
396 * Other chips have multiple choices, though they are not necessarily better.
397 */
398 switch (format) {
399 case V_028C70_COLOR_5_6_5:
400 case V_028C70_COLOR_1_5_5_5:
401 case V_028C70_COLOR_5_5_5_1:
402 case V_028C70_COLOR_4_4_4_4:
403 case V_028C70_COLOR_10_11_11:
404 case V_028C70_COLOR_11_11_10:
405 case V_028C70_COLOR_8:
406 case V_028C70_COLOR_8_8:
407 case V_028C70_COLOR_8_8_8_8:
408 case V_028C70_COLOR_10_10_10_2:
409 case V_028C70_COLOR_2_10_10_10:
410 if (ntype == V_028C70_NUMBER_UINT)
411 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
412 else if (ntype == V_028C70_NUMBER_SINT)
413 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
414 else
415 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
416 break;
417
418 case V_028C70_COLOR_16:
419 case V_028C70_COLOR_16_16:
420 case V_028C70_COLOR_16_16_16_16:
421 if (ntype == V_028C70_NUMBER_UNORM ||
422 ntype == V_028C70_NUMBER_SNORM) {
423 /* UNORM16 and SNORM16 don't support blending */
424 if (ntype == V_028C70_NUMBER_UNORM)
425 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
426 else
427 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
428
429 /* Use 32 bits per channel for blending. */
430 if (format == V_028C70_COLOR_16) {
431 if (swap == V_028C70_SWAP_STD) { /* R */
432 blend = V_028714_SPI_SHADER_32_R;
433 blend_alpha = V_028714_SPI_SHADER_32_AR;
434 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
435 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
436 else
437 assert(0);
438 } else if (format == V_028C70_COLOR_16_16) {
439 if (swap == V_028C70_SWAP_STD) { /* RG */
440 blend = V_028714_SPI_SHADER_32_GR;
441 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
442 } else if (swap == V_028C70_SWAP_ALT) /* RA */
443 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
444 else
445 assert(0);
446 } else /* 16_16_16_16 */
447 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
448 } else if (ntype == V_028C70_NUMBER_UINT)
449 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
450 else if (ntype == V_028C70_NUMBER_SINT)
451 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
452 else if (ntype == V_028C70_NUMBER_FLOAT)
453 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
454 else
455 assert(0);
456 break;
457
458 case V_028C70_COLOR_32:
459 if (swap == V_028C70_SWAP_STD) { /* R */
460 blend = normal = V_028714_SPI_SHADER_32_R;
461 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
462 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
463 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
464 else
465 assert(0);
466 break;
467
468 case V_028C70_COLOR_32_32:
469 if (swap == V_028C70_SWAP_STD) { /* RG */
470 blend = normal = V_028714_SPI_SHADER_32_GR;
471 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
472 } else if (swap == V_028C70_SWAP_ALT) /* RA */
473 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
474 else
475 assert(0);
476 break;
477
478 case V_028C70_COLOR_32_32_32_32:
479 case V_028C70_COLOR_8_24:
480 case V_028C70_COLOR_24_8:
481 case V_028C70_COLOR_X24_8_32_FLOAT:
482 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
483 break;
484
485 default:
486 unreachable("unhandled blend format");
487 }
488
489 if (blend_enable && blend_need_alpha)
490 return blend_alpha;
491 else if(blend_need_alpha)
492 return alpha;
493 else if(blend_enable)
494 return blend;
495 else
496 return normal;
497 }
498
499 static void
500 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
501 const VkGraphicsPipelineCreateInfo *pCreateInfo,
502 struct radv_blend_state *blend)
503 {
504 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
505 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
506 unsigned col_format = 0;
507 unsigned num_targets;
508
509 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
510 unsigned cf;
511
512 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
513 cf = V_028714_SPI_SHADER_ZERO;
514 } else {
515 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
516 bool blend_enable =
517 blend->blend_enable_4bit & (0xfu << (i * 4));
518
519 cf = si_choose_spi_color_format(attachment->format,
520 blend_enable,
521 blend->need_src_alpha & (1 << i));
522 }
523
524 col_format |= cf << (4 * i);
525 }
526
527 /* If the i-th target format is set, all previous target formats must
528 * be non-zero to avoid hangs.
529 */
530 num_targets = (util_last_bit(col_format) + 3) / 4;
531 for (unsigned i = 0; i < num_targets; i++) {
532 if (!(col_format & (0xf << (i * 4)))) {
533 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
534 }
535 }
536
537 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
538
539 if (blend->mrt0_is_dual_src)
540 col_format |= (col_format & 0xf) << 4;
541 blend->spi_shader_col_format = col_format;
542 }
543
544 static bool
545 format_is_int8(VkFormat format)
546 {
547 const struct vk_format_description *desc = vk_format_description(format);
548 int channel = vk_format_get_first_non_void_channel(format);
549
550 return channel >= 0 && desc->channel[channel].pure_integer &&
551 desc->channel[channel].size == 8;
552 }
553
554 static bool
555 format_is_int10(VkFormat format)
556 {
557 const struct vk_format_description *desc = vk_format_description(format);
558
559 if (desc->nr_channels != 4)
560 return false;
561 for (unsigned i = 0; i < 4; i++) {
562 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
563 return true;
564 }
565 return false;
566 }
567
568 unsigned radv_format_meta_fs_key(VkFormat format)
569 {
570 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
571 bool is_int8 = format_is_int8(format);
572 bool is_int10 = format_is_int10(format);
573
574 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
575 }
576
577 static void
578 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
579 unsigned *is_int8, unsigned *is_int10)
580 {
581 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
582 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
583 *is_int8 = 0;
584 *is_int10 = 0;
585
586 for (unsigned i = 0; i < subpass->color_count; ++i) {
587 struct radv_render_pass_attachment *attachment;
588
589 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
590 continue;
591
592 attachment = pass->attachments + subpass->color_attachments[i].attachment;
593
594 if (format_is_int8(attachment->format))
595 *is_int8 |= 1 << i;
596 if (format_is_int10(attachment->format))
597 *is_int10 |= 1 << i;
598 }
599 }
600
601 static void
602 radv_blend_check_commutativity(struct radv_blend_state *blend,
603 VkBlendOp op, VkBlendFactor src,
604 VkBlendFactor dst, unsigned chanmask)
605 {
606 /* Src factor is allowed when it does not depend on Dst. */
607 static const uint32_t src_allowed =
608 (1u << VK_BLEND_FACTOR_ONE) |
609 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
610 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
611 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
612 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
613 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
614 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
615 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
616 (1u << VK_BLEND_FACTOR_ZERO) |
617 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
618 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
619 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
623
624 if (dst == VK_BLEND_FACTOR_ONE &&
625 (src_allowed && (1u << src))) {
626 /* Addition is commutative, but floating point addition isn't
627 * associative: subtle changes can be introduced via different
628 * rounding. Be conservative, only enable for min and max.
629 */
630 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
631 blend->commutative_4bit |= chanmask;
632 }
633 }
634
635 static struct radv_blend_state
636 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
637 const VkGraphicsPipelineCreateInfo *pCreateInfo,
638 const struct radv_graphics_pipeline_create_info *extra)
639 {
640 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
641 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
642 struct radv_blend_state blend = {0};
643 unsigned mode = V_028808_CB_NORMAL;
644 int i;
645
646 if (!vkblend)
647 return blend;
648
649 if (extra && extra->custom_blend_mode) {
650 blend.single_cb_enable = true;
651 mode = extra->custom_blend_mode;
652 }
653 blend.cb_color_control = 0;
654 if (vkblend->logicOpEnable)
655 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
656 else
657 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
658
659 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
660 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
661 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
662 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
663
664 if (vkms && vkms->alphaToCoverageEnable) {
665 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
666 }
667
668 blend.cb_target_mask = 0;
669 for (i = 0; i < vkblend->attachmentCount; i++) {
670 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
671 unsigned blend_cntl = 0;
672 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
673 VkBlendOp eqRGB = att->colorBlendOp;
674 VkBlendFactor srcRGB = att->srcColorBlendFactor;
675 VkBlendFactor dstRGB = att->dstColorBlendFactor;
676 VkBlendOp eqA = att->alphaBlendOp;
677 VkBlendFactor srcA = att->srcAlphaBlendFactor;
678 VkBlendFactor dstA = att->dstAlphaBlendFactor;
679
680 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
681
682 if (!att->colorWriteMask)
683 continue;
684
685 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
686 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
687 if (!att->blendEnable) {
688 blend.cb_blend_control[i] = blend_cntl;
689 continue;
690 }
691
692 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
693 if (i == 0)
694 blend.mrt0_is_dual_src = true;
695
696 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
697 srcRGB = VK_BLEND_FACTOR_ONE;
698 dstRGB = VK_BLEND_FACTOR_ONE;
699 }
700 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
701 srcA = VK_BLEND_FACTOR_ONE;
702 dstA = VK_BLEND_FACTOR_ONE;
703 }
704
705 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
706 0x7 << (4 * i));
707 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
708 0x8 << (4 * i));
709
710 /* Blending optimizations for RB+.
711 * These transformations don't change the behavior.
712 *
713 * First, get rid of DST in the blend factors:
714 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
715 */
716 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
717 VK_BLEND_FACTOR_DST_COLOR,
718 VK_BLEND_FACTOR_SRC_COLOR);
719
720 si_blend_remove_dst(&eqA, &srcA, &dstA,
721 VK_BLEND_FACTOR_DST_COLOR,
722 VK_BLEND_FACTOR_SRC_COLOR);
723
724 si_blend_remove_dst(&eqA, &srcA, &dstA,
725 VK_BLEND_FACTOR_DST_ALPHA,
726 VK_BLEND_FACTOR_SRC_ALPHA);
727
728 /* Look up the ideal settings from tables. */
729 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
730 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
731 srcA_opt = si_translate_blend_opt_factor(srcA, true);
732 dstA_opt = si_translate_blend_opt_factor(dstA, true);
733
734 /* Handle interdependencies. */
735 if (si_blend_factor_uses_dst(srcRGB))
736 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
737 if (si_blend_factor_uses_dst(srcA))
738 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
739
740 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
741 (dstRGB == VK_BLEND_FACTOR_ZERO ||
742 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
743 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
744 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
745
746 /* Set the final value. */
747 blend.sx_mrt_blend_opt[i] =
748 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
749 S_028760_COLOR_DST_OPT(dstRGB_opt) |
750 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
751 S_028760_ALPHA_SRC_OPT(srcA_opt) |
752 S_028760_ALPHA_DST_OPT(dstA_opt) |
753 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
754 blend_cntl |= S_028780_ENABLE(1);
755
756 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
757 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
758 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
759 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
760 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
761 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
762 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
763 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
764 }
765 blend.cb_blend_control[i] = blend_cntl;
766
767 blend.blend_enable_4bit |= 0xfu << (i * 4);
768
769 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
770 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
771 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
772 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
773 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
774 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
775 blend.need_src_alpha |= 1 << i;
776 }
777 for (i = vkblend->attachmentCount; i < 8; i++) {
778 blend.cb_blend_control[i] = 0;
779 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
780 }
781
782 if (pipeline->device->physical_device->has_rbplus) {
783 /* Disable RB+ blend optimizations for dual source blending. */
784 if (blend.mrt0_is_dual_src) {
785 for (i = 0; i < 8; i++) {
786 blend.sx_mrt_blend_opt[i] =
787 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
788 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
789 }
790 }
791
792 /* RB+ doesn't work with dual source blending, logic op and
793 * RESOLVE.
794 */
795 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
796 mode == V_028808_CB_RESOLVE)
797 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
798 }
799
800 if (blend.cb_target_mask)
801 blend.cb_color_control |= S_028808_MODE(mode);
802 else
803 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
804
805 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
806 return blend;
807 }
808
809 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
810 {
811 switch (op) {
812 case VK_STENCIL_OP_KEEP:
813 return V_02842C_STENCIL_KEEP;
814 case VK_STENCIL_OP_ZERO:
815 return V_02842C_STENCIL_ZERO;
816 case VK_STENCIL_OP_REPLACE:
817 return V_02842C_STENCIL_REPLACE_TEST;
818 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
819 return V_02842C_STENCIL_ADD_CLAMP;
820 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
821 return V_02842C_STENCIL_SUB_CLAMP;
822 case VK_STENCIL_OP_INVERT:
823 return V_02842C_STENCIL_INVERT;
824 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
825 return V_02842C_STENCIL_ADD_WRAP;
826 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
827 return V_02842C_STENCIL_SUB_WRAP;
828 default:
829 return 0;
830 }
831 }
832
833 static uint32_t si_translate_fill(VkPolygonMode func)
834 {
835 switch(func) {
836 case VK_POLYGON_MODE_FILL:
837 return V_028814_X_DRAW_TRIANGLES;
838 case VK_POLYGON_MODE_LINE:
839 return V_028814_X_DRAW_LINES;
840 case VK_POLYGON_MODE_POINT:
841 return V_028814_X_DRAW_POINTS;
842 default:
843 assert(0);
844 return V_028814_X_DRAW_POINTS;
845 }
846 }
847
848 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
849 {
850 uint32_t num_samples = vkms->rasterizationSamples;
851 uint32_t ps_iter_samples = 1;
852
853 if (vkms->sampleShadingEnable) {
854 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
855 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
856 }
857 return ps_iter_samples;
858 }
859
860 static bool
861 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
862 {
863 return pCreateInfo->depthTestEnable &&
864 pCreateInfo->depthWriteEnable &&
865 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
866 }
867
868 static bool
869 radv_writes_stencil(const VkStencilOpState *state)
870 {
871 return state->writeMask &&
872 (state->failOp != VK_STENCIL_OP_KEEP ||
873 state->passOp != VK_STENCIL_OP_KEEP ||
874 state->depthFailOp != VK_STENCIL_OP_KEEP);
875 }
876
877 static bool
878 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
879 {
880 return pCreateInfo->stencilTestEnable &&
881 (radv_writes_stencil(&pCreateInfo->front) ||
882 radv_writes_stencil(&pCreateInfo->back));
883 }
884
885 static bool
886 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
887 {
888 return radv_is_depth_write_enabled(pCreateInfo) ||
889 radv_is_stencil_write_enabled(pCreateInfo);
890 }
891
892 static bool
893 radv_order_invariant_stencil_op(VkStencilOp op)
894 {
895 /* REPLACE is normally order invariant, except when the stencil
896 * reference value is written by the fragment shader. Tracking this
897 * interaction does not seem worth the effort, so be conservative.
898 */
899 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
900 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
901 op != VK_STENCIL_OP_REPLACE;
902 }
903
904 static bool
905 radv_order_invariant_stencil_state(const VkStencilOpState *state)
906 {
907 /* Compute whether, assuming Z writes are disabled, this stencil state
908 * is order invariant in the sense that the set of passing fragments as
909 * well as the final stencil buffer result does not depend on the order
910 * of fragments.
911 */
912 return !state->writeMask ||
913 /* The following assumes that Z writes are disabled. */
914 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
915 radv_order_invariant_stencil_op(state->passOp) &&
916 radv_order_invariant_stencil_op(state->depthFailOp)) ||
917 (state->compareOp == VK_COMPARE_OP_NEVER &&
918 radv_order_invariant_stencil_op(state->failOp));
919 }
920
921 static bool
922 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
923 struct radv_blend_state *blend,
924 const VkGraphicsPipelineCreateInfo *pCreateInfo)
925 {
926 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
927 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
928 unsigned colormask = blend->cb_target_enabled_4bit;
929
930 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
931 return false;
932
933 /* Be conservative if a logic operation is enabled with color buffers. */
934 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
935 return false;
936
937 /* Default depth/stencil invariance when no attachment is bound. */
938 struct radv_dsa_order_invariance dsa_order_invariant = {
939 .zs = true, .pass_set = true
940 };
941
942 if (pCreateInfo->pDepthStencilState &&
943 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
944 const VkPipelineDepthStencilStateCreateInfo *vkds =
945 pCreateInfo->pDepthStencilState;
946 struct radv_render_pass_attachment *attachment =
947 pass->attachments + subpass->depth_stencil_attachment.attachment;
948 bool has_stencil = vk_format_is_stencil(attachment->format);
949 struct radv_dsa_order_invariance order_invariance[2];
950 struct radv_shader_variant *ps =
951 pipeline->shaders[MESA_SHADER_FRAGMENT];
952
953 /* Compute depth/stencil order invariance in order to know if
954 * it's safe to enable out-of-order.
955 */
956 bool zfunc_is_ordered =
957 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
958 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
959 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
960 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
961 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
962
963 bool nozwrite_and_order_invariant_stencil =
964 !radv_is_ds_write_enabled(vkds) ||
965 (!radv_is_depth_write_enabled(vkds) &&
966 radv_order_invariant_stencil_state(&vkds->front) &&
967 radv_order_invariant_stencil_state(&vkds->back));
968
969 order_invariance[1].zs =
970 nozwrite_and_order_invariant_stencil ||
971 (!radv_is_stencil_write_enabled(vkds) &&
972 zfunc_is_ordered);
973 order_invariance[0].zs =
974 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
975
976 order_invariance[1].pass_set =
977 nozwrite_and_order_invariant_stencil ||
978 (!radv_is_stencil_write_enabled(vkds) &&
979 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
980 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
981 order_invariance[0].pass_set =
982 !radv_is_depth_write_enabled(vkds) ||
983 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
984 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
985
986 dsa_order_invariant = order_invariance[has_stencil];
987 if (!dsa_order_invariant.zs)
988 return false;
989
990 /* The set of PS invocations is always order invariant,
991 * except when early Z/S tests are requested.
992 */
993 if (ps &&
994 ps->info.info.ps.writes_memory &&
995 ps->info.fs.early_fragment_test &&
996 !dsa_order_invariant.pass_set)
997 return false;
998
999 /* Determine if out-of-order rasterization should be disabled
1000 * when occlusion queries are used.
1001 */
1002 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1003 !dsa_order_invariant.pass_set;
1004 }
1005
1006 /* No color buffers are enabled for writing. */
1007 if (!colormask)
1008 return true;
1009
1010 unsigned blendmask = colormask & blend->blend_enable_4bit;
1011
1012 if (blendmask) {
1013 /* Only commutative blending. */
1014 if (blendmask & ~blend->commutative_4bit)
1015 return false;
1016
1017 if (!dsa_order_invariant.pass_set)
1018 return false;
1019 }
1020
1021 if (colormask & ~blendmask)
1022 return false;
1023
1024 return true;
1025 }
1026
1027 static void
1028 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1029 struct radv_blend_state *blend,
1030 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1031 {
1032 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1033 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1034 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1035 bool out_of_order_rast = false;
1036 int ps_iter_samples = 1;
1037 uint32_t mask = 0xffff;
1038
1039 if (vkms)
1040 ms->num_samples = vkms->rasterizationSamples;
1041 else
1042 ms->num_samples = 1;
1043
1044 if (vkms)
1045 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1046 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1047 ps_iter_samples = ms->num_samples;
1048 }
1049
1050 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1051 ms->pa_sc_aa_config = 0;
1052 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1053 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1054 ms->pa_sc_mode_cntl_1 =
1055 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1056 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1057 /* always 1: */
1058 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1059 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1060 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1061 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1062 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1063 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1064 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1065 S_028A48_VPORT_SCISSOR_ENABLE(1);
1066
1067 if (ms->num_samples > 1) {
1068 unsigned log_samples = util_logbase2(ms->num_samples);
1069 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1070 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1071 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1072 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1073 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1074 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1075 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1076 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1077 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1078 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1079 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1080 if (ps_iter_samples > 1)
1081 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1082 }
1083
1084 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1085 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1086 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1087 /* Out-of-order rasterization is explicitly enabled by the
1088 * application.
1089 */
1090 out_of_order_rast = true;
1091 } else {
1092 /* Determine if the driver can enable out-of-order
1093 * rasterization internally.
1094 */
1095 out_of_order_rast =
1096 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1097 }
1098
1099 if (out_of_order_rast) {
1100 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
1101 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
1102 }
1103
1104 if (vkms && vkms->pSampleMask) {
1105 mask = vkms->pSampleMask[0] & 0xffff;
1106 }
1107
1108 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1109 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1110 }
1111
1112 static bool
1113 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1114 {
1115 switch (topology) {
1116 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1117 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1118 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1119 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1120 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1121 return false;
1122 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1123 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1124 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1125 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1126 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1127 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1128 return true;
1129 default:
1130 unreachable("unhandled primitive type");
1131 }
1132 }
1133
1134 static uint32_t
1135 si_translate_prim(enum VkPrimitiveTopology topology)
1136 {
1137 switch (topology) {
1138 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1139 return V_008958_DI_PT_POINTLIST;
1140 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1141 return V_008958_DI_PT_LINELIST;
1142 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1143 return V_008958_DI_PT_LINESTRIP;
1144 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1145 return V_008958_DI_PT_TRILIST;
1146 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1147 return V_008958_DI_PT_TRISTRIP;
1148 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1149 return V_008958_DI_PT_TRIFAN;
1150 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1151 return V_008958_DI_PT_LINELIST_ADJ;
1152 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1153 return V_008958_DI_PT_LINESTRIP_ADJ;
1154 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1155 return V_008958_DI_PT_TRILIST_ADJ;
1156 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1157 return V_008958_DI_PT_TRISTRIP_ADJ;
1158 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1159 return V_008958_DI_PT_PATCH;
1160 default:
1161 assert(0);
1162 return 0;
1163 }
1164 }
1165
1166 static uint32_t
1167 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1168 {
1169 switch (gl_prim) {
1170 case 0: /* GL_POINTS */
1171 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1172 case 1: /* GL_LINES */
1173 case 3: /* GL_LINE_STRIP */
1174 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1175 case 0x8E7A: /* GL_ISOLINES */
1176 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1177
1178 case 4: /* GL_TRIANGLES */
1179 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1180 case 5: /* GL_TRIANGLE_STRIP */
1181 case 7: /* GL_QUADS */
1182 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1183 default:
1184 assert(0);
1185 return 0;
1186 }
1187 }
1188
1189 static uint32_t
1190 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1191 {
1192 switch (topology) {
1193 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1194 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1195 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1196 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1197 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1198 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1199 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1200 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1201 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1202 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1203 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1206 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1207 default:
1208 assert(0);
1209 return 0;
1210 }
1211 }
1212
1213 static unsigned si_map_swizzle(unsigned swizzle)
1214 {
1215 switch (swizzle) {
1216 case VK_SWIZZLE_Y:
1217 return V_008F0C_SQ_SEL_Y;
1218 case VK_SWIZZLE_Z:
1219 return V_008F0C_SQ_SEL_Z;
1220 case VK_SWIZZLE_W:
1221 return V_008F0C_SQ_SEL_W;
1222 case VK_SWIZZLE_0:
1223 return V_008F0C_SQ_SEL_0;
1224 case VK_SWIZZLE_1:
1225 return V_008F0C_SQ_SEL_1;
1226 default: /* VK_SWIZZLE_X */
1227 return V_008F0C_SQ_SEL_X;
1228 }
1229 }
1230
1231
1232 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1233 {
1234 switch(state) {
1235 case VK_DYNAMIC_STATE_VIEWPORT:
1236 return RADV_DYNAMIC_VIEWPORT;
1237 case VK_DYNAMIC_STATE_SCISSOR:
1238 return RADV_DYNAMIC_SCISSOR;
1239 case VK_DYNAMIC_STATE_LINE_WIDTH:
1240 return RADV_DYNAMIC_LINE_WIDTH;
1241 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1242 return RADV_DYNAMIC_DEPTH_BIAS;
1243 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1244 return RADV_DYNAMIC_BLEND_CONSTANTS;
1245 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1246 return RADV_DYNAMIC_DEPTH_BOUNDS;
1247 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1248 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1249 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1250 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1251 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1252 return RADV_DYNAMIC_STENCIL_REFERENCE;
1253 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1254 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1255 default:
1256 unreachable("Unhandled dynamic state");
1257 }
1258 }
1259
1260 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1261 {
1262 uint32_t states = RADV_DYNAMIC_ALL;
1263
1264 /* If rasterization is disabled we do not care about any of the dynamic states,
1265 * since they are all rasterization related only. */
1266 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1267 return 0;
1268
1269 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1270 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1271
1272 if (!pCreateInfo->pDepthStencilState ||
1273 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1274 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1275
1276 if (!pCreateInfo->pDepthStencilState ||
1277 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1278 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1279 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1280 RADV_DYNAMIC_STENCIL_REFERENCE);
1281
1282 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1283 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1284
1285 /* TODO: blend constants & line width. */
1286
1287 return states;
1288 }
1289
1290
1291 static void
1292 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1293 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1294 {
1295 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1296 uint32_t states = needed_states;
1297 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1298 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1299
1300 pipeline->dynamic_state = default_dynamic_state;
1301 pipeline->graphics.needed_dynamic_state = needed_states;
1302
1303 if (pCreateInfo->pDynamicState) {
1304 /* Remove all of the states that are marked as dynamic */
1305 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1306 for (uint32_t s = 0; s < count; s++)
1307 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1308 }
1309
1310 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1311
1312 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1313 assert(pCreateInfo->pViewportState);
1314
1315 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1316 if (states & RADV_DYNAMIC_VIEWPORT) {
1317 typed_memcpy(dynamic->viewport.viewports,
1318 pCreateInfo->pViewportState->pViewports,
1319 pCreateInfo->pViewportState->viewportCount);
1320 }
1321 }
1322
1323 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1324 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1325 if (states & RADV_DYNAMIC_SCISSOR) {
1326 typed_memcpy(dynamic->scissor.scissors,
1327 pCreateInfo->pViewportState->pScissors,
1328 pCreateInfo->pViewportState->scissorCount);
1329 }
1330 }
1331
1332 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1333 assert(pCreateInfo->pRasterizationState);
1334 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1335 }
1336
1337 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1338 assert(pCreateInfo->pRasterizationState);
1339 dynamic->depth_bias.bias =
1340 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1341 dynamic->depth_bias.clamp =
1342 pCreateInfo->pRasterizationState->depthBiasClamp;
1343 dynamic->depth_bias.slope =
1344 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1345 }
1346
1347 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1348 *
1349 * pColorBlendState is [...] NULL if the pipeline has rasterization
1350 * disabled or if the subpass of the render pass the pipeline is
1351 * created against does not use any color attachments.
1352 */
1353 bool uses_color_att = false;
1354 for (unsigned i = 0; i < subpass->color_count; ++i) {
1355 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1356 uses_color_att = true;
1357 break;
1358 }
1359 }
1360
1361 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1362 assert(pCreateInfo->pColorBlendState);
1363 typed_memcpy(dynamic->blend_constants,
1364 pCreateInfo->pColorBlendState->blendConstants, 4);
1365 }
1366
1367 /* If there is no depthstencil attachment, then don't read
1368 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1369 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1370 * no need to override the depthstencil defaults in
1371 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1372 *
1373 * Section 9.2 of the Vulkan 1.0.15 spec says:
1374 *
1375 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1376 * disabled or if the subpass of the render pass the pipeline is created
1377 * against does not use a depth/stencil attachment.
1378 */
1379 if (needed_states &&
1380 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1381 assert(pCreateInfo->pDepthStencilState);
1382
1383 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1384 dynamic->depth_bounds.min =
1385 pCreateInfo->pDepthStencilState->minDepthBounds;
1386 dynamic->depth_bounds.max =
1387 pCreateInfo->pDepthStencilState->maxDepthBounds;
1388 }
1389
1390 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1391 dynamic->stencil_compare_mask.front =
1392 pCreateInfo->pDepthStencilState->front.compareMask;
1393 dynamic->stencil_compare_mask.back =
1394 pCreateInfo->pDepthStencilState->back.compareMask;
1395 }
1396
1397 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1398 dynamic->stencil_write_mask.front =
1399 pCreateInfo->pDepthStencilState->front.writeMask;
1400 dynamic->stencil_write_mask.back =
1401 pCreateInfo->pDepthStencilState->back.writeMask;
1402 }
1403
1404 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1405 dynamic->stencil_reference.front =
1406 pCreateInfo->pDepthStencilState->front.reference;
1407 dynamic->stencil_reference.back =
1408 pCreateInfo->pDepthStencilState->back.reference;
1409 }
1410 }
1411
1412 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1413 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1414 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1415 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1416 typed_memcpy(dynamic->discard_rectangle.rectangles,
1417 discard_rectangle_info->pDiscardRectangles,
1418 discard_rectangle_info->discardRectangleCount);
1419 }
1420
1421 pipeline->dynamic_state.mask = states;
1422 }
1423
1424 static struct radv_gs_state
1425 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1426 const struct radv_pipeline *pipeline)
1427 {
1428 struct radv_gs_state gs = {0};
1429 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1430 struct radv_es_output_info *es_info;
1431 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1432 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1433 else
1434 es_info = radv_pipeline_has_tess(pipeline) ?
1435 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1436 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1437
1438 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1439 bool uses_adjacency;
1440 switch(pCreateInfo->pInputAssemblyState->topology) {
1441 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1442 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1443 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1444 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1445 uses_adjacency = true;
1446 break;
1447 default:
1448 uses_adjacency = false;
1449 break;
1450 }
1451
1452 /* All these are in dwords: */
1453 /* We can't allow using the whole LDS, because GS waves compete with
1454 * other shader stages for LDS space. */
1455 const unsigned max_lds_size = 8 * 1024;
1456 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1457 unsigned esgs_lds_size;
1458
1459 /* All these are per subgroup: */
1460 const unsigned max_out_prims = 32 * 1024;
1461 const unsigned max_es_verts = 255;
1462 const unsigned ideal_gs_prims = 64;
1463 unsigned max_gs_prims, gs_prims;
1464 unsigned min_es_verts, es_verts, worst_case_es_verts;
1465
1466 if (uses_adjacency || gs_num_invocations > 1)
1467 max_gs_prims = 127 / gs_num_invocations;
1468 else
1469 max_gs_prims = 255;
1470
1471 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1472 * Make sure we don't go over the maximum value.
1473 */
1474 if (gs_info->gs.vertices_out > 0) {
1475 max_gs_prims = MIN2(max_gs_prims,
1476 max_out_prims /
1477 (gs_info->gs.vertices_out * gs_num_invocations));
1478 }
1479 assert(max_gs_prims > 0);
1480
1481 /* If the primitive has adjacency, halve the number of vertices
1482 * that will be reused in multiple primitives.
1483 */
1484 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1485
1486 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1487 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1488
1489 /* Compute ESGS LDS size based on the worst case number of ES vertices
1490 * needed to create the target number of GS prims per subgroup.
1491 */
1492 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1493
1494 /* If total LDS usage is too big, refactor partitions based on ratio
1495 * of ESGS item sizes.
1496 */
1497 if (esgs_lds_size > max_lds_size) {
1498 /* Our target GS Prims Per Subgroup was too large. Calculate
1499 * the maximum number of GS Prims Per Subgroup that will fit
1500 * into LDS, capped by the maximum that the hardware can support.
1501 */
1502 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1503 max_gs_prims);
1504 assert(gs_prims > 0);
1505 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1506 max_es_verts);
1507
1508 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1509 assert(esgs_lds_size <= max_lds_size);
1510 }
1511
1512 /* Now calculate remaining ESGS information. */
1513 if (esgs_lds_size)
1514 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1515 else
1516 es_verts = max_es_verts;
1517
1518 /* Vertices for adjacency primitives are not always reused, so restore
1519 * it for ES_VERTS_PER_SUBGRP.
1520 */
1521 min_es_verts = gs_info->gs.vertices_in;
1522
1523 /* For normal primitives, the VGT only checks if they are past the ES
1524 * verts per subgroup after allocating a full GS primitive and if they
1525 * are, kick off a new subgroup. But if those additional ES verts are
1526 * unique (e.g. not reused) we need to make sure there is enough LDS
1527 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1528 */
1529 es_verts -= min_es_verts - 1;
1530
1531 uint32_t es_verts_per_subgroup = es_verts;
1532 uint32_t gs_prims_per_subgroup = gs_prims;
1533 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1534 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1535 gs.lds_size = align(esgs_lds_size, 128) / 128;
1536 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1537 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1538 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1539 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1540 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1541 assert(max_prims_per_subgroup <= max_out_prims);
1542
1543 return gs;
1544 }
1545
1546 static void
1547 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1548 {
1549 struct radv_device *device = pipeline->device;
1550 unsigned num_se = device->physical_device->rad_info.max_se;
1551 unsigned wave_size = 64;
1552 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1553 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1554 unsigned alignment = 256 * num_se;
1555 /* The maximum size is 63.999 MB per SE. */
1556 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1557 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1558
1559 /* Calculate the minimum size. */
1560 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1561 wave_size, alignment);
1562 /* These are recommended sizes, not minimum sizes. */
1563 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1564 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1565 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1566 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1567
1568 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1569 esgs_ring_size = align(esgs_ring_size, alignment);
1570 gsvs_ring_size = align(gsvs_ring_size, alignment);
1571
1572 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1573 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1574
1575 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1576 }
1577
1578 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1579 unsigned *lds_size)
1580 {
1581 /* If tessellation is all offchip and on-chip GS isn't used, this
1582 * workaround is not needed.
1583 */
1584 return;
1585
1586 /* SPI barrier management bug:
1587 * Make sure we have at least 4k of LDS in use to avoid the bug.
1588 * It applies to workgroup sizes of more than one wavefront.
1589 */
1590 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1591 device->physical_device->rad_info.family == CHIP_KABINI ||
1592 device->physical_device->rad_info.family == CHIP_MULLINS)
1593 *lds_size = MAX2(*lds_size, 8);
1594 }
1595
1596 struct radv_shader_variant *
1597 radv_get_shader(struct radv_pipeline *pipeline,
1598 gl_shader_stage stage)
1599 {
1600 if (stage == MESA_SHADER_VERTEX) {
1601 if (pipeline->shaders[MESA_SHADER_VERTEX])
1602 return pipeline->shaders[MESA_SHADER_VERTEX];
1603 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1604 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1605 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1606 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1607 } else if (stage == MESA_SHADER_TESS_EVAL) {
1608 if (!radv_pipeline_has_tess(pipeline))
1609 return NULL;
1610 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1611 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1612 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1613 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1614 }
1615 return pipeline->shaders[stage];
1616 }
1617
1618 static struct radv_tessellation_state
1619 calculate_tess_state(struct radv_pipeline *pipeline,
1620 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1621 {
1622 unsigned num_tcs_input_cp;
1623 unsigned num_tcs_output_cp;
1624 unsigned lds_size;
1625 unsigned num_patches;
1626 struct radv_tessellation_state tess = {0};
1627
1628 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1629 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1630 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1631
1632 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1633
1634 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1635 assert(lds_size <= 65536);
1636 lds_size = align(lds_size, 512) / 512;
1637 } else {
1638 assert(lds_size <= 32768);
1639 lds_size = align(lds_size, 256) / 256;
1640 }
1641 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1642
1643 tess.lds_size = lds_size;
1644
1645 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1646 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1647 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1648 tess.num_patches = num_patches;
1649
1650 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1651 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1652
1653 switch (tes->info.tes.primitive_mode) {
1654 case GL_TRIANGLES:
1655 type = V_028B6C_TESS_TRIANGLE;
1656 break;
1657 case GL_QUADS:
1658 type = V_028B6C_TESS_QUAD;
1659 break;
1660 case GL_ISOLINES:
1661 type = V_028B6C_TESS_ISOLINE;
1662 break;
1663 }
1664
1665 switch (tes->info.tes.spacing) {
1666 case TESS_SPACING_EQUAL:
1667 partitioning = V_028B6C_PART_INTEGER;
1668 break;
1669 case TESS_SPACING_FRACTIONAL_ODD:
1670 partitioning = V_028B6C_PART_FRAC_ODD;
1671 break;
1672 case TESS_SPACING_FRACTIONAL_EVEN:
1673 partitioning = V_028B6C_PART_FRAC_EVEN;
1674 break;
1675 default:
1676 break;
1677 }
1678
1679 bool ccw = tes->info.tes.ccw;
1680 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1681 vk_find_struct_const(pCreateInfo->pTessellationState,
1682 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1683
1684 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1685 ccw = !ccw;
1686
1687 if (tes->info.tes.point_mode)
1688 topology = V_028B6C_OUTPUT_POINT;
1689 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1690 topology = V_028B6C_OUTPUT_LINE;
1691 else if (ccw)
1692 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1693 else
1694 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1695
1696 if (pipeline->device->has_distributed_tess) {
1697 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1698 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1699 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1700 else
1701 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1702 } else
1703 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1704
1705 tess.tf_param = S_028B6C_TYPE(type) |
1706 S_028B6C_PARTITIONING(partitioning) |
1707 S_028B6C_TOPOLOGY(topology) |
1708 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1709
1710 return tess;
1711 }
1712
1713 static const struct radv_prim_vertex_count prim_size_table[] = {
1714 [V_008958_DI_PT_NONE] = {0, 0},
1715 [V_008958_DI_PT_POINTLIST] = {1, 1},
1716 [V_008958_DI_PT_LINELIST] = {2, 2},
1717 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1718 [V_008958_DI_PT_TRILIST] = {3, 3},
1719 [V_008958_DI_PT_TRIFAN] = {3, 1},
1720 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1721 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1722 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1723 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1724 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1725 [V_008958_DI_PT_RECTLIST] = {3, 3},
1726 [V_008958_DI_PT_LINELOOP] = {2, 1},
1727 [V_008958_DI_PT_POLYGON] = {3, 1},
1728 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1729 };
1730
1731 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1732 {
1733 if (radv_pipeline_has_gs(pipeline))
1734 return &pipeline->gs_copy_shader->info.vs.outinfo;
1735 else if (radv_pipeline_has_tess(pipeline))
1736 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1737 else
1738 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1739 }
1740
1741 static void
1742 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1743 {
1744 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1745 int shader_count = 0;
1746
1747 if(shaders[MESA_SHADER_FRAGMENT]) {
1748 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1749 }
1750 if(shaders[MESA_SHADER_GEOMETRY]) {
1751 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1752 }
1753 if(shaders[MESA_SHADER_TESS_EVAL]) {
1754 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1755 }
1756 if(shaders[MESA_SHADER_TESS_CTRL]) {
1757 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1758 }
1759 if(shaders[MESA_SHADER_VERTEX]) {
1760 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1761 }
1762
1763 for (int i = 1; i < shader_count; ++i) {
1764 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1765 ordered_shaders[i - 1]);
1766
1767 nir_remove_dead_variables(ordered_shaders[i],
1768 nir_var_shader_out);
1769 nir_remove_dead_variables(ordered_shaders[i - 1],
1770 nir_var_shader_in);
1771
1772 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1773 ordered_shaders[i - 1]);
1774
1775 nir_compact_varyings(ordered_shaders[i],
1776 ordered_shaders[i - 1], true);
1777
1778 if (progress) {
1779 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1780 ac_lower_indirect_derefs(ordered_shaders[i],
1781 pipeline->device->physical_device->rad_info.chip_class);
1782 }
1783 radv_optimize_nir(ordered_shaders[i], false);
1784
1785 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1786 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1787 pipeline->device->physical_device->rad_info.chip_class);
1788 }
1789 radv_optimize_nir(ordered_shaders[i - 1], false);
1790 }
1791 }
1792 }
1793
1794
1795 static struct radv_pipeline_key
1796 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1797 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1798 const struct radv_blend_state *blend,
1799 bool has_view_index)
1800 {
1801 const VkPipelineVertexInputStateCreateInfo *input_state =
1802 pCreateInfo->pVertexInputState;
1803 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
1804 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1805
1806 struct radv_pipeline_key key;
1807 memset(&key, 0, sizeof(key));
1808
1809 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
1810 key.optimisations_disabled = 1;
1811
1812 key.has_multiview_view_index = has_view_index;
1813
1814 uint32_t binding_input_rate = 0;
1815 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
1816 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1817 if (input_state->pVertexBindingDescriptions[i].inputRate) {
1818 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
1819 binding_input_rate |= 1u << binding;
1820 instance_rate_divisors[binding] = 1;
1821 }
1822 }
1823 if (divisor_state) {
1824 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
1825 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
1826 divisor_state->pVertexBindingDivisors[i].divisor;
1827 }
1828 }
1829
1830 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1831 unsigned location = input_state->pVertexAttributeDescriptions[i].location;
1832 unsigned binding = input_state->pVertexAttributeDescriptions[i].binding;
1833 if (binding_input_rate & (1u << binding)) {
1834 key.instance_rate_inputs |= 1u << location;
1835 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
1836 }
1837
1838 if (pipeline->device->physical_device->rad_info.chip_class <= VI &&
1839 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
1840 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
1841 uint64_t adjust;
1842 switch(format) {
1843 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
1844 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
1845 adjust = RADV_ALPHA_ADJUST_SNORM;
1846 break;
1847 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
1848 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
1849 adjust = RADV_ALPHA_ADJUST_SSCALED;
1850 break;
1851 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
1852 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
1853 adjust = RADV_ALPHA_ADJUST_SINT;
1854 break;
1855 default:
1856 adjust = 0;
1857 break;
1858 }
1859 key.vertex_alpha_adjust |= adjust << (2 * location);
1860 }
1861 }
1862
1863 if (pCreateInfo->pTessellationState)
1864 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1865
1866
1867 if (pCreateInfo->pMultisampleState &&
1868 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1869 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1870 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1871 key.multisample = true;
1872 key.log2_num_samples = util_logbase2(num_samples);
1873 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1874 }
1875
1876 key.col_format = blend->spi_shader_col_format;
1877 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1878 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1879
1880 return key;
1881 }
1882
1883 static void
1884 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
1885 const struct radv_pipeline_key *key,
1886 nir_shader **nir)
1887 {
1888 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1889 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
1890 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i)
1891 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
1892
1893 if (nir[MESA_SHADER_TESS_CTRL]) {
1894 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1895 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
1896 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1897 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1898
1899 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1900 }
1901
1902 if (nir[MESA_SHADER_GEOMETRY]) {
1903 if (nir[MESA_SHADER_TESS_CTRL])
1904 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1905 else
1906 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1907 }
1908
1909 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1910 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1911
1912 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1913 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1914 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1915 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1916 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1917 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1918 }
1919
1920 static void
1921 merge_tess_info(struct shader_info *tes_info,
1922 const struct shader_info *tcs_info)
1923 {
1924 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1925 *
1926 * "PointMode. Controls generation of points rather than triangles
1927 * or lines. This functionality defaults to disabled, and is
1928 * enabled if either shader stage includes the execution mode.
1929 *
1930 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1931 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1932 * and OutputVertices, it says:
1933 *
1934 * "One mode must be set in at least one of the tessellation
1935 * shader stages."
1936 *
1937 * So, the fields can be set in either the TCS or TES, but they must
1938 * agree if set in both. Our backend looks at TES, so bitwise-or in
1939 * the values from the TCS.
1940 */
1941 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1942 tes_info->tess.tcs_vertices_out == 0 ||
1943 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1944 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1945
1946 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1947 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1948 tcs_info->tess.spacing == tes_info->tess.spacing);
1949 tes_info->tess.spacing |= tcs_info->tess.spacing;
1950
1951 assert(tcs_info->tess.primitive_mode == 0 ||
1952 tes_info->tess.primitive_mode == 0 ||
1953 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1954 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1955 tes_info->tess.ccw |= tcs_info->tess.ccw;
1956 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1957 }
1958
1959 static
1960 void radv_create_shaders(struct radv_pipeline *pipeline,
1961 struct radv_device *device,
1962 struct radv_pipeline_cache *cache,
1963 struct radv_pipeline_key key,
1964 const VkPipelineShaderStageCreateInfo **pStages,
1965 const VkPipelineCreateFlags flags)
1966 {
1967 struct radv_shader_module fs_m = {0};
1968 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1969 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1970 void *codes[MESA_SHADER_STAGES] = {0};
1971 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1972 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1973 unsigned char hash[20], gs_copy_hash[20];
1974
1975 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1976 if (pStages[i]) {
1977 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1978 if (modules[i]->nir)
1979 _mesa_sha1_compute(modules[i]->nir->info.name,
1980 strlen(modules[i]->nir->info.name),
1981 modules[i]->sha1);
1982
1983 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1984 }
1985 }
1986
1987 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1988 memcpy(gs_copy_hash, hash, 20);
1989 gs_copy_hash[0] ^= 1;
1990
1991 if (modules[MESA_SHADER_GEOMETRY]) {
1992 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1993 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1994 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1995 }
1996
1997 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1998 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1999 return;
2000 }
2001
2002 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2003 nir_builder fs_b;
2004 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2005 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2006 fs_m.nir = fs_b.shader;
2007 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2008 }
2009
2010 /* Determine first and last stage. */
2011 unsigned first = MESA_SHADER_STAGES;
2012 unsigned last = 0;
2013 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2014 if (!pStages[i])
2015 continue;
2016 if (first == MESA_SHADER_STAGES)
2017 first = i;
2018 last = i;
2019 }
2020
2021 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2022 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2023
2024 if (!modules[i])
2025 continue;
2026
2027 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2028 stage ? stage->pName : "main", i,
2029 stage ? stage->pSpecializationInfo : NULL,
2030 flags);
2031
2032 /* We don't want to alter meta shaders IR directly so clone it
2033 * first.
2034 */
2035 if (nir[i]->info.name) {
2036 nir[i] = nir_shader_clone(NULL, nir[i]);
2037 }
2038
2039 if (first != last) {
2040 nir_variable_mode mask = 0;
2041
2042 if (i != first)
2043 mask = mask | nir_var_shader_in;
2044
2045 if (i != last)
2046 mask = mask | nir_var_shader_out;
2047
2048 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) {
2049 nir_lower_io_to_scalar_early(nir[i], mask);
2050 radv_optimize_nir(nir[i], false);
2051 }
2052 }
2053 }
2054
2055 if (nir[MESA_SHADER_TESS_CTRL]) {
2056 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
2057 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2058 }
2059
2060 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2061 radv_link_shaders(pipeline, nir);
2062
2063 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2064 if (radv_can_dump_shader(device, modules[i], false))
2065 nir_print_shader(nir[i], stderr);
2066 }
2067
2068 radv_fill_shader_keys(keys, &key, nir);
2069
2070 if (nir[MESA_SHADER_FRAGMENT]) {
2071 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2072 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2073 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2074 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2075 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
2076 }
2077
2078 /* TODO: These are no longer used as keys we should refactor this */
2079 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
2080 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2081 keys[MESA_SHADER_VERTEX].vs.export_layer_id =
2082 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2083 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
2084 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2085 keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id =
2086 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2087 }
2088
2089 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2090 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2091 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2092 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2093 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2094 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2095 pipeline->layout,
2096 &key, &codes[MESA_SHADER_TESS_CTRL],
2097 &code_sizes[MESA_SHADER_TESS_CTRL]);
2098 }
2099 modules[MESA_SHADER_VERTEX] = NULL;
2100 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2101 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2102 }
2103
2104 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2105 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2106 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2107 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2108 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2109 pipeline->layout,
2110 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
2111 &code_sizes[MESA_SHADER_GEOMETRY]);
2112 }
2113 modules[pre_stage] = NULL;
2114 }
2115
2116 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2117 if(modules[i] && !pipeline->shaders[i]) {
2118 if (i == MESA_SHADER_TESS_CTRL) {
2119 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
2120 }
2121 if (i == MESA_SHADER_TESS_EVAL) {
2122 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2123 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2124 }
2125 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
2126 pipeline->layout,
2127 keys + i, &codes[i],
2128 &code_sizes[i]);
2129 }
2130 }
2131
2132 if(modules[MESA_SHADER_GEOMETRY]) {
2133 void *gs_copy_code = NULL;
2134 unsigned gs_copy_code_size = 0;
2135 if (!pipeline->gs_copy_shader) {
2136 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2137 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
2138 &gs_copy_code_size,
2139 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2140 }
2141
2142 if (pipeline->gs_copy_shader) {
2143 void *code[MESA_SHADER_STAGES] = {0};
2144 unsigned code_size[MESA_SHADER_STAGES] = {0};
2145 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2146
2147 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
2148 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
2149 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2150
2151 radv_pipeline_cache_insert_shaders(device, cache,
2152 gs_copy_hash,
2153 variants,
2154 (const void**)code,
2155 code_size);
2156 }
2157 free(gs_copy_code);
2158 }
2159
2160 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2161 (const void**)codes, code_sizes);
2162
2163 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2164 free(codes[i]);
2165 if (modules[i]) {
2166 if (!pipeline->device->keep_shader_info)
2167 ralloc_free(nir[i]);
2168
2169 if (radv_can_dump_shader_stats(device, modules[i]))
2170 radv_shader_dump_stats(device,
2171 pipeline->shaders[i],
2172 i, stderr);
2173 }
2174 }
2175
2176 if (fs_m.nir)
2177 ralloc_free(fs_m.nir);
2178 }
2179
2180 static uint32_t
2181 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2182 gl_shader_stage stage, enum chip_class chip_class)
2183 {
2184 bool has_gs = radv_pipeline_has_gs(pipeline);
2185 bool has_tess = radv_pipeline_has_tess(pipeline);
2186 switch (stage) {
2187 case MESA_SHADER_FRAGMENT:
2188 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2189 case MESA_SHADER_VERTEX:
2190 if (chip_class >= GFX9) {
2191 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2192 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2193 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2194 }
2195 if (has_tess)
2196 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2197 else
2198 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
2199 case MESA_SHADER_GEOMETRY:
2200 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2201 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2202 case MESA_SHADER_COMPUTE:
2203 return R_00B900_COMPUTE_USER_DATA_0;
2204 case MESA_SHADER_TESS_CTRL:
2205 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2206 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2207 case MESA_SHADER_TESS_EVAL:
2208 if (chip_class >= GFX9) {
2209 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2210 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2211 }
2212 if (has_gs)
2213 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2214 else
2215 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2216 default:
2217 unreachable("unknown shader");
2218 }
2219 }
2220
2221 struct radv_bin_size_entry {
2222 unsigned bpp;
2223 VkExtent2D extent;
2224 };
2225
2226 static VkExtent2D
2227 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2228 {
2229 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2230 {
2231 /* One RB / SE */
2232 {
2233 /* One shader engine */
2234 { 0, {128, 128}},
2235 { 1, { 64, 128}},
2236 { 2, { 32, 128}},
2237 { 3, { 16, 128}},
2238 { 17, { 0, 0}},
2239 { UINT_MAX, { 0, 0}},
2240 },
2241 {
2242 /* Two shader engines */
2243 { 0, {128, 128}},
2244 { 2, { 64, 128}},
2245 { 3, { 32, 128}},
2246 { 5, { 16, 128}},
2247 { 17, { 0, 0}},
2248 { UINT_MAX, { 0, 0}},
2249 },
2250 {
2251 /* Four shader engines */
2252 { 0, {128, 128}},
2253 { 3, { 64, 128}},
2254 { 5, { 16, 128}},
2255 { 17, { 0, 0}},
2256 { UINT_MAX, { 0, 0}},
2257 },
2258 },
2259 {
2260 /* Two RB / SE */
2261 {
2262 /* One shader engine */
2263 { 0, {128, 128}},
2264 { 2, { 64, 128}},
2265 { 3, { 32, 128}},
2266 { 5, { 16, 128}},
2267 { 33, { 0, 0}},
2268 { UINT_MAX, { 0, 0}},
2269 },
2270 {
2271 /* Two shader engines */
2272 { 0, {128, 128}},
2273 { 3, { 64, 128}},
2274 { 5, { 32, 128}},
2275 { 9, { 16, 128}},
2276 { 33, { 0, 0}},
2277 { UINT_MAX, { 0, 0}},
2278 },
2279 {
2280 /* Four shader engines */
2281 { 0, {256, 256}},
2282 { 2, {128, 256}},
2283 { 3, {128, 128}},
2284 { 5, { 64, 128}},
2285 { 9, { 16, 128}},
2286 { 33, { 0, 0}},
2287 { UINT_MAX, { 0, 0}},
2288 },
2289 },
2290 {
2291 /* Four RB / SE */
2292 {
2293 /* One shader engine */
2294 { 0, {128, 256}},
2295 { 2, {128, 128}},
2296 { 3, { 64, 128}},
2297 { 5, { 32, 128}},
2298 { 9, { 16, 128}},
2299 { 33, { 0, 0}},
2300 { UINT_MAX, { 0, 0}},
2301 },
2302 {
2303 /* Two shader engines */
2304 { 0, {256, 256}},
2305 { 2, {128, 256}},
2306 { 3, {128, 128}},
2307 { 5, { 64, 128}},
2308 { 9, { 32, 128}},
2309 { 17, { 16, 128}},
2310 { 33, { 0, 0}},
2311 { UINT_MAX, { 0, 0}},
2312 },
2313 {
2314 /* Four shader engines */
2315 { 0, {256, 512}},
2316 { 2, {256, 256}},
2317 { 3, {128, 256}},
2318 { 5, {128, 128}},
2319 { 9, { 64, 128}},
2320 { 17, { 16, 128}},
2321 { 33, { 0, 0}},
2322 { UINT_MAX, { 0, 0}},
2323 },
2324 },
2325 };
2326 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2327 {
2328 // One RB / SE
2329 {
2330 // One shader engine
2331 { 0, {128, 256}},
2332 { 2, {128, 128}},
2333 { 4, { 64, 128}},
2334 { 7, { 32, 128}},
2335 { 13, { 16, 128}},
2336 { 49, { 0, 0}},
2337 { UINT_MAX, { 0, 0}},
2338 },
2339 {
2340 // Two shader engines
2341 { 0, {256, 256}},
2342 { 2, {128, 256}},
2343 { 4, {128, 128}},
2344 { 7, { 64, 128}},
2345 { 13, { 32, 128}},
2346 { 25, { 16, 128}},
2347 { 49, { 0, 0}},
2348 { UINT_MAX, { 0, 0}},
2349 },
2350 {
2351 // Four shader engines
2352 { 0, {256, 512}},
2353 { 2, {256, 256}},
2354 { 4, {128, 256}},
2355 { 7, {128, 128}},
2356 { 13, { 64, 128}},
2357 { 25, { 16, 128}},
2358 { 49, { 0, 0}},
2359 { UINT_MAX, { 0, 0}},
2360 },
2361 },
2362 {
2363 // Two RB / SE
2364 {
2365 // One shader engine
2366 { 0, {256, 256}},
2367 { 2, {128, 256}},
2368 { 4, {128, 128}},
2369 { 7, { 64, 128}},
2370 { 13, { 32, 128}},
2371 { 25, { 16, 128}},
2372 { 97, { 0, 0}},
2373 { UINT_MAX, { 0, 0}},
2374 },
2375 {
2376 // Two shader engines
2377 { 0, {256, 512}},
2378 { 2, {256, 256}},
2379 { 4, {128, 256}},
2380 { 7, {128, 128}},
2381 { 13, { 64, 128}},
2382 { 25, { 32, 128}},
2383 { 49, { 16, 128}},
2384 { 97, { 0, 0}},
2385 { UINT_MAX, { 0, 0}},
2386 },
2387 {
2388 // Four shader engines
2389 { 0, {512, 512}},
2390 { 2, {256, 512}},
2391 { 4, {256, 256}},
2392 { 7, {128, 256}},
2393 { 13, {128, 128}},
2394 { 25, { 64, 128}},
2395 { 49, { 16, 128}},
2396 { 97, { 0, 0}},
2397 { UINT_MAX, { 0, 0}},
2398 },
2399 },
2400 {
2401 // Four RB / SE
2402 {
2403 // One shader engine
2404 { 0, {256, 512}},
2405 { 2, {256, 256}},
2406 { 4, {128, 256}},
2407 { 7, {128, 128}},
2408 { 13, { 64, 128}},
2409 { 25, { 32, 128}},
2410 { 49, { 16, 128}},
2411 { UINT_MAX, { 0, 0}},
2412 },
2413 {
2414 // Two shader engines
2415 { 0, {512, 512}},
2416 { 2, {256, 512}},
2417 { 4, {256, 256}},
2418 { 7, {128, 256}},
2419 { 13, {128, 128}},
2420 { 25, { 64, 128}},
2421 { 49, { 32, 128}},
2422 { 97, { 16, 128}},
2423 { UINT_MAX, { 0, 0}},
2424 },
2425 {
2426 // Four shader engines
2427 { 0, {512, 512}},
2428 { 4, {256, 512}},
2429 { 7, {256, 256}},
2430 { 13, {128, 256}},
2431 { 25, {128, 128}},
2432 { 49, { 64, 128}},
2433 { 97, { 16, 128}},
2434 { UINT_MAX, { 0, 0}},
2435 },
2436 },
2437 };
2438
2439 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2440 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2441 VkExtent2D extent = {512, 512};
2442
2443 unsigned log_num_rb_per_se =
2444 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2445 pipeline->device->physical_device->rad_info.max_se);
2446 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2447
2448 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2449 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2450 unsigned effective_samples = total_samples;
2451 unsigned color_bytes_per_pixel = 0;
2452
2453 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2454 if (vkblend) {
2455 for (unsigned i = 0; i < subpass->color_count; i++) {
2456 if (!vkblend->pAttachments[i].colorWriteMask)
2457 continue;
2458
2459 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2460 continue;
2461
2462 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2463 color_bytes_per_pixel += vk_format_get_blocksize(format);
2464 }
2465
2466 /* MSAA images typically don't use all samples all the time. */
2467 if (effective_samples >= 2 && ps_iter_samples <= 1)
2468 effective_samples = 2;
2469 color_bytes_per_pixel *= effective_samples;
2470 }
2471
2472 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2473 while(color_entry->bpp <= color_bytes_per_pixel)
2474 ++color_entry;
2475
2476 extent = color_entry->extent;
2477
2478 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2479 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2480
2481 /* Coefficients taken from AMDVLK */
2482 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2483 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2484 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2485
2486 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2487 while(ds_entry->bpp <= ds_bytes_per_pixel)
2488 ++ds_entry;
2489
2490 extent.width = MIN2(extent.width, ds_entry->extent.width);
2491 extent.height = MIN2(extent.height, ds_entry->extent.height);
2492 }
2493
2494 return extent;
2495 }
2496
2497 static void
2498 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2499 struct radv_pipeline *pipeline,
2500 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2501 {
2502 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2503 return;
2504
2505 uint32_t pa_sc_binner_cntl_0 =
2506 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2507 S_028C44_DISABLE_START_OF_PRIM(1);
2508 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2509
2510 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2511
2512 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2513 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2514 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2515
2516 switch (pipeline->device->physical_device->rad_info.family) {
2517 case CHIP_VEGA10:
2518 case CHIP_VEGA12:
2519 context_states_per_bin = 1;
2520 persistent_states_per_bin = 1;
2521 fpovs_per_batch = 63;
2522 break;
2523 case CHIP_RAVEN:
2524 context_states_per_bin = 6;
2525 persistent_states_per_bin = 32;
2526 fpovs_per_batch = 63;
2527 break;
2528 default:
2529 unreachable("unhandled family while determining binning state.");
2530 }
2531
2532 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2533 pa_sc_binner_cntl_0 =
2534 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2535 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2536 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2537 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2538 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2539 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2540 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2541 S_028C44_DISABLE_START_OF_PRIM(1) |
2542 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2543 S_028C44_OPTIMAL_BIN_SELECTION(1);
2544 }
2545
2546 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2547 pa_sc_binner_cntl_0);
2548 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2549 db_dfsm_control);
2550 }
2551
2552
2553 static void
2554 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2555 struct radv_pipeline *pipeline,
2556 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2557 const struct radv_graphics_pipeline_create_info *extra)
2558 {
2559 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2560 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2561 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2562 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2563 struct radv_render_pass_attachment *attachment = NULL;
2564 uint32_t db_depth_control = 0, db_stencil_control = 0;
2565 uint32_t db_render_control = 0, db_render_override2 = 0;
2566 uint32_t db_render_override = 0;
2567
2568 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2569 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2570
2571 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2572 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2573
2574 if (vkds && has_depth_attachment) {
2575 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2576 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2577 S_028800_ZFUNC(vkds->depthCompareOp) |
2578 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2579
2580 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2581 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2582 }
2583
2584 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2585 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2586 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2587 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2588 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2589 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2590
2591 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2592 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2593 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2594 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2595 }
2596
2597 if (attachment && extra) {
2598 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2599 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2600
2601 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2602 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2603 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2604 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2605 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2606 }
2607
2608 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2609 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2610
2611 if (pipeline->device->enabled_extensions.EXT_depth_range_unrestricted &&
2612 !pCreateInfo->pRasterizationState->depthClampEnable &&
2613 ps->info.info.ps.writes_z) {
2614 /* From VK_EXT_depth_range_unrestricted spec:
2615 *
2616 * "The behavior described in Primitive Clipping still applies.
2617 * If depth clamping is disabled the depth values are still
2618 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2619 * depth clamping is enabled the above equation is ignored and
2620 * the depth values are instead clamped to the VkViewport
2621 * minDepth and maxDepth values, which in the case of this
2622 * extension can be outside of the 0.0 to 1.0 range."
2623 */
2624 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2625 }
2626
2627 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2628 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2629
2630 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2631 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2632 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2633 }
2634
2635 static void
2636 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2637 struct radv_pipeline *pipeline,
2638 const struct radv_blend_state *blend)
2639 {
2640 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2641 radeon_emit_array(cs, blend->cb_blend_control,
2642 8);
2643 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2644 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2645
2646 if (pipeline->device->physical_device->has_rbplus) {
2647
2648 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2649 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2650 }
2651
2652 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2653
2654 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2655 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2656
2657 pipeline->graphics.col_format = blend->spi_shader_col_format;
2658 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
2659 }
2660
2661
2662 static void
2663 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2664 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2665 {
2666 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2667
2668 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2669 S_028810_PS_UCP_MODE(3) |
2670 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2671 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2672 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2673 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2674 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2675
2676 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2677 S_0286D4_FLAT_SHADE_ENA(1) |
2678 S_0286D4_PNT_SPRITE_ENA(1) |
2679 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2680 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2681 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2682 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2683 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2684
2685 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2686 S_028BE4_PIX_CENTER(1) | // TODO verify
2687 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2688 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2689
2690 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2691 S_028814_FACE(vkraster->frontFace) |
2692 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2693 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2694 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2695 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2696 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2697 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2698 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2699 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2700 }
2701
2702
2703 static void
2704 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2705 struct radv_pipeline *pipeline)
2706 {
2707 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2708
2709 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2710 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2711 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2712
2713 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2714 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2715
2716 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2717 uint32_t offset;
2718 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2719 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2720 if (loc->sgpr_idx == -1)
2721 return;
2722 assert(loc->num_sgprs == 1);
2723 assert(!loc->indirect);
2724 switch (pipeline->graphics.ms.num_samples) {
2725 default:
2726 offset = 0;
2727 break;
2728 case 2:
2729 offset = 1;
2730 break;
2731 case 4:
2732 offset = 3;
2733 break;
2734 case 8:
2735 offset = 7;
2736 break;
2737 case 16:
2738 offset = 15;
2739 break;
2740 }
2741
2742 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2743 }
2744 }
2745
2746 static void
2747 radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
2748 const struct radv_pipeline *pipeline)
2749 {
2750 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2751
2752 uint32_t vgt_primitiveid_en = false;
2753 uint32_t vgt_gs_mode = 0;
2754
2755 if (radv_pipeline_has_gs(pipeline)) {
2756 const struct radv_shader_variant *gs =
2757 pipeline->shaders[MESA_SHADER_GEOMETRY];
2758
2759 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2760 pipeline->device->physical_device->rad_info.chip_class);
2761 } else if (outinfo->export_prim_id) {
2762 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2763 vgt_primitiveid_en = true;
2764 }
2765
2766 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2767 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2768 }
2769
2770 static void
2771 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2772 struct radv_pipeline *pipeline,
2773 struct radv_shader_variant *shader)
2774 {
2775 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2776
2777 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2778 radeon_emit(cs, va >> 8);
2779 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
2780 radeon_emit(cs, shader->rsrc1);
2781 radeon_emit(cs, shader->rsrc2);
2782
2783 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2784 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2785 clip_dist_mask = outinfo->clip_dist_mask;
2786 cull_dist_mask = outinfo->cull_dist_mask;
2787 total_mask = clip_dist_mask | cull_dist_mask;
2788 bool misc_vec_ena = outinfo->writes_pointsize ||
2789 outinfo->writes_layer ||
2790 outinfo->writes_viewport_index;
2791
2792 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2793 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2794
2795 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2796 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2797 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2798 V_02870C_SPI_SHADER_4COMP :
2799 V_02870C_SPI_SHADER_NONE) |
2800 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2801 V_02870C_SPI_SHADER_4COMP :
2802 V_02870C_SPI_SHADER_NONE) |
2803 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2804 V_02870C_SPI_SHADER_4COMP :
2805 V_02870C_SPI_SHADER_NONE));
2806
2807 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2808 S_028818_VTX_W0_FMT(1) |
2809 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2810 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2811 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2812
2813 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2814 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2815 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2816 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2817 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2818 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2819 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2820 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2821 cull_dist_mask << 8 |
2822 clip_dist_mask);
2823
2824 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2825 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2826 outinfo->writes_viewport_index);
2827 }
2828
2829 static void
2830 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2831 struct radv_pipeline *pipeline,
2832 struct radv_shader_variant *shader)
2833 {
2834 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2835
2836 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2837 radeon_emit(cs, va >> 8);
2838 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
2839 radeon_emit(cs, shader->rsrc1);
2840 radeon_emit(cs, shader->rsrc2);
2841 }
2842
2843 static void
2844 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2845 struct radv_pipeline *pipeline,
2846 struct radv_shader_variant *shader,
2847 const struct radv_tessellation_state *tess)
2848 {
2849 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2850 uint32_t rsrc2 = shader->rsrc2;
2851
2852 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2853 radeon_emit(cs, va >> 8);
2854 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
2855
2856 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2857 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2858 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2859 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2860
2861 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2862 radeon_emit(cs, shader->rsrc1);
2863 radeon_emit(cs, rsrc2);
2864 }
2865
2866 static void
2867 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2868 struct radv_pipeline *pipeline,
2869 struct radv_shader_variant *shader,
2870 const struct radv_tessellation_state *tess)
2871 {
2872 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2873
2874 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2875 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2876 radeon_emit(cs, va >> 8);
2877 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
2878
2879 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2880 radeon_emit(cs, shader->rsrc1);
2881 radeon_emit(cs, shader->rsrc2 |
2882 S_00B42C_LDS_SIZE(tess->lds_size));
2883 } else {
2884 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2885 radeon_emit(cs, va >> 8);
2886 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
2887 radeon_emit(cs, shader->rsrc1);
2888 radeon_emit(cs, shader->rsrc2);
2889 }
2890 }
2891
2892 static void
2893 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2894 struct radv_pipeline *pipeline,
2895 const struct radv_tessellation_state *tess)
2896 {
2897 struct radv_shader_variant *vs;
2898
2899 /* Skip shaders merged into HS/GS */
2900 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2901 if (!vs)
2902 return;
2903
2904 if (vs->info.vs.as_ls)
2905 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2906 else if (vs->info.vs.as_es)
2907 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2908 else
2909 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2910 }
2911
2912 static void
2913 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2914 struct radv_pipeline *pipeline,
2915 const struct radv_tessellation_state *tess)
2916 {
2917 if (!radv_pipeline_has_tess(pipeline))
2918 return;
2919
2920 struct radv_shader_variant *tes, *tcs;
2921
2922 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2923 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2924
2925 if (tes) {
2926 if (tes->info.tes.as_es)
2927 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2928 else
2929 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2930 }
2931
2932 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2933
2934 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2935 tess->tf_param);
2936
2937 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2938 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2939 tess->ls_hs_config);
2940 else
2941 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2942 tess->ls_hs_config);
2943 }
2944
2945 static void
2946 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2947 struct radv_pipeline *pipeline,
2948 const struct radv_gs_state *gs_state)
2949 {
2950 struct radv_shader_variant *gs;
2951 uint64_t va;
2952
2953 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2954 if (!gs)
2955 return;
2956
2957 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2958
2959 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2960 radeon_emit(cs, gsvs_itemsize);
2961 radeon_emit(cs, gsvs_itemsize);
2962 radeon_emit(cs, gsvs_itemsize);
2963
2964 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2965
2966 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2967
2968 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2969 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2970 radeon_emit(cs, gs_vert_itemsize >> 2);
2971 radeon_emit(cs, 0);
2972 radeon_emit(cs, 0);
2973 radeon_emit(cs, 0);
2974
2975 uint32_t gs_num_invocations = gs->info.gs.invocations;
2976 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2977 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2978 S_028B90_ENABLE(gs_num_invocations > 0));
2979
2980 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2981 gs_state->vgt_esgs_ring_itemsize);
2982
2983 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2984
2985 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2986 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2987 radeon_emit(cs, va >> 8);
2988 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
2989
2990 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2991 radeon_emit(cs, gs->rsrc1);
2992 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
2993
2994 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
2995 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
2996 } else {
2997 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2998 radeon_emit(cs, va >> 8);
2999 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
3000 radeon_emit(cs, gs->rsrc1);
3001 radeon_emit(cs, gs->rsrc2);
3002 }
3003
3004 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
3005 }
3006
3007 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
3008 {
3009 uint32_t ps_input_cntl;
3010 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3011 ps_input_cntl = S_028644_OFFSET(offset);
3012 if (flat_shade)
3013 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3014 } else {
3015 /* The input is a DEFAULT_VAL constant. */
3016 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3017 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3018 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3019 ps_input_cntl = S_028644_OFFSET(0x20) |
3020 S_028644_DEFAULT_VAL(offset);
3021 }
3022 return ps_input_cntl;
3023 }
3024
3025 static void
3026 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
3027 struct radv_pipeline *pipeline)
3028 {
3029 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3030 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3031 uint32_t ps_input_cntl[32];
3032
3033 unsigned ps_offset = 0;
3034
3035 if (ps->info.info.ps.prim_id_input) {
3036 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
3037 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3038 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
3039 ++ps_offset;
3040 }
3041 }
3042
3043 if (ps->info.info.ps.layer_input ||
3044 ps->info.info.ps.uses_input_attachments ||
3045 ps->info.info.needs_multiview_view_index) {
3046 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
3047 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
3048 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
3049 else
3050 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
3051 ++ps_offset;
3052 }
3053
3054 if (ps->info.info.ps.has_pcoord) {
3055 unsigned val;
3056 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3057 ps_input_cntl[ps_offset] = val;
3058 ps_offset++;
3059 }
3060
3061 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
3062 unsigned vs_offset;
3063 bool flat_shade;
3064 if (!(ps->info.fs.input_mask & (1u << i)))
3065 continue;
3066
3067 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
3068 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
3069 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
3070 ++ps_offset;
3071 continue;
3072 }
3073
3074 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
3075
3076 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
3077 ++ps_offset;
3078 }
3079
3080 if (ps_offset) {
3081 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
3082 for (unsigned i = 0; i < ps_offset; i++) {
3083 radeon_emit(cs, ps_input_cntl[i]);
3084 }
3085 }
3086 }
3087
3088 static uint32_t
3089 radv_compute_db_shader_control(const struct radv_device *device,
3090 const struct radv_shader_variant *ps)
3091 {
3092 unsigned z_order;
3093 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
3094 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
3095 else
3096 z_order = V_02880C_LATE_Z;
3097
3098 bool disable_rbplus = device->physical_device->has_rbplus &&
3099 !device->physical_device->rbplus_allowed;
3100
3101 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
3102 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
3103 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
3104 S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
3105 S_02880C_Z_ORDER(z_order) |
3106 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
3107 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
3108 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
3109 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
3110 }
3111
3112 static void
3113 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
3114 struct radv_pipeline *pipeline)
3115 {
3116 struct radv_shader_variant *ps;
3117 uint64_t va;
3118 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
3119
3120 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3121 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
3122
3123 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
3124 radeon_emit(cs, va >> 8);
3125 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
3126 radeon_emit(cs, ps->rsrc1);
3127 radeon_emit(cs, ps->rsrc2);
3128
3129 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
3130 radv_compute_db_shader_control(pipeline->device, ps));
3131
3132 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
3133 ps->config.spi_ps_input_ena);
3134
3135 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
3136 ps->config.spi_ps_input_addr);
3137
3138 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
3139 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
3140
3141 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
3142
3143 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
3144 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
3145 ps->info.info.ps.writes_stencil,
3146 ps->info.info.ps.writes_sample_mask));
3147
3148 if (pipeline->device->dfsm_allowed) {
3149 /* optimise this? */
3150 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3151 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3152 }
3153 }
3154
3155 static void
3156 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
3157 struct radv_pipeline *pipeline)
3158 {
3159 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
3160 return;
3161
3162 unsigned vtx_reuse_depth = 30;
3163 if (radv_pipeline_has_tess(pipeline) &&
3164 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
3165 vtx_reuse_depth = 14;
3166 }
3167 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
3168 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
3169 }
3170
3171 static uint32_t
3172 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
3173 {
3174 uint32_t stages = 0;
3175 if (radv_pipeline_has_tess(pipeline)) {
3176 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3177 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3178
3179 if (radv_pipeline_has_gs(pipeline))
3180 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3181 S_028B54_GS_EN(1) |
3182 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3183 else
3184 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3185
3186 } else if (radv_pipeline_has_gs(pipeline))
3187 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3188 S_028B54_GS_EN(1) |
3189 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3190
3191 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
3192 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3193
3194 return stages;
3195 }
3196
3197 static uint32_t
3198 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
3199 {
3200 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
3201 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
3202
3203 if (!discard_rectangle_info)
3204 return 0xffff;
3205
3206 unsigned mask = 0;
3207
3208 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
3209 /* Interpret i as a bitmask, and then set the bit in the mask if
3210 * that combination of rectangles in which the pixel is contained
3211 * should pass the cliprect test. */
3212 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
3213
3214 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
3215 !relevant_subset)
3216 continue;
3217
3218 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
3219 relevant_subset)
3220 continue;
3221
3222 mask |= 1u << i;
3223 }
3224
3225 return mask;
3226 }
3227
3228 static void
3229 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
3230 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3231 const struct radv_graphics_pipeline_create_info *extra,
3232 const struct radv_blend_state *blend,
3233 const struct radv_tessellation_state *tess,
3234 const struct radv_gs_state *gs,
3235 unsigned prim, unsigned gs_out)
3236 {
3237 pipeline->cs.buf = malloc(4 * 256);
3238 pipeline->cs.max_dw = 256;
3239
3240 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
3241 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
3242 radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
3243 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
3244 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
3245 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
3246 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
3247 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs);
3248 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
3249 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
3250 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
3251 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
3252
3253 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
3254 S_0286E8_WAVES(pipeline->max_waves) |
3255 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3256
3257 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
3258
3259 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
3260 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
3261 } else {
3262 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
3263 }
3264 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
3265
3266 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
3267
3268 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3269 }
3270
3271 static struct radv_ia_multi_vgt_param_helpers
3272 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
3273 const struct radv_tessellation_state *tess,
3274 uint32_t prim)
3275 {
3276 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
3277 const struct radv_device *device = pipeline->device;
3278
3279 if (radv_pipeline_has_tess(pipeline))
3280 ia_multi_vgt_param.primgroup_size = tess->num_patches;
3281 else if (radv_pipeline_has_gs(pipeline))
3282 ia_multi_vgt_param.primgroup_size = 64;
3283 else
3284 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
3285
3286 ia_multi_vgt_param.partial_es_wave = false;
3287 if (pipeline->device->has_distributed_tess) {
3288 if (radv_pipeline_has_gs(pipeline)) {
3289 if (device->physical_device->rad_info.chip_class <= VI)
3290 ia_multi_vgt_param.partial_es_wave = true;
3291 }
3292 }
3293 /* GS requirement. */
3294 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= VI)
3295 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
3296 ia_multi_vgt_param.partial_es_wave = true;
3297
3298 ia_multi_vgt_param.wd_switch_on_eop = false;
3299 if (device->physical_device->rad_info.chip_class >= CIK) {
3300 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3301 * 4 shader engines. Set 1 to pass the assertion below.
3302 * The other cases are hardware requirements. */
3303 if (device->physical_device->rad_info.max_se < 4 ||
3304 prim == V_008958_DI_PT_POLYGON ||
3305 prim == V_008958_DI_PT_LINELOOP ||
3306 prim == V_008958_DI_PT_TRIFAN ||
3307 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3308 (pipeline->graphics.prim_restart_enable &&
3309 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3310 (prim != V_008958_DI_PT_POINTLIST &&
3311 prim != V_008958_DI_PT_LINESTRIP &&
3312 prim != V_008958_DI_PT_TRISTRIP))))
3313 ia_multi_vgt_param.wd_switch_on_eop = true;
3314 }
3315
3316 ia_multi_vgt_param.ia_switch_on_eoi = false;
3317 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
3318 ia_multi_vgt_param.ia_switch_on_eoi = true;
3319 if (radv_pipeline_has_gs(pipeline) &&
3320 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3321 ia_multi_vgt_param.ia_switch_on_eoi = true;
3322 if (radv_pipeline_has_tess(pipeline)) {
3323 /* SWITCH_ON_EOI must be set if PrimID is used. */
3324 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3325 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
3326 ia_multi_vgt_param.ia_switch_on_eoi = true;
3327 }
3328
3329 ia_multi_vgt_param.partial_vs_wave = false;
3330 if (radv_pipeline_has_tess(pipeline)) {
3331 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3332 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3333 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3334 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3335 radv_pipeline_has_gs(pipeline))
3336 ia_multi_vgt_param.partial_vs_wave = true;
3337 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3338 if (device->has_distributed_tess) {
3339 if (radv_pipeline_has_gs(pipeline)) {
3340 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3341 device->physical_device->rad_info.family == CHIP_FIJI ||
3342 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3343 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3344 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
3345 device->physical_device->rad_info.family == CHIP_VEGAM)
3346 ia_multi_vgt_param.partial_vs_wave = true;
3347 } else {
3348 ia_multi_vgt_param.partial_vs_wave = true;
3349 }
3350 }
3351 }
3352
3353 ia_multi_vgt_param.base =
3354 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3355 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3356 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3357 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3358 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3359
3360 return ia_multi_vgt_param;
3361 }
3362
3363
3364 static void
3365 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3366 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3367 {
3368 const VkPipelineVertexInputStateCreateInfo *vi_info =
3369 pCreateInfo->pVertexInputState;
3370 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3371
3372 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3373 const VkVertexInputAttributeDescription *desc =
3374 &vi_info->pVertexAttributeDescriptions[i];
3375 unsigned loc = desc->location;
3376 const struct vk_format_description *format_desc;
3377 int first_non_void;
3378 uint32_t num_format, data_format;
3379 format_desc = vk_format_description(desc->format);
3380 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3381
3382 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3383 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3384
3385 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3386 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3387 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3388 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3389 S_008F0C_NUM_FORMAT(num_format) |
3390 S_008F0C_DATA_FORMAT(data_format);
3391 velems->format_size[loc] = format_desc->block.bits / 8;
3392 velems->offset[loc] = desc->offset;
3393 velems->binding[loc] = desc->binding;
3394 velems->count = MAX2(velems->count, loc + 1);
3395 }
3396
3397 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3398 const VkVertexInputBindingDescription *desc =
3399 &vi_info->pVertexBindingDescriptions[i];
3400
3401 pipeline->binding_stride[desc->binding] = desc->stride;
3402 }
3403 }
3404
3405 static VkResult
3406 radv_pipeline_init(struct radv_pipeline *pipeline,
3407 struct radv_device *device,
3408 struct radv_pipeline_cache *cache,
3409 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3410 const struct radv_graphics_pipeline_create_info *extra,
3411 const VkAllocationCallbacks *alloc)
3412 {
3413 VkResult result;
3414 bool has_view_index = false;
3415
3416 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3417 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3418 if (subpass->view_mask)
3419 has_view_index = true;
3420 if (alloc == NULL)
3421 alloc = &device->alloc;
3422
3423 pipeline->device = device;
3424 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3425 assert(pipeline->layout);
3426
3427 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3428
3429 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3430 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3431 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3432 pStages[stage] = &pCreateInfo->pStages[i];
3433 }
3434
3435 radv_create_shaders(pipeline, device, cache,
3436 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
3437 pStages, pCreateInfo->flags);
3438
3439 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3440 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
3441 uint32_t gs_out;
3442 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3443
3444 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3445
3446 if (radv_pipeline_has_gs(pipeline)) {
3447 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3448 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3449 } else {
3450 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3451 }
3452 if (extra && extra->use_rectlist) {
3453 prim = V_008958_DI_PT_RECTLIST;
3454 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3455 pipeline->graphics.can_use_guardband = true;
3456 }
3457 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3458 /* prim vertex count will need TESS changes */
3459 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3460
3461 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3462
3463 /* Ensure that some export memory is always allocated, for two reasons:
3464 *
3465 * 1) Correctness: The hardware ignores the EXEC mask if no export
3466 * memory is allocated, so KILL and alpha test do not work correctly
3467 * without this.
3468 * 2) Performance: Every shader needs at least a NULL export, even when
3469 * it writes no color/depth output. The NULL export instruction
3470 * stalls without this setting.
3471 *
3472 * Don't add this to CB_SHADER_MASK.
3473 */
3474 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3475 if (!blend.spi_shader_col_format) {
3476 if (!ps->info.info.ps.writes_z &&
3477 !ps->info.info.ps.writes_stencil &&
3478 !ps->info.info.ps.writes_sample_mask)
3479 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3480 }
3481
3482 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3483 if (pipeline->shaders[i]) {
3484 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3485 }
3486 }
3487
3488 struct radv_gs_state gs = {0};
3489 if (radv_pipeline_has_gs(pipeline)) {
3490 gs = calculate_gs_info(pCreateInfo, pipeline);
3491 calculate_gs_ring_sizes(pipeline, &gs);
3492 }
3493
3494 struct radv_tessellation_state tess = {0};
3495 if (radv_pipeline_has_tess(pipeline)) {
3496 if (prim == V_008958_DI_PT_PATCH) {
3497 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3498 pipeline->graphics.prim_vertex_count.incr = 1;
3499 }
3500 tess = calculate_tess_state(pipeline, pCreateInfo);
3501 }
3502
3503 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3504
3505 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3506
3507 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3508 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3509
3510 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3511 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3512 if (loc->sgpr_idx != -1) {
3513 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3514 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3515 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id)
3516 pipeline->graphics.vtx_emit_num = 3;
3517 else
3518 pipeline->graphics.vtx_emit_num = 2;
3519 }
3520
3521 result = radv_pipeline_scratch_init(device, pipeline);
3522 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3523
3524 return result;
3525 }
3526
3527 VkResult
3528 radv_graphics_pipeline_create(
3529 VkDevice _device,
3530 VkPipelineCache _cache,
3531 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3532 const struct radv_graphics_pipeline_create_info *extra,
3533 const VkAllocationCallbacks *pAllocator,
3534 VkPipeline *pPipeline)
3535 {
3536 RADV_FROM_HANDLE(radv_device, device, _device);
3537 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3538 struct radv_pipeline *pipeline;
3539 VkResult result;
3540
3541 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3542 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3543 if (pipeline == NULL)
3544 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3545
3546 result = radv_pipeline_init(pipeline, device, cache,
3547 pCreateInfo, extra, pAllocator);
3548 if (result != VK_SUCCESS) {
3549 radv_pipeline_destroy(device, pipeline, pAllocator);
3550 return result;
3551 }
3552
3553 *pPipeline = radv_pipeline_to_handle(pipeline);
3554
3555 return VK_SUCCESS;
3556 }
3557
3558 VkResult radv_CreateGraphicsPipelines(
3559 VkDevice _device,
3560 VkPipelineCache pipelineCache,
3561 uint32_t count,
3562 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3563 const VkAllocationCallbacks* pAllocator,
3564 VkPipeline* pPipelines)
3565 {
3566 VkResult result = VK_SUCCESS;
3567 unsigned i = 0;
3568
3569 for (; i < count; i++) {
3570 VkResult r;
3571 r = radv_graphics_pipeline_create(_device,
3572 pipelineCache,
3573 &pCreateInfos[i],
3574 NULL, pAllocator, &pPipelines[i]);
3575 if (r != VK_SUCCESS) {
3576 result = r;
3577 pPipelines[i] = VK_NULL_HANDLE;
3578 }
3579 }
3580
3581 return result;
3582 }
3583
3584
3585 static void
3586 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3587 {
3588 struct radv_shader_variant *compute_shader;
3589 struct radv_device *device = pipeline->device;
3590 unsigned compute_resource_limits;
3591 unsigned waves_per_threadgroup;
3592 uint64_t va;
3593
3594 pipeline->cs.buf = malloc(20 * 4);
3595 pipeline->cs.max_dw = 20;
3596
3597 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3598 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3599
3600 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3601 radeon_emit(&pipeline->cs, va >> 8);
3602 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
3603
3604 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3605 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3606 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3607
3608 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3609 S_00B860_WAVES(pipeline->max_waves) |
3610 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3611
3612 /* Calculate best compute resource limits. */
3613 waves_per_threadgroup =
3614 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3615 compute_shader->info.cs.block_size[1] *
3616 compute_shader->info.cs.block_size[2], 64);
3617 compute_resource_limits =
3618 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3619
3620 if (device->physical_device->rad_info.chip_class >= CIK) {
3621 unsigned num_cu_per_se =
3622 device->physical_device->rad_info.num_good_compute_units /
3623 device->physical_device->rad_info.max_se;
3624
3625 /* Force even distribution on all SIMDs in CU if the workgroup
3626 * size is 64. This has shown some good improvements if # of
3627 * CUs per SE is not a multiple of 4.
3628 */
3629 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3630 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3631 }
3632
3633 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3634 compute_resource_limits);
3635
3636 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3637 radeon_emit(&pipeline->cs,
3638 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3639 radeon_emit(&pipeline->cs,
3640 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3641 radeon_emit(&pipeline->cs,
3642 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3643
3644 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3645 }
3646
3647 static VkResult radv_compute_pipeline_create(
3648 VkDevice _device,
3649 VkPipelineCache _cache,
3650 const VkComputePipelineCreateInfo* pCreateInfo,
3651 const VkAllocationCallbacks* pAllocator,
3652 VkPipeline* pPipeline)
3653 {
3654 RADV_FROM_HANDLE(radv_device, device, _device);
3655 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3656 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3657 struct radv_pipeline *pipeline;
3658 VkResult result;
3659
3660 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3661 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3662 if (pipeline == NULL)
3663 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3664
3665 pipeline->device = device;
3666 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3667 assert(pipeline->layout);
3668
3669 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3670 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags);
3671
3672 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3673 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3674 result = radv_pipeline_scratch_init(device, pipeline);
3675 if (result != VK_SUCCESS) {
3676 radv_pipeline_destroy(device, pipeline, pAllocator);
3677 return result;
3678 }
3679
3680 radv_compute_generate_pm4(pipeline);
3681
3682 *pPipeline = radv_pipeline_to_handle(pipeline);
3683
3684 return VK_SUCCESS;
3685 }
3686
3687 VkResult radv_CreateComputePipelines(
3688 VkDevice _device,
3689 VkPipelineCache pipelineCache,
3690 uint32_t count,
3691 const VkComputePipelineCreateInfo* pCreateInfos,
3692 const VkAllocationCallbacks* pAllocator,
3693 VkPipeline* pPipelines)
3694 {
3695 VkResult result = VK_SUCCESS;
3696
3697 unsigned i = 0;
3698 for (; i < count; i++) {
3699 VkResult r;
3700 r = radv_compute_pipeline_create(_device, pipelineCache,
3701 &pCreateInfos[i],
3702 pAllocator, &pPipelines[i]);
3703 if (r != VK_SUCCESS) {
3704 result = r;
3705 pPipelines[i] = VK_NULL_HANDLE;
3706 }
3707 }
3708
3709 return result;
3710 }