projects / mesa.git / blob
? search:


75785ec921d040ff59869fada72ed879f53b4a37
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 void radv_shader_variant_destroy(struct radv_device *device,
45 struct radv_shader_variant *variant);
46
47 static const struct nir_shader_compiler_options nir_options = {
48 .vertex_id_zero_based = true,
49 .lower_scmp = true,
50 .lower_flrp32 = true,
51 .lower_fsat = true,
52 .lower_pack_snorm_2x16 = true,
53 .lower_pack_snorm_4x8 = true,
54 .lower_pack_unorm_2x16 = true,
55 .lower_pack_unorm_4x8 = true,
56 .lower_unpack_snorm_2x16 = true,
57 .lower_unpack_snorm_4x8 = true,
58 .lower_unpack_unorm_2x16 = true,
59 .lower_unpack_unorm_4x8 = true,
60 .lower_extract_byte = true,
61 .lower_extract_word = true,
62 };
63
64 VkResult radv_CreateShaderModule(
65 VkDevice _device,
66 const VkShaderModuleCreateInfo* pCreateInfo,
67 const VkAllocationCallbacks* pAllocator,
68 VkShaderModule* pShaderModule)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 struct radv_shader_module *module;
72
73 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
74 assert(pCreateInfo->flags == 0);
75
76 module = vk_alloc2(&device->alloc, pAllocator,
77 sizeof(*module) + pCreateInfo->codeSize, 8,
78 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
79 if (module == NULL)
80 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
81
82 module->nir = NULL;
83 module->size = pCreateInfo->codeSize;
84 memcpy(module->data, pCreateInfo->pCode, module->size);
85
86 _mesa_sha1_compute(module->data, module->size, module->sha1);
87
88 *pShaderModule = radv_shader_module_to_handle(module);
89
90 return VK_SUCCESS;
91 }
92
93 void radv_DestroyShaderModule(
94 VkDevice _device,
95 VkShaderModule _module,
96 const VkAllocationCallbacks* pAllocator)
97 {
98 RADV_FROM_HANDLE(radv_device, device, _device);
99 RADV_FROM_HANDLE(radv_shader_module, module, _module);
100
101 if (!module)
102 return;
103
104 vk_free2(&device->alloc, pAllocator, module);
105 }
106
107 void radv_DestroyPipeline(
108 VkDevice _device,
109 VkPipeline _pipeline,
110 const VkAllocationCallbacks* pAllocator)
111 {
112 RADV_FROM_HANDLE(radv_device, device, _device);
113 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
114
115 if (!_pipeline)
116 return;
117
118 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
119 if (pipeline->shaders[i])
120 radv_shader_variant_destroy(device, pipeline->shaders[i]);
121
122 vk_free2(&device->alloc, pAllocator, pipeline);
123 }
124
125
126 static void
127 radv_optimize_nir(struct nir_shader *shader)
128 {
129 bool progress;
130
131 do {
132 progress = false;
133
134 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
135 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
136 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
137
138 NIR_PASS(progress, shader, nir_copy_prop);
139 NIR_PASS(progress, shader, nir_opt_remove_phis);
140 NIR_PASS(progress, shader, nir_opt_dce);
141 NIR_PASS(progress, shader, nir_opt_dead_cf);
142 NIR_PASS(progress, shader, nir_opt_cse);
143 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
144 NIR_PASS(progress, shader, nir_opt_algebraic);
145 NIR_PASS(progress, shader, nir_opt_constant_folding);
146 NIR_PASS(progress, shader, nir_opt_undef);
147 NIR_PASS(progress, shader, nir_opt_conditional_discard);
148 } while (progress);
149 }
150
151 static nir_shader *
152 radv_shader_compile_to_nir(struct radv_device *device,
153 struct radv_shader_module *module,
154 const char *entrypoint_name,
155 gl_shader_stage stage,
156 const VkSpecializationInfo *spec_info,
157 bool dump)
158 {
159 if (strcmp(entrypoint_name, "main") != 0) {
160 radv_finishme("Multiple shaders per module not really supported");
161 }
162
163 nir_shader *nir;
164 nir_function *entry_point;
165 if (module->nir) {
166 /* Some things such as our meta clear/blit code will give us a NIR
167 * shader directly. In that case, we just ignore the SPIR-V entirely
168 * and just use the NIR shader */
169 nir = module->nir;
170 nir->options = &nir_options;
171 nir_validate_shader(nir);
172
173 assert(exec_list_length(&nir->functions) == 1);
174 struct exec_node *node = exec_list_get_head(&nir->functions);
175 entry_point = exec_node_data(nir_function, node, node);
176 } else {
177 uint32_t *spirv = (uint32_t *) module->data;
178 assert(module->size % 4 == 0);
179
180 uint32_t num_spec_entries = 0;
181 struct nir_spirv_specialization *spec_entries = NULL;
182 if (spec_info && spec_info->mapEntryCount > 0) {
183 num_spec_entries = spec_info->mapEntryCount;
184 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
185 for (uint32_t i = 0; i < num_spec_entries; i++) {
186 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
187 const void *data = spec_info->pData + entry.offset;
188 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
189
190 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
191 spec_entries[i].data = *(const uint32_t *)data;
192 }
193 }
194 const struct nir_spirv_supported_extensions supported_ext = {
195 };
196 entry_point = spirv_to_nir(spirv, module->size / 4,
197 spec_entries, num_spec_entries,
198 stage, entrypoint_name, &supported_ext, &nir_options);
199 nir = entry_point->shader;
200 assert(nir->stage == stage);
201 nir_validate_shader(nir);
202
203 free(spec_entries);
204
205 nir_lower_returns(nir);
206 nir_validate_shader(nir);
207
208 nir_inline_functions(nir);
209 nir_validate_shader(nir);
210
211 /* Pick off the single entrypoint that we want */
212 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
213 if (func != entry_point)
214 exec_node_remove(&func->node);
215 }
216 assert(exec_list_length(&nir->functions) == 1);
217 entry_point->name = ralloc_strdup(entry_point, "main");
218
219 nir_remove_dead_variables(nir, nir_var_shader_in);
220 nir_remove_dead_variables(nir, nir_var_shader_out);
221 nir_remove_dead_variables(nir, nir_var_system_value);
222 nir_validate_shader(nir);
223
224 nir_lower_system_values(nir);
225 nir_validate_shader(nir);
226 }
227
228 /* Vulkan uses the separate-shader linking model */
229 nir->info->separate_shader = true;
230
231 // nir = brw_preprocess_nir(compiler, nir);
232
233 nir_shader_gather_info(nir, entry_point->impl);
234
235 nir_variable_mode indirect_mask = 0;
236 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
237 indirect_mask |= nir_var_shader_in;
238 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
239 indirect_mask |= nir_var_local;
240
241 nir_lower_indirect_derefs(nir, indirect_mask);
242
243 static const nir_lower_tex_options tex_options = {
244 .lower_txp = ~0,
245 };
246
247 nir_lower_tex(nir, &tex_options);
248
249 nir_lower_vars_to_ssa(nir);
250 nir_lower_var_copies(nir);
251 nir_lower_global_vars_to_local(nir);
252 nir_remove_dead_variables(nir, nir_var_local);
253 radv_optimize_nir(nir);
254
255 if (dump)
256 nir_print_shader(nir, stderr);
257
258 return nir;
259 }
260
261 static const char *radv_get_shader_name(struct radv_shader_variant *var,
262 gl_shader_stage stage)
263 {
264 switch (stage) {
265 case MESA_SHADER_VERTEX: return "Vertex Shader as VS";
266 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
267 case MESA_SHADER_COMPUTE: return "Compute Shader";
268 default:
269 return "Unknown shader";
270 };
271
272 }
273 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
274 {
275 unsigned lds_increment = device->instance->physicalDevice.rad_info.chip_class >= CIK ? 512 : 256;
276 struct radv_shader_variant *var;
277 struct ac_shader_config *conf;
278 int i;
279 FILE *file = stderr;
280 unsigned max_simd_waves = 10;
281 unsigned lds_per_wave = 0;
282
283 for (i = 0; i < MESA_SHADER_STAGES; i++) {
284 if (!pipeline->shaders[i])
285 continue;
286 var = pipeline->shaders[i];
287
288 conf = &var->config;
289
290 if (i == MESA_SHADER_FRAGMENT) {
291 lds_per_wave = conf->lds_size * lds_increment +
292 align(var->info.fs.num_interp * 48, lds_increment);
293 }
294
295 if (conf->num_sgprs) {
296 if (device->instance->physicalDevice.rad_info.chip_class >= VI)
297 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
298 else
299 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
300 }
301
302 if (conf->num_vgprs)
303 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
304
305 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
306 * that PS can use.
307 */
308 if (lds_per_wave)
309 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
310
311 fprintf(file, "\n%s:\n",
312 radv_get_shader_name(var, i));
313 if (i == MESA_SHADER_FRAGMENT) {
314 fprintf(file, "*** SHADER CONFIG ***\n"
315 "SPI_PS_INPUT_ADDR = 0x%04x\n"
316 "SPI_PS_INPUT_ENA = 0x%04x\n",
317 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
318 }
319 fprintf(file, "*** SHADER STATS ***\n"
320 "SGPRS: %d\n"
321 "VGPRS: %d\n"
322 "Spilled SGPRs: %d\n"
323 "Spilled VGPRs: %d\n"
324 "Code Size: %d bytes\n"
325 "LDS: %d blocks\n"
326 "Scratch: %d bytes per wave\n"
327 "Max Waves: %d\n"
328 "********************\n\n\n",
329 conf->num_sgprs, conf->num_vgprs,
330 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
331 conf->lds_size, conf->scratch_bytes_per_wave,
332 max_simd_waves);
333 }
334 }
335
336 void radv_shader_variant_destroy(struct radv_device *device,
337 struct radv_shader_variant *variant)
338 {
339 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
340 return;
341
342 device->ws->buffer_destroy(variant->bo);
343 free(variant);
344 }
345
346 static void radv_fill_shader_variant(struct radv_device *device,
347 struct radv_shader_variant *variant,
348 struct ac_shader_binary *binary,
349 gl_shader_stage stage)
350 {
351 variant->code_size = binary->code_size;
352 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
353 unsigned vgpr_comp_cnt = 0;
354
355 if (scratch_enabled)
356 radv_finishme("shader scratch space");
357
358 switch (stage) {
359 case MESA_SHADER_VERTEX:
360 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
361 S_00B12C_SCRATCH_EN(scratch_enabled);
362 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
363 break;
364 case MESA_SHADER_FRAGMENT:
365 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
366 S_00B12C_SCRATCH_EN(scratch_enabled);
367 break;
368 case MESA_SHADER_COMPUTE:
369 variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) |
370 S_00B84C_SCRATCH_EN(scratch_enabled) |
371 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
372 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
373 S_00B84C_TG_SIZE_EN(1) |
374 S_00B84C_LDS_SIZE(variant->config.lds_size);
375 break;
376 default:
377 unreachable("unsupported shader type");
378 break;
379 }
380
381 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
382 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
383 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
384 S_00B848_DX10_CLAMP(1) |
385 S_00B848_FLOAT_MODE(variant->config.float_mode);
386
387 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
388 RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS);
389
390 void *ptr = device->ws->buffer_map(variant->bo);
391 memcpy(ptr, binary->code, binary->code_size);
392 device->ws->buffer_unmap(variant->bo);
393
394
395 }
396
397 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
398 struct nir_shader *shader,
399 struct radv_pipeline_layout *layout,
400 const union ac_shader_variant_key *key,
401 void** code_out,
402 unsigned *code_size_out,
403 bool dump)
404 {
405 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
406 enum radeon_family chip_family = device->instance->physicalDevice.rad_info.family;
407 LLVMTargetMachineRef tm;
408 if (!variant)
409 return NULL;
410
411 struct ac_nir_compiler_options options = {0};
412 options.layout = layout;
413 if (key)
414 options.key = *key;
415
416 struct ac_shader_binary binary;
417
418 options.unsafe_math = env_var_as_boolean("RADV_UNSAFE_MATH", false);
419 options.family = chip_family;
420 options.chip_class = device->instance->physicalDevice.rad_info.chip_class;
421 tm = ac_create_target_machine(chip_family);
422 ac_compile_nir_shader(tm, &binary, &variant->config,
423 &variant->info, shader, &options, dump);
424 LLVMDisposeTargetMachine(tm);
425
426 radv_fill_shader_variant(device, variant, &binary, shader->stage);
427
428 if (code_out) {
429 *code_out = binary.code;
430 *code_size_out = binary.code_size;
431 } else
432 free(binary.code);
433 free(binary.config);
434 free(binary.rodata);
435 free(binary.global_symbol_offsets);
436 free(binary.relocs);
437 free(binary.disasm_string);
438 variant->ref_count = 1;
439 return variant;
440 }
441
442
443 static struct radv_shader_variant *
444 radv_pipeline_compile(struct radv_pipeline *pipeline,
445 struct radv_pipeline_cache *cache,
446 struct radv_shader_module *module,
447 const char *entrypoint,
448 gl_shader_stage stage,
449 const VkSpecializationInfo *spec_info,
450 struct radv_pipeline_layout *layout,
451 const union ac_shader_variant_key *key,
452 bool dump)
453 {
454 unsigned char sha1[20];
455 struct radv_shader_variant *variant;
456 nir_shader *nir;
457 void *code = NULL;
458 unsigned code_size = 0;
459
460 if (module->nir)
461 _mesa_sha1_compute(module->nir->info->name,
462 strlen(module->nir->info->name),
463 module->sha1);
464
465 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key);
466
467 if (cache) {
468 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
469 cache,
470 sha1);
471 if (variant)
472 return variant;
473 }
474
475 nir = radv_shader_compile_to_nir(pipeline->device,
476 module, entrypoint, stage,
477 spec_info, dump);
478 if (nir == NULL)
479 return NULL;
480
481 variant = radv_shader_variant_create(pipeline->device, nir, layout, key,
482 &code, &code_size, dump);
483 if (!module->nir)
484 ralloc_free(nir);
485
486 if (variant && cache)
487 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
488 code, code_size);
489
490 if (code)
491 free(code);
492 return variant;
493 }
494
495 static uint32_t si_translate_blend_function(VkBlendOp op)
496 {
497 switch (op) {
498 case VK_BLEND_OP_ADD:
499 return V_028780_COMB_DST_PLUS_SRC;
500 case VK_BLEND_OP_SUBTRACT:
501 return V_028780_COMB_SRC_MINUS_DST;
502 case VK_BLEND_OP_REVERSE_SUBTRACT:
503 return V_028780_COMB_DST_MINUS_SRC;
504 case VK_BLEND_OP_MIN:
505 return V_028780_COMB_MIN_DST_SRC;
506 case VK_BLEND_OP_MAX:
507 return V_028780_COMB_MAX_DST_SRC;
508 default:
509 return 0;
510 }
511 }
512
513 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
514 {
515 switch (factor) {
516 case VK_BLEND_FACTOR_ZERO:
517 return V_028780_BLEND_ZERO;
518 case VK_BLEND_FACTOR_ONE:
519 return V_028780_BLEND_ONE;
520 case VK_BLEND_FACTOR_SRC_COLOR:
521 return V_028780_BLEND_SRC_COLOR;
522 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
523 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
524 case VK_BLEND_FACTOR_DST_COLOR:
525 return V_028780_BLEND_DST_COLOR;
526 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
527 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
528 case VK_BLEND_FACTOR_SRC_ALPHA:
529 return V_028780_BLEND_SRC_ALPHA;
530 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
531 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
532 case VK_BLEND_FACTOR_DST_ALPHA:
533 return V_028780_BLEND_DST_ALPHA;
534 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
535 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
536 case VK_BLEND_FACTOR_CONSTANT_COLOR:
537 return V_028780_BLEND_CONSTANT_COLOR;
538 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
539 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
540 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
541 return V_028780_BLEND_CONSTANT_ALPHA;
542 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
543 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
544 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
545 return V_028780_BLEND_SRC_ALPHA_SATURATE;
546 case VK_BLEND_FACTOR_SRC1_COLOR:
547 return V_028780_BLEND_SRC1_COLOR;
548 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
549 return V_028780_BLEND_INV_SRC1_COLOR;
550 case VK_BLEND_FACTOR_SRC1_ALPHA:
551 return V_028780_BLEND_SRC1_ALPHA;
552 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
553 return V_028780_BLEND_INV_SRC1_ALPHA;
554 default:
555 return 0;
556 }
557 }
558
559 static bool is_dual_src(VkBlendFactor factor)
560 {
561 switch (factor) {
562 case VK_BLEND_FACTOR_SRC1_COLOR:
563 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
564 case VK_BLEND_FACTOR_SRC1_ALPHA:
565 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
566 return true;
567 default:
568 return false;
569 }
570 }
571
572 static unsigned si_choose_spi_color_format(VkFormat vk_format,
573 bool blend_enable,
574 bool blend_need_alpha)
575 {
576 const struct vk_format_description *desc = vk_format_description(vk_format);
577 unsigned format, ntype, swap;
578
579 /* Alpha is needed for alpha-to-coverage.
580 * Blending may be with or without alpha.
581 */
582 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
583 unsigned alpha = 0; /* exports alpha, but may not support blending */
584 unsigned blend = 0; /* supports blending, but may not export alpha */
585 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
586
587 format = radv_translate_colorformat(vk_format);
588 ntype = radv_translate_color_numformat(vk_format, desc,
589 vk_format_get_first_non_void_channel(vk_format));
590 swap = radv_translate_colorswap(vk_format, false);
591
592 /* Choose the SPI color formats. These are required values for Stoney/RB+.
593 * Other chips have multiple choices, though they are not necessarily better.
594 */
595 switch (format) {
596 case V_028C70_COLOR_5_6_5:
597 case V_028C70_COLOR_1_5_5_5:
598 case V_028C70_COLOR_5_5_5_1:
599 case V_028C70_COLOR_4_4_4_4:
600 case V_028C70_COLOR_10_11_11:
601 case V_028C70_COLOR_11_11_10:
602 case V_028C70_COLOR_8:
603 case V_028C70_COLOR_8_8:
604 case V_028C70_COLOR_8_8_8_8:
605 case V_028C70_COLOR_10_10_10_2:
606 case V_028C70_COLOR_2_10_10_10:
607 if (ntype == V_028C70_NUMBER_UINT)
608 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
609 else if (ntype == V_028C70_NUMBER_SINT)
610 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
611 else
612 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
613 break;
614
615 case V_028C70_COLOR_16:
616 case V_028C70_COLOR_16_16:
617 case V_028C70_COLOR_16_16_16_16:
618 if (ntype == V_028C70_NUMBER_UNORM ||
619 ntype == V_028C70_NUMBER_SNORM) {
620 /* UNORM16 and SNORM16 don't support blending */
621 if (ntype == V_028C70_NUMBER_UNORM)
622 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
623 else
624 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
625
626 /* Use 32 bits per channel for blending. */
627 if (format == V_028C70_COLOR_16) {
628 if (swap == V_028C70_SWAP_STD) { /* R */
629 blend = V_028714_SPI_SHADER_32_R;
630 blend_alpha = V_028714_SPI_SHADER_32_AR;
631 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
632 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
633 else
634 assert(0);
635 } else if (format == V_028C70_COLOR_16_16) {
636 if (swap == V_028C70_SWAP_STD) { /* RG */
637 blend = V_028714_SPI_SHADER_32_GR;
638 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
639 } else if (swap == V_028C70_SWAP_ALT) /* RA */
640 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
641 else
642 assert(0);
643 } else /* 16_16_16_16 */
644 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
645 } else if (ntype == V_028C70_NUMBER_UINT)
646 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
647 else if (ntype == V_028C70_NUMBER_SINT)
648 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
649 else if (ntype == V_028C70_NUMBER_FLOAT)
650 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
651 else
652 assert(0);
653 break;
654
655 case V_028C70_COLOR_32:
656 if (swap == V_028C70_SWAP_STD) { /* R */
657 blend = normal = V_028714_SPI_SHADER_32_R;
658 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
659 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
660 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
661 else
662 assert(0);
663 break;
664
665 case V_028C70_COLOR_32_32:
666 if (swap == V_028C70_SWAP_STD) { /* RG */
667 blend = normal = V_028714_SPI_SHADER_32_GR;
668 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
669 } else if (swap == V_028C70_SWAP_ALT) /* RA */
670 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
671 else
672 assert(0);
673 break;
674
675 case V_028C70_COLOR_32_32_32_32:
676 case V_028C70_COLOR_8_24:
677 case V_028C70_COLOR_24_8:
678 case V_028C70_COLOR_X24_8_32_FLOAT:
679 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
680 break;
681
682 default:
683 unreachable("unhandled blend format");
684 }
685
686 if (blend_enable && blend_need_alpha)
687 return blend_alpha;
688 else if(blend_need_alpha)
689 return alpha;
690 else if(blend_enable)
691 return blend;
692 else
693 return normal;
694 }
695
696 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
697 {
698 unsigned i, cb_shader_mask = 0;
699
700 for (i = 0; i < 8; i++) {
701 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
702 case V_028714_SPI_SHADER_ZERO:
703 break;
704 case V_028714_SPI_SHADER_32_R:
705 cb_shader_mask |= 0x1 << (i * 4);
706 break;
707 case V_028714_SPI_SHADER_32_GR:
708 cb_shader_mask |= 0x3 << (i * 4);
709 break;
710 case V_028714_SPI_SHADER_32_AR:
711 cb_shader_mask |= 0x9 << (i * 4);
712 break;
713 case V_028714_SPI_SHADER_FP16_ABGR:
714 case V_028714_SPI_SHADER_UNORM16_ABGR:
715 case V_028714_SPI_SHADER_SNORM16_ABGR:
716 case V_028714_SPI_SHADER_UINT16_ABGR:
717 case V_028714_SPI_SHADER_SINT16_ABGR:
718 case V_028714_SPI_SHADER_32_ABGR:
719 cb_shader_mask |= 0xf << (i * 4);
720 break;
721 default:
722 assert(0);
723 }
724 }
725 return cb_shader_mask;
726 }
727
728 static void
729 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
730 const VkGraphicsPipelineCreateInfo *pCreateInfo,
731 uint32_t blend_enable,
732 uint32_t blend_need_alpha,
733 bool single_cb_enable,
734 bool blend_mrt0_is_dual_src)
735 {
736 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
737 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
738 struct radv_blend_state *blend = &pipeline->graphics.blend;
739 unsigned col_format = 0;
740
741 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
742 struct radv_render_pass_attachment *attachment;
743 unsigned cf;
744
745 attachment = pass->attachments + subpass->color_attachments[i].attachment;
746
747 cf = si_choose_spi_color_format(attachment->format,
748 blend_enable & (1 << i),
749 blend_need_alpha & (1 << i));
750
751 col_format |= cf << (4 * i);
752 }
753
754 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
755
756 if (blend_mrt0_is_dual_src)
757 col_format |= (col_format & 0xf) << 4;
758 if (!col_format)
759 col_format |= V_028714_SPI_SHADER_32_R;
760 blend->spi_shader_col_format = col_format;
761 }
762
763 static bool
764 format_is_int8(VkFormat format)
765 {
766 const struct vk_format_description *desc = vk_format_description(format);
767 int channel = vk_format_get_first_non_void_channel(format);
768
769 return channel >= 0 && desc->channel[channel].pure_integer &&
770 desc->channel[channel].size == 8;
771 }
772
773 unsigned radv_format_meta_fs_key(VkFormat format)
774 {
775 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
776 bool is_int8 = format_is_int8(format);
777
778 return col_format + (is_int8 ? 3 : 0);
779 }
780
781 static unsigned
782 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
783 {
784 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
785 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
786 unsigned is_int8 = 0;
787
788 for (unsigned i = 0; i < subpass->color_count; ++i) {
789 struct radv_render_pass_attachment *attachment;
790
791 attachment = pass->attachments + subpass->color_attachments[i].attachment;
792
793 if (format_is_int8(attachment->format))
794 is_int8 |= 1 << i;
795 }
796
797 return is_int8;
798 }
799
800 static void
801 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
802 const VkGraphicsPipelineCreateInfo *pCreateInfo,
803 const struct radv_graphics_pipeline_create_info *extra)
804 {
805 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
806 struct radv_blend_state *blend = &pipeline->graphics.blend;
807 unsigned mode = V_028808_CB_NORMAL;
808 uint32_t blend_enable = 0, blend_need_alpha = 0;
809 bool blend_mrt0_is_dual_src = false;
810 int i;
811 bool single_cb_enable = false;
812
813 if (!vkblend)
814 return;
815
816 if (extra && extra->custom_blend_mode) {
817 single_cb_enable = true;
818 mode = extra->custom_blend_mode;
819 }
820 blend->cb_color_control = 0;
821 if (vkblend->logicOpEnable)
822 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
823 else
824 blend->cb_color_control |= S_028808_ROP3(0xcc);
825
826 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
827 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
828 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
829 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
830
831 blend->cb_target_mask = 0;
832 for (i = 0; i < vkblend->attachmentCount; i++) {
833 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
834 unsigned blend_cntl = 0;
835 VkBlendOp eqRGB = att->colorBlendOp;
836 VkBlendFactor srcRGB = att->srcColorBlendFactor;
837 VkBlendFactor dstRGB = att->dstColorBlendFactor;
838 VkBlendOp eqA = att->alphaBlendOp;
839 VkBlendFactor srcA = att->srcAlphaBlendFactor;
840 VkBlendFactor dstA = att->dstAlphaBlendFactor;
841
842 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
843
844 if (!att->colorWriteMask)
845 continue;
846
847 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
848 if (!att->blendEnable) {
849 blend->cb_blend_control[i] = blend_cntl;
850 continue;
851 }
852
853 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
854 if (i == 0)
855 blend_mrt0_is_dual_src = true;
856
857 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
858 srcRGB = VK_BLEND_FACTOR_ONE;
859 dstRGB = VK_BLEND_FACTOR_ONE;
860 }
861 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
862 srcA = VK_BLEND_FACTOR_ONE;
863 dstA = VK_BLEND_FACTOR_ONE;
864 }
865
866 blend_cntl |= S_028780_ENABLE(1);
867
868 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
869 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
870 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
871 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
872 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
873 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
874 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
875 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
876 }
877 blend->cb_blend_control[i] = blend_cntl;
878
879 blend_enable |= 1 << i;
880
881 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
882 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
883 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
884 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
885 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
886 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
887 blend_need_alpha |= 1 << i;
888 }
889 for (i = vkblend->attachmentCount; i < 8; i++)
890 blend->cb_blend_control[i] = 0;
891
892 if (blend->cb_target_mask)
893 blend->cb_color_control |= S_028808_MODE(mode);
894 else
895 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
896
897 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
898 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
899 }
900
901 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
902 {
903 switch (op) {
904 case VK_STENCIL_OP_KEEP:
905 return V_02842C_STENCIL_KEEP;
906 case VK_STENCIL_OP_ZERO:
907 return V_02842C_STENCIL_ZERO;
908 case VK_STENCIL_OP_REPLACE:
909 return V_02842C_STENCIL_REPLACE_TEST;
910 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
911 return V_02842C_STENCIL_ADD_CLAMP;
912 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
913 return V_02842C_STENCIL_SUB_CLAMP;
914 case VK_STENCIL_OP_INVERT:
915 return V_02842C_STENCIL_INVERT;
916 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
917 return V_02842C_STENCIL_ADD_WRAP;
918 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
919 return V_02842C_STENCIL_SUB_WRAP;
920 default:
921 return 0;
922 }
923 }
924 static void
925 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
926 const VkGraphicsPipelineCreateInfo *pCreateInfo,
927 const struct radv_graphics_pipeline_create_info *extra)
928 {
929 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
930 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
931
932 memset(ds, 0, sizeof(*ds));
933 if (!vkds)
934 return;
935 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
936 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
937 S_028800_ZFUNC(vkds->depthCompareOp) |
938 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
939
940 if (vkds->stencilTestEnable) {
941 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
942 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
943 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
944 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
945 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
946
947 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
948 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
949 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
950 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
951 }
952
953 if (extra) {
954
955 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
956 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
957
958 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
959 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
960 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
961 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
962 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
963 }
964 }
965
966 static uint32_t si_translate_fill(VkPolygonMode func)
967 {
968 switch(func) {
969 case VK_POLYGON_MODE_FILL:
970 return V_028814_X_DRAW_TRIANGLES;
971 case VK_POLYGON_MODE_LINE:
972 return V_028814_X_DRAW_LINES;
973 case VK_POLYGON_MODE_POINT:
974 return V_028814_X_DRAW_POINTS;
975 default:
976 assert(0);
977 return V_028814_X_DRAW_POINTS;
978 }
979 }
980 static void
981 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
982 const VkGraphicsPipelineCreateInfo *pCreateInfo)
983 {
984 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
985 struct radv_raster_state *raster = &pipeline->graphics.raster;
986
987 memset(raster, 0, sizeof(*raster));
988
989 raster->spi_interp_control =
990 S_0286D4_FLAT_SHADE_ENA(1) |
991 S_0286D4_PNT_SPRITE_ENA(1) |
992 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
993 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
994 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
995 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
996 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
997
998 raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
999 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1000 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1001 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1002 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1003 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1004 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1005
1006 raster->pa_su_vtx_cntl =
1007 S_028BE4_PIX_CENTER(1) | // TODO verify
1008 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1009 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1010
1011 raster->pa_su_sc_mode_cntl =
1012 S_028814_FACE(vkraster->frontFace) |
1013 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1014 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1015 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1016 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1017 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1018 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1019 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1020 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1021
1022 }
1023
1024 static void
1025 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1026 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1027 {
1028 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1029 struct radv_blend_state *blend = &pipeline->graphics.blend;
1030 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1031 unsigned num_tile_pipes = pipeline->device->instance->physicalDevice.rad_info.num_tile_pipes;
1032 int ps_iter_samples = 1;
1033 uint32_t mask = 0xffff;
1034
1035 ms->num_samples = vkms->rasterizationSamples;
1036
1037 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1038 ps_iter_samples = vkms->rasterizationSamples;
1039 }
1040
1041 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1042 ms->pa_sc_aa_config = 0;
1043 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1044 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1045 ms->pa_sc_mode_cntl_1 =
1046 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1047 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1048 /* always 1: */
1049 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1050 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1051 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1052 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1053 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1054 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1055
1056 if (vkms->rasterizationSamples > 1) {
1057 unsigned log_samples = util_logbase2(vkms->rasterizationSamples);
1058 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1059 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1060 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1061 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1062 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1063 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1064 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1065 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1066 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1067 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1068 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1069 }
1070
1071 if (vkms->alphaToCoverageEnable)
1072 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1073
1074 if (vkms->pSampleMask) {
1075 mask = vkms->pSampleMask[0] & 0xffff;
1076 }
1077
1078 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1079 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1080 }
1081
1082 static uint32_t
1083 si_translate_prim(enum VkPrimitiveTopology topology)
1084 {
1085 switch (topology) {
1086 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1087 return V_008958_DI_PT_POINTLIST;
1088 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1089 return V_008958_DI_PT_LINELIST;
1090 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1091 return V_008958_DI_PT_LINESTRIP;
1092 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1093 return V_008958_DI_PT_TRILIST;
1094 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1095 return V_008958_DI_PT_TRISTRIP;
1096 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1097 return V_008958_DI_PT_TRIFAN;
1098 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1099 return V_008958_DI_PT_LINELIST_ADJ;
1100 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1101 return V_008958_DI_PT_LINESTRIP_ADJ;
1102 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1103 return V_008958_DI_PT_TRILIST_ADJ;
1104 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1105 return V_008958_DI_PT_TRISTRIP_ADJ;
1106 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1107 return V_008958_DI_PT_PATCH;
1108 default:
1109 assert(0);
1110 return 0;
1111 }
1112 }
1113
1114 static uint32_t
1115 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1116 {
1117 switch (topology) {
1118 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1119 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1120 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1121 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1122 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1123 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1124 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1125 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1126 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1127 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1128 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1129 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1130 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1131 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1132 default:
1133 assert(0);
1134 return 0;
1135 }
1136 }
1137
1138 static unsigned si_map_swizzle(unsigned swizzle)
1139 {
1140 switch (swizzle) {
1141 case VK_SWIZZLE_Y:
1142 return V_008F0C_SQ_SEL_Y;
1143 case VK_SWIZZLE_Z:
1144 return V_008F0C_SQ_SEL_Z;
1145 case VK_SWIZZLE_W:
1146 return V_008F0C_SQ_SEL_W;
1147 case VK_SWIZZLE_0:
1148 return V_008F0C_SQ_SEL_0;
1149 case VK_SWIZZLE_1:
1150 return V_008F0C_SQ_SEL_1;
1151 default: /* VK_SWIZZLE_X */
1152 return V_008F0C_SQ_SEL_X;
1153 }
1154 }
1155
1156 static void
1157 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1158 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1159 {
1160 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1161 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1162 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1163
1164 pipeline->dynamic_state = default_dynamic_state;
1165
1166 if (pCreateInfo->pDynamicState) {
1167 /* Remove all of the states that are marked as dynamic */
1168 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1169 for (uint32_t s = 0; s < count; s++)
1170 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1171 }
1172
1173 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1174
1175 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1176 *
1177 * pViewportState is [...] NULL if the pipeline
1178 * has rasterization disabled.
1179 */
1180 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1181 assert(pCreateInfo->pViewportState);
1182
1183 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1184 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1185 typed_memcpy(dynamic->viewport.viewports,
1186 pCreateInfo->pViewportState->pViewports,
1187 pCreateInfo->pViewportState->viewportCount);
1188 }
1189
1190 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1191 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1192 typed_memcpy(dynamic->scissor.scissors,
1193 pCreateInfo->pViewportState->pScissors,
1194 pCreateInfo->pViewportState->scissorCount);
1195 }
1196 }
1197
1198 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1199 assert(pCreateInfo->pRasterizationState);
1200 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1201 }
1202
1203 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1204 assert(pCreateInfo->pRasterizationState);
1205 dynamic->depth_bias.bias =
1206 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1207 dynamic->depth_bias.clamp =
1208 pCreateInfo->pRasterizationState->depthBiasClamp;
1209 dynamic->depth_bias.slope =
1210 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1211 }
1212
1213 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1214 *
1215 * pColorBlendState is [...] NULL if the pipeline has rasterization
1216 * disabled or if the subpass of the render pass the pipeline is
1217 * created against does not use any color attachments.
1218 */
1219 bool uses_color_att = false;
1220 for (unsigned i = 0; i < subpass->color_count; ++i) {
1221 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1222 uses_color_att = true;
1223 break;
1224 }
1225 }
1226
1227 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1228 assert(pCreateInfo->pColorBlendState);
1229 typed_memcpy(dynamic->blend_constants,
1230 pCreateInfo->pColorBlendState->blendConstants, 4);
1231 }
1232
1233 /* If there is no depthstencil attachment, then don't read
1234 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1235 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1236 * no need to override the depthstencil defaults in
1237 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1238 *
1239 * Section 9.2 of the Vulkan 1.0.15 spec says:
1240 *
1241 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1242 * disabled or if the subpass of the render pass the pipeline is created
1243 * against does not use a depth/stencil attachment.
1244 */
1245 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1246 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1247 assert(pCreateInfo->pDepthStencilState);
1248
1249 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1250 dynamic->depth_bounds.min =
1251 pCreateInfo->pDepthStencilState->minDepthBounds;
1252 dynamic->depth_bounds.max =
1253 pCreateInfo->pDepthStencilState->maxDepthBounds;
1254 }
1255
1256 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1257 dynamic->stencil_compare_mask.front =
1258 pCreateInfo->pDepthStencilState->front.compareMask;
1259 dynamic->stencil_compare_mask.back =
1260 pCreateInfo->pDepthStencilState->back.compareMask;
1261 }
1262
1263 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1264 dynamic->stencil_write_mask.front =
1265 pCreateInfo->pDepthStencilState->front.writeMask;
1266 dynamic->stencil_write_mask.back =
1267 pCreateInfo->pDepthStencilState->back.writeMask;
1268 }
1269
1270 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1271 dynamic->stencil_reference.front =
1272 pCreateInfo->pDepthStencilState->front.reference;
1273 dynamic->stencil_reference.back =
1274 pCreateInfo->pDepthStencilState->back.reference;
1275 }
1276 }
1277
1278 pipeline->dynamic_state_mask = states;
1279 }
1280
1281 static union ac_shader_variant_key
1282 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1283 {
1284 union ac_shader_variant_key key;
1285 const VkPipelineVertexInputStateCreateInfo *input_state =
1286 pCreateInfo->pVertexInputState;
1287
1288 memset(&key, 0, sizeof(key));
1289 key.vs.instance_rate_inputs = 0;
1290
1291 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1292 unsigned binding;
1293 binding = input_state->pVertexAttributeDescriptions[i].binding;
1294 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1295 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1296 }
1297 return key;
1298 }
1299
1300 VkResult
1301 radv_pipeline_init(struct radv_pipeline *pipeline,
1302 struct radv_device *device,
1303 struct radv_pipeline_cache *cache,
1304 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1305 const struct radv_graphics_pipeline_create_info *extra,
1306 const VkAllocationCallbacks *alloc)
1307 {
1308 struct radv_shader_module fs_m = {0};
1309
1310 bool dump = getenv("RADV_DUMP_SHADERS");
1311 if (alloc == NULL)
1312 alloc = &device->alloc;
1313
1314 pipeline->device = device;
1315 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1316
1317 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1318 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1319 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1320 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1321 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1322 pStages[stage] = &pCreateInfo->pStages[i];
1323 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1324 }
1325
1326 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1327
1328 /* */
1329 if (modules[MESA_SHADER_VERTEX]) {
1330 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo);
1331
1332 pipeline->shaders[MESA_SHADER_VERTEX] =
1333 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1334 pStages[MESA_SHADER_VERTEX]->pName,
1335 MESA_SHADER_VERTEX,
1336 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1337 pipeline->layout, &key, dump);
1338
1339 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1340 }
1341
1342 if (!modules[MESA_SHADER_FRAGMENT]) {
1343 nir_builder fs_b;
1344 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1345 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
1346 fs_m.nir = fs_b.shader;
1347 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1348 }
1349
1350 if (modules[MESA_SHADER_FRAGMENT]) {
1351 union ac_shader_variant_key key;
1352 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1353 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
1354
1355 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1356
1357 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1358 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1359 stage ? stage->pName : "main",
1360 MESA_SHADER_FRAGMENT,
1361 stage ? stage->pSpecializationInfo : NULL,
1362 pipeline->layout, &key, dump);
1363 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1364 }
1365
1366 if (fs_m.nir)
1367 ralloc_free(fs_m.nir);
1368
1369 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1370 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1371 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1372 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1373 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1374 if (extra && extra->use_rectlist) {
1375 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1376 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1377 }
1378 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1379
1380 const VkPipelineVertexInputStateCreateInfo *vi_info =
1381 pCreateInfo->pVertexInputState;
1382 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1383 const VkVertexInputAttributeDescription *desc =
1384 &vi_info->pVertexAttributeDescriptions[i];
1385 unsigned loc = desc->location;
1386 const struct vk_format_description *format_desc;
1387 int first_non_void;
1388 uint32_t num_format, data_format;
1389 format_desc = vk_format_description(desc->format);
1390 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1391
1392 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1393 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1394
1395 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
1396 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
1397 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
1398 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
1399 S_008F0C_NUM_FORMAT(num_format) |
1400 S_008F0C_DATA_FORMAT(data_format);
1401 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
1402 pipeline->va_offset[loc] = desc->offset;
1403 pipeline->va_binding[loc] = desc->binding;
1404 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
1405 }
1406
1407 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1408 const VkVertexInputBindingDescription *desc =
1409 &vi_info->pVertexBindingDescriptions[i];
1410
1411 pipeline->binding_stride[desc->binding] = desc->stride;
1412 }
1413
1414 if (device->shader_stats_dump) {
1415 radv_dump_pipeline_stats(device, pipeline);
1416 }
1417
1418 return VK_SUCCESS;
1419 }
1420
1421 VkResult
1422 radv_graphics_pipeline_create(
1423 VkDevice _device,
1424 VkPipelineCache _cache,
1425 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1426 const struct radv_graphics_pipeline_create_info *extra,
1427 const VkAllocationCallbacks *pAllocator,
1428 VkPipeline *pPipeline)
1429 {
1430 RADV_FROM_HANDLE(radv_device, device, _device);
1431 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1432 struct radv_pipeline *pipeline;
1433 VkResult result;
1434
1435 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1436 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1437 if (pipeline == NULL)
1438 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1439
1440 memset(pipeline, 0, sizeof(*pipeline));
1441 result = radv_pipeline_init(pipeline, device, cache,
1442 pCreateInfo, extra, pAllocator);
1443 if (result != VK_SUCCESS) {
1444 vk_free2(&device->alloc, pAllocator, pipeline);
1445 return result;
1446 }
1447
1448 *pPipeline = radv_pipeline_to_handle(pipeline);
1449
1450 return VK_SUCCESS;
1451 }
1452
1453 VkResult radv_CreateGraphicsPipelines(
1454 VkDevice _device,
1455 VkPipelineCache pipelineCache,
1456 uint32_t count,
1457 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1458 const VkAllocationCallbacks* pAllocator,
1459 VkPipeline* pPipelines)
1460 {
1461 VkResult result = VK_SUCCESS;
1462 unsigned i = 0;
1463
1464 for (; i < count; i++) {
1465 VkResult r;
1466 r = radv_graphics_pipeline_create(_device,
1467 pipelineCache,
1468 &pCreateInfos[i],
1469 NULL, pAllocator, &pPipelines[i]);
1470 if (r != VK_SUCCESS) {
1471 result = r;
1472 pPipelines[i] = VK_NULL_HANDLE;
1473 }
1474 }
1475
1476 return result;
1477 }
1478
1479 static VkResult radv_compute_pipeline_create(
1480 VkDevice _device,
1481 VkPipelineCache _cache,
1482 const VkComputePipelineCreateInfo* pCreateInfo,
1483 const VkAllocationCallbacks* pAllocator,
1484 VkPipeline* pPipeline)
1485 {
1486 RADV_FROM_HANDLE(radv_device, device, _device);
1487 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1488 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
1489 struct radv_pipeline *pipeline;
1490 bool dump = getenv("RADV_DUMP_SHADERS");
1491
1492 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1493 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1494 if (pipeline == NULL)
1495 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1496
1497 memset(pipeline, 0, sizeof(*pipeline));
1498 pipeline->device = device;
1499 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1500
1501 pipeline->shaders[MESA_SHADER_COMPUTE] =
1502 radv_pipeline_compile(pipeline, cache, module,
1503 pCreateInfo->stage.pName,
1504 MESA_SHADER_COMPUTE,
1505 pCreateInfo->stage.pSpecializationInfo,
1506 pipeline->layout, NULL, dump);
1507
1508 *pPipeline = radv_pipeline_to_handle(pipeline);
1509
1510 if (device->shader_stats_dump) {
1511 radv_dump_pipeline_stats(device, pipeline);
1512 }
1513 return VK_SUCCESS;
1514 }
1515 VkResult radv_CreateComputePipelines(
1516 VkDevice _device,
1517 VkPipelineCache pipelineCache,
1518 uint32_t count,
1519 const VkComputePipelineCreateInfo* pCreateInfos,
1520 const VkAllocationCallbacks* pAllocator,
1521 VkPipeline* pPipelines)
1522 {
1523 VkResult result = VK_SUCCESS;
1524
1525 unsigned i = 0;
1526 for (; i < count; i++) {
1527 VkResult r;
1528 r = radv_compute_pipeline_create(_device, pipelineCache,
1529 &pCreateInfos[i],
1530 pAllocator, &pPipelines[i]);
1531 if (r != VK_SUCCESS) {
1532 result = r;
1533 pPipelines[i] = VK_NULL_HANDLE;
1534 }
1535 }
1536
1537 return result;
1538 }