2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 void radv_shader_variant_destroy(struct radv_device
*device
,
45 struct radv_shader_variant
*variant
);
47 static const struct nir_shader_compiler_options nir_options
= {
48 .vertex_id_zero_based
= true,
52 .lower_pack_snorm_2x16
= true,
53 .lower_pack_snorm_4x8
= true,
54 .lower_pack_unorm_2x16
= true,
55 .lower_pack_unorm_4x8
= true,
56 .lower_unpack_snorm_2x16
= true,
57 .lower_unpack_snorm_4x8
= true,
58 .lower_unpack_unorm_2x16
= true,
59 .lower_unpack_unorm_4x8
= true,
60 .lower_extract_byte
= true,
61 .lower_extract_word
= true,
64 VkResult
radv_CreateShaderModule(
66 const VkShaderModuleCreateInfo
* pCreateInfo
,
67 const VkAllocationCallbacks
* pAllocator
,
68 VkShaderModule
* pShaderModule
)
70 RADV_FROM_HANDLE(radv_device
, device
, _device
);
71 struct radv_shader_module
*module
;
73 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
74 assert(pCreateInfo
->flags
== 0);
76 module
= vk_alloc2(&device
->alloc
, pAllocator
,
77 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
78 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
80 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
83 module
->size
= pCreateInfo
->codeSize
;
84 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
86 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
88 *pShaderModule
= radv_shader_module_to_handle(module
);
93 void radv_DestroyShaderModule(
95 VkShaderModule _module
,
96 const VkAllocationCallbacks
* pAllocator
)
98 RADV_FROM_HANDLE(radv_device
, device
, _device
);
99 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
104 vk_free2(&device
->alloc
, pAllocator
, module
);
107 void radv_DestroyPipeline(
109 VkPipeline _pipeline
,
110 const VkAllocationCallbacks
* pAllocator
)
112 RADV_FROM_HANDLE(radv_device
, device
, _device
);
113 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
118 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
119 if (pipeline
->shaders
[i
])
120 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
122 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
127 radv_optimize_nir(struct nir_shader
*shader
)
134 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
135 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
136 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
138 NIR_PASS(progress
, shader
, nir_copy_prop
);
139 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
140 NIR_PASS(progress
, shader
, nir_opt_dce
);
141 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
142 NIR_PASS(progress
, shader
, nir_opt_cse
);
143 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8);
144 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
145 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
146 NIR_PASS(progress
, shader
, nir_opt_undef
);
147 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
152 radv_shader_compile_to_nir(struct radv_device
*device
,
153 struct radv_shader_module
*module
,
154 const char *entrypoint_name
,
155 gl_shader_stage stage
,
156 const VkSpecializationInfo
*spec_info
,
159 if (strcmp(entrypoint_name
, "main") != 0) {
160 radv_finishme("Multiple shaders per module not really supported");
164 nir_function
*entry_point
;
166 /* Some things such as our meta clear/blit code will give us a NIR
167 * shader directly. In that case, we just ignore the SPIR-V entirely
168 * and just use the NIR shader */
170 nir
->options
= &nir_options
;
171 nir_validate_shader(nir
);
173 assert(exec_list_length(&nir
->functions
) == 1);
174 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
175 entry_point
= exec_node_data(nir_function
, node
, node
);
177 uint32_t *spirv
= (uint32_t *) module
->data
;
178 assert(module
->size
% 4 == 0);
180 uint32_t num_spec_entries
= 0;
181 struct nir_spirv_specialization
*spec_entries
= NULL
;
182 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
183 num_spec_entries
= spec_info
->mapEntryCount
;
184 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
185 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
186 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
187 const void *data
= spec_info
->pData
+ entry
.offset
;
188 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
190 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
191 spec_entries
[i
].data
= *(const uint32_t *)data
;
195 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
196 spec_entries
, num_spec_entries
,
197 stage
, entrypoint_name
, &nir_options
);
198 nir
= entry_point
->shader
;
199 assert(nir
->stage
== stage
);
200 nir_validate_shader(nir
);
204 nir_lower_returns(nir
);
205 nir_validate_shader(nir
);
207 nir_inline_functions(nir
);
208 nir_validate_shader(nir
);
210 /* Pick off the single entrypoint that we want */
211 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
212 if (func
!= entry_point
)
213 exec_node_remove(&func
->node
);
215 assert(exec_list_length(&nir
->functions
) == 1);
216 entry_point
->name
= ralloc_strdup(entry_point
, "main");
218 nir_remove_dead_variables(nir
, nir_var_shader_in
);
219 nir_remove_dead_variables(nir
, nir_var_shader_out
);
220 nir_remove_dead_variables(nir
, nir_var_system_value
);
221 nir_validate_shader(nir
);
223 nir_lower_system_values(nir
);
224 nir_validate_shader(nir
);
227 /* Vulkan uses the separate-shader linking model */
228 nir
->info
->separate_shader
= true;
230 // nir = brw_preprocess_nir(compiler, nir);
232 nir_shader_gather_info(nir
, entry_point
->impl
);
234 nir_variable_mode indirect_mask
= 0;
235 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
236 indirect_mask
|= nir_var_shader_in
;
237 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
238 indirect_mask
|= nir_var_local
;
240 nir_lower_indirect_derefs(nir
, indirect_mask
);
242 static const nir_lower_tex_options tex_options
= {
246 nir_lower_tex(nir
, &tex_options
);
248 nir_lower_vars_to_ssa(nir
);
249 nir_lower_var_copies(nir
);
250 nir_lower_global_vars_to_local(nir
);
251 nir_remove_dead_variables(nir
, nir_var_local
);
252 radv_optimize_nir(nir
);
255 nir_print_shader(nir
, stderr
);
260 static const char *radv_get_shader_name(struct radv_shader_variant
*var
,
261 gl_shader_stage stage
)
264 case MESA_SHADER_VERTEX
: return "Vertex Shader as VS";
265 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
266 case MESA_SHADER_COMPUTE
: return "Compute Shader";
268 return "Unknown shader";
272 static void radv_dump_pipeline_stats(struct radv_device
*device
, struct radv_pipeline
*pipeline
)
274 unsigned lds_increment
= device
->instance
->physicalDevice
.rad_info
.chip_class
>= CIK
? 512 : 256;
275 struct radv_shader_variant
*var
;
276 struct ac_shader_config
*conf
;
279 unsigned max_simd_waves
= 10;
280 unsigned lds_per_wave
= 0;
282 for (i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
283 if (!pipeline
->shaders
[i
])
285 var
= pipeline
->shaders
[i
];
289 if (i
== MESA_SHADER_FRAGMENT
) {
290 lds_per_wave
= conf
->lds_size
* lds_increment
+
291 align(var
->info
.fs
.num_interp
* 48, lds_increment
);
294 if (conf
->num_sgprs
) {
295 if (device
->instance
->physicalDevice
.rad_info
.chip_class
>= VI
)
296 max_simd_waves
= MIN2(max_simd_waves
, 800 / conf
->num_sgprs
);
298 max_simd_waves
= MIN2(max_simd_waves
, 512 / conf
->num_sgprs
);
302 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
304 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
308 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
310 fprintf(file
, "\n%s:\n",
311 radv_get_shader_name(var
, i
));
312 if (i
== MESA_SHADER_FRAGMENT
) {
313 fprintf(file
, "*** SHADER CONFIG ***\n"
314 "SPI_PS_INPUT_ADDR = 0x%04x\n"
315 "SPI_PS_INPUT_ENA = 0x%04x\n",
316 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
318 fprintf(file
, "*** SHADER STATS ***\n"
321 "Spilled SGPRs: %d\n"
322 "Spilled VGPRs: %d\n"
323 "Code Size: %d bytes\n"
325 "Scratch: %d bytes per wave\n"
327 "********************\n\n\n",
328 conf
->num_sgprs
, conf
->num_vgprs
,
329 conf
->spilled_sgprs
, conf
->spilled_vgprs
, var
->code_size
,
330 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
335 void radv_shader_variant_destroy(struct radv_device
*device
,
336 struct radv_shader_variant
*variant
)
338 if (__sync_fetch_and_sub(&variant
->ref_count
, 1) != 1)
341 device
->ws
->buffer_destroy(variant
->bo
);
346 struct radv_shader_variant
*radv_shader_variant_create(struct radv_device
*device
,
347 struct nir_shader
*shader
,
348 struct radv_pipeline_layout
*layout
,
349 const union ac_shader_variant_key
*key
,
351 unsigned *code_size_out
,
354 struct radv_shader_variant
*variant
= calloc(1, sizeof(struct radv_shader_variant
));
355 enum radeon_family chip_family
= device
->instance
->physicalDevice
.rad_info
.family
;
356 LLVMTargetMachineRef tm
;
360 struct ac_nir_compiler_options options
= {0};
361 options
.layout
= layout
;
365 struct ac_shader_binary binary
;
367 options
.unsafe_math
= env_var_as_boolean("RADV_UNSAFE_MATH", false);
368 options
.family
= chip_family
;
369 options
.chip_class
= device
->instance
->physicalDevice
.rad_info
.chip_class
;
370 tm
= ac_create_target_machine(chip_family
);
371 ac_compile_nir_shader(tm
, &binary
, &variant
->config
,
372 &variant
->info
, shader
, &options
, dump
);
373 LLVMDisposeTargetMachine(tm
);
375 variant
->code_size
= binary
.code_size
;
376 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
377 unsigned vgpr_comp_cnt
= 0;
380 radv_finishme("shader scratch space");
381 switch (shader
->stage
) {
382 case MESA_SHADER_VERTEX
:
383 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
384 S_00B12C_SCRATCH_EN(scratch_enabled
);
385 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
387 case MESA_SHADER_FRAGMENT
:
388 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
389 S_00B12C_SCRATCH_EN(scratch_enabled
);
391 case MESA_SHADER_COMPUTE
:
392 variant
->rsrc2
= S_00B84C_USER_SGPR(variant
->info
.num_user_sgprs
) |
393 S_00B84C_SCRATCH_EN(scratch_enabled
) |
394 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
395 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
396 S_00B84C_TG_SIZE_EN(1) |
397 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
400 unreachable("unsupported shader type");
404 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
405 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
406 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
407 S_00B848_DX10_CLAMP(1) |
408 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
410 variant
->bo
= device
->ws
->buffer_create(device
->ws
, binary
.code_size
, 256,
411 RADEON_DOMAIN_GTT
, RADEON_FLAG_CPU_ACCESS
);
413 void *ptr
= device
->ws
->buffer_map(variant
->bo
);
414 memcpy(ptr
, binary
.code
, binary
.code_size
);
415 device
->ws
->buffer_unmap(variant
->bo
);
418 *code_out
= binary
.code
;
419 *code_size_out
= binary
.code_size
;
424 free(binary
.global_symbol_offsets
);
426 free(binary
.disasm_string
);
427 variant
->ref_count
= 1;
432 static struct radv_shader_variant
*
433 radv_pipeline_compile(struct radv_pipeline
*pipeline
,
434 struct radv_pipeline_cache
*cache
,
435 struct radv_shader_module
*module
,
436 const char *entrypoint
,
437 gl_shader_stage stage
,
438 const VkSpecializationInfo
*spec_info
,
439 struct radv_pipeline_layout
*layout
,
440 const union ac_shader_variant_key
*key
,
443 unsigned char sha1
[20];
444 struct radv_shader_variant
*variant
;
447 unsigned code_size
= 0;
450 _mesa_sha1_compute(module
->nir
->info
->name
,
451 strlen(module
->nir
->info
->name
),
454 radv_hash_shader(sha1
, module
, entrypoint
, spec_info
, layout
, key
);
457 variant
= radv_create_shader_variant_from_pipeline_cache(pipeline
->device
,
464 nir
= radv_shader_compile_to_nir(pipeline
->device
,
465 module
, entrypoint
, stage
,
470 variant
= radv_shader_variant_create(pipeline
->device
, nir
, layout
, key
,
471 &code
, &code_size
, dump
);
475 if (variant
&& cache
)
476 variant
= radv_pipeline_cache_insert_shader(cache
, sha1
, variant
,
484 static uint32_t si_translate_blend_function(VkBlendOp op
)
487 case VK_BLEND_OP_ADD
:
488 return V_028780_COMB_DST_PLUS_SRC
;
489 case VK_BLEND_OP_SUBTRACT
:
490 return V_028780_COMB_SRC_MINUS_DST
;
491 case VK_BLEND_OP_REVERSE_SUBTRACT
:
492 return V_028780_COMB_DST_MINUS_SRC
;
493 case VK_BLEND_OP_MIN
:
494 return V_028780_COMB_MIN_DST_SRC
;
495 case VK_BLEND_OP_MAX
:
496 return V_028780_COMB_MAX_DST_SRC
;
502 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
505 case VK_BLEND_FACTOR_ZERO
:
506 return V_028780_BLEND_ZERO
;
507 case VK_BLEND_FACTOR_ONE
:
508 return V_028780_BLEND_ONE
;
509 case VK_BLEND_FACTOR_SRC_COLOR
:
510 return V_028780_BLEND_SRC_COLOR
;
511 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
512 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
513 case VK_BLEND_FACTOR_DST_COLOR
:
514 return V_028780_BLEND_DST_COLOR
;
515 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
516 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
517 case VK_BLEND_FACTOR_SRC_ALPHA
:
518 return V_028780_BLEND_SRC_ALPHA
;
519 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
520 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
521 case VK_BLEND_FACTOR_DST_ALPHA
:
522 return V_028780_BLEND_DST_ALPHA
;
523 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
524 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
525 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
526 return V_028780_BLEND_CONSTANT_COLOR
;
527 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
528 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
529 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
530 return V_028780_BLEND_CONSTANT_ALPHA
;
531 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
532 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
533 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
534 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
535 case VK_BLEND_FACTOR_SRC1_COLOR
:
536 return V_028780_BLEND_SRC1_COLOR
;
537 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
538 return V_028780_BLEND_INV_SRC1_COLOR
;
539 case VK_BLEND_FACTOR_SRC1_ALPHA
:
540 return V_028780_BLEND_SRC1_ALPHA
;
541 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
542 return V_028780_BLEND_INV_SRC1_ALPHA
;
548 static bool is_dual_src(VkBlendFactor factor
)
551 case VK_BLEND_FACTOR_SRC1_COLOR
:
552 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
553 case VK_BLEND_FACTOR_SRC1_ALPHA
:
554 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
561 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
563 bool blend_need_alpha
)
565 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
566 unsigned format
, ntype
, swap
;
568 /* Alpha is needed for alpha-to-coverage.
569 * Blending may be with or without alpha.
571 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
572 unsigned alpha
= 0; /* exports alpha, but may not support blending */
573 unsigned blend
= 0; /* supports blending, but may not export alpha */
574 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
576 format
= radv_translate_colorformat(vk_format
);
577 ntype
= radv_translate_color_numformat(vk_format
, desc
,
578 vk_format_get_first_non_void_channel(vk_format
));
579 swap
= radv_translate_colorswap(vk_format
, false);
581 /* Choose the SPI color formats. These are required values for Stoney/RB+.
582 * Other chips have multiple choices, though they are not necessarily better.
585 case V_028C70_COLOR_5_6_5
:
586 case V_028C70_COLOR_1_5_5_5
:
587 case V_028C70_COLOR_5_5_5_1
:
588 case V_028C70_COLOR_4_4_4_4
:
589 case V_028C70_COLOR_10_11_11
:
590 case V_028C70_COLOR_11_11_10
:
591 case V_028C70_COLOR_8
:
592 case V_028C70_COLOR_8_8
:
593 case V_028C70_COLOR_8_8_8_8
:
594 case V_028C70_COLOR_10_10_10_2
:
595 case V_028C70_COLOR_2_10_10_10
:
596 if (ntype
== V_028C70_NUMBER_UINT
)
597 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
598 else if (ntype
== V_028C70_NUMBER_SINT
)
599 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
601 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
604 case V_028C70_COLOR_16
:
605 case V_028C70_COLOR_16_16
:
606 case V_028C70_COLOR_16_16_16_16
:
607 if (ntype
== V_028C70_NUMBER_UNORM
||
608 ntype
== V_028C70_NUMBER_SNORM
) {
609 /* UNORM16 and SNORM16 don't support blending */
610 if (ntype
== V_028C70_NUMBER_UNORM
)
611 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
613 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
615 /* Use 32 bits per channel for blending. */
616 if (format
== V_028C70_COLOR_16
) {
617 if (swap
== V_028C70_SWAP_STD
) { /* R */
618 blend
= V_028714_SPI_SHADER_32_R
;
619 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
620 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
621 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
624 } else if (format
== V_028C70_COLOR_16_16
) {
625 if (swap
== V_028C70_SWAP_STD
) { /* RG */
626 blend
= V_028714_SPI_SHADER_32_GR
;
627 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
628 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
629 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
632 } else /* 16_16_16_16 */
633 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
634 } else if (ntype
== V_028C70_NUMBER_UINT
)
635 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
636 else if (ntype
== V_028C70_NUMBER_SINT
)
637 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
638 else if (ntype
== V_028C70_NUMBER_FLOAT
)
639 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
644 case V_028C70_COLOR_32
:
645 if (swap
== V_028C70_SWAP_STD
) { /* R */
646 blend
= normal
= V_028714_SPI_SHADER_32_R
;
647 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
648 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
649 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
654 case V_028C70_COLOR_32_32
:
655 if (swap
== V_028C70_SWAP_STD
) { /* RG */
656 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
657 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
658 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
659 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
664 case V_028C70_COLOR_32_32_32_32
:
665 case V_028C70_COLOR_8_24
:
666 case V_028C70_COLOR_24_8
:
667 case V_028C70_COLOR_X24_8_32_FLOAT
:
668 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
672 unreachable("unhandled blend format");
675 if (blend_enable
&& blend_need_alpha
)
677 else if(blend_need_alpha
)
679 else if(blend_enable
)
685 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
687 unsigned i
, cb_shader_mask
= 0;
689 for (i
= 0; i
< 8; i
++) {
690 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
691 case V_028714_SPI_SHADER_ZERO
:
693 case V_028714_SPI_SHADER_32_R
:
694 cb_shader_mask
|= 0x1 << (i
* 4);
696 case V_028714_SPI_SHADER_32_GR
:
697 cb_shader_mask
|= 0x3 << (i
* 4);
699 case V_028714_SPI_SHADER_32_AR
:
700 cb_shader_mask
|= 0x9 << (i
* 4);
702 case V_028714_SPI_SHADER_FP16_ABGR
:
703 case V_028714_SPI_SHADER_UNORM16_ABGR
:
704 case V_028714_SPI_SHADER_SNORM16_ABGR
:
705 case V_028714_SPI_SHADER_UINT16_ABGR
:
706 case V_028714_SPI_SHADER_SINT16_ABGR
:
707 case V_028714_SPI_SHADER_32_ABGR
:
708 cb_shader_mask
|= 0xf << (i
* 4);
714 return cb_shader_mask
;
718 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
719 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
720 uint32_t blend_enable
,
721 uint32_t blend_need_alpha
,
722 bool single_cb_enable
,
723 bool blend_mrt0_is_dual_src
)
725 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
726 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
727 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
728 unsigned col_format
= 0;
730 for (unsigned i
= 0; i
< (single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
731 struct radv_render_pass_attachment
*attachment
;
734 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
736 cf
= si_choose_spi_color_format(attachment
->format
,
737 blend_enable
& (1 << i
),
738 blend_need_alpha
& (1 << i
));
740 col_format
|= cf
<< (4 * i
);
743 blend
->cb_shader_mask
= si_get_cb_shader_mask(col_format
);
745 if (blend_mrt0_is_dual_src
)
746 col_format
|= (col_format
& 0xf) << 4;
748 col_format
|= V_028714_SPI_SHADER_32_R
;
749 blend
->spi_shader_col_format
= col_format
;
753 format_is_int8(VkFormat format
)
755 const struct vk_format_description
*desc
= vk_format_description(format
);
756 int channel
= vk_format_get_first_non_void_channel(format
);
758 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
759 desc
->channel
[channel
].size
== 8;
762 unsigned radv_format_meta_fs_key(VkFormat format
)
764 unsigned col_format
= si_choose_spi_color_format(format
, false, false) - 1;
765 bool is_int8
= format_is_int8(format
);
767 return col_format
+ (is_int8
? 3 : 0);
771 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
773 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
774 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
775 unsigned is_int8
= 0;
777 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
778 struct radv_render_pass_attachment
*attachment
;
780 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
782 if (format_is_int8(attachment
->format
))
790 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
791 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
792 const struct radv_graphics_pipeline_create_info
*extra
)
794 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
795 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
796 unsigned mode
= V_028808_CB_NORMAL
;
797 uint32_t blend_enable
= 0, blend_need_alpha
= 0;
798 bool blend_mrt0_is_dual_src
= false;
800 bool single_cb_enable
= false;
805 if (extra
&& extra
->custom_blend_mode
) {
806 single_cb_enable
= true;
807 mode
= extra
->custom_blend_mode
;
809 blend
->cb_color_control
= 0;
810 if (vkblend
->logicOpEnable
)
811 blend
->cb_color_control
|= S_028808_ROP3(vkblend
->logicOp
| (vkblend
->logicOp
<< 4));
813 blend
->cb_color_control
|= S_028808_ROP3(0xcc);
815 blend
->db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
816 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
817 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
818 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
820 blend
->cb_target_mask
= 0;
821 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
822 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
823 unsigned blend_cntl
= 0;
824 VkBlendOp eqRGB
= att
->colorBlendOp
;
825 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
826 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
827 VkBlendOp eqA
= att
->alphaBlendOp
;
828 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
829 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
831 blend
->sx_mrt0_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
833 if (!att
->colorWriteMask
)
836 blend
->cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
837 if (!att
->blendEnable
) {
838 blend
->cb_blend_control
[i
] = blend_cntl
;
842 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
844 blend_mrt0_is_dual_src
= true;
846 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
847 srcRGB
= VK_BLEND_FACTOR_ONE
;
848 dstRGB
= VK_BLEND_FACTOR_ONE
;
850 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
851 srcA
= VK_BLEND_FACTOR_ONE
;
852 dstA
= VK_BLEND_FACTOR_ONE
;
855 blend_cntl
|= S_028780_ENABLE(1);
857 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
858 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
859 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
860 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
861 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
862 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
863 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
864 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
866 blend
->cb_blend_control
[i
] = blend_cntl
;
868 blend_enable
|= 1 << i
;
870 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
871 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
872 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
873 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
874 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
875 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
876 blend_need_alpha
|= 1 << i
;
878 for (i
= vkblend
->attachmentCount
; i
< 8; i
++)
879 blend
->cb_blend_control
[i
] = 0;
881 if (blend
->cb_target_mask
)
882 blend
->cb_color_control
|= S_028808_MODE(mode
);
884 blend
->cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
886 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
,
887 blend_enable
, blend_need_alpha
, single_cb_enable
, blend_mrt0_is_dual_src
);
890 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
893 case VK_STENCIL_OP_KEEP
:
894 return V_02842C_STENCIL_KEEP
;
895 case VK_STENCIL_OP_ZERO
:
896 return V_02842C_STENCIL_ZERO
;
897 case VK_STENCIL_OP_REPLACE
:
898 return V_02842C_STENCIL_REPLACE_TEST
;
899 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
900 return V_02842C_STENCIL_ADD_CLAMP
;
901 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
902 return V_02842C_STENCIL_SUB_CLAMP
;
903 case VK_STENCIL_OP_INVERT
:
904 return V_02842C_STENCIL_INVERT
;
905 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
906 return V_02842C_STENCIL_ADD_WRAP
;
907 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
908 return V_02842C_STENCIL_SUB_WRAP
;
914 radv_pipeline_init_depth_stencil_state(struct radv_pipeline
*pipeline
,
915 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
916 const struct radv_graphics_pipeline_create_info
*extra
)
918 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
919 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
921 memset(ds
, 0, sizeof(*ds
));
924 ds
->db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
925 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
926 S_028800_ZFUNC(vkds
->depthCompareOp
) |
927 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
929 if (vkds
->stencilTestEnable
) {
930 ds
->db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
931 ds
->db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
932 ds
->db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
933 ds
->db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
934 ds
->db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
936 ds
->db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
937 ds
->db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
938 ds
->db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
939 ds
->db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
944 ds
->db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
945 ds
->db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
947 ds
->db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
948 ds
->db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
949 ds
->db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
950 ds
->db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
951 ds
->db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
955 static uint32_t si_translate_fill(VkPolygonMode func
)
958 case VK_POLYGON_MODE_FILL
:
959 return V_028814_X_DRAW_TRIANGLES
;
960 case VK_POLYGON_MODE_LINE
:
961 return V_028814_X_DRAW_LINES
;
962 case VK_POLYGON_MODE_POINT
:
963 return V_028814_X_DRAW_POINTS
;
966 return V_028814_X_DRAW_POINTS
;
970 radv_pipeline_init_raster_state(struct radv_pipeline
*pipeline
,
971 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
973 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
974 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
976 memset(raster
, 0, sizeof(*raster
));
978 raster
->spi_interp_control
=
979 S_0286D4_FLAT_SHADE_ENA(1) |
980 S_0286D4_PNT_SPRITE_ENA(1) |
981 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
982 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
983 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
984 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
985 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
987 raster
->pa_cl_vs_out_cntl
= S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
988 raster
->pa_cl_clip_cntl
= S_028810_PS_UCP_MODE(3) |
989 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
990 S_028810_ZCLIP_NEAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
991 S_028810_ZCLIP_FAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
992 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
993 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
995 raster
->pa_su_vtx_cntl
=
996 S_028BE4_PIX_CENTER(1) | // TODO verify
997 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
998 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
);
1000 raster
->pa_su_sc_mode_cntl
=
1001 S_028814_FACE(vkraster
->frontFace
) |
1002 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
1003 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
1004 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
1005 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
1006 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
1007 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
1008 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
1009 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0);
1014 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1015 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1017 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
1018 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
1019 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1020 unsigned num_tile_pipes
= pipeline
->device
->instance
->physicalDevice
.rad_info
.num_tile_pipes
;
1021 int ps_iter_samples
= 1;
1022 uint32_t mask
= 0xffff;
1024 ms
->num_samples
= vkms
->rasterizationSamples
;
1025 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1026 ms
->pa_sc_aa_config
= 0;
1027 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1028 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1029 ms
->pa_sc_mode_cntl_1
=
1030 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1031 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1033 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1034 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1035 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1036 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1037 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1038 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1040 if (vkms
->rasterizationSamples
> 1) {
1041 unsigned log_samples
= util_logbase2(vkms
->rasterizationSamples
);
1042 unsigned log_ps_iter_samples
= util_logbase2(util_next_power_of_two(ps_iter_samples
));
1043 ms
->pa_sc_mode_cntl_0
= S_028A48_MSAA_ENABLE(1);
1044 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1045 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1046 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1047 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1048 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1049 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1050 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples
)) |
1051 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1052 ms
->pa_sc_mode_cntl_1
|= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1055 if (vkms
->alphaToCoverageEnable
)
1056 blend
->db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1058 if (vkms
->pSampleMask
) {
1059 mask
= vkms
->pSampleMask
[0] & 0xffff;
1062 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1063 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1067 si_translate_prim(enum VkPrimitiveTopology topology
)
1070 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1071 return V_008958_DI_PT_POINTLIST
;
1072 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1073 return V_008958_DI_PT_LINELIST
;
1074 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1075 return V_008958_DI_PT_LINESTRIP
;
1076 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1077 return V_008958_DI_PT_TRILIST
;
1078 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1079 return V_008958_DI_PT_TRISTRIP
;
1080 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1081 return V_008958_DI_PT_TRIFAN
;
1082 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1083 return V_008958_DI_PT_LINELIST_ADJ
;
1084 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1085 return V_008958_DI_PT_LINESTRIP_ADJ
;
1086 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1087 return V_008958_DI_PT_TRILIST_ADJ
;
1088 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1089 return V_008958_DI_PT_TRISTRIP_ADJ
;
1090 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1091 return V_008958_DI_PT_PATCH
;
1099 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1102 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1103 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1104 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1105 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1106 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1107 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1108 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1109 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1110 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1111 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1112 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1113 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1114 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1115 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1122 static unsigned si_map_swizzle(unsigned swizzle
)
1126 return V_008F0C_SQ_SEL_Y
;
1128 return V_008F0C_SQ_SEL_Z
;
1130 return V_008F0C_SQ_SEL_W
;
1132 return V_008F0C_SQ_SEL_0
;
1134 return V_008F0C_SQ_SEL_1
;
1135 default: /* VK_SWIZZLE_X */
1136 return V_008F0C_SQ_SEL_X
;
1141 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1142 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1144 radv_cmd_dirty_mask_t states
= RADV_CMD_DIRTY_DYNAMIC_ALL
;
1145 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1146 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1148 pipeline
->dynamic_state
= default_dynamic_state
;
1150 if (pCreateInfo
->pDynamicState
) {
1151 /* Remove all of the states that are marked as dynamic */
1152 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1153 for (uint32_t s
= 0; s
< count
; s
++)
1154 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1157 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1159 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1161 * pViewportState is [...] NULL if the pipeline
1162 * has rasterization disabled.
1164 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1165 assert(pCreateInfo
->pViewportState
);
1167 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1168 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1169 typed_memcpy(dynamic
->viewport
.viewports
,
1170 pCreateInfo
->pViewportState
->pViewports
,
1171 pCreateInfo
->pViewportState
->viewportCount
);
1174 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1175 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1176 typed_memcpy(dynamic
->scissor
.scissors
,
1177 pCreateInfo
->pViewportState
->pScissors
,
1178 pCreateInfo
->pViewportState
->scissorCount
);
1182 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1183 assert(pCreateInfo
->pRasterizationState
);
1184 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1187 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1188 assert(pCreateInfo
->pRasterizationState
);
1189 dynamic
->depth_bias
.bias
=
1190 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1191 dynamic
->depth_bias
.clamp
=
1192 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1193 dynamic
->depth_bias
.slope
=
1194 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1197 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1199 * pColorBlendState is [...] NULL if the pipeline has rasterization
1200 * disabled or if the subpass of the render pass the pipeline is
1201 * created against does not use any color attachments.
1203 bool uses_color_att
= false;
1204 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1205 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1206 uses_color_att
= true;
1211 if (uses_color_att
&& states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
1212 assert(pCreateInfo
->pColorBlendState
);
1213 typed_memcpy(dynamic
->blend_constants
,
1214 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1217 /* If there is no depthstencil attachment, then don't read
1218 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1219 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1220 * no need to override the depthstencil defaults in
1221 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1223 * Section 9.2 of the Vulkan 1.0.15 spec says:
1225 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1226 * disabled or if the subpass of the render pass the pipeline is created
1227 * against does not use a depth/stencil attachment.
1229 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1230 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1231 assert(pCreateInfo
->pDepthStencilState
);
1233 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1234 dynamic
->depth_bounds
.min
=
1235 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1236 dynamic
->depth_bounds
.max
=
1237 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1240 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1241 dynamic
->stencil_compare_mask
.front
=
1242 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1243 dynamic
->stencil_compare_mask
.back
=
1244 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1247 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1248 dynamic
->stencil_write_mask
.front
=
1249 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1250 dynamic
->stencil_write_mask
.back
=
1251 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1254 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1255 dynamic
->stencil_reference
.front
=
1256 pCreateInfo
->pDepthStencilState
->front
.reference
;
1257 dynamic
->stencil_reference
.back
=
1258 pCreateInfo
->pDepthStencilState
->back
.reference
;
1262 pipeline
->dynamic_state_mask
= states
;
1265 static union ac_shader_variant_key
1266 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1268 union ac_shader_variant_key key
;
1269 const VkPipelineVertexInputStateCreateInfo
*input_state
=
1270 pCreateInfo
->pVertexInputState
;
1272 memset(&key
, 0, sizeof(key
));
1273 key
.vs
.instance_rate_inputs
= 0;
1275 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
1277 binding
= input_state
->pVertexAttributeDescriptions
[i
].binding
;
1278 if (input_state
->pVertexBindingDescriptions
[binding
].inputRate
)
1279 key
.vs
.instance_rate_inputs
|= 1u << input_state
->pVertexAttributeDescriptions
[i
].location
;
1285 radv_pipeline_init(struct radv_pipeline
*pipeline
,
1286 struct radv_device
*device
,
1287 struct radv_pipeline_cache
*cache
,
1288 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1289 const struct radv_graphics_pipeline_create_info
*extra
,
1290 const VkAllocationCallbacks
*alloc
)
1292 struct radv_shader_module fs_m
= {0};
1294 bool dump
= getenv("RADV_DUMP_SHADERS");
1296 alloc
= &device
->alloc
;
1298 pipeline
->device
= device
;
1299 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1301 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
1302 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1303 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1304 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1305 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1306 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1307 modules
[stage
] = radv_shader_module_from_handle(pStages
[stage
]->module
);
1310 radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
1313 if (modules
[MESA_SHADER_VERTEX
]) {
1314 union ac_shader_variant_key key
= radv_compute_vs_key(pCreateInfo
);
1316 pipeline
->shaders
[MESA_SHADER_VERTEX
] =
1317 radv_pipeline_compile(pipeline
, cache
, modules
[MESA_SHADER_VERTEX
],
1318 pStages
[MESA_SHADER_VERTEX
]->pName
,
1320 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
,
1321 pipeline
->layout
, &key
, dump
);
1323 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX
);
1326 if (!modules
[MESA_SHADER_FRAGMENT
]) {
1328 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
1329 fs_b
.shader
->info
->name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
1330 fs_m
.nir
= fs_b
.shader
;
1331 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
1334 if (modules
[MESA_SHADER_FRAGMENT
]) {
1335 union ac_shader_variant_key key
;
1336 key
.fs
.col_format
= pipeline
->graphics
.blend
.spi_shader_col_format
;
1337 key
.fs
.is_int8
= radv_pipeline_compute_is_int8(pCreateInfo
);
1339 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[MESA_SHADER_FRAGMENT
];
1341 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
1342 radv_pipeline_compile(pipeline
, cache
, modules
[MESA_SHADER_FRAGMENT
],
1343 stage
? stage
->pName
: "main",
1344 MESA_SHADER_FRAGMENT
,
1345 stage
? stage
->pSpecializationInfo
: NULL
,
1346 pipeline
->layout
, &key
, dump
);
1347 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT
);
1351 ralloc_free(fs_m
.nir
);
1353 radv_pipeline_init_depth_stencil_state(pipeline
, pCreateInfo
, extra
);
1354 radv_pipeline_init_raster_state(pipeline
, pCreateInfo
);
1355 radv_pipeline_init_multisample_state(pipeline
, pCreateInfo
);
1356 pipeline
->graphics
.prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
1357 pipeline
->graphics
.gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
1358 if (extra
&& extra
->use_rectlist
) {
1359 pipeline
->graphics
.prim
= V_008958_DI_PT_RECTLIST
;
1360 pipeline
->graphics
.gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1362 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
1364 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1365 pCreateInfo
->pVertexInputState
;
1366 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1367 const VkVertexInputAttributeDescription
*desc
=
1368 &vi_info
->pVertexAttributeDescriptions
[i
];
1369 unsigned loc
= desc
->location
;
1370 const struct vk_format_description
*format_desc
;
1372 uint32_t num_format
, data_format
;
1373 format_desc
= vk_format_description(desc
->format
);
1374 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
1376 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
1377 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
1379 pipeline
->va_rsrc_word3
[loc
] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc
->swizzle
[0])) |
1380 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc
->swizzle
[1])) |
1381 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc
->swizzle
[2])) |
1382 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc
->swizzle
[3])) |
1383 S_008F0C_NUM_FORMAT(num_format
) |
1384 S_008F0C_DATA_FORMAT(data_format
);
1385 pipeline
->va_format_size
[loc
] = format_desc
->block
.bits
/ 8;
1386 pipeline
->va_offset
[loc
] = desc
->offset
;
1387 pipeline
->va_binding
[loc
] = desc
->binding
;
1388 pipeline
->num_vertex_attribs
= MAX2(pipeline
->num_vertex_attribs
, loc
+ 1);
1391 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1392 const VkVertexInputBindingDescription
*desc
=
1393 &vi_info
->pVertexBindingDescriptions
[i
];
1395 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1398 if (device
->shader_stats_dump
) {
1399 radv_dump_pipeline_stats(device
, pipeline
);
1406 radv_graphics_pipeline_create(
1408 VkPipelineCache _cache
,
1409 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1410 const struct radv_graphics_pipeline_create_info
*extra
,
1411 const VkAllocationCallbacks
*pAllocator
,
1412 VkPipeline
*pPipeline
)
1414 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1415 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
1416 struct radv_pipeline
*pipeline
;
1419 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1420 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1421 if (pipeline
== NULL
)
1422 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1424 memset(pipeline
, 0, sizeof(*pipeline
));
1425 result
= radv_pipeline_init(pipeline
, device
, cache
,
1426 pCreateInfo
, extra
, pAllocator
);
1427 if (result
!= VK_SUCCESS
) {
1428 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
1432 *pPipeline
= radv_pipeline_to_handle(pipeline
);
1437 VkResult
radv_CreateGraphicsPipelines(
1439 VkPipelineCache pipelineCache
,
1441 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1442 const VkAllocationCallbacks
* pAllocator
,
1443 VkPipeline
* pPipelines
)
1445 VkResult result
= VK_SUCCESS
;
1448 for (; i
< count
; i
++) {
1449 result
= radv_graphics_pipeline_create(_device
,
1452 NULL
, pAllocator
, &pPipelines
[i
]);
1453 if (result
!= VK_SUCCESS
) {
1454 for (unsigned j
= 0; j
< i
; j
++) {
1455 radv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);
1465 static VkResult
radv_compute_pipeline_create(
1467 VkPipelineCache _cache
,
1468 const VkComputePipelineCreateInfo
* pCreateInfo
,
1469 const VkAllocationCallbacks
* pAllocator
,
1470 VkPipeline
* pPipeline
)
1472 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1473 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
1474 RADV_FROM_HANDLE(radv_shader_module
, module
, pCreateInfo
->stage
.module
);
1475 struct radv_pipeline
*pipeline
;
1476 bool dump
= getenv("RADV_DUMP_SHADERS");
1478 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1479 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1480 if (pipeline
== NULL
)
1481 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1483 memset(pipeline
, 0, sizeof(*pipeline
));
1484 pipeline
->device
= device
;
1485 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1487 pipeline
->shaders
[MESA_SHADER_COMPUTE
] =
1488 radv_pipeline_compile(pipeline
, cache
, module
,
1489 pCreateInfo
->stage
.pName
,
1490 MESA_SHADER_COMPUTE
,
1491 pCreateInfo
->stage
.pSpecializationInfo
,
1492 pipeline
->layout
, NULL
, dump
);
1494 *pPipeline
= radv_pipeline_to_handle(pipeline
);
1496 if (device
->shader_stats_dump
) {
1497 radv_dump_pipeline_stats(device
, pipeline
);
1501 VkResult
radv_CreateComputePipelines(
1503 VkPipelineCache pipelineCache
,
1505 const VkComputePipelineCreateInfo
* pCreateInfos
,
1506 const VkAllocationCallbacks
* pAllocator
,
1507 VkPipeline
* pPipelines
)
1509 VkResult result
= VK_SUCCESS
;
1512 for (; i
< count
; i
++) {
1513 result
= radv_compute_pipeline_create(_device
, pipelineCache
,
1515 pAllocator
, &pPipelines
[i
]);
1516 if (result
!= VK_SUCCESS
) {
1517 for (unsigned j
= 0; j
< i
; j
++) {
1518 radv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);