2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
33 #include "radv_shader.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
53 struct radv_blend_state
{
54 uint32_t blend_enable_4bit
;
55 uint32_t need_src_alpha
;
57 uint32_t cb_color_control
;
58 uint32_t cb_target_mask
;
59 uint32_t cb_target_enabled_4bit
;
60 uint32_t sx_mrt_blend_opt
[8];
61 uint32_t cb_blend_control
[8];
63 uint32_t spi_shader_col_format
;
64 uint32_t cb_shader_mask
;
65 uint32_t db_alpha_to_mask
;
67 uint32_t commutative_4bit
;
69 bool single_cb_enable
;
70 bool mrt0_is_dual_src
;
73 struct radv_dsa_order_invariance
{
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
86 struct radv_tessellation_state
{
87 uint32_t ls_hs_config
;
93 struct radv_gs_state
{
94 uint32_t vgt_gs_onchip_cntl
;
95 uint32_t vgt_gs_max_prims_per_subgroup
;
96 uint32_t vgt_esgs_ring_itemsize
;
101 radv_pipeline_destroy(struct radv_device
*device
,
102 struct radv_pipeline
*pipeline
,
103 const VkAllocationCallbacks
* allocator
)
105 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
106 if (pipeline
->shaders
[i
])
107 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
109 if (pipeline
->gs_copy_shader
)
110 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
113 free(pipeline
->cs
.buf
);
114 vk_free2(&device
->alloc
, allocator
, pipeline
);
117 void radv_DestroyPipeline(
119 VkPipeline _pipeline
,
120 const VkAllocationCallbacks
* pAllocator
)
122 RADV_FROM_HANDLE(radv_device
, device
, _device
);
123 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
128 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
131 static uint32_t get_hash_flags(struct radv_device
*device
)
133 uint32_t hash_flags
= 0;
135 if (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
)
136 hash_flags
|= RADV_HASH_SHADER_UNSAFE_MATH
;
137 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
138 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
143 radv_pipeline_scratch_init(struct radv_device
*device
,
144 struct radv_pipeline
*pipeline
)
146 unsigned scratch_bytes_per_wave
= 0;
147 unsigned max_waves
= 0;
148 unsigned min_waves
= 1;
150 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
151 if (pipeline
->shaders
[i
]) {
152 unsigned max_stage_waves
= device
->scratch_waves
;
154 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
155 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
157 max_stage_waves
= MIN2(max_stage_waves
,
158 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
159 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
160 max_waves
= MAX2(max_waves
, max_stage_waves
);
164 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
165 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
166 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
167 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
168 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
171 if (scratch_bytes_per_wave
)
172 max_waves
= MIN2(max_waves
, 0xffffffffu
/ scratch_bytes_per_wave
);
174 if (scratch_bytes_per_wave
&& max_waves
< min_waves
) {
175 /* Not really true at this moment, but will be true on first
176 * execution. Avoid having hanging shaders. */
177 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
179 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
180 pipeline
->max_waves
= max_waves
;
184 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
187 case VK_LOGIC_OP_CLEAR
:
188 return V_028808_ROP3_CLEAR
;
189 case VK_LOGIC_OP_AND
:
190 return V_028808_ROP3_AND
;
191 case VK_LOGIC_OP_AND_REVERSE
:
192 return V_028808_ROP3_AND_REVERSE
;
193 case VK_LOGIC_OP_COPY
:
194 return V_028808_ROP3_COPY
;
195 case VK_LOGIC_OP_AND_INVERTED
:
196 return V_028808_ROP3_AND_INVERTED
;
197 case VK_LOGIC_OP_NO_OP
:
198 return V_028808_ROP3_NO_OP
;
199 case VK_LOGIC_OP_XOR
:
200 return V_028808_ROP3_XOR
;
202 return V_028808_ROP3_OR
;
203 case VK_LOGIC_OP_NOR
:
204 return V_028808_ROP3_NOR
;
205 case VK_LOGIC_OP_EQUIVALENT
:
206 return V_028808_ROP3_EQUIVALENT
;
207 case VK_LOGIC_OP_INVERT
:
208 return V_028808_ROP3_INVERT
;
209 case VK_LOGIC_OP_OR_REVERSE
:
210 return V_028808_ROP3_OR_REVERSE
;
211 case VK_LOGIC_OP_COPY_INVERTED
:
212 return V_028808_ROP3_COPY_INVERTED
;
213 case VK_LOGIC_OP_OR_INVERTED
:
214 return V_028808_ROP3_OR_INVERTED
;
215 case VK_LOGIC_OP_NAND
:
216 return V_028808_ROP3_NAND
;
217 case VK_LOGIC_OP_SET
:
218 return V_028808_ROP3_SET
;
220 unreachable("Unhandled logic op");
225 static uint32_t si_translate_blend_function(VkBlendOp op
)
228 case VK_BLEND_OP_ADD
:
229 return V_028780_COMB_DST_PLUS_SRC
;
230 case VK_BLEND_OP_SUBTRACT
:
231 return V_028780_COMB_SRC_MINUS_DST
;
232 case VK_BLEND_OP_REVERSE_SUBTRACT
:
233 return V_028780_COMB_DST_MINUS_SRC
;
234 case VK_BLEND_OP_MIN
:
235 return V_028780_COMB_MIN_DST_SRC
;
236 case VK_BLEND_OP_MAX
:
237 return V_028780_COMB_MAX_DST_SRC
;
243 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
246 case VK_BLEND_FACTOR_ZERO
:
247 return V_028780_BLEND_ZERO
;
248 case VK_BLEND_FACTOR_ONE
:
249 return V_028780_BLEND_ONE
;
250 case VK_BLEND_FACTOR_SRC_COLOR
:
251 return V_028780_BLEND_SRC_COLOR
;
252 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
253 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
254 case VK_BLEND_FACTOR_DST_COLOR
:
255 return V_028780_BLEND_DST_COLOR
;
256 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
257 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
258 case VK_BLEND_FACTOR_SRC_ALPHA
:
259 return V_028780_BLEND_SRC_ALPHA
;
260 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
261 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
262 case VK_BLEND_FACTOR_DST_ALPHA
:
263 return V_028780_BLEND_DST_ALPHA
;
264 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
265 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
266 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
267 return V_028780_BLEND_CONSTANT_COLOR
;
268 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
269 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
270 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
271 return V_028780_BLEND_CONSTANT_ALPHA
;
272 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
273 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
274 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
275 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
276 case VK_BLEND_FACTOR_SRC1_COLOR
:
277 return V_028780_BLEND_SRC1_COLOR
;
278 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
279 return V_028780_BLEND_INV_SRC1_COLOR
;
280 case VK_BLEND_FACTOR_SRC1_ALPHA
:
281 return V_028780_BLEND_SRC1_ALPHA
;
282 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
283 return V_028780_BLEND_INV_SRC1_ALPHA
;
289 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
292 case VK_BLEND_OP_ADD
:
293 return V_028760_OPT_COMB_ADD
;
294 case VK_BLEND_OP_SUBTRACT
:
295 return V_028760_OPT_COMB_SUBTRACT
;
296 case VK_BLEND_OP_REVERSE_SUBTRACT
:
297 return V_028760_OPT_COMB_REVSUBTRACT
;
298 case VK_BLEND_OP_MIN
:
299 return V_028760_OPT_COMB_MIN
;
300 case VK_BLEND_OP_MAX
:
301 return V_028760_OPT_COMB_MAX
;
303 return V_028760_OPT_COMB_BLEND_DISABLED
;
307 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
310 case VK_BLEND_FACTOR_ZERO
:
311 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
312 case VK_BLEND_FACTOR_ONE
:
313 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
314 case VK_BLEND_FACTOR_SRC_COLOR
:
315 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
316 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
317 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
318 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
319 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
320 case VK_BLEND_FACTOR_SRC_ALPHA
:
321 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
322 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
323 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
325 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
326 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
328 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
333 * Get rid of DST in the blend factors by commuting the operands:
334 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
336 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
337 unsigned *dst_factor
, unsigned expected_dst
,
338 unsigned replacement_src
)
340 if (*src_factor
== expected_dst
&&
341 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
342 *src_factor
= VK_BLEND_FACTOR_ZERO
;
343 *dst_factor
= replacement_src
;
345 /* Commuting the operands requires reversing subtractions. */
346 if (*func
== VK_BLEND_OP_SUBTRACT
)
347 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
348 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
349 *func
= VK_BLEND_OP_SUBTRACT
;
353 static bool si_blend_factor_uses_dst(unsigned factor
)
355 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
356 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
357 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
358 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
359 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
362 static bool is_dual_src(VkBlendFactor factor
)
365 case VK_BLEND_FACTOR_SRC1_COLOR
:
366 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
367 case VK_BLEND_FACTOR_SRC1_ALPHA
:
368 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
375 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
377 bool blend_need_alpha
)
379 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
380 unsigned format
, ntype
, swap
;
382 /* Alpha is needed for alpha-to-coverage.
383 * Blending may be with or without alpha.
385 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
386 unsigned alpha
= 0; /* exports alpha, but may not support blending */
387 unsigned blend
= 0; /* supports blending, but may not export alpha */
388 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
390 format
= radv_translate_colorformat(vk_format
);
391 ntype
= radv_translate_color_numformat(vk_format
, desc
,
392 vk_format_get_first_non_void_channel(vk_format
));
393 swap
= radv_translate_colorswap(vk_format
, false);
395 /* Choose the SPI color formats. These are required values for Stoney/RB+.
396 * Other chips have multiple choices, though they are not necessarily better.
399 case V_028C70_COLOR_5_6_5
:
400 case V_028C70_COLOR_1_5_5_5
:
401 case V_028C70_COLOR_5_5_5_1
:
402 case V_028C70_COLOR_4_4_4_4
:
403 case V_028C70_COLOR_10_11_11
:
404 case V_028C70_COLOR_11_11_10
:
405 case V_028C70_COLOR_8
:
406 case V_028C70_COLOR_8_8
:
407 case V_028C70_COLOR_8_8_8_8
:
408 case V_028C70_COLOR_10_10_10_2
:
409 case V_028C70_COLOR_2_10_10_10
:
410 if (ntype
== V_028C70_NUMBER_UINT
)
411 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
412 else if (ntype
== V_028C70_NUMBER_SINT
)
413 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
415 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
418 case V_028C70_COLOR_16
:
419 case V_028C70_COLOR_16_16
:
420 case V_028C70_COLOR_16_16_16_16
:
421 if (ntype
== V_028C70_NUMBER_UNORM
||
422 ntype
== V_028C70_NUMBER_SNORM
) {
423 /* UNORM16 and SNORM16 don't support blending */
424 if (ntype
== V_028C70_NUMBER_UNORM
)
425 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
427 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
429 /* Use 32 bits per channel for blending. */
430 if (format
== V_028C70_COLOR_16
) {
431 if (swap
== V_028C70_SWAP_STD
) { /* R */
432 blend
= V_028714_SPI_SHADER_32_R
;
433 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
434 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
435 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
438 } else if (format
== V_028C70_COLOR_16_16
) {
439 if (swap
== V_028C70_SWAP_STD
) { /* RG */
440 blend
= V_028714_SPI_SHADER_32_GR
;
441 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
442 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
443 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
446 } else /* 16_16_16_16 */
447 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
448 } else if (ntype
== V_028C70_NUMBER_UINT
)
449 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
450 else if (ntype
== V_028C70_NUMBER_SINT
)
451 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
452 else if (ntype
== V_028C70_NUMBER_FLOAT
)
453 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
458 case V_028C70_COLOR_32
:
459 if (swap
== V_028C70_SWAP_STD
) { /* R */
460 blend
= normal
= V_028714_SPI_SHADER_32_R
;
461 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
462 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
463 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
468 case V_028C70_COLOR_32_32
:
469 if (swap
== V_028C70_SWAP_STD
) { /* RG */
470 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
471 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
472 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
473 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
478 case V_028C70_COLOR_32_32_32_32
:
479 case V_028C70_COLOR_8_24
:
480 case V_028C70_COLOR_24_8
:
481 case V_028C70_COLOR_X24_8_32_FLOAT
:
482 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
486 unreachable("unhandled blend format");
489 if (blend_enable
&& blend_need_alpha
)
491 else if(blend_need_alpha
)
493 else if(blend_enable
)
500 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
501 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
502 struct radv_blend_state
*blend
)
504 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
505 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
506 unsigned col_format
= 0;
507 unsigned num_targets
;
509 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
512 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
513 cf
= V_028714_SPI_SHADER_ZERO
;
515 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
517 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
519 cf
= si_choose_spi_color_format(attachment
->format
,
521 blend
->need_src_alpha
& (1 << i
));
524 col_format
|= cf
<< (4 * i
);
527 if (!col_format
&& blend
->need_src_alpha
& (1 << 0)) {
528 /* When a subpass doesn't have any color attachments, write the
529 * alpha channel of MRT0 when alpha coverage is enabled because
530 * the depth attachment needs it.
532 col_format
|= V_028714_SPI_SHADER_32_AR
;
535 /* If the i-th target format is set, all previous target formats must
536 * be non-zero to avoid hangs.
538 num_targets
= (util_last_bit(col_format
) + 3) / 4;
539 for (unsigned i
= 0; i
< num_targets
; i
++) {
540 if (!(col_format
& (0xf << (i
* 4)))) {
541 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
545 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
547 if (blend
->mrt0_is_dual_src
)
548 col_format
|= (col_format
& 0xf) << 4;
549 blend
->spi_shader_col_format
= col_format
;
553 format_is_int8(VkFormat format
)
555 const struct vk_format_description
*desc
= vk_format_description(format
);
556 int channel
= vk_format_get_first_non_void_channel(format
);
558 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
559 desc
->channel
[channel
].size
== 8;
563 format_is_int10(VkFormat format
)
565 const struct vk_format_description
*desc
= vk_format_description(format
);
567 if (desc
->nr_channels
!= 4)
569 for (unsigned i
= 0; i
< 4; i
++) {
570 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
577 * Ordered so that for each i,
578 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
580 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
581 VK_FORMAT_R32_SFLOAT
,
582 VK_FORMAT_R32G32_SFLOAT
,
583 VK_FORMAT_R8G8B8A8_UNORM
,
584 VK_FORMAT_R16G16B16A16_UNORM
,
585 VK_FORMAT_R16G16B16A16_SNORM
,
586 VK_FORMAT_R16G16B16A16_UINT
,
587 VK_FORMAT_R16G16B16A16_SINT
,
588 VK_FORMAT_R32G32B32A32_SFLOAT
,
589 VK_FORMAT_R8G8B8A8_UINT
,
590 VK_FORMAT_R8G8B8A8_SINT
,
591 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
592 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
595 unsigned radv_format_meta_fs_key(VkFormat format
)
597 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
599 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
600 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
601 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
603 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
604 bool is_int8
= format_is_int8(format
);
605 bool is_int10
= format_is_int10(format
);
607 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
611 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
612 unsigned *is_int8
, unsigned *is_int10
)
614 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
615 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
619 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
620 struct radv_render_pass_attachment
*attachment
;
622 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
625 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
627 if (format_is_int8(attachment
->format
))
629 if (format_is_int10(attachment
->format
))
635 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
636 VkBlendOp op
, VkBlendFactor src
,
637 VkBlendFactor dst
, unsigned chanmask
)
639 /* Src factor is allowed when it does not depend on Dst. */
640 static const uint32_t src_allowed
=
641 (1u << VK_BLEND_FACTOR_ONE
) |
642 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
643 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
644 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
645 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
646 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
647 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
648 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
649 (1u << VK_BLEND_FACTOR_ZERO
) |
650 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
651 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
652 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
653 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
654 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
655 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
657 if (dst
== VK_BLEND_FACTOR_ONE
&&
658 (src_allowed
& (1u << src
))) {
659 /* Addition is commutative, but floating point addition isn't
660 * associative: subtle changes can be introduced via different
661 * rounding. Be conservative, only enable for min and max.
663 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
664 blend
->commutative_4bit
|= chanmask
;
668 static struct radv_blend_state
669 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
670 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
671 const struct radv_graphics_pipeline_create_info
*extra
)
673 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
674 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
675 struct radv_blend_state blend
= {0};
676 unsigned mode
= V_028808_CB_NORMAL
;
682 if (extra
&& extra
->custom_blend_mode
) {
683 blend
.single_cb_enable
= true;
684 mode
= extra
->custom_blend_mode
;
686 blend
.cb_color_control
= 0;
687 if (vkblend
->logicOpEnable
)
688 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
690 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
692 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
693 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
694 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
695 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
696 S_028B70_OFFSET_ROUND(1);
698 if (vkms
&& vkms
->alphaToCoverageEnable
) {
699 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
700 blend
.need_src_alpha
|= 0x1;
703 blend
.cb_target_mask
= 0;
704 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
705 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
706 unsigned blend_cntl
= 0;
707 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
708 VkBlendOp eqRGB
= att
->colorBlendOp
;
709 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
710 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
711 VkBlendOp eqA
= att
->alphaBlendOp
;
712 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
713 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
715 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
717 if (!att
->colorWriteMask
)
720 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
721 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
722 if (!att
->blendEnable
) {
723 blend
.cb_blend_control
[i
] = blend_cntl
;
727 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
729 blend
.mrt0_is_dual_src
= true;
731 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
732 srcRGB
= VK_BLEND_FACTOR_ONE
;
733 dstRGB
= VK_BLEND_FACTOR_ONE
;
735 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
736 srcA
= VK_BLEND_FACTOR_ONE
;
737 dstA
= VK_BLEND_FACTOR_ONE
;
740 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
742 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
745 /* Blending optimizations for RB+.
746 * These transformations don't change the behavior.
748 * First, get rid of DST in the blend factors:
749 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
751 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
752 VK_BLEND_FACTOR_DST_COLOR
,
753 VK_BLEND_FACTOR_SRC_COLOR
);
755 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
756 VK_BLEND_FACTOR_DST_COLOR
,
757 VK_BLEND_FACTOR_SRC_COLOR
);
759 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
760 VK_BLEND_FACTOR_DST_ALPHA
,
761 VK_BLEND_FACTOR_SRC_ALPHA
);
763 /* Look up the ideal settings from tables. */
764 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
765 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
766 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
767 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
769 /* Handle interdependencies. */
770 if (si_blend_factor_uses_dst(srcRGB
))
771 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
772 if (si_blend_factor_uses_dst(srcA
))
773 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
775 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
776 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
777 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
778 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
779 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
781 /* Set the final value. */
782 blend
.sx_mrt_blend_opt
[i
] =
783 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
784 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
785 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
786 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
787 S_028760_ALPHA_DST_OPT(dstA_opt
) |
788 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
789 blend_cntl
|= S_028780_ENABLE(1);
791 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
792 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
793 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
794 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
795 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
796 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
797 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
798 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
800 blend
.cb_blend_control
[i
] = blend_cntl
;
802 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
804 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
805 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
806 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
807 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
808 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
809 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
810 blend
.need_src_alpha
|= 1 << i
;
812 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
813 blend
.cb_blend_control
[i
] = 0;
814 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
817 if (pipeline
->device
->physical_device
->has_rbplus
) {
818 /* Disable RB+ blend optimizations for dual source blending. */
819 if (blend
.mrt0_is_dual_src
) {
820 for (i
= 0; i
< 8; i
++) {
821 blend
.sx_mrt_blend_opt
[i
] =
822 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
823 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
827 /* RB+ doesn't work with dual source blending, logic op and
830 if (blend
.mrt0_is_dual_src
|| vkblend
->logicOpEnable
||
831 mode
== V_028808_CB_RESOLVE
)
832 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
835 if (blend
.cb_target_mask
)
836 blend
.cb_color_control
|= S_028808_MODE(mode
);
838 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
840 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
844 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
847 case VK_STENCIL_OP_KEEP
:
848 return V_02842C_STENCIL_KEEP
;
849 case VK_STENCIL_OP_ZERO
:
850 return V_02842C_STENCIL_ZERO
;
851 case VK_STENCIL_OP_REPLACE
:
852 return V_02842C_STENCIL_REPLACE_TEST
;
853 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
854 return V_02842C_STENCIL_ADD_CLAMP
;
855 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
856 return V_02842C_STENCIL_SUB_CLAMP
;
857 case VK_STENCIL_OP_INVERT
:
858 return V_02842C_STENCIL_INVERT
;
859 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
860 return V_02842C_STENCIL_ADD_WRAP
;
861 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
862 return V_02842C_STENCIL_SUB_WRAP
;
868 static uint32_t si_translate_fill(VkPolygonMode func
)
871 case VK_POLYGON_MODE_FILL
:
872 return V_028814_X_DRAW_TRIANGLES
;
873 case VK_POLYGON_MODE_LINE
:
874 return V_028814_X_DRAW_LINES
;
875 case VK_POLYGON_MODE_POINT
:
876 return V_028814_X_DRAW_POINTS
;
879 return V_028814_X_DRAW_POINTS
;
883 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo
*vkms
)
885 uint32_t num_samples
= vkms
->rasterizationSamples
;
886 uint32_t ps_iter_samples
= 1;
888 if (vkms
->sampleShadingEnable
) {
889 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
890 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
892 return ps_iter_samples
;
896 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
898 return pCreateInfo
->depthTestEnable
&&
899 pCreateInfo
->depthWriteEnable
&&
900 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
904 radv_writes_stencil(const VkStencilOpState
*state
)
906 return state
->writeMask
&&
907 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
908 state
->passOp
!= VK_STENCIL_OP_KEEP
||
909 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
913 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
915 return pCreateInfo
->stencilTestEnable
&&
916 (radv_writes_stencil(&pCreateInfo
->front
) ||
917 radv_writes_stencil(&pCreateInfo
->back
));
921 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
923 return radv_is_depth_write_enabled(pCreateInfo
) ||
924 radv_is_stencil_write_enabled(pCreateInfo
);
928 radv_order_invariant_stencil_op(VkStencilOp op
)
930 /* REPLACE is normally order invariant, except when the stencil
931 * reference value is written by the fragment shader. Tracking this
932 * interaction does not seem worth the effort, so be conservative.
934 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
935 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
936 op
!= VK_STENCIL_OP_REPLACE
;
940 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
942 /* Compute whether, assuming Z writes are disabled, this stencil state
943 * is order invariant in the sense that the set of passing fragments as
944 * well as the final stencil buffer result does not depend on the order
947 return !state
->writeMask
||
948 /* The following assumes that Z writes are disabled. */
949 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
950 radv_order_invariant_stencil_op(state
->passOp
) &&
951 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
952 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
953 radv_order_invariant_stencil_op(state
->failOp
));
957 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
958 struct radv_blend_state
*blend
,
959 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
961 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
962 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
963 unsigned colormask
= blend
->cb_target_enabled_4bit
;
965 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
968 /* Be conservative if a logic operation is enabled with color buffers. */
969 if (colormask
&& pCreateInfo
->pColorBlendState
->logicOpEnable
)
972 /* Default depth/stencil invariance when no attachment is bound. */
973 struct radv_dsa_order_invariance dsa_order_invariant
= {
974 .zs
= true, .pass_set
= true
977 if (pCreateInfo
->pDepthStencilState
&&
978 subpass
->depth_stencil_attachment
) {
979 const VkPipelineDepthStencilStateCreateInfo
*vkds
=
980 pCreateInfo
->pDepthStencilState
;
981 struct radv_render_pass_attachment
*attachment
=
982 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
983 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
984 struct radv_dsa_order_invariance order_invariance
[2];
985 struct radv_shader_variant
*ps
=
986 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
988 /* Compute depth/stencil order invariance in order to know if
989 * it's safe to enable out-of-order.
991 bool zfunc_is_ordered
=
992 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
993 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
994 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
995 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
996 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
998 bool nozwrite_and_order_invariant_stencil
=
999 !radv_is_ds_write_enabled(vkds
) ||
1000 (!radv_is_depth_write_enabled(vkds
) &&
1001 radv_order_invariant_stencil_state(&vkds
->front
) &&
1002 radv_order_invariant_stencil_state(&vkds
->back
));
1004 order_invariance
[1].zs
=
1005 nozwrite_and_order_invariant_stencil
||
1006 (!radv_is_stencil_write_enabled(vkds
) &&
1008 order_invariance
[0].zs
=
1009 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1011 order_invariance
[1].pass_set
=
1012 nozwrite_and_order_invariant_stencil
||
1013 (!radv_is_stencil_write_enabled(vkds
) &&
1014 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1015 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1016 order_invariance
[0].pass_set
=
1017 !radv_is_depth_write_enabled(vkds
) ||
1018 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1019 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1021 dsa_order_invariant
= order_invariance
[has_stencil
];
1022 if (!dsa_order_invariant
.zs
)
1025 /* The set of PS invocations is always order invariant,
1026 * except when early Z/S tests are requested.
1029 ps
->info
.info
.ps
.writes_memory
&&
1030 ps
->info
.fs
.early_fragment_test
&&
1031 !dsa_order_invariant
.pass_set
)
1034 /* Determine if out-of-order rasterization should be disabled
1035 * when occlusion queries are used.
1037 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1038 !dsa_order_invariant
.pass_set
;
1041 /* No color buffers are enabled for writing. */
1045 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1048 /* Only commutative blending. */
1049 if (blendmask
& ~blend
->commutative_4bit
)
1052 if (!dsa_order_invariant
.pass_set
)
1056 if (colormask
& ~blendmask
)
1063 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1064 struct radv_blend_state
*blend
,
1065 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1067 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
1068 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1069 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1070 bool out_of_order_rast
= false;
1071 int ps_iter_samples
= 1;
1072 uint32_t mask
= 0xffff;
1075 ms
->num_samples
= vkms
->rasterizationSamples
;
1077 ms
->num_samples
= 1;
1080 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
1081 if (vkms
&& !vkms
->sampleShadingEnable
&& pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.force_persample
) {
1082 ps_iter_samples
= ms
->num_samples
;
1085 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1086 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1087 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1088 /* Out-of-order rasterization is explicitly enabled by the
1091 out_of_order_rast
= true;
1093 /* Determine if the driver can enable out-of-order
1094 * rasterization internally.
1097 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1100 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1101 ms
->pa_sc_aa_config
= 0;
1102 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1103 S_028804_INCOHERENT_EQAA_READS(1) |
1104 S_028804_INTERPOLATE_COMP_Z(1) |
1105 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1106 ms
->pa_sc_mode_cntl_1
=
1107 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1108 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1109 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1110 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1112 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1113 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1114 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1115 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1116 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1117 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1118 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1119 S_028A48_VPORT_SCISSOR_ENABLE(1);
1121 if (ms
->num_samples
> 1) {
1122 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1123 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1124 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1125 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1126 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1127 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1128 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1129 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1130 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1131 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples
)) |
1132 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1133 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1134 if (ps_iter_samples
> 1)
1135 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1138 if (vkms
&& vkms
->pSampleMask
) {
1139 mask
= vkms
->pSampleMask
[0] & 0xffff;
1142 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1143 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1147 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1150 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1151 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1152 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1153 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1154 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1156 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1157 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1158 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1159 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1160 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1161 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1164 unreachable("unhandled primitive type");
1169 si_translate_prim(enum VkPrimitiveTopology topology
)
1172 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1173 return V_008958_DI_PT_POINTLIST
;
1174 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1175 return V_008958_DI_PT_LINELIST
;
1176 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1177 return V_008958_DI_PT_LINESTRIP
;
1178 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1179 return V_008958_DI_PT_TRILIST
;
1180 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1181 return V_008958_DI_PT_TRISTRIP
;
1182 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1183 return V_008958_DI_PT_TRIFAN
;
1184 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1185 return V_008958_DI_PT_LINELIST_ADJ
;
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1187 return V_008958_DI_PT_LINESTRIP_ADJ
;
1188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1189 return V_008958_DI_PT_TRILIST_ADJ
;
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1191 return V_008958_DI_PT_TRISTRIP_ADJ
;
1192 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1193 return V_008958_DI_PT_PATCH
;
1201 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1204 case 0: /* GL_POINTS */
1205 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1206 case 1: /* GL_LINES */
1207 case 3: /* GL_LINE_STRIP */
1208 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1209 case 0x8E7A: /* GL_ISOLINES */
1210 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1212 case 4: /* GL_TRIANGLES */
1213 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1214 case 5: /* GL_TRIANGLE_STRIP */
1215 case 7: /* GL_QUADS */
1216 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1224 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1227 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1228 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1229 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1230 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1233 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1234 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1236 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1238 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1240 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1247 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1250 case VK_DYNAMIC_STATE_VIEWPORT
:
1251 return RADV_DYNAMIC_VIEWPORT
;
1252 case VK_DYNAMIC_STATE_SCISSOR
:
1253 return RADV_DYNAMIC_SCISSOR
;
1254 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1255 return RADV_DYNAMIC_LINE_WIDTH
;
1256 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1257 return RADV_DYNAMIC_DEPTH_BIAS
;
1258 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1259 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1260 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1261 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1262 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1263 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1264 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1265 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1266 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1267 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1268 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1269 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1271 unreachable("Unhandled dynamic state");
1275 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1277 uint32_t states
= RADV_DYNAMIC_ALL
;
1279 /* If rasterization is disabled we do not care about any of the dynamic states,
1280 * since they are all rasterization related only. */
1281 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1284 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1285 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1287 if (!pCreateInfo
->pDepthStencilState
||
1288 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1289 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1291 if (!pCreateInfo
->pDepthStencilState
||
1292 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1293 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1294 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1295 RADV_DYNAMIC_STENCIL_REFERENCE
);
1297 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1298 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1300 /* TODO: blend constants & line width. */
1307 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1308 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1310 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1311 uint32_t states
= needed_states
;
1312 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1313 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1315 pipeline
->dynamic_state
= default_dynamic_state
;
1316 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1318 if (pCreateInfo
->pDynamicState
) {
1319 /* Remove all of the states that are marked as dynamic */
1320 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1321 for (uint32_t s
= 0; s
< count
; s
++)
1322 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1325 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1327 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1328 assert(pCreateInfo
->pViewportState
);
1330 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1331 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1332 typed_memcpy(dynamic
->viewport
.viewports
,
1333 pCreateInfo
->pViewportState
->pViewports
,
1334 pCreateInfo
->pViewportState
->viewportCount
);
1338 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1339 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1340 if (states
& RADV_DYNAMIC_SCISSOR
) {
1341 typed_memcpy(dynamic
->scissor
.scissors
,
1342 pCreateInfo
->pViewportState
->pScissors
,
1343 pCreateInfo
->pViewportState
->scissorCount
);
1347 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1348 assert(pCreateInfo
->pRasterizationState
);
1349 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1352 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1353 assert(pCreateInfo
->pRasterizationState
);
1354 dynamic
->depth_bias
.bias
=
1355 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1356 dynamic
->depth_bias
.clamp
=
1357 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1358 dynamic
->depth_bias
.slope
=
1359 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1362 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1364 * pColorBlendState is [...] NULL if the pipeline has rasterization
1365 * disabled or if the subpass of the render pass the pipeline is
1366 * created against does not use any color attachments.
1368 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1369 assert(pCreateInfo
->pColorBlendState
);
1370 typed_memcpy(dynamic
->blend_constants
,
1371 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1374 /* If there is no depthstencil attachment, then don't read
1375 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1376 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1377 * no need to override the depthstencil defaults in
1378 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1380 * Section 9.2 of the Vulkan 1.0.15 spec says:
1382 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1383 * disabled or if the subpass of the render pass the pipeline is created
1384 * against does not use a depth/stencil attachment.
1386 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1387 assert(pCreateInfo
->pDepthStencilState
);
1389 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1390 dynamic
->depth_bounds
.min
=
1391 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1392 dynamic
->depth_bounds
.max
=
1393 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1396 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1397 dynamic
->stencil_compare_mask
.front
=
1398 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1399 dynamic
->stencil_compare_mask
.back
=
1400 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1403 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1404 dynamic
->stencil_write_mask
.front
=
1405 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1406 dynamic
->stencil_write_mask
.back
=
1407 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1410 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1411 dynamic
->stencil_reference
.front
=
1412 pCreateInfo
->pDepthStencilState
->front
.reference
;
1413 dynamic
->stencil_reference
.back
=
1414 pCreateInfo
->pDepthStencilState
->back
.reference
;
1418 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1419 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1420 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1421 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1422 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1423 discard_rectangle_info
->pDiscardRectangles
,
1424 discard_rectangle_info
->discardRectangleCount
);
1427 pipeline
->dynamic_state
.mask
= states
;
1430 static struct radv_gs_state
1431 calculate_gs_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1432 const struct radv_pipeline
*pipeline
)
1434 struct radv_gs_state gs
= {0};
1435 struct radv_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1436 struct radv_es_output_info
*es_info
;
1437 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1438 es_info
= radv_pipeline_has_tess(pipeline
) ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1440 es_info
= radv_pipeline_has_tess(pipeline
) ?
1441 &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.es_info
:
1442 &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.es_info
;
1444 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1445 bool uses_adjacency
;
1446 switch(pCreateInfo
->pInputAssemblyState
->topology
) {
1447 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1448 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1449 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1450 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1451 uses_adjacency
= true;
1454 uses_adjacency
= false;
1458 /* All these are in dwords: */
1459 /* We can't allow using the whole LDS, because GS waves compete with
1460 * other shader stages for LDS space. */
1461 const unsigned max_lds_size
= 8 * 1024;
1462 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1463 unsigned esgs_lds_size
;
1465 /* All these are per subgroup: */
1466 const unsigned max_out_prims
= 32 * 1024;
1467 const unsigned max_es_verts
= 255;
1468 const unsigned ideal_gs_prims
= 64;
1469 unsigned max_gs_prims
, gs_prims
;
1470 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1472 if (uses_adjacency
|| gs_num_invocations
> 1)
1473 max_gs_prims
= 127 / gs_num_invocations
;
1477 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1478 * Make sure we don't go over the maximum value.
1480 if (gs_info
->gs
.vertices_out
> 0) {
1481 max_gs_prims
= MIN2(max_gs_prims
,
1483 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1485 assert(max_gs_prims
> 0);
1487 /* If the primitive has adjacency, halve the number of vertices
1488 * that will be reused in multiple primitives.
1490 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1492 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1493 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1495 /* Compute ESGS LDS size based on the worst case number of ES vertices
1496 * needed to create the target number of GS prims per subgroup.
1498 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1500 /* If total LDS usage is too big, refactor partitions based on ratio
1501 * of ESGS item sizes.
1503 if (esgs_lds_size
> max_lds_size
) {
1504 /* Our target GS Prims Per Subgroup was too large. Calculate
1505 * the maximum number of GS Prims Per Subgroup that will fit
1506 * into LDS, capped by the maximum that the hardware can support.
1508 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1510 assert(gs_prims
> 0);
1511 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1514 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1515 assert(esgs_lds_size
<= max_lds_size
);
1518 /* Now calculate remaining ESGS information. */
1520 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1522 es_verts
= max_es_verts
;
1524 /* Vertices for adjacency primitives are not always reused, so restore
1525 * it for ES_VERTS_PER_SUBGRP.
1527 min_es_verts
= gs_info
->gs
.vertices_in
;
1529 /* For normal primitives, the VGT only checks if they are past the ES
1530 * verts per subgroup after allocating a full GS primitive and if they
1531 * are, kick off a new subgroup. But if those additional ES verts are
1532 * unique (e.g. not reused) we need to make sure there is enough LDS
1533 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1535 es_verts
-= min_es_verts
- 1;
1537 uint32_t es_verts_per_subgroup
= es_verts
;
1538 uint32_t gs_prims_per_subgroup
= gs_prims
;
1539 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1540 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1541 gs
.lds_size
= align(esgs_lds_size
, 128) / 128;
1542 gs
.vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1543 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1544 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1545 gs
.vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1546 gs
.vgt_esgs_ring_itemsize
= esgs_itemsize
;
1547 assert(max_prims_per_subgroup
<= max_out_prims
);
1553 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
, const struct radv_gs_state
*gs
)
1555 struct radv_device
*device
= pipeline
->device
;
1556 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1557 unsigned wave_size
= 64;
1558 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1559 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
1560 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1562 unsigned gs_vertex_reuse
=
1563 (device
->physical_device
->rad_info
.chip_class
>= VI
? 32 : 16) * num_se
;
1564 unsigned alignment
= 256 * num_se
;
1565 /* The maximum size is 63.999 MB per SE. */
1566 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1567 struct radv_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1569 /* Calculate the minimum size. */
1570 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1571 wave_size
, alignment
);
1572 /* These are recommended sizes, not minimum sizes. */
1573 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1574 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1575 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1576 gs_info
->gs
.max_gsvs_emit_size
;
1578 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1579 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1580 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1582 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= VI
)
1583 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1585 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1588 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1591 /* If tessellation is all offchip and on-chip GS isn't used, this
1592 * workaround is not needed.
1596 /* SPI barrier management bug:
1597 * Make sure we have at least 4k of LDS in use to avoid the bug.
1598 * It applies to workgroup sizes of more than one wavefront.
1600 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1601 device
->physical_device
->rad_info
.family
== CHIP_KABINI
||
1602 device
->physical_device
->rad_info
.family
== CHIP_MULLINS
)
1603 *lds_size
= MAX2(*lds_size
, 8);
1606 struct radv_shader_variant
*
1607 radv_get_shader(struct radv_pipeline
*pipeline
,
1608 gl_shader_stage stage
)
1610 if (stage
== MESA_SHADER_VERTEX
) {
1611 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1612 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1613 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1614 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1615 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1616 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1617 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1618 if (!radv_pipeline_has_tess(pipeline
))
1620 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1621 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1622 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1623 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1625 return pipeline
->shaders
[stage
];
1628 static struct radv_tessellation_state
1629 calculate_tess_state(struct radv_pipeline
*pipeline
,
1630 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1632 unsigned num_tcs_input_cp
;
1633 unsigned num_tcs_output_cp
;
1635 unsigned num_patches
;
1636 struct radv_tessellation_state tess
= {0};
1638 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1639 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1640 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1642 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1644 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1645 assert(lds_size
<= 65536);
1646 lds_size
= align(lds_size
, 512) / 512;
1648 assert(lds_size
<= 32768);
1649 lds_size
= align(lds_size
, 256) / 256;
1651 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1653 tess
.lds_size
= lds_size
;
1655 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1656 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1657 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1658 tess
.num_patches
= num_patches
;
1660 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1661 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1663 switch (tes
->info
.tes
.primitive_mode
) {
1665 type
= V_028B6C_TESS_TRIANGLE
;
1668 type
= V_028B6C_TESS_QUAD
;
1671 type
= V_028B6C_TESS_ISOLINE
;
1675 switch (tes
->info
.tes
.spacing
) {
1676 case TESS_SPACING_EQUAL
:
1677 partitioning
= V_028B6C_PART_INTEGER
;
1679 case TESS_SPACING_FRACTIONAL_ODD
:
1680 partitioning
= V_028B6C_PART_FRAC_ODD
;
1682 case TESS_SPACING_FRACTIONAL_EVEN
:
1683 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1689 bool ccw
= tes
->info
.tes
.ccw
;
1690 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
1691 vk_find_struct_const(pCreateInfo
->pTessellationState
,
1692 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
1694 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
1697 if (tes
->info
.tes
.point_mode
)
1698 topology
= V_028B6C_OUTPUT_POINT
;
1699 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
1700 topology
= V_028B6C_OUTPUT_LINE
;
1702 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
1704 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
1706 if (pipeline
->device
->has_distributed_tess
) {
1707 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
1708 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
1709 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
1711 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
1713 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
1715 tess
.tf_param
= S_028B6C_TYPE(type
) |
1716 S_028B6C_PARTITIONING(partitioning
) |
1717 S_028B6C_TOPOLOGY(topology
) |
1718 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
1723 static const struct radv_prim_vertex_count prim_size_table
[] = {
1724 [V_008958_DI_PT_NONE
] = {0, 0},
1725 [V_008958_DI_PT_POINTLIST
] = {1, 1},
1726 [V_008958_DI_PT_LINELIST
] = {2, 2},
1727 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
1728 [V_008958_DI_PT_TRILIST
] = {3, 3},
1729 [V_008958_DI_PT_TRIFAN
] = {3, 1},
1730 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
1731 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
1732 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
1733 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
1734 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
1735 [V_008958_DI_PT_RECTLIST
] = {3, 3},
1736 [V_008958_DI_PT_LINELOOP
] = {2, 1},
1737 [V_008958_DI_PT_POLYGON
] = {3, 1},
1738 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
1741 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
1743 if (radv_pipeline_has_gs(pipeline
))
1744 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
1745 else if (radv_pipeline_has_tess(pipeline
))
1746 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
1748 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
1752 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
1754 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
1755 int shader_count
= 0;
1757 if(shaders
[MESA_SHADER_FRAGMENT
]) {
1758 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
1760 if(shaders
[MESA_SHADER_GEOMETRY
]) {
1761 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
1763 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
1764 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
1766 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
1767 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
1769 if(shaders
[MESA_SHADER_VERTEX
]) {
1770 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
1773 if (shader_count
> 1) {
1774 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
1775 unsigned last
= ordered_shaders
[0]->info
.stage
;
1777 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
1778 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
1779 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
1781 for (int i
= 0; i
< shader_count
; ++i
) {
1782 nir_variable_mode mask
= 0;
1784 if (ordered_shaders
[i
]->info
.stage
!= first
)
1785 mask
= mask
| nir_var_shader_in
;
1787 if (ordered_shaders
[i
]->info
.stage
!= last
)
1788 mask
= mask
| nir_var_shader_out
;
1790 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
1791 radv_optimize_nir(ordered_shaders
[i
], false, false);
1795 for (int i
= 1; i
< shader_count
; ++i
) {
1796 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
1797 ordered_shaders
[i
- 1]);
1799 if (nir_link_opt_varyings(ordered_shaders
[i
],
1800 ordered_shaders
[i
- 1]))
1801 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
1803 nir_remove_dead_variables(ordered_shaders
[i
],
1804 nir_var_shader_out
);
1805 nir_remove_dead_variables(ordered_shaders
[i
- 1],
1808 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
1809 ordered_shaders
[i
- 1]);
1811 nir_compact_varyings(ordered_shaders
[i
],
1812 ordered_shaders
[i
- 1], true);
1815 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
1816 ac_lower_indirect_derefs(ordered_shaders
[i
],
1817 pipeline
->device
->physical_device
->rad_info
.chip_class
);
1819 radv_optimize_nir(ordered_shaders
[i
], false, false);
1821 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
1822 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
1823 pipeline
->device
->physical_device
->rad_info
.chip_class
);
1825 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
1831 static struct radv_pipeline_key
1832 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
1833 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1834 const struct radv_blend_state
*blend
,
1835 bool has_view_index
)
1837 const VkPipelineVertexInputStateCreateInfo
*input_state
=
1838 pCreateInfo
->pVertexInputState
;
1839 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
1840 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1842 struct radv_pipeline_key key
;
1843 memset(&key
, 0, sizeof(key
));
1845 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
1846 key
.optimisations_disabled
= 1;
1848 key
.has_multiview_view_index
= has_view_index
;
1850 uint32_t binding_input_rate
= 0;
1851 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
1852 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
1853 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
1854 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
1855 binding_input_rate
|= 1u << binding
;
1856 instance_rate_divisors
[binding
] = 1;
1859 if (divisor_state
) {
1860 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
1861 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
1862 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
1866 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
1867 const VkVertexInputAttributeDescription
*desc
=
1868 &input_state
->pVertexAttributeDescriptions
[i
];
1869 const struct vk_format_description
*format_desc
;
1870 unsigned location
= desc
->location
;
1871 unsigned binding
= desc
->binding
;
1872 unsigned num_format
, data_format
;
1875 if (binding_input_rate
& (1u << binding
)) {
1876 key
.instance_rate_inputs
|= 1u << location
;
1877 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
1880 format_desc
= vk_format_description(desc
->format
);
1881 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
1883 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
1884 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
1886 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
1887 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
1888 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
1889 key
.vertex_attribute_strides
[location
] = input_state
->pVertexBindingDescriptions
[desc
->binding
].stride
;
1891 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= VI
&&
1892 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
1893 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
1896 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
1897 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
1898 adjust
= RADV_ALPHA_ADJUST_SNORM
;
1900 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
1901 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
1902 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
1904 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
1905 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
1906 adjust
= RADV_ALPHA_ADJUST_SINT
;
1912 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
1915 switch (desc
->format
) {
1916 case VK_FORMAT_B8G8R8A8_UNORM
:
1917 case VK_FORMAT_B8G8R8A8_SNORM
:
1918 case VK_FORMAT_B8G8R8A8_USCALED
:
1919 case VK_FORMAT_B8G8R8A8_SSCALED
:
1920 case VK_FORMAT_B8G8R8A8_UINT
:
1921 case VK_FORMAT_B8G8R8A8_SINT
:
1922 case VK_FORMAT_B8G8R8A8_SRGB
:
1923 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
1924 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
1925 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
1926 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
1927 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
1928 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
1929 key
.vertex_post_shuffle
|= 1 << location
;
1936 if (pCreateInfo
->pTessellationState
)
1937 key
.tess_input_vertices
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1940 if (pCreateInfo
->pMultisampleState
&&
1941 pCreateInfo
->pMultisampleState
->rasterizationSamples
> 1) {
1942 uint32_t num_samples
= pCreateInfo
->pMultisampleState
->rasterizationSamples
;
1943 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
->pMultisampleState
);
1944 key
.num_samples
= num_samples
;
1945 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1948 key
.col_format
= blend
->spi_shader_col_format
;
1949 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< VI
)
1950 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
1956 radv_fill_shader_keys(struct radv_shader_variant_key
*keys
,
1957 const struct radv_pipeline_key
*key
,
1960 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
1961 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
1962 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
1963 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
1964 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
1965 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
1966 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
1967 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
1968 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
1971 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1972 keys
[MESA_SHADER_VERTEX
].vs
.as_ls
= true;
1973 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
1974 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
1975 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
1977 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
1980 if (nir
[MESA_SHADER_GEOMETRY
]) {
1981 if (nir
[MESA_SHADER_TESS_CTRL
])
1982 keys
[MESA_SHADER_TESS_EVAL
].tes
.as_es
= true;
1984 keys
[MESA_SHADER_VERTEX
].vs
.as_es
= true;
1987 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
1988 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
1990 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
1991 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
1992 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
1993 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
1994 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
1998 merge_tess_info(struct shader_info
*tes_info
,
1999 const struct shader_info
*tcs_info
)
2001 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2003 * "PointMode. Controls generation of points rather than triangles
2004 * or lines. This functionality defaults to disabled, and is
2005 * enabled if either shader stage includes the execution mode.
2007 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2008 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2009 * and OutputVertices, it says:
2011 * "One mode must be set in at least one of the tessellation
2014 * So, the fields can be set in either the TCS or TES, but they must
2015 * agree if set in both. Our backend looks at TES, so bitwise-or in
2016 * the values from the TCS.
2018 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2019 tes_info
->tess
.tcs_vertices_out
== 0 ||
2020 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2021 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2023 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2024 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2025 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2026 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2028 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2029 tes_info
->tess
.primitive_mode
== 0 ||
2030 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2031 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2032 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2033 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2037 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2038 struct radv_device
*device
,
2039 struct radv_pipeline_cache
*cache
,
2040 const struct radv_pipeline_key
*key
,
2041 const VkPipelineShaderStageCreateInfo
**pStages
,
2042 const VkPipelineCreateFlags flags
)
2044 struct radv_shader_module fs_m
= {0};
2045 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2046 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2047 void *codes
[MESA_SHADER_STAGES
] = {0};
2048 unsigned code_sizes
[MESA_SHADER_STAGES
] = {0};
2049 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{0}}}};
2050 unsigned char hash
[20], gs_copy_hash
[20];
2052 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2054 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2055 if (modules
[i
]->nir
)
2056 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2057 strlen(modules
[i
]->nir
->info
.name
),
2060 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2064 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2065 memcpy(gs_copy_hash
, hash
, 20);
2066 gs_copy_hash
[0] ^= 1;
2068 if (modules
[MESA_SHADER_GEOMETRY
]) {
2069 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2070 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
);
2071 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2074 if (radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
) &&
2075 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2079 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2081 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2082 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2083 fs_m
.nir
= fs_b
.shader
;
2084 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2087 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2088 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2093 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2094 stage
? stage
->pName
: "main", i
,
2095 stage
? stage
->pSpecializationInfo
: NULL
,
2098 /* We don't want to alter meta shaders IR directly so clone it
2101 if (nir
[i
]->info
.name
) {
2102 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2106 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2107 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2108 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2111 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2112 radv_link_shaders(pipeline
, nir
);
2114 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2116 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2119 if (radv_can_dump_shader(device
, modules
[i
], false))
2120 nir_print_shader(nir
[i
], stderr
);
2123 radv_fill_shader_keys(keys
, key
, nir
);
2125 if (nir
[MESA_SHADER_FRAGMENT
]) {
2126 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2127 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2128 radv_shader_variant_create(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2129 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2130 &codes
[MESA_SHADER_FRAGMENT
], &code_sizes
[MESA_SHADER_FRAGMENT
]);
2133 /* TODO: These are no longer used as keys we should refactor this */
2134 keys
[MESA_SHADER_VERTEX
].vs
.export_prim_id
=
2135 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
;
2136 keys
[MESA_SHADER_VERTEX
].vs
.export_layer_id
=
2137 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.layer_input
;
2138 keys
[MESA_SHADER_TESS_EVAL
].tes
.export_prim_id
=
2139 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
;
2140 keys
[MESA_SHADER_TESS_EVAL
].tes
.export_layer_id
=
2141 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.layer_input
;
2144 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2145 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2146 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2147 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2148 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2149 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_create(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2151 &key
, &codes
[MESA_SHADER_TESS_CTRL
],
2152 &code_sizes
[MESA_SHADER_TESS_CTRL
]);
2154 modules
[MESA_SHADER_VERTEX
] = NULL
;
2155 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2156 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.tcs
.outputs_written
);
2159 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2160 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2161 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2162 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2163 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_create(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2165 &keys
[pre_stage
] , &codes
[MESA_SHADER_GEOMETRY
],
2166 &code_sizes
[MESA_SHADER_GEOMETRY
]);
2168 modules
[pre_stage
] = NULL
;
2171 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2172 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2173 if (i
== MESA_SHADER_TESS_CTRL
) {
2174 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.ls_outputs_written
);
2176 if (i
== MESA_SHADER_TESS_EVAL
) {
2177 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2178 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.tcs
.outputs_written
);
2180 pipeline
->shaders
[i
] = radv_shader_variant_create(device
, modules
[i
], &nir
[i
], 1,
2182 keys
+ i
, &codes
[i
],
2187 if(modules
[MESA_SHADER_GEOMETRY
]) {
2188 void *gs_copy_code
= NULL
;
2189 unsigned gs_copy_code_size
= 0;
2190 if (!pipeline
->gs_copy_shader
) {
2191 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2192 device
, nir
[MESA_SHADER_GEOMETRY
], &gs_copy_code
,
2194 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2197 if (pipeline
->gs_copy_shader
) {
2198 void *code
[MESA_SHADER_STAGES
] = {0};
2199 unsigned code_size
[MESA_SHADER_STAGES
] = {0};
2200 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2202 code
[MESA_SHADER_GEOMETRY
] = gs_copy_code
;
2203 code_size
[MESA_SHADER_GEOMETRY
] = gs_copy_code_size
;
2204 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2206 radv_pipeline_cache_insert_shaders(device
, cache
,
2215 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2216 (const void**)codes
, code_sizes
);
2218 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2221 if (!pipeline
->device
->keep_shader_info
)
2222 ralloc_free(nir
[i
]);
2224 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2225 radv_shader_dump_stats(device
,
2226 pipeline
->shaders
[i
],
2232 ralloc_free(fs_m
.nir
);
2236 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2237 gl_shader_stage stage
, enum chip_class chip_class
)
2239 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2240 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2242 case MESA_SHADER_FRAGMENT
:
2243 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2244 case MESA_SHADER_VERTEX
:
2245 if (chip_class
>= GFX9
) {
2246 return has_tess
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2247 has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2248 R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2251 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
2253 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
: R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2254 case MESA_SHADER_GEOMETRY
:
2255 return chip_class
>= GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2256 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2257 case MESA_SHADER_COMPUTE
:
2258 return R_00B900_COMPUTE_USER_DATA_0
;
2259 case MESA_SHADER_TESS_CTRL
:
2260 return chip_class
>= GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2261 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2262 case MESA_SHADER_TESS_EVAL
:
2263 if (chip_class
>= GFX9
) {
2264 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2265 R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2268 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2270 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2272 unreachable("unknown shader");
2276 struct radv_bin_size_entry
{
2282 radv_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2284 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
2288 /* One shader engine */
2294 { UINT_MAX
, { 0, 0}},
2297 /* Two shader engines */
2303 { UINT_MAX
, { 0, 0}},
2306 /* Four shader engines */
2311 { UINT_MAX
, { 0, 0}},
2317 /* One shader engine */
2323 { UINT_MAX
, { 0, 0}},
2326 /* Two shader engines */
2332 { UINT_MAX
, { 0, 0}},
2335 /* Four shader engines */
2342 { UINT_MAX
, { 0, 0}},
2348 /* One shader engine */
2355 { UINT_MAX
, { 0, 0}},
2358 /* Two shader engines */
2366 { UINT_MAX
, { 0, 0}},
2369 /* Four shader engines */
2377 { UINT_MAX
, { 0, 0}},
2381 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
2385 // One shader engine
2392 { UINT_MAX
, { 0, 0}},
2395 // Two shader engines
2403 { UINT_MAX
, { 0, 0}},
2406 // Four shader engines
2414 { UINT_MAX
, { 0, 0}},
2420 // One shader engine
2428 { UINT_MAX
, { 0, 0}},
2431 // Two shader engines
2440 { UINT_MAX
, { 0, 0}},
2443 // Four shader engines
2452 { UINT_MAX
, { 0, 0}},
2458 // One shader engine
2466 { UINT_MAX
, { 0, 0}},
2469 // Two shader engines
2478 { UINT_MAX
, { 0, 0}},
2481 // Four shader engines
2489 { UINT_MAX
, { 0, 0}},
2494 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2495 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2496 VkExtent2D extent
= {512, 512};
2498 unsigned log_num_rb_per_se
=
2499 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
2500 pipeline
->device
->physical_device
->rad_info
.max_se
);
2501 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
2503 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
2504 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
2505 unsigned effective_samples
= total_samples
;
2506 unsigned color_bytes_per_pixel
= 0;
2508 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
2510 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2511 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
2514 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
2517 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
2518 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
2521 /* MSAA images typically don't use all samples all the time. */
2522 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
2523 effective_samples
= 2;
2524 color_bytes_per_pixel
*= effective_samples
;
2527 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
2528 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
2531 extent
= color_entry
->extent
;
2533 if (subpass
->depth_stencil_attachment
) {
2534 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
2536 /* Coefficients taken from AMDVLK */
2537 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
2538 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
2539 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
2541 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
2542 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
2545 extent
.width
= MIN2(extent
.width
, ds_entry
->extent
.width
);
2546 extent
.height
= MIN2(extent
.height
, ds_entry
->extent
.height
);
2553 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
2554 struct radv_pipeline
*pipeline
,
2555 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2557 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
2560 uint32_t pa_sc_binner_cntl_0
=
2561 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
2562 S_028C44_DISABLE_START_OF_PRIM(1);
2563 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
2565 VkExtent2D bin_size
= radv_compute_bin_size(pipeline
, pCreateInfo
);
2567 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
2568 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
2569 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
2571 switch (pipeline
->device
->physical_device
->rad_info
.family
) {
2575 context_states_per_bin
= 1;
2576 persistent_states_per_bin
= 1;
2577 fpovs_per_batch
= 63;
2581 context_states_per_bin
= 6;
2582 persistent_states_per_bin
= 32;
2583 fpovs_per_batch
= 63;
2586 unreachable("unhandled family while determining binning state.");
2589 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
2590 pa_sc_binner_cntl_0
=
2591 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
2592 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
2593 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
2594 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
2595 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
2596 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
- 1) |
2597 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
- 1) |
2598 S_028C44_DISABLE_START_OF_PRIM(1) |
2599 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
2600 S_028C44_OPTIMAL_BIN_SELECTION(1);
2603 radeon_set_context_reg(ctx_cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
2604 pa_sc_binner_cntl_0
);
2605 radeon_set_context_reg(ctx_cs
, R_028060_DB_DFSM_CONTROL
,
2611 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
2612 struct radv_pipeline
*pipeline
,
2613 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2614 const struct radv_graphics_pipeline_create_info
*extra
)
2616 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
2617 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2618 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2619 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
2620 struct radv_render_pass_attachment
*attachment
= NULL
;
2621 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
2622 uint32_t db_render_control
= 0, db_render_override2
= 0;
2623 uint32_t db_render_override
= 0;
2625 if (subpass
->depth_stencil_attachment
)
2626 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
2628 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
2629 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
2631 if (vkds
&& has_depth_attachment
) {
2632 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
2633 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
2634 S_028800_ZFUNC(vkds
->depthCompareOp
) |
2635 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
2637 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2638 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
2641 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
2642 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2643 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
2644 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
2645 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
2646 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
2648 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
2649 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
2650 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
2651 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
2654 if (attachment
&& extra
) {
2655 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
2656 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
2658 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
2659 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
2660 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
2661 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
2662 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
2665 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
2666 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
2668 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
2669 ps
->info
.info
.ps
.writes_z
) {
2670 /* From VK_EXT_depth_range_unrestricted spec:
2672 * "The behavior described in Primitive Clipping still applies.
2673 * If depth clamping is disabled the depth values are still
2674 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2675 * depth clamping is enabled the above equation is ignored and
2676 * the depth values are instead clamped to the VkViewport
2677 * minDepth and maxDepth values, which in the case of this
2678 * extension can be outside of the 0.0 to 1.0 range."
2680 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2683 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
2684 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
2686 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
2687 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
2688 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
2692 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
2693 struct radv_pipeline
*pipeline
,
2694 const struct radv_blend_state
*blend
)
2696 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
2697 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
2699 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
2700 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
2702 if (pipeline
->device
->physical_device
->has_rbplus
) {
2704 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
2705 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
2708 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
2710 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
2711 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
2713 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
2714 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
2717 static const VkConservativeRasterizationModeEXT
2718 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
2720 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
2721 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
2723 if (!conservative_raster
)
2724 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
2725 return conservative_raster
->conservativeRasterizationMode
;
2729 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
2730 struct radv_pipeline
*pipeline
,
2731 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2733 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
2734 const VkConservativeRasterizationModeEXT mode
=
2735 radv_get_conservative_raster_mode(vkraster
);
2736 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
2737 bool depth_clip_disable
= vkraster
->depthClampEnable
;
2739 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
2740 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
2741 if (depth_clip_state
) {
2742 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
2745 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
2746 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2747 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
2748 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
2749 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
2750 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2752 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
2753 S_0286D4_FLAT_SHADE_ENA(1) |
2754 S_0286D4_PNT_SPRITE_ENA(1) |
2755 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
2756 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
2757 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
2758 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
2759 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2761 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
2762 S_028BE4_PIX_CENTER(1) | // TODO verify
2763 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
2764 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
2766 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
2767 S_028814_FACE(vkraster
->frontFace
) |
2768 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
2769 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
2770 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
2771 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
2772 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
2773 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
2774 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
2775 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
2777 /* Conservative rasterization. */
2778 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
2779 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
2781 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
2782 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
2783 S_028804_OVERRASTERIZATION_AMOUNT(4);
2785 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
2786 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
2787 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
2789 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
2790 pa_sc_conservative_rast
|=
2791 S_028C4C_OVER_RAST_ENABLE(1) |
2792 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
2793 S_028C4C_UNDER_RAST_ENABLE(0) |
2794 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
2795 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
2797 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
2798 pa_sc_conservative_rast
|=
2799 S_028C4C_OVER_RAST_ENABLE(0) |
2800 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
2801 S_028C4C_UNDER_RAST_ENABLE(1) |
2802 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
2803 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
2807 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
2808 pa_sc_conservative_rast
);
2813 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
2814 struct radv_pipeline
*pipeline
)
2816 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
2818 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2819 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
2820 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
2822 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
2823 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
2825 /* The exclusion bits can be set to improve rasterization efficiency
2826 * if no sample lies on the pixel boundary (-8 sample offset). It's
2827 * currently always TRUE because the driver doesn't support 16 samples.
2829 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
2830 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
2831 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
2832 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
2836 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
2837 struct radv_pipeline
*pipeline
)
2839 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
2841 uint32_t vgt_primitiveid_en
= false;
2842 uint32_t vgt_gs_mode
= 0;
2844 if (radv_pipeline_has_gs(pipeline
)) {
2845 const struct radv_shader_variant
*gs
=
2846 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2848 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
2849 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2850 } else if (outinfo
->export_prim_id
) {
2851 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
2852 vgt_primitiveid_en
= true;
2855 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
2856 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
2860 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
2861 struct radeon_cmdbuf
*cs
,
2862 struct radv_pipeline
*pipeline
,
2863 struct radv_shader_variant
*shader
)
2865 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2867 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
2868 radeon_emit(cs
, va
>> 8);
2869 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
2870 radeon_emit(cs
, shader
->rsrc1
);
2871 radeon_emit(cs
, shader
->rsrc2
);
2873 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
2874 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
2875 clip_dist_mask
= outinfo
->clip_dist_mask
;
2876 cull_dist_mask
= outinfo
->cull_dist_mask
;
2877 total_mask
= clip_dist_mask
| cull_dist_mask
;
2878 bool misc_vec_ena
= outinfo
->writes_pointsize
||
2879 outinfo
->writes_layer
||
2880 outinfo
->writes_viewport_index
;
2882 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
2883 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo
->param_exports
) - 1));
2885 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
2886 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
2887 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
2888 V_02870C_SPI_SHADER_4COMP
:
2889 V_02870C_SPI_SHADER_NONE
) |
2890 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
2891 V_02870C_SPI_SHADER_4COMP
:
2892 V_02870C_SPI_SHADER_NONE
) |
2893 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
2894 V_02870C_SPI_SHADER_4COMP
:
2895 V_02870C_SPI_SHADER_NONE
));
2897 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
2898 S_028818_VTX_W0_FMT(1) |
2899 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2900 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2901 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2903 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
2904 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
2905 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
2906 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
2907 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2908 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
2909 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
2910 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
2911 cull_dist_mask
<< 8 |
2914 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= VI
)
2915 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
2916 outinfo
->writes_viewport_index
);
2920 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
2921 struct radv_pipeline
*pipeline
,
2922 struct radv_shader_variant
*shader
)
2924 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2926 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
2927 radeon_emit(cs
, va
>> 8);
2928 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
2929 radeon_emit(cs
, shader
->rsrc1
);
2930 radeon_emit(cs
, shader
->rsrc2
);
2934 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
2935 struct radv_pipeline
*pipeline
,
2936 struct radv_shader_variant
*shader
,
2937 const struct radv_tessellation_state
*tess
)
2939 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2940 uint32_t rsrc2
= shader
->rsrc2
;
2942 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
2943 radeon_emit(cs
, va
>> 8);
2944 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
2946 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
2947 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== CIK
&&
2948 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
2949 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
2951 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
2952 radeon_emit(cs
, shader
->rsrc1
);
2953 radeon_emit(cs
, rsrc2
);
2957 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
2958 struct radv_pipeline
*pipeline
,
2959 struct radv_shader_variant
*shader
,
2960 const struct radv_tessellation_state
*tess
)
2962 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2964 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2965 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
2966 radeon_emit(cs
, va
>> 8);
2967 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
2969 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
2970 radeon_emit(cs
, shader
->rsrc1
);
2971 radeon_emit(cs
, shader
->rsrc2
|
2972 S_00B42C_LDS_SIZE(tess
->lds_size
));
2974 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
2975 radeon_emit(cs
, va
>> 8);
2976 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
2977 radeon_emit(cs
, shader
->rsrc1
);
2978 radeon_emit(cs
, shader
->rsrc2
);
2983 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
2984 struct radeon_cmdbuf
*cs
,
2985 struct radv_pipeline
*pipeline
,
2986 const struct radv_tessellation_state
*tess
)
2988 struct radv_shader_variant
*vs
;
2990 /* Skip shaders merged into HS/GS */
2991 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
2995 if (vs
->info
.vs
.as_ls
)
2996 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
2997 else if (vs
->info
.vs
.as_es
)
2998 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
3000 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
3004 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
3005 struct radeon_cmdbuf
*cs
,
3006 struct radv_pipeline
*pipeline
,
3007 const struct radv_tessellation_state
*tess
)
3009 if (!radv_pipeline_has_tess(pipeline
))
3012 struct radv_shader_variant
*tes
, *tcs
;
3014 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
3015 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
3018 if (tes
->info
.tes
.as_es
)
3019 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
3021 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
3024 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
3026 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
3029 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
3030 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
3031 tess
->ls_hs_config
);
3033 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
3034 tess
->ls_hs_config
);
3038 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
3039 struct radeon_cmdbuf
*cs
,
3040 struct radv_pipeline
*pipeline
,
3041 const struct radv_gs_state
*gs_state
)
3043 struct radv_shader_variant
*gs
;
3044 unsigned gs_max_out_vertices
;
3045 uint8_t *num_components
;
3050 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3054 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
3055 max_stream
= gs
->info
.info
.gs
.max_stream
;
3056 num_components
= gs
->info
.info
.gs
.num_stream_output_components
;
3058 offset
= num_components
[0] * gs_max_out_vertices
;
3060 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
3061 radeon_emit(ctx_cs
, offset
);
3062 if (max_stream
>= 1)
3063 offset
+= num_components
[1] * gs_max_out_vertices
;
3064 radeon_emit(ctx_cs
, offset
);
3065 if (max_stream
>= 2)
3066 offset
+= num_components
[2] * gs_max_out_vertices
;
3067 radeon_emit(ctx_cs
, offset
);
3068 if (max_stream
>= 3)
3069 offset
+= num_components
[3] * gs_max_out_vertices
;
3070 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
3072 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
3074 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
3075 radeon_emit(ctx_cs
, num_components
[0]);
3076 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
3077 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
3078 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
3080 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
3081 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
3082 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
3083 S_028B90_ENABLE(gs_num_invocations
> 0));
3085 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3086 gs_state
->vgt_esgs_ring_itemsize
);
3088 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
3090 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3091 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
3092 radeon_emit(cs
, va
>> 8);
3093 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
3095 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3096 radeon_emit(cs
, gs
->rsrc1
);
3097 radeon_emit(cs
, gs
->rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
3099 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
3100 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
3102 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
3103 radeon_emit(cs
, va
>> 8);
3104 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
3105 radeon_emit(cs
, gs
->rsrc1
);
3106 radeon_emit(cs
, gs
->rsrc2
);
3109 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
3112 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
, bool float16
)
3114 uint32_t ps_input_cntl
;
3115 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3116 ps_input_cntl
= S_028644_OFFSET(offset
);
3118 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3120 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
3121 S_028644_ATTR0_VALID(1);
3124 /* The input is a DEFAULT_VAL constant. */
3125 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3126 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3127 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3128 ps_input_cntl
= S_028644_OFFSET(0x20) |
3129 S_028644_DEFAULT_VAL(offset
);
3131 return ps_input_cntl
;
3135 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
3136 struct radv_pipeline
*pipeline
)
3138 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3139 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3140 uint32_t ps_input_cntl
[32];
3142 unsigned ps_offset
= 0;
3144 if (ps
->info
.info
.ps
.prim_id_input
) {
3145 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
3146 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
3147 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
3152 if (ps
->info
.info
.ps
.layer_input
||
3153 ps
->info
.info
.ps
.uses_input_attachments
||
3154 ps
->info
.info
.needs_multiview_view_index
) {
3155 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
3156 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
3157 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
3159 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false);
3163 if (ps
->info
.info
.ps
.has_pcoord
) {
3165 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3166 ps_input_cntl
[ps_offset
] = val
;
3170 if (ps
->info
.info
.ps
.num_input_clips_culls
) {
3173 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
3174 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
3175 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
3179 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
3180 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
3181 ps
->info
.info
.ps
.num_input_clips_culls
> 4) {
3182 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
3187 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.fs
.input_mask
; ++i
) {
3191 if (!(ps
->info
.fs
.input_mask
& (1u << i
)))
3194 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
3195 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
3196 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
3201 flat_shade
= !!(ps
->info
.fs
.flat_shaded_mask
& (1u << ps_offset
));
3202 float16
= !!(ps
->info
.fs
.float16_shaded_mask
& (1u << ps_offset
));
3204 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, float16
);
3209 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
3210 for (unsigned i
= 0; i
< ps_offset
; i
++) {
3211 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
3217 radv_compute_db_shader_control(const struct radv_device
*device
,
3218 const struct radv_pipeline
*pipeline
,
3219 const struct radv_shader_variant
*ps
)
3222 if (ps
->info
.fs
.early_fragment_test
|| !ps
->info
.info
.ps
.writes_memory
)
3223 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
3225 z_order
= V_02880C_LATE_Z
;
3227 bool disable_rbplus
= device
->physical_device
->has_rbplus
&&
3228 !device
->physical_device
->rbplus_allowed
;
3230 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
3231 * but this appears to break Project Cars (DXVK). See
3232 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
3234 bool mask_export_enable
= ps
->info
.info
.ps
.writes_sample_mask
;
3236 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.info
.ps
.writes_z
) |
3237 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.info
.ps
.writes_stencil
) |
3238 S_02880C_KILL_ENABLE(!!ps
->info
.fs
.can_discard
) |
3239 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
3240 S_02880C_Z_ORDER(z_order
) |
3241 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.fs
.early_fragment_test
) |
3242 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.info
.ps
.writes_memory
) |
3243 S_02880C_EXEC_ON_NOOP(ps
->info
.info
.ps
.writes_memory
) |
3244 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
3248 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
3249 struct radeon_cmdbuf
*cs
,
3250 struct radv_pipeline
*pipeline
)
3252 struct radv_shader_variant
*ps
;
3254 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
3256 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3257 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
3259 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
3260 radeon_emit(cs
, va
>> 8);
3261 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
3262 radeon_emit(cs
, ps
->rsrc1
);
3263 radeon_emit(cs
, ps
->rsrc2
);
3265 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
3266 radv_compute_db_shader_control(pipeline
->device
,
3269 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
3270 ps
->config
.spi_ps_input_ena
);
3272 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
3273 ps
->config
.spi_ps_input_addr
);
3275 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
3276 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
3278 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
3280 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
3281 ac_get_spi_shader_z_format(ps
->info
.info
.ps
.writes_z
,
3282 ps
->info
.info
.ps
.writes_stencil
,
3283 ps
->info
.info
.ps
.writes_sample_mask
));
3285 if (pipeline
->device
->dfsm_allowed
) {
3286 /* optimise this? */
3287 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3288 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3293 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
3294 struct radv_pipeline
*pipeline
)
3296 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
3299 unsigned vtx_reuse_depth
= 30;
3300 if (radv_pipeline_has_tess(pipeline
) &&
3301 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
3302 vtx_reuse_depth
= 14;
3304 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
3305 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
3309 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
3311 uint32_t stages
= 0;
3312 if (radv_pipeline_has_tess(pipeline
)) {
3313 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3314 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3316 if (radv_pipeline_has_gs(pipeline
))
3317 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3319 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3321 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3323 } else if (radv_pipeline_has_gs(pipeline
))
3324 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3326 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3328 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
3329 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3335 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3337 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
3338 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
3340 if (!discard_rectangle_info
)
3345 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
3346 /* Interpret i as a bitmask, and then set the bit in the mask if
3347 * that combination of rectangles in which the pixel is contained
3348 * should pass the cliprect test. */
3349 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
3351 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
3355 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
3366 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
3367 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3368 const struct radv_graphics_pipeline_create_info
*extra
,
3369 const struct radv_blend_state
*blend
,
3370 const struct radv_tessellation_state
*tess
,
3371 const struct radv_gs_state
*gs
,
3372 unsigned prim
, unsigned gs_out
)
3374 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
3375 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
3378 ctx_cs
->max_dw
= 256;
3379 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
3380 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
3382 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
3383 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
3384 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
3385 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
3386 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
3387 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
3388 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
3389 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
, gs
);
3390 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
3391 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
3392 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
3393 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3395 radeon_set_context_reg(ctx_cs
, R_0286E8_SPI_TMPRING_SIZE
,
3396 S_0286E8_WAVES(pipeline
->max_waves
) |
3397 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
3399 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
3401 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3402 radeon_set_uconfig_reg_idx(cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
3404 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
3406 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
3408 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
3410 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
3412 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
3413 assert(cs
->cdw
<= cs
->max_dw
);
3416 static struct radv_ia_multi_vgt_param_helpers
3417 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
3418 const struct radv_tessellation_state
*tess
,
3421 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
3422 const struct radv_device
*device
= pipeline
->device
;
3424 if (radv_pipeline_has_tess(pipeline
))
3425 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
3426 else if (radv_pipeline_has_gs(pipeline
))
3427 ia_multi_vgt_param
.primgroup_size
= 64;
3429 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
3431 /* GS requirement. */
3432 ia_multi_vgt_param
.partial_es_wave
= false;
3433 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= VI
)
3434 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
3435 ia_multi_vgt_param
.partial_es_wave
= true;
3437 ia_multi_vgt_param
.wd_switch_on_eop
= false;
3438 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3439 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3440 * 4 shader engines. Set 1 to pass the assertion below.
3441 * The other cases are hardware requirements. */
3442 if (device
->physical_device
->rad_info
.max_se
< 4 ||
3443 prim
== V_008958_DI_PT_POLYGON
||
3444 prim
== V_008958_DI_PT_LINELOOP
||
3445 prim
== V_008958_DI_PT_TRIFAN
||
3446 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
3447 (pipeline
->graphics
.prim_restart_enable
&&
3448 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
3449 (prim
!= V_008958_DI_PT_POINTLIST
&&
3450 prim
!= V_008958_DI_PT_LINESTRIP
))))
3451 ia_multi_vgt_param
.wd_switch_on_eop
= true;
3454 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
3455 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
)
3456 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3457 if (radv_pipeline_has_gs(pipeline
) &&
3458 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.info
.uses_prim_id
)
3459 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3460 if (radv_pipeline_has_tess(pipeline
)) {
3461 /* SWITCH_ON_EOI must be set if PrimID is used. */
3462 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.uses_prim_id
||
3463 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.info
.uses_prim_id
)
3464 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3467 ia_multi_vgt_param
.partial_vs_wave
= false;
3468 if (radv_pipeline_has_tess(pipeline
)) {
3469 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3470 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
3471 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
3472 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
3473 radv_pipeline_has_gs(pipeline
))
3474 ia_multi_vgt_param
.partial_vs_wave
= true;
3475 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3476 if (device
->has_distributed_tess
) {
3477 if (radv_pipeline_has_gs(pipeline
)) {
3478 if (device
->physical_device
->rad_info
.chip_class
<= VI
)
3479 ia_multi_vgt_param
.partial_es_wave
= true;
3481 ia_multi_vgt_param
.partial_vs_wave
= true;
3486 /* Workaround for a VGT hang when strip primitive types are used with
3487 * primitive restart.
3489 if (pipeline
->graphics
.prim_restart_enable
&&
3490 (prim
== V_008958_DI_PT_LINESTRIP
||
3491 prim
== V_008958_DI_PT_TRISTRIP
||
3492 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
3493 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
3494 ia_multi_vgt_param
.partial_vs_wave
= true;
3497 if (radv_pipeline_has_gs(pipeline
)) {
3498 /* On these chips there is the possibility of a hang if the
3499 * pipeline uses a GS and partial_vs_wave is not set.
3501 * This mostly does not hit 4-SE chips, as those typically set
3502 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
3503 * with GS due to another workaround.
3505 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
3507 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
3508 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
3509 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
3510 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
3511 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
3512 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
3513 ia_multi_vgt_param
.partial_vs_wave
= true;
3517 ia_multi_vgt_param
.base
=
3518 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
3519 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3520 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== VI
? 2 : 0) |
3521 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
3522 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
3524 return ia_multi_vgt_param
;
3529 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
3530 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3532 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
3533 pCreateInfo
->pVertexInputState
;
3534 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
3536 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
3537 const VkVertexInputAttributeDescription
*desc
=
3538 &vi_info
->pVertexAttributeDescriptions
[i
];
3539 unsigned loc
= desc
->location
;
3540 const struct vk_format_description
*format_desc
;
3542 format_desc
= vk_format_description(desc
->format
);
3544 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
3547 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
3548 const VkVertexInputBindingDescription
*desc
=
3549 &vi_info
->pVertexBindingDescriptions
[i
];
3551 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
3552 pipeline
->num_vertex_bindings
=
3553 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
3557 static struct radv_shader_variant
*
3558 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
3562 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
3563 struct radv_shader_variant
*shader
=
3564 radv_get_shader(pipeline
, i
);
3566 if (shader
&& shader
->info
.info
.so
.num_outputs
> 0)
3574 radv_pipeline_init(struct radv_pipeline
*pipeline
,
3575 struct radv_device
*device
,
3576 struct radv_pipeline_cache
*cache
,
3577 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3578 const struct radv_graphics_pipeline_create_info
*extra
)
3581 bool has_view_index
= false;
3583 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3584 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3585 if (subpass
->view_mask
)
3586 has_view_index
= true;
3588 pipeline
->device
= device
;
3589 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
3590 assert(pipeline
->layout
);
3592 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
3594 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
3595 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
3596 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
3597 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
3600 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
3601 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
);
3603 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
3604 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
3606 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
3608 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
3610 if (radv_pipeline_has_gs(pipeline
)) {
3611 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
3612 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
3614 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
3616 if (extra
&& extra
->use_rectlist
) {
3617 prim
= V_008958_DI_PT_RECTLIST
;
3618 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
3619 pipeline
->graphics
.can_use_guardband
= true;
3621 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
3622 /* prim vertex count will need TESS changes */
3623 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
3625 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
3627 /* Ensure that some export memory is always allocated, for two reasons:
3629 * 1) Correctness: The hardware ignores the EXEC mask if no export
3630 * memory is allocated, so KILL and alpha test do not work correctly
3632 * 2) Performance: Every shader needs at least a NULL export, even when
3633 * it writes no color/depth output. The NULL export instruction
3634 * stalls without this setting.
3636 * Don't add this to CB_SHADER_MASK.
3638 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3639 if (!blend
.spi_shader_col_format
) {
3640 if (!ps
->info
.info
.ps
.writes_z
&&
3641 !ps
->info
.info
.ps
.writes_stencil
&&
3642 !ps
->info
.info
.ps
.writes_sample_mask
)
3643 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
3646 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
3647 if (pipeline
->shaders
[i
]) {
3648 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
3652 struct radv_gs_state gs
= {0};
3653 if (radv_pipeline_has_gs(pipeline
)) {
3654 gs
= calculate_gs_info(pCreateInfo
, pipeline
);
3655 calculate_gs_ring_sizes(pipeline
, &gs
);
3658 struct radv_tessellation_state tess
= {0};
3659 if (radv_pipeline_has_tess(pipeline
)) {
3660 if (prim
== V_008958_DI_PT_PATCH
) {
3661 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
3662 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
3664 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
3667 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
3669 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
3671 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
3672 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
3674 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
3675 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
3676 if (loc
->sgpr_idx
!= -1) {
3677 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
3678 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
3679 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
)
3680 pipeline
->graphics
.vtx_emit_num
= 3;
3682 pipeline
->graphics
.vtx_emit_num
= 2;
3685 /* Find the last vertex shader stage that eventually uses streamout. */
3686 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
3688 result
= radv_pipeline_scratch_init(device
, pipeline
);
3689 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, &gs
, prim
, gs_out
);
3695 radv_graphics_pipeline_create(
3697 VkPipelineCache _cache
,
3698 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3699 const struct radv_graphics_pipeline_create_info
*extra
,
3700 const VkAllocationCallbacks
*pAllocator
,
3701 VkPipeline
*pPipeline
)
3703 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3704 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
3705 struct radv_pipeline
*pipeline
;
3708 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
3709 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3710 if (pipeline
== NULL
)
3711 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3713 result
= radv_pipeline_init(pipeline
, device
, cache
,
3714 pCreateInfo
, extra
);
3715 if (result
!= VK_SUCCESS
) {
3716 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
3720 *pPipeline
= radv_pipeline_to_handle(pipeline
);
3725 VkResult
radv_CreateGraphicsPipelines(
3727 VkPipelineCache pipelineCache
,
3729 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
3730 const VkAllocationCallbacks
* pAllocator
,
3731 VkPipeline
* pPipelines
)
3733 VkResult result
= VK_SUCCESS
;
3736 for (; i
< count
; i
++) {
3738 r
= radv_graphics_pipeline_create(_device
,
3741 NULL
, pAllocator
, &pPipelines
[i
]);
3742 if (r
!= VK_SUCCESS
) {
3744 pPipelines
[i
] = VK_NULL_HANDLE
;
3753 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
3755 struct radv_shader_variant
*compute_shader
;
3756 struct radv_device
*device
= pipeline
->device
;
3757 unsigned compute_resource_limits
;
3758 unsigned waves_per_threadgroup
;
3761 pipeline
->cs
.buf
= malloc(20 * 4);
3762 pipeline
->cs
.max_dw
= 20;
3764 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3765 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
3767 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
3768 radeon_emit(&pipeline
->cs
, va
>> 8);
3769 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
3771 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
3772 radeon_emit(&pipeline
->cs
, compute_shader
->rsrc1
);
3773 radeon_emit(&pipeline
->cs
, compute_shader
->rsrc2
);
3775 radeon_set_sh_reg(&pipeline
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3776 S_00B860_WAVES(pipeline
->max_waves
) |
3777 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
3779 /* Calculate best compute resource limits. */
3780 waves_per_threadgroup
=
3781 DIV_ROUND_UP(compute_shader
->info
.cs
.block_size
[0] *
3782 compute_shader
->info
.cs
.block_size
[1] *
3783 compute_shader
->info
.cs
.block_size
[2], 64);
3784 compute_resource_limits
=
3785 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0);
3787 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3788 unsigned num_cu_per_se
=
3789 device
->physical_device
->rad_info
.num_good_compute_units
/
3790 device
->physical_device
->rad_info
.max_se
;
3792 /* Force even distribution on all SIMDs in CU if the workgroup
3793 * size is 64. This has shown some good improvements if # of
3794 * CUs per SE is not a multiple of 4.
3796 if (num_cu_per_se
% 4 && waves_per_threadgroup
== 1)
3797 compute_resource_limits
|= S_00B854_FORCE_SIMD_DIST(1);
3800 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
3801 compute_resource_limits
);
3803 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3804 radeon_emit(&pipeline
->cs
,
3805 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
3806 radeon_emit(&pipeline
->cs
,
3807 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
3808 radeon_emit(&pipeline
->cs
,
3809 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
3811 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
3814 static VkResult
radv_compute_pipeline_create(
3816 VkPipelineCache _cache
,
3817 const VkComputePipelineCreateInfo
* pCreateInfo
,
3818 const VkAllocationCallbacks
* pAllocator
,
3819 VkPipeline
* pPipeline
)
3821 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3822 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
3823 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
3824 struct radv_pipeline
*pipeline
;
3827 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
3828 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3829 if (pipeline
== NULL
)
3830 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3832 pipeline
->device
= device
;
3833 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
3834 assert(pipeline
->layout
);
3836 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
3837 radv_create_shaders(pipeline
, device
, cache
, &(struct radv_pipeline_key
) {0}, pStages
, pCreateInfo
->flags
);
3839 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
3840 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
3841 result
= radv_pipeline_scratch_init(device
, pipeline
);
3842 if (result
!= VK_SUCCESS
) {
3843 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
3847 radv_compute_generate_pm4(pipeline
);
3849 *pPipeline
= radv_pipeline_to_handle(pipeline
);
3854 VkResult
radv_CreateComputePipelines(
3856 VkPipelineCache pipelineCache
,
3858 const VkComputePipelineCreateInfo
* pCreateInfos
,
3859 const VkAllocationCallbacks
* pAllocator
,
3860 VkPipeline
* pPipelines
)
3862 VkResult result
= VK_SUCCESS
;
3865 for (; i
< count
; i
++) {
3867 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
3869 pAllocator
, &pPipelines
[i
]);
3870 if (r
!= VK_SUCCESS
) {
3872 pPipelines
[i
] = VK_NULL_HANDLE
;