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radv: port merge tess info from anv
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36 #include "vk_util.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40
41 #include "sid.h"
42 #include "gfx9d.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
49 #include "ac_shader_util.h"
50
51 static void
52 radv_pipeline_destroy(struct radv_device *device,
53 struct radv_pipeline *pipeline,
54 const VkAllocationCallbacks* allocator)
55 {
56 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
57 if (pipeline->shaders[i])
58 radv_shader_variant_destroy(device, pipeline->shaders[i]);
59
60 if (pipeline->gs_copy_shader)
61 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
62
63 vk_free2(&device->alloc, allocator, pipeline);
64 }
65
66 void radv_DestroyPipeline(
67 VkDevice _device,
68 VkPipeline _pipeline,
69 const VkAllocationCallbacks* pAllocator)
70 {
71 RADV_FROM_HANDLE(radv_device, device, _device);
72 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
73
74 if (!_pipeline)
75 return;
76
77 radv_pipeline_destroy(device, pipeline, pAllocator);
78 }
79
80 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
81 {
82 int i;
83
84 for (i = 0; i < MESA_SHADER_STAGES; i++) {
85 if (!pipeline->shaders[i])
86 continue;
87
88 radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr);
89 }
90 }
91
92 static uint32_t get_hash_flags(struct radv_device *device)
93 {
94 uint32_t hash_flags = 0;
95
96 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
97 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
98 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
99 hash_flags |= RADV_HASH_SHADER_SISCHED;
100 return hash_flags;
101 }
102
103 static VkResult
104 radv_pipeline_scratch_init(struct radv_device *device,
105 struct radv_pipeline *pipeline)
106 {
107 unsigned scratch_bytes_per_wave = 0;
108 unsigned max_waves = 0;
109 unsigned min_waves = 1;
110
111 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
112 if (pipeline->shaders[i]) {
113 unsigned max_stage_waves = device->scratch_waves;
114
115 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
116 pipeline->shaders[i]->config.scratch_bytes_per_wave);
117
118 max_stage_waves = MIN2(max_stage_waves,
119 4 * device->physical_device->rad_info.num_good_compute_units *
120 (256 / pipeline->shaders[i]->config.num_vgprs));
121 max_waves = MAX2(max_waves, max_stage_waves);
122 }
123 }
124
125 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
126 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
127 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
128 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
129 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
130 }
131
132 if (scratch_bytes_per_wave)
133 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
134
135 if (scratch_bytes_per_wave && max_waves < min_waves) {
136 /* Not really true at this moment, but will be true on first
137 * execution. Avoid having hanging shaders. */
138 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
139 }
140 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
141 pipeline->max_waves = max_waves;
142 return VK_SUCCESS;
143 }
144
145 static uint32_t si_translate_blend_function(VkBlendOp op)
146 {
147 switch (op) {
148 case VK_BLEND_OP_ADD:
149 return V_028780_COMB_DST_PLUS_SRC;
150 case VK_BLEND_OP_SUBTRACT:
151 return V_028780_COMB_SRC_MINUS_DST;
152 case VK_BLEND_OP_REVERSE_SUBTRACT:
153 return V_028780_COMB_DST_MINUS_SRC;
154 case VK_BLEND_OP_MIN:
155 return V_028780_COMB_MIN_DST_SRC;
156 case VK_BLEND_OP_MAX:
157 return V_028780_COMB_MAX_DST_SRC;
158 default:
159 return 0;
160 }
161 }
162
163 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
164 {
165 switch (factor) {
166 case VK_BLEND_FACTOR_ZERO:
167 return V_028780_BLEND_ZERO;
168 case VK_BLEND_FACTOR_ONE:
169 return V_028780_BLEND_ONE;
170 case VK_BLEND_FACTOR_SRC_COLOR:
171 return V_028780_BLEND_SRC_COLOR;
172 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
173 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
174 case VK_BLEND_FACTOR_DST_COLOR:
175 return V_028780_BLEND_DST_COLOR;
176 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
177 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
178 case VK_BLEND_FACTOR_SRC_ALPHA:
179 return V_028780_BLEND_SRC_ALPHA;
180 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
181 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
182 case VK_BLEND_FACTOR_DST_ALPHA:
183 return V_028780_BLEND_DST_ALPHA;
184 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
185 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
186 case VK_BLEND_FACTOR_CONSTANT_COLOR:
187 return V_028780_BLEND_CONSTANT_COLOR;
188 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
189 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
190 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
191 return V_028780_BLEND_CONSTANT_ALPHA;
192 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
193 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
194 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
195 return V_028780_BLEND_SRC_ALPHA_SATURATE;
196 case VK_BLEND_FACTOR_SRC1_COLOR:
197 return V_028780_BLEND_SRC1_COLOR;
198 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
199 return V_028780_BLEND_INV_SRC1_COLOR;
200 case VK_BLEND_FACTOR_SRC1_ALPHA:
201 return V_028780_BLEND_SRC1_ALPHA;
202 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
203 return V_028780_BLEND_INV_SRC1_ALPHA;
204 default:
205 return 0;
206 }
207 }
208
209 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
210 {
211 switch (op) {
212 case VK_BLEND_OP_ADD:
213 return V_028760_OPT_COMB_ADD;
214 case VK_BLEND_OP_SUBTRACT:
215 return V_028760_OPT_COMB_SUBTRACT;
216 case VK_BLEND_OP_REVERSE_SUBTRACT:
217 return V_028760_OPT_COMB_REVSUBTRACT;
218 case VK_BLEND_OP_MIN:
219 return V_028760_OPT_COMB_MIN;
220 case VK_BLEND_OP_MAX:
221 return V_028760_OPT_COMB_MAX;
222 default:
223 return V_028760_OPT_COMB_BLEND_DISABLED;
224 }
225 }
226
227 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
228 {
229 switch (factor) {
230 case VK_BLEND_FACTOR_ZERO:
231 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
232 case VK_BLEND_FACTOR_ONE:
233 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
234 case VK_BLEND_FACTOR_SRC_COLOR:
235 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
236 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
237 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
238 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
239 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
240 case VK_BLEND_FACTOR_SRC_ALPHA:
241 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
242 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
243 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
244 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
245 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
246 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
247 default:
248 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
249 }
250 }
251
252 /**
253 * Get rid of DST in the blend factors by commuting the operands:
254 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
255 */
256 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
257 unsigned *dst_factor, unsigned expected_dst,
258 unsigned replacement_src)
259 {
260 if (*src_factor == expected_dst &&
261 *dst_factor == VK_BLEND_FACTOR_ZERO) {
262 *src_factor = VK_BLEND_FACTOR_ZERO;
263 *dst_factor = replacement_src;
264
265 /* Commuting the operands requires reversing subtractions. */
266 if (*func == VK_BLEND_OP_SUBTRACT)
267 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
268 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
269 *func = VK_BLEND_OP_SUBTRACT;
270 }
271 }
272
273 static bool si_blend_factor_uses_dst(unsigned factor)
274 {
275 return factor == VK_BLEND_FACTOR_DST_COLOR ||
276 factor == VK_BLEND_FACTOR_DST_ALPHA ||
277 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
278 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
279 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
280 }
281
282 static bool is_dual_src(VkBlendFactor factor)
283 {
284 switch (factor) {
285 case VK_BLEND_FACTOR_SRC1_COLOR:
286 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
287 case VK_BLEND_FACTOR_SRC1_ALPHA:
288 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
289 return true;
290 default:
291 return false;
292 }
293 }
294
295 static unsigned si_choose_spi_color_format(VkFormat vk_format,
296 bool blend_enable,
297 bool blend_need_alpha)
298 {
299 const struct vk_format_description *desc = vk_format_description(vk_format);
300 unsigned format, ntype, swap;
301
302 /* Alpha is needed for alpha-to-coverage.
303 * Blending may be with or without alpha.
304 */
305 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
306 unsigned alpha = 0; /* exports alpha, but may not support blending */
307 unsigned blend = 0; /* supports blending, but may not export alpha */
308 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
309
310 format = radv_translate_colorformat(vk_format);
311 ntype = radv_translate_color_numformat(vk_format, desc,
312 vk_format_get_first_non_void_channel(vk_format));
313 swap = radv_translate_colorswap(vk_format, false);
314
315 /* Choose the SPI color formats. These are required values for Stoney/RB+.
316 * Other chips have multiple choices, though they are not necessarily better.
317 */
318 switch (format) {
319 case V_028C70_COLOR_5_6_5:
320 case V_028C70_COLOR_1_5_5_5:
321 case V_028C70_COLOR_5_5_5_1:
322 case V_028C70_COLOR_4_4_4_4:
323 case V_028C70_COLOR_10_11_11:
324 case V_028C70_COLOR_11_11_10:
325 case V_028C70_COLOR_8:
326 case V_028C70_COLOR_8_8:
327 case V_028C70_COLOR_8_8_8_8:
328 case V_028C70_COLOR_10_10_10_2:
329 case V_028C70_COLOR_2_10_10_10:
330 if (ntype == V_028C70_NUMBER_UINT)
331 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
332 else if (ntype == V_028C70_NUMBER_SINT)
333 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
334 else
335 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
336 break;
337
338 case V_028C70_COLOR_16:
339 case V_028C70_COLOR_16_16:
340 case V_028C70_COLOR_16_16_16_16:
341 if (ntype == V_028C70_NUMBER_UNORM ||
342 ntype == V_028C70_NUMBER_SNORM) {
343 /* UNORM16 and SNORM16 don't support blending */
344 if (ntype == V_028C70_NUMBER_UNORM)
345 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
346 else
347 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
348
349 /* Use 32 bits per channel for blending. */
350 if (format == V_028C70_COLOR_16) {
351 if (swap == V_028C70_SWAP_STD) { /* R */
352 blend = V_028714_SPI_SHADER_32_R;
353 blend_alpha = V_028714_SPI_SHADER_32_AR;
354 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
355 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
356 else
357 assert(0);
358 } else if (format == V_028C70_COLOR_16_16) {
359 if (swap == V_028C70_SWAP_STD) { /* RG */
360 blend = V_028714_SPI_SHADER_32_GR;
361 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
362 } else if (swap == V_028C70_SWAP_ALT) /* RA */
363 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
364 else
365 assert(0);
366 } else /* 16_16_16_16 */
367 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
368 } else if (ntype == V_028C70_NUMBER_UINT)
369 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
370 else if (ntype == V_028C70_NUMBER_SINT)
371 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
372 else if (ntype == V_028C70_NUMBER_FLOAT)
373 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
374 else
375 assert(0);
376 break;
377
378 case V_028C70_COLOR_32:
379 if (swap == V_028C70_SWAP_STD) { /* R */
380 blend = normal = V_028714_SPI_SHADER_32_R;
381 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
382 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
383 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
384 else
385 assert(0);
386 break;
387
388 case V_028C70_COLOR_32_32:
389 if (swap == V_028C70_SWAP_STD) { /* RG */
390 blend = normal = V_028714_SPI_SHADER_32_GR;
391 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
392 } else if (swap == V_028C70_SWAP_ALT) /* RA */
393 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
394 else
395 assert(0);
396 break;
397
398 case V_028C70_COLOR_32_32_32_32:
399 case V_028C70_COLOR_8_24:
400 case V_028C70_COLOR_24_8:
401 case V_028C70_COLOR_X24_8_32_FLOAT:
402 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
403 break;
404
405 default:
406 unreachable("unhandled blend format");
407 }
408
409 if (blend_enable && blend_need_alpha)
410 return blend_alpha;
411 else if(blend_need_alpha)
412 return alpha;
413 else if(blend_enable)
414 return blend;
415 else
416 return normal;
417 }
418
419 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
420 {
421 unsigned i, cb_shader_mask = 0;
422
423 for (i = 0; i < 8; i++) {
424 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
425 case V_028714_SPI_SHADER_ZERO:
426 break;
427 case V_028714_SPI_SHADER_32_R:
428 cb_shader_mask |= 0x1 << (i * 4);
429 break;
430 case V_028714_SPI_SHADER_32_GR:
431 cb_shader_mask |= 0x3 << (i * 4);
432 break;
433 case V_028714_SPI_SHADER_32_AR:
434 cb_shader_mask |= 0x9 << (i * 4);
435 break;
436 case V_028714_SPI_SHADER_FP16_ABGR:
437 case V_028714_SPI_SHADER_UNORM16_ABGR:
438 case V_028714_SPI_SHADER_SNORM16_ABGR:
439 case V_028714_SPI_SHADER_UINT16_ABGR:
440 case V_028714_SPI_SHADER_SINT16_ABGR:
441 case V_028714_SPI_SHADER_32_ABGR:
442 cb_shader_mask |= 0xf << (i * 4);
443 break;
444 default:
445 assert(0);
446 }
447 }
448 return cb_shader_mask;
449 }
450
451 static void
452 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
453 const VkGraphicsPipelineCreateInfo *pCreateInfo,
454 uint32_t blend_enable,
455 uint32_t blend_need_alpha,
456 bool single_cb_enable,
457 bool blend_mrt0_is_dual_src)
458 {
459 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
460 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
461 struct radv_blend_state *blend = &pipeline->graphics.blend;
462 unsigned col_format = 0;
463
464 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
465 unsigned cf;
466
467 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
468 cf = V_028714_SPI_SHADER_ZERO;
469 } else {
470 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
471
472 cf = si_choose_spi_color_format(attachment->format,
473 blend_enable & (1 << i),
474 blend_need_alpha & (1 << i));
475 }
476
477 col_format |= cf << (4 * i);
478 }
479
480 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
481
482 if (blend_mrt0_is_dual_src)
483 col_format |= (col_format & 0xf) << 4;
484 blend->spi_shader_col_format = col_format;
485 }
486
487 static bool
488 format_is_int8(VkFormat format)
489 {
490 const struct vk_format_description *desc = vk_format_description(format);
491 int channel = vk_format_get_first_non_void_channel(format);
492
493 return channel >= 0 && desc->channel[channel].pure_integer &&
494 desc->channel[channel].size == 8;
495 }
496
497 static bool
498 format_is_int10(VkFormat format)
499 {
500 const struct vk_format_description *desc = vk_format_description(format);
501
502 if (desc->nr_channels != 4)
503 return false;
504 for (unsigned i = 0; i < 4; i++) {
505 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
506 return true;
507 }
508 return false;
509 }
510
511 unsigned radv_format_meta_fs_key(VkFormat format)
512 {
513 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
514 bool is_int8 = format_is_int8(format);
515 bool is_int10 = format_is_int10(format);
516
517 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
518 }
519
520 static void
521 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
522 unsigned *is_int8, unsigned *is_int10)
523 {
524 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
525 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
526 *is_int8 = 0;
527 *is_int10 = 0;
528
529 for (unsigned i = 0; i < subpass->color_count; ++i) {
530 struct radv_render_pass_attachment *attachment;
531
532 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
533 continue;
534
535 attachment = pass->attachments + subpass->color_attachments[i].attachment;
536
537 if (format_is_int8(attachment->format))
538 *is_int8 |= 1 << i;
539 if (format_is_int10(attachment->format))
540 *is_int10 |= 1 << i;
541 }
542 }
543
544 static void
545 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
546 const VkGraphicsPipelineCreateInfo *pCreateInfo,
547 const struct radv_graphics_pipeline_create_info *extra)
548 {
549 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
550 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
551 struct radv_blend_state *blend = &pipeline->graphics.blend;
552 unsigned mode = V_028808_CB_NORMAL;
553 uint32_t blend_enable = 0, blend_need_alpha = 0;
554 bool blend_mrt0_is_dual_src = false;
555 int i;
556 bool single_cb_enable = false;
557
558 if (!vkblend)
559 return;
560
561 if (extra && extra->custom_blend_mode) {
562 single_cb_enable = true;
563 mode = extra->custom_blend_mode;
564 }
565 blend->cb_color_control = 0;
566 if (vkblend->logicOpEnable)
567 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
568 else
569 blend->cb_color_control |= S_028808_ROP3(0xcc);
570
571 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
572 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
573 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
574 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
575
576 if (vkms && vkms->alphaToCoverageEnable) {
577 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
578 }
579
580 blend->cb_target_mask = 0;
581 for (i = 0; i < vkblend->attachmentCount; i++) {
582 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
583 unsigned blend_cntl = 0;
584 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
585 VkBlendOp eqRGB = att->colorBlendOp;
586 VkBlendFactor srcRGB = att->srcColorBlendFactor;
587 VkBlendFactor dstRGB = att->dstColorBlendFactor;
588 VkBlendOp eqA = att->alphaBlendOp;
589 VkBlendFactor srcA = att->srcAlphaBlendFactor;
590 VkBlendFactor dstA = att->dstAlphaBlendFactor;
591
592 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
593
594 if (!att->colorWriteMask)
595 continue;
596
597 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
598 if (!att->blendEnable) {
599 blend->cb_blend_control[i] = blend_cntl;
600 continue;
601 }
602
603 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
604 if (i == 0)
605 blend_mrt0_is_dual_src = true;
606
607 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
608 srcRGB = VK_BLEND_FACTOR_ONE;
609 dstRGB = VK_BLEND_FACTOR_ONE;
610 }
611 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
612 srcA = VK_BLEND_FACTOR_ONE;
613 dstA = VK_BLEND_FACTOR_ONE;
614 }
615
616 /* Blending optimizations for RB+.
617 * These transformations don't change the behavior.
618 *
619 * First, get rid of DST in the blend factors:
620 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
621 */
622 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
623 VK_BLEND_FACTOR_DST_COLOR,
624 VK_BLEND_FACTOR_SRC_COLOR);
625
626 si_blend_remove_dst(&eqA, &srcA, &dstA,
627 VK_BLEND_FACTOR_DST_COLOR,
628 VK_BLEND_FACTOR_SRC_COLOR);
629
630 si_blend_remove_dst(&eqA, &srcA, &dstA,
631 VK_BLEND_FACTOR_DST_ALPHA,
632 VK_BLEND_FACTOR_SRC_ALPHA);
633
634 /* Look up the ideal settings from tables. */
635 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
636 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
637 srcA_opt = si_translate_blend_opt_factor(srcA, true);
638 dstA_opt = si_translate_blend_opt_factor(dstA, true);
639
640 /* Handle interdependencies. */
641 if (si_blend_factor_uses_dst(srcRGB))
642 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
643 if (si_blend_factor_uses_dst(srcA))
644 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
645
646 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
647 (dstRGB == VK_BLEND_FACTOR_ZERO ||
648 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
649 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
650 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
651
652 /* Set the final value. */
653 blend->sx_mrt_blend_opt[i] =
654 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
655 S_028760_COLOR_DST_OPT(dstRGB_opt) |
656 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
657 S_028760_ALPHA_SRC_OPT(srcA_opt) |
658 S_028760_ALPHA_DST_OPT(dstA_opt) |
659 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
660 blend_cntl |= S_028780_ENABLE(1);
661
662 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
663 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
664 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
665 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
666 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
667 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
668 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
669 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
670 }
671 blend->cb_blend_control[i] = blend_cntl;
672
673 blend_enable |= 1 << i;
674
675 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
676 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
677 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
678 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
679 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
680 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
681 blend_need_alpha |= 1 << i;
682 }
683 for (i = vkblend->attachmentCount; i < 8; i++) {
684 blend->cb_blend_control[i] = 0;
685 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
686 }
687
688 /* disable RB+ for now */
689 if (pipeline->device->physical_device->has_rbplus)
690 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
691
692 if (blend->cb_target_mask)
693 blend->cb_color_control |= S_028808_MODE(mode);
694 else
695 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
696
697 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
698 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
699 }
700
701 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
702 {
703 switch (op) {
704 case VK_STENCIL_OP_KEEP:
705 return V_02842C_STENCIL_KEEP;
706 case VK_STENCIL_OP_ZERO:
707 return V_02842C_STENCIL_ZERO;
708 case VK_STENCIL_OP_REPLACE:
709 return V_02842C_STENCIL_REPLACE_TEST;
710 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
711 return V_02842C_STENCIL_ADD_CLAMP;
712 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
713 return V_02842C_STENCIL_SUB_CLAMP;
714 case VK_STENCIL_OP_INVERT:
715 return V_02842C_STENCIL_INVERT;
716 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
717 return V_02842C_STENCIL_ADD_WRAP;
718 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
719 return V_02842C_STENCIL_SUB_WRAP;
720 default:
721 return 0;
722 }
723 }
724 static void
725 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
726 const VkGraphicsPipelineCreateInfo *pCreateInfo,
727 const struct radv_graphics_pipeline_create_info *extra)
728 {
729 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
730 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
731
732 if (!vkds)
733 return;
734
735 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
736 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
737 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
738 return;
739
740 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
741 bool has_depth_attachment = vk_format_is_depth(attachment->format);
742 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
743
744 if (has_depth_attachment) {
745 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
746 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
747 S_028800_ZFUNC(vkds->depthCompareOp) |
748 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
749 }
750
751 if (has_stencil_attachment && vkds->stencilTestEnable) {
752 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
753 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
754 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
755 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
756 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
757
758 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
759 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
760 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
761 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
762 }
763
764 if (extra) {
765
766 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
767 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
768
769 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
770 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
771 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
772 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
773 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
774 }
775 }
776
777 static uint32_t si_translate_fill(VkPolygonMode func)
778 {
779 switch(func) {
780 case VK_POLYGON_MODE_FILL:
781 return V_028814_X_DRAW_TRIANGLES;
782 case VK_POLYGON_MODE_LINE:
783 return V_028814_X_DRAW_LINES;
784 case VK_POLYGON_MODE_POINT:
785 return V_028814_X_DRAW_POINTS;
786 default:
787 assert(0);
788 return V_028814_X_DRAW_POINTS;
789 }
790 }
791 static void
792 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
793 const VkGraphicsPipelineCreateInfo *pCreateInfo)
794 {
795 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
796 struct radv_raster_state *raster = &pipeline->graphics.raster;
797
798 raster->spi_interp_control =
799 S_0286D4_FLAT_SHADE_ENA(1) |
800 S_0286D4_PNT_SPRITE_ENA(1) |
801 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
802 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
803 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
804 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
805 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
806
807
808 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
809 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
810 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
811 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
812 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
813 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
814
815 raster->pa_su_vtx_cntl =
816 S_028BE4_PIX_CENTER(1) | // TODO verify
817 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
818 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
819
820 raster->pa_su_sc_mode_cntl =
821 S_028814_FACE(vkraster->frontFace) |
822 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
823 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
824 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
825 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
826 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
827 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
828 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
829 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
830
831 }
832
833 static void
834 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
835 const VkGraphicsPipelineCreateInfo *pCreateInfo)
836 {
837 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
838 struct radv_multisample_state *ms = &pipeline->graphics.ms;
839 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
840 int ps_iter_samples = 1;
841 uint32_t mask = 0xffff;
842
843 if (vkms)
844 ms->num_samples = vkms->rasterizationSamples;
845 else
846 ms->num_samples = 1;
847
848 if (vkms && vkms->sampleShadingEnable) {
849 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
850 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
851 ps_iter_samples = ms->num_samples;
852 }
853
854 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
855 ms->pa_sc_aa_config = 0;
856 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
857 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
858 ms->pa_sc_mode_cntl_1 =
859 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
860 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
861 /* always 1: */
862 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
863 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
864 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
865 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
866 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
867 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
868 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
869
870 if (ms->num_samples > 1) {
871 unsigned log_samples = util_logbase2(ms->num_samples);
872 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
873 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
874 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
875 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
876 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
877 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
878 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
879 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
880 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
881 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
882 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
883 }
884
885 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
886 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
887 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
888 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
889 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
890 }
891
892 if (vkms && vkms->pSampleMask) {
893 mask = vkms->pSampleMask[0] & 0xffff;
894 }
895
896 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
897 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
898 }
899
900 static bool
901 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
902 {
903 switch (topology) {
904 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
905 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
906 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
907 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
908 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
909 return false;
910 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
911 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
912 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
913 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
914 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
915 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
916 return true;
917 default:
918 unreachable("unhandled primitive type");
919 }
920 }
921
922 static uint32_t
923 si_translate_prim(enum VkPrimitiveTopology topology)
924 {
925 switch (topology) {
926 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
927 return V_008958_DI_PT_POINTLIST;
928 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
929 return V_008958_DI_PT_LINELIST;
930 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
931 return V_008958_DI_PT_LINESTRIP;
932 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
933 return V_008958_DI_PT_TRILIST;
934 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
935 return V_008958_DI_PT_TRISTRIP;
936 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
937 return V_008958_DI_PT_TRIFAN;
938 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
939 return V_008958_DI_PT_LINELIST_ADJ;
940 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
941 return V_008958_DI_PT_LINESTRIP_ADJ;
942 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
943 return V_008958_DI_PT_TRILIST_ADJ;
944 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
945 return V_008958_DI_PT_TRISTRIP_ADJ;
946 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
947 return V_008958_DI_PT_PATCH;
948 default:
949 assert(0);
950 return 0;
951 }
952 }
953
954 static uint32_t
955 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
956 {
957 switch (gl_prim) {
958 case 0: /* GL_POINTS */
959 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
960 case 1: /* GL_LINES */
961 case 3: /* GL_LINE_STRIP */
962 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
963 case 0x8E7A: /* GL_ISOLINES */
964 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
965
966 case 4: /* GL_TRIANGLES */
967 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
968 case 5: /* GL_TRIANGLE_STRIP */
969 case 7: /* GL_QUADS */
970 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
971 default:
972 assert(0);
973 return 0;
974 }
975 }
976
977 static uint32_t
978 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
979 {
980 switch (topology) {
981 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
982 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
983 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
984 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
985 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
986 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
987 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
988 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
989 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
990 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
991 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
992 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
993 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
994 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
995 default:
996 assert(0);
997 return 0;
998 }
999 }
1000
1001 static unsigned si_map_swizzle(unsigned swizzle)
1002 {
1003 switch (swizzle) {
1004 case VK_SWIZZLE_Y:
1005 return V_008F0C_SQ_SEL_Y;
1006 case VK_SWIZZLE_Z:
1007 return V_008F0C_SQ_SEL_Z;
1008 case VK_SWIZZLE_W:
1009 return V_008F0C_SQ_SEL_W;
1010 case VK_SWIZZLE_0:
1011 return V_008F0C_SQ_SEL_0;
1012 case VK_SWIZZLE_1:
1013 return V_008F0C_SQ_SEL_1;
1014 default: /* VK_SWIZZLE_X */
1015 return V_008F0C_SQ_SEL_X;
1016 }
1017 }
1018
1019 static void
1020 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1021 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1022 {
1023 uint32_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1024 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1025 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1026
1027 pipeline->dynamic_state = default_dynamic_state;
1028
1029 if (pCreateInfo->pDynamicState) {
1030 /* Remove all of the states that are marked as dynamic */
1031 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1032 for (uint32_t s = 0; s < count; s++)
1033 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1034 }
1035
1036 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1037
1038 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1039 *
1040 * pViewportState is [...] NULL if the pipeline
1041 * has rasterization disabled.
1042 */
1043 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1044 assert(pCreateInfo->pViewportState);
1045
1046 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1047 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1048 typed_memcpy(dynamic->viewport.viewports,
1049 pCreateInfo->pViewportState->pViewports,
1050 pCreateInfo->pViewportState->viewportCount);
1051 }
1052
1053 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1054 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1055 typed_memcpy(dynamic->scissor.scissors,
1056 pCreateInfo->pViewportState->pScissors,
1057 pCreateInfo->pViewportState->scissorCount);
1058 }
1059 }
1060
1061 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1062 assert(pCreateInfo->pRasterizationState);
1063 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1064 }
1065
1066 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1067 assert(pCreateInfo->pRasterizationState);
1068 dynamic->depth_bias.bias =
1069 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1070 dynamic->depth_bias.clamp =
1071 pCreateInfo->pRasterizationState->depthBiasClamp;
1072 dynamic->depth_bias.slope =
1073 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1074 }
1075
1076 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1077 *
1078 * pColorBlendState is [...] NULL if the pipeline has rasterization
1079 * disabled or if the subpass of the render pass the pipeline is
1080 * created against does not use any color attachments.
1081 */
1082 bool uses_color_att = false;
1083 for (unsigned i = 0; i < subpass->color_count; ++i) {
1084 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1085 uses_color_att = true;
1086 break;
1087 }
1088 }
1089
1090 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1091 assert(pCreateInfo->pColorBlendState);
1092 typed_memcpy(dynamic->blend_constants,
1093 pCreateInfo->pColorBlendState->blendConstants, 4);
1094 }
1095
1096 /* If there is no depthstencil attachment, then don't read
1097 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1098 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1099 * no need to override the depthstencil defaults in
1100 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1101 *
1102 * Section 9.2 of the Vulkan 1.0.15 spec says:
1103 *
1104 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1105 * disabled or if the subpass of the render pass the pipeline is created
1106 * against does not use a depth/stencil attachment.
1107 */
1108 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1109 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1110 assert(pCreateInfo->pDepthStencilState);
1111
1112 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1113 dynamic->depth_bounds.min =
1114 pCreateInfo->pDepthStencilState->minDepthBounds;
1115 dynamic->depth_bounds.max =
1116 pCreateInfo->pDepthStencilState->maxDepthBounds;
1117 }
1118
1119 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1120 dynamic->stencil_compare_mask.front =
1121 pCreateInfo->pDepthStencilState->front.compareMask;
1122 dynamic->stencil_compare_mask.back =
1123 pCreateInfo->pDepthStencilState->back.compareMask;
1124 }
1125
1126 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1127 dynamic->stencil_write_mask.front =
1128 pCreateInfo->pDepthStencilState->front.writeMask;
1129 dynamic->stencil_write_mask.back =
1130 pCreateInfo->pDepthStencilState->back.writeMask;
1131 }
1132
1133 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1134 dynamic->stencil_reference.front =
1135 pCreateInfo->pDepthStencilState->front.reference;
1136 dynamic->stencil_reference.back =
1137 pCreateInfo->pDepthStencilState->back.reference;
1138 }
1139 }
1140
1141 pipeline->dynamic_state.mask = states;
1142 }
1143
1144 static void calculate_gfx9_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1145 struct radv_pipeline *pipeline)
1146 {
1147 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1148 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1149 &gs_info->tes.es_info : &gs_info->vs.es_info;
1150 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1151 bool uses_adjacency;
1152 switch(pCreateInfo->pInputAssemblyState->topology) {
1153 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1154 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1155 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1156 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1157 uses_adjacency = false;
1158 break;
1159 default:
1160 uses_adjacency = false;
1161 break;
1162 }
1163
1164 /* All these are in dwords: */
1165 /* We can't allow using the whole LDS, because GS waves compete with
1166 * other shader stages for LDS space. */
1167 const unsigned max_lds_size = 8 * 1024;
1168 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1169 unsigned esgs_lds_size;
1170
1171 /* All these are per subgroup: */
1172 const unsigned max_out_prims = 32 * 1024;
1173 const unsigned max_es_verts = 255;
1174 const unsigned ideal_gs_prims = 64;
1175 unsigned max_gs_prims, gs_prims;
1176 unsigned min_es_verts, es_verts, worst_case_es_verts;
1177
1178 if (uses_adjacency || gs_num_invocations > 1)
1179 max_gs_prims = 127 / gs_num_invocations;
1180 else
1181 max_gs_prims = 255;
1182
1183 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1184 * Make sure we don't go over the maximum value.
1185 */
1186 if (gs_info->gs.vertices_out > 0) {
1187 max_gs_prims = MIN2(max_gs_prims,
1188 max_out_prims /
1189 (gs_info->gs.vertices_out * gs_num_invocations));
1190 }
1191 assert(max_gs_prims > 0);
1192
1193 /* If the primitive has adjacency, halve the number of vertices
1194 * that will be reused in multiple primitives.
1195 */
1196 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1197
1198 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1199 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1200
1201 /* Compute ESGS LDS size based on the worst case number of ES vertices
1202 * needed to create the target number of GS prims per subgroup.
1203 */
1204 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1205
1206 /* If total LDS usage is too big, refactor partitions based on ratio
1207 * of ESGS item sizes.
1208 */
1209 if (esgs_lds_size > max_lds_size) {
1210 /* Our target GS Prims Per Subgroup was too large. Calculate
1211 * the maximum number of GS Prims Per Subgroup that will fit
1212 * into LDS, capped by the maximum that the hardware can support.
1213 */
1214 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1215 max_gs_prims);
1216 assert(gs_prims > 0);
1217 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1218 max_es_verts);
1219
1220 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1221 assert(esgs_lds_size <= max_lds_size);
1222 }
1223
1224 /* Now calculate remaining ESGS information. */
1225 if (esgs_lds_size)
1226 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1227 else
1228 es_verts = max_es_verts;
1229
1230 /* Vertices for adjacency primitives are not always reused, so restore
1231 * it for ES_VERTS_PER_SUBGRP.
1232 */
1233 min_es_verts = gs_info->gs.vertices_in;
1234
1235 /* For normal primitives, the VGT only checks if they are past the ES
1236 * verts per subgroup after allocating a full GS primitive and if they
1237 * are, kick off a new subgroup. But if those additional ES verts are
1238 * unique (e.g. not reused) we need to make sure there is enough LDS
1239 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1240 */
1241 es_verts -= min_es_verts - 1;
1242
1243 uint32_t es_verts_per_subgroup = es_verts;
1244 uint32_t gs_prims_per_subgroup = gs_prims;
1245 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1246 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1247 pipeline->graphics.gs.lds_size = align(esgs_lds_size, 128) / 128;
1248 pipeline->graphics.gs.vgt_gs_onchip_cntl =
1249 S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1250 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1251 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1252 pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup =
1253 S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1254 pipeline->graphics.gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1255 assert(max_prims_per_subgroup <= max_out_prims);
1256 }
1257
1258 static void
1259 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1260 {
1261 struct radv_device *device = pipeline->device;
1262 unsigned num_se = device->physical_device->rad_info.max_se;
1263 unsigned wave_size = 64;
1264 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1265 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1266 unsigned alignment = 256 * num_se;
1267 /* The maximum size is 63.999 MB per SE. */
1268 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1269 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1270 struct ac_es_output_info *es_info;
1271 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1272 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1273 else
1274 es_info = radv_pipeline_has_tess(pipeline) ?
1275 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1276 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1277
1278 /* Calculate the minimum size. */
1279 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1280 wave_size, alignment);
1281 /* These are recommended sizes, not minimum sizes. */
1282 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1283 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1284 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1285 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1286
1287 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1288 esgs_ring_size = align(esgs_ring_size, alignment);
1289 gsvs_ring_size = align(gsvs_ring_size, alignment);
1290
1291 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1292 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1293
1294 pipeline->graphics.gs.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1295 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1296 }
1297
1298 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1299 unsigned *lds_size)
1300 {
1301 /* SPI barrier management bug:
1302 * Make sure we have at least 4k of LDS in use to avoid the bug.
1303 * It applies to workgroup sizes of more than one wavefront.
1304 */
1305 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1306 device->physical_device->rad_info.family == CHIP_KABINI ||
1307 device->physical_device->rad_info.family == CHIP_MULLINS)
1308 *lds_size = MAX2(*lds_size, 8);
1309 }
1310
1311 struct radv_shader_variant *
1312 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1313 {
1314 if (pipeline->shaders[MESA_SHADER_VERTEX])
1315 return pipeline->shaders[MESA_SHADER_VERTEX];
1316 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1317 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1318 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1319 }
1320
1321 static struct radv_shader_variant *
1322 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1323 {
1324 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1325 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1326 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1327 }
1328
1329 static void
1330 calculate_tess_state(struct radv_pipeline *pipeline,
1331 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1332 {
1333 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1334 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1335 unsigned num_tcs_patch_outputs;
1336 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1337 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1338 unsigned lds_size, hardware_lds_size;
1339 unsigned perpatch_output_offset;
1340 unsigned num_patches;
1341 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1342
1343 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1344 * are laid out in LDS. */
1345 num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
1346
1347 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1348 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1349 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1350
1351 /* Ensure that we only need one wave per SIMD so we don't need to check
1352 * resource usage. Also ensures that the number of tcs in and out
1353 * vertices per threadgroup are at most 256.
1354 */
1355 input_vertex_size = num_tcs_inputs * 16;
1356 output_vertex_size = num_tcs_outputs * 16;
1357
1358 input_patch_size = num_tcs_input_cp * input_vertex_size;
1359
1360 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1361 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1362 /* Ensure that we only need one wave per SIMD so we don't need to check
1363 * resource usage. Also ensures that the number of tcs in and out
1364 * vertices per threadgroup are at most 256.
1365 */
1366 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1367
1368 /* Make sure that the data fits in LDS. This assumes the shaders only
1369 * use LDS for the inputs and outputs.
1370 */
1371 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1372 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1373
1374 /* Make sure the output data fits in the offchip buffer */
1375 num_patches = MIN2(num_patches,
1376 (pipeline->device->tess_offchip_block_dw_size * 4) /
1377 output_patch_size);
1378
1379 /* Not necessary for correctness, but improves performance. The
1380 * specific value is taken from the proprietary driver.
1381 */
1382 num_patches = MIN2(num_patches, 40);
1383
1384 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1385 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1386 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1387 num_patches = MIN2(num_patches, one_wave);
1388 }
1389
1390 output_patch0_offset = input_patch_size * num_patches;
1391 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1392
1393 lds_size = output_patch0_offset + output_patch_size * num_patches;
1394
1395 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1396 assert(lds_size <= 65536);
1397 lds_size = align(lds_size, 512) / 512;
1398 } else {
1399 assert(lds_size <= 32768);
1400 lds_size = align(lds_size, 256) / 256;
1401 }
1402 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1403
1404 tess->lds_size = lds_size;
1405
1406 tess->tcs_in_layout = (input_patch_size / 4) |
1407 ((input_vertex_size / 4) << 13);
1408 tess->tcs_out_layout = (output_patch_size / 4) |
1409 ((output_vertex_size / 4) << 13);
1410 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1411 ((perpatch_output_offset / 16) << 16);
1412 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1413 (num_tcs_output_cp << 9) | num_patches;
1414
1415 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1416 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1417 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1418 tess->num_patches = num_patches;
1419 tess->num_tcs_input_cp = num_tcs_input_cp;
1420
1421 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1422 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1423
1424 switch (tes->info.tes.primitive_mode) {
1425 case GL_TRIANGLES:
1426 type = V_028B6C_TESS_TRIANGLE;
1427 break;
1428 case GL_QUADS:
1429 type = V_028B6C_TESS_QUAD;
1430 break;
1431 case GL_ISOLINES:
1432 type = V_028B6C_TESS_ISOLINE;
1433 break;
1434 }
1435
1436 switch (tes->info.tes.spacing) {
1437 case TESS_SPACING_EQUAL:
1438 partitioning = V_028B6C_PART_INTEGER;
1439 break;
1440 case TESS_SPACING_FRACTIONAL_ODD:
1441 partitioning = V_028B6C_PART_FRAC_ODD;
1442 break;
1443 case TESS_SPACING_FRACTIONAL_EVEN:
1444 partitioning = V_028B6C_PART_FRAC_EVEN;
1445 break;
1446 default:
1447 break;
1448 }
1449
1450 bool ccw = tes->info.tes.ccw;
1451 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1452 vk_find_struct_const(pCreateInfo->pTessellationState,
1453 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1454
1455 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1456 ccw = !ccw;
1457
1458 if (tes->info.tes.point_mode)
1459 topology = V_028B6C_OUTPUT_POINT;
1460 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1461 topology = V_028B6C_OUTPUT_LINE;
1462 else if (ccw)
1463 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1464 else
1465 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1466
1467 if (pipeline->device->has_distributed_tess) {
1468 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1469 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1470 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1471 else
1472 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1473 } else
1474 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1475
1476 tess->tf_param = S_028B6C_TYPE(type) |
1477 S_028B6C_PARTITIONING(partitioning) |
1478 S_028B6C_TOPOLOGY(topology) |
1479 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1480 }
1481
1482 static const struct radv_prim_vertex_count prim_size_table[] = {
1483 [V_008958_DI_PT_NONE] = {0, 0},
1484 [V_008958_DI_PT_POINTLIST] = {1, 1},
1485 [V_008958_DI_PT_LINELIST] = {2, 2},
1486 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1487 [V_008958_DI_PT_TRILIST] = {3, 3},
1488 [V_008958_DI_PT_TRIFAN] = {3, 1},
1489 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1490 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1491 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1492 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1493 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1494 [V_008958_DI_PT_RECTLIST] = {3, 3},
1495 [V_008958_DI_PT_LINELOOP] = {2, 1},
1496 [V_008958_DI_PT_POLYGON] = {3, 1},
1497 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1498 };
1499
1500 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs,
1501 enum chip_class chip_class)
1502 {
1503 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1504 unsigned cut_mode;
1505
1506 if (gs_max_vert_out <= 128) {
1507 cut_mode = V_028A40_GS_CUT_128;
1508 } else if (gs_max_vert_out <= 256) {
1509 cut_mode = V_028A40_GS_CUT_256;
1510 } else if (gs_max_vert_out <= 512) {
1511 cut_mode = V_028A40_GS_CUT_512;
1512 } else {
1513 assert(gs_max_vert_out <= 1024);
1514 cut_mode = V_028A40_GS_CUT_1024;
1515 }
1516
1517 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1518 S_028A40_CUT_MODE(cut_mode)|
1519 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
1520 S_028A40_GS_WRITE_OPTIMIZE(1) |
1521 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
1522 }
1523
1524 static struct ac_vs_output_info *get_vs_output_info(struct radv_pipeline *pipeline)
1525 {
1526 if (radv_pipeline_has_gs(pipeline))
1527 return &pipeline->gs_copy_shader->info.vs.outinfo;
1528 else if (radv_pipeline_has_tess(pipeline))
1529 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1530 else
1531 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1532 }
1533
1534 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1535 {
1536 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1537
1538 pipeline->graphics.vgt_primitiveid_en = false;
1539 pipeline->graphics.vgt_gs_mode = 0;
1540
1541 if (radv_pipeline_has_gs(pipeline)) {
1542 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY],
1543 pipeline->device->physical_device->rad_info.chip_class);
1544 } else if (outinfo->export_prim_id) {
1545 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1546 pipeline->graphics.vgt_primitiveid_en = true;
1547 }
1548 }
1549
1550 static void calculate_vs_outinfo(struct radv_pipeline *pipeline)
1551 {
1552 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1553
1554 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1555 clip_dist_mask = outinfo->clip_dist_mask;
1556 cull_dist_mask = outinfo->cull_dist_mask;
1557 total_mask = clip_dist_mask | cull_dist_mask;
1558
1559 bool misc_vec_ena = outinfo->writes_pointsize ||
1560 outinfo->writes_layer ||
1561 outinfo->writes_viewport_index;
1562 pipeline->graphics.vs.pa_cl_vs_out_cntl =
1563 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1564 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1565 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1566 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1567 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1568 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1569 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1570 cull_dist_mask << 8 |
1571 clip_dist_mask;
1572
1573 pipeline->graphics.vs.spi_shader_pos_format =
1574 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1575 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
1576 V_02870C_SPI_SHADER_4COMP :
1577 V_02870C_SPI_SHADER_NONE) |
1578 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
1579 V_02870C_SPI_SHADER_4COMP :
1580 V_02870C_SPI_SHADER_NONE) |
1581 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
1582 V_02870C_SPI_SHADER_4COMP :
1583 V_02870C_SPI_SHADER_NONE);
1584
1585 pipeline->graphics.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1);
1586 /* only emitted on pre-VI */
1587 pipeline->graphics.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(outinfo->writes_viewport_index);
1588 }
1589
1590 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1591 {
1592 uint32_t ps_input_cntl;
1593 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1594 ps_input_cntl = S_028644_OFFSET(offset);
1595 if (flat_shade)
1596 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1597 } else {
1598 /* The input is a DEFAULT_VAL constant. */
1599 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1600 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1601 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1602 ps_input_cntl = S_028644_OFFSET(0x20) |
1603 S_028644_DEFAULT_VAL(offset);
1604 }
1605 return ps_input_cntl;
1606 }
1607
1608 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1609 {
1610 struct radv_shader_variant *ps;
1611 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1612
1613 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1614
1615 unsigned ps_offset = 0;
1616
1617 if (ps->info.fs.prim_id_input) {
1618 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1619 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1620 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1621 ++ps_offset;
1622 }
1623 }
1624
1625 if (ps->info.fs.layer_input) {
1626 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1627 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
1628 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1629 else
1630 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
1631 ++ps_offset;
1632 }
1633
1634 if (ps->info.fs.has_pcoord) {
1635 unsigned val;
1636 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1637 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1638 ps_offset++;
1639 }
1640
1641 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1642 unsigned vs_offset;
1643 bool flat_shade;
1644 if (!(ps->info.fs.input_mask & (1u << i)))
1645 continue;
1646
1647 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1648 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1649 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1650 ++ps_offset;
1651 continue;
1652 }
1653
1654 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1655
1656 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1657 ++ps_offset;
1658 }
1659
1660 pipeline->graphics.ps_input_cntl_num = ps_offset;
1661 }
1662
1663 static void
1664 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1665 {
1666 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1667 int shader_count = 0;
1668
1669 if(shaders[MESA_SHADER_FRAGMENT]) {
1670 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1671 }
1672 if(shaders[MESA_SHADER_GEOMETRY]) {
1673 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1674 }
1675 if(shaders[MESA_SHADER_TESS_EVAL]) {
1676 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1677 }
1678 if(shaders[MESA_SHADER_TESS_CTRL]) {
1679 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1680 }
1681 if(shaders[MESA_SHADER_VERTEX]) {
1682 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1683 }
1684
1685 for (int i = 1; i < shader_count; ++i) {
1686 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1687 ordered_shaders[i - 1]);
1688
1689 nir_remove_dead_variables(ordered_shaders[i],
1690 nir_var_shader_out);
1691 nir_remove_dead_variables(ordered_shaders[i - 1],
1692 nir_var_shader_in);
1693
1694 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1695 ordered_shaders[i - 1]);
1696
1697 if (progress) {
1698 nir_lower_global_vars_to_local(ordered_shaders[i]);
1699 radv_optimize_nir(ordered_shaders[i]);
1700 nir_lower_global_vars_to_local(ordered_shaders[i - 1]);
1701 radv_optimize_nir(ordered_shaders[i - 1]);
1702 }
1703 }
1704 }
1705
1706
1707 static struct radv_pipeline_key
1708 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1709 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1710 bool has_view_index)
1711 {
1712 const VkPipelineVertexInputStateCreateInfo *input_state =
1713 pCreateInfo->pVertexInputState;
1714 struct radv_pipeline_key key;
1715 memset(&key, 0, sizeof(key));
1716
1717 key.has_multiview_view_index = has_view_index;
1718
1719 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1720 unsigned binding;
1721 binding = input_state->pVertexAttributeDescriptions[i].binding;
1722 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1723 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1724 }
1725
1726 if (pCreateInfo->pTessellationState)
1727 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1728
1729
1730 if (pCreateInfo->pMultisampleState &&
1731 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
1732 key.multisample = true;
1733
1734 key.col_format = pipeline->graphics.blend.spi_shader_col_format;
1735 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1736 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1737
1738 return key;
1739 }
1740
1741 static void
1742 radv_fill_shader_keys(struct ac_shader_variant_key *keys,
1743 const struct radv_pipeline_key *key,
1744 nir_shader **nir)
1745 {
1746 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1747
1748 if (nir[MESA_SHADER_TESS_CTRL]) {
1749 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1750 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1751 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1752
1753 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1754 }
1755
1756 if (nir[MESA_SHADER_GEOMETRY]) {
1757 if (nir[MESA_SHADER_TESS_CTRL])
1758 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1759 else
1760 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1761 }
1762
1763 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1764 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1765
1766 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1767 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1768 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1769 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1770 }
1771
1772 static void
1773 merge_tess_info(struct shader_info *tes_info,
1774 const struct shader_info *tcs_info)
1775 {
1776 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1777 *
1778 * "PointMode. Controls generation of points rather than triangles
1779 * or lines. This functionality defaults to disabled, and is
1780 * enabled if either shader stage includes the execution mode.
1781 *
1782 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1783 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1784 * and OutputVertices, it says:
1785 *
1786 * "One mode must be set in at least one of the tessellation
1787 * shader stages."
1788 *
1789 * So, the fields can be set in either the TCS or TES, but they must
1790 * agree if set in both. Our backend looks at TES, so bitwise-or in
1791 * the values from the TCS.
1792 */
1793 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1794 tes_info->tess.tcs_vertices_out == 0 ||
1795 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1796 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1797
1798 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1799 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1800 tcs_info->tess.spacing == tes_info->tess.spacing);
1801 tes_info->tess.spacing |= tcs_info->tess.spacing;
1802
1803 assert(tcs_info->tess.primitive_mode == 0 ||
1804 tes_info->tess.primitive_mode == 0 ||
1805 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1806 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1807 tes_info->tess.ccw |= tcs_info->tess.ccw;
1808 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1809 }
1810
1811 static
1812 void radv_create_shaders(struct radv_pipeline *pipeline,
1813 struct radv_device *device,
1814 struct radv_pipeline_cache *cache,
1815 struct radv_pipeline_key key,
1816 const VkPipelineShaderStageCreateInfo **pStages)
1817 {
1818 struct radv_shader_module fs_m = {0};
1819 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1820 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1821 void *codes[MESA_SHADER_STAGES] = {0};
1822 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1823 struct ac_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1824 unsigned char hash[20], gs_copy_hash[20];
1825
1826 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1827 if (pStages[i]) {
1828 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1829 if (modules[i]->nir)
1830 _mesa_sha1_compute(modules[i]->nir->info.name,
1831 strlen(modules[i]->nir->info.name),
1832 modules[i]->sha1);
1833 }
1834 }
1835
1836 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1837 memcpy(gs_copy_hash, hash, 20);
1838 gs_copy_hash[0] ^= 1;
1839
1840 if (modules[MESA_SHADER_GEOMETRY]) {
1841 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1842 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1843 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1844 }
1845
1846 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1847 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1848 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1849 if (pipeline->shaders[i])
1850 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1851 }
1852 return;
1853 }
1854
1855 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1856 nir_builder fs_b;
1857 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1858 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1859 fs_m.nir = fs_b.shader;
1860 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1861 }
1862
1863 /* Determine first and last stage. */
1864 unsigned first = MESA_SHADER_STAGES;
1865 unsigned last = 0;
1866 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1867 if (!pStages[i])
1868 continue;
1869 if (first == MESA_SHADER_STAGES)
1870 first = i;
1871 last = i;
1872 }
1873
1874 int prev = -1;
1875 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1876 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1877
1878 if (!modules[i])
1879 continue;
1880
1881 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1882 stage ? stage->pName : "main", i,
1883 stage ? stage->pSpecializationInfo : NULL);
1884 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1885
1886 /* We don't want to alter meta shaders IR directly so clone it
1887 * first.
1888 */
1889 if (nir[i]->info.name) {
1890 nir[i] = nir_shader_clone(NULL, nir[i]);
1891 }
1892
1893 if (first != last) {
1894 nir_variable_mode mask = 0;
1895
1896 if (i != first)
1897 mask = mask | nir_var_shader_in;
1898
1899 if (i != last)
1900 mask = mask | nir_var_shader_out;
1901
1902 nir_lower_io_to_scalar_early(nir[i], mask);
1903 radv_optimize_nir(nir[i]);
1904 }
1905
1906 if (prev != -1) {
1907 nir_compact_varyings(nir[prev], nir[i], true);
1908 }
1909 prev = i;
1910 }
1911
1912 if (nir[MESA_SHADER_TESS_CTRL]) {
1913 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1914 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1915 }
1916
1917 radv_link_shaders(pipeline, nir);
1918
1919 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1920 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1921 nir_print_shader(nir[i], stderr);
1922 }
1923
1924 radv_fill_shader_keys(keys, &key, nir);
1925
1926 if (nir[MESA_SHADER_FRAGMENT]) {
1927 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1928 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1929 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1930 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1931 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1932 }
1933
1934 /* TODO: These are no longer used as keys we should refactor this */
1935 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1936 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1937 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1938 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1939 }
1940
1941 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1942 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1943 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1944 struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1945 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1946 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1947 pipeline->layout,
1948 &key, &codes[MESA_SHADER_TESS_CTRL],
1949 &code_sizes[MESA_SHADER_TESS_CTRL]);
1950 }
1951 modules[MESA_SHADER_VERTEX] = NULL;
1952 }
1953
1954 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1955 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1956 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1957 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1958 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1959 pipeline->layout,
1960 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1961 &code_sizes[MESA_SHADER_GEOMETRY]);
1962 }
1963 modules[pre_stage] = NULL;
1964 }
1965
1966 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1967 if(modules[i] && !pipeline->shaders[i]) {
1968 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
1969 pipeline->layout,
1970 keys + i, &codes[i],
1971 &code_sizes[i]);
1972 }
1973 }
1974
1975 if(modules[MESA_SHADER_GEOMETRY]) {
1976 void *gs_copy_code = NULL;
1977 unsigned gs_copy_code_size = 0;
1978 if (!pipeline->gs_copy_shader) {
1979 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
1980 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
1981 &gs_copy_code_size,
1982 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
1983 }
1984
1985 if (pipeline->gs_copy_shader) {
1986 void *code[MESA_SHADER_STAGES] = {0};
1987 unsigned code_size[MESA_SHADER_STAGES] = {0};
1988 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1989
1990 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
1991 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
1992 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
1993
1994 radv_pipeline_cache_insert_shaders(device, cache,
1995 gs_copy_hash,
1996 variants,
1997 (const void**)code,
1998 code_size);
1999 }
2000 free(gs_copy_code);
2001 }
2002
2003 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2004 (const void**)codes, code_sizes);
2005
2006 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2007 free(codes[i]);
2008 if (modules[i] && !pipeline->device->keep_shader_info)
2009 ralloc_free(nir[i]);
2010 }
2011
2012 if (fs_m.nir)
2013 ralloc_free(fs_m.nir);
2014 }
2015
2016 static uint32_t
2017 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2018 gl_shader_stage stage, enum chip_class chip_class)
2019 {
2020 bool has_gs = radv_pipeline_has_gs(pipeline);
2021 bool has_tess = radv_pipeline_has_tess(pipeline);
2022 switch (stage) {
2023 case MESA_SHADER_FRAGMENT:
2024 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2025 case MESA_SHADER_VERTEX:
2026 if (chip_class >= GFX9) {
2027 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2028 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2029 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2030 }
2031 if (has_tess)
2032 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2033 else
2034 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
2035 case MESA_SHADER_GEOMETRY:
2036 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2037 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2038 case MESA_SHADER_COMPUTE:
2039 return R_00B900_COMPUTE_USER_DATA_0;
2040 case MESA_SHADER_TESS_CTRL:
2041 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2042 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2043 case MESA_SHADER_TESS_EVAL:
2044 if (chip_class >= GFX9) {
2045 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2046 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2047 }
2048 if (has_gs)
2049 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2050 else
2051 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2052 default:
2053 unreachable("unknown shader");
2054 }
2055 }
2056
2057
2058 static VkResult
2059 radv_pipeline_init(struct radv_pipeline *pipeline,
2060 struct radv_device *device,
2061 struct radv_pipeline_cache *cache,
2062 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2063 const struct radv_graphics_pipeline_create_info *extra,
2064 const VkAllocationCallbacks *alloc)
2065 {
2066 VkResult result;
2067 bool has_view_index = false;
2068
2069 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2070 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2071 if (subpass->view_mask)
2072 has_view_index = true;
2073 if (alloc == NULL)
2074 alloc = &device->alloc;
2075
2076 pipeline->device = device;
2077 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2078
2079 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2080 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2081
2082 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2083 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2084 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2085 pStages[stage] = &pCreateInfo->pStages[i];
2086 }
2087
2088 radv_create_shaders(pipeline, device, cache,
2089 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, has_view_index),
2090 pStages);
2091
2092 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2093 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2094 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2095 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2096 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2097
2098 if (radv_pipeline_has_gs(pipeline)) {
2099 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2100 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2101 } else {
2102 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2103 }
2104 if (extra && extra->use_rectlist) {
2105 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2106 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2107 pipeline->graphics.can_use_guardband = true;
2108 }
2109 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2110 /* prim vertex count will need TESS changes */
2111 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2112
2113 /* Ensure that some export memory is always allocated, for two reasons:
2114 *
2115 * 1) Correctness: The hardware ignores the EXEC mask if no export
2116 * memory is allocated, so KILL and alpha test do not work correctly
2117 * without this.
2118 * 2) Performance: Every shader needs at least a NULL export, even when
2119 * it writes no color/depth output. The NULL export instruction
2120 * stalls without this setting.
2121 *
2122 * Don't add this to CB_SHADER_MASK.
2123 */
2124 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2125 if (!pipeline->graphics.blend.spi_shader_col_format) {
2126 if (!ps->info.fs.writes_z &&
2127 !ps->info.fs.writes_stencil &&
2128 !ps->info.fs.writes_sample_mask)
2129 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2130 }
2131
2132 unsigned z_order;
2133 pipeline->graphics.db_shader_control = 0;
2134 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2135 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2136 else
2137 z_order = V_02880C_LATE_Z;
2138
2139 pipeline->graphics.db_shader_control =
2140 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2141 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2142 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2143 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2144 S_02880C_Z_ORDER(z_order) |
2145 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2146 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2147 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2148
2149 if (pipeline->device->physical_device->has_rbplus)
2150 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
2151
2152 unsigned shader_z_format =
2153 ac_get_spi_shader_z_format(ps->info.fs.writes_z,
2154 ps->info.fs.writes_stencil,
2155 ps->info.fs.writes_sample_mask);
2156 pipeline->graphics.shader_z_format = shader_z_format;
2157
2158 calculate_vgt_gs_mode(pipeline);
2159 calculate_vs_outinfo(pipeline);
2160 calculate_ps_inputs(pipeline);
2161
2162 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2163 if (pipeline->shaders[i]) {
2164 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2165 }
2166 }
2167
2168 uint32_t stages = 0;
2169 if (radv_pipeline_has_tess(pipeline)) {
2170 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2171 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2172
2173 if (radv_pipeline_has_gs(pipeline))
2174 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2175 S_028B54_GS_EN(1) |
2176 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2177 else
2178 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2179
2180 } else if (radv_pipeline_has_gs(pipeline))
2181 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2182 S_028B54_GS_EN(1) |
2183 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2184
2185 if (device->physical_device->rad_info.chip_class >= GFX9)
2186 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2187
2188 pipeline->graphics.vgt_shader_stages_en = stages;
2189
2190 if (radv_pipeline_has_gs(pipeline)) {
2191 calculate_gs_ring_sizes(pipeline);
2192 if (device->physical_device->rad_info.chip_class >= GFX9)
2193 calculate_gfx9_gs_info(pCreateInfo, pipeline);
2194 }
2195
2196 if (radv_pipeline_has_tess(pipeline)) {
2197 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2198 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2199 pipeline->graphics.prim_vertex_count.incr = 1;
2200 }
2201 calculate_tess_state(pipeline, pCreateInfo);
2202 }
2203
2204 if (radv_pipeline_has_tess(pipeline))
2205 pipeline->graphics.primgroup_size = pipeline->graphics.tess.num_patches;
2206 else if (radv_pipeline_has_gs(pipeline))
2207 pipeline->graphics.primgroup_size = 64;
2208 else
2209 pipeline->graphics.primgroup_size = 128; /* recommended without a GS */
2210
2211 pipeline->graphics.partial_es_wave = false;
2212 if (pipeline->device->has_distributed_tess) {
2213 if (radv_pipeline_has_gs(pipeline)) {
2214 if (device->physical_device->rad_info.chip_class <= VI)
2215 pipeline->graphics.partial_es_wave = true;
2216 }
2217 }
2218 /* GS requirement. */
2219 if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= pipeline->device->gs_table_depth - 3)
2220 pipeline->graphics.partial_es_wave = true;
2221
2222 pipeline->graphics.wd_switch_on_eop = false;
2223 if (device->physical_device->rad_info.chip_class >= CIK) {
2224 unsigned prim = pipeline->graphics.prim;
2225 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
2226 * 4 shader engines. Set 1 to pass the assertion below.
2227 * The other cases are hardware requirements. */
2228 if (device->physical_device->rad_info.max_se < 4 ||
2229 prim == V_008958_DI_PT_POLYGON ||
2230 prim == V_008958_DI_PT_LINELOOP ||
2231 prim == V_008958_DI_PT_TRIFAN ||
2232 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
2233 (pipeline->graphics.prim_restart_enable &&
2234 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
2235 (prim != V_008958_DI_PT_POINTLIST &&
2236 prim != V_008958_DI_PT_LINESTRIP &&
2237 prim != V_008958_DI_PT_TRISTRIP))))
2238 pipeline->graphics.wd_switch_on_eop = true;
2239 }
2240
2241 pipeline->graphics.ia_switch_on_eoi = false;
2242 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2243 pipeline->graphics.ia_switch_on_eoi = true;
2244 if (radv_pipeline_has_gs(pipeline) &&
2245 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.uses_prim_id)
2246 pipeline->graphics.ia_switch_on_eoi = true;
2247 if (radv_pipeline_has_tess(pipeline)) {
2248 /* SWITCH_ON_EOI must be set if PrimID is used. */
2249 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
2250 radv_get_tess_eval_shader(pipeline)->info.tes.uses_prim_id)
2251 pipeline->graphics.ia_switch_on_eoi = true;
2252 }
2253
2254 pipeline->graphics.partial_vs_wave = false;
2255 if (radv_pipeline_has_tess(pipeline)) {
2256 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
2257 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
2258 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
2259 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
2260 radv_pipeline_has_gs(pipeline))
2261 pipeline->graphics.partial_vs_wave = true;
2262 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
2263 if (device->has_distributed_tess) {
2264 if (radv_pipeline_has_gs(pipeline)) {
2265 if (device->physical_device->rad_info.family == CHIP_TONGA ||
2266 device->physical_device->rad_info.family == CHIP_FIJI ||
2267 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
2268 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
2269 device->physical_device->rad_info.family == CHIP_POLARIS12)
2270 pipeline->graphics.partial_vs_wave = true;
2271 } else {
2272 pipeline->graphics.partial_vs_wave = true;
2273 }
2274 }
2275 }
2276
2277 pipeline->graphics.base_ia_multi_vgt_param =
2278 S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
2279 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
2280 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
2281 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
2282 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
2283
2284 const VkPipelineVertexInputStateCreateInfo *vi_info =
2285 pCreateInfo->pVertexInputState;
2286 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
2287
2288 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2289 const VkVertexInputAttributeDescription *desc =
2290 &vi_info->pVertexAttributeDescriptions[i];
2291 unsigned loc = desc->location;
2292 const struct vk_format_description *format_desc;
2293 int first_non_void;
2294 uint32_t num_format, data_format;
2295 format_desc = vk_format_description(desc->format);
2296 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2297
2298 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2299 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2300
2301 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2302 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2303 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2304 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2305 S_008F0C_NUM_FORMAT(num_format) |
2306 S_008F0C_DATA_FORMAT(data_format);
2307 velems->format_size[loc] = format_desc->block.bits / 8;
2308 velems->offset[loc] = desc->offset;
2309 velems->binding[loc] = desc->binding;
2310 velems->count = MAX2(velems->count, loc + 1);
2311 }
2312
2313 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2314 const VkVertexInputBindingDescription *desc =
2315 &vi_info->pVertexBindingDescriptions[i];
2316
2317 pipeline->binding_stride[desc->binding] = desc->stride;
2318 }
2319
2320 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
2321 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
2322
2323 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2324 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2325 if (loc->sgpr_idx != -1) {
2326 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
2327 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2328 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
2329 pipeline->graphics.vtx_emit_num = 3;
2330 else
2331 pipeline->graphics.vtx_emit_num = 2;
2332 }
2333
2334 pipeline->graphics.vtx_reuse_depth = 30;
2335 if (radv_pipeline_has_tess(pipeline) &&
2336 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2337 pipeline->graphics.vtx_reuse_depth = 14;
2338 }
2339
2340 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2341 radv_dump_pipeline_stats(device, pipeline);
2342 }
2343
2344 result = radv_pipeline_scratch_init(device, pipeline);
2345 return result;
2346 }
2347
2348 VkResult
2349 radv_graphics_pipeline_create(
2350 VkDevice _device,
2351 VkPipelineCache _cache,
2352 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2353 const struct radv_graphics_pipeline_create_info *extra,
2354 const VkAllocationCallbacks *pAllocator,
2355 VkPipeline *pPipeline)
2356 {
2357 RADV_FROM_HANDLE(radv_device, device, _device);
2358 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2359 struct radv_pipeline *pipeline;
2360 VkResult result;
2361
2362 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2363 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2364 if (pipeline == NULL)
2365 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2366
2367 result = radv_pipeline_init(pipeline, device, cache,
2368 pCreateInfo, extra, pAllocator);
2369 if (result != VK_SUCCESS) {
2370 radv_pipeline_destroy(device, pipeline, pAllocator);
2371 return result;
2372 }
2373
2374 *pPipeline = radv_pipeline_to_handle(pipeline);
2375
2376 return VK_SUCCESS;
2377 }
2378
2379 VkResult radv_CreateGraphicsPipelines(
2380 VkDevice _device,
2381 VkPipelineCache pipelineCache,
2382 uint32_t count,
2383 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2384 const VkAllocationCallbacks* pAllocator,
2385 VkPipeline* pPipelines)
2386 {
2387 VkResult result = VK_SUCCESS;
2388 unsigned i = 0;
2389
2390 for (; i < count; i++) {
2391 VkResult r;
2392 r = radv_graphics_pipeline_create(_device,
2393 pipelineCache,
2394 &pCreateInfos[i],
2395 NULL, pAllocator, &pPipelines[i]);
2396 if (r != VK_SUCCESS) {
2397 result = r;
2398 pPipelines[i] = VK_NULL_HANDLE;
2399 }
2400 }
2401
2402 return result;
2403 }
2404
2405 static VkResult radv_compute_pipeline_create(
2406 VkDevice _device,
2407 VkPipelineCache _cache,
2408 const VkComputePipelineCreateInfo* pCreateInfo,
2409 const VkAllocationCallbacks* pAllocator,
2410 VkPipeline* pPipeline)
2411 {
2412 RADV_FROM_HANDLE(radv_device, device, _device);
2413 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2414 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2415 struct radv_pipeline *pipeline;
2416 VkResult result;
2417
2418 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2419 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2420 if (pipeline == NULL)
2421 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2422
2423 pipeline->device = device;
2424 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2425
2426 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
2427 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
2428
2429 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
2430 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2431 result = radv_pipeline_scratch_init(device, pipeline);
2432 if (result != VK_SUCCESS) {
2433 radv_pipeline_destroy(device, pipeline, pAllocator);
2434 return result;
2435 }
2436
2437 *pPipeline = radv_pipeline_to_handle(pipeline);
2438
2439 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2440 radv_dump_pipeline_stats(device, pipeline);
2441 }
2442 return VK_SUCCESS;
2443 }
2444 VkResult radv_CreateComputePipelines(
2445 VkDevice _device,
2446 VkPipelineCache pipelineCache,
2447 uint32_t count,
2448 const VkComputePipelineCreateInfo* pCreateInfos,
2449 const VkAllocationCallbacks* pAllocator,
2450 VkPipeline* pPipelines)
2451 {
2452 VkResult result = VK_SUCCESS;
2453
2454 unsigned i = 0;
2455 for (; i < count; i++) {
2456 VkResult r;
2457 r = radv_compute_pipeline_create(_device, pipelineCache,
2458 &pCreateInfos[i],
2459 pAllocator, &pPipelines[i]);
2460 if (r != VK_SUCCESS) {
2461 result = r;
2462 pPipelines[i] = VK_NULL_HANDLE;
2463 }
2464 }
2465
2466 return result;
2467 }