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acc955f32b2435e22509451e9e424c585ea425f5
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36
37 #include <llvm-c/Core.h>
38 #include <llvm-c/TargetMachine.h>
39
40 #include "sid.h"
41 #include "gfx9d.h"
42 #include "r600d_common.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
49
50 static void
51 radv_pipeline_destroy(struct radv_device *device,
52 struct radv_pipeline *pipeline,
53 const VkAllocationCallbacks* allocator)
54 {
55 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
56 if (pipeline->shaders[i])
57 radv_shader_variant_destroy(device, pipeline->shaders[i]);
58
59 if (pipeline->gs_copy_shader)
60 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
61
62 vk_free2(&device->alloc, allocator, pipeline);
63 }
64
65 void radv_DestroyPipeline(
66 VkDevice _device,
67 VkPipeline _pipeline,
68 const VkAllocationCallbacks* pAllocator)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
72
73 if (!_pipeline)
74 return;
75
76 radv_pipeline_destroy(device, pipeline, pAllocator);
77 }
78
79 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
80 {
81 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
82 struct radv_shader_variant *var;
83 struct ac_shader_config *conf;
84 int i;
85 FILE *file = stderr;
86 unsigned max_simd_waves;
87 unsigned lds_per_wave = 0;
88
89 switch (device->physical_device->rad_info.family) {
90 /* These always have 8 waves: */
91 case CHIP_POLARIS10:
92 case CHIP_POLARIS11:
93 case CHIP_POLARIS12:
94 max_simd_waves = 8;
95 break;
96 default:
97 max_simd_waves = 10;
98 }
99
100 for (i = 0; i < MESA_SHADER_STAGES; i++) {
101 if (!pipeline->shaders[i])
102 continue;
103 var = pipeline->shaders[i];
104
105 conf = &var->config;
106
107 if (i == MESA_SHADER_FRAGMENT) {
108 lds_per_wave = conf->lds_size * lds_increment +
109 align(var->info.fs.num_interp * 48, lds_increment);
110 }
111
112 if (conf->num_sgprs) {
113 if (device->physical_device->rad_info.chip_class >= VI)
114 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
115 else
116 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
117 }
118
119 if (conf->num_vgprs)
120 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
121
122 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
123 * that PS can use.
124 */
125 if (lds_per_wave)
126 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
127
128 fprintf(file, "\n%s:\n",
129 radv_get_shader_name(var, i));
130 if (i == MESA_SHADER_FRAGMENT) {
131 fprintf(file, "*** SHADER CONFIG ***\n"
132 "SPI_PS_INPUT_ADDR = 0x%04x\n"
133 "SPI_PS_INPUT_ENA = 0x%04x\n",
134 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
135 }
136 fprintf(file, "*** SHADER STATS ***\n"
137 "SGPRS: %d\n"
138 "VGPRS: %d\n"
139 "Spilled SGPRs: %d\n"
140 "Spilled VGPRs: %d\n"
141 "Code Size: %d bytes\n"
142 "LDS: %d blocks\n"
143 "Scratch: %d bytes per wave\n"
144 "Max Waves: %d\n"
145 "********************\n\n\n",
146 conf->num_sgprs, conf->num_vgprs,
147 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
148 conf->lds_size, conf->scratch_bytes_per_wave,
149 max_simd_waves);
150 }
151 }
152
153 static struct radv_shader_variant *
154 radv_pipeline_compile(struct radv_pipeline *pipeline,
155 struct radv_pipeline_cache *cache,
156 struct radv_shader_module *module,
157 const char *entrypoint,
158 gl_shader_stage stage,
159 const VkSpecializationInfo *spec_info,
160 struct radv_pipeline_layout *layout,
161 const struct ac_shader_variant_key *key)
162 {
163 unsigned char sha1[20];
164 unsigned char gs_copy_sha1[20];
165 struct radv_shader_variant *variant;
166 nir_shader *nir;
167 void *code = NULL;
168 unsigned code_size = 0;
169
170 if (module->nir)
171 _mesa_sha1_compute(module->nir->info.name,
172 strlen(module->nir->info.name),
173 module->sha1);
174
175 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
176 if (stage == MESA_SHADER_GEOMETRY)
177 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
178 layout, key, 1);
179
180 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
181 cache,
182 sha1);
183
184 if (stage == MESA_SHADER_GEOMETRY) {
185 pipeline->gs_copy_shader =
186 radv_create_shader_variant_from_pipeline_cache(
187 pipeline->device,
188 cache,
189 gs_copy_sha1);
190 }
191
192 if (variant &&
193 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
194 return variant;
195
196 nir = radv_shader_compile_to_nir(pipeline->device,
197 module, entrypoint, stage,
198 spec_info);
199 if (nir == NULL)
200 return NULL;
201
202 if (!variant) {
203 variant = radv_shader_variant_create(pipeline->device, nir,
204 layout, key, &code,
205 &code_size);
206 }
207
208 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
209 void *gs_copy_code = NULL;
210 unsigned gs_copy_code_size = 0;
211 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
212 pipeline->device, nir, &gs_copy_code,
213 &gs_copy_code_size, key->has_multiview_view_index);
214
215 if (pipeline->gs_copy_shader) {
216 pipeline->gs_copy_shader =
217 radv_pipeline_cache_insert_shader(cache,
218 gs_copy_sha1,
219 pipeline->gs_copy_shader,
220 gs_copy_code,
221 gs_copy_code_size);
222 }
223
224 free(gs_copy_code);
225 }
226 if (!module->nir)
227 ralloc_free(nir);
228
229 if (variant)
230 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
231 code, code_size);
232
233 if (code)
234 free(code);
235 return variant;
236 }
237
238 static struct ac_shader_variant_key
239 radv_compute_tes_key(bool as_es, bool export_prim_id)
240 {
241 struct ac_shader_variant_key key;
242 memset(&key, 0, sizeof(key));
243 key.tes.as_es = as_es;
244 /* export prim id only happens when no geom shader */
245 if (!as_es)
246 key.tes.export_prim_id = export_prim_id;
247 return key;
248 }
249
250 static struct ac_shader_variant_key
251 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
252 {
253 struct ac_shader_variant_key key;
254 memset(&key, 0, sizeof(key));
255 key.tcs.primitive_mode = primitive_mode;
256 key.tcs.input_vertices = input_vertices;
257 return key;
258 }
259
260 static void
261 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
262 struct radv_pipeline_cache *cache,
263 struct radv_shader_module *tcs_module,
264 struct radv_shader_module *tes_module,
265 const char *tcs_entrypoint,
266 const char *tes_entrypoint,
267 const VkSpecializationInfo *tcs_spec_info,
268 const VkSpecializationInfo *tes_spec_info,
269 struct radv_pipeline_layout *layout,
270 unsigned input_vertices,
271 bool has_view_index)
272 {
273 unsigned char tcs_sha1[20], tes_sha1[20];
274 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
275 nir_shader *tes_nir, *tcs_nir;
276 void *tes_code = NULL, *tcs_code = NULL;
277 unsigned tes_code_size = 0, tcs_code_size = 0;
278 struct ac_shader_variant_key tes_key;
279 struct ac_shader_variant_key tcs_key;
280
281 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
282 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
283 tes_key.has_multiview_view_index = has_view_index;
284 if (tes_module->nir)
285 _mesa_sha1_compute(tes_module->nir->info.name,
286 strlen(tes_module->nir->info.name),
287 tes_module->sha1);
288 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
289
290 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
291 cache,
292 tes_sha1);
293
294 if (tes_variant) {
295 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
296
297 if (tcs_module->nir)
298 _mesa_sha1_compute(tcs_module->nir->info.name,
299 strlen(tcs_module->nir->info.name),
300 tcs_module->sha1);
301
302 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
303
304 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
305 cache,
306 tcs_sha1);
307 }
308
309 if (tcs_variant && tes_variant) {
310 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
311 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
312 return;
313 }
314
315 tes_nir = radv_shader_compile_to_nir(pipeline->device,
316 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
317 tes_spec_info);
318 if (tes_nir == NULL)
319 return;
320
321 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
322 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
323 tcs_spec_info);
324 if (tcs_nir == NULL)
325 return;
326
327 nir_lower_tes_patch_vertices(tes_nir,
328 tcs_nir->info.tess.tcs_vertices_out);
329
330 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
331 layout, &tes_key, &tes_code,
332 &tes_code_size);
333
334 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
335 if (tcs_module->nir)
336 _mesa_sha1_compute(tcs_module->nir->info.name,
337 strlen(tcs_module->nir->info.name),
338 tcs_module->sha1);
339
340 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
341
342 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
343 layout, &tcs_key, &tcs_code,
344 &tcs_code_size);
345
346 if (!tes_module->nir)
347 ralloc_free(tes_nir);
348
349 if (!tcs_module->nir)
350 ralloc_free(tcs_nir);
351
352 if (tes_variant)
353 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
354 tes_code, tes_code_size);
355
356 if (tcs_variant)
357 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
358 tcs_code, tcs_code_size);
359
360 if (tes_code)
361 free(tes_code);
362 if (tcs_code)
363 free(tcs_code);
364 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
365 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
366 return;
367 }
368
369 static VkResult
370 radv_pipeline_scratch_init(struct radv_device *device,
371 struct radv_pipeline *pipeline)
372 {
373 unsigned scratch_bytes_per_wave = 0;
374 unsigned max_waves = 0;
375 unsigned min_waves = 1;
376
377 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
378 if (pipeline->shaders[i]) {
379 unsigned max_stage_waves = device->scratch_waves;
380
381 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
382 pipeline->shaders[i]->config.scratch_bytes_per_wave);
383
384 max_stage_waves = MIN2(max_stage_waves,
385 4 * device->physical_device->rad_info.num_good_compute_units *
386 (256 / pipeline->shaders[i]->config.num_vgprs));
387 max_waves = MAX2(max_waves, max_stage_waves);
388 }
389 }
390
391 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
392 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
393 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
394 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
395 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
396 }
397
398 if (scratch_bytes_per_wave)
399 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
400
401 if (scratch_bytes_per_wave && max_waves < min_waves) {
402 /* Not really true at this moment, but will be true on first
403 * execution. Avoid having hanging shaders. */
404 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
405 }
406 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
407 pipeline->max_waves = max_waves;
408 return VK_SUCCESS;
409 }
410
411 static uint32_t si_translate_blend_function(VkBlendOp op)
412 {
413 switch (op) {
414 case VK_BLEND_OP_ADD:
415 return V_028780_COMB_DST_PLUS_SRC;
416 case VK_BLEND_OP_SUBTRACT:
417 return V_028780_COMB_SRC_MINUS_DST;
418 case VK_BLEND_OP_REVERSE_SUBTRACT:
419 return V_028780_COMB_DST_MINUS_SRC;
420 case VK_BLEND_OP_MIN:
421 return V_028780_COMB_MIN_DST_SRC;
422 case VK_BLEND_OP_MAX:
423 return V_028780_COMB_MAX_DST_SRC;
424 default:
425 return 0;
426 }
427 }
428
429 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
430 {
431 switch (factor) {
432 case VK_BLEND_FACTOR_ZERO:
433 return V_028780_BLEND_ZERO;
434 case VK_BLEND_FACTOR_ONE:
435 return V_028780_BLEND_ONE;
436 case VK_BLEND_FACTOR_SRC_COLOR:
437 return V_028780_BLEND_SRC_COLOR;
438 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
439 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
440 case VK_BLEND_FACTOR_DST_COLOR:
441 return V_028780_BLEND_DST_COLOR;
442 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
443 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
444 case VK_BLEND_FACTOR_SRC_ALPHA:
445 return V_028780_BLEND_SRC_ALPHA;
446 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
447 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
448 case VK_BLEND_FACTOR_DST_ALPHA:
449 return V_028780_BLEND_DST_ALPHA;
450 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
451 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
452 case VK_BLEND_FACTOR_CONSTANT_COLOR:
453 return V_028780_BLEND_CONSTANT_COLOR;
454 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
455 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
456 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
457 return V_028780_BLEND_CONSTANT_ALPHA;
458 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
459 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
460 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
461 return V_028780_BLEND_SRC_ALPHA_SATURATE;
462 case VK_BLEND_FACTOR_SRC1_COLOR:
463 return V_028780_BLEND_SRC1_COLOR;
464 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
465 return V_028780_BLEND_INV_SRC1_COLOR;
466 case VK_BLEND_FACTOR_SRC1_ALPHA:
467 return V_028780_BLEND_SRC1_ALPHA;
468 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
469 return V_028780_BLEND_INV_SRC1_ALPHA;
470 default:
471 return 0;
472 }
473 }
474
475 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
476 {
477 switch (op) {
478 case VK_BLEND_OP_ADD:
479 return V_028760_OPT_COMB_ADD;
480 case VK_BLEND_OP_SUBTRACT:
481 return V_028760_OPT_COMB_SUBTRACT;
482 case VK_BLEND_OP_REVERSE_SUBTRACT:
483 return V_028760_OPT_COMB_REVSUBTRACT;
484 case VK_BLEND_OP_MIN:
485 return V_028760_OPT_COMB_MIN;
486 case VK_BLEND_OP_MAX:
487 return V_028760_OPT_COMB_MAX;
488 default:
489 return V_028760_OPT_COMB_BLEND_DISABLED;
490 }
491 }
492
493 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
494 {
495 switch (factor) {
496 case VK_BLEND_FACTOR_ZERO:
497 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
498 case VK_BLEND_FACTOR_ONE:
499 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
500 case VK_BLEND_FACTOR_SRC_COLOR:
501 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
502 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
503 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
504 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
505 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
506 case VK_BLEND_FACTOR_SRC_ALPHA:
507 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
508 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
509 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
510 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
511 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
512 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
513 default:
514 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
515 }
516 }
517
518 /**
519 * Get rid of DST in the blend factors by commuting the operands:
520 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
521 */
522 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
523 unsigned *dst_factor, unsigned expected_dst,
524 unsigned replacement_src)
525 {
526 if (*src_factor == expected_dst &&
527 *dst_factor == VK_BLEND_FACTOR_ZERO) {
528 *src_factor = VK_BLEND_FACTOR_ZERO;
529 *dst_factor = replacement_src;
530
531 /* Commuting the operands requires reversing subtractions. */
532 if (*func == VK_BLEND_OP_SUBTRACT)
533 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
534 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
535 *func = VK_BLEND_OP_SUBTRACT;
536 }
537 }
538
539 static bool si_blend_factor_uses_dst(unsigned factor)
540 {
541 return factor == VK_BLEND_FACTOR_DST_COLOR ||
542 factor == VK_BLEND_FACTOR_DST_ALPHA ||
543 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
544 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
545 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
546 }
547
548 static bool is_dual_src(VkBlendFactor factor)
549 {
550 switch (factor) {
551 case VK_BLEND_FACTOR_SRC1_COLOR:
552 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
553 case VK_BLEND_FACTOR_SRC1_ALPHA:
554 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
555 return true;
556 default:
557 return false;
558 }
559 }
560
561 static unsigned si_choose_spi_color_format(VkFormat vk_format,
562 bool blend_enable,
563 bool blend_need_alpha)
564 {
565 const struct vk_format_description *desc = vk_format_description(vk_format);
566 unsigned format, ntype, swap;
567
568 /* Alpha is needed for alpha-to-coverage.
569 * Blending may be with or without alpha.
570 */
571 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
572 unsigned alpha = 0; /* exports alpha, but may not support blending */
573 unsigned blend = 0; /* supports blending, but may not export alpha */
574 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
575
576 format = radv_translate_colorformat(vk_format);
577 ntype = radv_translate_color_numformat(vk_format, desc,
578 vk_format_get_first_non_void_channel(vk_format));
579 swap = radv_translate_colorswap(vk_format, false);
580
581 /* Choose the SPI color formats. These are required values for Stoney/RB+.
582 * Other chips have multiple choices, though they are not necessarily better.
583 */
584 switch (format) {
585 case V_028C70_COLOR_5_6_5:
586 case V_028C70_COLOR_1_5_5_5:
587 case V_028C70_COLOR_5_5_5_1:
588 case V_028C70_COLOR_4_4_4_4:
589 case V_028C70_COLOR_10_11_11:
590 case V_028C70_COLOR_11_11_10:
591 case V_028C70_COLOR_8:
592 case V_028C70_COLOR_8_8:
593 case V_028C70_COLOR_8_8_8_8:
594 case V_028C70_COLOR_10_10_10_2:
595 case V_028C70_COLOR_2_10_10_10:
596 if (ntype == V_028C70_NUMBER_UINT)
597 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
598 else if (ntype == V_028C70_NUMBER_SINT)
599 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
600 else
601 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
602 break;
603
604 case V_028C70_COLOR_16:
605 case V_028C70_COLOR_16_16:
606 case V_028C70_COLOR_16_16_16_16:
607 if (ntype == V_028C70_NUMBER_UNORM ||
608 ntype == V_028C70_NUMBER_SNORM) {
609 /* UNORM16 and SNORM16 don't support blending */
610 if (ntype == V_028C70_NUMBER_UNORM)
611 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
612 else
613 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
614
615 /* Use 32 bits per channel for blending. */
616 if (format == V_028C70_COLOR_16) {
617 if (swap == V_028C70_SWAP_STD) { /* R */
618 blend = V_028714_SPI_SHADER_32_R;
619 blend_alpha = V_028714_SPI_SHADER_32_AR;
620 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
621 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
622 else
623 assert(0);
624 } else if (format == V_028C70_COLOR_16_16) {
625 if (swap == V_028C70_SWAP_STD) { /* RG */
626 blend = V_028714_SPI_SHADER_32_GR;
627 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
628 } else if (swap == V_028C70_SWAP_ALT) /* RA */
629 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
630 else
631 assert(0);
632 } else /* 16_16_16_16 */
633 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
634 } else if (ntype == V_028C70_NUMBER_UINT)
635 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
636 else if (ntype == V_028C70_NUMBER_SINT)
637 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
638 else if (ntype == V_028C70_NUMBER_FLOAT)
639 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
640 else
641 assert(0);
642 break;
643
644 case V_028C70_COLOR_32:
645 if (swap == V_028C70_SWAP_STD) { /* R */
646 blend = normal = V_028714_SPI_SHADER_32_R;
647 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
648 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
649 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
650 else
651 assert(0);
652 break;
653
654 case V_028C70_COLOR_32_32:
655 if (swap == V_028C70_SWAP_STD) { /* RG */
656 blend = normal = V_028714_SPI_SHADER_32_GR;
657 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
658 } else if (swap == V_028C70_SWAP_ALT) /* RA */
659 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
660 else
661 assert(0);
662 break;
663
664 case V_028C70_COLOR_32_32_32_32:
665 case V_028C70_COLOR_8_24:
666 case V_028C70_COLOR_24_8:
667 case V_028C70_COLOR_X24_8_32_FLOAT:
668 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
669 break;
670
671 default:
672 unreachable("unhandled blend format");
673 }
674
675 if (blend_enable && blend_need_alpha)
676 return blend_alpha;
677 else if(blend_need_alpha)
678 return alpha;
679 else if(blend_enable)
680 return blend;
681 else
682 return normal;
683 }
684
685 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
686 {
687 unsigned i, cb_shader_mask = 0;
688
689 for (i = 0; i < 8; i++) {
690 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
691 case V_028714_SPI_SHADER_ZERO:
692 break;
693 case V_028714_SPI_SHADER_32_R:
694 cb_shader_mask |= 0x1 << (i * 4);
695 break;
696 case V_028714_SPI_SHADER_32_GR:
697 cb_shader_mask |= 0x3 << (i * 4);
698 break;
699 case V_028714_SPI_SHADER_32_AR:
700 cb_shader_mask |= 0x9 << (i * 4);
701 break;
702 case V_028714_SPI_SHADER_FP16_ABGR:
703 case V_028714_SPI_SHADER_UNORM16_ABGR:
704 case V_028714_SPI_SHADER_SNORM16_ABGR:
705 case V_028714_SPI_SHADER_UINT16_ABGR:
706 case V_028714_SPI_SHADER_SINT16_ABGR:
707 case V_028714_SPI_SHADER_32_ABGR:
708 cb_shader_mask |= 0xf << (i * 4);
709 break;
710 default:
711 assert(0);
712 }
713 }
714 return cb_shader_mask;
715 }
716
717 static void
718 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
719 const VkGraphicsPipelineCreateInfo *pCreateInfo,
720 uint32_t blend_enable,
721 uint32_t blend_need_alpha,
722 bool single_cb_enable,
723 bool blend_mrt0_is_dual_src)
724 {
725 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
726 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
727 struct radv_blend_state *blend = &pipeline->graphics.blend;
728 unsigned col_format = 0;
729
730 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
731 unsigned cf;
732
733 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
734 cf = V_028714_SPI_SHADER_ZERO;
735 } else {
736 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
737
738 cf = si_choose_spi_color_format(attachment->format,
739 blend_enable & (1 << i),
740 blend_need_alpha & (1 << i));
741 }
742
743 col_format |= cf << (4 * i);
744 }
745
746 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
747
748 if (blend_mrt0_is_dual_src)
749 col_format |= (col_format & 0xf) << 4;
750 blend->spi_shader_col_format = col_format;
751 }
752
753 static bool
754 format_is_int8(VkFormat format)
755 {
756 const struct vk_format_description *desc = vk_format_description(format);
757 int channel = vk_format_get_first_non_void_channel(format);
758
759 return channel >= 0 && desc->channel[channel].pure_integer &&
760 desc->channel[channel].size == 8;
761 }
762
763 static bool
764 format_is_int10(VkFormat format)
765 {
766 const struct vk_format_description *desc = vk_format_description(format);
767
768 if (desc->nr_channels != 4)
769 return false;
770 for (unsigned i = 0; i < 4; i++) {
771 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
772 return true;
773 }
774 return false;
775 }
776
777 unsigned radv_format_meta_fs_key(VkFormat format)
778 {
779 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
780 bool is_int8 = format_is_int8(format);
781 bool is_int10 = format_is_int10(format);
782
783 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
784 }
785
786 static void
787 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
788 unsigned *is_int8, unsigned *is_int10)
789 {
790 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
791 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
792 *is_int8 = 0;
793 *is_int10 = 0;
794
795 for (unsigned i = 0; i < subpass->color_count; ++i) {
796 struct radv_render_pass_attachment *attachment;
797
798 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
799 continue;
800
801 attachment = pass->attachments + subpass->color_attachments[i].attachment;
802
803 if (format_is_int8(attachment->format))
804 *is_int8 |= 1 << i;
805 if (format_is_int10(attachment->format))
806 *is_int10 |= 1 << i;
807 }
808 }
809
810 static void
811 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
812 const VkGraphicsPipelineCreateInfo *pCreateInfo,
813 const struct radv_graphics_pipeline_create_info *extra)
814 {
815 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
816 struct radv_blend_state *blend = &pipeline->graphics.blend;
817 unsigned mode = V_028808_CB_NORMAL;
818 uint32_t blend_enable = 0, blend_need_alpha = 0;
819 bool blend_mrt0_is_dual_src = false;
820 int i;
821 bool single_cb_enable = false;
822
823 if (!vkblend)
824 return;
825
826 if (extra && extra->custom_blend_mode) {
827 single_cb_enable = true;
828 mode = extra->custom_blend_mode;
829 }
830 blend->cb_color_control = 0;
831 if (vkblend->logicOpEnable)
832 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
833 else
834 blend->cb_color_control |= S_028808_ROP3(0xcc);
835
836 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
837 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
838 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
839 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
840
841 blend->cb_target_mask = 0;
842 for (i = 0; i < vkblend->attachmentCount; i++) {
843 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
844 unsigned blend_cntl = 0;
845 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
846 VkBlendOp eqRGB = att->colorBlendOp;
847 VkBlendFactor srcRGB = att->srcColorBlendFactor;
848 VkBlendFactor dstRGB = att->dstColorBlendFactor;
849 VkBlendOp eqA = att->alphaBlendOp;
850 VkBlendFactor srcA = att->srcAlphaBlendFactor;
851 VkBlendFactor dstA = att->dstAlphaBlendFactor;
852
853 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
854
855 if (!att->colorWriteMask)
856 continue;
857
858 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
859 if (!att->blendEnable) {
860 blend->cb_blend_control[i] = blend_cntl;
861 continue;
862 }
863
864 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
865 if (i == 0)
866 blend_mrt0_is_dual_src = true;
867
868 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
869 srcRGB = VK_BLEND_FACTOR_ONE;
870 dstRGB = VK_BLEND_FACTOR_ONE;
871 }
872 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
873 srcA = VK_BLEND_FACTOR_ONE;
874 dstA = VK_BLEND_FACTOR_ONE;
875 }
876
877 /* Blending optimizations for RB+.
878 * These transformations don't change the behavior.
879 *
880 * First, get rid of DST in the blend factors:
881 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
882 */
883 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
884 VK_BLEND_FACTOR_DST_COLOR,
885 VK_BLEND_FACTOR_SRC_COLOR);
886
887 si_blend_remove_dst(&eqA, &srcA, &dstA,
888 VK_BLEND_FACTOR_DST_COLOR,
889 VK_BLEND_FACTOR_SRC_COLOR);
890
891 si_blend_remove_dst(&eqA, &srcA, &dstA,
892 VK_BLEND_FACTOR_DST_ALPHA,
893 VK_BLEND_FACTOR_SRC_ALPHA);
894
895 /* Look up the ideal settings from tables. */
896 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
897 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
898 srcA_opt = si_translate_blend_opt_factor(srcA, true);
899 dstA_opt = si_translate_blend_opt_factor(dstA, true);
900
901 /* Handle interdependencies. */
902 if (si_blend_factor_uses_dst(srcRGB))
903 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
904 if (si_blend_factor_uses_dst(srcA))
905 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
906
907 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
908 (dstRGB == VK_BLEND_FACTOR_ZERO ||
909 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
910 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
911 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
912
913 /* Set the final value. */
914 blend->sx_mrt_blend_opt[i] =
915 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
916 S_028760_COLOR_DST_OPT(dstRGB_opt) |
917 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
918 S_028760_ALPHA_SRC_OPT(srcA_opt) |
919 S_028760_ALPHA_DST_OPT(dstA_opt) |
920 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
921 blend_cntl |= S_028780_ENABLE(1);
922
923 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
924 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
925 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
926 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
927 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
928 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
929 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
930 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
931 }
932 blend->cb_blend_control[i] = blend_cntl;
933
934 blend_enable |= 1 << i;
935
936 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
937 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
938 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
939 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
940 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
941 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
942 blend_need_alpha |= 1 << i;
943 }
944 for (i = vkblend->attachmentCount; i < 8; i++) {
945 blend->cb_blend_control[i] = 0;
946 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
947 }
948
949 /* disable RB+ for now */
950 if (pipeline->device->physical_device->has_rbplus)
951 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
952
953 if (blend->cb_target_mask)
954 blend->cb_color_control |= S_028808_MODE(mode);
955 else
956 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
957
958 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
959 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
960 }
961
962 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
963 {
964 switch (op) {
965 case VK_STENCIL_OP_KEEP:
966 return V_02842C_STENCIL_KEEP;
967 case VK_STENCIL_OP_ZERO:
968 return V_02842C_STENCIL_ZERO;
969 case VK_STENCIL_OP_REPLACE:
970 return V_02842C_STENCIL_REPLACE_TEST;
971 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
972 return V_02842C_STENCIL_ADD_CLAMP;
973 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
974 return V_02842C_STENCIL_SUB_CLAMP;
975 case VK_STENCIL_OP_INVERT:
976 return V_02842C_STENCIL_INVERT;
977 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
978 return V_02842C_STENCIL_ADD_WRAP;
979 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
980 return V_02842C_STENCIL_SUB_WRAP;
981 default:
982 return 0;
983 }
984 }
985 static void
986 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
987 const VkGraphicsPipelineCreateInfo *pCreateInfo,
988 const struct radv_graphics_pipeline_create_info *extra)
989 {
990 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
991 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
992
993 memset(ds, 0, sizeof(*ds));
994 if (!vkds)
995 return;
996
997 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
998 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
999 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
1000 return;
1001
1002 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
1003 bool has_depth_attachment = vk_format_is_depth(attachment->format);
1004 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
1005
1006 if (has_depth_attachment) {
1007 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1008 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1009 S_028800_ZFUNC(vkds->depthCompareOp) |
1010 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1011 }
1012
1013 if (has_stencil_attachment && vkds->stencilTestEnable) {
1014 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1015 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1016 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1017 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1018 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1019
1020 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1021 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1022 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1023 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1024 }
1025
1026 if (extra) {
1027
1028 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1029 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1030
1031 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1032 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1033 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1034 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1035 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1036 }
1037 }
1038
1039 static uint32_t si_translate_fill(VkPolygonMode func)
1040 {
1041 switch(func) {
1042 case VK_POLYGON_MODE_FILL:
1043 return V_028814_X_DRAW_TRIANGLES;
1044 case VK_POLYGON_MODE_LINE:
1045 return V_028814_X_DRAW_LINES;
1046 case VK_POLYGON_MODE_POINT:
1047 return V_028814_X_DRAW_POINTS;
1048 default:
1049 assert(0);
1050 return V_028814_X_DRAW_POINTS;
1051 }
1052 }
1053 static void
1054 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1055 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1056 {
1057 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1058 struct radv_raster_state *raster = &pipeline->graphics.raster;
1059
1060 memset(raster, 0, sizeof(*raster));
1061
1062 raster->spi_interp_control =
1063 S_0286D4_FLAT_SHADE_ENA(1) |
1064 S_0286D4_PNT_SPRITE_ENA(1) |
1065 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1066 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1067 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1068 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1069 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1070
1071
1072 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1073 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1074 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1075 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1076 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1077 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1078
1079 raster->pa_su_vtx_cntl =
1080 S_028BE4_PIX_CENTER(1) | // TODO verify
1081 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1082 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1083
1084 raster->pa_su_sc_mode_cntl =
1085 S_028814_FACE(vkraster->frontFace) |
1086 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1087 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1088 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1089 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1090 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1091 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1092 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1093 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1094
1095 }
1096
1097 static void
1098 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1099 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1100 {
1101 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1102 struct radv_blend_state *blend = &pipeline->graphics.blend;
1103 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1104 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1105 int ps_iter_samples = 1;
1106 uint32_t mask = 0xffff;
1107
1108 if (vkms)
1109 ms->num_samples = vkms->rasterizationSamples;
1110 else
1111 ms->num_samples = 1;
1112
1113 if (vkms && vkms->sampleShadingEnable) {
1114 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
1115 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1116 ps_iter_samples = ms->num_samples;
1117 }
1118
1119 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1120 ms->pa_sc_aa_config = 0;
1121 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1122 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1123 ms->pa_sc_mode_cntl_1 =
1124 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1125 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1126 /* always 1: */
1127 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1128 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1129 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1130 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1131 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1132 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1133 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1134
1135 if (ms->num_samples > 1) {
1136 unsigned log_samples = util_logbase2(ms->num_samples);
1137 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1138 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1139 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1140 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1141 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1142 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1143 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1144 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1145 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1146 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1147 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1148 }
1149
1150 if (vkms) {
1151 if (vkms->alphaToCoverageEnable)
1152 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1153
1154 if (vkms->pSampleMask)
1155 mask = vkms->pSampleMask[0] & 0xffff;
1156 }
1157
1158 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1159 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1160 }
1161
1162 static bool
1163 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1164 {
1165 switch (topology) {
1166 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1167 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1168 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1169 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1170 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1171 return false;
1172 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1173 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1174 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1175 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1176 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1177 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1178 return true;
1179 default:
1180 unreachable("unhandled primitive type");
1181 }
1182 }
1183
1184 static uint32_t
1185 si_translate_prim(enum VkPrimitiveTopology topology)
1186 {
1187 switch (topology) {
1188 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1189 return V_008958_DI_PT_POINTLIST;
1190 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1191 return V_008958_DI_PT_LINELIST;
1192 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1193 return V_008958_DI_PT_LINESTRIP;
1194 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1195 return V_008958_DI_PT_TRILIST;
1196 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1197 return V_008958_DI_PT_TRISTRIP;
1198 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1199 return V_008958_DI_PT_TRIFAN;
1200 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1201 return V_008958_DI_PT_LINELIST_ADJ;
1202 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1203 return V_008958_DI_PT_LINESTRIP_ADJ;
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1205 return V_008958_DI_PT_TRILIST_ADJ;
1206 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1207 return V_008958_DI_PT_TRISTRIP_ADJ;
1208 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1209 return V_008958_DI_PT_PATCH;
1210 default:
1211 assert(0);
1212 return 0;
1213 }
1214 }
1215
1216 static uint32_t
1217 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1218 {
1219 switch (gl_prim) {
1220 case 0: /* GL_POINTS */
1221 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1222 case 1: /* GL_LINES */
1223 case 3: /* GL_LINE_STRIP */
1224 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1225 case 0x8E7A: /* GL_ISOLINES */
1226 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1227
1228 case 4: /* GL_TRIANGLES */
1229 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1230 case 5: /* GL_TRIANGLE_STRIP */
1231 case 7: /* GL_QUADS */
1232 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1233 default:
1234 assert(0);
1235 return 0;
1236 }
1237 }
1238
1239 static uint32_t
1240 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1241 {
1242 switch (topology) {
1243 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1244 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1245 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1246 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1247 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1248 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1249 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1250 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1251 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1252 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1253 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1254 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1255 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1256 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1257 default:
1258 assert(0);
1259 return 0;
1260 }
1261 }
1262
1263 static unsigned si_map_swizzle(unsigned swizzle)
1264 {
1265 switch (swizzle) {
1266 case VK_SWIZZLE_Y:
1267 return V_008F0C_SQ_SEL_Y;
1268 case VK_SWIZZLE_Z:
1269 return V_008F0C_SQ_SEL_Z;
1270 case VK_SWIZZLE_W:
1271 return V_008F0C_SQ_SEL_W;
1272 case VK_SWIZZLE_0:
1273 return V_008F0C_SQ_SEL_0;
1274 case VK_SWIZZLE_1:
1275 return V_008F0C_SQ_SEL_1;
1276 default: /* VK_SWIZZLE_X */
1277 return V_008F0C_SQ_SEL_X;
1278 }
1279 }
1280
1281 static void
1282 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1283 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1284 {
1285 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1286 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1287 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1288
1289 pipeline->dynamic_state = default_dynamic_state;
1290
1291 if (pCreateInfo->pDynamicState) {
1292 /* Remove all of the states that are marked as dynamic */
1293 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1294 for (uint32_t s = 0; s < count; s++)
1295 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1296 }
1297
1298 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1299
1300 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1301 *
1302 * pViewportState is [...] NULL if the pipeline
1303 * has rasterization disabled.
1304 */
1305 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1306 assert(pCreateInfo->pViewportState);
1307
1308 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1309 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1310 typed_memcpy(dynamic->viewport.viewports,
1311 pCreateInfo->pViewportState->pViewports,
1312 pCreateInfo->pViewportState->viewportCount);
1313 }
1314
1315 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1316 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1317 typed_memcpy(dynamic->scissor.scissors,
1318 pCreateInfo->pViewportState->pScissors,
1319 pCreateInfo->pViewportState->scissorCount);
1320 }
1321 }
1322
1323 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1324 assert(pCreateInfo->pRasterizationState);
1325 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1326 }
1327
1328 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1329 assert(pCreateInfo->pRasterizationState);
1330 dynamic->depth_bias.bias =
1331 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1332 dynamic->depth_bias.clamp =
1333 pCreateInfo->pRasterizationState->depthBiasClamp;
1334 dynamic->depth_bias.slope =
1335 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1336 }
1337
1338 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1339 *
1340 * pColorBlendState is [...] NULL if the pipeline has rasterization
1341 * disabled or if the subpass of the render pass the pipeline is
1342 * created against does not use any color attachments.
1343 */
1344 bool uses_color_att = false;
1345 for (unsigned i = 0; i < subpass->color_count; ++i) {
1346 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1347 uses_color_att = true;
1348 break;
1349 }
1350 }
1351
1352 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1353 assert(pCreateInfo->pColorBlendState);
1354 typed_memcpy(dynamic->blend_constants,
1355 pCreateInfo->pColorBlendState->blendConstants, 4);
1356 }
1357
1358 /* If there is no depthstencil attachment, then don't read
1359 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1360 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1361 * no need to override the depthstencil defaults in
1362 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1363 *
1364 * Section 9.2 of the Vulkan 1.0.15 spec says:
1365 *
1366 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1367 * disabled or if the subpass of the render pass the pipeline is created
1368 * against does not use a depth/stencil attachment.
1369 */
1370 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1371 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1372 assert(pCreateInfo->pDepthStencilState);
1373
1374 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1375 dynamic->depth_bounds.min =
1376 pCreateInfo->pDepthStencilState->minDepthBounds;
1377 dynamic->depth_bounds.max =
1378 pCreateInfo->pDepthStencilState->maxDepthBounds;
1379 }
1380
1381 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1382 dynamic->stencil_compare_mask.front =
1383 pCreateInfo->pDepthStencilState->front.compareMask;
1384 dynamic->stencil_compare_mask.back =
1385 pCreateInfo->pDepthStencilState->back.compareMask;
1386 }
1387
1388 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1389 dynamic->stencil_write_mask.front =
1390 pCreateInfo->pDepthStencilState->front.writeMask;
1391 dynamic->stencil_write_mask.back =
1392 pCreateInfo->pDepthStencilState->back.writeMask;
1393 }
1394
1395 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1396 dynamic->stencil_reference.front =
1397 pCreateInfo->pDepthStencilState->front.reference;
1398 dynamic->stencil_reference.back =
1399 pCreateInfo->pDepthStencilState->back.reference;
1400 }
1401 }
1402
1403 pipeline->dynamic_state_mask = states;
1404 }
1405
1406 static struct ac_shader_variant_key
1407 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1408 {
1409 struct ac_shader_variant_key key;
1410 const VkPipelineVertexInputStateCreateInfo *input_state =
1411 pCreateInfo->pVertexInputState;
1412
1413 memset(&key, 0, sizeof(key));
1414 key.vs.instance_rate_inputs = 0;
1415 key.vs.as_es = as_es;
1416 key.vs.as_ls = as_ls;
1417 key.vs.export_prim_id = export_prim_id;
1418
1419 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1420 unsigned binding;
1421 binding = input_state->pVertexAttributeDescriptions[i].binding;
1422 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1423 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1424 }
1425 return key;
1426 }
1427
1428 static void
1429 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1430 {
1431 struct radv_device *device = pipeline->device;
1432 unsigned num_se = device->physical_device->rad_info.max_se;
1433 unsigned wave_size = 64;
1434 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1435 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1436 unsigned alignment = 256 * num_se;
1437 /* The maximum size is 63.999 MB per SE. */
1438 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1439 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1440 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1441 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1442 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1443
1444 /* Calculate the minimum size. */
1445 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1446 wave_size, alignment);
1447 /* These are recommended sizes, not minimum sizes. */
1448 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1449 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1450 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1451 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1452
1453 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1454 esgs_ring_size = align(esgs_ring_size, alignment);
1455 gsvs_ring_size = align(gsvs_ring_size, alignment);
1456
1457 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1458 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1459 }
1460
1461 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1462 unsigned *lds_size)
1463 {
1464 /* SPI barrier management bug:
1465 * Make sure we have at least 4k of LDS in use to avoid the bug.
1466 * It applies to workgroup sizes of more than one wavefront.
1467 */
1468 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1469 device->physical_device->rad_info.family == CHIP_KABINI ||
1470 device->physical_device->rad_info.family == CHIP_MULLINS)
1471 *lds_size = MAX2(*lds_size, 8);
1472 }
1473
1474 static void
1475 calculate_tess_state(struct radv_pipeline *pipeline,
1476 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1477 {
1478 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1479 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1480 unsigned num_tcs_patch_outputs;
1481 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1482 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1483 unsigned lds_size, hardware_lds_size;
1484 unsigned perpatch_output_offset;
1485 unsigned num_patches;
1486 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1487
1488 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1489 * are laid out in LDS. */
1490 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1491
1492 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1493 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1494 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1495
1496 /* Ensure that we only need one wave per SIMD so we don't need to check
1497 * resource usage. Also ensures that the number of tcs in and out
1498 * vertices per threadgroup are at most 256.
1499 */
1500 input_vertex_size = num_tcs_inputs * 16;
1501 output_vertex_size = num_tcs_outputs * 16;
1502
1503 input_patch_size = num_tcs_input_cp * input_vertex_size;
1504
1505 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1506 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1507 /* Ensure that we only need one wave per SIMD so we don't need to check
1508 * resource usage. Also ensures that the number of tcs in and out
1509 * vertices per threadgroup are at most 256.
1510 */
1511 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1512
1513 /* Make sure that the data fits in LDS. This assumes the shaders only
1514 * use LDS for the inputs and outputs.
1515 */
1516 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1517 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1518
1519 /* Make sure the output data fits in the offchip buffer */
1520 num_patches = MIN2(num_patches,
1521 (pipeline->device->tess_offchip_block_dw_size * 4) /
1522 output_patch_size);
1523
1524 /* Not necessary for correctness, but improves performance. The
1525 * specific value is taken from the proprietary driver.
1526 */
1527 num_patches = MIN2(num_patches, 40);
1528
1529 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1530 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1531 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1532 num_patches = MIN2(num_patches, one_wave);
1533 }
1534
1535 output_patch0_offset = input_patch_size * num_patches;
1536 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1537
1538 lds_size = output_patch0_offset + output_patch_size * num_patches;
1539
1540 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1541 assert(lds_size <= 65536);
1542 lds_size = align(lds_size, 512) / 512;
1543 } else {
1544 assert(lds_size <= 32768);
1545 lds_size = align(lds_size, 256) / 256;
1546 }
1547 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1548
1549 tess->lds_size = lds_size;
1550
1551 tess->tcs_in_layout = (input_patch_size / 4) |
1552 ((input_vertex_size / 4) << 13);
1553 tess->tcs_out_layout = (output_patch_size / 4) |
1554 ((output_vertex_size / 4) << 13);
1555 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1556 ((perpatch_output_offset / 16) << 16);
1557 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1558 (num_tcs_output_cp << 9) | num_patches;
1559
1560 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1561 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1562 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1563 tess->num_patches = num_patches;
1564 tess->num_tcs_input_cp = num_tcs_input_cp;
1565
1566 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1567 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1568
1569 switch (tes->info.tes.primitive_mode) {
1570 case GL_TRIANGLES:
1571 type = V_028B6C_TESS_TRIANGLE;
1572 break;
1573 case GL_QUADS:
1574 type = V_028B6C_TESS_QUAD;
1575 break;
1576 case GL_ISOLINES:
1577 type = V_028B6C_TESS_ISOLINE;
1578 break;
1579 }
1580
1581 switch (tes->info.tes.spacing) {
1582 case TESS_SPACING_EQUAL:
1583 partitioning = V_028B6C_PART_INTEGER;
1584 break;
1585 case TESS_SPACING_FRACTIONAL_ODD:
1586 partitioning = V_028B6C_PART_FRAC_ODD;
1587 break;
1588 case TESS_SPACING_FRACTIONAL_EVEN:
1589 partitioning = V_028B6C_PART_FRAC_EVEN;
1590 break;
1591 default:
1592 break;
1593 }
1594
1595 if (tes->info.tes.point_mode)
1596 topology = V_028B6C_OUTPUT_POINT;
1597 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1598 topology = V_028B6C_OUTPUT_LINE;
1599 else if (tes->info.tes.ccw)
1600 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1601 else
1602 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1603
1604 if (pipeline->device->has_distributed_tess) {
1605 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1606 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1607 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1608 else
1609 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1610 } else
1611 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1612
1613 tess->tf_param = S_028B6C_TYPE(type) |
1614 S_028B6C_PARTITIONING(partitioning) |
1615 S_028B6C_TOPOLOGY(topology) |
1616 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1617 }
1618
1619 static const struct radv_prim_vertex_count prim_size_table[] = {
1620 [V_008958_DI_PT_NONE] = {0, 0},
1621 [V_008958_DI_PT_POINTLIST] = {1, 1},
1622 [V_008958_DI_PT_LINELIST] = {2, 2},
1623 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1624 [V_008958_DI_PT_TRILIST] = {3, 3},
1625 [V_008958_DI_PT_TRIFAN] = {3, 1},
1626 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1627 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1628 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1629 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1630 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1631 [V_008958_DI_PT_RECTLIST] = {3, 3},
1632 [V_008958_DI_PT_LINELOOP] = {2, 1},
1633 [V_008958_DI_PT_POLYGON] = {3, 1},
1634 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1635 };
1636
1637 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1638 {
1639 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1640 unsigned cut_mode;
1641
1642 if (gs_max_vert_out <= 128) {
1643 cut_mode = V_028A40_GS_CUT_128;
1644 } else if (gs_max_vert_out <= 256) {
1645 cut_mode = V_028A40_GS_CUT_256;
1646 } else if (gs_max_vert_out <= 512) {
1647 cut_mode = V_028A40_GS_CUT_512;
1648 } else {
1649 assert(gs_max_vert_out <= 1024);
1650 cut_mode = V_028A40_GS_CUT_1024;
1651 }
1652
1653 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1654 S_028A40_CUT_MODE(cut_mode)|
1655 S_028A40_ES_WRITE_OPTIMIZE(1) |
1656 S_028A40_GS_WRITE_OPTIMIZE(1);
1657 }
1658
1659 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1660 {
1661 struct radv_shader_variant *vs;
1662 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1663
1664 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1665
1666 pipeline->graphics.vgt_primitiveid_en = false;
1667 pipeline->graphics.vgt_gs_mode = 0;
1668
1669 if (radv_pipeline_has_gs(pipeline)) {
1670 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
1671 } else if (outinfo->export_prim_id) {
1672 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1673 pipeline->graphics.vgt_primitiveid_en = true;
1674 }
1675 }
1676
1677 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1678 {
1679 struct radv_shader_variant *vs;
1680 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1681
1682 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1683
1684 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1685 clip_dist_mask = outinfo->clip_dist_mask;
1686 cull_dist_mask = outinfo->cull_dist_mask;
1687 total_mask = clip_dist_mask | cull_dist_mask;
1688
1689 bool misc_vec_ena = outinfo->writes_pointsize ||
1690 outinfo->writes_layer ||
1691 outinfo->writes_viewport_index;
1692 pipeline->graphics.pa_cl_vs_out_cntl =
1693 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1694 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1695 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1696 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1697 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1698 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1699 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1700 cull_dist_mask << 8 |
1701 clip_dist_mask;
1702
1703 }
1704
1705 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1706 {
1707 uint32_t ps_input_cntl;
1708 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1709 ps_input_cntl = S_028644_OFFSET(offset);
1710 if (flat_shade)
1711 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1712 } else {
1713 /* The input is a DEFAULT_VAL constant. */
1714 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1715 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1716 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1717 ps_input_cntl = S_028644_OFFSET(0x20) |
1718 S_028644_DEFAULT_VAL(offset);
1719 }
1720 return ps_input_cntl;
1721 }
1722
1723 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1724 {
1725 struct radv_shader_variant *ps, *vs;
1726 struct ac_vs_output_info *outinfo;
1727
1728 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1729 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1730
1731 outinfo = &vs->info.vs.outinfo;
1732
1733 unsigned ps_offset = 0;
1734
1735 if (ps->info.fs.prim_id_input) {
1736 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1737 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1738 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1739 ++ps_offset;
1740 }
1741 }
1742
1743 if (ps->info.fs.layer_input) {
1744 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1745 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
1746 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1747 else
1748 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
1749 ++ps_offset;
1750 }
1751
1752 if (ps->info.fs.has_pcoord) {
1753 unsigned val;
1754 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1755 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1756 ps_offset++;
1757 }
1758
1759 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1760 unsigned vs_offset;
1761 bool flat_shade;
1762 if (!(ps->info.fs.input_mask & (1u << i)))
1763 continue;
1764
1765 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1766 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1767 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1768 ++ps_offset;
1769 continue;
1770 }
1771
1772 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1773
1774 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1775 ++ps_offset;
1776 }
1777
1778 pipeline->graphics.ps_input_cntl_num = ps_offset;
1779 }
1780
1781 VkResult
1782 radv_pipeline_init(struct radv_pipeline *pipeline,
1783 struct radv_device *device,
1784 struct radv_pipeline_cache *cache,
1785 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1786 const struct radv_graphics_pipeline_create_info *extra,
1787 const VkAllocationCallbacks *alloc)
1788 {
1789 struct radv_shader_module fs_m = {0};
1790 VkResult result;
1791 bool has_view_index = false;
1792
1793 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1794 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1795 if (subpass->view_mask)
1796 has_view_index = true;
1797 if (alloc == NULL)
1798 alloc = &device->alloc;
1799
1800 pipeline->device = device;
1801 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1802
1803 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1804 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1805 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1806 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1807 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1808 pStages[stage] = &pCreateInfo->pStages[i];
1809 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1810 }
1811
1812 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1813
1814 if (!modules[MESA_SHADER_FRAGMENT]) {
1815 nir_builder fs_b;
1816 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1817 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1818 fs_m.nir = fs_b.shader;
1819 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1820 }
1821
1822 if (modules[MESA_SHADER_FRAGMENT]) {
1823 struct ac_shader_variant_key key = {0};
1824 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1825 if (pCreateInfo->pMultisampleState &&
1826 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
1827 key.fs.multisample = true;
1828
1829 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1830 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);
1831
1832 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1833
1834 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1835 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1836 stage ? stage->pName : "main",
1837 MESA_SHADER_FRAGMENT,
1838 stage ? stage->pSpecializationInfo : NULL,
1839 pipeline->layout, &key);
1840 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1841 }
1842
1843 if (fs_m.nir)
1844 ralloc_free(fs_m.nir);
1845
1846 if (modules[MESA_SHADER_VERTEX]) {
1847 bool as_es = false;
1848 bool as_ls = false;
1849 bool export_prim_id = false;
1850 if (modules[MESA_SHADER_TESS_CTRL])
1851 as_ls = true;
1852 else if (modules[MESA_SHADER_GEOMETRY])
1853 as_es = true;
1854 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
1855 export_prim_id = true;
1856 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
1857 key.has_multiview_view_index = has_view_index;
1858
1859 pipeline->shaders[MESA_SHADER_VERTEX] =
1860 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1861 pStages[MESA_SHADER_VERTEX]->pName,
1862 MESA_SHADER_VERTEX,
1863 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1864 pipeline->layout, &key);
1865
1866 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1867 }
1868
1869 if (modules[MESA_SHADER_GEOMETRY]) {
1870 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
1871 key.has_multiview_view_index = has_view_index;
1872
1873 pipeline->shaders[MESA_SHADER_GEOMETRY] =
1874 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
1875 pStages[MESA_SHADER_GEOMETRY]->pName,
1876 MESA_SHADER_GEOMETRY,
1877 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
1878 pipeline->layout, &key);
1879
1880 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
1881 }
1882
1883 if (modules[MESA_SHADER_TESS_EVAL]) {
1884 assert(modules[MESA_SHADER_TESS_CTRL]);
1885
1886 radv_tess_pipeline_compile(pipeline,
1887 cache,
1888 modules[MESA_SHADER_TESS_CTRL],
1889 modules[MESA_SHADER_TESS_EVAL],
1890 pStages[MESA_SHADER_TESS_CTRL]->pName,
1891 pStages[MESA_SHADER_TESS_EVAL]->pName,
1892 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1893 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
1894 pipeline->layout,
1895 pCreateInfo->pTessellationState->patchControlPoints,
1896 has_view_index);
1897 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
1898 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
1899 }
1900
1901 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1902 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1903 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1904 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1905 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
1906
1907 if (radv_pipeline_has_gs(pipeline)) {
1908 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
1909 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1910 } else {
1911 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1912 }
1913 if (extra && extra->use_rectlist) {
1914 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1915 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1916 pipeline->graphics.can_use_guardband = true;
1917 }
1918 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1919 /* prim vertex count will need TESS changes */
1920 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
1921
1922 /* Ensure that some export memory is always allocated, for two reasons:
1923 *
1924 * 1) Correctness: The hardware ignores the EXEC mask if no export
1925 * memory is allocated, so KILL and alpha test do not work correctly
1926 * without this.
1927 * 2) Performance: Every shader needs at least a NULL export, even when
1928 * it writes no color/depth output. The NULL export instruction
1929 * stalls without this setting.
1930 *
1931 * Don't add this to CB_SHADER_MASK.
1932 */
1933 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1934 if (!pipeline->graphics.blend.spi_shader_col_format) {
1935 if (!ps->info.fs.writes_z &&
1936 !ps->info.fs.writes_stencil &&
1937 !ps->info.fs.writes_sample_mask)
1938 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1939 }
1940
1941 unsigned z_order;
1942 pipeline->graphics.db_shader_control = 0;
1943 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
1944 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
1945 else
1946 z_order = V_02880C_LATE_Z;
1947
1948 pipeline->graphics.db_shader_control =
1949 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
1950 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
1951 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
1952 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
1953 S_02880C_Z_ORDER(z_order) |
1954 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
1955 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
1956 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
1957
1958 if (pipeline->device->physical_device->has_rbplus)
1959 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1960
1961 pipeline->graphics.shader_z_format =
1962 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
1963 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
1964 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
1965 V_028710_SPI_SHADER_ZERO;
1966
1967 calculate_vgt_gs_mode(pipeline);
1968 calculate_pa_cl_vs_out_cntl(pipeline);
1969 calculate_ps_inputs(pipeline);
1970
1971 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1972 if (pipeline->shaders[i]) {
1973 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
1974 }
1975 }
1976
1977 uint32_t stages = 0;
1978 if (radv_pipeline_has_tess(pipeline)) {
1979 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1980 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
1981
1982 if (radv_pipeline_has_gs(pipeline))
1983 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1984 S_028B54_GS_EN(1) |
1985 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1986 else
1987 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1988
1989 } else if (radv_pipeline_has_gs(pipeline))
1990 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1991 S_028B54_GS_EN(1) |
1992 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1993
1994 if (device->physical_device->rad_info.chip_class >= GFX9)
1995 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
1996
1997 pipeline->graphics.vgt_shader_stages_en = stages;
1998
1999 if (radv_pipeline_has_gs(pipeline))
2000 calculate_gs_ring_sizes(pipeline);
2001
2002 if (radv_pipeline_has_tess(pipeline)) {
2003 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2004 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2005 pipeline->graphics.prim_vertex_count.incr = 1;
2006 }
2007 calculate_tess_state(pipeline, pCreateInfo);
2008 }
2009
2010 const VkPipelineVertexInputStateCreateInfo *vi_info =
2011 pCreateInfo->pVertexInputState;
2012 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
2013
2014 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2015 const VkVertexInputAttributeDescription *desc =
2016 &vi_info->pVertexAttributeDescriptions[i];
2017 unsigned loc = desc->location;
2018 const struct vk_format_description *format_desc;
2019 int first_non_void;
2020 uint32_t num_format, data_format;
2021 format_desc = vk_format_description(desc->format);
2022 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2023
2024 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2025 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2026
2027 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2028 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2029 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2030 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2031 S_008F0C_NUM_FORMAT(num_format) |
2032 S_008F0C_DATA_FORMAT(data_format);
2033 velems->format_size[loc] = format_desc->block.bits / 8;
2034 velems->offset[loc] = desc->offset;
2035 velems->binding[loc] = desc->binding;
2036 velems->count = MAX2(velems->count, loc + 1);
2037 }
2038
2039 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2040 const VkVertexInputBindingDescription *desc =
2041 &vi_info->pVertexBindingDescriptions[i];
2042
2043 pipeline->binding_stride[desc->binding] = desc->stride;
2044 }
2045
2046 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2047 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2048 if (loc->sgpr_idx != -1) {
2049 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2050 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2051 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2052 pipeline->graphics.vtx_emit_num = 3;
2053 else
2054 pipeline->graphics.vtx_emit_num = 2;
2055 }
2056 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2057 radv_dump_pipeline_stats(device, pipeline);
2058 }
2059
2060 result = radv_pipeline_scratch_init(device, pipeline);
2061 return result;
2062 }
2063
2064 VkResult
2065 radv_graphics_pipeline_create(
2066 VkDevice _device,
2067 VkPipelineCache _cache,
2068 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2069 const struct radv_graphics_pipeline_create_info *extra,
2070 const VkAllocationCallbacks *pAllocator,
2071 VkPipeline *pPipeline)
2072 {
2073 RADV_FROM_HANDLE(radv_device, device, _device);
2074 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2075 struct radv_pipeline *pipeline;
2076 VkResult result;
2077
2078 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2079 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2080 if (pipeline == NULL)
2081 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2082
2083 memset(pipeline, 0, sizeof(*pipeline));
2084 result = radv_pipeline_init(pipeline, device, cache,
2085 pCreateInfo, extra, pAllocator);
2086 if (result != VK_SUCCESS) {
2087 radv_pipeline_destroy(device, pipeline, pAllocator);
2088 return result;
2089 }
2090
2091 *pPipeline = radv_pipeline_to_handle(pipeline);
2092
2093 return VK_SUCCESS;
2094 }
2095
2096 VkResult radv_CreateGraphicsPipelines(
2097 VkDevice _device,
2098 VkPipelineCache pipelineCache,
2099 uint32_t count,
2100 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2101 const VkAllocationCallbacks* pAllocator,
2102 VkPipeline* pPipelines)
2103 {
2104 VkResult result = VK_SUCCESS;
2105 unsigned i = 0;
2106
2107 for (; i < count; i++) {
2108 VkResult r;
2109 r = radv_graphics_pipeline_create(_device,
2110 pipelineCache,
2111 &pCreateInfos[i],
2112 NULL, pAllocator, &pPipelines[i]);
2113 if (r != VK_SUCCESS) {
2114 result = r;
2115 pPipelines[i] = VK_NULL_HANDLE;
2116 }
2117 }
2118
2119 return result;
2120 }
2121
2122 static VkResult radv_compute_pipeline_create(
2123 VkDevice _device,
2124 VkPipelineCache _cache,
2125 const VkComputePipelineCreateInfo* pCreateInfo,
2126 const VkAllocationCallbacks* pAllocator,
2127 VkPipeline* pPipeline)
2128 {
2129 RADV_FROM_HANDLE(radv_device, device, _device);
2130 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2131 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2132 struct radv_pipeline *pipeline;
2133 VkResult result;
2134
2135 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2136 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2137 if (pipeline == NULL)
2138 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2139
2140 memset(pipeline, 0, sizeof(*pipeline));
2141 pipeline->device = device;
2142 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2143
2144 pipeline->shaders[MESA_SHADER_COMPUTE] =
2145 radv_pipeline_compile(pipeline, cache, module,
2146 pCreateInfo->stage.pName,
2147 MESA_SHADER_COMPUTE,
2148 pCreateInfo->stage.pSpecializationInfo,
2149 pipeline->layout, NULL);
2150
2151
2152 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2153 result = radv_pipeline_scratch_init(device, pipeline);
2154 if (result != VK_SUCCESS) {
2155 radv_pipeline_destroy(device, pipeline, pAllocator);
2156 return result;
2157 }
2158
2159 *pPipeline = radv_pipeline_to_handle(pipeline);
2160
2161 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2162 radv_dump_pipeline_stats(device, pipeline);
2163 }
2164 return VK_SUCCESS;
2165 }
2166 VkResult radv_CreateComputePipelines(
2167 VkDevice _device,
2168 VkPipelineCache pipelineCache,
2169 uint32_t count,
2170 const VkComputePipelineCreateInfo* pCreateInfos,
2171 const VkAllocationCallbacks* pAllocator,
2172 VkPipeline* pPipelines)
2173 {
2174 VkResult result = VK_SUCCESS;
2175
2176 unsigned i = 0;
2177 for (; i < count; i++) {
2178 VkResult r;
2179 r = radv_compute_pipeline_create(_device, pipelineCache,
2180 &pCreateInfos[i],
2181 pAllocator, &pPipelines[i]);
2182 if (r != VK_SUCCESS) {
2183 result = r;
2184 pPipelines[i] = VK_NULL_HANDLE;
2185 }
2186 }
2187
2188 return result;
2189 }