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radv: fix a GPU hang when MRTs are sparse
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
52
53 struct radv_blend_state {
54 uint32_t blend_enable_4bit;
55 uint32_t need_src_alpha;
56
57 uint32_t cb_color_control;
58 uint32_t cb_target_mask;
59 uint32_t cb_target_enabled_4bit;
60 uint32_t sx_mrt_blend_opt[8];
61 uint32_t cb_blend_control[8];
62
63 uint32_t spi_shader_col_format;
64 uint32_t cb_shader_mask;
65 uint32_t db_alpha_to_mask;
66
67 uint32_t commutative_4bit;
68
69 bool single_cb_enable;
70 bool mrt0_is_dual_src;
71 };
72
73 struct radv_dsa_order_invariance {
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
76 */
77 bool zs;
78
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
81 * fragments arrive.
82 */
83 bool pass_set;
84 };
85
86 struct radv_tessellation_state {
87 uint32_t ls_hs_config;
88 unsigned num_patches;
89 unsigned lds_size;
90 uint32_t tf_param;
91 };
92
93 struct radv_gs_state {
94 uint32_t vgt_gs_onchip_cntl;
95 uint32_t vgt_gs_max_prims_per_subgroup;
96 uint32_t vgt_esgs_ring_itemsize;
97 uint32_t lds_size;
98 };
99
100 static void
101 radv_pipeline_destroy(struct radv_device *device,
102 struct radv_pipeline *pipeline,
103 const VkAllocationCallbacks* allocator)
104 {
105 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
106 if (pipeline->shaders[i])
107 radv_shader_variant_destroy(device, pipeline->shaders[i]);
108
109 if (pipeline->gs_copy_shader)
110 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
111
112 if(pipeline->cs.buf)
113 free(pipeline->cs.buf);
114 vk_free2(&device->alloc, allocator, pipeline);
115 }
116
117 void radv_DestroyPipeline(
118 VkDevice _device,
119 VkPipeline _pipeline,
120 const VkAllocationCallbacks* pAllocator)
121 {
122 RADV_FROM_HANDLE(radv_device, device, _device);
123 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
124
125 if (!_pipeline)
126 return;
127
128 radv_pipeline_destroy(device, pipeline, pAllocator);
129 }
130
131 static uint32_t get_hash_flags(struct radv_device *device)
132 {
133 uint32_t hash_flags = 0;
134
135 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
136 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
137 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
138 hash_flags |= RADV_HASH_SHADER_SISCHED;
139 return hash_flags;
140 }
141
142 static VkResult
143 radv_pipeline_scratch_init(struct radv_device *device,
144 struct radv_pipeline *pipeline)
145 {
146 unsigned scratch_bytes_per_wave = 0;
147 unsigned max_waves = 0;
148 unsigned min_waves = 1;
149
150 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
151 if (pipeline->shaders[i]) {
152 unsigned max_stage_waves = device->scratch_waves;
153
154 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
155 pipeline->shaders[i]->config.scratch_bytes_per_wave);
156
157 max_stage_waves = MIN2(max_stage_waves,
158 4 * device->physical_device->rad_info.num_good_compute_units *
159 (256 / pipeline->shaders[i]->config.num_vgprs));
160 max_waves = MAX2(max_waves, max_stage_waves);
161 }
162 }
163
164 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
165 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
166 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
167 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
168 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
169 }
170
171 if (scratch_bytes_per_wave)
172 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
173
174 if (scratch_bytes_per_wave && max_waves < min_waves) {
175 /* Not really true at this moment, but will be true on first
176 * execution. Avoid having hanging shaders. */
177 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
178 }
179 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
180 pipeline->max_waves = max_waves;
181 return VK_SUCCESS;
182 }
183
184 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
185 {
186 switch (op) {
187 case VK_LOGIC_OP_CLEAR:
188 return V_028808_ROP3_CLEAR;
189 case VK_LOGIC_OP_AND:
190 return V_028808_ROP3_AND;
191 case VK_LOGIC_OP_AND_REVERSE:
192 return V_028808_ROP3_AND_REVERSE;
193 case VK_LOGIC_OP_COPY:
194 return V_028808_ROP3_COPY;
195 case VK_LOGIC_OP_AND_INVERTED:
196 return V_028808_ROP3_AND_INVERTED;
197 case VK_LOGIC_OP_NO_OP:
198 return V_028808_ROP3_NO_OP;
199 case VK_LOGIC_OP_XOR:
200 return V_028808_ROP3_XOR;
201 case VK_LOGIC_OP_OR:
202 return V_028808_ROP3_OR;
203 case VK_LOGIC_OP_NOR:
204 return V_028808_ROP3_NOR;
205 case VK_LOGIC_OP_EQUIVALENT:
206 return V_028808_ROP3_EQUIVALENT;
207 case VK_LOGIC_OP_INVERT:
208 return V_028808_ROP3_INVERT;
209 case VK_LOGIC_OP_OR_REVERSE:
210 return V_028808_ROP3_OR_REVERSE;
211 case VK_LOGIC_OP_COPY_INVERTED:
212 return V_028808_ROP3_COPY_INVERTED;
213 case VK_LOGIC_OP_OR_INVERTED:
214 return V_028808_ROP3_OR_INVERTED;
215 case VK_LOGIC_OP_NAND:
216 return V_028808_ROP3_NAND;
217 case VK_LOGIC_OP_SET:
218 return V_028808_ROP3_SET;
219 default:
220 unreachable("Unhandled logic op");
221 }
222 }
223
224
225 static uint32_t si_translate_blend_function(VkBlendOp op)
226 {
227 switch (op) {
228 case VK_BLEND_OP_ADD:
229 return V_028780_COMB_DST_PLUS_SRC;
230 case VK_BLEND_OP_SUBTRACT:
231 return V_028780_COMB_SRC_MINUS_DST;
232 case VK_BLEND_OP_REVERSE_SUBTRACT:
233 return V_028780_COMB_DST_MINUS_SRC;
234 case VK_BLEND_OP_MIN:
235 return V_028780_COMB_MIN_DST_SRC;
236 case VK_BLEND_OP_MAX:
237 return V_028780_COMB_MAX_DST_SRC;
238 default:
239 return 0;
240 }
241 }
242
243 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
244 {
245 switch (factor) {
246 case VK_BLEND_FACTOR_ZERO:
247 return V_028780_BLEND_ZERO;
248 case VK_BLEND_FACTOR_ONE:
249 return V_028780_BLEND_ONE;
250 case VK_BLEND_FACTOR_SRC_COLOR:
251 return V_028780_BLEND_SRC_COLOR;
252 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
253 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
254 case VK_BLEND_FACTOR_DST_COLOR:
255 return V_028780_BLEND_DST_COLOR;
256 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
257 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
258 case VK_BLEND_FACTOR_SRC_ALPHA:
259 return V_028780_BLEND_SRC_ALPHA;
260 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
261 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
262 case VK_BLEND_FACTOR_DST_ALPHA:
263 return V_028780_BLEND_DST_ALPHA;
264 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
265 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
266 case VK_BLEND_FACTOR_CONSTANT_COLOR:
267 return V_028780_BLEND_CONSTANT_COLOR;
268 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
269 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
270 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
271 return V_028780_BLEND_CONSTANT_ALPHA;
272 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
273 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
274 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
275 return V_028780_BLEND_SRC_ALPHA_SATURATE;
276 case VK_BLEND_FACTOR_SRC1_COLOR:
277 return V_028780_BLEND_SRC1_COLOR;
278 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
279 return V_028780_BLEND_INV_SRC1_COLOR;
280 case VK_BLEND_FACTOR_SRC1_ALPHA:
281 return V_028780_BLEND_SRC1_ALPHA;
282 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
283 return V_028780_BLEND_INV_SRC1_ALPHA;
284 default:
285 return 0;
286 }
287 }
288
289 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
290 {
291 switch (op) {
292 case VK_BLEND_OP_ADD:
293 return V_028760_OPT_COMB_ADD;
294 case VK_BLEND_OP_SUBTRACT:
295 return V_028760_OPT_COMB_SUBTRACT;
296 case VK_BLEND_OP_REVERSE_SUBTRACT:
297 return V_028760_OPT_COMB_REVSUBTRACT;
298 case VK_BLEND_OP_MIN:
299 return V_028760_OPT_COMB_MIN;
300 case VK_BLEND_OP_MAX:
301 return V_028760_OPT_COMB_MAX;
302 default:
303 return V_028760_OPT_COMB_BLEND_DISABLED;
304 }
305 }
306
307 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
308 {
309 switch (factor) {
310 case VK_BLEND_FACTOR_ZERO:
311 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
312 case VK_BLEND_FACTOR_ONE:
313 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
314 case VK_BLEND_FACTOR_SRC_COLOR:
315 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
316 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
317 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
318 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
319 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
320 case VK_BLEND_FACTOR_SRC_ALPHA:
321 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
322 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
323 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
325 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
326 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
327 default:
328 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
329 }
330 }
331
332 /**
333 * Get rid of DST in the blend factors by commuting the operands:
334 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
335 */
336 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
337 unsigned *dst_factor, unsigned expected_dst,
338 unsigned replacement_src)
339 {
340 if (*src_factor == expected_dst &&
341 *dst_factor == VK_BLEND_FACTOR_ZERO) {
342 *src_factor = VK_BLEND_FACTOR_ZERO;
343 *dst_factor = replacement_src;
344
345 /* Commuting the operands requires reversing subtractions. */
346 if (*func == VK_BLEND_OP_SUBTRACT)
347 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
348 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
349 *func = VK_BLEND_OP_SUBTRACT;
350 }
351 }
352
353 static bool si_blend_factor_uses_dst(unsigned factor)
354 {
355 return factor == VK_BLEND_FACTOR_DST_COLOR ||
356 factor == VK_BLEND_FACTOR_DST_ALPHA ||
357 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
358 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
359 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
360 }
361
362 static bool is_dual_src(VkBlendFactor factor)
363 {
364 switch (factor) {
365 case VK_BLEND_FACTOR_SRC1_COLOR:
366 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
367 case VK_BLEND_FACTOR_SRC1_ALPHA:
368 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
369 return true;
370 default:
371 return false;
372 }
373 }
374
375 static unsigned si_choose_spi_color_format(VkFormat vk_format,
376 bool blend_enable,
377 bool blend_need_alpha)
378 {
379 const struct vk_format_description *desc = vk_format_description(vk_format);
380 unsigned format, ntype, swap;
381
382 /* Alpha is needed for alpha-to-coverage.
383 * Blending may be with or without alpha.
384 */
385 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
386 unsigned alpha = 0; /* exports alpha, but may not support blending */
387 unsigned blend = 0; /* supports blending, but may not export alpha */
388 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
389
390 format = radv_translate_colorformat(vk_format);
391 ntype = radv_translate_color_numformat(vk_format, desc,
392 vk_format_get_first_non_void_channel(vk_format));
393 swap = radv_translate_colorswap(vk_format, false);
394
395 /* Choose the SPI color formats. These are required values for Stoney/RB+.
396 * Other chips have multiple choices, though they are not necessarily better.
397 */
398 switch (format) {
399 case V_028C70_COLOR_5_6_5:
400 case V_028C70_COLOR_1_5_5_5:
401 case V_028C70_COLOR_5_5_5_1:
402 case V_028C70_COLOR_4_4_4_4:
403 case V_028C70_COLOR_10_11_11:
404 case V_028C70_COLOR_11_11_10:
405 case V_028C70_COLOR_8:
406 case V_028C70_COLOR_8_8:
407 case V_028C70_COLOR_8_8_8_8:
408 case V_028C70_COLOR_10_10_10_2:
409 case V_028C70_COLOR_2_10_10_10:
410 if (ntype == V_028C70_NUMBER_UINT)
411 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
412 else if (ntype == V_028C70_NUMBER_SINT)
413 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
414 else
415 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
416 break;
417
418 case V_028C70_COLOR_16:
419 case V_028C70_COLOR_16_16:
420 case V_028C70_COLOR_16_16_16_16:
421 if (ntype == V_028C70_NUMBER_UNORM ||
422 ntype == V_028C70_NUMBER_SNORM) {
423 /* UNORM16 and SNORM16 don't support blending */
424 if (ntype == V_028C70_NUMBER_UNORM)
425 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
426 else
427 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
428
429 /* Use 32 bits per channel for blending. */
430 if (format == V_028C70_COLOR_16) {
431 if (swap == V_028C70_SWAP_STD) { /* R */
432 blend = V_028714_SPI_SHADER_32_R;
433 blend_alpha = V_028714_SPI_SHADER_32_AR;
434 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
435 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
436 else
437 assert(0);
438 } else if (format == V_028C70_COLOR_16_16) {
439 if (swap == V_028C70_SWAP_STD) { /* RG */
440 blend = V_028714_SPI_SHADER_32_GR;
441 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
442 } else if (swap == V_028C70_SWAP_ALT) /* RA */
443 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
444 else
445 assert(0);
446 } else /* 16_16_16_16 */
447 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
448 } else if (ntype == V_028C70_NUMBER_UINT)
449 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
450 else if (ntype == V_028C70_NUMBER_SINT)
451 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
452 else if (ntype == V_028C70_NUMBER_FLOAT)
453 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
454 else
455 assert(0);
456 break;
457
458 case V_028C70_COLOR_32:
459 if (swap == V_028C70_SWAP_STD) { /* R */
460 blend = normal = V_028714_SPI_SHADER_32_R;
461 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
462 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
463 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
464 else
465 assert(0);
466 break;
467
468 case V_028C70_COLOR_32_32:
469 if (swap == V_028C70_SWAP_STD) { /* RG */
470 blend = normal = V_028714_SPI_SHADER_32_GR;
471 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
472 } else if (swap == V_028C70_SWAP_ALT) /* RA */
473 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
474 else
475 assert(0);
476 break;
477
478 case V_028C70_COLOR_32_32_32_32:
479 case V_028C70_COLOR_8_24:
480 case V_028C70_COLOR_24_8:
481 case V_028C70_COLOR_X24_8_32_FLOAT:
482 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
483 break;
484
485 default:
486 unreachable("unhandled blend format");
487 }
488
489 if (blend_enable && blend_need_alpha)
490 return blend_alpha;
491 else if(blend_need_alpha)
492 return alpha;
493 else if(blend_enable)
494 return blend;
495 else
496 return normal;
497 }
498
499 static void
500 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
501 const VkGraphicsPipelineCreateInfo *pCreateInfo,
502 struct radv_blend_state *blend)
503 {
504 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
505 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
506 unsigned col_format = 0;
507 unsigned num_targets;
508
509 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
510 unsigned cf;
511
512 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
513 cf = V_028714_SPI_SHADER_ZERO;
514 } else {
515 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
516 bool blend_enable =
517 blend->blend_enable_4bit & (0xfu << (i * 4));
518
519 cf = si_choose_spi_color_format(attachment->format,
520 blend_enable,
521 blend->need_src_alpha & (1 << i));
522 }
523
524 col_format |= cf << (4 * i);
525 }
526
527 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
528
529 if (blend->mrt0_is_dual_src)
530 col_format |= (col_format & 0xf) << 4;
531 blend->spi_shader_col_format = col_format;
532
533 /* If the i-th target format is set, all previous target formats must
534 * be non-zero to avoid hangs.
535 */
536 num_targets = (util_last_bit(blend->spi_shader_col_format) + 3) / 4;
537 for (unsigned i = 0; i < num_targets; i++) {
538 if (!(blend->spi_shader_col_format & (0xf << (i * 4))))
539 blend->spi_shader_col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
540 }
541 }
542
543 static bool
544 format_is_int8(VkFormat format)
545 {
546 const struct vk_format_description *desc = vk_format_description(format);
547 int channel = vk_format_get_first_non_void_channel(format);
548
549 return channel >= 0 && desc->channel[channel].pure_integer &&
550 desc->channel[channel].size == 8;
551 }
552
553 static bool
554 format_is_int10(VkFormat format)
555 {
556 const struct vk_format_description *desc = vk_format_description(format);
557
558 if (desc->nr_channels != 4)
559 return false;
560 for (unsigned i = 0; i < 4; i++) {
561 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
562 return true;
563 }
564 return false;
565 }
566
567 unsigned radv_format_meta_fs_key(VkFormat format)
568 {
569 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
570 bool is_int8 = format_is_int8(format);
571 bool is_int10 = format_is_int10(format);
572
573 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
574 }
575
576 static void
577 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
578 unsigned *is_int8, unsigned *is_int10)
579 {
580 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
581 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
582 *is_int8 = 0;
583 *is_int10 = 0;
584
585 for (unsigned i = 0; i < subpass->color_count; ++i) {
586 struct radv_render_pass_attachment *attachment;
587
588 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
589 continue;
590
591 attachment = pass->attachments + subpass->color_attachments[i].attachment;
592
593 if (format_is_int8(attachment->format))
594 *is_int8 |= 1 << i;
595 if (format_is_int10(attachment->format))
596 *is_int10 |= 1 << i;
597 }
598 }
599
600 static void
601 radv_blend_check_commutativity(struct radv_blend_state *blend,
602 VkBlendOp op, VkBlendFactor src,
603 VkBlendFactor dst, unsigned chanmask)
604 {
605 /* Src factor is allowed when it does not depend on Dst. */
606 static const uint32_t src_allowed =
607 (1u << VK_BLEND_FACTOR_ONE) |
608 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
609 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
610 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
611 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
612 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
613 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
614 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
615 (1u << VK_BLEND_FACTOR_ZERO) |
616 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
617 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
618 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
619 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
622
623 if (dst == VK_BLEND_FACTOR_ONE &&
624 (src_allowed && (1u << src))) {
625 /* Addition is commutative, but floating point addition isn't
626 * associative: subtle changes can be introduced via different
627 * rounding. Be conservative, only enable for min and max.
628 */
629 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
630 blend->commutative_4bit |= chanmask;
631 }
632 }
633
634 static struct radv_blend_state
635 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
636 const VkGraphicsPipelineCreateInfo *pCreateInfo,
637 const struct radv_graphics_pipeline_create_info *extra)
638 {
639 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
640 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
641 struct radv_blend_state blend = {0};
642 unsigned mode = V_028808_CB_NORMAL;
643 int i;
644
645 if (!vkblend)
646 return blend;
647
648 if (extra && extra->custom_blend_mode) {
649 blend.single_cb_enable = true;
650 mode = extra->custom_blend_mode;
651 }
652 blend.cb_color_control = 0;
653 if (vkblend->logicOpEnable)
654 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
655 else
656 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
657
658 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
659 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
660 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
661 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
662
663 if (vkms && vkms->alphaToCoverageEnable) {
664 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
665 }
666
667 blend.cb_target_mask = 0;
668 for (i = 0; i < vkblend->attachmentCount; i++) {
669 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
670 unsigned blend_cntl = 0;
671 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
672 VkBlendOp eqRGB = att->colorBlendOp;
673 VkBlendFactor srcRGB = att->srcColorBlendFactor;
674 VkBlendFactor dstRGB = att->dstColorBlendFactor;
675 VkBlendOp eqA = att->alphaBlendOp;
676 VkBlendFactor srcA = att->srcAlphaBlendFactor;
677 VkBlendFactor dstA = att->dstAlphaBlendFactor;
678
679 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
680
681 if (!att->colorWriteMask)
682 continue;
683
684 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
685 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
686 if (!att->blendEnable) {
687 blend.cb_blend_control[i] = blend_cntl;
688 continue;
689 }
690
691 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
692 if (i == 0)
693 blend.mrt0_is_dual_src = true;
694
695 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
696 srcRGB = VK_BLEND_FACTOR_ONE;
697 dstRGB = VK_BLEND_FACTOR_ONE;
698 }
699 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
700 srcA = VK_BLEND_FACTOR_ONE;
701 dstA = VK_BLEND_FACTOR_ONE;
702 }
703
704 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
705 0x7 << (4 * i));
706 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
707 0x8 << (4 * i));
708
709 /* Blending optimizations for RB+.
710 * These transformations don't change the behavior.
711 *
712 * First, get rid of DST in the blend factors:
713 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
714 */
715 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
716 VK_BLEND_FACTOR_DST_COLOR,
717 VK_BLEND_FACTOR_SRC_COLOR);
718
719 si_blend_remove_dst(&eqA, &srcA, &dstA,
720 VK_BLEND_FACTOR_DST_COLOR,
721 VK_BLEND_FACTOR_SRC_COLOR);
722
723 si_blend_remove_dst(&eqA, &srcA, &dstA,
724 VK_BLEND_FACTOR_DST_ALPHA,
725 VK_BLEND_FACTOR_SRC_ALPHA);
726
727 /* Look up the ideal settings from tables. */
728 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
729 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
730 srcA_opt = si_translate_blend_opt_factor(srcA, true);
731 dstA_opt = si_translate_blend_opt_factor(dstA, true);
732
733 /* Handle interdependencies. */
734 if (si_blend_factor_uses_dst(srcRGB))
735 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
736 if (si_blend_factor_uses_dst(srcA))
737 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
738
739 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
740 (dstRGB == VK_BLEND_FACTOR_ZERO ||
741 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
742 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
743 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
744
745 /* Set the final value. */
746 blend.sx_mrt_blend_opt[i] =
747 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
748 S_028760_COLOR_DST_OPT(dstRGB_opt) |
749 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
750 S_028760_ALPHA_SRC_OPT(srcA_opt) |
751 S_028760_ALPHA_DST_OPT(dstA_opt) |
752 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
753 blend_cntl |= S_028780_ENABLE(1);
754
755 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
756 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
757 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
758 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
759 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
760 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
761 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
762 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
763 }
764 blend.cb_blend_control[i] = blend_cntl;
765
766 blend.blend_enable_4bit |= 0xfu << (i * 4);
767
768 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
769 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
770 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
771 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
772 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
773 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
774 blend.need_src_alpha |= 1 << i;
775 }
776 for (i = vkblend->attachmentCount; i < 8; i++) {
777 blend.cb_blend_control[i] = 0;
778 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
779 }
780
781 if (pipeline->device->physical_device->has_rbplus) {
782 /* Disable RB+ blend optimizations for dual source blending. */
783 if (blend.mrt0_is_dual_src) {
784 for (i = 0; i < 8; i++) {
785 blend.sx_mrt_blend_opt[i] =
786 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
787 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
788 }
789 }
790
791 /* RB+ doesn't work with dual source blending, logic op and
792 * RESOLVE.
793 */
794 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
795 mode == V_028808_CB_RESOLVE)
796 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
797 }
798
799 if (blend.cb_target_mask)
800 blend.cb_color_control |= S_028808_MODE(mode);
801 else
802 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
803
804 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
805 return blend;
806 }
807
808 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
809 {
810 switch (op) {
811 case VK_STENCIL_OP_KEEP:
812 return V_02842C_STENCIL_KEEP;
813 case VK_STENCIL_OP_ZERO:
814 return V_02842C_STENCIL_ZERO;
815 case VK_STENCIL_OP_REPLACE:
816 return V_02842C_STENCIL_REPLACE_TEST;
817 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
818 return V_02842C_STENCIL_ADD_CLAMP;
819 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
820 return V_02842C_STENCIL_SUB_CLAMP;
821 case VK_STENCIL_OP_INVERT:
822 return V_02842C_STENCIL_INVERT;
823 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
824 return V_02842C_STENCIL_ADD_WRAP;
825 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
826 return V_02842C_STENCIL_SUB_WRAP;
827 default:
828 return 0;
829 }
830 }
831
832 static uint32_t si_translate_fill(VkPolygonMode func)
833 {
834 switch(func) {
835 case VK_POLYGON_MODE_FILL:
836 return V_028814_X_DRAW_TRIANGLES;
837 case VK_POLYGON_MODE_LINE:
838 return V_028814_X_DRAW_LINES;
839 case VK_POLYGON_MODE_POINT:
840 return V_028814_X_DRAW_POINTS;
841 default:
842 assert(0);
843 return V_028814_X_DRAW_POINTS;
844 }
845 }
846
847 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
848 {
849 uint32_t num_samples = vkms->rasterizationSamples;
850 uint32_t ps_iter_samples = 1;
851
852 if (vkms->sampleShadingEnable) {
853 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
854 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
855 }
856 return ps_iter_samples;
857 }
858
859 static bool
860 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
861 {
862 return pCreateInfo->depthTestEnable &&
863 pCreateInfo->depthWriteEnable &&
864 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
865 }
866
867 static bool
868 radv_writes_stencil(const VkStencilOpState *state)
869 {
870 return state->writeMask &&
871 (state->failOp != VK_STENCIL_OP_KEEP ||
872 state->passOp != VK_STENCIL_OP_KEEP ||
873 state->depthFailOp != VK_STENCIL_OP_KEEP);
874 }
875
876 static bool
877 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
878 {
879 return pCreateInfo->stencilTestEnable &&
880 (radv_writes_stencil(&pCreateInfo->front) ||
881 radv_writes_stencil(&pCreateInfo->back));
882 }
883
884 static bool
885 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
886 {
887 return radv_is_depth_write_enabled(pCreateInfo) ||
888 radv_is_stencil_write_enabled(pCreateInfo);
889 }
890
891 static bool
892 radv_order_invariant_stencil_op(VkStencilOp op)
893 {
894 /* REPLACE is normally order invariant, except when the stencil
895 * reference value is written by the fragment shader. Tracking this
896 * interaction does not seem worth the effort, so be conservative.
897 */
898 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
899 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
900 op != VK_STENCIL_OP_REPLACE;
901 }
902
903 static bool
904 radv_order_invariant_stencil_state(const VkStencilOpState *state)
905 {
906 /* Compute whether, assuming Z writes are disabled, this stencil state
907 * is order invariant in the sense that the set of passing fragments as
908 * well as the final stencil buffer result does not depend on the order
909 * of fragments.
910 */
911 return !state->writeMask ||
912 /* The following assumes that Z writes are disabled. */
913 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
914 radv_order_invariant_stencil_op(state->passOp) &&
915 radv_order_invariant_stencil_op(state->depthFailOp)) ||
916 (state->compareOp == VK_COMPARE_OP_NEVER &&
917 radv_order_invariant_stencil_op(state->failOp));
918 }
919
920 static bool
921 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
922 struct radv_blend_state *blend,
923 const VkGraphicsPipelineCreateInfo *pCreateInfo)
924 {
925 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
926 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
927 unsigned colormask = blend->cb_target_enabled_4bit;
928
929 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
930 return false;
931
932 /* Be conservative if a logic operation is enabled with color buffers. */
933 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
934 return false;
935
936 /* Default depth/stencil invariance when no attachment is bound. */
937 struct radv_dsa_order_invariance dsa_order_invariant = {
938 .zs = true, .pass_set = true
939 };
940
941 if (pCreateInfo->pDepthStencilState &&
942 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
943 const VkPipelineDepthStencilStateCreateInfo *vkds =
944 pCreateInfo->pDepthStencilState;
945 struct radv_render_pass_attachment *attachment =
946 pass->attachments + subpass->depth_stencil_attachment.attachment;
947 bool has_stencil = vk_format_is_stencil(attachment->format);
948 struct radv_dsa_order_invariance order_invariance[2];
949 struct radv_shader_variant *ps =
950 pipeline->shaders[MESA_SHADER_FRAGMENT];
951
952 /* Compute depth/stencil order invariance in order to know if
953 * it's safe to enable out-of-order.
954 */
955 bool zfunc_is_ordered =
956 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
957 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
958 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
959 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
960 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
961
962 bool nozwrite_and_order_invariant_stencil =
963 !radv_is_ds_write_enabled(vkds) ||
964 (!radv_is_depth_write_enabled(vkds) &&
965 radv_order_invariant_stencil_state(&vkds->front) &&
966 radv_order_invariant_stencil_state(&vkds->back));
967
968 order_invariance[1].zs =
969 nozwrite_and_order_invariant_stencil ||
970 (!radv_is_stencil_write_enabled(vkds) &&
971 zfunc_is_ordered);
972 order_invariance[0].zs =
973 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
974
975 order_invariance[1].pass_set =
976 nozwrite_and_order_invariant_stencil ||
977 (!radv_is_stencil_write_enabled(vkds) &&
978 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
979 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
980 order_invariance[0].pass_set =
981 !radv_is_depth_write_enabled(vkds) ||
982 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
983 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
984
985 dsa_order_invariant = order_invariance[has_stencil];
986 if (!dsa_order_invariant.zs)
987 return false;
988
989 /* The set of PS invocations is always order invariant,
990 * except when early Z/S tests are requested.
991 */
992 if (ps &&
993 ps->info.info.ps.writes_memory &&
994 ps->info.fs.early_fragment_test &&
995 !dsa_order_invariant.pass_set)
996 return false;
997
998 /* Determine if out-of-order rasterization should be disabled
999 * when occlusion queries are used.
1000 */
1001 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1002 !dsa_order_invariant.pass_set;
1003 }
1004
1005 /* No color buffers are enabled for writing. */
1006 if (!colormask)
1007 return true;
1008
1009 unsigned blendmask = colormask & blend->blend_enable_4bit;
1010
1011 if (blendmask) {
1012 /* Only commutative blending. */
1013 if (blendmask & ~blend->commutative_4bit)
1014 return false;
1015
1016 if (!dsa_order_invariant.pass_set)
1017 return false;
1018 }
1019
1020 if (colormask & ~blendmask)
1021 return false;
1022
1023 return true;
1024 }
1025
1026 static void
1027 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1028 struct radv_blend_state *blend,
1029 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1030 {
1031 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1032 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1033 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1034 bool out_of_order_rast = false;
1035 int ps_iter_samples = 1;
1036 uint32_t mask = 0xffff;
1037
1038 if (vkms)
1039 ms->num_samples = vkms->rasterizationSamples;
1040 else
1041 ms->num_samples = 1;
1042
1043 if (vkms)
1044 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1045 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1046 ps_iter_samples = ms->num_samples;
1047 }
1048
1049 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1050 ms->pa_sc_aa_config = 0;
1051 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1052 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1053 ms->pa_sc_mode_cntl_1 =
1054 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1055 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1056 /* always 1: */
1057 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1058 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1059 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1060 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1061 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1062 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1063 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1064 S_028A48_VPORT_SCISSOR_ENABLE(1);
1065
1066 if (ms->num_samples > 1) {
1067 unsigned log_samples = util_logbase2(ms->num_samples);
1068 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1069 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1070 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1071 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1072 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1073 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1074 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1075 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1076 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1077 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1078 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1079 if (ps_iter_samples > 1)
1080 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1081 }
1082
1083 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1084 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1085 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1086 /* Out-of-order rasterization is explicitly enabled by the
1087 * application.
1088 */
1089 out_of_order_rast = true;
1090 } else {
1091 /* Determine if the driver can enable out-of-order
1092 * rasterization internally.
1093 */
1094 out_of_order_rast =
1095 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1096 }
1097
1098 if (out_of_order_rast) {
1099 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
1100 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
1101 }
1102
1103 if (vkms && vkms->pSampleMask) {
1104 mask = vkms->pSampleMask[0] & 0xffff;
1105 }
1106
1107 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1108 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1109 }
1110
1111 static bool
1112 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1113 {
1114 switch (topology) {
1115 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1116 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1117 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1118 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1119 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1120 return false;
1121 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1122 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1123 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1124 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1125 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1126 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1127 return true;
1128 default:
1129 unreachable("unhandled primitive type");
1130 }
1131 }
1132
1133 static uint32_t
1134 si_translate_prim(enum VkPrimitiveTopology topology)
1135 {
1136 switch (topology) {
1137 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1138 return V_008958_DI_PT_POINTLIST;
1139 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1140 return V_008958_DI_PT_LINELIST;
1141 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1142 return V_008958_DI_PT_LINESTRIP;
1143 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1144 return V_008958_DI_PT_TRILIST;
1145 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1146 return V_008958_DI_PT_TRISTRIP;
1147 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1148 return V_008958_DI_PT_TRIFAN;
1149 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1150 return V_008958_DI_PT_LINELIST_ADJ;
1151 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1152 return V_008958_DI_PT_LINESTRIP_ADJ;
1153 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1154 return V_008958_DI_PT_TRILIST_ADJ;
1155 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1156 return V_008958_DI_PT_TRISTRIP_ADJ;
1157 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1158 return V_008958_DI_PT_PATCH;
1159 default:
1160 assert(0);
1161 return 0;
1162 }
1163 }
1164
1165 static uint32_t
1166 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1167 {
1168 switch (gl_prim) {
1169 case 0: /* GL_POINTS */
1170 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1171 case 1: /* GL_LINES */
1172 case 3: /* GL_LINE_STRIP */
1173 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1174 case 0x8E7A: /* GL_ISOLINES */
1175 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1176
1177 case 4: /* GL_TRIANGLES */
1178 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1179 case 5: /* GL_TRIANGLE_STRIP */
1180 case 7: /* GL_QUADS */
1181 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1182 default:
1183 assert(0);
1184 return 0;
1185 }
1186 }
1187
1188 static uint32_t
1189 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1190 {
1191 switch (topology) {
1192 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1193 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1194 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1195 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1196 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1197 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1198 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1199 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1200 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1201 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1202 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1203 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1205 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1206 default:
1207 assert(0);
1208 return 0;
1209 }
1210 }
1211
1212 static unsigned si_map_swizzle(unsigned swizzle)
1213 {
1214 switch (swizzle) {
1215 case VK_SWIZZLE_Y:
1216 return V_008F0C_SQ_SEL_Y;
1217 case VK_SWIZZLE_Z:
1218 return V_008F0C_SQ_SEL_Z;
1219 case VK_SWIZZLE_W:
1220 return V_008F0C_SQ_SEL_W;
1221 case VK_SWIZZLE_0:
1222 return V_008F0C_SQ_SEL_0;
1223 case VK_SWIZZLE_1:
1224 return V_008F0C_SQ_SEL_1;
1225 default: /* VK_SWIZZLE_X */
1226 return V_008F0C_SQ_SEL_X;
1227 }
1228 }
1229
1230
1231 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1232 {
1233 switch(state) {
1234 case VK_DYNAMIC_STATE_VIEWPORT:
1235 return RADV_DYNAMIC_VIEWPORT;
1236 case VK_DYNAMIC_STATE_SCISSOR:
1237 return RADV_DYNAMIC_SCISSOR;
1238 case VK_DYNAMIC_STATE_LINE_WIDTH:
1239 return RADV_DYNAMIC_LINE_WIDTH;
1240 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1241 return RADV_DYNAMIC_DEPTH_BIAS;
1242 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1243 return RADV_DYNAMIC_BLEND_CONSTANTS;
1244 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1245 return RADV_DYNAMIC_DEPTH_BOUNDS;
1246 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1247 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1248 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1249 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1250 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1251 return RADV_DYNAMIC_STENCIL_REFERENCE;
1252 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1253 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1254 default:
1255 unreachable("Unhandled dynamic state");
1256 }
1257 }
1258
1259 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1260 {
1261 uint32_t states = RADV_DYNAMIC_ALL;
1262
1263 /* If rasterization is disabled we do not care about any of the dynamic states,
1264 * since they are all rasterization related only. */
1265 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1266 return 0;
1267
1268 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1269 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1270
1271 if (!pCreateInfo->pDepthStencilState ||
1272 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1273 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1274
1275 if (!pCreateInfo->pDepthStencilState ||
1276 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1277 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1278 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1279 RADV_DYNAMIC_STENCIL_REFERENCE);
1280
1281 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1282 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1283
1284 /* TODO: blend constants & line width. */
1285
1286 return states;
1287 }
1288
1289
1290 static void
1291 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1292 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1293 {
1294 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1295 uint32_t states = needed_states;
1296 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1297 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1298
1299 pipeline->dynamic_state = default_dynamic_state;
1300 pipeline->graphics.needed_dynamic_state = needed_states;
1301
1302 if (pCreateInfo->pDynamicState) {
1303 /* Remove all of the states that are marked as dynamic */
1304 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1305 for (uint32_t s = 0; s < count; s++)
1306 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1307 }
1308
1309 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1310
1311 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1312 assert(pCreateInfo->pViewportState);
1313
1314 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1315 if (states & RADV_DYNAMIC_VIEWPORT) {
1316 typed_memcpy(dynamic->viewport.viewports,
1317 pCreateInfo->pViewportState->pViewports,
1318 pCreateInfo->pViewportState->viewportCount);
1319 }
1320 }
1321
1322 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1323 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1324 if (states & RADV_DYNAMIC_SCISSOR) {
1325 typed_memcpy(dynamic->scissor.scissors,
1326 pCreateInfo->pViewportState->pScissors,
1327 pCreateInfo->pViewportState->scissorCount);
1328 }
1329 }
1330
1331 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1332 assert(pCreateInfo->pRasterizationState);
1333 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1334 }
1335
1336 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1337 assert(pCreateInfo->pRasterizationState);
1338 dynamic->depth_bias.bias =
1339 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1340 dynamic->depth_bias.clamp =
1341 pCreateInfo->pRasterizationState->depthBiasClamp;
1342 dynamic->depth_bias.slope =
1343 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1344 }
1345
1346 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1347 *
1348 * pColorBlendState is [...] NULL if the pipeline has rasterization
1349 * disabled or if the subpass of the render pass the pipeline is
1350 * created against does not use any color attachments.
1351 */
1352 bool uses_color_att = false;
1353 for (unsigned i = 0; i < subpass->color_count; ++i) {
1354 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1355 uses_color_att = true;
1356 break;
1357 }
1358 }
1359
1360 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1361 assert(pCreateInfo->pColorBlendState);
1362 typed_memcpy(dynamic->blend_constants,
1363 pCreateInfo->pColorBlendState->blendConstants, 4);
1364 }
1365
1366 /* If there is no depthstencil attachment, then don't read
1367 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1368 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1369 * no need to override the depthstencil defaults in
1370 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1371 *
1372 * Section 9.2 of the Vulkan 1.0.15 spec says:
1373 *
1374 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1375 * disabled or if the subpass of the render pass the pipeline is created
1376 * against does not use a depth/stencil attachment.
1377 */
1378 if (needed_states &&
1379 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1380 assert(pCreateInfo->pDepthStencilState);
1381
1382 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1383 dynamic->depth_bounds.min =
1384 pCreateInfo->pDepthStencilState->minDepthBounds;
1385 dynamic->depth_bounds.max =
1386 pCreateInfo->pDepthStencilState->maxDepthBounds;
1387 }
1388
1389 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1390 dynamic->stencil_compare_mask.front =
1391 pCreateInfo->pDepthStencilState->front.compareMask;
1392 dynamic->stencil_compare_mask.back =
1393 pCreateInfo->pDepthStencilState->back.compareMask;
1394 }
1395
1396 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1397 dynamic->stencil_write_mask.front =
1398 pCreateInfo->pDepthStencilState->front.writeMask;
1399 dynamic->stencil_write_mask.back =
1400 pCreateInfo->pDepthStencilState->back.writeMask;
1401 }
1402
1403 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1404 dynamic->stencil_reference.front =
1405 pCreateInfo->pDepthStencilState->front.reference;
1406 dynamic->stencil_reference.back =
1407 pCreateInfo->pDepthStencilState->back.reference;
1408 }
1409 }
1410
1411 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1412 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1413 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1414 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1415 typed_memcpy(dynamic->discard_rectangle.rectangles,
1416 discard_rectangle_info->pDiscardRectangles,
1417 discard_rectangle_info->discardRectangleCount);
1418 }
1419
1420 pipeline->dynamic_state.mask = states;
1421 }
1422
1423 static struct radv_gs_state
1424 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1425 const struct radv_pipeline *pipeline)
1426 {
1427 struct radv_gs_state gs = {0};
1428 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1429 struct radv_es_output_info *es_info;
1430 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1431 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1432 else
1433 es_info = radv_pipeline_has_tess(pipeline) ?
1434 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1435 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1436
1437 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1438 bool uses_adjacency;
1439 switch(pCreateInfo->pInputAssemblyState->topology) {
1440 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1441 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1442 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1443 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1444 uses_adjacency = true;
1445 break;
1446 default:
1447 uses_adjacency = false;
1448 break;
1449 }
1450
1451 /* All these are in dwords: */
1452 /* We can't allow using the whole LDS, because GS waves compete with
1453 * other shader stages for LDS space. */
1454 const unsigned max_lds_size = 8 * 1024;
1455 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1456 unsigned esgs_lds_size;
1457
1458 /* All these are per subgroup: */
1459 const unsigned max_out_prims = 32 * 1024;
1460 const unsigned max_es_verts = 255;
1461 const unsigned ideal_gs_prims = 64;
1462 unsigned max_gs_prims, gs_prims;
1463 unsigned min_es_verts, es_verts, worst_case_es_verts;
1464
1465 if (uses_adjacency || gs_num_invocations > 1)
1466 max_gs_prims = 127 / gs_num_invocations;
1467 else
1468 max_gs_prims = 255;
1469
1470 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1471 * Make sure we don't go over the maximum value.
1472 */
1473 if (gs_info->gs.vertices_out > 0) {
1474 max_gs_prims = MIN2(max_gs_prims,
1475 max_out_prims /
1476 (gs_info->gs.vertices_out * gs_num_invocations));
1477 }
1478 assert(max_gs_prims > 0);
1479
1480 /* If the primitive has adjacency, halve the number of vertices
1481 * that will be reused in multiple primitives.
1482 */
1483 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1484
1485 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1486 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1487
1488 /* Compute ESGS LDS size based on the worst case number of ES vertices
1489 * needed to create the target number of GS prims per subgroup.
1490 */
1491 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1492
1493 /* If total LDS usage is too big, refactor partitions based on ratio
1494 * of ESGS item sizes.
1495 */
1496 if (esgs_lds_size > max_lds_size) {
1497 /* Our target GS Prims Per Subgroup was too large. Calculate
1498 * the maximum number of GS Prims Per Subgroup that will fit
1499 * into LDS, capped by the maximum that the hardware can support.
1500 */
1501 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1502 max_gs_prims);
1503 assert(gs_prims > 0);
1504 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1505 max_es_verts);
1506
1507 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1508 assert(esgs_lds_size <= max_lds_size);
1509 }
1510
1511 /* Now calculate remaining ESGS information. */
1512 if (esgs_lds_size)
1513 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1514 else
1515 es_verts = max_es_verts;
1516
1517 /* Vertices for adjacency primitives are not always reused, so restore
1518 * it for ES_VERTS_PER_SUBGRP.
1519 */
1520 min_es_verts = gs_info->gs.vertices_in;
1521
1522 /* For normal primitives, the VGT only checks if they are past the ES
1523 * verts per subgroup after allocating a full GS primitive and if they
1524 * are, kick off a new subgroup. But if those additional ES verts are
1525 * unique (e.g. not reused) we need to make sure there is enough LDS
1526 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1527 */
1528 es_verts -= min_es_verts - 1;
1529
1530 uint32_t es_verts_per_subgroup = es_verts;
1531 uint32_t gs_prims_per_subgroup = gs_prims;
1532 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1533 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1534 gs.lds_size = align(esgs_lds_size, 128) / 128;
1535 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1536 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1537 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1538 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1539 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1540 assert(max_prims_per_subgroup <= max_out_prims);
1541
1542 return gs;
1543 }
1544
1545 static void
1546 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1547 {
1548 struct radv_device *device = pipeline->device;
1549 unsigned num_se = device->physical_device->rad_info.max_se;
1550 unsigned wave_size = 64;
1551 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1552 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1553 unsigned alignment = 256 * num_se;
1554 /* The maximum size is 63.999 MB per SE. */
1555 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1556 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1557
1558 /* Calculate the minimum size. */
1559 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1560 wave_size, alignment);
1561 /* These are recommended sizes, not minimum sizes. */
1562 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1563 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1564 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1565 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1566
1567 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1568 esgs_ring_size = align(esgs_ring_size, alignment);
1569 gsvs_ring_size = align(gsvs_ring_size, alignment);
1570
1571 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1572 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1573
1574 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1575 }
1576
1577 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1578 unsigned *lds_size)
1579 {
1580 /* If tessellation is all offchip and on-chip GS isn't used, this
1581 * workaround is not needed.
1582 */
1583 return;
1584
1585 /* SPI barrier management bug:
1586 * Make sure we have at least 4k of LDS in use to avoid the bug.
1587 * It applies to workgroup sizes of more than one wavefront.
1588 */
1589 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1590 device->physical_device->rad_info.family == CHIP_KABINI ||
1591 device->physical_device->rad_info.family == CHIP_MULLINS)
1592 *lds_size = MAX2(*lds_size, 8);
1593 }
1594
1595 struct radv_shader_variant *
1596 radv_get_shader(struct radv_pipeline *pipeline,
1597 gl_shader_stage stage)
1598 {
1599 if (stage == MESA_SHADER_VERTEX) {
1600 if (pipeline->shaders[MESA_SHADER_VERTEX])
1601 return pipeline->shaders[MESA_SHADER_VERTEX];
1602 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1603 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1604 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1605 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1606 } else if (stage == MESA_SHADER_TESS_EVAL) {
1607 if (!radv_pipeline_has_tess(pipeline))
1608 return NULL;
1609 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1610 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1611 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1612 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1613 }
1614 return pipeline->shaders[stage];
1615 }
1616
1617 static struct radv_tessellation_state
1618 calculate_tess_state(struct radv_pipeline *pipeline,
1619 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1620 {
1621 unsigned num_tcs_input_cp;
1622 unsigned num_tcs_output_cp;
1623 unsigned lds_size;
1624 unsigned num_patches;
1625 struct radv_tessellation_state tess = {0};
1626
1627 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1628 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1629 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1630
1631 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1632
1633 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1634 assert(lds_size <= 65536);
1635 lds_size = align(lds_size, 512) / 512;
1636 } else {
1637 assert(lds_size <= 32768);
1638 lds_size = align(lds_size, 256) / 256;
1639 }
1640 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1641
1642 tess.lds_size = lds_size;
1643
1644 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1645 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1646 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1647 tess.num_patches = num_patches;
1648
1649 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1650 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1651
1652 switch (tes->info.tes.primitive_mode) {
1653 case GL_TRIANGLES:
1654 type = V_028B6C_TESS_TRIANGLE;
1655 break;
1656 case GL_QUADS:
1657 type = V_028B6C_TESS_QUAD;
1658 break;
1659 case GL_ISOLINES:
1660 type = V_028B6C_TESS_ISOLINE;
1661 break;
1662 }
1663
1664 switch (tes->info.tes.spacing) {
1665 case TESS_SPACING_EQUAL:
1666 partitioning = V_028B6C_PART_INTEGER;
1667 break;
1668 case TESS_SPACING_FRACTIONAL_ODD:
1669 partitioning = V_028B6C_PART_FRAC_ODD;
1670 break;
1671 case TESS_SPACING_FRACTIONAL_EVEN:
1672 partitioning = V_028B6C_PART_FRAC_EVEN;
1673 break;
1674 default:
1675 break;
1676 }
1677
1678 bool ccw = tes->info.tes.ccw;
1679 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1680 vk_find_struct_const(pCreateInfo->pTessellationState,
1681 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1682
1683 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1684 ccw = !ccw;
1685
1686 if (tes->info.tes.point_mode)
1687 topology = V_028B6C_OUTPUT_POINT;
1688 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1689 topology = V_028B6C_OUTPUT_LINE;
1690 else if (ccw)
1691 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1692 else
1693 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1694
1695 if (pipeline->device->has_distributed_tess) {
1696 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1697 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1698 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1699 else
1700 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1701 } else
1702 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1703
1704 tess.tf_param = S_028B6C_TYPE(type) |
1705 S_028B6C_PARTITIONING(partitioning) |
1706 S_028B6C_TOPOLOGY(topology) |
1707 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1708
1709 return tess;
1710 }
1711
1712 static const struct radv_prim_vertex_count prim_size_table[] = {
1713 [V_008958_DI_PT_NONE] = {0, 0},
1714 [V_008958_DI_PT_POINTLIST] = {1, 1},
1715 [V_008958_DI_PT_LINELIST] = {2, 2},
1716 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1717 [V_008958_DI_PT_TRILIST] = {3, 3},
1718 [V_008958_DI_PT_TRIFAN] = {3, 1},
1719 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1720 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1721 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1722 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1723 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1724 [V_008958_DI_PT_RECTLIST] = {3, 3},
1725 [V_008958_DI_PT_LINELOOP] = {2, 1},
1726 [V_008958_DI_PT_POLYGON] = {3, 1},
1727 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1728 };
1729
1730 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1731 {
1732 if (radv_pipeline_has_gs(pipeline))
1733 return &pipeline->gs_copy_shader->info.vs.outinfo;
1734 else if (radv_pipeline_has_tess(pipeline))
1735 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1736 else
1737 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1738 }
1739
1740 static void
1741 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1742 {
1743 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1744 int shader_count = 0;
1745
1746 if(shaders[MESA_SHADER_FRAGMENT]) {
1747 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1748 }
1749 if(shaders[MESA_SHADER_GEOMETRY]) {
1750 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1751 }
1752 if(shaders[MESA_SHADER_TESS_EVAL]) {
1753 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1754 }
1755 if(shaders[MESA_SHADER_TESS_CTRL]) {
1756 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1757 }
1758 if(shaders[MESA_SHADER_VERTEX]) {
1759 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1760 }
1761
1762 for (int i = 1; i < shader_count; ++i) {
1763 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1764 ordered_shaders[i - 1]);
1765
1766 nir_remove_dead_variables(ordered_shaders[i],
1767 nir_var_shader_out);
1768 nir_remove_dead_variables(ordered_shaders[i - 1],
1769 nir_var_shader_in);
1770
1771 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1772 ordered_shaders[i - 1]);
1773
1774 nir_compact_varyings(ordered_shaders[i],
1775 ordered_shaders[i - 1], true);
1776
1777 if (progress) {
1778 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1779 ac_lower_indirect_derefs(ordered_shaders[i],
1780 pipeline->device->physical_device->rad_info.chip_class);
1781 }
1782 radv_optimize_nir(ordered_shaders[i], false);
1783
1784 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1785 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1786 pipeline->device->physical_device->rad_info.chip_class);
1787 }
1788 radv_optimize_nir(ordered_shaders[i - 1], false);
1789 }
1790 }
1791 }
1792
1793
1794 static struct radv_pipeline_key
1795 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1796 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1797 const struct radv_blend_state *blend,
1798 bool has_view_index)
1799 {
1800 const VkPipelineVertexInputStateCreateInfo *input_state =
1801 pCreateInfo->pVertexInputState;
1802 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
1803 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1804
1805 struct radv_pipeline_key key;
1806 memset(&key, 0, sizeof(key));
1807
1808 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
1809 key.optimisations_disabled = 1;
1810
1811 key.has_multiview_view_index = has_view_index;
1812
1813 uint32_t binding_input_rate = 0;
1814 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
1815 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1816 if (input_state->pVertexBindingDescriptions[i].inputRate) {
1817 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
1818 binding_input_rate |= 1u << binding;
1819 instance_rate_divisors[binding] = 1;
1820 }
1821 }
1822 if (divisor_state) {
1823 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
1824 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
1825 divisor_state->pVertexBindingDivisors[i].divisor;
1826 }
1827 }
1828
1829 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1830 unsigned location = input_state->pVertexAttributeDescriptions[i].location;
1831 unsigned binding = input_state->pVertexAttributeDescriptions[i].binding;
1832 if (binding_input_rate & (1u << binding)) {
1833 key.instance_rate_inputs |= 1u << location;
1834 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
1835 }
1836
1837 if (pipeline->device->physical_device->rad_info.chip_class <= VI &&
1838 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
1839 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
1840 uint64_t adjust;
1841 switch(format) {
1842 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
1843 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
1844 adjust = RADV_ALPHA_ADJUST_SNORM;
1845 break;
1846 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
1847 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
1848 adjust = RADV_ALPHA_ADJUST_SSCALED;
1849 break;
1850 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
1851 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
1852 adjust = RADV_ALPHA_ADJUST_SINT;
1853 break;
1854 default:
1855 adjust = 0;
1856 break;
1857 }
1858 key.vertex_alpha_adjust |= adjust << (2 * location);
1859 }
1860 }
1861
1862 if (pCreateInfo->pTessellationState)
1863 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1864
1865
1866 if (pCreateInfo->pMultisampleState &&
1867 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1868 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1869 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1870 key.multisample = true;
1871 key.log2_num_samples = util_logbase2(num_samples);
1872 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1873 }
1874
1875 key.col_format = blend->spi_shader_col_format;
1876 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1877 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1878
1879 return key;
1880 }
1881
1882 static void
1883 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
1884 const struct radv_pipeline_key *key,
1885 nir_shader **nir)
1886 {
1887 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1888 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
1889 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i)
1890 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
1891
1892 if (nir[MESA_SHADER_TESS_CTRL]) {
1893 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1894 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
1895 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1896 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1897
1898 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1899 }
1900
1901 if (nir[MESA_SHADER_GEOMETRY]) {
1902 if (nir[MESA_SHADER_TESS_CTRL])
1903 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1904 else
1905 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1906 }
1907
1908 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1909 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1910
1911 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1912 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1913 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1914 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1915 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1916 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1917 }
1918
1919 static void
1920 merge_tess_info(struct shader_info *tes_info,
1921 const struct shader_info *tcs_info)
1922 {
1923 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1924 *
1925 * "PointMode. Controls generation of points rather than triangles
1926 * or lines. This functionality defaults to disabled, and is
1927 * enabled if either shader stage includes the execution mode.
1928 *
1929 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1930 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1931 * and OutputVertices, it says:
1932 *
1933 * "One mode must be set in at least one of the tessellation
1934 * shader stages."
1935 *
1936 * So, the fields can be set in either the TCS or TES, but they must
1937 * agree if set in both. Our backend looks at TES, so bitwise-or in
1938 * the values from the TCS.
1939 */
1940 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1941 tes_info->tess.tcs_vertices_out == 0 ||
1942 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1943 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1944
1945 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1946 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1947 tcs_info->tess.spacing == tes_info->tess.spacing);
1948 tes_info->tess.spacing |= tcs_info->tess.spacing;
1949
1950 assert(tcs_info->tess.primitive_mode == 0 ||
1951 tes_info->tess.primitive_mode == 0 ||
1952 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1953 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1954 tes_info->tess.ccw |= tcs_info->tess.ccw;
1955 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1956 }
1957
1958 static
1959 void radv_create_shaders(struct radv_pipeline *pipeline,
1960 struct radv_device *device,
1961 struct radv_pipeline_cache *cache,
1962 struct radv_pipeline_key key,
1963 const VkPipelineShaderStageCreateInfo **pStages,
1964 const VkPipelineCreateFlags flags)
1965 {
1966 struct radv_shader_module fs_m = {0};
1967 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1968 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1969 void *codes[MESA_SHADER_STAGES] = {0};
1970 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1971 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1972 unsigned char hash[20], gs_copy_hash[20];
1973
1974 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1975 if (pStages[i]) {
1976 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1977 if (modules[i]->nir)
1978 _mesa_sha1_compute(modules[i]->nir->info.name,
1979 strlen(modules[i]->nir->info.name),
1980 modules[i]->sha1);
1981
1982 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1983 }
1984 }
1985
1986 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1987 memcpy(gs_copy_hash, hash, 20);
1988 gs_copy_hash[0] ^= 1;
1989
1990 if (modules[MESA_SHADER_GEOMETRY]) {
1991 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1992 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1993 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1994 }
1995
1996 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1997 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1998 return;
1999 }
2000
2001 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2002 nir_builder fs_b;
2003 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2004 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2005 fs_m.nir = fs_b.shader;
2006 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2007 }
2008
2009 /* Determine first and last stage. */
2010 unsigned first = MESA_SHADER_STAGES;
2011 unsigned last = 0;
2012 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2013 if (!pStages[i])
2014 continue;
2015 if (first == MESA_SHADER_STAGES)
2016 first = i;
2017 last = i;
2018 }
2019
2020 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2021 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2022
2023 if (!modules[i])
2024 continue;
2025
2026 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2027 stage ? stage->pName : "main", i,
2028 stage ? stage->pSpecializationInfo : NULL,
2029 flags);
2030
2031 /* We don't want to alter meta shaders IR directly so clone it
2032 * first.
2033 */
2034 if (nir[i]->info.name) {
2035 nir[i] = nir_shader_clone(NULL, nir[i]);
2036 }
2037
2038 if (first != last) {
2039 nir_variable_mode mask = 0;
2040
2041 if (i != first)
2042 mask = mask | nir_var_shader_in;
2043
2044 if (i != last)
2045 mask = mask | nir_var_shader_out;
2046
2047 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) {
2048 nir_lower_io_to_scalar_early(nir[i], mask);
2049 radv_optimize_nir(nir[i], false);
2050 }
2051 }
2052 }
2053
2054 if (nir[MESA_SHADER_TESS_CTRL]) {
2055 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
2056 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2057 }
2058
2059 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2060 radv_link_shaders(pipeline, nir);
2061
2062 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2063 if (radv_can_dump_shader(device, modules[i], false))
2064 nir_print_shader(nir[i], stderr);
2065 }
2066
2067 radv_fill_shader_keys(keys, &key, nir);
2068
2069 if (nir[MESA_SHADER_FRAGMENT]) {
2070 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2071 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2072 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2073 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2074 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
2075 }
2076
2077 /* TODO: These are no longer used as keys we should refactor this */
2078 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
2079 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2080 keys[MESA_SHADER_VERTEX].vs.export_layer_id =
2081 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2082 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
2083 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2084 keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id =
2085 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2086 }
2087
2088 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2089 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2090 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2091 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2092 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2093 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2094 pipeline->layout,
2095 &key, &codes[MESA_SHADER_TESS_CTRL],
2096 &code_sizes[MESA_SHADER_TESS_CTRL]);
2097 }
2098 modules[MESA_SHADER_VERTEX] = NULL;
2099 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2100 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2101 }
2102
2103 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2104 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2105 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2106 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2107 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2108 pipeline->layout,
2109 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
2110 &code_sizes[MESA_SHADER_GEOMETRY]);
2111 }
2112 modules[pre_stage] = NULL;
2113 }
2114
2115 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2116 if(modules[i] && !pipeline->shaders[i]) {
2117 if (i == MESA_SHADER_TESS_CTRL) {
2118 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
2119 }
2120 if (i == MESA_SHADER_TESS_EVAL) {
2121 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2122 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2123 }
2124 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
2125 pipeline->layout,
2126 keys + i, &codes[i],
2127 &code_sizes[i]);
2128 }
2129 }
2130
2131 if(modules[MESA_SHADER_GEOMETRY]) {
2132 void *gs_copy_code = NULL;
2133 unsigned gs_copy_code_size = 0;
2134 if (!pipeline->gs_copy_shader) {
2135 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2136 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
2137 &gs_copy_code_size,
2138 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2139 }
2140
2141 if (pipeline->gs_copy_shader) {
2142 void *code[MESA_SHADER_STAGES] = {0};
2143 unsigned code_size[MESA_SHADER_STAGES] = {0};
2144 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2145
2146 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
2147 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
2148 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2149
2150 radv_pipeline_cache_insert_shaders(device, cache,
2151 gs_copy_hash,
2152 variants,
2153 (const void**)code,
2154 code_size);
2155 }
2156 free(gs_copy_code);
2157 }
2158
2159 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2160 (const void**)codes, code_sizes);
2161
2162 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2163 free(codes[i]);
2164 if (modules[i]) {
2165 if (!pipeline->device->keep_shader_info)
2166 ralloc_free(nir[i]);
2167
2168 if (radv_can_dump_shader_stats(device, modules[i]))
2169 radv_shader_dump_stats(device,
2170 pipeline->shaders[i],
2171 i, stderr);
2172 }
2173 }
2174
2175 if (fs_m.nir)
2176 ralloc_free(fs_m.nir);
2177 }
2178
2179 static uint32_t
2180 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2181 gl_shader_stage stage, enum chip_class chip_class)
2182 {
2183 bool has_gs = radv_pipeline_has_gs(pipeline);
2184 bool has_tess = radv_pipeline_has_tess(pipeline);
2185 switch (stage) {
2186 case MESA_SHADER_FRAGMENT:
2187 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2188 case MESA_SHADER_VERTEX:
2189 if (chip_class >= GFX9) {
2190 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2191 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2192 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2193 }
2194 if (has_tess)
2195 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2196 else
2197 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
2198 case MESA_SHADER_GEOMETRY:
2199 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2200 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2201 case MESA_SHADER_COMPUTE:
2202 return R_00B900_COMPUTE_USER_DATA_0;
2203 case MESA_SHADER_TESS_CTRL:
2204 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2205 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2206 case MESA_SHADER_TESS_EVAL:
2207 if (chip_class >= GFX9) {
2208 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2209 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2210 }
2211 if (has_gs)
2212 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2213 else
2214 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2215 default:
2216 unreachable("unknown shader");
2217 }
2218 }
2219
2220 struct radv_bin_size_entry {
2221 unsigned bpp;
2222 VkExtent2D extent;
2223 };
2224
2225 static VkExtent2D
2226 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2227 {
2228 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2229 {
2230 /* One RB / SE */
2231 {
2232 /* One shader engine */
2233 { 0, {128, 128}},
2234 { 1, { 64, 128}},
2235 { 2, { 32, 128}},
2236 { 3, { 16, 128}},
2237 { 17, { 0, 0}},
2238 { UINT_MAX, { 0, 0}},
2239 },
2240 {
2241 /* Two shader engines */
2242 { 0, {128, 128}},
2243 { 2, { 64, 128}},
2244 { 3, { 32, 128}},
2245 { 5, { 16, 128}},
2246 { 17, { 0, 0}},
2247 { UINT_MAX, { 0, 0}},
2248 },
2249 {
2250 /* Four shader engines */
2251 { 0, {128, 128}},
2252 { 3, { 64, 128}},
2253 { 5, { 16, 128}},
2254 { 17, { 0, 0}},
2255 { UINT_MAX, { 0, 0}},
2256 },
2257 },
2258 {
2259 /* Two RB / SE */
2260 {
2261 /* One shader engine */
2262 { 0, {128, 128}},
2263 { 2, { 64, 128}},
2264 { 3, { 32, 128}},
2265 { 5, { 16, 128}},
2266 { 33, { 0, 0}},
2267 { UINT_MAX, { 0, 0}},
2268 },
2269 {
2270 /* Two shader engines */
2271 { 0, {128, 128}},
2272 { 3, { 64, 128}},
2273 { 5, { 32, 128}},
2274 { 9, { 16, 128}},
2275 { 33, { 0, 0}},
2276 { UINT_MAX, { 0, 0}},
2277 },
2278 {
2279 /* Four shader engines */
2280 { 0, {256, 256}},
2281 { 2, {128, 256}},
2282 { 3, {128, 128}},
2283 { 5, { 64, 128}},
2284 { 9, { 16, 128}},
2285 { 33, { 0, 0}},
2286 { UINT_MAX, { 0, 0}},
2287 },
2288 },
2289 {
2290 /* Four RB / SE */
2291 {
2292 /* One shader engine */
2293 { 0, {128, 256}},
2294 { 2, {128, 128}},
2295 { 3, { 64, 128}},
2296 { 5, { 32, 128}},
2297 { 9, { 16, 128}},
2298 { 33, { 0, 0}},
2299 { UINT_MAX, { 0, 0}},
2300 },
2301 {
2302 /* Two shader engines */
2303 { 0, {256, 256}},
2304 { 2, {128, 256}},
2305 { 3, {128, 128}},
2306 { 5, { 64, 128}},
2307 { 9, { 32, 128}},
2308 { 17, { 16, 128}},
2309 { 33, { 0, 0}},
2310 { UINT_MAX, { 0, 0}},
2311 },
2312 {
2313 /* Four shader engines */
2314 { 0, {256, 512}},
2315 { 2, {256, 256}},
2316 { 3, {128, 256}},
2317 { 5, {128, 128}},
2318 { 9, { 64, 128}},
2319 { 17, { 16, 128}},
2320 { 33, { 0, 0}},
2321 { UINT_MAX, { 0, 0}},
2322 },
2323 },
2324 };
2325 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2326 {
2327 // One RB / SE
2328 {
2329 // One shader engine
2330 { 0, {128, 256}},
2331 { 2, {128, 128}},
2332 { 4, { 64, 128}},
2333 { 7, { 32, 128}},
2334 { 13, { 16, 128}},
2335 { 49, { 0, 0}},
2336 { UINT_MAX, { 0, 0}},
2337 },
2338 {
2339 // Two shader engines
2340 { 0, {256, 256}},
2341 { 2, {128, 256}},
2342 { 4, {128, 128}},
2343 { 7, { 64, 128}},
2344 { 13, { 32, 128}},
2345 { 25, { 16, 128}},
2346 { 49, { 0, 0}},
2347 { UINT_MAX, { 0, 0}},
2348 },
2349 {
2350 // Four shader engines
2351 { 0, {256, 512}},
2352 { 2, {256, 256}},
2353 { 4, {128, 256}},
2354 { 7, {128, 128}},
2355 { 13, { 64, 128}},
2356 { 25, { 16, 128}},
2357 { 49, { 0, 0}},
2358 { UINT_MAX, { 0, 0}},
2359 },
2360 },
2361 {
2362 // Two RB / SE
2363 {
2364 // One shader engine
2365 { 0, {256, 256}},
2366 { 2, {128, 256}},
2367 { 4, {128, 128}},
2368 { 7, { 64, 128}},
2369 { 13, { 32, 128}},
2370 { 25, { 16, 128}},
2371 { 97, { 0, 0}},
2372 { UINT_MAX, { 0, 0}},
2373 },
2374 {
2375 // Two shader engines
2376 { 0, {256, 512}},
2377 { 2, {256, 256}},
2378 { 4, {128, 256}},
2379 { 7, {128, 128}},
2380 { 13, { 64, 128}},
2381 { 25, { 32, 128}},
2382 { 49, { 16, 128}},
2383 { 97, { 0, 0}},
2384 { UINT_MAX, { 0, 0}},
2385 },
2386 {
2387 // Four shader engines
2388 { 0, {512, 512}},
2389 { 2, {256, 512}},
2390 { 4, {256, 256}},
2391 { 7, {128, 256}},
2392 { 13, {128, 128}},
2393 { 25, { 64, 128}},
2394 { 49, { 16, 128}},
2395 { 97, { 0, 0}},
2396 { UINT_MAX, { 0, 0}},
2397 },
2398 },
2399 {
2400 // Four RB / SE
2401 {
2402 // One shader engine
2403 { 0, {256, 512}},
2404 { 2, {256, 256}},
2405 { 4, {128, 256}},
2406 { 7, {128, 128}},
2407 { 13, { 64, 128}},
2408 { 25, { 32, 128}},
2409 { 49, { 16, 128}},
2410 { UINT_MAX, { 0, 0}},
2411 },
2412 {
2413 // Two shader engines
2414 { 0, {512, 512}},
2415 { 2, {256, 512}},
2416 { 4, {256, 256}},
2417 { 7, {128, 256}},
2418 { 13, {128, 128}},
2419 { 25, { 64, 128}},
2420 { 49, { 32, 128}},
2421 { 97, { 16, 128}},
2422 { UINT_MAX, { 0, 0}},
2423 },
2424 {
2425 // Four shader engines
2426 { 0, {512, 512}},
2427 { 4, {256, 512}},
2428 { 7, {256, 256}},
2429 { 13, {128, 256}},
2430 { 25, {128, 128}},
2431 { 49, { 64, 128}},
2432 { 97, { 16, 128}},
2433 { UINT_MAX, { 0, 0}},
2434 },
2435 },
2436 };
2437
2438 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2439 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2440 VkExtent2D extent = {512, 512};
2441
2442 unsigned log_num_rb_per_se =
2443 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2444 pipeline->device->physical_device->rad_info.max_se);
2445 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2446
2447 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2448 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2449 unsigned effective_samples = total_samples;
2450 unsigned color_bytes_per_pixel = 0;
2451
2452 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2453 if (vkblend) {
2454 for (unsigned i = 0; i < subpass->color_count; i++) {
2455 if (!vkblend->pAttachments[i].colorWriteMask)
2456 continue;
2457
2458 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2459 continue;
2460
2461 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2462 color_bytes_per_pixel += vk_format_get_blocksize(format);
2463 }
2464
2465 /* MSAA images typically don't use all samples all the time. */
2466 if (effective_samples >= 2 && ps_iter_samples <= 1)
2467 effective_samples = 2;
2468 color_bytes_per_pixel *= effective_samples;
2469 }
2470
2471 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2472 while(color_entry->bpp <= color_bytes_per_pixel)
2473 ++color_entry;
2474
2475 extent = color_entry->extent;
2476
2477 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2478 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2479
2480 /* Coefficients taken from AMDVLK */
2481 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2482 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2483 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2484
2485 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2486 while(ds_entry->bpp <= ds_bytes_per_pixel)
2487 ++ds_entry;
2488
2489 extent.width = MIN2(extent.width, ds_entry->extent.width);
2490 extent.height = MIN2(extent.height, ds_entry->extent.height);
2491 }
2492
2493 return extent;
2494 }
2495
2496 static void
2497 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2498 struct radv_pipeline *pipeline,
2499 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2500 {
2501 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2502 return;
2503
2504 uint32_t pa_sc_binner_cntl_0 =
2505 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2506 S_028C44_DISABLE_START_OF_PRIM(1);
2507 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2508
2509 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2510
2511 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2512 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2513 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2514
2515 switch (pipeline->device->physical_device->rad_info.family) {
2516 case CHIP_VEGA10:
2517 case CHIP_VEGA12:
2518 context_states_per_bin = 1;
2519 persistent_states_per_bin = 1;
2520 fpovs_per_batch = 63;
2521 break;
2522 case CHIP_RAVEN:
2523 context_states_per_bin = 6;
2524 persistent_states_per_bin = 32;
2525 fpovs_per_batch = 63;
2526 break;
2527 default:
2528 unreachable("unhandled family while determining binning state.");
2529 }
2530
2531 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2532 pa_sc_binner_cntl_0 =
2533 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2534 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2535 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2536 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2537 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2538 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2539 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2540 S_028C44_DISABLE_START_OF_PRIM(1) |
2541 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2542 S_028C44_OPTIMAL_BIN_SELECTION(1);
2543 }
2544
2545 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2546 pa_sc_binner_cntl_0);
2547 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2548 db_dfsm_control);
2549 }
2550
2551
2552 static void
2553 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2554 struct radv_pipeline *pipeline,
2555 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2556 const struct radv_graphics_pipeline_create_info *extra)
2557 {
2558 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2559 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2560 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2561 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2562 struct radv_render_pass_attachment *attachment = NULL;
2563 uint32_t db_depth_control = 0, db_stencil_control = 0;
2564 uint32_t db_render_control = 0, db_render_override2 = 0;
2565 uint32_t db_render_override = 0;
2566
2567 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2568 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2569
2570 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2571 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2572
2573 if (vkds && has_depth_attachment) {
2574 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2575 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2576 S_028800_ZFUNC(vkds->depthCompareOp) |
2577 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2578
2579 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2580 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2581 }
2582
2583 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2584 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2585 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2586 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2587 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2588 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2589
2590 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2591 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2592 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2593 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2594 }
2595
2596 if (attachment && extra) {
2597 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2598 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2599
2600 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2601 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2602 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2603 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2604 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2605 }
2606
2607 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2608 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2609
2610 if (pipeline->device->enabled_extensions.EXT_depth_range_unrestricted &&
2611 !pCreateInfo->pRasterizationState->depthClampEnable &&
2612 ps->info.info.ps.writes_z) {
2613 /* From VK_EXT_depth_range_unrestricted spec:
2614 *
2615 * "The behavior described in Primitive Clipping still applies.
2616 * If depth clamping is disabled the depth values are still
2617 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2618 * depth clamping is enabled the above equation is ignored and
2619 * the depth values are instead clamped to the VkViewport
2620 * minDepth and maxDepth values, which in the case of this
2621 * extension can be outside of the 0.0 to 1.0 range."
2622 */
2623 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2624 }
2625
2626 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2627 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2628
2629 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2630 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2631 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2632 }
2633
2634 static void
2635 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2636 struct radv_pipeline *pipeline,
2637 const struct radv_blend_state *blend)
2638 {
2639 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2640 radeon_emit_array(cs, blend->cb_blend_control,
2641 8);
2642 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2643 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2644
2645 if (pipeline->device->physical_device->has_rbplus) {
2646
2647 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2648 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2649 }
2650
2651 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2652
2653 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2654 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2655
2656 pipeline->graphics.col_format = blend->spi_shader_col_format;
2657 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
2658 }
2659
2660
2661 static void
2662 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2663 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2664 {
2665 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2666
2667 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2668 S_028810_PS_UCP_MODE(3) |
2669 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2670 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2671 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2672 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2673 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2674
2675 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2676 S_0286D4_FLAT_SHADE_ENA(1) |
2677 S_0286D4_PNT_SPRITE_ENA(1) |
2678 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2679 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2680 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2681 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2682 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2683
2684 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2685 S_028BE4_PIX_CENTER(1) | // TODO verify
2686 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2687 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2688
2689 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2690 S_028814_FACE(vkraster->frontFace) |
2691 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2692 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2693 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2694 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2695 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2696 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2697 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2698 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2699 }
2700
2701
2702 static void
2703 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2704 struct radv_pipeline *pipeline)
2705 {
2706 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2707
2708 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2709 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2710 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2711
2712 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2713 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2714
2715 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2716 uint32_t offset;
2717 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2718 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2719 if (loc->sgpr_idx == -1)
2720 return;
2721 assert(loc->num_sgprs == 1);
2722 assert(!loc->indirect);
2723 switch (pipeline->graphics.ms.num_samples) {
2724 default:
2725 offset = 0;
2726 break;
2727 case 2:
2728 offset = 1;
2729 break;
2730 case 4:
2731 offset = 3;
2732 break;
2733 case 8:
2734 offset = 7;
2735 break;
2736 case 16:
2737 offset = 15;
2738 break;
2739 }
2740
2741 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2742 }
2743 }
2744
2745 static void
2746 radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
2747 const struct radv_pipeline *pipeline)
2748 {
2749 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2750
2751 uint32_t vgt_primitiveid_en = false;
2752 uint32_t vgt_gs_mode = 0;
2753
2754 if (radv_pipeline_has_gs(pipeline)) {
2755 const struct radv_shader_variant *gs =
2756 pipeline->shaders[MESA_SHADER_GEOMETRY];
2757
2758 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2759 pipeline->device->physical_device->rad_info.chip_class);
2760 } else if (outinfo->export_prim_id) {
2761 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2762 vgt_primitiveid_en = true;
2763 }
2764
2765 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2766 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2767 }
2768
2769 static void
2770 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2771 struct radv_pipeline *pipeline,
2772 struct radv_shader_variant *shader)
2773 {
2774 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2775
2776 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2777 radeon_emit(cs, va >> 8);
2778 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
2779 radeon_emit(cs, shader->rsrc1);
2780 radeon_emit(cs, shader->rsrc2);
2781
2782 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2783 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2784 clip_dist_mask = outinfo->clip_dist_mask;
2785 cull_dist_mask = outinfo->cull_dist_mask;
2786 total_mask = clip_dist_mask | cull_dist_mask;
2787 bool misc_vec_ena = outinfo->writes_pointsize ||
2788 outinfo->writes_layer ||
2789 outinfo->writes_viewport_index;
2790
2791 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2792 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2793
2794 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2795 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2796 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2797 V_02870C_SPI_SHADER_4COMP :
2798 V_02870C_SPI_SHADER_NONE) |
2799 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2800 V_02870C_SPI_SHADER_4COMP :
2801 V_02870C_SPI_SHADER_NONE) |
2802 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2803 V_02870C_SPI_SHADER_4COMP :
2804 V_02870C_SPI_SHADER_NONE));
2805
2806 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2807 S_028818_VTX_W0_FMT(1) |
2808 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2809 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2810 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2811
2812 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2813 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2814 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2815 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2816 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2817 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2818 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2819 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2820 cull_dist_mask << 8 |
2821 clip_dist_mask);
2822
2823 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2824 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2825 outinfo->writes_viewport_index);
2826 }
2827
2828 static void
2829 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2830 struct radv_pipeline *pipeline,
2831 struct radv_shader_variant *shader)
2832 {
2833 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2834
2835 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2836 radeon_emit(cs, va >> 8);
2837 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
2838 radeon_emit(cs, shader->rsrc1);
2839 radeon_emit(cs, shader->rsrc2);
2840 }
2841
2842 static void
2843 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2844 struct radv_pipeline *pipeline,
2845 struct radv_shader_variant *shader,
2846 const struct radv_tessellation_state *tess)
2847 {
2848 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2849 uint32_t rsrc2 = shader->rsrc2;
2850
2851 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2852 radeon_emit(cs, va >> 8);
2853 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
2854
2855 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2856 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2857 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2858 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2859
2860 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2861 radeon_emit(cs, shader->rsrc1);
2862 radeon_emit(cs, rsrc2);
2863 }
2864
2865 static void
2866 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2867 struct radv_pipeline *pipeline,
2868 struct radv_shader_variant *shader,
2869 const struct radv_tessellation_state *tess)
2870 {
2871 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2872
2873 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2874 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2875 radeon_emit(cs, va >> 8);
2876 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
2877
2878 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2879 radeon_emit(cs, shader->rsrc1);
2880 radeon_emit(cs, shader->rsrc2 |
2881 S_00B42C_LDS_SIZE(tess->lds_size));
2882 } else {
2883 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2884 radeon_emit(cs, va >> 8);
2885 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
2886 radeon_emit(cs, shader->rsrc1);
2887 radeon_emit(cs, shader->rsrc2);
2888 }
2889 }
2890
2891 static void
2892 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2893 struct radv_pipeline *pipeline,
2894 const struct radv_tessellation_state *tess)
2895 {
2896 struct radv_shader_variant *vs;
2897
2898 /* Skip shaders merged into HS/GS */
2899 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2900 if (!vs)
2901 return;
2902
2903 if (vs->info.vs.as_ls)
2904 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2905 else if (vs->info.vs.as_es)
2906 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2907 else
2908 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2909 }
2910
2911 static void
2912 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2913 struct radv_pipeline *pipeline,
2914 const struct radv_tessellation_state *tess)
2915 {
2916 if (!radv_pipeline_has_tess(pipeline))
2917 return;
2918
2919 struct radv_shader_variant *tes, *tcs;
2920
2921 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2922 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2923
2924 if (tes) {
2925 if (tes->info.tes.as_es)
2926 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2927 else
2928 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2929 }
2930
2931 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2932
2933 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2934 tess->tf_param);
2935
2936 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2937 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2938 tess->ls_hs_config);
2939 else
2940 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2941 tess->ls_hs_config);
2942 }
2943
2944 static void
2945 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2946 struct radv_pipeline *pipeline,
2947 const struct radv_gs_state *gs_state)
2948 {
2949 struct radv_shader_variant *gs;
2950 uint64_t va;
2951
2952 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2953 if (!gs)
2954 return;
2955
2956 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2957
2958 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2959 radeon_emit(cs, gsvs_itemsize);
2960 radeon_emit(cs, gsvs_itemsize);
2961 radeon_emit(cs, gsvs_itemsize);
2962
2963 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2964
2965 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2966
2967 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2968 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2969 radeon_emit(cs, gs_vert_itemsize >> 2);
2970 radeon_emit(cs, 0);
2971 radeon_emit(cs, 0);
2972 radeon_emit(cs, 0);
2973
2974 uint32_t gs_num_invocations = gs->info.gs.invocations;
2975 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2976 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2977 S_028B90_ENABLE(gs_num_invocations > 0));
2978
2979 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2980 gs_state->vgt_esgs_ring_itemsize);
2981
2982 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2983
2984 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2985 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2986 radeon_emit(cs, va >> 8);
2987 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
2988
2989 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2990 radeon_emit(cs, gs->rsrc1);
2991 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
2992
2993 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
2994 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
2995 } else {
2996 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2997 radeon_emit(cs, va >> 8);
2998 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
2999 radeon_emit(cs, gs->rsrc1);
3000 radeon_emit(cs, gs->rsrc2);
3001 }
3002
3003 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
3004 }
3005
3006 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
3007 {
3008 uint32_t ps_input_cntl;
3009 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3010 ps_input_cntl = S_028644_OFFSET(offset);
3011 if (flat_shade)
3012 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3013 } else {
3014 /* The input is a DEFAULT_VAL constant. */
3015 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3016 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3017 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3018 ps_input_cntl = S_028644_OFFSET(0x20) |
3019 S_028644_DEFAULT_VAL(offset);
3020 }
3021 return ps_input_cntl;
3022 }
3023
3024 static void
3025 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
3026 struct radv_pipeline *pipeline)
3027 {
3028 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3029 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3030 uint32_t ps_input_cntl[32];
3031
3032 unsigned ps_offset = 0;
3033
3034 if (ps->info.info.ps.prim_id_input) {
3035 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
3036 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3037 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
3038 ++ps_offset;
3039 }
3040 }
3041
3042 if (ps->info.info.ps.layer_input ||
3043 ps->info.info.ps.uses_input_attachments ||
3044 ps->info.info.needs_multiview_view_index) {
3045 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
3046 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
3047 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
3048 else
3049 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
3050 ++ps_offset;
3051 }
3052
3053 if (ps->info.info.ps.has_pcoord) {
3054 unsigned val;
3055 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3056 ps_input_cntl[ps_offset] = val;
3057 ps_offset++;
3058 }
3059
3060 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
3061 unsigned vs_offset;
3062 bool flat_shade;
3063 if (!(ps->info.fs.input_mask & (1u << i)))
3064 continue;
3065
3066 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
3067 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
3068 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
3069 ++ps_offset;
3070 continue;
3071 }
3072
3073 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
3074
3075 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
3076 ++ps_offset;
3077 }
3078
3079 if (ps_offset) {
3080 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
3081 for (unsigned i = 0; i < ps_offset; i++) {
3082 radeon_emit(cs, ps_input_cntl[i]);
3083 }
3084 }
3085 }
3086
3087 static uint32_t
3088 radv_compute_db_shader_control(const struct radv_device *device,
3089 const struct radv_shader_variant *ps)
3090 {
3091 unsigned z_order;
3092 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
3093 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
3094 else
3095 z_order = V_02880C_LATE_Z;
3096
3097 bool disable_rbplus = device->physical_device->has_rbplus &&
3098 !device->physical_device->rbplus_allowed;
3099
3100 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
3101 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
3102 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
3103 S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
3104 S_02880C_Z_ORDER(z_order) |
3105 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
3106 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
3107 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
3108 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
3109 }
3110
3111 static void
3112 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
3113 struct radv_pipeline *pipeline)
3114 {
3115 struct radv_shader_variant *ps;
3116 uint64_t va;
3117 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
3118
3119 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3120 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
3121
3122 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
3123 radeon_emit(cs, va >> 8);
3124 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
3125 radeon_emit(cs, ps->rsrc1);
3126 radeon_emit(cs, ps->rsrc2);
3127
3128 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
3129 radv_compute_db_shader_control(pipeline->device, ps));
3130
3131 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
3132 ps->config.spi_ps_input_ena);
3133
3134 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
3135 ps->config.spi_ps_input_addr);
3136
3137 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
3138 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
3139
3140 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
3141
3142 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
3143 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
3144 ps->info.info.ps.writes_stencil,
3145 ps->info.info.ps.writes_sample_mask));
3146
3147 if (pipeline->device->dfsm_allowed) {
3148 /* optimise this? */
3149 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3150 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3151 }
3152 }
3153
3154 static void
3155 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
3156 struct radv_pipeline *pipeline)
3157 {
3158 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
3159 return;
3160
3161 unsigned vtx_reuse_depth = 30;
3162 if (radv_pipeline_has_tess(pipeline) &&
3163 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
3164 vtx_reuse_depth = 14;
3165 }
3166 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
3167 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
3168 }
3169
3170 static uint32_t
3171 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
3172 {
3173 uint32_t stages = 0;
3174 if (radv_pipeline_has_tess(pipeline)) {
3175 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3176 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3177
3178 if (radv_pipeline_has_gs(pipeline))
3179 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3180 S_028B54_GS_EN(1) |
3181 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3182 else
3183 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3184
3185 } else if (radv_pipeline_has_gs(pipeline))
3186 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3187 S_028B54_GS_EN(1) |
3188 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3189
3190 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
3191 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3192
3193 return stages;
3194 }
3195
3196 static uint32_t
3197 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
3198 {
3199 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
3200 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
3201
3202 if (!discard_rectangle_info)
3203 return 0xffff;
3204
3205 unsigned mask = 0;
3206
3207 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
3208 /* Interpret i as a bitmask, and then set the bit in the mask if
3209 * that combination of rectangles in which the pixel is contained
3210 * should pass the cliprect test. */
3211 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
3212
3213 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
3214 !relevant_subset)
3215 continue;
3216
3217 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
3218 relevant_subset)
3219 continue;
3220
3221 mask |= 1u << i;
3222 }
3223
3224 return mask;
3225 }
3226
3227 static void
3228 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
3229 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3230 const struct radv_graphics_pipeline_create_info *extra,
3231 const struct radv_blend_state *blend,
3232 const struct radv_tessellation_state *tess,
3233 const struct radv_gs_state *gs,
3234 unsigned prim, unsigned gs_out)
3235 {
3236 pipeline->cs.buf = malloc(4 * 256);
3237 pipeline->cs.max_dw = 256;
3238
3239 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
3240 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
3241 radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
3242 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
3243 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
3244 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
3245 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
3246 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs);
3247 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
3248 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
3249 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
3250 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
3251
3252 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
3253 S_0286E8_WAVES(pipeline->max_waves) |
3254 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3255
3256 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
3257
3258 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
3259 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
3260 } else {
3261 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
3262 }
3263 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
3264
3265 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
3266
3267 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3268 }
3269
3270 static struct radv_ia_multi_vgt_param_helpers
3271 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
3272 const struct radv_tessellation_state *tess,
3273 uint32_t prim)
3274 {
3275 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
3276 const struct radv_device *device = pipeline->device;
3277
3278 if (radv_pipeline_has_tess(pipeline))
3279 ia_multi_vgt_param.primgroup_size = tess->num_patches;
3280 else if (radv_pipeline_has_gs(pipeline))
3281 ia_multi_vgt_param.primgroup_size = 64;
3282 else
3283 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
3284
3285 ia_multi_vgt_param.partial_es_wave = false;
3286 if (pipeline->device->has_distributed_tess) {
3287 if (radv_pipeline_has_gs(pipeline)) {
3288 if (device->physical_device->rad_info.chip_class <= VI)
3289 ia_multi_vgt_param.partial_es_wave = true;
3290 }
3291 }
3292 /* GS requirement. */
3293 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= VI)
3294 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
3295 ia_multi_vgt_param.partial_es_wave = true;
3296
3297 ia_multi_vgt_param.wd_switch_on_eop = false;
3298 if (device->physical_device->rad_info.chip_class >= CIK) {
3299 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3300 * 4 shader engines. Set 1 to pass the assertion below.
3301 * The other cases are hardware requirements. */
3302 if (device->physical_device->rad_info.max_se < 4 ||
3303 prim == V_008958_DI_PT_POLYGON ||
3304 prim == V_008958_DI_PT_LINELOOP ||
3305 prim == V_008958_DI_PT_TRIFAN ||
3306 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3307 (pipeline->graphics.prim_restart_enable &&
3308 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3309 (prim != V_008958_DI_PT_POINTLIST &&
3310 prim != V_008958_DI_PT_LINESTRIP &&
3311 prim != V_008958_DI_PT_TRISTRIP))))
3312 ia_multi_vgt_param.wd_switch_on_eop = true;
3313 }
3314
3315 ia_multi_vgt_param.ia_switch_on_eoi = false;
3316 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
3317 ia_multi_vgt_param.ia_switch_on_eoi = true;
3318 if (radv_pipeline_has_gs(pipeline) &&
3319 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3320 ia_multi_vgt_param.ia_switch_on_eoi = true;
3321 if (radv_pipeline_has_tess(pipeline)) {
3322 /* SWITCH_ON_EOI must be set if PrimID is used. */
3323 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3324 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
3325 ia_multi_vgt_param.ia_switch_on_eoi = true;
3326 }
3327
3328 ia_multi_vgt_param.partial_vs_wave = false;
3329 if (radv_pipeline_has_tess(pipeline)) {
3330 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3331 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3332 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3333 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3334 radv_pipeline_has_gs(pipeline))
3335 ia_multi_vgt_param.partial_vs_wave = true;
3336 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3337 if (device->has_distributed_tess) {
3338 if (radv_pipeline_has_gs(pipeline)) {
3339 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3340 device->physical_device->rad_info.family == CHIP_FIJI ||
3341 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3342 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3343 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
3344 device->physical_device->rad_info.family == CHIP_VEGAM)
3345 ia_multi_vgt_param.partial_vs_wave = true;
3346 } else {
3347 ia_multi_vgt_param.partial_vs_wave = true;
3348 }
3349 }
3350 }
3351
3352 ia_multi_vgt_param.base =
3353 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3354 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3355 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3356 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3357 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3358
3359 return ia_multi_vgt_param;
3360 }
3361
3362
3363 static void
3364 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3365 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3366 {
3367 const VkPipelineVertexInputStateCreateInfo *vi_info =
3368 pCreateInfo->pVertexInputState;
3369 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3370
3371 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3372 const VkVertexInputAttributeDescription *desc =
3373 &vi_info->pVertexAttributeDescriptions[i];
3374 unsigned loc = desc->location;
3375 const struct vk_format_description *format_desc;
3376 int first_non_void;
3377 uint32_t num_format, data_format;
3378 format_desc = vk_format_description(desc->format);
3379 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3380
3381 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3382 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3383
3384 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3385 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3386 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3387 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3388 S_008F0C_NUM_FORMAT(num_format) |
3389 S_008F0C_DATA_FORMAT(data_format);
3390 velems->format_size[loc] = format_desc->block.bits / 8;
3391 velems->offset[loc] = desc->offset;
3392 velems->binding[loc] = desc->binding;
3393 velems->count = MAX2(velems->count, loc + 1);
3394 }
3395
3396 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3397 const VkVertexInputBindingDescription *desc =
3398 &vi_info->pVertexBindingDescriptions[i];
3399
3400 pipeline->binding_stride[desc->binding] = desc->stride;
3401 }
3402 }
3403
3404 static VkResult
3405 radv_pipeline_init(struct radv_pipeline *pipeline,
3406 struct radv_device *device,
3407 struct radv_pipeline_cache *cache,
3408 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3409 const struct radv_graphics_pipeline_create_info *extra,
3410 const VkAllocationCallbacks *alloc)
3411 {
3412 VkResult result;
3413 bool has_view_index = false;
3414
3415 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3416 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3417 if (subpass->view_mask)
3418 has_view_index = true;
3419 if (alloc == NULL)
3420 alloc = &device->alloc;
3421
3422 pipeline->device = device;
3423 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3424 assert(pipeline->layout);
3425
3426 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3427
3428 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3429 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3430 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3431 pStages[stage] = &pCreateInfo->pStages[i];
3432 }
3433
3434 radv_create_shaders(pipeline, device, cache,
3435 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
3436 pStages, pCreateInfo->flags);
3437
3438 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3439 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
3440 uint32_t gs_out;
3441 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3442
3443 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3444
3445 if (radv_pipeline_has_gs(pipeline)) {
3446 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3447 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3448 } else {
3449 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3450 }
3451 if (extra && extra->use_rectlist) {
3452 prim = V_008958_DI_PT_RECTLIST;
3453 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3454 pipeline->graphics.can_use_guardband = true;
3455 }
3456 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3457 /* prim vertex count will need TESS changes */
3458 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3459
3460 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3461
3462 /* Ensure that some export memory is always allocated, for two reasons:
3463 *
3464 * 1) Correctness: The hardware ignores the EXEC mask if no export
3465 * memory is allocated, so KILL and alpha test do not work correctly
3466 * without this.
3467 * 2) Performance: Every shader needs at least a NULL export, even when
3468 * it writes no color/depth output. The NULL export instruction
3469 * stalls without this setting.
3470 *
3471 * Don't add this to CB_SHADER_MASK.
3472 */
3473 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3474 if (!blend.spi_shader_col_format) {
3475 if (!ps->info.info.ps.writes_z &&
3476 !ps->info.info.ps.writes_stencil &&
3477 !ps->info.info.ps.writes_sample_mask)
3478 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3479 }
3480
3481 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3482 if (pipeline->shaders[i]) {
3483 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3484 }
3485 }
3486
3487 struct radv_gs_state gs = {0};
3488 if (radv_pipeline_has_gs(pipeline)) {
3489 gs = calculate_gs_info(pCreateInfo, pipeline);
3490 calculate_gs_ring_sizes(pipeline, &gs);
3491 }
3492
3493 struct radv_tessellation_state tess = {0};
3494 if (radv_pipeline_has_tess(pipeline)) {
3495 if (prim == V_008958_DI_PT_PATCH) {
3496 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3497 pipeline->graphics.prim_vertex_count.incr = 1;
3498 }
3499 tess = calculate_tess_state(pipeline, pCreateInfo);
3500 }
3501
3502 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3503
3504 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3505
3506 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3507 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3508
3509 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3510 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3511 if (loc->sgpr_idx != -1) {
3512 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3513 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3514 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id)
3515 pipeline->graphics.vtx_emit_num = 3;
3516 else
3517 pipeline->graphics.vtx_emit_num = 2;
3518 }
3519
3520 result = radv_pipeline_scratch_init(device, pipeline);
3521 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3522
3523 return result;
3524 }
3525
3526 VkResult
3527 radv_graphics_pipeline_create(
3528 VkDevice _device,
3529 VkPipelineCache _cache,
3530 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3531 const struct radv_graphics_pipeline_create_info *extra,
3532 const VkAllocationCallbacks *pAllocator,
3533 VkPipeline *pPipeline)
3534 {
3535 RADV_FROM_HANDLE(radv_device, device, _device);
3536 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3537 struct radv_pipeline *pipeline;
3538 VkResult result;
3539
3540 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3541 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3542 if (pipeline == NULL)
3543 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3544
3545 result = radv_pipeline_init(pipeline, device, cache,
3546 pCreateInfo, extra, pAllocator);
3547 if (result != VK_SUCCESS) {
3548 radv_pipeline_destroy(device, pipeline, pAllocator);
3549 return result;
3550 }
3551
3552 *pPipeline = radv_pipeline_to_handle(pipeline);
3553
3554 return VK_SUCCESS;
3555 }
3556
3557 VkResult radv_CreateGraphicsPipelines(
3558 VkDevice _device,
3559 VkPipelineCache pipelineCache,
3560 uint32_t count,
3561 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3562 const VkAllocationCallbacks* pAllocator,
3563 VkPipeline* pPipelines)
3564 {
3565 VkResult result = VK_SUCCESS;
3566 unsigned i = 0;
3567
3568 for (; i < count; i++) {
3569 VkResult r;
3570 r = radv_graphics_pipeline_create(_device,
3571 pipelineCache,
3572 &pCreateInfos[i],
3573 NULL, pAllocator, &pPipelines[i]);
3574 if (r != VK_SUCCESS) {
3575 result = r;
3576 pPipelines[i] = VK_NULL_HANDLE;
3577 }
3578 }
3579
3580 return result;
3581 }
3582
3583
3584 static void
3585 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3586 {
3587 struct radv_shader_variant *compute_shader;
3588 struct radv_device *device = pipeline->device;
3589 unsigned compute_resource_limits;
3590 unsigned waves_per_threadgroup;
3591 uint64_t va;
3592
3593 pipeline->cs.buf = malloc(20 * 4);
3594 pipeline->cs.max_dw = 20;
3595
3596 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3597 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3598
3599 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3600 radeon_emit(&pipeline->cs, va >> 8);
3601 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
3602
3603 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3604 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3605 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3606
3607 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3608 S_00B860_WAVES(pipeline->max_waves) |
3609 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3610
3611 /* Calculate best compute resource limits. */
3612 waves_per_threadgroup =
3613 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3614 compute_shader->info.cs.block_size[1] *
3615 compute_shader->info.cs.block_size[2], 64);
3616 compute_resource_limits =
3617 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3618
3619 if (device->physical_device->rad_info.chip_class >= CIK) {
3620 unsigned num_cu_per_se =
3621 device->physical_device->rad_info.num_good_compute_units /
3622 device->physical_device->rad_info.max_se;
3623
3624 /* Force even distribution on all SIMDs in CU if the workgroup
3625 * size is 64. This has shown some good improvements if # of
3626 * CUs per SE is not a multiple of 4.
3627 */
3628 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3629 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3630 }
3631
3632 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3633 compute_resource_limits);
3634
3635 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3636 radeon_emit(&pipeline->cs,
3637 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3638 radeon_emit(&pipeline->cs,
3639 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3640 radeon_emit(&pipeline->cs,
3641 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3642
3643 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3644 }
3645
3646 static VkResult radv_compute_pipeline_create(
3647 VkDevice _device,
3648 VkPipelineCache _cache,
3649 const VkComputePipelineCreateInfo* pCreateInfo,
3650 const VkAllocationCallbacks* pAllocator,
3651 VkPipeline* pPipeline)
3652 {
3653 RADV_FROM_HANDLE(radv_device, device, _device);
3654 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3655 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3656 struct radv_pipeline *pipeline;
3657 VkResult result;
3658
3659 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3660 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3661 if (pipeline == NULL)
3662 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3663
3664 pipeline->device = device;
3665 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3666 assert(pipeline->layout);
3667
3668 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3669 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags);
3670
3671 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3672 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3673 result = radv_pipeline_scratch_init(device, pipeline);
3674 if (result != VK_SUCCESS) {
3675 radv_pipeline_destroy(device, pipeline, pAllocator);
3676 return result;
3677 }
3678
3679 radv_compute_generate_pm4(pipeline);
3680
3681 *pPipeline = radv_pipeline_to_handle(pipeline);
3682
3683 return VK_SUCCESS;
3684 }
3685
3686 VkResult radv_CreateComputePipelines(
3687 VkDevice _device,
3688 VkPipelineCache pipelineCache,
3689 uint32_t count,
3690 const VkComputePipelineCreateInfo* pCreateInfos,
3691 const VkAllocationCallbacks* pAllocator,
3692 VkPipeline* pPipelines)
3693 {
3694 VkResult result = VK_SUCCESS;
3695
3696 unsigned i = 0;
3697 for (; i < count; i++) {
3698 VkResult r;
3699 r = radv_compute_pipeline_create(_device, pipelineCache,
3700 &pCreateInfos[i],
3701 pAllocator, &pPipelines[i]);
3702 if (r != VK_SUCCESS) {
3703 result = r;
3704 pPipelines[i] = VK_NULL_HANDLE;
3705 }
3706 }
3707
3708 return result;
3709 }