2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_private.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
35 #include <llvm-c/Core.h>
36 #include <llvm-c/TargetMachine.h>
40 #include "r600d_common.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_nir_to_llvm.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
48 void radv_shader_variant_destroy(struct radv_device
*device
,
49 struct radv_shader_variant
*variant
);
51 static const struct nir_shader_compiler_options nir_options
= {
52 .vertex_id_zero_based
= true,
58 .lower_pack_snorm_2x16
= true,
59 .lower_pack_snorm_4x8
= true,
60 .lower_pack_unorm_2x16
= true,
61 .lower_pack_unorm_4x8
= true,
62 .lower_unpack_snorm_2x16
= true,
63 .lower_unpack_snorm_4x8
= true,
64 .lower_unpack_unorm_2x16
= true,
65 .lower_unpack_unorm_4x8
= true,
66 .lower_extract_byte
= true,
67 .lower_extract_word
= true,
68 .max_unroll_iterations
= 32
71 VkResult
radv_CreateShaderModule(
73 const VkShaderModuleCreateInfo
* pCreateInfo
,
74 const VkAllocationCallbacks
* pAllocator
,
75 VkShaderModule
* pShaderModule
)
77 RADV_FROM_HANDLE(radv_device
, device
, _device
);
78 struct radv_shader_module
*module
;
80 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
81 assert(pCreateInfo
->flags
== 0);
83 module
= vk_alloc2(&device
->alloc
, pAllocator
,
84 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
85 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
87 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
90 module
->size
= pCreateInfo
->codeSize
;
91 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
93 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
95 *pShaderModule
= radv_shader_module_to_handle(module
);
100 void radv_DestroyShaderModule(
102 VkShaderModule _module
,
103 const VkAllocationCallbacks
* pAllocator
)
105 RADV_FROM_HANDLE(radv_device
, device
, _device
);
106 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
111 vk_free2(&device
->alloc
, pAllocator
, module
);
116 radv_pipeline_destroy(struct radv_device
*device
,
117 struct radv_pipeline
*pipeline
,
118 const VkAllocationCallbacks
* allocator
)
120 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
121 if (pipeline
->shaders
[i
])
122 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
124 if (pipeline
->gs_copy_shader
)
125 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
127 vk_free2(&device
->alloc
, allocator
, pipeline
);
130 void radv_DestroyPipeline(
132 VkPipeline _pipeline
,
133 const VkAllocationCallbacks
* pAllocator
)
135 RADV_FROM_HANDLE(radv_device
, device
, _device
);
136 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
141 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
146 radv_optimize_nir(struct nir_shader
*shader
)
153 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
154 NIR_PASS_V(shader
, nir_lower_64bit_pack
);
155 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
156 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
158 NIR_PASS(progress
, shader
, nir_copy_prop
);
159 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
160 NIR_PASS(progress
, shader
, nir_opt_dce
);
161 if (nir_opt_trivial_continues(shader
)) {
163 NIR_PASS(progress
, shader
, nir_copy_prop
);
164 NIR_PASS(progress
, shader
, nir_opt_dce
);
166 NIR_PASS(progress
, shader
, nir_opt_if
);
167 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
168 NIR_PASS(progress
, shader
, nir_opt_cse
);
169 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8);
170 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
171 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
172 NIR_PASS(progress
, shader
, nir_opt_undef
);
173 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
174 if (shader
->options
->max_unroll_iterations
) {
175 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
181 radv_shader_compile_to_nir(struct radv_device
*device
,
182 struct radv_shader_module
*module
,
183 const char *entrypoint_name
,
184 gl_shader_stage stage
,
185 const VkSpecializationInfo
*spec_info
,
188 if (strcmp(entrypoint_name
, "main") != 0) {
189 radv_finishme("Multiple shaders per module not really supported");
193 nir_function
*entry_point
;
195 /* Some things such as our meta clear/blit code will give us a NIR
196 * shader directly. In that case, we just ignore the SPIR-V entirely
197 * and just use the NIR shader */
199 nir
->options
= &nir_options
;
200 nir_validate_shader(nir
);
202 assert(exec_list_length(&nir
->functions
) == 1);
203 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
204 entry_point
= exec_node_data(nir_function
, node
, node
);
206 uint32_t *spirv
= (uint32_t *) module
->data
;
207 assert(module
->size
% 4 == 0);
209 uint32_t num_spec_entries
= 0;
210 struct nir_spirv_specialization
*spec_entries
= NULL
;
211 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
212 num_spec_entries
= spec_info
->mapEntryCount
;
213 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
214 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
215 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
216 const void *data
= spec_info
->pData
+ entry
.offset
;
217 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
219 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
220 if (spec_info
->dataSize
== 8)
221 spec_entries
[i
].data64
= *(const uint64_t *)data
;
223 spec_entries
[i
].data32
= *(const uint32_t *)data
;
226 const struct nir_spirv_supported_extensions supported_ext
= {
227 .draw_parameters
= true,
229 .image_read_without_format
= true,
230 .image_write_without_format
= true,
231 .tessellation
= true,
233 .variable_pointers
= true,
235 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
236 spec_entries
, num_spec_entries
,
237 stage
, entrypoint_name
, &supported_ext
, &nir_options
);
238 nir
= entry_point
->shader
;
239 assert(nir
->stage
== stage
);
240 nir_validate_shader(nir
);
244 /* We have to lower away local constant initializers right before we
245 * inline functions. That way they get properly initialized at the top
246 * of the function and not at the top of its caller.
248 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
249 NIR_PASS_V(nir
, nir_lower_returns
);
250 NIR_PASS_V(nir
, nir_inline_functions
);
252 /* Pick off the single entrypoint that we want */
253 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
254 if (func
!= entry_point
)
255 exec_node_remove(&func
->node
);
257 assert(exec_list_length(&nir
->functions
) == 1);
258 entry_point
->name
= ralloc_strdup(entry_point
, "main");
260 NIR_PASS_V(nir
, nir_remove_dead_variables
,
261 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
263 /* Now that we've deleted all but the main function, we can go ahead and
264 * lower the rest of the constant initializers.
266 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
267 NIR_PASS_V(nir
, nir_lower_system_values
);
268 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
271 /* Vulkan uses the separate-shader linking model */
272 nir
->info
.separate_shader
= true;
274 nir_shader_gather_info(nir
, entry_point
->impl
);
276 nir_variable_mode indirect_mask
= 0;
277 indirect_mask
|= nir_var_shader_in
;
278 indirect_mask
|= nir_var_local
;
280 nir_lower_indirect_derefs(nir
, indirect_mask
);
282 static const nir_lower_tex_options tex_options
= {
286 nir_lower_tex(nir
, &tex_options
);
288 nir_lower_vars_to_ssa(nir
);
289 nir_lower_var_copies(nir
);
290 nir_lower_global_vars_to_local(nir
);
291 nir_remove_dead_variables(nir
, nir_var_local
);
292 radv_optimize_nir(nir
);
295 nir_print_shader(nir
, stderr
);
300 static const char *radv_get_shader_name(struct radv_shader_variant
*var
,
301 gl_shader_stage stage
)
304 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
305 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
306 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
307 case MESA_SHADER_COMPUTE
: return "Compute Shader";
308 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
309 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
311 return "Unknown shader";
315 static void radv_dump_pipeline_stats(struct radv_device
*device
, struct radv_pipeline
*pipeline
)
317 unsigned lds_increment
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
318 struct radv_shader_variant
*var
;
319 struct ac_shader_config
*conf
;
322 unsigned max_simd_waves
= 10;
323 unsigned lds_per_wave
= 0;
325 for (i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
326 if (!pipeline
->shaders
[i
])
328 var
= pipeline
->shaders
[i
];
332 if (i
== MESA_SHADER_FRAGMENT
) {
333 lds_per_wave
= conf
->lds_size
* lds_increment
+
334 align(var
->info
.fs
.num_interp
* 48, lds_increment
);
337 if (conf
->num_sgprs
) {
338 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
339 max_simd_waves
= MIN2(max_simd_waves
, 800 / conf
->num_sgprs
);
341 max_simd_waves
= MIN2(max_simd_waves
, 512 / conf
->num_sgprs
);
345 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
347 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
351 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
353 fprintf(file
, "\n%s:\n",
354 radv_get_shader_name(var
, i
));
355 if (i
== MESA_SHADER_FRAGMENT
) {
356 fprintf(file
, "*** SHADER CONFIG ***\n"
357 "SPI_PS_INPUT_ADDR = 0x%04x\n"
358 "SPI_PS_INPUT_ENA = 0x%04x\n",
359 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
361 fprintf(file
, "*** SHADER STATS ***\n"
364 "Spilled SGPRs: %d\n"
365 "Spilled VGPRs: %d\n"
366 "Code Size: %d bytes\n"
368 "Scratch: %d bytes per wave\n"
370 "********************\n\n\n",
371 conf
->num_sgprs
, conf
->num_vgprs
,
372 conf
->spilled_sgprs
, conf
->spilled_vgprs
, var
->code_size
,
373 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
378 void radv_shader_variant_destroy(struct radv_device
*device
,
379 struct radv_shader_variant
*variant
)
381 if (!p_atomic_dec_zero(&variant
->ref_count
))
384 mtx_lock(&device
->shader_slab_mutex
);
385 list_del(&variant
->slab_list
);
386 mtx_unlock(&device
->shader_slab_mutex
);
391 static void radv_fill_shader_variant(struct radv_device
*device
,
392 struct radv_shader_variant
*variant
,
393 struct ac_shader_binary
*binary
,
394 gl_shader_stage stage
)
396 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
397 unsigned vgpr_comp_cnt
= 0;
399 if (scratch_enabled
&& !device
->llvm_supports_spill
)
400 radv_finishme("shader scratch support only available with LLVM 4.0");
402 variant
->code_size
= binary
->code_size
;
403 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
404 S_00B12C_SCRATCH_EN(scratch_enabled
);
407 case MESA_SHADER_TESS_EVAL
:
410 case MESA_SHADER_TESS_CTRL
:
411 variant
->rsrc2
|= S_00B42C_OC_LDS_EN(1);
413 case MESA_SHADER_VERTEX
:
414 case MESA_SHADER_GEOMETRY
:
415 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
417 case MESA_SHADER_FRAGMENT
:
419 case MESA_SHADER_COMPUTE
:
421 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
422 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
423 S_00B84C_TG_SIZE_EN(1) |
424 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
427 unreachable("unsupported shader type");
431 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
432 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
433 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
434 S_00B848_DX10_CLAMP(1) |
435 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
437 void *ptr
= radv_alloc_shader_memory(device
, variant
);
438 memcpy(ptr
, binary
->code
, binary
->code_size
);
441 static struct radv_shader_variant
*radv_shader_variant_create(struct radv_device
*device
,
442 struct nir_shader
*shader
,
443 struct radv_pipeline_layout
*layout
,
444 const union ac_shader_variant_key
*key
,
446 unsigned *code_size_out
,
449 struct radv_shader_variant
*variant
= calloc(1, sizeof(struct radv_shader_variant
));
450 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
451 LLVMTargetMachineRef tm
;
455 struct ac_nir_compiler_options options
= {0};
456 options
.layout
= layout
;
460 struct ac_shader_binary binary
;
461 enum ac_target_machine_options tm_options
= 0;
462 options
.unsafe_math
= !!(device
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
463 options
.family
= chip_family
;
464 options
.chip_class
= device
->physical_device
->rad_info
.chip_class
;
465 options
.supports_spill
= device
->llvm_supports_spill
;
466 if (options
.supports_spill
)
467 tm_options
|= AC_TM_SUPPORTS_SPILL
;
468 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
469 tm_options
|= AC_TM_SISCHED
;
470 tm
= ac_create_target_machine(chip_family
, tm_options
);
471 ac_compile_nir_shader(tm
, &binary
, &variant
->config
,
472 &variant
->info
, shader
, &options
, dump
);
473 LLVMDisposeTargetMachine(tm
);
475 radv_fill_shader_variant(device
, variant
, &binary
, shader
->stage
);
478 *code_out
= binary
.code
;
479 *code_size_out
= binary
.code_size
;
484 free(binary
.global_symbol_offsets
);
486 free(binary
.disasm_string
);
487 variant
->ref_count
= 1;
491 static struct radv_shader_variant
*
492 radv_pipeline_create_gs_copy_shader(struct radv_pipeline
*pipeline
,
493 struct nir_shader
*nir
,
495 unsigned *code_size_out
,
498 struct radv_shader_variant
*variant
= calloc(1, sizeof(struct radv_shader_variant
));
499 enum radeon_family chip_family
= pipeline
->device
->physical_device
->rad_info
.family
;
500 LLVMTargetMachineRef tm
;
504 struct ac_nir_compiler_options options
= {0};
505 struct ac_shader_binary binary
;
506 enum ac_target_machine_options tm_options
= 0;
507 options
.family
= chip_family
;
508 options
.chip_class
= pipeline
->device
->physical_device
->rad_info
.chip_class
;
509 if (options
.supports_spill
)
510 tm_options
|= AC_TM_SUPPORTS_SPILL
;
511 if (pipeline
->device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
512 tm_options
|= AC_TM_SISCHED
;
513 tm
= ac_create_target_machine(chip_family
, tm_options
);
514 ac_create_gs_copy_shader(tm
, nir
, &binary
, &variant
->config
, &variant
->info
, &options
, dump_shader
);
515 LLVMDisposeTargetMachine(tm
);
517 radv_fill_shader_variant(pipeline
->device
, variant
, &binary
, MESA_SHADER_VERTEX
);
520 *code_out
= binary
.code
;
521 *code_size_out
= binary
.code_size
;
526 free(binary
.global_symbol_offsets
);
528 free(binary
.disasm_string
);
529 variant
->ref_count
= 1;
533 static struct radv_shader_variant
*
534 radv_pipeline_compile(struct radv_pipeline
*pipeline
,
535 struct radv_pipeline_cache
*cache
,
536 struct radv_shader_module
*module
,
537 const char *entrypoint
,
538 gl_shader_stage stage
,
539 const VkSpecializationInfo
*spec_info
,
540 struct radv_pipeline_layout
*layout
,
541 const union ac_shader_variant_key
*key
)
543 unsigned char sha1
[20];
544 unsigned char gs_copy_sha1
[20];
545 struct radv_shader_variant
*variant
;
548 unsigned code_size
= 0;
549 bool dump
= (pipeline
->device
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
);
552 _mesa_sha1_compute(module
->nir
->info
.name
,
553 strlen(module
->nir
->info
.name
),
556 radv_hash_shader(sha1
, module
, entrypoint
, spec_info
, layout
, key
, 0);
557 if (stage
== MESA_SHADER_GEOMETRY
)
558 radv_hash_shader(gs_copy_sha1
, module
, entrypoint
, spec_info
,
561 variant
= radv_create_shader_variant_from_pipeline_cache(pipeline
->device
,
565 if (stage
== MESA_SHADER_GEOMETRY
) {
566 pipeline
->gs_copy_shader
=
567 radv_create_shader_variant_from_pipeline_cache(
574 (stage
!= MESA_SHADER_GEOMETRY
|| pipeline
->gs_copy_shader
))
577 nir
= radv_shader_compile_to_nir(pipeline
->device
,
578 module
, entrypoint
, stage
,
584 variant
= radv_shader_variant_create(pipeline
->device
, nir
,
589 if (stage
== MESA_SHADER_GEOMETRY
&& !pipeline
->gs_copy_shader
) {
590 void *gs_copy_code
= NULL
;
591 unsigned gs_copy_code_size
= 0;
592 pipeline
->gs_copy_shader
= radv_pipeline_create_gs_copy_shader(
593 pipeline
, nir
, &gs_copy_code
, &gs_copy_code_size
, dump
);
595 if (pipeline
->gs_copy_shader
) {
596 pipeline
->gs_copy_shader
=
597 radv_pipeline_cache_insert_shader(cache
,
599 pipeline
->gs_copy_shader
,
608 variant
= radv_pipeline_cache_insert_shader(cache
, sha1
, variant
,
616 static union ac_shader_variant_key
617 radv_compute_tes_key(bool as_es
, bool export_prim_id
)
619 union ac_shader_variant_key key
;
620 memset(&key
, 0, sizeof(key
));
621 key
.tes
.as_es
= as_es
;
622 /* export prim id only happens when no geom shader */
624 key
.tes
.export_prim_id
= export_prim_id
;
628 static union ac_shader_variant_key
629 radv_compute_tcs_key(unsigned primitive_mode
, unsigned input_vertices
)
631 union ac_shader_variant_key key
;
632 memset(&key
, 0, sizeof(key
));
633 key
.tcs
.primitive_mode
= primitive_mode
;
634 key
.tcs
.input_vertices
= input_vertices
;
639 radv_tess_pipeline_compile(struct radv_pipeline
*pipeline
,
640 struct radv_pipeline_cache
*cache
,
641 struct radv_shader_module
*tcs_module
,
642 struct radv_shader_module
*tes_module
,
643 const char *tcs_entrypoint
,
644 const char *tes_entrypoint
,
645 const VkSpecializationInfo
*tcs_spec_info
,
646 const VkSpecializationInfo
*tes_spec_info
,
647 struct radv_pipeline_layout
*layout
,
648 unsigned input_vertices
)
650 unsigned char tcs_sha1
[20], tes_sha1
[20];
651 struct radv_shader_variant
*tes_variant
= NULL
, *tcs_variant
= NULL
;
652 nir_shader
*tes_nir
, *tcs_nir
;
653 void *tes_code
= NULL
, *tcs_code
= NULL
;
654 unsigned tes_code_size
= 0, tcs_code_size
= 0;
655 union ac_shader_variant_key tes_key
;
656 union ac_shader_variant_key tcs_key
;
657 bool dump
= (pipeline
->device
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
);
659 tes_key
= radv_compute_tes_key(radv_pipeline_has_gs(pipeline
),
660 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.fs
.prim_id_input
);
662 _mesa_sha1_compute(tes_module
->nir
->info
.name
,
663 strlen(tes_module
->nir
->info
.name
),
665 radv_hash_shader(tes_sha1
, tes_module
, tes_entrypoint
, tes_spec_info
, layout
, &tes_key
, 0);
667 tes_variant
= radv_create_shader_variant_from_pipeline_cache(pipeline
->device
,
672 tcs_key
= radv_compute_tcs_key(tes_variant
->info
.tes
.primitive_mode
, input_vertices
);
675 _mesa_sha1_compute(tcs_module
->nir
->info
.name
,
676 strlen(tcs_module
->nir
->info
.name
),
679 radv_hash_shader(tcs_sha1
, tcs_module
, tcs_entrypoint
, tcs_spec_info
, layout
, &tcs_key
, 0);
681 tcs_variant
= radv_create_shader_variant_from_pipeline_cache(pipeline
->device
,
686 if (tcs_variant
&& tes_variant
) {
687 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = tcs_variant
;
688 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] = tes_variant
;
692 tes_nir
= radv_shader_compile_to_nir(pipeline
->device
,
693 tes_module
, tes_entrypoint
, MESA_SHADER_TESS_EVAL
,
694 tes_spec_info
, dump
);
698 tcs_nir
= radv_shader_compile_to_nir(pipeline
->device
,
699 tcs_module
, tcs_entrypoint
, MESA_SHADER_TESS_CTRL
,
700 tcs_spec_info
, dump
);
704 nir_lower_tes_patch_vertices(tes_nir
,
705 tcs_nir
->info
.tess
.tcs_vertices_out
);
707 tes_variant
= radv_shader_variant_create(pipeline
->device
, tes_nir
,
708 layout
, &tes_key
, &tes_code
,
709 &tes_code_size
, dump
);
711 tcs_key
= radv_compute_tcs_key(tes_nir
->info
.tess
.primitive_mode
, input_vertices
);
713 _mesa_sha1_compute(tcs_module
->nir
->info
.name
,
714 strlen(tcs_module
->nir
->info
.name
),
717 radv_hash_shader(tcs_sha1
, tcs_module
, tcs_entrypoint
, tcs_spec_info
, layout
, &tcs_key
, 0);
719 tcs_variant
= radv_shader_variant_create(pipeline
->device
, tcs_nir
,
720 layout
, &tcs_key
, &tcs_code
,
721 &tcs_code_size
, dump
);
723 if (!tes_module
->nir
)
724 ralloc_free(tes_nir
);
726 if (!tcs_module
->nir
)
727 ralloc_free(tcs_nir
);
730 tes_variant
= radv_pipeline_cache_insert_shader(cache
, tes_sha1
, tes_variant
,
731 tes_code
, tes_code_size
);
734 tcs_variant
= radv_pipeline_cache_insert_shader(cache
, tcs_sha1
, tcs_variant
,
735 tcs_code
, tcs_code_size
);
741 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = tcs_variant
;
742 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] = tes_variant
;
747 radv_pipeline_scratch_init(struct radv_device
*device
,
748 struct radv_pipeline
*pipeline
)
750 unsigned scratch_bytes_per_wave
= 0;
751 unsigned max_waves
= 0;
752 unsigned min_waves
= 1;
754 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
755 if (pipeline
->shaders
[i
]) {
756 unsigned max_stage_waves
= device
->scratch_waves
;
758 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
759 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
761 max_stage_waves
= MIN2(max_stage_waves
,
762 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
763 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
764 max_waves
= MAX2(max_waves
, max_stage_waves
);
768 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
769 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
770 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
771 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
772 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
775 if (scratch_bytes_per_wave
)
776 max_waves
= MIN2(max_waves
, 0xffffffffu
/ scratch_bytes_per_wave
);
778 if (scratch_bytes_per_wave
&& max_waves
< min_waves
) {
779 /* Not really true at this moment, but will be true on first
780 * execution. Avoid having hanging shaders. */
781 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
783 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
784 pipeline
->max_waves
= max_waves
;
788 static uint32_t si_translate_blend_function(VkBlendOp op
)
791 case VK_BLEND_OP_ADD
:
792 return V_028780_COMB_DST_PLUS_SRC
;
793 case VK_BLEND_OP_SUBTRACT
:
794 return V_028780_COMB_SRC_MINUS_DST
;
795 case VK_BLEND_OP_REVERSE_SUBTRACT
:
796 return V_028780_COMB_DST_MINUS_SRC
;
797 case VK_BLEND_OP_MIN
:
798 return V_028780_COMB_MIN_DST_SRC
;
799 case VK_BLEND_OP_MAX
:
800 return V_028780_COMB_MAX_DST_SRC
;
806 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
809 case VK_BLEND_FACTOR_ZERO
:
810 return V_028780_BLEND_ZERO
;
811 case VK_BLEND_FACTOR_ONE
:
812 return V_028780_BLEND_ONE
;
813 case VK_BLEND_FACTOR_SRC_COLOR
:
814 return V_028780_BLEND_SRC_COLOR
;
815 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
816 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
817 case VK_BLEND_FACTOR_DST_COLOR
:
818 return V_028780_BLEND_DST_COLOR
;
819 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
820 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
821 case VK_BLEND_FACTOR_SRC_ALPHA
:
822 return V_028780_BLEND_SRC_ALPHA
;
823 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
824 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
825 case VK_BLEND_FACTOR_DST_ALPHA
:
826 return V_028780_BLEND_DST_ALPHA
;
827 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
828 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
829 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
830 return V_028780_BLEND_CONSTANT_COLOR
;
831 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
832 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
833 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
834 return V_028780_BLEND_CONSTANT_ALPHA
;
835 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
836 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
837 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
838 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
839 case VK_BLEND_FACTOR_SRC1_COLOR
:
840 return V_028780_BLEND_SRC1_COLOR
;
841 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
842 return V_028780_BLEND_INV_SRC1_COLOR
;
843 case VK_BLEND_FACTOR_SRC1_ALPHA
:
844 return V_028780_BLEND_SRC1_ALPHA
;
845 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
846 return V_028780_BLEND_INV_SRC1_ALPHA
;
852 static bool is_dual_src(VkBlendFactor factor
)
855 case VK_BLEND_FACTOR_SRC1_COLOR
:
856 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
857 case VK_BLEND_FACTOR_SRC1_ALPHA
:
858 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
865 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
867 bool blend_need_alpha
)
869 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
870 unsigned format
, ntype
, swap
;
872 /* Alpha is needed for alpha-to-coverage.
873 * Blending may be with or without alpha.
875 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
876 unsigned alpha
= 0; /* exports alpha, but may not support blending */
877 unsigned blend
= 0; /* supports blending, but may not export alpha */
878 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
880 format
= radv_translate_colorformat(vk_format
);
881 ntype
= radv_translate_color_numformat(vk_format
, desc
,
882 vk_format_get_first_non_void_channel(vk_format
));
883 swap
= radv_translate_colorswap(vk_format
, false);
885 /* Choose the SPI color formats. These are required values for Stoney/RB+.
886 * Other chips have multiple choices, though they are not necessarily better.
889 case V_028C70_COLOR_5_6_5
:
890 case V_028C70_COLOR_1_5_5_5
:
891 case V_028C70_COLOR_5_5_5_1
:
892 case V_028C70_COLOR_4_4_4_4
:
893 case V_028C70_COLOR_10_11_11
:
894 case V_028C70_COLOR_11_11_10
:
895 case V_028C70_COLOR_8
:
896 case V_028C70_COLOR_8_8
:
897 case V_028C70_COLOR_8_8_8_8
:
898 case V_028C70_COLOR_10_10_10_2
:
899 case V_028C70_COLOR_2_10_10_10
:
900 if (ntype
== V_028C70_NUMBER_UINT
)
901 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
902 else if (ntype
== V_028C70_NUMBER_SINT
)
903 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
905 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
908 case V_028C70_COLOR_16
:
909 case V_028C70_COLOR_16_16
:
910 case V_028C70_COLOR_16_16_16_16
:
911 if (ntype
== V_028C70_NUMBER_UNORM
||
912 ntype
== V_028C70_NUMBER_SNORM
) {
913 /* UNORM16 and SNORM16 don't support blending */
914 if (ntype
== V_028C70_NUMBER_UNORM
)
915 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
917 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
919 /* Use 32 bits per channel for blending. */
920 if (format
== V_028C70_COLOR_16
) {
921 if (swap
== V_028C70_SWAP_STD
) { /* R */
922 blend
= V_028714_SPI_SHADER_32_R
;
923 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
924 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
925 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
928 } else if (format
== V_028C70_COLOR_16_16
) {
929 if (swap
== V_028C70_SWAP_STD
) { /* RG */
930 blend
= V_028714_SPI_SHADER_32_GR
;
931 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
932 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
933 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
936 } else /* 16_16_16_16 */
937 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
938 } else if (ntype
== V_028C70_NUMBER_UINT
)
939 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
940 else if (ntype
== V_028C70_NUMBER_SINT
)
941 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
942 else if (ntype
== V_028C70_NUMBER_FLOAT
)
943 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
948 case V_028C70_COLOR_32
:
949 if (swap
== V_028C70_SWAP_STD
) { /* R */
950 blend
= normal
= V_028714_SPI_SHADER_32_R
;
951 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
952 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
953 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
958 case V_028C70_COLOR_32_32
:
959 if (swap
== V_028C70_SWAP_STD
) { /* RG */
960 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
961 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
962 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
963 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
968 case V_028C70_COLOR_32_32_32_32
:
969 case V_028C70_COLOR_8_24
:
970 case V_028C70_COLOR_24_8
:
971 case V_028C70_COLOR_X24_8_32_FLOAT
:
972 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
976 unreachable("unhandled blend format");
979 if (blend_enable
&& blend_need_alpha
)
981 else if(blend_need_alpha
)
983 else if(blend_enable
)
989 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
991 unsigned i
, cb_shader_mask
= 0;
993 for (i
= 0; i
< 8; i
++) {
994 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
995 case V_028714_SPI_SHADER_ZERO
:
997 case V_028714_SPI_SHADER_32_R
:
998 cb_shader_mask
|= 0x1 << (i
* 4);
1000 case V_028714_SPI_SHADER_32_GR
:
1001 cb_shader_mask
|= 0x3 << (i
* 4);
1003 case V_028714_SPI_SHADER_32_AR
:
1004 cb_shader_mask
|= 0x9 << (i
* 4);
1006 case V_028714_SPI_SHADER_FP16_ABGR
:
1007 case V_028714_SPI_SHADER_UNORM16_ABGR
:
1008 case V_028714_SPI_SHADER_SNORM16_ABGR
:
1009 case V_028714_SPI_SHADER_UINT16_ABGR
:
1010 case V_028714_SPI_SHADER_SINT16_ABGR
:
1011 case V_028714_SPI_SHADER_32_ABGR
:
1012 cb_shader_mask
|= 0xf << (i
* 4);
1018 return cb_shader_mask
;
1022 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
1023 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1024 uint32_t blend_enable
,
1025 uint32_t blend_need_alpha
,
1026 bool single_cb_enable
,
1027 bool blend_mrt0_is_dual_src
)
1029 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1030 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1031 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
1032 unsigned col_format
= 0;
1034 for (unsigned i
= 0; i
< (single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
1037 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1038 cf
= V_028714_SPI_SHADER_ZERO
;
1040 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
1042 cf
= si_choose_spi_color_format(attachment
->format
,
1043 blend_enable
& (1 << i
),
1044 blend_need_alpha
& (1 << i
));
1047 col_format
|= cf
<< (4 * i
);
1050 blend
->cb_shader_mask
= si_get_cb_shader_mask(col_format
);
1052 if (blend_mrt0_is_dual_src
)
1053 col_format
|= (col_format
& 0xf) << 4;
1054 blend
->spi_shader_col_format
= col_format
;
1058 format_is_int8(VkFormat format
)
1060 const struct vk_format_description
*desc
= vk_format_description(format
);
1061 int channel
= vk_format_get_first_non_void_channel(format
);
1063 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
1064 desc
->channel
[channel
].size
== 8;
1068 format_is_int10(VkFormat format
)
1070 const struct vk_format_description
*desc
= vk_format_description(format
);
1072 if (desc
->nr_channels
!= 4)
1074 for (unsigned i
= 0; i
< 4; i
++) {
1075 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
1081 unsigned radv_format_meta_fs_key(VkFormat format
)
1083 unsigned col_format
= si_choose_spi_color_format(format
, false, false) - 1;
1084 bool is_int8
= format_is_int8(format
);
1085 bool is_int10
= format_is_int10(format
);
1087 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
1091 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1092 unsigned *is_int8
, unsigned *is_int10
)
1094 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1095 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1099 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1100 struct radv_render_pass_attachment
*attachment
;
1102 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
1105 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
1107 if (format_is_int8(attachment
->format
))
1109 if (format_is_int10(attachment
->format
))
1110 *is_int10
|= 1 << i
;
1115 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
1116 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1117 const struct radv_graphics_pipeline_create_info
*extra
)
1119 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
1120 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
1121 unsigned mode
= V_028808_CB_NORMAL
;
1122 uint32_t blend_enable
= 0, blend_need_alpha
= 0;
1123 bool blend_mrt0_is_dual_src
= false;
1125 bool single_cb_enable
= false;
1130 if (extra
&& extra
->custom_blend_mode
) {
1131 single_cb_enable
= true;
1132 mode
= extra
->custom_blend_mode
;
1134 blend
->cb_color_control
= 0;
1135 if (vkblend
->logicOpEnable
)
1136 blend
->cb_color_control
|= S_028808_ROP3(vkblend
->logicOp
| (vkblend
->logicOp
<< 4));
1138 blend
->cb_color_control
|= S_028808_ROP3(0xcc);
1140 blend
->db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1141 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1142 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1143 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1145 blend
->cb_target_mask
= 0;
1146 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
1147 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
1148 unsigned blend_cntl
= 0;
1149 VkBlendOp eqRGB
= att
->colorBlendOp
;
1150 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
1151 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
1152 VkBlendOp eqA
= att
->alphaBlendOp
;
1153 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
1154 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
1156 blend
->sx_mrt0_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
1158 if (!att
->colorWriteMask
)
1161 blend
->cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
1162 if (!att
->blendEnable
) {
1163 blend
->cb_blend_control
[i
] = blend_cntl
;
1167 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
1169 blend_mrt0_is_dual_src
= true;
1171 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
1172 srcRGB
= VK_BLEND_FACTOR_ONE
;
1173 dstRGB
= VK_BLEND_FACTOR_ONE
;
1175 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
1176 srcA
= VK_BLEND_FACTOR_ONE
;
1177 dstA
= VK_BLEND_FACTOR_ONE
;
1180 blend_cntl
|= S_028780_ENABLE(1);
1182 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
1183 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
1184 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
1185 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
1186 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
1187 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
1188 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
1189 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
1191 blend
->cb_blend_control
[i
] = blend_cntl
;
1193 blend_enable
|= 1 << i
;
1195 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
1196 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
1197 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
1198 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
1199 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
1200 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
1201 blend_need_alpha
|= 1 << i
;
1203 for (i
= vkblend
->attachmentCount
; i
< 8; i
++)
1204 blend
->cb_blend_control
[i
] = 0;
1206 if (blend
->cb_target_mask
)
1207 blend
->cb_color_control
|= S_028808_MODE(mode
);
1209 blend
->cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
1211 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
,
1212 blend_enable
, blend_need_alpha
, single_cb_enable
, blend_mrt0_is_dual_src
);
1215 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
1218 case VK_STENCIL_OP_KEEP
:
1219 return V_02842C_STENCIL_KEEP
;
1220 case VK_STENCIL_OP_ZERO
:
1221 return V_02842C_STENCIL_ZERO
;
1222 case VK_STENCIL_OP_REPLACE
:
1223 return V_02842C_STENCIL_REPLACE_TEST
;
1224 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
1225 return V_02842C_STENCIL_ADD_CLAMP
;
1226 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
1227 return V_02842C_STENCIL_SUB_CLAMP
;
1228 case VK_STENCIL_OP_INVERT
:
1229 return V_02842C_STENCIL_INVERT
;
1230 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
1231 return V_02842C_STENCIL_ADD_WRAP
;
1232 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
1233 return V_02842C_STENCIL_SUB_WRAP
;
1239 radv_pipeline_init_depth_stencil_state(struct radv_pipeline
*pipeline
,
1240 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1241 const struct radv_graphics_pipeline_create_info
*extra
)
1243 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
1244 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
1246 memset(ds
, 0, sizeof(*ds
));
1250 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1251 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1252 if (subpass
->depth_stencil_attachment
.attachment
== VK_ATTACHMENT_UNUSED
)
1255 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
.attachment
;
1256 bool has_depth_attachment
= vk_format_is_depth(attachment
->format
);
1257 bool has_stencil_attachment
= vk_format_is_stencil(attachment
->format
);
1259 if (has_depth_attachment
) {
1260 ds
->db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
1261 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
1262 S_028800_ZFUNC(vkds
->depthCompareOp
) |
1263 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
1266 if (has_stencil_attachment
&& vkds
->stencilTestEnable
) {
1267 ds
->db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1268 ds
->db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
1269 ds
->db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
1270 ds
->db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
1271 ds
->db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
1273 ds
->db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
1274 ds
->db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
1275 ds
->db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
1276 ds
->db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
1281 ds
->db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
1282 ds
->db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
1284 ds
->db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
1285 ds
->db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
1286 ds
->db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
1287 ds
->db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
1288 ds
->db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
1292 static uint32_t si_translate_fill(VkPolygonMode func
)
1295 case VK_POLYGON_MODE_FILL
:
1296 return V_028814_X_DRAW_TRIANGLES
;
1297 case VK_POLYGON_MODE_LINE
:
1298 return V_028814_X_DRAW_LINES
;
1299 case VK_POLYGON_MODE_POINT
:
1300 return V_028814_X_DRAW_POINTS
;
1303 return V_028814_X_DRAW_POINTS
;
1307 radv_pipeline_init_raster_state(struct radv_pipeline
*pipeline
,
1308 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1310 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
1311 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
1313 memset(raster
, 0, sizeof(*raster
));
1315 raster
->spi_interp_control
=
1316 S_0286D4_FLAT_SHADE_ENA(1) |
1317 S_0286D4_PNT_SPRITE_ENA(1) |
1318 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
1319 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
1320 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
1321 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
1322 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1325 raster
->pa_cl_clip_cntl
= S_028810_PS_UCP_MODE(3) |
1326 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1327 S_028810_ZCLIP_NEAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
1328 S_028810_ZCLIP_FAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
1329 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
1330 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1332 raster
->pa_su_vtx_cntl
=
1333 S_028BE4_PIX_CENTER(1) | // TODO verify
1334 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
1335 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
);
1337 raster
->pa_su_sc_mode_cntl
=
1338 S_028814_FACE(vkraster
->frontFace
) |
1339 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
1340 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
1341 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
1342 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
1343 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
1344 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
1345 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
1346 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0);
1351 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1352 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1354 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
1355 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
1356 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1357 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1358 int ps_iter_samples
= 1;
1359 uint32_t mask
= 0xffff;
1362 ms
->num_samples
= vkms
->rasterizationSamples
;
1364 ms
->num_samples
= 1;
1366 if (vkms
&& vkms
->sampleShadingEnable
) {
1367 ps_iter_samples
= ceil(vkms
->minSampleShading
* ms
->num_samples
);
1368 } else if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.force_persample
) {
1369 ps_iter_samples
= ms
->num_samples
;
1372 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1373 ms
->pa_sc_aa_config
= 0;
1374 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1375 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1376 ms
->pa_sc_mode_cntl_1
=
1377 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1378 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1380 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1381 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1382 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1383 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1384 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1385 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1386 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
);
1388 if (ms
->num_samples
> 1) {
1389 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1390 unsigned log_ps_iter_samples
= util_logbase2(util_next_power_of_two(ps_iter_samples
));
1391 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1392 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1393 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1394 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1395 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1396 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1397 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1398 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples
)) |
1399 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1400 ms
->pa_sc_mode_cntl_1
|= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1404 if (vkms
->alphaToCoverageEnable
)
1405 blend
->db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1407 if (vkms
->pSampleMask
)
1408 mask
= vkms
->pSampleMask
[0] & 0xffff;
1411 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1412 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1416 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1419 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1420 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1421 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1422 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1423 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1425 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1426 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1427 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1428 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1429 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1430 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1433 unreachable("unhandled primitive type");
1438 si_translate_prim(enum VkPrimitiveTopology topology
)
1441 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1442 return V_008958_DI_PT_POINTLIST
;
1443 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1444 return V_008958_DI_PT_LINELIST
;
1445 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1446 return V_008958_DI_PT_LINESTRIP
;
1447 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1448 return V_008958_DI_PT_TRILIST
;
1449 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1450 return V_008958_DI_PT_TRISTRIP
;
1451 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1452 return V_008958_DI_PT_TRIFAN
;
1453 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1454 return V_008958_DI_PT_LINELIST_ADJ
;
1455 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1456 return V_008958_DI_PT_LINESTRIP_ADJ
;
1457 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1458 return V_008958_DI_PT_TRILIST_ADJ
;
1459 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1460 return V_008958_DI_PT_TRISTRIP_ADJ
;
1461 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1462 return V_008958_DI_PT_PATCH
;
1470 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1473 case 0: /* GL_POINTS */
1474 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1475 case 1: /* GL_LINES */
1476 case 3: /* GL_LINE_STRIP */
1477 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1478 case 0x8E7A: /* GL_ISOLINES */
1479 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1481 case 4: /* GL_TRIANGLES */
1482 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1483 case 5: /* GL_TRIANGLE_STRIP */
1484 case 7: /* GL_QUADS */
1485 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1493 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1496 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1497 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1498 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1499 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1500 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1501 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1502 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1503 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1504 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1505 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1506 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1507 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1508 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1509 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1516 static unsigned si_map_swizzle(unsigned swizzle
)
1520 return V_008F0C_SQ_SEL_Y
;
1522 return V_008F0C_SQ_SEL_Z
;
1524 return V_008F0C_SQ_SEL_W
;
1526 return V_008F0C_SQ_SEL_0
;
1528 return V_008F0C_SQ_SEL_1
;
1529 default: /* VK_SWIZZLE_X */
1530 return V_008F0C_SQ_SEL_X
;
1535 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1536 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1538 radv_cmd_dirty_mask_t states
= RADV_CMD_DIRTY_DYNAMIC_ALL
;
1539 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1540 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1542 pipeline
->dynamic_state
= default_dynamic_state
;
1544 if (pCreateInfo
->pDynamicState
) {
1545 /* Remove all of the states that are marked as dynamic */
1546 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1547 for (uint32_t s
= 0; s
< count
; s
++)
1548 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1551 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1553 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1555 * pViewportState is [...] NULL if the pipeline
1556 * has rasterization disabled.
1558 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1559 assert(pCreateInfo
->pViewportState
);
1561 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1562 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1563 typed_memcpy(dynamic
->viewport
.viewports
,
1564 pCreateInfo
->pViewportState
->pViewports
,
1565 pCreateInfo
->pViewportState
->viewportCount
);
1568 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1569 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1570 typed_memcpy(dynamic
->scissor
.scissors
,
1571 pCreateInfo
->pViewportState
->pScissors
,
1572 pCreateInfo
->pViewportState
->scissorCount
);
1576 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1577 assert(pCreateInfo
->pRasterizationState
);
1578 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1581 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1582 assert(pCreateInfo
->pRasterizationState
);
1583 dynamic
->depth_bias
.bias
=
1584 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1585 dynamic
->depth_bias
.clamp
=
1586 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1587 dynamic
->depth_bias
.slope
=
1588 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1591 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1593 * pColorBlendState is [...] NULL if the pipeline has rasterization
1594 * disabled or if the subpass of the render pass the pipeline is
1595 * created against does not use any color attachments.
1597 bool uses_color_att
= false;
1598 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1599 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1600 uses_color_att
= true;
1605 if (uses_color_att
&& states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
1606 assert(pCreateInfo
->pColorBlendState
);
1607 typed_memcpy(dynamic
->blend_constants
,
1608 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1611 /* If there is no depthstencil attachment, then don't read
1612 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1613 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1614 * no need to override the depthstencil defaults in
1615 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1617 * Section 9.2 of the Vulkan 1.0.15 spec says:
1619 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1620 * disabled or if the subpass of the render pass the pipeline is created
1621 * against does not use a depth/stencil attachment.
1623 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1624 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1625 assert(pCreateInfo
->pDepthStencilState
);
1627 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1628 dynamic
->depth_bounds
.min
=
1629 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1630 dynamic
->depth_bounds
.max
=
1631 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1634 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1635 dynamic
->stencil_compare_mask
.front
=
1636 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1637 dynamic
->stencil_compare_mask
.back
=
1638 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1641 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1642 dynamic
->stencil_write_mask
.front
=
1643 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1644 dynamic
->stencil_write_mask
.back
=
1645 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1648 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1649 dynamic
->stencil_reference
.front
=
1650 pCreateInfo
->pDepthStencilState
->front
.reference
;
1651 dynamic
->stencil_reference
.back
=
1652 pCreateInfo
->pDepthStencilState
->back
.reference
;
1656 pipeline
->dynamic_state_mask
= states
;
1659 static union ac_shader_variant_key
1660 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo
*pCreateInfo
, bool as_es
, bool as_ls
, bool export_prim_id
)
1662 union ac_shader_variant_key key
;
1663 const VkPipelineVertexInputStateCreateInfo
*input_state
=
1664 pCreateInfo
->pVertexInputState
;
1666 memset(&key
, 0, sizeof(key
));
1667 key
.vs
.instance_rate_inputs
= 0;
1668 key
.vs
.as_es
= as_es
;
1669 key
.vs
.as_ls
= as_ls
;
1670 key
.vs
.export_prim_id
= export_prim_id
;
1672 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
1674 binding
= input_state
->pVertexAttributeDescriptions
[i
].binding
;
1675 if (input_state
->pVertexBindingDescriptions
[binding
].inputRate
)
1676 key
.vs
.instance_rate_inputs
|= 1u << input_state
->pVertexAttributeDescriptions
[i
].location
;
1682 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
)
1684 struct radv_device
*device
= pipeline
->device
;
1685 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1686 unsigned wave_size
= 64;
1687 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1688 unsigned gs_vertex_reuse
= 16 * num_se
; /* GS_VERTEX_REUSE register (per SE) */
1689 unsigned alignment
= 256 * num_se
;
1690 /* The maximum size is 63.999 MB per SE. */
1691 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1692 struct ac_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1693 struct ac_es_output_info
*es_info
= radv_pipeline_has_tess(pipeline
) ?
1694 &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.es_info
:
1695 &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.es_info
;
1697 /* Calculate the minimum size. */
1698 unsigned min_esgs_ring_size
= align(es_info
->esgs_itemsize
* gs_vertex_reuse
*
1699 wave_size
, alignment
);
1700 /* These are recommended sizes, not minimum sizes. */
1701 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1702 es_info
->esgs_itemsize
* gs_info
->gs
.vertices_in
;
1703 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1704 gs_info
->gs
.max_gsvs_emit_size
* 1; // no streams in VK (gs->max_gs_stream + 1);
1706 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1707 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1708 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1710 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1711 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1714 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1717 /* SPI barrier management bug:
1718 * Make sure we have at least 4k of LDS in use to avoid the bug.
1719 * It applies to workgroup sizes of more than one wavefront.
1721 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1722 device
->physical_device
->rad_info
.family
== CHIP_KABINI
||
1723 device
->physical_device
->rad_info
.family
== CHIP_MULLINS
)
1724 *lds_size
= MAX2(*lds_size
, 8);
1728 calculate_tess_state(struct radv_pipeline
*pipeline
,
1729 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1731 unsigned num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1732 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
1733 unsigned num_tcs_patch_outputs
;
1734 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
1735 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
1736 unsigned lds_size
, hardware_lds_size
;
1737 unsigned perpatch_output_offset
;
1738 unsigned num_patches
;
1739 struct radv_tessellation_state
*tess
= &pipeline
->graphics
.tess
;
1741 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1742 * are laid out in LDS. */
1743 num_tcs_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outputs_written
);
1745 num_tcs_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
); //tcs->outputs_written
1746 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1747 num_tcs_patch_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.patch_outputs_written
);
1749 /* Ensure that we only need one wave per SIMD so we don't need to check
1750 * resource usage. Also ensures that the number of tcs in and out
1751 * vertices per threadgroup are at most 256.
1753 input_vertex_size
= num_tcs_inputs
* 16;
1754 output_vertex_size
= num_tcs_outputs
* 16;
1756 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
1758 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
1759 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
1760 /* Ensure that we only need one wave per SIMD so we don't need to check
1761 * resource usage. Also ensures that the number of tcs in and out
1762 * vertices per threadgroup are at most 256.
1764 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
1766 /* Make sure that the data fits in LDS. This assumes the shaders only
1767 * use LDS for the inputs and outputs.
1769 hardware_lds_size
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
? 65536 : 32768;
1770 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
1772 /* Make sure the output data fits in the offchip buffer */
1773 num_patches
= MIN2(num_patches
,
1774 (pipeline
->device
->tess_offchip_block_dw_size
* 4) /
1777 /* Not necessary for correctness, but improves performance. The
1778 * specific value is taken from the proprietary driver.
1780 num_patches
= MIN2(num_patches
, 40);
1782 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1783 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== SI
) {
1784 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
1785 num_patches
= MIN2(num_patches
, one_wave
);
1788 output_patch0_offset
= input_patch_size
* num_patches
;
1789 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
1791 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
1793 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1794 assert(lds_size
<= 65536);
1795 lds_size
= align(lds_size
, 512) / 512;
1797 assert(lds_size
<= 32768);
1798 lds_size
= align(lds_size
, 256) / 256;
1800 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1802 tess
->lds_size
= lds_size
;
1804 tess
->tcs_in_layout
= (input_patch_size
/ 4) |
1805 ((input_vertex_size
/ 4) << 13);
1806 tess
->tcs_out_layout
= (output_patch_size
/ 4) |
1807 ((output_vertex_size
/ 4) << 13);
1808 tess
->tcs_out_offsets
= (output_patch0_offset
/ 16) |
1809 ((perpatch_output_offset
/ 16) << 16);
1810 tess
->offchip_layout
= (pervertex_output_patch_size
* num_patches
<< 16) |
1811 (num_tcs_output_cp
<< 9) | num_patches
;
1813 tess
->ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1814 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1815 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1816 tess
->num_patches
= num_patches
;
1817 tess
->num_tcs_input_cp
= num_tcs_input_cp
;
1819 struct radv_shader_variant
*tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1820 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1822 switch (tes
->info
.tes
.primitive_mode
) {
1824 type
= V_028B6C_TESS_TRIANGLE
;
1827 type
= V_028B6C_TESS_QUAD
;
1830 type
= V_028B6C_TESS_ISOLINE
;
1834 switch (tes
->info
.tes
.spacing
) {
1835 case TESS_SPACING_EQUAL
:
1836 partitioning
= V_028B6C_PART_INTEGER
;
1838 case TESS_SPACING_FRACTIONAL_ODD
:
1839 partitioning
= V_028B6C_PART_FRAC_ODD
;
1841 case TESS_SPACING_FRACTIONAL_EVEN
:
1842 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1848 if (tes
->info
.tes
.point_mode
)
1849 topology
= V_028B6C_OUTPUT_POINT
;
1850 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
1851 topology
= V_028B6C_OUTPUT_LINE
;
1852 else if (tes
->info
.tes
.ccw
)
1853 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
1855 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
1857 if (pipeline
->device
->has_distributed_tess
) {
1858 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
1859 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
1860 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
1862 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
1864 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
1866 tess
->tf_param
= S_028B6C_TYPE(type
) |
1867 S_028B6C_PARTITIONING(partitioning
) |
1868 S_028B6C_TOPOLOGY(topology
) |
1869 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
1872 static const struct radv_prim_vertex_count prim_size_table
[] = {
1873 [V_008958_DI_PT_NONE
] = {0, 0},
1874 [V_008958_DI_PT_POINTLIST
] = {1, 1},
1875 [V_008958_DI_PT_LINELIST
] = {2, 2},
1876 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
1877 [V_008958_DI_PT_TRILIST
] = {3, 3},
1878 [V_008958_DI_PT_TRIFAN
] = {3, 1},
1879 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
1880 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
1881 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
1882 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
1883 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
1884 [V_008958_DI_PT_RECTLIST
] = {3, 3},
1885 [V_008958_DI_PT_LINELOOP
] = {2, 1},
1886 [V_008958_DI_PT_POLYGON
] = {3, 1},
1887 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
1890 static uint32_t si_vgt_gs_mode(struct radv_shader_variant
*gs
)
1892 unsigned gs_max_vert_out
= gs
->info
.gs
.vertices_out
;
1895 if (gs_max_vert_out
<= 128) {
1896 cut_mode
= V_028A40_GS_CUT_128
;
1897 } else if (gs_max_vert_out
<= 256) {
1898 cut_mode
= V_028A40_GS_CUT_256
;
1899 } else if (gs_max_vert_out
<= 512) {
1900 cut_mode
= V_028A40_GS_CUT_512
;
1902 assert(gs_max_vert_out
<= 1024);
1903 cut_mode
= V_028A40_GS_CUT_1024
;
1906 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
1907 S_028A40_CUT_MODE(cut_mode
)|
1908 S_028A40_ES_WRITE_OPTIMIZE(1) |
1909 S_028A40_GS_WRITE_OPTIMIZE(1);
1912 static void calculate_vgt_gs_mode(struct radv_pipeline
*pipeline
)
1914 struct radv_shader_variant
*vs
;
1915 vs
= radv_pipeline_has_gs(pipeline
) ? pipeline
->gs_copy_shader
: (radv_pipeline_has_tess(pipeline
) ? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1917 struct ac_vs_output_info
*outinfo
= &vs
->info
.vs
.outinfo
;
1919 pipeline
->graphics
.vgt_primitiveid_en
= false;
1920 pipeline
->graphics
.vgt_gs_mode
= 0;
1922 if (radv_pipeline_has_gs(pipeline
)) {
1923 pipeline
->graphics
.vgt_gs_mode
= si_vgt_gs_mode(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
1924 } else if (outinfo
->export_prim_id
) {
1925 pipeline
->graphics
.vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
1926 pipeline
->graphics
.vgt_primitiveid_en
= true;
1930 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline
*pipeline
)
1932 struct radv_shader_variant
*vs
;
1933 vs
= radv_pipeline_has_gs(pipeline
) ? pipeline
->gs_copy_shader
: (radv_pipeline_has_tess(pipeline
) ? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1935 struct ac_vs_output_info
*outinfo
= &vs
->info
.vs
.outinfo
;
1937 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
1938 clip_dist_mask
= outinfo
->clip_dist_mask
;
1939 cull_dist_mask
= outinfo
->cull_dist_mask
;
1940 total_mask
= clip_dist_mask
| cull_dist_mask
;
1942 bool misc_vec_ena
= outinfo
->writes_pointsize
||
1943 outinfo
->writes_layer
||
1944 outinfo
->writes_viewport_index
;
1945 pipeline
->graphics
.pa_cl_vs_out_cntl
=
1946 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
1947 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
1948 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
1949 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
1950 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
1951 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
1952 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
1953 cull_dist_mask
<< 8 |
1958 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
)
1960 uint32_t ps_input_cntl
;
1961 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
1962 ps_input_cntl
= S_028644_OFFSET(offset
);
1964 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
1966 /* The input is a DEFAULT_VAL constant. */
1967 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
1968 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
1969 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
1970 ps_input_cntl
= S_028644_OFFSET(0x20) |
1971 S_028644_DEFAULT_VAL(offset
);
1973 return ps_input_cntl
;
1976 static void calculate_ps_inputs(struct radv_pipeline
*pipeline
)
1978 struct radv_shader_variant
*ps
, *vs
;
1979 struct ac_vs_output_info
*outinfo
;
1981 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1982 vs
= radv_pipeline_has_gs(pipeline
) ? pipeline
->gs_copy_shader
: (radv_pipeline_has_tess(pipeline
) ? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1984 outinfo
= &vs
->info
.vs
.outinfo
;
1986 unsigned ps_offset
= 0;
1988 if (ps
->info
.fs
.prim_id_input
) {
1989 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
1990 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
1991 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true);
1996 if (ps
->info
.fs
.layer_input
) {
1997 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
1998 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
1999 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true);
2004 if (ps
->info
.fs
.has_pcoord
) {
2006 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2007 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = val
;
2011 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.fs
.input_mask
; ++i
) {
2014 if (!(ps
->info
.fs
.input_mask
& (1u << i
)))
2017 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
2018 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
2019 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
2024 flat_shade
= !!(ps
->info
.fs
.flat_shaded_mask
& (1u << ps_offset
));
2026 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
);
2030 pipeline
->graphics
.ps_input_cntl_num
= ps_offset
;
2034 radv_pipeline_init(struct radv_pipeline
*pipeline
,
2035 struct radv_device
*device
,
2036 struct radv_pipeline_cache
*cache
,
2037 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2038 const struct radv_graphics_pipeline_create_info
*extra
,
2039 const VkAllocationCallbacks
*alloc
)
2041 struct radv_shader_module fs_m
= {0};
2045 alloc
= &device
->alloc
;
2047 pipeline
->device
= device
;
2048 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
2050 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
2051 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
2052 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2053 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
2054 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
2055 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
2056 modules
[stage
] = radv_shader_module_from_handle(pStages
[stage
]->module
);
2059 radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
2061 if (!modules
[MESA_SHADER_FRAGMENT
]) {
2063 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2064 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2065 fs_m
.nir
= fs_b
.shader
;
2066 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2069 if (modules
[MESA_SHADER_FRAGMENT
]) {
2070 union ac_shader_variant_key key
= {0};
2071 key
.fs
.col_format
= pipeline
->graphics
.blend
.spi_shader_col_format
;
2073 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< VI
)
2074 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.fs
.is_int8
, &key
.fs
.is_int10
);
2076 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[MESA_SHADER_FRAGMENT
];
2078 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2079 radv_pipeline_compile(pipeline
, cache
, modules
[MESA_SHADER_FRAGMENT
],
2080 stage
? stage
->pName
: "main",
2081 MESA_SHADER_FRAGMENT
,
2082 stage
? stage
->pSpecializationInfo
: NULL
,
2083 pipeline
->layout
, &key
);
2084 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT
);
2088 ralloc_free(fs_m
.nir
);
2090 if (modules
[MESA_SHADER_VERTEX
]) {
2093 bool export_prim_id
= false;
2094 if (modules
[MESA_SHADER_TESS_CTRL
])
2096 else if (modules
[MESA_SHADER_GEOMETRY
])
2098 else if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.fs
.prim_id_input
)
2099 export_prim_id
= true;
2100 union ac_shader_variant_key key
= radv_compute_vs_key(pCreateInfo
, as_es
, as_ls
, export_prim_id
);
2102 pipeline
->shaders
[MESA_SHADER_VERTEX
] =
2103 radv_pipeline_compile(pipeline
, cache
, modules
[MESA_SHADER_VERTEX
],
2104 pStages
[MESA_SHADER_VERTEX
]->pName
,
2106 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
,
2107 pipeline
->layout
, &key
);
2109 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX
);
2112 if (modules
[MESA_SHADER_GEOMETRY
]) {
2113 union ac_shader_variant_key key
= radv_compute_vs_key(pCreateInfo
, false, false, false);
2115 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] =
2116 radv_pipeline_compile(pipeline
, cache
, modules
[MESA_SHADER_GEOMETRY
],
2117 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
2118 MESA_SHADER_GEOMETRY
,
2119 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
,
2120 pipeline
->layout
, &key
);
2122 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY
);
2125 if (modules
[MESA_SHADER_TESS_EVAL
]) {
2126 assert(modules
[MESA_SHADER_TESS_CTRL
]);
2128 radv_tess_pipeline_compile(pipeline
,
2130 modules
[MESA_SHADER_TESS_CTRL
],
2131 modules
[MESA_SHADER_TESS_EVAL
],
2132 pStages
[MESA_SHADER_TESS_CTRL
]->pName
,
2133 pStages
[MESA_SHADER_TESS_EVAL
]->pName
,
2134 pStages
[MESA_SHADER_TESS_CTRL
]->pSpecializationInfo
,
2135 pStages
[MESA_SHADER_TESS_EVAL
]->pSpecializationInfo
,
2137 pCreateInfo
->pTessellationState
->patchControlPoints
);
2138 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL
) |
2139 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL
);
2142 radv_pipeline_init_depth_stencil_state(pipeline
, pCreateInfo
, extra
);
2143 radv_pipeline_init_raster_state(pipeline
, pCreateInfo
);
2144 radv_pipeline_init_multisample_state(pipeline
, pCreateInfo
);
2145 pipeline
->graphics
.prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
2146 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
2148 if (radv_pipeline_has_gs(pipeline
)) {
2149 pipeline
->graphics
.gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
2150 pipeline
->graphics
.can_use_guardband
= pipeline
->graphics
.gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2152 pipeline
->graphics
.gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
2154 if (extra
&& extra
->use_rectlist
) {
2155 pipeline
->graphics
.prim
= V_008958_DI_PT_RECTLIST
;
2156 pipeline
->graphics
.gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2157 pipeline
->graphics
.can_use_guardband
= true;
2159 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
2160 /* prim vertex count will need TESS changes */
2161 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[pipeline
->graphics
.prim
];
2163 /* Ensure that some export memory is always allocated, for two reasons:
2165 * 1) Correctness: The hardware ignores the EXEC mask if no export
2166 * memory is allocated, so KILL and alpha test do not work correctly
2168 * 2) Performance: Every shader needs at least a NULL export, even when
2169 * it writes no color/depth output. The NULL export instruction
2170 * stalls without this setting.
2172 * Don't add this to CB_SHADER_MASK.
2174 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
2175 if (!pipeline
->graphics
.blend
.spi_shader_col_format
) {
2176 if (!ps
->info
.fs
.writes_z
&&
2177 !ps
->info
.fs
.writes_stencil
&&
2178 !ps
->info
.fs
.writes_sample_mask
)
2179 pipeline
->graphics
.blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
2183 pipeline
->graphics
.db_shader_control
= 0;
2184 if (ps
->info
.fs
.early_fragment_test
|| !ps
->info
.fs
.writes_memory
)
2185 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
2187 z_order
= V_02880C_LATE_Z
;
2189 pipeline
->graphics
.db_shader_control
=
2190 S_02880C_Z_EXPORT_ENABLE(ps
->info
.fs
.writes_z
) |
2191 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.fs
.writes_stencil
) |
2192 S_02880C_KILL_ENABLE(!!ps
->info
.fs
.can_discard
) |
2193 S_02880C_MASK_EXPORT_ENABLE(ps
->info
.fs
.writes_sample_mask
) |
2194 S_02880C_Z_ORDER(z_order
) |
2195 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.fs
.early_fragment_test
) |
2196 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.fs
.writes_memory
) |
2197 S_02880C_EXEC_ON_NOOP(ps
->info
.fs
.writes_memory
);
2199 pipeline
->graphics
.shader_z_format
=
2200 ps
->info
.fs
.writes_sample_mask
? V_028710_SPI_SHADER_32_ABGR
:
2201 ps
->info
.fs
.writes_stencil
? V_028710_SPI_SHADER_32_GR
:
2202 ps
->info
.fs
.writes_z
? V_028710_SPI_SHADER_32_R
:
2203 V_028710_SPI_SHADER_ZERO
;
2205 calculate_vgt_gs_mode(pipeline
);
2206 calculate_pa_cl_vs_out_cntl(pipeline
);
2207 calculate_ps_inputs(pipeline
);
2209 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2210 if (pipeline
->shaders
[i
]) {
2211 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
2215 uint32_t stages
= 0;
2216 if (radv_pipeline_has_tess(pipeline
)) {
2217 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
2218 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2220 if (radv_pipeline_has_gs(pipeline
))
2221 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
2223 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2225 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
2227 } else if (radv_pipeline_has_gs(pipeline
))
2228 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
2230 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2232 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
2233 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2235 pipeline
->graphics
.vgt_shader_stages_en
= stages
;
2237 if (radv_pipeline_has_gs(pipeline
))
2238 calculate_gs_ring_sizes(pipeline
);
2240 if (radv_pipeline_has_tess(pipeline
)) {
2241 if (pipeline
->graphics
.prim
== V_008958_DI_PT_PATCH
) {
2242 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2243 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
2245 calculate_tess_state(pipeline
, pCreateInfo
);
2248 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
2249 pCreateInfo
->pVertexInputState
;
2250 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
2251 const VkVertexInputAttributeDescription
*desc
=
2252 &vi_info
->pVertexAttributeDescriptions
[i
];
2253 unsigned loc
= desc
->location
;
2254 const struct vk_format_description
*format_desc
;
2256 uint32_t num_format
, data_format
;
2257 format_desc
= vk_format_description(desc
->format
);
2258 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2260 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2261 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2263 pipeline
->va_rsrc_word3
[loc
] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc
->swizzle
[0])) |
2264 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc
->swizzle
[1])) |
2265 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc
->swizzle
[2])) |
2266 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc
->swizzle
[3])) |
2267 S_008F0C_NUM_FORMAT(num_format
) |
2268 S_008F0C_DATA_FORMAT(data_format
);
2269 pipeline
->va_format_size
[loc
] = format_desc
->block
.bits
/ 8;
2270 pipeline
->va_offset
[loc
] = desc
->offset
;
2271 pipeline
->va_binding
[loc
] = desc
->binding
;
2272 pipeline
->num_vertex_attribs
= MAX2(pipeline
->num_vertex_attribs
, loc
+ 1);
2275 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
2276 const VkVertexInputBindingDescription
*desc
=
2277 &vi_info
->pVertexBindingDescriptions
[i
];
2279 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
2282 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
2283 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
2284 if (loc
->sgpr_idx
!= -1) {
2285 pipeline
->graphics
.vtx_base_sgpr
= radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
2286 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
2287 if (pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.needs_draw_id
)
2288 pipeline
->graphics
.vtx_emit_num
= 3;
2290 pipeline
->graphics
.vtx_emit_num
= 2;
2292 if (device
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) {
2293 radv_dump_pipeline_stats(device
, pipeline
);
2296 result
= radv_pipeline_scratch_init(device
, pipeline
);
2301 radv_graphics_pipeline_create(
2303 VkPipelineCache _cache
,
2304 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2305 const struct radv_graphics_pipeline_create_info
*extra
,
2306 const VkAllocationCallbacks
*pAllocator
,
2307 VkPipeline
*pPipeline
)
2309 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2310 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
2311 struct radv_pipeline
*pipeline
;
2314 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
2315 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2316 if (pipeline
== NULL
)
2317 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2319 memset(pipeline
, 0, sizeof(*pipeline
));
2320 result
= radv_pipeline_init(pipeline
, device
, cache
,
2321 pCreateInfo
, extra
, pAllocator
);
2322 if (result
!= VK_SUCCESS
) {
2323 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
2327 *pPipeline
= radv_pipeline_to_handle(pipeline
);
2332 VkResult
radv_CreateGraphicsPipelines(
2334 VkPipelineCache pipelineCache
,
2336 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
2337 const VkAllocationCallbacks
* pAllocator
,
2338 VkPipeline
* pPipelines
)
2340 VkResult result
= VK_SUCCESS
;
2343 for (; i
< count
; i
++) {
2345 r
= radv_graphics_pipeline_create(_device
,
2348 NULL
, pAllocator
, &pPipelines
[i
]);
2349 if (r
!= VK_SUCCESS
) {
2351 pPipelines
[i
] = VK_NULL_HANDLE
;
2358 static VkResult
radv_compute_pipeline_create(
2360 VkPipelineCache _cache
,
2361 const VkComputePipelineCreateInfo
* pCreateInfo
,
2362 const VkAllocationCallbacks
* pAllocator
,
2363 VkPipeline
* pPipeline
)
2365 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2366 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
2367 RADV_FROM_HANDLE(radv_shader_module
, module
, pCreateInfo
->stage
.module
);
2368 struct radv_pipeline
*pipeline
;
2371 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
2372 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2373 if (pipeline
== NULL
)
2374 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2376 memset(pipeline
, 0, sizeof(*pipeline
));
2377 pipeline
->device
= device
;
2378 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
2380 pipeline
->shaders
[MESA_SHADER_COMPUTE
] =
2381 radv_pipeline_compile(pipeline
, cache
, module
,
2382 pCreateInfo
->stage
.pName
,
2383 MESA_SHADER_COMPUTE
,
2384 pCreateInfo
->stage
.pSpecializationInfo
,
2385 pipeline
->layout
, NULL
);
2388 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
2389 result
= radv_pipeline_scratch_init(device
, pipeline
);
2390 if (result
!= VK_SUCCESS
) {
2391 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
2395 *pPipeline
= radv_pipeline_to_handle(pipeline
);
2397 if (device
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) {
2398 radv_dump_pipeline_stats(device
, pipeline
);
2402 VkResult
radv_CreateComputePipelines(
2404 VkPipelineCache pipelineCache
,
2406 const VkComputePipelineCreateInfo
* pCreateInfos
,
2407 const VkAllocationCallbacks
* pAllocator
,
2408 VkPipeline
* pPipelines
)
2410 VkResult result
= VK_SUCCESS
;
2413 for (; i
< count
; i
++) {
2415 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
2417 pAllocator
, &pPipelines
[i
]);
2418 if (r
!= VK_SUCCESS
) {
2420 pPipelines
[i
] = VK_NULL_HANDLE
;
2427 void *radv_alloc_shader_memory(struct radv_device
*device
,
2428 struct radv_shader_variant
*shader
)
2430 mtx_lock(&device
->shader_slab_mutex
);
2431 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
2432 uint64_t offset
= 0;
2433 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
2434 if (s
->bo_offset
- offset
>= shader
->code_size
) {
2435 shader
->bo
= slab
->bo
;
2436 shader
->bo_offset
= offset
;
2437 list_addtail(&shader
->slab_list
, &s
->slab_list
);
2438 mtx_unlock(&device
->shader_slab_mutex
);
2439 return slab
->ptr
+ offset
;
2441 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
2443 if (slab
->size
- offset
>= shader
->code_size
) {
2444 shader
->bo
= slab
->bo
;
2445 shader
->bo_offset
= offset
;
2446 list_addtail(&shader
->slab_list
, &slab
->shaders
);
2447 mtx_unlock(&device
->shader_slab_mutex
);
2448 return slab
->ptr
+ offset
;
2452 mtx_unlock(&device
->shader_slab_mutex
);
2453 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
2455 slab
->size
= 256 * 1024;
2456 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
2457 RADEON_DOMAIN_VRAM
, 0);
2458 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
2459 list_inithead(&slab
->shaders
);
2461 mtx_lock(&device
->shader_slab_mutex
);
2462 list_add(&slab
->slabs
, &device
->shader_slabs
);
2464 shader
->bo
= slab
->bo
;
2465 shader
->bo_offset
= 0;
2466 list_add(&shader
->slab_list
, &slab
->shaders
);
2467 mtx_unlock(&device
->shader_slab_mutex
);
2471 void radv_destroy_shader_slabs(struct radv_device
*device
)
2473 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
2474 device
->ws
->buffer_destroy(slab
->bo
);
2477 mtx_destroy(&device
->shader_slab_mutex
);